TrafficLightsPlusPlus.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001ac 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 000022dc 080001b0 080001b0 000011b0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000018 0800248c 0800248c 0000348c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080024a4 080024a4 0000400c 2**0 CONTENTS, READONLY 4 .ARM 00000008 080024a4 080024a4 000034a4 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 080024ac 080024ac 0000400c 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 080024ac 080024ac 000034ac 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 080024b0 080024b0 000034b0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 0000000c 20000000 080024b4 00004000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .ccmram 00000000 10000000 10000000 0000400c 2**0 CONTENTS 10 .bss 00000128 2000000c 2000000c 0000400c 2**2 ALLOC 11 ._user_heap_stack 00000604 20000134 20000134 0000400c 2**0 ALLOC 12 .ARM.attributes 00000030 00000000 00000000 0000400c 2**0 CONTENTS, READONLY 13 .debug_info 0000c2b8 00000000 00000000 0000403c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_abbrev 00001fdb 00000000 00000000 000102f4 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00000c88 00000000 00000000 000122d0 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 0000099e 00000000 00000000 00012f58 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00024bc7 00000000 00000000 000138f6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0000d485 00000000 00000000 000384bd 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000df3ae 00000000 00000000 00045942 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00124cf0 2**0 CONTENTS, READONLY 21 .debug_frame 00003374 00000000 00000000 00124d34 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 00000055 00000000 00000000 001280a8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001b0 <__do_global_dtors_aux>: 80001b0: b510 push {r4, lr} 80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>) 80001b4: 7823 ldrb r3, [r4, #0] 80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16> 80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>) 80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12> 80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>) 80001be: f3af 8000 nop.w 80001c2: 2301 movs r3, #1 80001c4: 7023 strb r3, [r4, #0] 80001c6: bd10 pop {r4, pc} 80001c8: 2000000c .word 0x2000000c 80001cc: 00000000 .word 0x00000000 80001d0: 08002474 .word 0x08002474 080001d4 : 80001d4: b508 push {r3, lr} 80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 ) 80001d8: b11b cbz r3, 80001e2 80001da: 4903 ldr r1, [pc, #12] @ (80001e8 ) 80001dc: 4803 ldr r0, [pc, #12] @ (80001ec ) 80001de: f3af 8000 nop.w 80001e2: bd08 pop {r3, pc} 80001e4: 00000000 .word 0x00000000 80001e8: 20000010 .word 0x20000010 80001ec: 08002474 .word 0x08002474 080001f0 <__aeabi_uldivmod>: 80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18> 80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18> 80001f4: 2900 cmp r1, #0 80001f6: bf08 it eq 80001f8: 2800 cmpeq r0, #0 80001fa: bf1c itt ne 80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000204: f000 b988 b.w 8000518 <__aeabi_idiv0> 8000208: f1ad 0c08 sub.w ip, sp, #8 800020c: e96d ce04 strd ip, lr, [sp, #-16]! 8000210: f000 f806 bl 8000220 <__udivmoddi4> 8000214: f8dd e004 ldr.w lr, [sp, #4] 8000218: e9dd 2302 ldrd r2, r3, [sp, #8] 800021c: b004 add sp, #16 800021e: 4770 bx lr 08000220 <__udivmoddi4>: 8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000224: 9d08 ldr r5, [sp, #32] 8000226: 468e mov lr, r1 8000228: 4604 mov r4, r0 800022a: 4688 mov r8, r1 800022c: 2b00 cmp r3, #0 800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6> 8000230: 428a cmp r2, r1 8000232: 4617 mov r7, r2 8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc> 8000236: fab2 f682 clz r6, r2 800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30> 800023c: f1c6 0320 rsb r3, r6, #32 8000240: fa01 f806 lsl.w r8, r1, r6 8000244: fa20 f303 lsr.w r3, r0, r3 8000248: 40b7 lsls r7, r6 800024a: ea43 0808 orr.w r8, r3, r8 800024e: 40b4 lsls r4, r6 8000250: ea4f 4e17 mov.w lr, r7, lsr #16 8000254: fa1f fc87 uxth.w ip, r7 8000258: fbb8 f1fe udiv r1, r8, lr 800025c: 0c23 lsrs r3, r4, #16 800025e: fb0e 8811 mls r8, lr, r1, r8 8000262: ea43 4308 orr.w r3, r3, r8, lsl #16 8000266: fb01 f20c mul.w r2, r1, ip 800026a: 429a cmp r2, r3 800026c: d909 bls.n 8000282 <__udivmoddi4+0x62> 800026e: 18fb adds r3, r7, r3 8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c> 8000278: 429a cmp r2, r3 800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c> 800027e: 3902 subs r1, #2 8000280: 443b add r3, r7 8000282: 1a9a subs r2, r3, r2 8000284: b2a3 uxth r3, r4 8000286: fbb2 f0fe udiv r0, r2, lr 800028a: fb0e 2210 mls r2, lr, r0, r2 800028e: ea43 4302 orr.w r3, r3, r2, lsl #16 8000292: fb00 fc0c mul.w ip, r0, ip 8000296: 459c cmp ip, r3 8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e> 800029a: 18fb adds r3, r7, r3 800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230> 80002a4: 459c cmp ip, r3 80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230> 80002aa: 443b add r3, r7 80002ac: 3802 subs r0, #2 80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16 80002b2: eba3 030c sub.w r3, r3, ip 80002b6: 2100 movs r1, #0 80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2> 80002ba: 40f3 lsrs r3, r6 80002bc: 2200 movs r2, #0 80002be: e9c5 3200 strd r3, r2, [r5] 80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002c6: 428b cmp r3, r1 80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6> 80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0> 80002cc: e9c5 0100 strd r0, r1, [r5] 80002d0: 2100 movs r1, #0 80002d2: 4608 mov r0, r1 80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2> 80002d6: fab3 f183 clz r1, r3 80002da: 2900 cmp r1, #0 80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c> 80002de: 4573 cmp r3, lr 80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8> 80002e2: 4282 cmp r2, r0 80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2> 80002e8: 1a84 subs r4, r0, r2 80002ea: eb6e 0203 sbc.w r2, lr, r3 80002ee: 2001 movs r0, #1 80002f0: 4690 mov r8, r2 80002f2: 2d00 cmp r5, #0 80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2> 80002f6: e9c5 4800 strd r4, r8, [r5] 80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2> 80002fc: 2a00 cmp r2, #0 80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202> 8000302: fab2 f682 clz r6, r2 8000306: 2e00 cmp r6, #0 8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234> 800030c: 1a8a subs r2, r1, r2 800030e: 0c03 lsrs r3, r0, #16 8000310: ea4f 4e17 mov.w lr, r7, lsr #16 8000314: b280 uxth r0, r0 8000316: b2bc uxth r4, r7 8000318: 2101 movs r1, #1 800031a: fbb2 fcfe udiv ip, r2, lr 800031e: fb0e 221c mls r2, lr, ip, r2 8000322: ea43 4302 orr.w r3, r3, r2, lsl #16 8000326: fb04 f20c mul.w r2, r4, ip 800032a: 429a cmp r2, r3 800032c: d907 bls.n 800033e <__udivmoddi4+0x11e> 800032e: 18fb adds r3, r7, r3 8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c> 8000336: 429a cmp r2, r3 8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc> 800033c: 46c4 mov ip, r8 800033e: 1a9b subs r3, r3, r2 8000340: fbb3 f2fe udiv r2, r3, lr 8000344: fb0e 3312 mls r3, lr, r2, r3 8000348: ea40 4303 orr.w r3, r0, r3, lsl #16 800034c: fb02 f404 mul.w r4, r2, r4 8000350: 429c cmp r4, r3 8000352: d907 bls.n 8000364 <__udivmoddi4+0x144> 8000354: 18fb adds r3, r7, r3 8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142> 800035c: 429c cmp r4, r3 800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6> 8000362: 4602 mov r2, r0 8000364: 1b1b subs r3, r3, r4 8000366: ea42 400c orr.w r0, r2, ip, lsl #16 800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98> 800036c: f1c1 0620 rsb r6, r1, #32 8000370: 408b lsls r3, r1 8000372: fa22 f706 lsr.w r7, r2, r6 8000376: 431f orrs r7, r3 8000378: fa0e f401 lsl.w r4, lr, r1 800037c: fa20 f306 lsr.w r3, r0, r6 8000380: fa2e fe06 lsr.w lr, lr, r6 8000384: ea4f 4917 mov.w r9, r7, lsr #16 8000388: 4323 orrs r3, r4 800038a: fa00 f801 lsl.w r8, r0, r1 800038e: fa1f fc87 uxth.w ip, r7 8000392: fbbe f0f9 udiv r0, lr, r9 8000396: 0c1c lsrs r4, r3, #16 8000398: fb09 ee10 mls lr, r9, r0, lr 800039c: ea44 440e orr.w r4, r4, lr, lsl #16 80003a0: fb00 fe0c mul.w lr, r0, ip 80003a4: 45a6 cmp lr, r4 80003a6: fa02 f201 lsl.w r2, r2, r1 80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0> 80003ac: 193c adds r4, r7, r4 80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce> 80003b6: 45a6 cmp lr, r4 80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce> 80003bc: 3802 subs r0, #2 80003be: 443c add r4, r7 80003c0: eba4 040e sub.w r4, r4, lr 80003c4: fa1f fe83 uxth.w lr, r3 80003c8: fbb4 f3f9 udiv r3, r4, r9 80003cc: fb09 4413 mls r4, r9, r3, r4 80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003d4: fb03 fc0c mul.w ip, r3, ip 80003d8: 45a4 cmp ip, r4 80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce> 80003dc: 193c adds r4, r7, r4 80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca> 80003e6: 45a4 cmp ip, r4 80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca> 80003ea: 3b02 subs r3, #2 80003ec: 443c add r4, r7 80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16 80003f2: eba4 040c sub.w r4, r4, ip 80003f6: fba0 ec02 umull lr, ip, r0, r2 80003fa: 4564 cmp r4, ip 80003fc: 4673 mov r3, lr 80003fe: 46e1 mov r9, ip 8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8> 8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4> 8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe> 8000406: ebb8 0203 subs.w r2, r8, r3 800040a: eb64 0409 sbc.w r4, r4, r9 800040e: fa04 f606 lsl.w r6, r4, r6 8000412: fa22 f301 lsr.w r3, r2, r1 8000416: 431e orrs r6, r3 8000418: 40cc lsrs r4, r1 800041a: e9c5 6400 strd r6, r4, [r5] 800041e: 2100 movs r1, #0 8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2> 8000422: fbb1 fcf2 udiv ip, r1, r2 8000426: 0c01 lsrs r1, r0, #16 8000428: ea41 410e orr.w r1, r1, lr, lsl #16 800042c: b280 uxth r0, r0 800042e: ea40 4201 orr.w r2, r0, r1, lsl #16 8000432: 463b mov r3, r7 8000434: 4638 mov r0, r7 8000436: 463c mov r4, r7 8000438: 46b8 mov r8, r7 800043a: 46be mov lr, r7 800043c: 2620 movs r6, #32 800043e: fbb1 f1f7 udiv r1, r1, r7 8000442: eba2 0208 sub.w r2, r2, r8 8000446: ea41 410c orr.w r1, r1, ip, lsl #16 800044a: e766 b.n 800031a <__udivmoddi4+0xfa> 800044c: 4601 mov r1, r0 800044e: e718 b.n 8000282 <__udivmoddi4+0x62> 8000450: 4610 mov r0, r2 8000452: e72c b.n 80002ae <__udivmoddi4+0x8e> 8000454: f1c6 0220 rsb r2, r6, #32 8000458: fa2e f302 lsr.w r3, lr, r2 800045c: 40b7 lsls r7, r6 800045e: 40b1 lsls r1, r6 8000460: fa20 f202 lsr.w r2, r0, r2 8000464: ea4f 4e17 mov.w lr, r7, lsr #16 8000468: 430a orrs r2, r1 800046a: fbb3 f8fe udiv r8, r3, lr 800046e: b2bc uxth r4, r7 8000470: fb0e 3318 mls r3, lr, r8, r3 8000474: 0c11 lsrs r1, r2, #16 8000476: ea41 4103 orr.w r1, r1, r3, lsl #16 800047a: fb08 f904 mul.w r9, r8, r4 800047e: 40b0 lsls r0, r6 8000480: 4589 cmp r9, r1 8000482: ea4f 4310 mov.w r3, r0, lsr #16 8000486: b280 uxth r0, r0 8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8> 800048a: 1879 adds r1, r7, r1 800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276> 8000492: 4589 cmp r9, r1 8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6> 8000496: eba1 0109 sub.w r1, r1, r9 800049a: fbb1 f9fe udiv r9, r1, lr 800049e: fb09 f804 mul.w r8, r9, r4 80004a2: fb0e 1119 mls r1, lr, r9, r1 80004a6: b292 uxth r2, r2 80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16 80004ac: 4542 cmp r2, r8 80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4> 80004b0: 18ba adds r2, r7, r2 80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222> 80004b8: 4542 cmp r2, r8 80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222> 80004bc: f1a9 0102 sub.w r1, r9, #2 80004c0: 443a add r2, r7 80004c2: e7be b.n 8000442 <__udivmoddi4+0x222> 80004c4: 45f0 cmp r8, lr 80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4> 80004c8: ebbe 0302 subs.w r3, lr, r2 80004cc: eb6c 0c07 sbc.w ip, ip, r7 80004d0: 3801 subs r0, #1 80004d2: 46e1 mov r9, ip 80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4> 80004d6: eba7 0909 sub.w r9, r7, r9 80004da: 4449 add r1, r9 80004dc: f1a8 0c02 sub.w ip, r8, #2 80004e0: fbb1 f9fe udiv r9, r1, lr 80004e4: fb09 f804 mul.w r8, r9, r4 80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282> 80004ea: 4673 mov r3, lr 80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce> 80004ee: 4650 mov r0, sl 80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0> 80004f2: 4608 mov r0, r1 80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2> 80004f6: 443b add r3, r7 80004f8: 3a02 subs r2, #2 80004fa: e733 b.n 8000364 <__udivmoddi4+0x144> 80004fc: f1ac 0c02 sub.w ip, ip, #2 8000500: 443b add r3, r7 8000502: e71c b.n 800033e <__udivmoddi4+0x11e> 8000504: 4649 mov r1, r9 8000506: e79c b.n 8000442 <__udivmoddi4+0x222> 8000508: eba1 0109 sub.w r1, r1, r9 800050c: 46c4 mov ip, r8 800050e: fbb1 f9fe udiv r9, r1, lr 8000512: fb09 f804 mul.w r8, r9, r4 8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282> 08000518 <__aeabi_idiv0>: 8000518: 4770 bx lr 800051a: bf00 nop 0800051c : } /* USER CODE END 2 */ /* USER CODE BEGIN 4 */ __weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 800051c: b480 push {r7} 800051e: b083 sub sp, #12 8000520: af00 add r7, sp, #0 8000522: 6078 str r0, [r7, #4] 8000524: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 8000526: bf00 nop 8000528: 370c adds r7, #12 800052a: 46bd mov sp, r7 800052c: f85d 7b04 ldr.w r7, [sp], #4 8000530: 4770 bx lr ... 08000534 <_Z16SetTrafficLights12TrafficState>: * @retval int */ void SetTrafficLights(TrafficState s) { 8000534: b580 push {r7, lr} 8000536: b082 sub sp, #8 8000538: af00 add r7, sp, #0 800053a: 6078 str r0, [r7, #4] // reset all HAL_GPIO_WritePin(GPIOD, Green_Pin|Yellow_Pin, GPIO_PIN_RESET); 800053c: 2200 movs r2, #0 800053e: 21a0 movs r1, #160 @ 0xa0 8000540: 4815 ldr r0, [pc, #84] @ (8000598 <_Z16SetTrafficLights12TrafficState+0x64>) 8000542: f000 fdcb bl 80010dc HAL_GPIO_WritePin(GPIOD, Red_Pin, GPIO_PIN_SET); 8000546: 2201 movs r2, #1 8000548: 2108 movs r1, #8 800054a: 4813 ldr r0, [pc, #76] @ (8000598 <_Z16SetTrafficLights12TrafficState+0x64>) 800054c: f000 fdc6 bl 80010dc switch (s) 8000550: 687b ldr r3, [r7, #4] 8000552: 2b02 cmp r3, #2 8000554: d015 beq.n 8000582 <_Z16SetTrafficLights12TrafficState+0x4e> 8000556: 687b ldr r3, [r7, #4] 8000558: 2b02 cmp r3, #2 800055a: dc18 bgt.n 800058e <_Z16SetTrafficLights12TrafficState+0x5a> 800055c: 687b ldr r3, [r7, #4] 800055e: 2b00 cmp r3, #0 8000560: d003 beq.n 800056a <_Z16SetTrafficLights12TrafficState+0x36> 8000562: 687b ldr r3, [r7, #4] 8000564: 2b01 cmp r3, #1 8000566: d006 beq.n 8000576 <_Z16SetTrafficLights12TrafficState+0x42> break; case TrafficState::RED: HAL_GPIO_WritePin(GPIOD, Red_Pin, GPIO_PIN_SET); break; } } 8000568: e011 b.n 800058e <_Z16SetTrafficLights12TrafficState+0x5a> HAL_GPIO_WritePin(GPIOD, Green_Pin, GPIO_PIN_SET); 800056a: 2201 movs r2, #1 800056c: 2180 movs r1, #128 @ 0x80 800056e: 480a ldr r0, [pc, #40] @ (8000598 <_Z16SetTrafficLights12TrafficState+0x64>) 8000570: f000 fdb4 bl 80010dc break; 8000574: e00b b.n 800058e <_Z16SetTrafficLights12TrafficState+0x5a> HAL_GPIO_WritePin(GPIOD, Yellow_Pin, GPIO_PIN_SET); 8000576: 2201 movs r2, #1 8000578: 2120 movs r1, #32 800057a: 4807 ldr r0, [pc, #28] @ (8000598 <_Z16SetTrafficLights12TrafficState+0x64>) 800057c: f000 fdae bl 80010dc break; 8000580: e005 b.n 800058e <_Z16SetTrafficLights12TrafficState+0x5a> HAL_GPIO_WritePin(GPIOD, Red_Pin, GPIO_PIN_SET); 8000582: 2201 movs r2, #1 8000584: 2108 movs r1, #8 8000586: 4804 ldr r0, [pc, #16] @ (8000598 <_Z16SetTrafficLights12TrafficState+0x64>) 8000588: f000 fda8 bl 80010dc break; 800058c: bf00 nop } 800058e: bf00 nop 8000590: 3708 adds r7, #8 8000592: 46bd mov sp, r7 8000594: bd80 pop {r7, pc} 8000596: bf00 nop 8000598: 40020c00 .word 0x40020c00 0800059c
: int main(void) { 800059c: b580 push {r7, lr} 800059e: b082 sub sp, #8 80005a0: af00 add r7, sp, #0 HAL_Init(); 80005a2: f000 fadf bl 8000b64 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80005a6: f000 f8b1 bl 800070c MX_GPIO_Init(); 80005aa: f000 f925 bl 80007f8 stateStartTime = HAL_GetTick(); 80005ae: f000 fafb bl 8000ba8 80005b2: 4603 mov r3, r0 80005b4: 4a4f ldr r2, [pc, #316] @ (80006f4 ) 80005b6: 6013 str r3, [r2, #0] SetTrafficLights(currentState); 80005b8: 4b4f ldr r3, [pc, #316] @ (80006f8 ) 80005ba: 681b ldr r3, [r3, #0] 80005bc: 4618 mov r0, r3 80005be: f7ff ffb9 bl 8000534 <_Z16SetTrafficLights12TrafficState> while (1) { /* USER CODE END WHILE */ uint32_t now = HAL_GetTick(); 80005c2: f000 faf1 bl 8000ba8 80005c6: 6078 str r0, [r7, #4] uint32_t elapsed = now - stateStartTime; 80005c8: 4b4a ldr r3, [pc, #296] @ (80006f4 ) 80005ca: 681b ldr r3, [r3, #0] 80005cc: 687a ldr r2, [r7, #4] 80005ce: 1ad3 subs r3, r2, r3 80005d0: 603b str r3, [r7, #0] switch(currentState) 80005d2: 4b49 ldr r3, [pc, #292] @ (80006f8 ) 80005d4: 681b ldr r3, [r3, #0] 80005d6: 2b02 cmp r3, #2 80005d8: d03d beq.n 8000656 80005da: 2b02 cmp r3, #2 80005dc: dcf1 bgt.n 80005c2 80005de: 2b00 cmp r3, #0 80005e0: d002 beq.n 80005e8 80005e2: 2b01 cmp r3, #1 80005e4: d018 beq.n 8000618 80005e6: e083 b.n 80006f0 { case TrafficState::GREEN: // Record if the button was pressed during this green cycle if (buttonPressedThisCycle) 80005e8: 4b44 ldr r3, [pc, #272] @ (80006fc ) 80005ea: 781b ldrb r3, [r3, #0] 80005ec: 2b00 cmp r3, #0 80005ee: d002 beq.n 80005f6 { pedestrianThisCycle = true; 80005f0: 4b43 ldr r3, [pc, #268] @ (8000700 ) 80005f2: 2201 movs r2, #1 80005f4: 701a strb r2, [r3, #0] // else // { // pedestrianNextCycle = false; // SetTrafficLights(currentState); // } if (elapsed >= DURATION_GREEN) 80005f6: 683b ldr r3, [r7, #0] 80005f8: f241 3287 movw r2, #4999 @ 0x1387 80005fc: 4293 cmp r3, r2 80005fe: d972 bls.n 80006e6 { currentState = TrafficState::YELLOW; 8000600: 4b3d ldr r3, [pc, #244] @ (80006f8 ) 8000602: 2201 movs r2, #1 8000604: 601a str r2, [r3, #0] stateStartTime = now; 8000606: 4a3b ldr r2, [pc, #236] @ (80006f4 ) 8000608: 687b ldr r3, [r7, #4] 800060a: 6013 str r3, [r2, #0] SetTrafficLights(currentState); 800060c: 4b3a ldr r3, [pc, #232] @ (80006f8 ) 800060e: 681b ldr r3, [r3, #0] 8000610: 4618 mov r0, r3 8000612: f7ff ff8f bl 8000534 <_Z16SetTrafficLights12TrafficState> } break; 8000616: e066 b.n 80006e6 case TrafficState::YELLOW: // Record if button pressed during yellow if (buttonPressedThisCycle || pedestrianNextCycle) 8000618: 4b38 ldr r3, [pc, #224] @ (80006fc ) 800061a: 781b ldrb r3, [r3, #0] 800061c: 2b00 cmp r3, #0 800061e: d103 bne.n 8000628 8000620: 4b38 ldr r3, [pc, #224] @ (8000704 ) 8000622: 781b ldrb r3, [r3, #0] 8000624: 2b00 cmp r3, #0 8000626: d002 beq.n 800062e { pedestrianThisCycle = true; 8000628: 4b35 ldr r3, [pc, #212] @ (8000700 ) 800062a: 2201 movs r2, #1 800062c: 701a strb r2, [r3, #0] } if (elapsed >= DURATION_YELLOW) 800062e: 683b ldr r3, [r7, #0] 8000630: f640 32b7 movw r2, #2999 @ 0xbb7 8000634: 4293 cmp r3, r2 8000636: d958 bls.n 80006ea { currentState = TrafficState::RED; 8000638: 4b2f ldr r3, [pc, #188] @ (80006f8 ) 800063a: 2202 movs r2, #2 800063c: 601a str r2, [r3, #0] stateStartTime = now; 800063e: 4a2d ldr r2, [pc, #180] @ (80006f4 ) 8000640: 687b ldr r3, [r7, #4] 8000642: 6013 str r3, [r2, #0] SetTrafficLights(currentState); 8000644: 4b2c ldr r3, [pc, #176] @ (80006f8 ) 8000646: 681b ldr r3, [r3, #0] 8000648: 4618 mov r0, r3 800064a: f7ff ff73 bl 8000534 <_Z16SetTrafficLights12TrafficState> pedestrianNextCycle = false; 800064e: 4b2d ldr r3, [pc, #180] @ (8000704 ) 8000650: 2200 movs r2, #0 8000652: 701a strb r2, [r3, #0] // If Ped Button was pressed during GREEN or YELLOW, we need to enable WHITE this cycle } break; 8000654: e049 b.n 80006ea case TrafficState::RED: if (buttonPressedThisCycle) 8000656: 4b29 ldr r3, [pc, #164] @ (80006fc ) 8000658: 781b ldrb r3, [r3, #0] 800065a: 2b00 cmp r3, #0 800065c: d002 beq.n 8000664 { pedestrianNextCycle = true; 800065e: 4b29 ldr r3, [pc, #164] @ (8000704 ) 8000660: 2201 movs r2, #1 8000662: 701a strb r2, [r3, #0] } if (pedestrianThisCycle) 8000664: 4b26 ldr r3, [pc, #152] @ (8000700 ) 8000666: 781b ldrb r3, [r3, #0] 8000668: 2b00 cmp r3, #0 800066a: d023 beq.n 80006b4 { HAL_GPIO_WritePin(GPIOD,White_Pin,GPIO_PIN_SET); // turn on Pedestrian LED 800066c: 2201 movs r2, #1 800066e: 2102 movs r1, #2 8000670: 4825 ldr r0, [pc, #148] @ (8000708 ) 8000672: f000 fd33 bl 80010dc if (elapsed >= DURATION_RED_PED) 8000676: 683b ldr r3, [r7, #0] 8000678: f641 3257 movw r2, #6999 @ 0x1b57 800067c: 4293 cmp r3, r2 800067e: d936 bls.n 80006ee { HAL_GPIO_WritePin(GPIOD,White_Pin,GPIO_PIN_RESET); 8000680: 2200 movs r2, #0 8000682: 2102 movs r1, #2 8000684: 4820 ldr r0, [pc, #128] @ (8000708 ) 8000686: f000 fd29 bl 80010dc pedestrianThisCycle = false; 800068a: 4b1d ldr r3, [pc, #116] @ (8000700 ) 800068c: 2200 movs r2, #0 800068e: 701a strb r2, [r3, #0] pedestrianNextCycle = false; 8000690: 4b1c ldr r3, [pc, #112] @ (8000704 ) 8000692: 2200 movs r2, #0 8000694: 701a strb r2, [r3, #0] currentState = TrafficState::GREEN; 8000696: 4b18 ldr r3, [pc, #96] @ (80006f8 ) 8000698: 2200 movs r2, #0 800069a: 601a str r2, [r3, #0] stateStartTime = now; 800069c: 4a15 ldr r2, [pc, #84] @ (80006f4 ) 800069e: 687b ldr r3, [r7, #4] 80006a0: 6013 str r3, [r2, #0] SetTrafficLights(currentState); 80006a2: 4b15 ldr r3, [pc, #84] @ (80006f8 ) 80006a4: 681b ldr r3, [r3, #0] 80006a6: 4618 mov r0, r3 80006a8: f7ff ff44 bl 8000534 <_Z16SetTrafficLights12TrafficState> buttonPressedThisCycle = false; // reset button flag on transition 80006ac: 4b13 ldr r3, [pc, #76] @ (80006fc ) 80006ae: 2200 movs r2, #0 80006b0: 701a strb r2, [r3, #0] stateStartTime = now; SetTrafficLights(currentState); buttonPressedThisCycle = false; // reset button flag on transition } } break; 80006b2: e01c b.n 80006ee HAL_GPIO_WritePin(GPIOD,White_Pin,GPIO_PIN_RESET); 80006b4: 2200 movs r2, #0 80006b6: 2102 movs r1, #2 80006b8: 4813 ldr r0, [pc, #76] @ (8000708 ) 80006ba: f000 fd0f bl 80010dc if(elapsed >= DURATION_RED_NOPED) 80006be: 683b ldr r3, [r7, #0] 80006c0: f241 3287 movw r2, #4999 @ 0x1387 80006c4: 4293 cmp r3, r2 80006c6: d912 bls.n 80006ee currentState = TrafficState::GREEN; 80006c8: 4b0b ldr r3, [pc, #44] @ (80006f8 ) 80006ca: 2200 movs r2, #0 80006cc: 601a str r2, [r3, #0] stateStartTime = now; 80006ce: 4a09 ldr r2, [pc, #36] @ (80006f4 ) 80006d0: 687b ldr r3, [r7, #4] 80006d2: 6013 str r3, [r2, #0] SetTrafficLights(currentState); 80006d4: 4b08 ldr r3, [pc, #32] @ (80006f8 ) 80006d6: 681b ldr r3, [r3, #0] 80006d8: 4618 mov r0, r3 80006da: f7ff ff2b bl 8000534 <_Z16SetTrafficLights12TrafficState> buttonPressedThisCycle = false; // reset button flag on transition 80006de: 4b07 ldr r3, [pc, #28] @ (80006fc ) 80006e0: 2200 movs r2, #0 80006e2: 701a strb r2, [r3, #0] break; 80006e4: e003 b.n 80006ee break; 80006e6: bf00 nop 80006e8: e76b b.n 80005c2 break; 80006ea: bf00 nop 80006ec: e769 b.n 80005c2 break; 80006ee: bf00 nop }// switch /* USER CODE BEGIN 3 */ }// while 80006f0: e767 b.n 80005c2 80006f2: bf00 nop 80006f4: 20000028 .word 0x20000028 80006f8: 20000000 .word 0x20000000 80006fc: 2000002c .word 0x2000002c 8000700: 2000002e .word 0x2000002e 8000704: 2000002d .word 0x2000002d 8000708: 40020c00 .word 0x40020c00 0800070c : void SystemClock_Config(void) { 800070c: b580 push {r7, lr} 800070e: b094 sub sp, #80 @ 0x50 8000710: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000712: f107 0320 add.w r3, r7, #32 8000716: 2230 movs r2, #48 @ 0x30 8000718: 2100 movs r1, #0 800071a: 4618 mov r0, r3 800071c: f001 fe7e bl 800241c RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000720: f107 030c add.w r3, r7, #12 8000724: 2200 movs r2, #0 8000726: 601a str r2, [r3, #0] 8000728: 605a str r2, [r3, #4] 800072a: 609a str r2, [r3, #8] 800072c: 60da str r2, [r3, #12] 800072e: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000730: 2300 movs r3, #0 8000732: 60bb str r3, [r7, #8] 8000734: 4b2e ldr r3, [pc, #184] @ (80007f0 ) 8000736: 6c1b ldr r3, [r3, #64] @ 0x40 8000738: 4a2d ldr r2, [pc, #180] @ (80007f0 ) 800073a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800073e: 6413 str r3, [r2, #64] @ 0x40 8000740: 4b2b ldr r3, [pc, #172] @ (80007f0 ) 8000742: 6c1b ldr r3, [r3, #64] @ 0x40 8000744: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000748: 60bb str r3, [r7, #8] 800074a: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 800074c: 2300 movs r3, #0 800074e: 607b str r3, [r7, #4] 8000750: 4b28 ldr r3, [pc, #160] @ (80007f4 ) 8000752: 681b ldr r3, [r3, #0] 8000754: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000758: 4a26 ldr r2, [pc, #152] @ (80007f4 ) 800075a: f443 4380 orr.w r3, r3, #16384 @ 0x4000 800075e: 6013 str r3, [r2, #0] 8000760: 4b24 ldr r3, [pc, #144] @ (80007f4 ) 8000762: 681b ldr r3, [r3, #0] 8000764: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000768: 607b str r3, [r7, #4] 800076a: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 800076c: 2302 movs r3, #2 800076e: 623b str r3, [r7, #32] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8000770: 2301 movs r3, #1 8000772: 62fb str r3, [r7, #44] @ 0x2c RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 8000774: 2310 movs r3, #16 8000776: 633b str r3, [r7, #48] @ 0x30 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 8000778: 2302 movs r3, #2 800077a: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 800077c: 2300 movs r3, #0 800077e: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLM = 8; 8000780: 2308 movs r3, #8 8000782: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLN = 50; 8000784: 2332 movs r3, #50 @ 0x32 8000786: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 8000788: 2304 movs r3, #4 800078a: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLQ = 7; 800078c: 2307 movs r3, #7 800078e: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000790: f107 0320 add.w r3, r7, #32 8000794: 4618 mov r0, r3 8000796: f000 fcd3 bl 8001140 800079a: 4603 mov r3, r0 800079c: 2b00 cmp r3, #0 800079e: bf14 ite ne 80007a0: 2301 movne r3, #1 80007a2: 2300 moveq r3, #0 80007a4: b2db uxtb r3, r3 80007a6: 2b00 cmp r3, #0 80007a8: d001 beq.n 80007ae { Error_Handler(); 80007aa: f000 f8a1 bl 80008f0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80007ae: 230f movs r3, #15 80007b0: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 80007b2: 2302 movs r3, #2 80007b4: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 80007b6: 2300 movs r3, #0 80007b8: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV8; 80007ba: f44f 53c0 mov.w r3, #6144 @ 0x1800 80007be: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV4; 80007c0: f44f 53a0 mov.w r3, #5120 @ 0x1400 80007c4: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 80007c6: f107 030c add.w r3, r7, #12 80007ca: 2100 movs r1, #0 80007cc: 4618 mov r0, r3 80007ce: f000 ff2f bl 8001630 80007d2: 4603 mov r3, r0 80007d4: 2b00 cmp r3, #0 80007d6: bf14 ite ne 80007d8: 2301 movne r3, #1 80007da: 2300 moveq r3, #0 80007dc: b2db uxtb r3, r3 80007de: 2b00 cmp r3, #0 80007e0: d001 beq.n 80007e6 { Error_Handler(); 80007e2: f000 f885 bl 80008f0 } } 80007e6: bf00 nop 80007e8: 3750 adds r7, #80 @ 0x50 80007ea: 46bd mov sp, r7 80007ec: bd80 pop {r7, pc} 80007ee: bf00 nop 80007f0: 40023800 .word 0x40023800 80007f4: 40007000 .word 0x40007000 080007f8 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 80007f8: b580 push {r7, lr} 80007fa: b088 sub sp, #32 80007fc: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80007fe: f107 030c add.w r3, r7, #12 8000802: 2200 movs r2, #0 8000804: 601a str r2, [r3, #0] 8000806: 605a str r2, [r3, #4] 8000808: 609a str r2, [r3, #8] 800080a: 60da str r2, [r3, #12] 800080c: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 800080e: 2300 movs r3, #0 8000810: 60bb str r3, [r7, #8] 8000812: 4b23 ldr r3, [pc, #140] @ (80008a0 ) 8000814: 6b1b ldr r3, [r3, #48] @ 0x30 8000816: 4a22 ldr r2, [pc, #136] @ (80008a0 ) 8000818: f043 0301 orr.w r3, r3, #1 800081c: 6313 str r3, [r2, #48] @ 0x30 800081e: 4b20 ldr r3, [pc, #128] @ (80008a0 ) 8000820: 6b1b ldr r3, [r3, #48] @ 0x30 8000822: f003 0301 and.w r3, r3, #1 8000826: 60bb str r3, [r7, #8] 8000828: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 800082a: 2300 movs r3, #0 800082c: 607b str r3, [r7, #4] 800082e: 4b1c ldr r3, [pc, #112] @ (80008a0 ) 8000830: 6b1b ldr r3, [r3, #48] @ 0x30 8000832: 4a1b ldr r2, [pc, #108] @ (80008a0 ) 8000834: f043 0308 orr.w r3, r3, #8 8000838: 6313 str r3, [r2, #48] @ 0x30 800083a: 4b19 ldr r3, [pc, #100] @ (80008a0 ) 800083c: 6b1b ldr r3, [r3, #48] @ 0x30 800083e: f003 0308 and.w r3, r3, #8 8000842: 607b str r3, [r7, #4] 8000844: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, White_Pin|Red_Pin|Yellow_Pin|Green_Pin, GPIO_PIN_RESET); 8000846: 2200 movs r2, #0 8000848: 21aa movs r1, #170 @ 0xaa 800084a: 4816 ldr r0, [pc, #88] @ (80008a4 ) 800084c: f000 fc46 bl 80010dc /*Configure GPIO pin : PedButton_Pin */ GPIO_InitStruct.Pin = PedButton_Pin; 8000850: f44f 4380 mov.w r3, #16384 @ 0x4000 8000854: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; 8000856: f44f 1388 mov.w r3, #1114112 @ 0x110000 800085a: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 800085c: 2300 movs r3, #0 800085e: 617b str r3, [r7, #20] HAL_GPIO_Init(PedButton_GPIO_Port, &GPIO_InitStruct); 8000860: f107 030c add.w r3, r7, #12 8000864: 4619 mov r1, r3 8000866: 4810 ldr r0, [pc, #64] @ (80008a8 ) 8000868: f000 fa8c bl 8000d84 /*Configure GPIO pins : White_Pin Red_Pin Yellow_Pin Green_Pin */ GPIO_InitStruct.Pin = White_Pin|Red_Pin|Yellow_Pin|Green_Pin; 800086c: 23aa movs r3, #170 @ 0xaa 800086e: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000870: 2301 movs r3, #1 8000872: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8000874: 2300 movs r3, #0 8000876: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000878: 2300 movs r3, #0 800087a: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800087c: f107 030c add.w r3, r7, #12 8000880: 4619 mov r1, r3 8000882: 4808 ldr r0, [pc, #32] @ (80008a4 ) 8000884: f000 fa7e bl 8000d84 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI15_10_IRQn, 15, 0); 8000888: 2200 movs r2, #0 800088a: 210f movs r1, #15 800088c: 2028 movs r0, #40 @ 0x28 800088e: f000 fa4f bl 8000d30 HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); 8000892: 2028 movs r0, #40 @ 0x28 8000894: f000 fa68 bl 8000d68 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000898: bf00 nop 800089a: 3720 adds r7, #32 800089c: 46bd mov sp, r7 800089e: bd80 pop {r7, pc} 80008a0: 40023800 .word 0x40023800 80008a4: 40020c00 .word 0x40020c00 80008a8: 40020000 .word 0x40020000 080008ac : //{ // HAL_GPIO_EXTI_IRQHandler(PedButton_Pin); //} extern "C" void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 80008ac: b580 push {r7, lr} 80008ae: b084 sub sp, #16 80008b0: af00 add r7, sp, #0 80008b2: 4603 mov r3, r0 80008b4: 80fb strh r3, [r7, #6] static uint32_t lastInterruptTime = 0; uint32_t now = HAL_GetTick(); 80008b6: f000 f977 bl 8000ba8 80008ba: 60f8 str r0, [r7, #12] /* software debounce */ if(now - lastInterruptTime < 100) 80008bc: 4b0a ldr r3, [pc, #40] @ (80008e8 ) 80008be: 681b ldr r3, [r3, #0] 80008c0: 68fa ldr r2, [r7, #12] 80008c2: 1ad3 subs r3, r2, r3 80008c4: 2b63 cmp r3, #99 @ 0x63 80008c6: d90a bls.n 80008de { return; } lastInterruptTime = now; 80008c8: 4a07 ldr r2, [pc, #28] @ (80008e8 ) 80008ca: 68fb ldr r3, [r7, #12] 80008cc: 6013 str r3, [r2, #0] if (GPIO_Pin == PedButton_Pin) 80008ce: 88fb ldrh r3, [r7, #6] 80008d0: f5b3 4f80 cmp.w r3, #16384 @ 0x4000 80008d4: d104 bne.n 80008e0 { buttonPressedThisCycle = true; 80008d6: 4b05 ldr r3, [pc, #20] @ (80008ec ) 80008d8: 2201 movs r2, #1 80008da: 701a strb r2, [r3, #0] 80008dc: e000 b.n 80008e0 return; 80008de: bf00 nop } } 80008e0: 3710 adds r7, #16 80008e2: 46bd mov sp, r7 80008e4: bd80 pop {r7, pc} 80008e6: bf00 nop 80008e8: 20000030 .word 0x20000030 80008ec: 2000002c .word 0x2000002c 080008f0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 80008f0: b480 push {r7} 80008f2: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80008f4: b672 cpsid i } 80008f6: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 80008f8: bf00 nop 80008fa: e7fd b.n 80008f8 080008fc : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 80008fc: b580 push {r7, lr} 80008fe: b082 sub sp, #8 8000900: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000902: 2300 movs r3, #0 8000904: 607b str r3, [r7, #4] 8000906: 4b12 ldr r3, [pc, #72] @ (8000950 ) 8000908: 6c5b ldr r3, [r3, #68] @ 0x44 800090a: 4a11 ldr r2, [pc, #68] @ (8000950 ) 800090c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000910: 6453 str r3, [r2, #68] @ 0x44 8000912: 4b0f ldr r3, [pc, #60] @ (8000950 ) 8000914: 6c5b ldr r3, [r3, #68] @ 0x44 8000916: f403 4380 and.w r3, r3, #16384 @ 0x4000 800091a: 607b str r3, [r7, #4] 800091c: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 800091e: 2300 movs r3, #0 8000920: 603b str r3, [r7, #0] 8000922: 4b0b ldr r3, [pc, #44] @ (8000950 ) 8000924: 6c1b ldr r3, [r3, #64] @ 0x40 8000926: 4a0a ldr r2, [pc, #40] @ (8000950 ) 8000928: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800092c: 6413 str r3, [r2, #64] @ 0x40 800092e: 4b08 ldr r3, [pc, #32] @ (8000950 ) 8000930: 6c1b ldr r3, [r3, #64] @ 0x40 8000932: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000936: 603b str r3, [r7, #0] 8000938: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 800093a: 2200 movs r2, #0 800093c: 210f movs r1, #15 800093e: f06f 0001 mvn.w r0, #1 8000942: f000 f9f5 bl 8000d30 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000946: bf00 nop 8000948: 3708 adds r7, #8 800094a: 46bd mov sp, r7 800094c: bd80 pop {r7, pc} 800094e: bf00 nop 8000950: 40023800 .word 0x40023800 08000954 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8000954: b480 push {r7} 8000956: b085 sub sp, #20 8000958: af00 add r7, sp, #0 800095a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 800095c: 687b ldr r3, [r7, #4] 800095e: 681b ldr r3, [r3, #0] 8000960: 4a0b ldr r2, [pc, #44] @ (8000990 ) 8000962: 4293 cmp r3, r2 8000964: d10d bne.n 8000982 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8000966: 2300 movs r3, #0 8000968: 60fb str r3, [r7, #12] 800096a: 4b0a ldr r3, [pc, #40] @ (8000994 ) 800096c: 6c5b ldr r3, [r3, #68] @ 0x44 800096e: 4a09 ldr r2, [pc, #36] @ (8000994 ) 8000970: f043 0301 orr.w r3, r3, #1 8000974: 6453 str r3, [r2, #68] @ 0x44 8000976: 4b07 ldr r3, [pc, #28] @ (8000994 ) 8000978: 6c5b ldr r3, [r3, #68] @ 0x44 800097a: f003 0301 and.w r3, r3, #1 800097e: 60fb str r3, [r7, #12] 8000980: 68fb ldr r3, [r7, #12] /* USER CODE END TIM1_MspInit 1 */ } } 8000982: bf00 nop 8000984: 3714 adds r7, #20 8000986: 46bd mov sp, r7 8000988: f85d 7b04 ldr.w r7, [sp], #4 800098c: 4770 bx lr 800098e: bf00 nop 8000990: 40010000 .word 0x40010000 8000994: 40023800 .word 0x40023800 08000998 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8000998: b580 push {r7, lr} 800099a: b08e sub sp, #56 @ 0x38 800099c: af00 add r7, sp, #0 800099e: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock, uwAPB1Prescaler = 0U; 80009a0: 2300 movs r3, #0 80009a2: 62fb str r3, [r7, #44] @ 0x2c uint32_t uwPrescalerValue = 0U; 80009a4: 2300 movs r3, #0 80009a6: 62bb str r3, [r7, #40] @ 0x28 uint32_t pFLatency; HAL_StatusTypeDef status; /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 80009a8: 2300 movs r3, #0 80009aa: 60fb str r3, [r7, #12] 80009ac: 4b33 ldr r3, [pc, #204] @ (8000a7c ) 80009ae: 6c1b ldr r3, [r3, #64] @ 0x40 80009b0: 4a32 ldr r2, [pc, #200] @ (8000a7c ) 80009b2: f043 0310 orr.w r3, r3, #16 80009b6: 6413 str r3, [r2, #64] @ 0x40 80009b8: 4b30 ldr r3, [pc, #192] @ (8000a7c ) 80009ba: 6c1b ldr r3, [r3, #64] @ 0x40 80009bc: f003 0310 and.w r3, r3, #16 80009c0: 60fb str r3, [r7, #12] 80009c2: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80009c4: f107 0210 add.w r2, r7, #16 80009c8: f107 0314 add.w r3, r7, #20 80009cc: 4611 mov r1, r2 80009ce: 4618 mov r0, r3 80009d0: f001 f83a bl 8001a48 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80009d4: 6a3b ldr r3, [r7, #32] 80009d6: 62fb str r3, [r7, #44] @ 0x2c /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80009d8: 6afb ldr r3, [r7, #44] @ 0x2c 80009da: 2b00 cmp r3, #0 80009dc: d103 bne.n 80009e6 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80009de: f001 f81f bl 8001a20 80009e2: 6378 str r0, [r7, #52] @ 0x34 80009e4: e004 b.n 80009f0 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80009e6: f001 f81b bl 8001a20 80009ea: 4603 mov r3, r0 80009ec: 005b lsls r3, r3, #1 80009ee: 637b str r3, [r7, #52] @ 0x34 } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80009f0: 6b7b ldr r3, [r7, #52] @ 0x34 80009f2: 4a23 ldr r2, [pc, #140] @ (8000a80 ) 80009f4: fba2 2303 umull r2, r3, r2, r3 80009f8: 0c9b lsrs r3, r3, #18 80009fa: 3b01 subs r3, #1 80009fc: 62bb str r3, [r7, #40] @ 0x28 /* Initialize TIM6 */ htim6.Instance = TIM6; 80009fe: 4b21 ldr r3, [pc, #132] @ (8000a84 ) 8000a00: 4a21 ldr r2, [pc, #132] @ (8000a88 ) 8000a02: 601a str r2, [r3, #0] * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8000a04: 4b1f ldr r3, [pc, #124] @ (8000a84 ) 8000a06: f240 32e7 movw r2, #999 @ 0x3e7 8000a0a: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8000a0c: 4a1d ldr r2, [pc, #116] @ (8000a84 ) 8000a0e: 6abb ldr r3, [r7, #40] @ 0x28 8000a10: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 8000a12: 4b1c ldr r3, [pc, #112] @ (8000a84 ) 8000a14: 2200 movs r2, #0 8000a16: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8000a18: 4b1a ldr r3, [pc, #104] @ (8000a84 ) 8000a1a: 2200 movs r2, #0 8000a1c: 609a str r2, [r3, #8] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000a1e: 4b19 ldr r3, [pc, #100] @ (8000a84 ) 8000a20: 2200 movs r2, #0 8000a22: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim6); 8000a24: 4817 ldr r0, [pc, #92] @ (8000a84 ) 8000a26: f001 f841 bl 8001aac 8000a2a: 4603 mov r3, r0 8000a2c: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 8000a30: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8000a34: 2b00 cmp r3, #0 8000a36: d11b bne.n 8000a70 { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim6); 8000a38: 4812 ldr r0, [pc, #72] @ (8000a84 ) 8000a3a: f001 f887 bl 8001b4c 8000a3e: 4603 mov r3, r0 8000a40: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 8000a44: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8000a48: 2b00 cmp r3, #0 8000a4a: d111 bne.n 8000a70 { /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8000a4c: 2036 movs r0, #54 @ 0x36 8000a4e: f000 f98b bl 8000d68 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8000a52: 687b ldr r3, [r7, #4] 8000a54: 2b0f cmp r3, #15 8000a56: d808 bhi.n 8000a6a { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); 8000a58: 2200 movs r2, #0 8000a5a: 6879 ldr r1, [r7, #4] 8000a5c: 2036 movs r0, #54 @ 0x36 8000a5e: f000 f967 bl 8000d30 uwTickPrio = TickPriority; 8000a62: 4a0a ldr r2, [pc, #40] @ (8000a8c ) 8000a64: 687b ldr r3, [r7, #4] 8000a66: 6013 str r3, [r2, #0] 8000a68: e002 b.n 8000a70 } else { status = HAL_ERROR; 8000a6a: 2301 movs r3, #1 8000a6c: f887 3033 strb.w r3, [r7, #51] @ 0x33 } } } /* Return function status */ return status; 8000a70: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 } 8000a74: 4618 mov r0, r3 8000a76: 3738 adds r7, #56 @ 0x38 8000a78: 46bd mov sp, r7 8000a7a: bd80 pop {r7, pc} 8000a7c: 40023800 .word 0x40023800 8000a80: 431bde83 .word 0x431bde83 8000a84: 20000034 .word 0x20000034 8000a88: 40001000 .word 0x40001000 8000a8c: 20000008 .word 0x20000008 08000a90 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8000a90: b480 push {r7} 8000a92: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8000a94: bf00 nop 8000a96: e7fd b.n 8000a94 08000a98 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8000a98: b480 push {r7} 8000a9a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8000a9c: bf00 nop 8000a9e: e7fd b.n 8000a9c 08000aa0 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8000aa0: b480 push {r7} 8000aa2: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8000aa4: bf00 nop 8000aa6: e7fd b.n 8000aa4 08000aa8 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8000aa8: b480 push {r7} 8000aaa: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8000aac: bf00 nop 8000aae: e7fd b.n 8000aac 08000ab0 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8000ab0: b480 push {r7} 8000ab2: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8000ab4: bf00 nop 8000ab6: e7fd b.n 8000ab4 08000ab8 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8000ab8: b480 push {r7} 8000aba: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8000abc: bf00 nop 8000abe: 46bd mov sp, r7 8000ac0: f85d 7b04 ldr.w r7, [sp], #4 8000ac4: 4770 bx lr 08000ac6 : /** * @brief This function handles EXTI line[15:10] interrupts. */ void EXTI15_10_IRQHandler(void) { 8000ac6: b580 push {r7, lr} 8000ac8: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(PedButton_Pin); 8000aca: f44f 4080 mov.w r0, #16384 @ 0x4000 8000ace: f000 fb1f bl 8001110 /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } 8000ad2: bf00 nop 8000ad4: bd80 pop {r7, pc} ... 08000ad8 : /** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8000ad8: b580 push {r7, lr} 8000ada: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8000adc: 4802 ldr r0, [pc, #8] @ (8000ae8 ) 8000ade: f001 f8a5 bl 8001c2c /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 8000ae2: bf00 nop 8000ae4: bd80 pop {r7, pc} 8000ae6: bf00 nop 8000ae8: 20000034 .word 0x20000034 08000aec : * configuration. * @param None * @retval None */ void SystemInit(void) { 8000aec: b480 push {r7} 8000aee: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8000af0: 4b06 ldr r3, [pc, #24] @ (8000b0c ) 8000af2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8000af6: 4a05 ldr r2, [pc, #20] @ (8000b0c ) 8000af8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8000afc: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8000b00: bf00 nop 8000b02: 46bd mov sp, r7 8000b04: f85d 7b04 ldr.w r7, [sp], #4 8000b08: 4770 bx lr 8000b0a: bf00 nop 8000b0c: e000ed00 .word 0xe000ed00 08000b10 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8000b10: f8df d034 ldr.w sp, [pc, #52] @ 8000b48 /* Call the clock system initialization function.*/ bl SystemInit 8000b14: f7ff ffea bl 8000aec /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 8000b18: 480c ldr r0, [pc, #48] @ (8000b4c ) ldr r1, =_edata 8000b1a: 490d ldr r1, [pc, #52] @ (8000b50 ) ldr r2, =_sidata 8000b1c: 4a0d ldr r2, [pc, #52] @ (8000b54 ) movs r3, #0 8000b1e: 2300 movs r3, #0 b LoopCopyDataInit 8000b20: e002 b.n 8000b28 08000b22 : CopyDataInit: ldr r4, [r2, r3] 8000b22: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8000b24: 50c4 str r4, [r0, r3] adds r3, r3, #4 8000b26: 3304 adds r3, #4 08000b28 : LoopCopyDataInit: adds r4, r0, r3 8000b28: 18c4 adds r4, r0, r3 cmp r4, r1 8000b2a: 428c cmp r4, r1 bcc CopyDataInit 8000b2c: d3f9 bcc.n 8000b22 /* Zero fill the bss segment. */ ldr r2, =_sbss 8000b2e: 4a0a ldr r2, [pc, #40] @ (8000b58 ) ldr r4, =_ebss 8000b30: 4c0a ldr r4, [pc, #40] @ (8000b5c ) movs r3, #0 8000b32: 2300 movs r3, #0 b LoopFillZerobss 8000b34: e001 b.n 8000b3a 08000b36 : FillZerobss: str r3, [r2] 8000b36: 6013 str r3, [r2, #0] adds r2, r2, #4 8000b38: 3204 adds r2, #4 08000b3a : LoopFillZerobss: cmp r2, r4 8000b3a: 42a2 cmp r2, r4 bcc FillZerobss 8000b3c: d3fb bcc.n 8000b36 /* Call static constructors */ bl __libc_init_array 8000b3e: f001 fc75 bl 800242c <__libc_init_array> /* Call the application's entry point.*/ bl main 8000b42: f7ff fd2b bl 800059c
bx lr 8000b46: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 8000b48: 20030000 .word 0x20030000 ldr r0, =_sdata 8000b4c: 20000000 .word 0x20000000 ldr r1, =_edata 8000b50: 2000000c .word 0x2000000c ldr r2, =_sidata 8000b54: 080024b4 .word 0x080024b4 ldr r2, =_sbss 8000b58: 2000000c .word 0x2000000c ldr r4, =_ebss 8000b5c: 20000134 .word 0x20000134 08000b60 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000b60: e7fe b.n 8000b60 ... 08000b64 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000b64: b580 push {r7, lr} 8000b66: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 8000b68: 4b0e ldr r3, [pc, #56] @ (8000ba4 ) 8000b6a: 681b ldr r3, [r3, #0] 8000b6c: 4a0d ldr r2, [pc, #52] @ (8000ba4 ) 8000b6e: f443 7300 orr.w r3, r3, #512 @ 0x200 8000b72: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8000b74: 4b0b ldr r3, [pc, #44] @ (8000ba4 ) 8000b76: 681b ldr r3, [r3, #0] 8000b78: 4a0a ldr r2, [pc, #40] @ (8000ba4 ) 8000b7a: f443 6380 orr.w r3, r3, #1024 @ 0x400 8000b7e: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8000b80: 4b08 ldr r3, [pc, #32] @ (8000ba4 ) 8000b82: 681b ldr r3, [r3, #0] 8000b84: 4a07 ldr r2, [pc, #28] @ (8000ba4 ) 8000b86: f443 7380 orr.w r3, r3, #256 @ 0x100 8000b8a: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8000b8c: 2003 movs r0, #3 8000b8e: f000 f8c4 bl 8000d1a /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000b92: 200f movs r0, #15 8000b94: f7ff ff00 bl 8000998 /* Init the low level hardware */ HAL_MspInit(); 8000b98: f7ff feb0 bl 80008fc /* Return function status */ return HAL_OK; 8000b9c: 2300 movs r3, #0 } 8000b9e: 4618 mov r0, r3 8000ba0: bd80 pop {r7, pc} 8000ba2: bf00 nop 8000ba4: 40023c00 .word 0x40023c00 08000ba8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8000ba8: b480 push {r7} 8000baa: af00 add r7, sp, #0 return uwTick; 8000bac: 4b03 ldr r3, [pc, #12] @ (8000bbc ) 8000bae: 681b ldr r3, [r3, #0] } 8000bb0: 4618 mov r0, r3 8000bb2: 46bd mov sp, r7 8000bb4: f85d 7b04 ldr.w r7, [sp], #4 8000bb8: 4770 bx lr 8000bba: bf00 nop 8000bbc: 2000007c .word 0x2000007c 08000bc0 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000bc0: b480 push {r7} 8000bc2: b085 sub sp, #20 8000bc4: af00 add r7, sp, #0 8000bc6: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000bc8: 687b ldr r3, [r7, #4] 8000bca: f003 0307 and.w r3, r3, #7 8000bce: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000bd0: 4b0c ldr r3, [pc, #48] @ (8000c04 <__NVIC_SetPriorityGrouping+0x44>) 8000bd2: 68db ldr r3, [r3, #12] 8000bd4: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000bd6: 68ba ldr r2, [r7, #8] 8000bd8: f64f 03ff movw r3, #63743 @ 0xf8ff 8000bdc: 4013 ands r3, r2 8000bde: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 8000be0: 68fb ldr r3, [r7, #12] 8000be2: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000be4: 68bb ldr r3, [r7, #8] 8000be6: 4313 orrs r3, r2 reg_value = (reg_value | 8000be8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8000bec: f443 3300 orr.w r3, r3, #131072 @ 0x20000 8000bf0: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 8000bf2: 4a04 ldr r2, [pc, #16] @ (8000c04 <__NVIC_SetPriorityGrouping+0x44>) 8000bf4: 68bb ldr r3, [r7, #8] 8000bf6: 60d3 str r3, [r2, #12] } 8000bf8: bf00 nop 8000bfa: 3714 adds r7, #20 8000bfc: 46bd mov sp, r7 8000bfe: f85d 7b04 ldr.w r7, [sp], #4 8000c02: 4770 bx lr 8000c04: e000ed00 .word 0xe000ed00 08000c08 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8000c08: b480 push {r7} 8000c0a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8000c0c: 4b04 ldr r3, [pc, #16] @ (8000c20 <__NVIC_GetPriorityGrouping+0x18>) 8000c0e: 68db ldr r3, [r3, #12] 8000c10: 0a1b lsrs r3, r3, #8 8000c12: f003 0307 and.w r3, r3, #7 } 8000c16: 4618 mov r0, r3 8000c18: 46bd mov sp, r7 8000c1a: f85d 7b04 ldr.w r7, [sp], #4 8000c1e: 4770 bx lr 8000c20: e000ed00 .word 0xe000ed00 08000c24 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8000c24: b480 push {r7} 8000c26: b083 sub sp, #12 8000c28: af00 add r7, sp, #0 8000c2a: 4603 mov r3, r0 8000c2c: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000c2e: f997 3007 ldrsb.w r3, [r7, #7] 8000c32: 2b00 cmp r3, #0 8000c34: db0b blt.n 8000c4e <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8000c36: 79fb ldrb r3, [r7, #7] 8000c38: f003 021f and.w r2, r3, #31 8000c3c: 4907 ldr r1, [pc, #28] @ (8000c5c <__NVIC_EnableIRQ+0x38>) 8000c3e: f997 3007 ldrsb.w r3, [r7, #7] 8000c42: 095b lsrs r3, r3, #5 8000c44: 2001 movs r0, #1 8000c46: fa00 f202 lsl.w r2, r0, r2 8000c4a: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8000c4e: bf00 nop 8000c50: 370c adds r7, #12 8000c52: 46bd mov sp, r7 8000c54: f85d 7b04 ldr.w r7, [sp], #4 8000c58: 4770 bx lr 8000c5a: bf00 nop 8000c5c: e000e100 .word 0xe000e100 08000c60 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000c60: b480 push {r7} 8000c62: b083 sub sp, #12 8000c64: af00 add r7, sp, #0 8000c66: 4603 mov r3, r0 8000c68: 6039 str r1, [r7, #0] 8000c6a: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8000c6c: f997 3007 ldrsb.w r3, [r7, #7] 8000c70: 2b00 cmp r3, #0 8000c72: db0a blt.n 8000c8a <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000c74: 683b ldr r3, [r7, #0] 8000c76: b2da uxtb r2, r3 8000c78: 490c ldr r1, [pc, #48] @ (8000cac <__NVIC_SetPriority+0x4c>) 8000c7a: f997 3007 ldrsb.w r3, [r7, #7] 8000c7e: 0112 lsls r2, r2, #4 8000c80: b2d2 uxtb r2, r2 8000c82: 440b add r3, r1 8000c84: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8000c88: e00a b.n 8000ca0 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000c8a: 683b ldr r3, [r7, #0] 8000c8c: b2da uxtb r2, r3 8000c8e: 4908 ldr r1, [pc, #32] @ (8000cb0 <__NVIC_SetPriority+0x50>) 8000c90: 79fb ldrb r3, [r7, #7] 8000c92: f003 030f and.w r3, r3, #15 8000c96: 3b04 subs r3, #4 8000c98: 0112 lsls r2, r2, #4 8000c9a: b2d2 uxtb r2, r2 8000c9c: 440b add r3, r1 8000c9e: 761a strb r2, [r3, #24] } 8000ca0: bf00 nop 8000ca2: 370c adds r7, #12 8000ca4: 46bd mov sp, r7 8000ca6: f85d 7b04 ldr.w r7, [sp], #4 8000caa: 4770 bx lr 8000cac: e000e100 .word 0xe000e100 8000cb0: e000ed00 .word 0xe000ed00 08000cb4 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 8000cb4: b480 push {r7} 8000cb6: b089 sub sp, #36 @ 0x24 8000cb8: af00 add r7, sp, #0 8000cba: 60f8 str r0, [r7, #12] 8000cbc: 60b9 str r1, [r7, #8] 8000cbe: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000cc0: 68fb ldr r3, [r7, #12] 8000cc2: f003 0307 and.w r3, r3, #7 8000cc6: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8000cc8: 69fb ldr r3, [r7, #28] 8000cca: f1c3 0307 rsb r3, r3, #7 8000cce: 2b04 cmp r3, #4 8000cd0: bf28 it cs 8000cd2: 2304 movcs r3, #4 8000cd4: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8000cd6: 69fb ldr r3, [r7, #28] 8000cd8: 3304 adds r3, #4 8000cda: 2b06 cmp r3, #6 8000cdc: d902 bls.n 8000ce4 8000cde: 69fb ldr r3, [r7, #28] 8000ce0: 3b03 subs r3, #3 8000ce2: e000 b.n 8000ce6 8000ce4: 2300 movs r3, #0 8000ce6: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000ce8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8000cec: 69bb ldr r3, [r7, #24] 8000cee: fa02 f303 lsl.w r3, r2, r3 8000cf2: 43da mvns r2, r3 8000cf4: 68bb ldr r3, [r7, #8] 8000cf6: 401a ands r2, r3 8000cf8: 697b ldr r3, [r7, #20] 8000cfa: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8000cfc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 8000d00: 697b ldr r3, [r7, #20] 8000d02: fa01 f303 lsl.w r3, r1, r3 8000d06: 43d9 mvns r1, r3 8000d08: 687b ldr r3, [r7, #4] 8000d0a: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8000d0c: 4313 orrs r3, r2 ); } 8000d0e: 4618 mov r0, r3 8000d10: 3724 adds r7, #36 @ 0x24 8000d12: 46bd mov sp, r7 8000d14: f85d 7b04 ldr.w r7, [sp], #4 8000d18: 4770 bx lr 08000d1a : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000d1a: b580 push {r7, lr} 8000d1c: b082 sub sp, #8 8000d1e: af00 add r7, sp, #0 8000d20: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000d22: 6878 ldr r0, [r7, #4] 8000d24: f7ff ff4c bl 8000bc0 <__NVIC_SetPriorityGrouping> } 8000d28: bf00 nop 8000d2a: 3708 adds r7, #8 8000d2c: 46bd mov sp, r7 8000d2e: bd80 pop {r7, pc} 08000d30 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000d30: b580 push {r7, lr} 8000d32: b086 sub sp, #24 8000d34: af00 add r7, sp, #0 8000d36: 4603 mov r3, r0 8000d38: 60b9 str r1, [r7, #8] 8000d3a: 607a str r2, [r7, #4] 8000d3c: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8000d3e: 2300 movs r3, #0 8000d40: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000d42: f7ff ff61 bl 8000c08 <__NVIC_GetPriorityGrouping> 8000d46: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8000d48: 687a ldr r2, [r7, #4] 8000d4a: 68b9 ldr r1, [r7, #8] 8000d4c: 6978 ldr r0, [r7, #20] 8000d4e: f7ff ffb1 bl 8000cb4 8000d52: 4602 mov r2, r0 8000d54: f997 300f ldrsb.w r3, [r7, #15] 8000d58: 4611 mov r1, r2 8000d5a: 4618 mov r0, r3 8000d5c: f7ff ff80 bl 8000c60 <__NVIC_SetPriority> } 8000d60: bf00 nop 8000d62: 3718 adds r7, #24 8000d64: 46bd mov sp, r7 8000d66: bd80 pop {r7, pc} 08000d68 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8000d68: b580 push {r7, lr} 8000d6a: b082 sub sp, #8 8000d6c: af00 add r7, sp, #0 8000d6e: 4603 mov r3, r0 8000d70: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 8000d72: f997 3007 ldrsb.w r3, [r7, #7] 8000d76: 4618 mov r0, r3 8000d78: f7ff ff54 bl 8000c24 <__NVIC_EnableIRQ> } 8000d7c: bf00 nop 8000d7e: 3708 adds r7, #8 8000d80: 46bd mov sp, r7 8000d82: bd80 pop {r7, pc} 08000d84 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000d84: b480 push {r7} 8000d86: b089 sub sp, #36 @ 0x24 8000d88: af00 add r7, sp, #0 8000d8a: 6078 str r0, [r7, #4] 8000d8c: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8000d8e: 2300 movs r3, #0 8000d90: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8000d92: 2300 movs r3, #0 8000d94: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8000d96: 2300 movs r3, #0 8000d98: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8000d9a: 2300 movs r3, #0 8000d9c: 61fb str r3, [r7, #28] 8000d9e: e177 b.n 8001090 { /* Get the IO position */ ioposition = 0x01U << position; 8000da0: 2201 movs r2, #1 8000da2: 69fb ldr r3, [r7, #28] 8000da4: fa02 f303 lsl.w r3, r2, r3 8000da8: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8000daa: 683b ldr r3, [r7, #0] 8000dac: 681b ldr r3, [r3, #0] 8000dae: 697a ldr r2, [r7, #20] 8000db0: 4013 ands r3, r2 8000db2: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8000db4: 693a ldr r2, [r7, #16] 8000db6: 697b ldr r3, [r7, #20] 8000db8: 429a cmp r2, r3 8000dba: f040 8166 bne.w 800108a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8000dbe: 683b ldr r3, [r7, #0] 8000dc0: 685b ldr r3, [r3, #4] 8000dc2: f003 0303 and.w r3, r3, #3 8000dc6: 2b01 cmp r3, #1 8000dc8: d005 beq.n 8000dd6 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000dca: 683b ldr r3, [r7, #0] 8000dcc: 685b ldr r3, [r3, #4] 8000dce: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8000dd2: 2b02 cmp r3, #2 8000dd4: d130 bne.n 8000e38 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8000dd6: 687b ldr r3, [r7, #4] 8000dd8: 689b ldr r3, [r3, #8] 8000dda: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8000ddc: 69fb ldr r3, [r7, #28] 8000dde: 005b lsls r3, r3, #1 8000de0: 2203 movs r2, #3 8000de2: fa02 f303 lsl.w r3, r2, r3 8000de6: 43db mvns r3, r3 8000de8: 69ba ldr r2, [r7, #24] 8000dea: 4013 ands r3, r2 8000dec: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8000dee: 683b ldr r3, [r7, #0] 8000df0: 68da ldr r2, [r3, #12] 8000df2: 69fb ldr r3, [r7, #28] 8000df4: 005b lsls r3, r3, #1 8000df6: fa02 f303 lsl.w r3, r2, r3 8000dfa: 69ba ldr r2, [r7, #24] 8000dfc: 4313 orrs r3, r2 8000dfe: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8000e00: 687b ldr r3, [r7, #4] 8000e02: 69ba ldr r2, [r7, #24] 8000e04: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8000e06: 687b ldr r3, [r7, #4] 8000e08: 685b ldr r3, [r3, #4] 8000e0a: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8000e0c: 2201 movs r2, #1 8000e0e: 69fb ldr r3, [r7, #28] 8000e10: fa02 f303 lsl.w r3, r2, r3 8000e14: 43db mvns r3, r3 8000e16: 69ba ldr r2, [r7, #24] 8000e18: 4013 ands r3, r2 8000e1a: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8000e1c: 683b ldr r3, [r7, #0] 8000e1e: 685b ldr r3, [r3, #4] 8000e20: 091b lsrs r3, r3, #4 8000e22: f003 0201 and.w r2, r3, #1 8000e26: 69fb ldr r3, [r7, #28] 8000e28: fa02 f303 lsl.w r3, r2, r3 8000e2c: 69ba ldr r2, [r7, #24] 8000e2e: 4313 orrs r3, r2 8000e30: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8000e32: 687b ldr r3, [r7, #4] 8000e34: 69ba ldr r2, [r7, #24] 8000e36: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8000e38: 683b ldr r3, [r7, #0] 8000e3a: 685b ldr r3, [r3, #4] 8000e3c: f003 0303 and.w r3, r3, #3 8000e40: 2b03 cmp r3, #3 8000e42: d017 beq.n 8000e74 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8000e44: 687b ldr r3, [r7, #4] 8000e46: 68db ldr r3, [r3, #12] 8000e48: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8000e4a: 69fb ldr r3, [r7, #28] 8000e4c: 005b lsls r3, r3, #1 8000e4e: 2203 movs r2, #3 8000e50: fa02 f303 lsl.w r3, r2, r3 8000e54: 43db mvns r3, r3 8000e56: 69ba ldr r2, [r7, #24] 8000e58: 4013 ands r3, r2 8000e5a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8000e5c: 683b ldr r3, [r7, #0] 8000e5e: 689a ldr r2, [r3, #8] 8000e60: 69fb ldr r3, [r7, #28] 8000e62: 005b lsls r3, r3, #1 8000e64: fa02 f303 lsl.w r3, r2, r3 8000e68: 69ba ldr r2, [r7, #24] 8000e6a: 4313 orrs r3, r2 8000e6c: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8000e6e: 687b ldr r3, [r7, #4] 8000e70: 69ba ldr r2, [r7, #24] 8000e72: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8000e74: 683b ldr r3, [r7, #0] 8000e76: 685b ldr r3, [r3, #4] 8000e78: f003 0303 and.w r3, r3, #3 8000e7c: 2b02 cmp r3, #2 8000e7e: d123 bne.n 8000ec8 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8000e80: 69fb ldr r3, [r7, #28] 8000e82: 08da lsrs r2, r3, #3 8000e84: 687b ldr r3, [r7, #4] 8000e86: 3208 adds r2, #8 8000e88: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8000e8c: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8000e8e: 69fb ldr r3, [r7, #28] 8000e90: f003 0307 and.w r3, r3, #7 8000e94: 009b lsls r3, r3, #2 8000e96: 220f movs r2, #15 8000e98: fa02 f303 lsl.w r3, r2, r3 8000e9c: 43db mvns r3, r3 8000e9e: 69ba ldr r2, [r7, #24] 8000ea0: 4013 ands r3, r2 8000ea2: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8000ea4: 683b ldr r3, [r7, #0] 8000ea6: 691a ldr r2, [r3, #16] 8000ea8: 69fb ldr r3, [r7, #28] 8000eaa: f003 0307 and.w r3, r3, #7 8000eae: 009b lsls r3, r3, #2 8000eb0: fa02 f303 lsl.w r3, r2, r3 8000eb4: 69ba ldr r2, [r7, #24] 8000eb6: 4313 orrs r3, r2 8000eb8: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8000eba: 69fb ldr r3, [r7, #28] 8000ebc: 08da lsrs r2, r3, #3 8000ebe: 687b ldr r3, [r7, #4] 8000ec0: 3208 adds r2, #8 8000ec2: 69b9 ldr r1, [r7, #24] 8000ec4: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 681b ldr r3, [r3, #0] 8000ecc: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8000ece: 69fb ldr r3, [r7, #28] 8000ed0: 005b lsls r3, r3, #1 8000ed2: 2203 movs r2, #3 8000ed4: fa02 f303 lsl.w r3, r2, r3 8000ed8: 43db mvns r3, r3 8000eda: 69ba ldr r2, [r7, #24] 8000edc: 4013 ands r3, r2 8000ede: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8000ee0: 683b ldr r3, [r7, #0] 8000ee2: 685b ldr r3, [r3, #4] 8000ee4: f003 0203 and.w r2, r3, #3 8000ee8: 69fb ldr r3, [r7, #28] 8000eea: 005b lsls r3, r3, #1 8000eec: fa02 f303 lsl.w r3, r2, r3 8000ef0: 69ba ldr r2, [r7, #24] 8000ef2: 4313 orrs r3, r2 8000ef4: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8000ef6: 687b ldr r3, [r7, #4] 8000ef8: 69ba ldr r2, [r7, #24] 8000efa: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8000efc: 683b ldr r3, [r7, #0] 8000efe: 685b ldr r3, [r3, #4] 8000f00: f403 3340 and.w r3, r3, #196608 @ 0x30000 8000f04: 2b00 cmp r3, #0 8000f06: f000 80c0 beq.w 800108a { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000f0a: 2300 movs r3, #0 8000f0c: 60fb str r3, [r7, #12] 8000f0e: 4b66 ldr r3, [pc, #408] @ (80010a8 ) 8000f10: 6c5b ldr r3, [r3, #68] @ 0x44 8000f12: 4a65 ldr r2, [pc, #404] @ (80010a8 ) 8000f14: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000f18: 6453 str r3, [r2, #68] @ 0x44 8000f1a: 4b63 ldr r3, [pc, #396] @ (80010a8 ) 8000f1c: 6c5b ldr r3, [r3, #68] @ 0x44 8000f1e: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000f22: 60fb str r3, [r7, #12] 8000f24: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8000f26: 4a61 ldr r2, [pc, #388] @ (80010ac ) 8000f28: 69fb ldr r3, [r7, #28] 8000f2a: 089b lsrs r3, r3, #2 8000f2c: 3302 adds r3, #2 8000f2e: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8000f32: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8000f34: 69fb ldr r3, [r7, #28] 8000f36: f003 0303 and.w r3, r3, #3 8000f3a: 009b lsls r3, r3, #2 8000f3c: 220f movs r2, #15 8000f3e: fa02 f303 lsl.w r3, r2, r3 8000f42: 43db mvns r3, r3 8000f44: 69ba ldr r2, [r7, #24] 8000f46: 4013 ands r3, r2 8000f48: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8000f4a: 687b ldr r3, [r7, #4] 8000f4c: 4a58 ldr r2, [pc, #352] @ (80010b0 ) 8000f4e: 4293 cmp r3, r2 8000f50: d037 beq.n 8000fc2 8000f52: 687b ldr r3, [r7, #4] 8000f54: 4a57 ldr r2, [pc, #348] @ (80010b4 ) 8000f56: 4293 cmp r3, r2 8000f58: d031 beq.n 8000fbe 8000f5a: 687b ldr r3, [r7, #4] 8000f5c: 4a56 ldr r2, [pc, #344] @ (80010b8 ) 8000f5e: 4293 cmp r3, r2 8000f60: d02b beq.n 8000fba 8000f62: 687b ldr r3, [r7, #4] 8000f64: 4a55 ldr r2, [pc, #340] @ (80010bc ) 8000f66: 4293 cmp r3, r2 8000f68: d025 beq.n 8000fb6 8000f6a: 687b ldr r3, [r7, #4] 8000f6c: 4a54 ldr r2, [pc, #336] @ (80010c0 ) 8000f6e: 4293 cmp r3, r2 8000f70: d01f beq.n 8000fb2 8000f72: 687b ldr r3, [r7, #4] 8000f74: 4a53 ldr r2, [pc, #332] @ (80010c4 ) 8000f76: 4293 cmp r3, r2 8000f78: d019 beq.n 8000fae 8000f7a: 687b ldr r3, [r7, #4] 8000f7c: 4a52 ldr r2, [pc, #328] @ (80010c8 ) 8000f7e: 4293 cmp r3, r2 8000f80: d013 beq.n 8000faa 8000f82: 687b ldr r3, [r7, #4] 8000f84: 4a51 ldr r2, [pc, #324] @ (80010cc ) 8000f86: 4293 cmp r3, r2 8000f88: d00d beq.n 8000fa6 8000f8a: 687b ldr r3, [r7, #4] 8000f8c: 4a50 ldr r2, [pc, #320] @ (80010d0 ) 8000f8e: 4293 cmp r3, r2 8000f90: d007 beq.n 8000fa2 8000f92: 687b ldr r3, [r7, #4] 8000f94: 4a4f ldr r2, [pc, #316] @ (80010d4 ) 8000f96: 4293 cmp r3, r2 8000f98: d101 bne.n 8000f9e 8000f9a: 2309 movs r3, #9 8000f9c: e012 b.n 8000fc4 8000f9e: 230a movs r3, #10 8000fa0: e010 b.n 8000fc4 8000fa2: 2308 movs r3, #8 8000fa4: e00e b.n 8000fc4 8000fa6: 2307 movs r3, #7 8000fa8: e00c b.n 8000fc4 8000faa: 2306 movs r3, #6 8000fac: e00a b.n 8000fc4 8000fae: 2305 movs r3, #5 8000fb0: e008 b.n 8000fc4 8000fb2: 2304 movs r3, #4 8000fb4: e006 b.n 8000fc4 8000fb6: 2303 movs r3, #3 8000fb8: e004 b.n 8000fc4 8000fba: 2302 movs r3, #2 8000fbc: e002 b.n 8000fc4 8000fbe: 2301 movs r3, #1 8000fc0: e000 b.n 8000fc4 8000fc2: 2300 movs r3, #0 8000fc4: 69fa ldr r2, [r7, #28] 8000fc6: f002 0203 and.w r2, r2, #3 8000fca: 0092 lsls r2, r2, #2 8000fcc: 4093 lsls r3, r2 8000fce: 69ba ldr r2, [r7, #24] 8000fd0: 4313 orrs r3, r2 8000fd2: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8000fd4: 4935 ldr r1, [pc, #212] @ (80010ac ) 8000fd6: 69fb ldr r3, [r7, #28] 8000fd8: 089b lsrs r3, r3, #2 8000fda: 3302 adds r3, #2 8000fdc: 69ba ldr r2, [r7, #24] 8000fde: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8000fe2: 4b3d ldr r3, [pc, #244] @ (80010d8 ) 8000fe4: 689b ldr r3, [r3, #8] 8000fe6: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8000fe8: 693b ldr r3, [r7, #16] 8000fea: 43db mvns r3, r3 8000fec: 69ba ldr r2, [r7, #24] 8000fee: 4013 ands r3, r2 8000ff0: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8000ff2: 683b ldr r3, [r7, #0] 8000ff4: 685b ldr r3, [r3, #4] 8000ff6: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8000ffa: 2b00 cmp r3, #0 8000ffc: d003 beq.n 8001006 { temp |= iocurrent; 8000ffe: 69ba ldr r2, [r7, #24] 8001000: 693b ldr r3, [r7, #16] 8001002: 4313 orrs r3, r2 8001004: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8001006: 4a34 ldr r2, [pc, #208] @ (80010d8 ) 8001008: 69bb ldr r3, [r7, #24] 800100a: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 800100c: 4b32 ldr r3, [pc, #200] @ (80010d8 ) 800100e: 68db ldr r3, [r3, #12] 8001010: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001012: 693b ldr r3, [r7, #16] 8001014: 43db mvns r3, r3 8001016: 69ba ldr r2, [r7, #24] 8001018: 4013 ands r3, r2 800101a: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 800101c: 683b ldr r3, [r7, #0] 800101e: 685b ldr r3, [r3, #4] 8001020: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001024: 2b00 cmp r3, #0 8001026: d003 beq.n 8001030 { temp |= iocurrent; 8001028: 69ba ldr r2, [r7, #24] 800102a: 693b ldr r3, [r7, #16] 800102c: 4313 orrs r3, r2 800102e: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8001030: 4a29 ldr r2, [pc, #164] @ (80010d8 ) 8001032: 69bb ldr r3, [r7, #24] 8001034: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8001036: 4b28 ldr r3, [pc, #160] @ (80010d8 ) 8001038: 685b ldr r3, [r3, #4] 800103a: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 800103c: 693b ldr r3, [r7, #16] 800103e: 43db mvns r3, r3 8001040: 69ba ldr r2, [r7, #24] 8001042: 4013 ands r3, r2 8001044: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001046: 683b ldr r3, [r7, #0] 8001048: 685b ldr r3, [r3, #4] 800104a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800104e: 2b00 cmp r3, #0 8001050: d003 beq.n 800105a { temp |= iocurrent; 8001052: 69ba ldr r2, [r7, #24] 8001054: 693b ldr r3, [r7, #16] 8001056: 4313 orrs r3, r2 8001058: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 800105a: 4a1f ldr r2, [pc, #124] @ (80010d8 ) 800105c: 69bb ldr r3, [r7, #24] 800105e: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001060: 4b1d ldr r3, [pc, #116] @ (80010d8 ) 8001062: 681b ldr r3, [r3, #0] 8001064: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001066: 693b ldr r3, [r7, #16] 8001068: 43db mvns r3, r3 800106a: 69ba ldr r2, [r7, #24] 800106c: 4013 ands r3, r2 800106e: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001070: 683b ldr r3, [r7, #0] 8001072: 685b ldr r3, [r3, #4] 8001074: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001078: 2b00 cmp r3, #0 800107a: d003 beq.n 8001084 { temp |= iocurrent; 800107c: 69ba ldr r2, [r7, #24] 800107e: 693b ldr r3, [r7, #16] 8001080: 4313 orrs r3, r2 8001082: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8001084: 4a14 ldr r2, [pc, #80] @ (80010d8 ) 8001086: 69bb ldr r3, [r7, #24] 8001088: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 800108a: 69fb ldr r3, [r7, #28] 800108c: 3301 adds r3, #1 800108e: 61fb str r3, [r7, #28] 8001090: 69fb ldr r3, [r7, #28] 8001092: 2b0f cmp r3, #15 8001094: f67f ae84 bls.w 8000da0 } } } } 8001098: bf00 nop 800109a: bf00 nop 800109c: 3724 adds r7, #36 @ 0x24 800109e: 46bd mov sp, r7 80010a0: f85d 7b04 ldr.w r7, [sp], #4 80010a4: 4770 bx lr 80010a6: bf00 nop 80010a8: 40023800 .word 0x40023800 80010ac: 40013800 .word 0x40013800 80010b0: 40020000 .word 0x40020000 80010b4: 40020400 .word 0x40020400 80010b8: 40020800 .word 0x40020800 80010bc: 40020c00 .word 0x40020c00 80010c0: 40021000 .word 0x40021000 80010c4: 40021400 .word 0x40021400 80010c8: 40021800 .word 0x40021800 80010cc: 40021c00 .word 0x40021c00 80010d0: 40022000 .word 0x40022000 80010d4: 40022400 .word 0x40022400 80010d8: 40013c00 .word 0x40013c00 080010dc : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80010dc: b480 push {r7} 80010de: b083 sub sp, #12 80010e0: af00 add r7, sp, #0 80010e2: 6078 str r0, [r7, #4] 80010e4: 460b mov r3, r1 80010e6: 807b strh r3, [r7, #2] 80010e8: 4613 mov r3, r2 80010ea: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 80010ec: 787b ldrb r3, [r7, #1] 80010ee: 2b00 cmp r3, #0 80010f0: d003 beq.n 80010fa { GPIOx->BSRR = GPIO_Pin; 80010f2: 887a ldrh r2, [r7, #2] 80010f4: 687b ldr r3, [r7, #4] 80010f6: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 80010f8: e003 b.n 8001102 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 80010fa: 887b ldrh r3, [r7, #2] 80010fc: 041a lsls r2, r3, #16 80010fe: 687b ldr r3, [r7, #4] 8001100: 619a str r2, [r3, #24] } 8001102: bf00 nop 8001104: 370c adds r7, #12 8001106: 46bd mov sp, r7 8001108: f85d 7b04 ldr.w r7, [sp], #4 800110c: 4770 bx lr ... 08001110 : * @brief This function handles EXTI interrupt request. * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8001110: b580 push {r7, lr} 8001112: b082 sub sp, #8 8001114: af00 add r7, sp, #0 8001116: 4603 mov r3, r0 8001118: 80fb strh r3, [r7, #6] /* EXTI line interrupt detected */ if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) 800111a: 4b08 ldr r3, [pc, #32] @ (800113c ) 800111c: 695a ldr r2, [r3, #20] 800111e: 88fb ldrh r3, [r7, #6] 8001120: 4013 ands r3, r2 8001122: 2b00 cmp r3, #0 8001124: d006 beq.n 8001134 { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); 8001126: 4a05 ldr r2, [pc, #20] @ (800113c ) 8001128: 88fb ldrh r3, [r7, #6] 800112a: 6153 str r3, [r2, #20] HAL_GPIO_EXTI_Callback(GPIO_Pin); 800112c: 88fb ldrh r3, [r7, #6] 800112e: 4618 mov r0, r3 8001130: f7ff fbbc bl 80008ac } } 8001134: bf00 nop 8001136: 3708 adds r7, #8 8001138: 46bd mov sp, r7 800113a: bd80 pop {r7, pc} 800113c: 40013c00 .word 0x40013c00 08001140 : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8001140: b580 push {r7, lr} 8001142: b086 sub sp, #24 8001144: af00 add r7, sp, #0 8001146: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8001148: 687b ldr r3, [r7, #4] 800114a: 2b00 cmp r3, #0 800114c: d101 bne.n 8001152 { return HAL_ERROR; 800114e: 2301 movs r3, #1 8001150: e267 b.n 8001622 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8001152: 687b ldr r3, [r7, #4] 8001154: 681b ldr r3, [r3, #0] 8001156: f003 0301 and.w r3, r3, #1 800115a: 2b00 cmp r3, #0 800115c: d075 beq.n 800124a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 800115e: 4b88 ldr r3, [pc, #544] @ (8001380 ) 8001160: 689b ldr r3, [r3, #8] 8001162: f003 030c and.w r3, r3, #12 8001166: 2b04 cmp r3, #4 8001168: d00c beq.n 8001184 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800116a: 4b85 ldr r3, [pc, #532] @ (8001380 ) 800116c: 689b ldr r3, [r3, #8] 800116e: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 8001172: 2b08 cmp r3, #8 8001174: d112 bne.n 800119c ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 8001176: 4b82 ldr r3, [pc, #520] @ (8001380 ) 8001178: 685b ldr r3, [r3, #4] 800117a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800117e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8001182: d10b bne.n 800119c { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001184: 4b7e ldr r3, [pc, #504] @ (8001380 ) 8001186: 681b ldr r3, [r3, #0] 8001188: f403 3300 and.w r3, r3, #131072 @ 0x20000 800118c: 2b00 cmp r3, #0 800118e: d05b beq.n 8001248 8001190: 687b ldr r3, [r7, #4] 8001192: 685b ldr r3, [r3, #4] 8001194: 2b00 cmp r3, #0 8001196: d157 bne.n 8001248 { return HAL_ERROR; 8001198: 2301 movs r3, #1 800119a: e242 b.n 8001622 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 800119c: 687b ldr r3, [r7, #4] 800119e: 685b ldr r3, [r3, #4] 80011a0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80011a4: d106 bne.n 80011b4 80011a6: 4b76 ldr r3, [pc, #472] @ (8001380 ) 80011a8: 681b ldr r3, [r3, #0] 80011aa: 4a75 ldr r2, [pc, #468] @ (8001380 ) 80011ac: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80011b0: 6013 str r3, [r2, #0] 80011b2: e01d b.n 80011f0 80011b4: 687b ldr r3, [r7, #4] 80011b6: 685b ldr r3, [r3, #4] 80011b8: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80011bc: d10c bne.n 80011d8 80011be: 4b70 ldr r3, [pc, #448] @ (8001380 ) 80011c0: 681b ldr r3, [r3, #0] 80011c2: 4a6f ldr r2, [pc, #444] @ (8001380 ) 80011c4: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80011c8: 6013 str r3, [r2, #0] 80011ca: 4b6d ldr r3, [pc, #436] @ (8001380 ) 80011cc: 681b ldr r3, [r3, #0] 80011ce: 4a6c ldr r2, [pc, #432] @ (8001380 ) 80011d0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80011d4: 6013 str r3, [r2, #0] 80011d6: e00b b.n 80011f0 80011d8: 4b69 ldr r3, [pc, #420] @ (8001380 ) 80011da: 681b ldr r3, [r3, #0] 80011dc: 4a68 ldr r2, [pc, #416] @ (8001380 ) 80011de: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80011e2: 6013 str r3, [r2, #0] 80011e4: 4b66 ldr r3, [pc, #408] @ (8001380 ) 80011e6: 681b ldr r3, [r3, #0] 80011e8: 4a65 ldr r2, [pc, #404] @ (8001380 ) 80011ea: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80011ee: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 80011f0: 687b ldr r3, [r7, #4] 80011f2: 685b ldr r3, [r3, #4] 80011f4: 2b00 cmp r3, #0 80011f6: d013 beq.n 8001220 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80011f8: f7ff fcd6 bl 8000ba8 80011fc: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80011fe: e008 b.n 8001212 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001200: f7ff fcd2 bl 8000ba8 8001204: 4602 mov r2, r0 8001206: 693b ldr r3, [r7, #16] 8001208: 1ad3 subs r3, r2, r3 800120a: 2b64 cmp r3, #100 @ 0x64 800120c: d901 bls.n 8001212 { return HAL_TIMEOUT; 800120e: 2303 movs r3, #3 8001210: e207 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8001212: 4b5b ldr r3, [pc, #364] @ (8001380 ) 8001214: 681b ldr r3, [r3, #0] 8001216: f403 3300 and.w r3, r3, #131072 @ 0x20000 800121a: 2b00 cmp r3, #0 800121c: d0f0 beq.n 8001200 800121e: e014 b.n 800124a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001220: f7ff fcc2 bl 8000ba8 8001224: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8001226: e008 b.n 800123a { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8001228: f7ff fcbe bl 8000ba8 800122c: 4602 mov r2, r0 800122e: 693b ldr r3, [r7, #16] 8001230: 1ad3 subs r3, r2, r3 8001232: 2b64 cmp r3, #100 @ 0x64 8001234: d901 bls.n 800123a { return HAL_TIMEOUT; 8001236: 2303 movs r3, #3 8001238: e1f3 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800123a: 4b51 ldr r3, [pc, #324] @ (8001380 ) 800123c: 681b ldr r3, [r3, #0] 800123e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001242: 2b00 cmp r3, #0 8001244: d1f0 bne.n 8001228 8001246: e000 b.n 800124a if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8001248: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800124a: 687b ldr r3, [r7, #4] 800124c: 681b ldr r3, [r3, #0] 800124e: f003 0302 and.w r3, r3, #2 8001252: 2b00 cmp r3, #0 8001254: d063 beq.n 800131e /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 8001256: 4b4a ldr r3, [pc, #296] @ (8001380 ) 8001258: 689b ldr r3, [r3, #8] 800125a: f003 030c and.w r3, r3, #12 800125e: 2b00 cmp r3, #0 8001260: d00b beq.n 800127a ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8001262: 4b47 ldr r3, [pc, #284] @ (8001380 ) 8001264: 689b ldr r3, [r3, #8] 8001266: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 800126a: 2b08 cmp r3, #8 800126c: d11c bne.n 80012a8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800126e: 4b44 ldr r3, [pc, #272] @ (8001380 ) 8001270: 685b ldr r3, [r3, #4] 8001272: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8001276: 2b00 cmp r3, #0 8001278: d116 bne.n 80012a8 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800127a: 4b41 ldr r3, [pc, #260] @ (8001380 ) 800127c: 681b ldr r3, [r3, #0] 800127e: f003 0302 and.w r3, r3, #2 8001282: 2b00 cmp r3, #0 8001284: d005 beq.n 8001292 8001286: 687b ldr r3, [r7, #4] 8001288: 68db ldr r3, [r3, #12] 800128a: 2b01 cmp r3, #1 800128c: d001 beq.n 8001292 { return HAL_ERROR; 800128e: 2301 movs r3, #1 8001290: e1c7 b.n 8001622 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8001292: 4b3b ldr r3, [pc, #236] @ (8001380 ) 8001294: 681b ldr r3, [r3, #0] 8001296: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800129a: 687b ldr r3, [r7, #4] 800129c: 691b ldr r3, [r3, #16] 800129e: 00db lsls r3, r3, #3 80012a0: 4937 ldr r1, [pc, #220] @ (8001380 ) 80012a2: 4313 orrs r3, r2 80012a4: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80012a6: e03a b.n 800131e } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 80012a8: 687b ldr r3, [r7, #4] 80012aa: 68db ldr r3, [r3, #12] 80012ac: 2b00 cmp r3, #0 80012ae: d020 beq.n 80012f2 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80012b0: 4b34 ldr r3, [pc, #208] @ (8001384 ) 80012b2: 2201 movs r2, #1 80012b4: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80012b6: f7ff fc77 bl 8000ba8 80012ba: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80012bc: e008 b.n 80012d0 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80012be: f7ff fc73 bl 8000ba8 80012c2: 4602 mov r2, r0 80012c4: 693b ldr r3, [r7, #16] 80012c6: 1ad3 subs r3, r2, r3 80012c8: 2b02 cmp r3, #2 80012ca: d901 bls.n 80012d0 { return HAL_TIMEOUT; 80012cc: 2303 movs r3, #3 80012ce: e1a8 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80012d0: 4b2b ldr r3, [pc, #172] @ (8001380 ) 80012d2: 681b ldr r3, [r3, #0] 80012d4: f003 0302 and.w r3, r3, #2 80012d8: 2b00 cmp r3, #0 80012da: d0f0 beq.n 80012be } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80012dc: 4b28 ldr r3, [pc, #160] @ (8001380 ) 80012de: 681b ldr r3, [r3, #0] 80012e0: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80012e4: 687b ldr r3, [r7, #4] 80012e6: 691b ldr r3, [r3, #16] 80012e8: 00db lsls r3, r3, #3 80012ea: 4925 ldr r1, [pc, #148] @ (8001380 ) 80012ec: 4313 orrs r3, r2 80012ee: 600b str r3, [r1, #0] 80012f0: e015 b.n 800131e } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80012f2: 4b24 ldr r3, [pc, #144] @ (8001384 ) 80012f4: 2200 movs r2, #0 80012f6: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80012f8: f7ff fc56 bl 8000ba8 80012fc: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80012fe: e008 b.n 8001312 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8001300: f7ff fc52 bl 8000ba8 8001304: 4602 mov r2, r0 8001306: 693b ldr r3, [r7, #16] 8001308: 1ad3 subs r3, r2, r3 800130a: 2b02 cmp r3, #2 800130c: d901 bls.n 8001312 { return HAL_TIMEOUT; 800130e: 2303 movs r3, #3 8001310: e187 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8001312: 4b1b ldr r3, [pc, #108] @ (8001380 ) 8001314: 681b ldr r3, [r3, #0] 8001316: f003 0302 and.w r3, r3, #2 800131a: 2b00 cmp r3, #0 800131c: d1f0 bne.n 8001300 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800131e: 687b ldr r3, [r7, #4] 8001320: 681b ldr r3, [r3, #0] 8001322: f003 0308 and.w r3, r3, #8 8001326: 2b00 cmp r3, #0 8001328: d036 beq.n 8001398 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800132a: 687b ldr r3, [r7, #4] 800132c: 695b ldr r3, [r3, #20] 800132e: 2b00 cmp r3, #0 8001330: d016 beq.n 8001360 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8001332: 4b15 ldr r3, [pc, #84] @ (8001388 ) 8001334: 2201 movs r2, #1 8001336: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001338: f7ff fc36 bl 8000ba8 800133c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800133e: e008 b.n 8001352 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8001340: f7ff fc32 bl 8000ba8 8001344: 4602 mov r2, r0 8001346: 693b ldr r3, [r7, #16] 8001348: 1ad3 subs r3, r2, r3 800134a: 2b02 cmp r3, #2 800134c: d901 bls.n 8001352 { return HAL_TIMEOUT; 800134e: 2303 movs r3, #3 8001350: e167 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8001352: 4b0b ldr r3, [pc, #44] @ (8001380 ) 8001354: 6f5b ldr r3, [r3, #116] @ 0x74 8001356: f003 0302 and.w r3, r3, #2 800135a: 2b00 cmp r3, #0 800135c: d0f0 beq.n 8001340 800135e: e01b b.n 8001398 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8001360: 4b09 ldr r3, [pc, #36] @ (8001388 ) 8001362: 2200 movs r2, #0 8001364: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001366: f7ff fc1f bl 8000ba8 800136a: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800136c: e00e b.n 800138c { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800136e: f7ff fc1b bl 8000ba8 8001372: 4602 mov r2, r0 8001374: 693b ldr r3, [r7, #16] 8001376: 1ad3 subs r3, r2, r3 8001378: 2b02 cmp r3, #2 800137a: d907 bls.n 800138c { return HAL_TIMEOUT; 800137c: 2303 movs r3, #3 800137e: e150 b.n 8001622 8001380: 40023800 .word 0x40023800 8001384: 42470000 .word 0x42470000 8001388: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 800138c: 4b88 ldr r3, [pc, #544] @ (80015b0 ) 800138e: 6f5b ldr r3, [r3, #116] @ 0x74 8001390: f003 0302 and.w r3, r3, #2 8001394: 2b00 cmp r3, #0 8001396: d1ea bne.n 800136e } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8001398: 687b ldr r3, [r7, #4] 800139a: 681b ldr r3, [r3, #0] 800139c: f003 0304 and.w r3, r3, #4 80013a0: 2b00 cmp r3, #0 80013a2: f000 8097 beq.w 80014d4 { FlagStatus pwrclkchanged = RESET; 80013a6: 2300 movs r3, #0 80013a8: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80013aa: 4b81 ldr r3, [pc, #516] @ (80015b0 ) 80013ac: 6c1b ldr r3, [r3, #64] @ 0x40 80013ae: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80013b2: 2b00 cmp r3, #0 80013b4: d10f bne.n 80013d6 { __HAL_RCC_PWR_CLK_ENABLE(); 80013b6: 2300 movs r3, #0 80013b8: 60bb str r3, [r7, #8] 80013ba: 4b7d ldr r3, [pc, #500] @ (80015b0 ) 80013bc: 6c1b ldr r3, [r3, #64] @ 0x40 80013be: 4a7c ldr r2, [pc, #496] @ (80015b0 ) 80013c0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80013c4: 6413 str r3, [r2, #64] @ 0x40 80013c6: 4b7a ldr r3, [pc, #488] @ (80015b0 ) 80013c8: 6c1b ldr r3, [r3, #64] @ 0x40 80013ca: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80013ce: 60bb str r3, [r7, #8] 80013d0: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80013d2: 2301 movs r3, #1 80013d4: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80013d6: 4b77 ldr r3, [pc, #476] @ (80015b4 ) 80013d8: 681b ldr r3, [r3, #0] 80013da: f403 7380 and.w r3, r3, #256 @ 0x100 80013de: 2b00 cmp r3, #0 80013e0: d118 bne.n 8001414 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80013e2: 4b74 ldr r3, [pc, #464] @ (80015b4 ) 80013e4: 681b ldr r3, [r3, #0] 80013e6: 4a73 ldr r2, [pc, #460] @ (80015b4 ) 80013e8: f443 7380 orr.w r3, r3, #256 @ 0x100 80013ec: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80013ee: f7ff fbdb bl 8000ba8 80013f2: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80013f4: e008 b.n 8001408 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80013f6: f7ff fbd7 bl 8000ba8 80013fa: 4602 mov r2, r0 80013fc: 693b ldr r3, [r7, #16] 80013fe: 1ad3 subs r3, r2, r3 8001400: 2b02 cmp r3, #2 8001402: d901 bls.n 8001408 { return HAL_TIMEOUT; 8001404: 2303 movs r3, #3 8001406: e10c b.n 8001622 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8001408: 4b6a ldr r3, [pc, #424] @ (80015b4 ) 800140a: 681b ldr r3, [r3, #0] 800140c: f403 7380 and.w r3, r3, #256 @ 0x100 8001410: 2b00 cmp r3, #0 8001412: d0f0 beq.n 80013f6 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8001414: 687b ldr r3, [r7, #4] 8001416: 689b ldr r3, [r3, #8] 8001418: 2b01 cmp r3, #1 800141a: d106 bne.n 800142a 800141c: 4b64 ldr r3, [pc, #400] @ (80015b0 ) 800141e: 6f1b ldr r3, [r3, #112] @ 0x70 8001420: 4a63 ldr r2, [pc, #396] @ (80015b0 ) 8001422: f043 0301 orr.w r3, r3, #1 8001426: 6713 str r3, [r2, #112] @ 0x70 8001428: e01c b.n 8001464 800142a: 687b ldr r3, [r7, #4] 800142c: 689b ldr r3, [r3, #8] 800142e: 2b05 cmp r3, #5 8001430: d10c bne.n 800144c 8001432: 4b5f ldr r3, [pc, #380] @ (80015b0 ) 8001434: 6f1b ldr r3, [r3, #112] @ 0x70 8001436: 4a5e ldr r2, [pc, #376] @ (80015b0 ) 8001438: f043 0304 orr.w r3, r3, #4 800143c: 6713 str r3, [r2, #112] @ 0x70 800143e: 4b5c ldr r3, [pc, #368] @ (80015b0 ) 8001440: 6f1b ldr r3, [r3, #112] @ 0x70 8001442: 4a5b ldr r2, [pc, #364] @ (80015b0 ) 8001444: f043 0301 orr.w r3, r3, #1 8001448: 6713 str r3, [r2, #112] @ 0x70 800144a: e00b b.n 8001464 800144c: 4b58 ldr r3, [pc, #352] @ (80015b0 ) 800144e: 6f1b ldr r3, [r3, #112] @ 0x70 8001450: 4a57 ldr r2, [pc, #348] @ (80015b0 ) 8001452: f023 0301 bic.w r3, r3, #1 8001456: 6713 str r3, [r2, #112] @ 0x70 8001458: 4b55 ldr r3, [pc, #340] @ (80015b0 ) 800145a: 6f1b ldr r3, [r3, #112] @ 0x70 800145c: 4a54 ldr r2, [pc, #336] @ (80015b0 ) 800145e: f023 0304 bic.w r3, r3, #4 8001462: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8001464: 687b ldr r3, [r7, #4] 8001466: 689b ldr r3, [r3, #8] 8001468: 2b00 cmp r3, #0 800146a: d015 beq.n 8001498 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 800146c: f7ff fb9c bl 8000ba8 8001470: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8001472: e00a b.n 800148a { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8001474: f7ff fb98 bl 8000ba8 8001478: 4602 mov r2, r0 800147a: 693b ldr r3, [r7, #16] 800147c: 1ad3 subs r3, r2, r3 800147e: f241 3288 movw r2, #5000 @ 0x1388 8001482: 4293 cmp r3, r2 8001484: d901 bls.n 800148a { return HAL_TIMEOUT; 8001486: 2303 movs r3, #3 8001488: e0cb b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800148a: 4b49 ldr r3, [pc, #292] @ (80015b0 ) 800148c: 6f1b ldr r3, [r3, #112] @ 0x70 800148e: f003 0302 and.w r3, r3, #2 8001492: 2b00 cmp r3, #0 8001494: d0ee beq.n 8001474 8001496: e014 b.n 80014c2 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8001498: f7ff fb86 bl 8000ba8 800149c: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 800149e: e00a b.n 80014b6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80014a0: f7ff fb82 bl 8000ba8 80014a4: 4602 mov r2, r0 80014a6: 693b ldr r3, [r7, #16] 80014a8: 1ad3 subs r3, r2, r3 80014aa: f241 3288 movw r2, #5000 @ 0x1388 80014ae: 4293 cmp r3, r2 80014b0: d901 bls.n 80014b6 { return HAL_TIMEOUT; 80014b2: 2303 movs r3, #3 80014b4: e0b5 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80014b6: 4b3e ldr r3, [pc, #248] @ (80015b0 ) 80014b8: 6f1b ldr r3, [r3, #112] @ 0x70 80014ba: f003 0302 and.w r3, r3, #2 80014be: 2b00 cmp r3, #0 80014c0: d1ee bne.n 80014a0 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80014c2: 7dfb ldrb r3, [r7, #23] 80014c4: 2b01 cmp r3, #1 80014c6: d105 bne.n 80014d4 { __HAL_RCC_PWR_CLK_DISABLE(); 80014c8: 4b39 ldr r3, [pc, #228] @ (80015b0 ) 80014ca: 6c1b ldr r3, [r3, #64] @ 0x40 80014cc: 4a38 ldr r2, [pc, #224] @ (80015b0 ) 80014ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80014d2: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80014d4: 687b ldr r3, [r7, #4] 80014d6: 699b ldr r3, [r3, #24] 80014d8: 2b00 cmp r3, #0 80014da: f000 80a1 beq.w 8001620 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80014de: 4b34 ldr r3, [pc, #208] @ (80015b0 ) 80014e0: 689b ldr r3, [r3, #8] 80014e2: f003 030c and.w r3, r3, #12 80014e6: 2b08 cmp r3, #8 80014e8: d05c beq.n 80015a4 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80014ea: 687b ldr r3, [r7, #4] 80014ec: 699b ldr r3, [r3, #24] 80014ee: 2b02 cmp r3, #2 80014f0: d141 bne.n 8001576 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80014f2: 4b31 ldr r3, [pc, #196] @ (80015b8 ) 80014f4: 2200 movs r2, #0 80014f6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80014f8: f7ff fb56 bl 8000ba8 80014fc: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80014fe: e008 b.n 8001512 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001500: f7ff fb52 bl 8000ba8 8001504: 4602 mov r2, r0 8001506: 693b ldr r3, [r7, #16] 8001508: 1ad3 subs r3, r2, r3 800150a: 2b02 cmp r3, #2 800150c: d901 bls.n 8001512 { return HAL_TIMEOUT; 800150e: 2303 movs r3, #3 8001510: e087 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001512: 4b27 ldr r3, [pc, #156] @ (80015b0 ) 8001514: 681b ldr r3, [r3, #0] 8001516: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800151a: 2b00 cmp r3, #0 800151c: d1f0 bne.n 8001500 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800151e: 687b ldr r3, [r7, #4] 8001520: 69da ldr r2, [r3, #28] 8001522: 687b ldr r3, [r7, #4] 8001524: 6a1b ldr r3, [r3, #32] 8001526: 431a orrs r2, r3 8001528: 687b ldr r3, [r7, #4] 800152a: 6a5b ldr r3, [r3, #36] @ 0x24 800152c: 019b lsls r3, r3, #6 800152e: 431a orrs r2, r3 8001530: 687b ldr r3, [r7, #4] 8001532: 6a9b ldr r3, [r3, #40] @ 0x28 8001534: 085b lsrs r3, r3, #1 8001536: 3b01 subs r3, #1 8001538: 041b lsls r3, r3, #16 800153a: 431a orrs r2, r3 800153c: 687b ldr r3, [r7, #4] 800153e: 6adb ldr r3, [r3, #44] @ 0x2c 8001540: 061b lsls r3, r3, #24 8001542: 491b ldr r1, [pc, #108] @ (80015b0 ) 8001544: 4313 orrs r3, r2 8001546: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8001548: 4b1b ldr r3, [pc, #108] @ (80015b8 ) 800154a: 2201 movs r2, #1 800154c: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800154e: f7ff fb2b bl 8000ba8 8001552: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001554: e008 b.n 8001568 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001556: f7ff fb27 bl 8000ba8 800155a: 4602 mov r2, r0 800155c: 693b ldr r3, [r7, #16] 800155e: 1ad3 subs r3, r2, r3 8001560: 2b02 cmp r3, #2 8001562: d901 bls.n 8001568 { return HAL_TIMEOUT; 8001564: 2303 movs r3, #3 8001566: e05c b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8001568: 4b11 ldr r3, [pc, #68] @ (80015b0 ) 800156a: 681b ldr r3, [r3, #0] 800156c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8001570: 2b00 cmp r3, #0 8001572: d0f0 beq.n 8001556 8001574: e054 b.n 8001620 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8001576: 4b10 ldr r3, [pc, #64] @ (80015b8 ) 8001578: 2200 movs r2, #0 800157a: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800157c: f7ff fb14 bl 8000ba8 8001580: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001582: e008 b.n 8001596 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8001584: f7ff fb10 bl 8000ba8 8001588: 4602 mov r2, r0 800158a: 693b ldr r3, [r7, #16] 800158c: 1ad3 subs r3, r2, r3 800158e: 2b02 cmp r3, #2 8001590: d901 bls.n 8001596 { return HAL_TIMEOUT; 8001592: 2303 movs r3, #3 8001594: e045 b.n 8001622 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8001596: 4b06 ldr r3, [pc, #24] @ (80015b0 ) 8001598: 681b ldr r3, [r3, #0] 800159a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800159e: 2b00 cmp r3, #0 80015a0: d1f0 bne.n 8001584 80015a2: e03d b.n 8001620 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80015a4: 687b ldr r3, [r7, #4] 80015a6: 699b ldr r3, [r3, #24] 80015a8: 2b01 cmp r3, #1 80015aa: d107 bne.n 80015bc { return HAL_ERROR; 80015ac: 2301 movs r3, #1 80015ae: e038 b.n 8001622 80015b0: 40023800 .word 0x40023800 80015b4: 40007000 .word 0x40007000 80015b8: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80015bc: 4b1b ldr r3, [pc, #108] @ (800162c ) 80015be: 685b ldr r3, [r3, #4] 80015c0: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80015c2: 687b ldr r3, [r7, #4] 80015c4: 699b ldr r3, [r3, #24] 80015c6: 2b01 cmp r3, #1 80015c8: d028 beq.n 800161c (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80015ca: 68fb ldr r3, [r7, #12] 80015cc: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80015d0: 687b ldr r3, [r7, #4] 80015d2: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80015d4: 429a cmp r2, r3 80015d6: d121 bne.n 800161c (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80015d8: 68fb ldr r3, [r7, #12] 80015da: f003 023f and.w r2, r3, #63 @ 0x3f 80015de: 687b ldr r3, [r7, #4] 80015e0: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80015e2: 429a cmp r2, r3 80015e4: d11a bne.n 800161c (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80015e6: 68fa ldr r2, [r7, #12] 80015e8: f647 73c0 movw r3, #32704 @ 0x7fc0 80015ec: 4013 ands r3, r2 80015ee: 687a ldr r2, [r7, #4] 80015f0: 6a52 ldr r2, [r2, #36] @ 0x24 80015f2: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80015f4: 4293 cmp r3, r2 80015f6: d111 bne.n 800161c (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80015f8: 68fb ldr r3, [r7, #12] 80015fa: f403 3240 and.w r2, r3, #196608 @ 0x30000 80015fe: 687b ldr r3, [r7, #4] 8001600: 6a9b ldr r3, [r3, #40] @ 0x28 8001602: 085b lsrs r3, r3, #1 8001604: 3b01 subs r3, #1 8001606: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8001608: 429a cmp r2, r3 800160a: d107 bne.n 800161c (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) 800160c: 68fb ldr r3, [r7, #12] 800160e: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8001612: 687b ldr r3, [r7, #4] 8001614: 6adb ldr r3, [r3, #44] @ 0x2c 8001616: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8001618: 429a cmp r2, r3 800161a: d001 beq.n 8001620 #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 800161c: 2301 movs r3, #1 800161e: e000 b.n 8001622 } } } } return HAL_OK; 8001620: 2300 movs r3, #0 } 8001622: 4618 mov r0, r3 8001624: 3718 adds r7, #24 8001626: 46bd mov sp, r7 8001628: bd80 pop {r7, pc} 800162a: bf00 nop 800162c: 40023800 .word 0x40023800 08001630 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8001630: b580 push {r7, lr} 8001632: b084 sub sp, #16 8001634: af00 add r7, sp, #0 8001636: 6078 str r0, [r7, #4] 8001638: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 800163a: 687b ldr r3, [r7, #4] 800163c: 2b00 cmp r3, #0 800163e: d101 bne.n 8001644 { return HAL_ERROR; 8001640: 2301 movs r3, #1 8001642: e0cc b.n 80017de /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8001644: 4b68 ldr r3, [pc, #416] @ (80017e8 ) 8001646: 681b ldr r3, [r3, #0] 8001648: f003 030f and.w r3, r3, #15 800164c: 683a ldr r2, [r7, #0] 800164e: 429a cmp r2, r3 8001650: d90c bls.n 800166c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001652: 4b65 ldr r3, [pc, #404] @ (80017e8 ) 8001654: 683a ldr r2, [r7, #0] 8001656: b2d2 uxtb r2, r2 8001658: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 800165a: 4b63 ldr r3, [pc, #396] @ (80017e8 ) 800165c: 681b ldr r3, [r3, #0] 800165e: f003 030f and.w r3, r3, #15 8001662: 683a ldr r2, [r7, #0] 8001664: 429a cmp r2, r3 8001666: d001 beq.n 800166c { return HAL_ERROR; 8001668: 2301 movs r3, #1 800166a: e0b8 b.n 80017de } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 800166c: 687b ldr r3, [r7, #4] 800166e: 681b ldr r3, [r3, #0] 8001670: f003 0302 and.w r3, r3, #2 8001674: 2b00 cmp r3, #0 8001676: d020 beq.n 80016ba { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001678: 687b ldr r3, [r7, #4] 800167a: 681b ldr r3, [r3, #0] 800167c: f003 0304 and.w r3, r3, #4 8001680: 2b00 cmp r3, #0 8001682: d005 beq.n 8001690 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8001684: 4b59 ldr r3, [pc, #356] @ (80017ec ) 8001686: 689b ldr r3, [r3, #8] 8001688: 4a58 ldr r2, [pc, #352] @ (80017ec ) 800168a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 800168e: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8001690: 687b ldr r3, [r7, #4] 8001692: 681b ldr r3, [r3, #0] 8001694: f003 0308 and.w r3, r3, #8 8001698: 2b00 cmp r3, #0 800169a: d005 beq.n 80016a8 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 800169c: 4b53 ldr r3, [pc, #332] @ (80017ec ) 800169e: 689b ldr r3, [r3, #8] 80016a0: 4a52 ldr r2, [pc, #328] @ (80017ec ) 80016a2: f443 4360 orr.w r3, r3, #57344 @ 0xe000 80016a6: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80016a8: 4b50 ldr r3, [pc, #320] @ (80017ec ) 80016aa: 689b ldr r3, [r3, #8] 80016ac: f023 02f0 bic.w r2, r3, #240 @ 0xf0 80016b0: 687b ldr r3, [r7, #4] 80016b2: 689b ldr r3, [r3, #8] 80016b4: 494d ldr r1, [pc, #308] @ (80017ec ) 80016b6: 4313 orrs r3, r2 80016b8: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80016ba: 687b ldr r3, [r7, #4] 80016bc: 681b ldr r3, [r3, #0] 80016be: f003 0301 and.w r3, r3, #1 80016c2: 2b00 cmp r3, #0 80016c4: d044 beq.n 8001750 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80016c6: 687b ldr r3, [r7, #4] 80016c8: 685b ldr r3, [r3, #4] 80016ca: 2b01 cmp r3, #1 80016cc: d107 bne.n 80016de { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80016ce: 4b47 ldr r3, [pc, #284] @ (80017ec ) 80016d0: 681b ldr r3, [r3, #0] 80016d2: f403 3300 and.w r3, r3, #131072 @ 0x20000 80016d6: 2b00 cmp r3, #0 80016d8: d119 bne.n 800170e { return HAL_ERROR; 80016da: 2301 movs r3, #1 80016dc: e07f b.n 80017de } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80016de: 687b ldr r3, [r7, #4] 80016e0: 685b ldr r3, [r3, #4] 80016e2: 2b02 cmp r3, #2 80016e4: d003 beq.n 80016ee (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 80016e6: 687b ldr r3, [r7, #4] 80016e8: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 80016ea: 2b03 cmp r3, #3 80016ec: d107 bne.n 80016fe { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80016ee: 4b3f ldr r3, [pc, #252] @ (80017ec ) 80016f0: 681b ldr r3, [r3, #0] 80016f2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80016f6: 2b00 cmp r3, #0 80016f8: d109 bne.n 800170e { return HAL_ERROR; 80016fa: 2301 movs r3, #1 80016fc: e06f b.n 80017de } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80016fe: 4b3b ldr r3, [pc, #236] @ (80017ec ) 8001700: 681b ldr r3, [r3, #0] 8001702: f003 0302 and.w r3, r3, #2 8001706: 2b00 cmp r3, #0 8001708: d101 bne.n 800170e { return HAL_ERROR; 800170a: 2301 movs r3, #1 800170c: e067 b.n 80017de } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 800170e: 4b37 ldr r3, [pc, #220] @ (80017ec ) 8001710: 689b ldr r3, [r3, #8] 8001712: f023 0203 bic.w r2, r3, #3 8001716: 687b ldr r3, [r7, #4] 8001718: 685b ldr r3, [r3, #4] 800171a: 4934 ldr r1, [pc, #208] @ (80017ec ) 800171c: 4313 orrs r3, r2 800171e: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8001720: f7ff fa42 bl 8000ba8 8001724: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8001726: e00a b.n 800173e { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001728: f7ff fa3e bl 8000ba8 800172c: 4602 mov r2, r0 800172e: 68fb ldr r3, [r7, #12] 8001730: 1ad3 subs r3, r2, r3 8001732: f241 3288 movw r2, #5000 @ 0x1388 8001736: 4293 cmp r3, r2 8001738: d901 bls.n 800173e { return HAL_TIMEOUT; 800173a: 2303 movs r3, #3 800173c: e04f b.n 80017de while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800173e: 4b2b ldr r3, [pc, #172] @ (80017ec ) 8001740: 689b ldr r3, [r3, #8] 8001742: f003 020c and.w r2, r3, #12 8001746: 687b ldr r3, [r7, #4] 8001748: 685b ldr r3, [r3, #4] 800174a: 009b lsls r3, r3, #2 800174c: 429a cmp r2, r3 800174e: d1eb bne.n 8001728 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8001750: 4b25 ldr r3, [pc, #148] @ (80017e8 ) 8001752: 681b ldr r3, [r3, #0] 8001754: f003 030f and.w r3, r3, #15 8001758: 683a ldr r2, [r7, #0] 800175a: 429a cmp r2, r3 800175c: d20c bcs.n 8001778 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 800175e: 4b22 ldr r3, [pc, #136] @ (80017e8 ) 8001760: 683a ldr r2, [r7, #0] 8001762: b2d2 uxtb r2, r2 8001764: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8001766: 4b20 ldr r3, [pc, #128] @ (80017e8 ) 8001768: 681b ldr r3, [r3, #0] 800176a: f003 030f and.w r3, r3, #15 800176e: 683a ldr r2, [r7, #0] 8001770: 429a cmp r2, r3 8001772: d001 beq.n 8001778 { return HAL_ERROR; 8001774: 2301 movs r3, #1 8001776: e032 b.n 80017de } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001778: 687b ldr r3, [r7, #4] 800177a: 681b ldr r3, [r3, #0] 800177c: f003 0304 and.w r3, r3, #4 8001780: 2b00 cmp r3, #0 8001782: d008 beq.n 8001796 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8001784: 4b19 ldr r3, [pc, #100] @ (80017ec ) 8001786: 689b ldr r3, [r3, #8] 8001788: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 800178c: 687b ldr r3, [r7, #4] 800178e: 68db ldr r3, [r3, #12] 8001790: 4916 ldr r1, [pc, #88] @ (80017ec ) 8001792: 4313 orrs r3, r2 8001794: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8001796: 687b ldr r3, [r7, #4] 8001798: 681b ldr r3, [r3, #0] 800179a: f003 0308 and.w r3, r3, #8 800179e: 2b00 cmp r3, #0 80017a0: d009 beq.n 80017b6 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 80017a2: 4b12 ldr r3, [pc, #72] @ (80017ec ) 80017a4: 689b ldr r3, [r3, #8] 80017a6: f423 4260 bic.w r2, r3, #57344 @ 0xe000 80017aa: 687b ldr r3, [r7, #4] 80017ac: 691b ldr r3, [r3, #16] 80017ae: 00db lsls r3, r3, #3 80017b0: 490e ldr r1, [pc, #56] @ (80017ec ) 80017b2: 4313 orrs r3, r2 80017b4: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 80017b6: f000 f821 bl 80017fc 80017ba: 4602 mov r2, r0 80017bc: 4b0b ldr r3, [pc, #44] @ (80017ec ) 80017be: 689b ldr r3, [r3, #8] 80017c0: 091b lsrs r3, r3, #4 80017c2: f003 030f and.w r3, r3, #15 80017c6: 490a ldr r1, [pc, #40] @ (80017f0 ) 80017c8: 5ccb ldrb r3, [r1, r3] 80017ca: fa22 f303 lsr.w r3, r2, r3 80017ce: 4a09 ldr r2, [pc, #36] @ (80017f4 ) 80017d0: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 80017d2: 4b09 ldr r3, [pc, #36] @ (80017f8 ) 80017d4: 681b ldr r3, [r3, #0] 80017d6: 4618 mov r0, r3 80017d8: f7ff f8de bl 8000998 return HAL_OK; 80017dc: 2300 movs r3, #0 } 80017de: 4618 mov r0, r3 80017e0: 3710 adds r7, #16 80017e2: 46bd mov sp, r7 80017e4: bd80 pop {r7, pc} 80017e6: bf00 nop 80017e8: 40023c00 .word 0x40023c00 80017ec: 40023800 .word 0x40023800 80017f0: 0800248c .word 0x0800248c 80017f4: 20000004 .word 0x20000004 80017f8: 20000008 .word 0x20000008 080017fc : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { 80017fc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8001800: b094 sub sp, #80 @ 0x50 8001802: af00 add r7, sp, #0 uint32_t pllm = 0U; 8001804: 2300 movs r3, #0 8001806: 647b str r3, [r7, #68] @ 0x44 uint32_t pllvco = 0U; 8001808: 2300 movs r3, #0 800180a: 64fb str r3, [r7, #76] @ 0x4c uint32_t pllp = 0U; 800180c: 2300 movs r3, #0 800180e: 643b str r3, [r7, #64] @ 0x40 uint32_t sysclockfreq = 0U; 8001810: 2300 movs r3, #0 8001812: 64bb str r3, [r7, #72] @ 0x48 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8001814: 4b79 ldr r3, [pc, #484] @ (80019fc ) 8001816: 689b ldr r3, [r3, #8] 8001818: f003 030c and.w r3, r3, #12 800181c: 2b08 cmp r3, #8 800181e: d00d beq.n 800183c 8001820: 2b08 cmp r3, #8 8001822: f200 80e1 bhi.w 80019e8 8001826: 2b00 cmp r3, #0 8001828: d002 beq.n 8001830 800182a: 2b04 cmp r3, #4 800182c: d003 beq.n 8001836 800182e: e0db b.n 80019e8 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8001830: 4b73 ldr r3, [pc, #460] @ (8001a00 ) 8001832: 64bb str r3, [r7, #72] @ 0x48 break; 8001834: e0db b.n 80019ee } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8001836: 4b73 ldr r3, [pc, #460] @ (8001a04 ) 8001838: 64bb str r3, [r7, #72] @ 0x48 break; 800183a: e0d8 b.n 80019ee } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 800183c: 4b6f ldr r3, [pc, #444] @ (80019fc ) 800183e: 685b ldr r3, [r3, #4] 8001840: f003 033f and.w r3, r3, #63 @ 0x3f 8001844: 647b str r3, [r7, #68] @ 0x44 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8001846: 4b6d ldr r3, [pc, #436] @ (80019fc ) 8001848: 685b ldr r3, [r3, #4] 800184a: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800184e: 2b00 cmp r3, #0 8001850: d063 beq.n 800191a { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8001852: 4b6a ldr r3, [pc, #424] @ (80019fc ) 8001854: 685b ldr r3, [r3, #4] 8001856: 099b lsrs r3, r3, #6 8001858: 2200 movs r2, #0 800185a: 63bb str r3, [r7, #56] @ 0x38 800185c: 63fa str r2, [r7, #60] @ 0x3c 800185e: 6bbb ldr r3, [r7, #56] @ 0x38 8001860: f3c3 0308 ubfx r3, r3, #0, #9 8001864: 633b str r3, [r7, #48] @ 0x30 8001866: 2300 movs r3, #0 8001868: 637b str r3, [r7, #52] @ 0x34 800186a: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 800186e: 4622 mov r2, r4 8001870: 462b mov r3, r5 8001872: f04f 0000 mov.w r0, #0 8001876: f04f 0100 mov.w r1, #0 800187a: 0159 lsls r1, r3, #5 800187c: ea41 61d2 orr.w r1, r1, r2, lsr #27 8001880: 0150 lsls r0, r2, #5 8001882: 4602 mov r2, r0 8001884: 460b mov r3, r1 8001886: 4621 mov r1, r4 8001888: 1a51 subs r1, r2, r1 800188a: 6139 str r1, [r7, #16] 800188c: 4629 mov r1, r5 800188e: eb63 0301 sbc.w r3, r3, r1 8001892: 617b str r3, [r7, #20] 8001894: f04f 0200 mov.w r2, #0 8001898: f04f 0300 mov.w r3, #0 800189c: e9d7 ab04 ldrd sl, fp, [r7, #16] 80018a0: 4659 mov r1, fp 80018a2: 018b lsls r3, r1, #6 80018a4: 4651 mov r1, sl 80018a6: ea43 6391 orr.w r3, r3, r1, lsr #26 80018aa: 4651 mov r1, sl 80018ac: 018a lsls r2, r1, #6 80018ae: 4651 mov r1, sl 80018b0: ebb2 0801 subs.w r8, r2, r1 80018b4: 4659 mov r1, fp 80018b6: eb63 0901 sbc.w r9, r3, r1 80018ba: f04f 0200 mov.w r2, #0 80018be: f04f 0300 mov.w r3, #0 80018c2: ea4f 03c9 mov.w r3, r9, lsl #3 80018c6: ea43 7358 orr.w r3, r3, r8, lsr #29 80018ca: ea4f 02c8 mov.w r2, r8, lsl #3 80018ce: 4690 mov r8, r2 80018d0: 4699 mov r9, r3 80018d2: 4623 mov r3, r4 80018d4: eb18 0303 adds.w r3, r8, r3 80018d8: 60bb str r3, [r7, #8] 80018da: 462b mov r3, r5 80018dc: eb49 0303 adc.w r3, r9, r3 80018e0: 60fb str r3, [r7, #12] 80018e2: f04f 0200 mov.w r2, #0 80018e6: f04f 0300 mov.w r3, #0 80018ea: e9d7 4502 ldrd r4, r5, [r7, #8] 80018ee: 4629 mov r1, r5 80018f0: 024b lsls r3, r1, #9 80018f2: 4621 mov r1, r4 80018f4: ea43 53d1 orr.w r3, r3, r1, lsr #23 80018f8: 4621 mov r1, r4 80018fa: 024a lsls r2, r1, #9 80018fc: 4610 mov r0, r2 80018fe: 4619 mov r1, r3 8001900: 6c7b ldr r3, [r7, #68] @ 0x44 8001902: 2200 movs r2, #0 8001904: 62bb str r3, [r7, #40] @ 0x28 8001906: 62fa str r2, [r7, #44] @ 0x2c 8001908: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 800190c: f7fe fc70 bl 80001f0 <__aeabi_uldivmod> 8001910: 4602 mov r2, r0 8001912: 460b mov r3, r1 8001914: 4613 mov r3, r2 8001916: 64fb str r3, [r7, #76] @ 0x4c 8001918: e058 b.n 80019cc } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 800191a: 4b38 ldr r3, [pc, #224] @ (80019fc ) 800191c: 685b ldr r3, [r3, #4] 800191e: 099b lsrs r3, r3, #6 8001920: 2200 movs r2, #0 8001922: 4618 mov r0, r3 8001924: 4611 mov r1, r2 8001926: f3c0 0308 ubfx r3, r0, #0, #9 800192a: 623b str r3, [r7, #32] 800192c: 2300 movs r3, #0 800192e: 627b str r3, [r7, #36] @ 0x24 8001930: e9d7 8908 ldrd r8, r9, [r7, #32] 8001934: 4642 mov r2, r8 8001936: 464b mov r3, r9 8001938: f04f 0000 mov.w r0, #0 800193c: f04f 0100 mov.w r1, #0 8001940: 0159 lsls r1, r3, #5 8001942: ea41 61d2 orr.w r1, r1, r2, lsr #27 8001946: 0150 lsls r0, r2, #5 8001948: 4602 mov r2, r0 800194a: 460b mov r3, r1 800194c: 4641 mov r1, r8 800194e: ebb2 0a01 subs.w sl, r2, r1 8001952: 4649 mov r1, r9 8001954: eb63 0b01 sbc.w fp, r3, r1 8001958: f04f 0200 mov.w r2, #0 800195c: f04f 0300 mov.w r3, #0 8001960: ea4f 138b mov.w r3, fp, lsl #6 8001964: ea43 639a orr.w r3, r3, sl, lsr #26 8001968: ea4f 128a mov.w r2, sl, lsl #6 800196c: ebb2 040a subs.w r4, r2, sl 8001970: eb63 050b sbc.w r5, r3, fp 8001974: f04f 0200 mov.w r2, #0 8001978: f04f 0300 mov.w r3, #0 800197c: 00eb lsls r3, r5, #3 800197e: ea43 7354 orr.w r3, r3, r4, lsr #29 8001982: 00e2 lsls r2, r4, #3 8001984: 4614 mov r4, r2 8001986: 461d mov r5, r3 8001988: 4643 mov r3, r8 800198a: 18e3 adds r3, r4, r3 800198c: 603b str r3, [r7, #0] 800198e: 464b mov r3, r9 8001990: eb45 0303 adc.w r3, r5, r3 8001994: 607b str r3, [r7, #4] 8001996: f04f 0200 mov.w r2, #0 800199a: f04f 0300 mov.w r3, #0 800199e: e9d7 4500 ldrd r4, r5, [r7] 80019a2: 4629 mov r1, r5 80019a4: 028b lsls r3, r1, #10 80019a6: 4621 mov r1, r4 80019a8: ea43 5391 orr.w r3, r3, r1, lsr #22 80019ac: 4621 mov r1, r4 80019ae: 028a lsls r2, r1, #10 80019b0: 4610 mov r0, r2 80019b2: 4619 mov r1, r3 80019b4: 6c7b ldr r3, [r7, #68] @ 0x44 80019b6: 2200 movs r2, #0 80019b8: 61bb str r3, [r7, #24] 80019ba: 61fa str r2, [r7, #28] 80019bc: e9d7 2306 ldrd r2, r3, [r7, #24] 80019c0: f7fe fc16 bl 80001f0 <__aeabi_uldivmod> 80019c4: 4602 mov r2, r0 80019c6: 460b mov r3, r1 80019c8: 4613 mov r3, r2 80019ca: 64fb str r3, [r7, #76] @ 0x4c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 80019cc: 4b0b ldr r3, [pc, #44] @ (80019fc ) 80019ce: 685b ldr r3, [r3, #4] 80019d0: 0c1b lsrs r3, r3, #16 80019d2: f003 0303 and.w r3, r3, #3 80019d6: 3301 adds r3, #1 80019d8: 005b lsls r3, r3, #1 80019da: 643b str r3, [r7, #64] @ 0x40 sysclockfreq = pllvco / pllp; 80019dc: 6cfa ldr r2, [r7, #76] @ 0x4c 80019de: 6c3b ldr r3, [r7, #64] @ 0x40 80019e0: fbb2 f3f3 udiv r3, r2, r3 80019e4: 64bb str r3, [r7, #72] @ 0x48 break; 80019e6: e002 b.n 80019ee } default: { sysclockfreq = HSI_VALUE; 80019e8: 4b05 ldr r3, [pc, #20] @ (8001a00 ) 80019ea: 64bb str r3, [r7, #72] @ 0x48 break; 80019ec: bf00 nop } } return sysclockfreq; 80019ee: 6cbb ldr r3, [r7, #72] @ 0x48 } 80019f0: 4618 mov r0, r3 80019f2: 3750 adds r7, #80 @ 0x50 80019f4: 46bd mov sp, r7 80019f6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 80019fa: bf00 nop 80019fc: 40023800 .word 0x40023800 8001a00: 00f42400 .word 0x00f42400 8001a04: 007a1200 .word 0x007a1200 08001a08 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8001a08: b480 push {r7} 8001a0a: af00 add r7, sp, #0 return SystemCoreClock; 8001a0c: 4b03 ldr r3, [pc, #12] @ (8001a1c ) 8001a0e: 681b ldr r3, [r3, #0] } 8001a10: 4618 mov r0, r3 8001a12: 46bd mov sp, r7 8001a14: f85d 7b04 ldr.w r7, [sp], #4 8001a18: 4770 bx lr 8001a1a: bf00 nop 8001a1c: 20000004 .word 0x20000004 08001a20 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8001a20: b580 push {r7, lr} 8001a22: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8001a24: f7ff fff0 bl 8001a08 8001a28: 4602 mov r2, r0 8001a2a: 4b05 ldr r3, [pc, #20] @ (8001a40 ) 8001a2c: 689b ldr r3, [r3, #8] 8001a2e: 0a9b lsrs r3, r3, #10 8001a30: f003 0307 and.w r3, r3, #7 8001a34: 4903 ldr r1, [pc, #12] @ (8001a44 ) 8001a36: 5ccb ldrb r3, [r1, r3] 8001a38: fa22 f303 lsr.w r3, r2, r3 } 8001a3c: 4618 mov r0, r3 8001a3e: bd80 pop {r7, pc} 8001a40: 40023800 .word 0x40023800 8001a44: 0800249c .word 0x0800249c 08001a48 : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8001a48: b480 push {r7} 8001a4a: b083 sub sp, #12 8001a4c: af00 add r7, sp, #0 8001a4e: 6078 str r0, [r7, #4] 8001a50: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8001a52: 687b ldr r3, [r7, #4] 8001a54: 220f movs r2, #15 8001a56: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8001a58: 4b12 ldr r3, [pc, #72] @ (8001aa4 ) 8001a5a: 689b ldr r3, [r3, #8] 8001a5c: f003 0203 and.w r2, r3, #3 8001a60: 687b ldr r3, [r7, #4] 8001a62: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8001a64: 4b0f ldr r3, [pc, #60] @ (8001aa4 ) 8001a66: 689b ldr r3, [r3, #8] 8001a68: f003 02f0 and.w r2, r3, #240 @ 0xf0 8001a6c: 687b ldr r3, [r7, #4] 8001a6e: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8001a70: 4b0c ldr r3, [pc, #48] @ (8001aa4 ) 8001a72: 689b ldr r3, [r3, #8] 8001a74: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8001a78: 687b ldr r3, [r7, #4] 8001a7a: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); 8001a7c: 4b09 ldr r3, [pc, #36] @ (8001aa4 ) 8001a7e: 689b ldr r3, [r3, #8] 8001a80: 08db lsrs r3, r3, #3 8001a82: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8001a86: 687b ldr r3, [r7, #4] 8001a88: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8001a8a: 4b07 ldr r3, [pc, #28] @ (8001aa8 ) 8001a8c: 681b ldr r3, [r3, #0] 8001a8e: f003 020f and.w r2, r3, #15 8001a92: 683b ldr r3, [r7, #0] 8001a94: 601a str r2, [r3, #0] } 8001a96: bf00 nop 8001a98: 370c adds r7, #12 8001a9a: 46bd mov sp, r7 8001a9c: f85d 7b04 ldr.w r7, [sp], #4 8001aa0: 4770 bx lr 8001aa2: bf00 nop 8001aa4: 40023800 .word 0x40023800 8001aa8: 40023c00 .word 0x40023c00 08001aac : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8001aac: b580 push {r7, lr} 8001aae: b082 sub sp, #8 8001ab0: af00 add r7, sp, #0 8001ab2: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8001ab4: 687b ldr r3, [r7, #4] 8001ab6: 2b00 cmp r3, #0 8001ab8: d101 bne.n 8001abe { return HAL_ERROR; 8001aba: 2301 movs r3, #1 8001abc: e041 b.n 8001b42 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8001abe: 687b ldr r3, [r7, #4] 8001ac0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8001ac4: b2db uxtb r3, r3 8001ac6: 2b00 cmp r3, #0 8001ac8: d106 bne.n 8001ad8 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8001aca: 687b ldr r3, [r7, #4] 8001acc: 2200 movs r2, #0 8001ace: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8001ad2: 6878 ldr r0, [r7, #4] 8001ad4: f7fe ff3e bl 8000954 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001ad8: 687b ldr r3, [r7, #4] 8001ada: 2202 movs r2, #2 8001adc: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 8001ae0: 687b ldr r3, [r7, #4] 8001ae2: 681a ldr r2, [r3, #0] 8001ae4: 687b ldr r3, [r7, #4] 8001ae6: 3304 adds r3, #4 8001ae8: 4619 mov r1, r3 8001aea: 4610 mov r0, r2 8001aec: f000 f9c0 bl 8001e70 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8001af0: 687b ldr r3, [r7, #4] 8001af2: 2201 movs r2, #1 8001af4: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001af8: 687b ldr r3, [r7, #4] 8001afa: 2201 movs r2, #1 8001afc: f883 203e strb.w r2, [r3, #62] @ 0x3e 8001b00: 687b ldr r3, [r7, #4] 8001b02: 2201 movs r2, #1 8001b04: f883 203f strb.w r2, [r3, #63] @ 0x3f 8001b08: 687b ldr r3, [r7, #4] 8001b0a: 2201 movs r2, #1 8001b0c: f883 2040 strb.w r2, [r3, #64] @ 0x40 8001b10: 687b ldr r3, [r7, #4] 8001b12: 2201 movs r2, #1 8001b14: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8001b18: 687b ldr r3, [r7, #4] 8001b1a: 2201 movs r2, #1 8001b1c: f883 2042 strb.w r2, [r3, #66] @ 0x42 8001b20: 687b ldr r3, [r7, #4] 8001b22: 2201 movs r2, #1 8001b24: f883 2043 strb.w r2, [r3, #67] @ 0x43 8001b28: 687b ldr r3, [r7, #4] 8001b2a: 2201 movs r2, #1 8001b2c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8001b30: 687b ldr r3, [r7, #4] 8001b32: 2201 movs r2, #1 8001b34: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8001b38: 687b ldr r3, [r7, #4] 8001b3a: 2201 movs r2, #1 8001b3c: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8001b40: 2300 movs r3, #0 } 8001b42: 4618 mov r0, r3 8001b44: 3708 adds r7, #8 8001b46: 46bd mov sp, r7 8001b48: bd80 pop {r7, pc} ... 08001b4c : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8001b4c: b480 push {r7} 8001b4e: b085 sub sp, #20 8001b50: af00 add r7, sp, #0 8001b52: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8001b54: 687b ldr r3, [r7, #4] 8001b56: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8001b5a: b2db uxtb r3, r3 8001b5c: 2b01 cmp r3, #1 8001b5e: d001 beq.n 8001b64 { return HAL_ERROR; 8001b60: 2301 movs r3, #1 8001b62: e04e b.n 8001c02 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8001b64: 687b ldr r3, [r7, #4] 8001b66: 2202 movs r2, #2 8001b68: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 681b ldr r3, [r3, #0] 8001b70: 68da ldr r2, [r3, #12] 8001b72: 687b ldr r3, [r7, #4] 8001b74: 681b ldr r3, [r3, #0] 8001b76: f042 0201 orr.w r2, r2, #1 8001b7a: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8001b7c: 687b ldr r3, [r7, #4] 8001b7e: 681b ldr r3, [r3, #0] 8001b80: 4a23 ldr r2, [pc, #140] @ (8001c10 ) 8001b82: 4293 cmp r3, r2 8001b84: d022 beq.n 8001bcc 8001b86: 687b ldr r3, [r7, #4] 8001b88: 681b ldr r3, [r3, #0] 8001b8a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001b8e: d01d beq.n 8001bcc 8001b90: 687b ldr r3, [r7, #4] 8001b92: 681b ldr r3, [r3, #0] 8001b94: 4a1f ldr r2, [pc, #124] @ (8001c14 ) 8001b96: 4293 cmp r3, r2 8001b98: d018 beq.n 8001bcc 8001b9a: 687b ldr r3, [r7, #4] 8001b9c: 681b ldr r3, [r3, #0] 8001b9e: 4a1e ldr r2, [pc, #120] @ (8001c18 ) 8001ba0: 4293 cmp r3, r2 8001ba2: d013 beq.n 8001bcc 8001ba4: 687b ldr r3, [r7, #4] 8001ba6: 681b ldr r3, [r3, #0] 8001ba8: 4a1c ldr r2, [pc, #112] @ (8001c1c ) 8001baa: 4293 cmp r3, r2 8001bac: d00e beq.n 8001bcc 8001bae: 687b ldr r3, [r7, #4] 8001bb0: 681b ldr r3, [r3, #0] 8001bb2: 4a1b ldr r2, [pc, #108] @ (8001c20 ) 8001bb4: 4293 cmp r3, r2 8001bb6: d009 beq.n 8001bcc 8001bb8: 687b ldr r3, [r7, #4] 8001bba: 681b ldr r3, [r3, #0] 8001bbc: 4a19 ldr r2, [pc, #100] @ (8001c24 ) 8001bbe: 4293 cmp r3, r2 8001bc0: d004 beq.n 8001bcc 8001bc2: 687b ldr r3, [r7, #4] 8001bc4: 681b ldr r3, [r3, #0] 8001bc6: 4a18 ldr r2, [pc, #96] @ (8001c28 ) 8001bc8: 4293 cmp r3, r2 8001bca: d111 bne.n 8001bf0 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8001bcc: 687b ldr r3, [r7, #4] 8001bce: 681b ldr r3, [r3, #0] 8001bd0: 689b ldr r3, [r3, #8] 8001bd2: f003 0307 and.w r3, r3, #7 8001bd6: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001bd8: 68fb ldr r3, [r7, #12] 8001bda: 2b06 cmp r3, #6 8001bdc: d010 beq.n 8001c00 { __HAL_TIM_ENABLE(htim); 8001bde: 687b ldr r3, [r7, #4] 8001be0: 681b ldr r3, [r3, #0] 8001be2: 681a ldr r2, [r3, #0] 8001be4: 687b ldr r3, [r7, #4] 8001be6: 681b ldr r3, [r3, #0] 8001be8: f042 0201 orr.w r2, r2, #1 8001bec: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8001bee: e007 b.n 8001c00 } } else { __HAL_TIM_ENABLE(htim); 8001bf0: 687b ldr r3, [r7, #4] 8001bf2: 681b ldr r3, [r3, #0] 8001bf4: 681a ldr r2, [r3, #0] 8001bf6: 687b ldr r3, [r7, #4] 8001bf8: 681b ldr r3, [r3, #0] 8001bfa: f042 0201 orr.w r2, r2, #1 8001bfe: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8001c00: 2300 movs r3, #0 } 8001c02: 4618 mov r0, r3 8001c04: 3714 adds r7, #20 8001c06: 46bd mov sp, r7 8001c08: f85d 7b04 ldr.w r7, [sp], #4 8001c0c: 4770 bx lr 8001c0e: bf00 nop 8001c10: 40010000 .word 0x40010000 8001c14: 40000400 .word 0x40000400 8001c18: 40000800 .word 0x40000800 8001c1c: 40000c00 .word 0x40000c00 8001c20: 40010400 .word 0x40010400 8001c24: 40014000 .word 0x40014000 8001c28: 40001800 .word 0x40001800 08001c2c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8001c2c: b580 push {r7, lr} 8001c2e: b084 sub sp, #16 8001c30: af00 add r7, sp, #0 8001c32: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8001c34: 687b ldr r3, [r7, #4] 8001c36: 681b ldr r3, [r3, #0] 8001c38: 68db ldr r3, [r3, #12] 8001c3a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8001c3c: 687b ldr r3, [r7, #4] 8001c3e: 681b ldr r3, [r3, #0] 8001c40: 691b ldr r3, [r3, #16] 8001c42: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8001c44: 68bb ldr r3, [r7, #8] 8001c46: f003 0302 and.w r3, r3, #2 8001c4a: 2b00 cmp r3, #0 8001c4c: d020 beq.n 8001c90 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8001c4e: 68fb ldr r3, [r7, #12] 8001c50: f003 0302 and.w r3, r3, #2 8001c54: 2b00 cmp r3, #0 8001c56: d01b beq.n 8001c90 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8001c58: 687b ldr r3, [r7, #4] 8001c5a: 681b ldr r3, [r3, #0] 8001c5c: f06f 0202 mvn.w r2, #2 8001c60: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8001c62: 687b ldr r3, [r7, #4] 8001c64: 2201 movs r2, #1 8001c66: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8001c68: 687b ldr r3, [r7, #4] 8001c6a: 681b ldr r3, [r3, #0] 8001c6c: 699b ldr r3, [r3, #24] 8001c6e: f003 0303 and.w r3, r3, #3 8001c72: 2b00 cmp r3, #0 8001c74: d003 beq.n 8001c7e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8001c76: 6878 ldr r0, [r7, #4] 8001c78: f000 f8dc bl 8001e34 8001c7c: e005 b.n 8001c8a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8001c7e: 6878 ldr r0, [r7, #4] 8001c80: f000 f8ce bl 8001e20 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001c84: 6878 ldr r0, [r7, #4] 8001c86: f000 f8df bl 8001e48 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001c8a: 687b ldr r3, [r7, #4] 8001c8c: 2200 movs r2, #0 8001c8e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8001c90: 68bb ldr r3, [r7, #8] 8001c92: f003 0304 and.w r3, r3, #4 8001c96: 2b00 cmp r3, #0 8001c98: d020 beq.n 8001cdc { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8001c9a: 68fb ldr r3, [r7, #12] 8001c9c: f003 0304 and.w r3, r3, #4 8001ca0: 2b00 cmp r3, #0 8001ca2: d01b beq.n 8001cdc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 681b ldr r3, [r3, #0] 8001ca8: f06f 0204 mvn.w r2, #4 8001cac: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 2202 movs r2, #2 8001cb2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8001cb4: 687b ldr r3, [r7, #4] 8001cb6: 681b ldr r3, [r3, #0] 8001cb8: 699b ldr r3, [r3, #24] 8001cba: f403 7340 and.w r3, r3, #768 @ 0x300 8001cbe: 2b00 cmp r3, #0 8001cc0: d003 beq.n 8001cca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8001cc2: 6878 ldr r0, [r7, #4] 8001cc4: f000 f8b6 bl 8001e34 8001cc8: e005 b.n 8001cd6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8001cca: 6878 ldr r0, [r7, #4] 8001ccc: f000 f8a8 bl 8001e20 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001cd0: 6878 ldr r0, [r7, #4] 8001cd2: f000 f8b9 bl 8001e48 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001cd6: 687b ldr r3, [r7, #4] 8001cd8: 2200 movs r2, #0 8001cda: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8001cdc: 68bb ldr r3, [r7, #8] 8001cde: f003 0308 and.w r3, r3, #8 8001ce2: 2b00 cmp r3, #0 8001ce4: d020 beq.n 8001d28 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8001ce6: 68fb ldr r3, [r7, #12] 8001ce8: f003 0308 and.w r3, r3, #8 8001cec: 2b00 cmp r3, #0 8001cee: d01b beq.n 8001d28 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8001cf0: 687b ldr r3, [r7, #4] 8001cf2: 681b ldr r3, [r3, #0] 8001cf4: f06f 0208 mvn.w r2, #8 8001cf8: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8001cfa: 687b ldr r3, [r7, #4] 8001cfc: 2204 movs r2, #4 8001cfe: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8001d00: 687b ldr r3, [r7, #4] 8001d02: 681b ldr r3, [r3, #0] 8001d04: 69db ldr r3, [r3, #28] 8001d06: f003 0303 and.w r3, r3, #3 8001d0a: 2b00 cmp r3, #0 8001d0c: d003 beq.n 8001d16 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8001d0e: 6878 ldr r0, [r7, #4] 8001d10: f000 f890 bl 8001e34 8001d14: e005 b.n 8001d22 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8001d16: 6878 ldr r0, [r7, #4] 8001d18: f000 f882 bl 8001e20 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001d1c: 6878 ldr r0, [r7, #4] 8001d1e: f000 f893 bl 8001e48 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001d22: 687b ldr r3, [r7, #4] 8001d24: 2200 movs r2, #0 8001d26: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8001d28: 68bb ldr r3, [r7, #8] 8001d2a: f003 0310 and.w r3, r3, #16 8001d2e: 2b00 cmp r3, #0 8001d30: d020 beq.n 8001d74 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8001d32: 68fb ldr r3, [r7, #12] 8001d34: f003 0310 and.w r3, r3, #16 8001d38: 2b00 cmp r3, #0 8001d3a: d01b beq.n 8001d74 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8001d3c: 687b ldr r3, [r7, #4] 8001d3e: 681b ldr r3, [r3, #0] 8001d40: f06f 0210 mvn.w r2, #16 8001d44: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8001d46: 687b ldr r3, [r7, #4] 8001d48: 2208 movs r2, #8 8001d4a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8001d4c: 687b ldr r3, [r7, #4] 8001d4e: 681b ldr r3, [r3, #0] 8001d50: 69db ldr r3, [r3, #28] 8001d52: f403 7340 and.w r3, r3, #768 @ 0x300 8001d56: 2b00 cmp r3, #0 8001d58: d003 beq.n 8001d62 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8001d5a: 6878 ldr r0, [r7, #4] 8001d5c: f000 f86a bl 8001e34 8001d60: e005 b.n 8001d6e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8001d62: 6878 ldr r0, [r7, #4] 8001d64: f000 f85c bl 8001e20 HAL_TIM_PWM_PulseFinishedCallback(htim); 8001d68: 6878 ldr r0, [r7, #4] 8001d6a: f000 f86d bl 8001e48 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8001d6e: 687b ldr r3, [r7, #4] 8001d70: 2200 movs r2, #0 8001d72: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8001d74: 68bb ldr r3, [r7, #8] 8001d76: f003 0301 and.w r3, r3, #1 8001d7a: 2b00 cmp r3, #0 8001d7c: d00c beq.n 8001d98 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8001d7e: 68fb ldr r3, [r7, #12] 8001d80: f003 0301 and.w r3, r3, #1 8001d84: 2b00 cmp r3, #0 8001d86: d007 beq.n 8001d98 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8001d88: 687b ldr r3, [r7, #4] 8001d8a: 681b ldr r3, [r3, #0] 8001d8c: f06f 0201 mvn.w r2, #1 8001d90: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8001d92: 6878 ldr r0, [r7, #4] 8001d94: f000 f83a bl 8001e0c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 8001d98: 68bb ldr r3, [r7, #8] 8001d9a: f003 0380 and.w r3, r3, #128 @ 0x80 8001d9e: 2b00 cmp r3, #0 8001da0: d00c beq.n 8001dbc { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8001da2: 68fb ldr r3, [r7, #12] 8001da4: f003 0380 and.w r3, r3, #128 @ 0x80 8001da8: 2b00 cmp r3, #0 8001daa: d007 beq.n 8001dbc { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8001dac: 687b ldr r3, [r7, #4] 8001dae: 681b ldr r3, [r3, #0] 8001db0: f06f 0280 mvn.w r2, #128 @ 0x80 8001db4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8001db6: 6878 ldr r0, [r7, #4] 8001db8: f000 f90a bl 8001fd0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8001dbc: 68bb ldr r3, [r7, #8] 8001dbe: f003 0340 and.w r3, r3, #64 @ 0x40 8001dc2: 2b00 cmp r3, #0 8001dc4: d00c beq.n 8001de0 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8001dc6: 68fb ldr r3, [r7, #12] 8001dc8: f003 0340 and.w r3, r3, #64 @ 0x40 8001dcc: 2b00 cmp r3, #0 8001dce: d007 beq.n 8001de0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8001dd0: 687b ldr r3, [r7, #4] 8001dd2: 681b ldr r3, [r3, #0] 8001dd4: f06f 0240 mvn.w r2, #64 @ 0x40 8001dd8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8001dda: 6878 ldr r0, [r7, #4] 8001ddc: f000 f83e bl 8001e5c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8001de0: 68bb ldr r3, [r7, #8] 8001de2: f003 0320 and.w r3, r3, #32 8001de6: 2b00 cmp r3, #0 8001de8: d00c beq.n 8001e04 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8001dea: 68fb ldr r3, [r7, #12] 8001dec: f003 0320 and.w r3, r3, #32 8001df0: 2b00 cmp r3, #0 8001df2: d007 beq.n 8001e04 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8001df4: 687b ldr r3, [r7, #4] 8001df6: 681b ldr r3, [r3, #0] 8001df8: f06f 0220 mvn.w r2, #32 8001dfc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8001dfe: 6878 ldr r0, [r7, #4] 8001e00: f000 f8dc bl 8001fbc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8001e04: bf00 nop 8001e06: 3710 adds r7, #16 8001e08: 46bd mov sp, r7 8001e0a: bd80 pop {r7, pc} 08001e0c : * @brief Period elapsed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8001e0c: b480 push {r7} 8001e0e: b083 sub sp, #12 8001e10: af00 add r7, sp, #0 8001e12: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PeriodElapsedCallback could be implemented in the user file */ } 8001e14: bf00 nop 8001e16: 370c adds r7, #12 8001e18: 46bd mov sp, r7 8001e1a: f85d 7b04 ldr.w r7, [sp], #4 8001e1e: 4770 bx lr 08001e20 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 8001e20: b480 push {r7} 8001e22: b083 sub sp, #12 8001e24: af00 add r7, sp, #0 8001e26: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 8001e28: bf00 nop 8001e2a: 370c adds r7, #12 8001e2c: 46bd mov sp, r7 8001e2e: f85d 7b04 ldr.w r7, [sp], #4 8001e32: 4770 bx lr 08001e34 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 8001e34: b480 push {r7} 8001e36: b083 sub sp, #12 8001e38: af00 add r7, sp, #0 8001e3a: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8001e3c: bf00 nop 8001e3e: 370c adds r7, #12 8001e40: 46bd mov sp, r7 8001e42: f85d 7b04 ldr.w r7, [sp], #4 8001e46: 4770 bx lr 08001e48 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 8001e48: b480 push {r7} 8001e4a: b083 sub sp, #12 8001e4c: af00 add r7, sp, #0 8001e4e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8001e50: bf00 nop 8001e52: 370c adds r7, #12 8001e54: 46bd mov sp, r7 8001e56: f85d 7b04 ldr.w r7, [sp], #4 8001e5a: 4770 bx lr 08001e5c : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8001e5c: b480 push {r7} 8001e5e: b083 sub sp, #12 8001e60: af00 add r7, sp, #0 8001e62: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8001e64: bf00 nop 8001e66: 370c adds r7, #12 8001e68: 46bd mov sp, r7 8001e6a: f85d 7b04 ldr.w r7, [sp], #4 8001e6e: 4770 bx lr 08001e70 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8001e70: b480 push {r7} 8001e72: b085 sub sp, #20 8001e74: af00 add r7, sp, #0 8001e76: 6078 str r0, [r7, #4] 8001e78: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8001e7a: 687b ldr r3, [r7, #4] 8001e7c: 681b ldr r3, [r3, #0] 8001e7e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8001e80: 687b ldr r3, [r7, #4] 8001e82: 4a43 ldr r2, [pc, #268] @ (8001f90 ) 8001e84: 4293 cmp r3, r2 8001e86: d013 beq.n 8001eb0 8001e88: 687b ldr r3, [r7, #4] 8001e8a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001e8e: d00f beq.n 8001eb0 8001e90: 687b ldr r3, [r7, #4] 8001e92: 4a40 ldr r2, [pc, #256] @ (8001f94 ) 8001e94: 4293 cmp r3, r2 8001e96: d00b beq.n 8001eb0 8001e98: 687b ldr r3, [r7, #4] 8001e9a: 4a3f ldr r2, [pc, #252] @ (8001f98 ) 8001e9c: 4293 cmp r3, r2 8001e9e: d007 beq.n 8001eb0 8001ea0: 687b ldr r3, [r7, #4] 8001ea2: 4a3e ldr r2, [pc, #248] @ (8001f9c ) 8001ea4: 4293 cmp r3, r2 8001ea6: d003 beq.n 8001eb0 8001ea8: 687b ldr r3, [r7, #4] 8001eaa: 4a3d ldr r2, [pc, #244] @ (8001fa0 ) 8001eac: 4293 cmp r3, r2 8001eae: d108 bne.n 8001ec2 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8001eb0: 68fb ldr r3, [r7, #12] 8001eb2: f023 0370 bic.w r3, r3, #112 @ 0x70 8001eb6: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8001eb8: 683b ldr r3, [r7, #0] 8001eba: 685b ldr r3, [r3, #4] 8001ebc: 68fa ldr r2, [r7, #12] 8001ebe: 4313 orrs r3, r2 8001ec0: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8001ec2: 687b ldr r3, [r7, #4] 8001ec4: 4a32 ldr r2, [pc, #200] @ (8001f90 ) 8001ec6: 4293 cmp r3, r2 8001ec8: d02b beq.n 8001f22 8001eca: 687b ldr r3, [r7, #4] 8001ecc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8001ed0: d027 beq.n 8001f22 8001ed2: 687b ldr r3, [r7, #4] 8001ed4: 4a2f ldr r2, [pc, #188] @ (8001f94 ) 8001ed6: 4293 cmp r3, r2 8001ed8: d023 beq.n 8001f22 8001eda: 687b ldr r3, [r7, #4] 8001edc: 4a2e ldr r2, [pc, #184] @ (8001f98 ) 8001ede: 4293 cmp r3, r2 8001ee0: d01f beq.n 8001f22 8001ee2: 687b ldr r3, [r7, #4] 8001ee4: 4a2d ldr r2, [pc, #180] @ (8001f9c ) 8001ee6: 4293 cmp r3, r2 8001ee8: d01b beq.n 8001f22 8001eea: 687b ldr r3, [r7, #4] 8001eec: 4a2c ldr r2, [pc, #176] @ (8001fa0 ) 8001eee: 4293 cmp r3, r2 8001ef0: d017 beq.n 8001f22 8001ef2: 687b ldr r3, [r7, #4] 8001ef4: 4a2b ldr r2, [pc, #172] @ (8001fa4 ) 8001ef6: 4293 cmp r3, r2 8001ef8: d013 beq.n 8001f22 8001efa: 687b ldr r3, [r7, #4] 8001efc: 4a2a ldr r2, [pc, #168] @ (8001fa8 ) 8001efe: 4293 cmp r3, r2 8001f00: d00f beq.n 8001f22 8001f02: 687b ldr r3, [r7, #4] 8001f04: 4a29 ldr r2, [pc, #164] @ (8001fac ) 8001f06: 4293 cmp r3, r2 8001f08: d00b beq.n 8001f22 8001f0a: 687b ldr r3, [r7, #4] 8001f0c: 4a28 ldr r2, [pc, #160] @ (8001fb0 ) 8001f0e: 4293 cmp r3, r2 8001f10: d007 beq.n 8001f22 8001f12: 687b ldr r3, [r7, #4] 8001f14: 4a27 ldr r2, [pc, #156] @ (8001fb4 ) 8001f16: 4293 cmp r3, r2 8001f18: d003 beq.n 8001f22 8001f1a: 687b ldr r3, [r7, #4] 8001f1c: 4a26 ldr r2, [pc, #152] @ (8001fb8 ) 8001f1e: 4293 cmp r3, r2 8001f20: d108 bne.n 8001f34 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8001f22: 68fb ldr r3, [r7, #12] 8001f24: f423 7340 bic.w r3, r3, #768 @ 0x300 8001f28: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8001f2a: 683b ldr r3, [r7, #0] 8001f2c: 68db ldr r3, [r3, #12] 8001f2e: 68fa ldr r2, [r7, #12] 8001f30: 4313 orrs r3, r2 8001f32: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8001f34: 68fb ldr r3, [r7, #12] 8001f36: f023 0280 bic.w r2, r3, #128 @ 0x80 8001f3a: 683b ldr r3, [r7, #0] 8001f3c: 695b ldr r3, [r3, #20] 8001f3e: 4313 orrs r3, r2 8001f40: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8001f42: 683b ldr r3, [r7, #0] 8001f44: 689a ldr r2, [r3, #8] 8001f46: 687b ldr r3, [r7, #4] 8001f48: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8001f4a: 683b ldr r3, [r7, #0] 8001f4c: 681a ldr r2, [r3, #0] 8001f4e: 687b ldr r3, [r7, #4] 8001f50: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8001f52: 687b ldr r3, [r7, #4] 8001f54: 4a0e ldr r2, [pc, #56] @ (8001f90 ) 8001f56: 4293 cmp r3, r2 8001f58: d003 beq.n 8001f62 8001f5a: 687b ldr r3, [r7, #4] 8001f5c: 4a10 ldr r2, [pc, #64] @ (8001fa0 ) 8001f5e: 4293 cmp r3, r2 8001f60: d103 bne.n 8001f6a { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8001f62: 683b ldr r3, [r7, #0] 8001f64: 691a ldr r2, [r3, #16] 8001f66: 687b ldr r3, [r7, #4] 8001f68: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8001f6a: 687b ldr r3, [r7, #4] 8001f6c: 681b ldr r3, [r3, #0] 8001f6e: f043 0204 orr.w r2, r3, #4 8001f72: 687b ldr r3, [r7, #4] 8001f74: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8001f76: 687b ldr r3, [r7, #4] 8001f78: 2201 movs r2, #1 8001f7a: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8001f7c: 687b ldr r3, [r7, #4] 8001f7e: 68fa ldr r2, [r7, #12] 8001f80: 601a str r2, [r3, #0] } 8001f82: bf00 nop 8001f84: 3714 adds r7, #20 8001f86: 46bd mov sp, r7 8001f88: f85d 7b04 ldr.w r7, [sp], #4 8001f8c: 4770 bx lr 8001f8e: bf00 nop 8001f90: 40010000 .word 0x40010000 8001f94: 40000400 .word 0x40000400 8001f98: 40000800 .word 0x40000800 8001f9c: 40000c00 .word 0x40000c00 8001fa0: 40010400 .word 0x40010400 8001fa4: 40014000 .word 0x40014000 8001fa8: 40014400 .word 0x40014400 8001fac: 40014800 .word 0x40014800 8001fb0: 40001800 .word 0x40001800 8001fb4: 40001c00 .word 0x40001c00 8001fb8: 40002000 .word 0x40002000 08001fbc : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8001fbc: b480 push {r7} 8001fbe: b083 sub sp, #12 8001fc0: af00 add r7, sp, #0 8001fc2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8001fc4: bf00 nop 8001fc6: 370c adds r7, #12 8001fc8: 46bd mov sp, r7 8001fca: f85d 7b04 ldr.w r7, [sp], #4 8001fce: 4770 bx lr 08001fd0 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8001fd0: b480 push {r7} 8001fd2: b083 sub sp, #12 8001fd4: af00 add r7, sp, #0 8001fd6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8001fd8: bf00 nop 8001fda: 370c adds r7, #12 8001fdc: 46bd mov sp, r7 8001fde: f85d 7b04 ldr.w r7, [sp], #4 8001fe2: 4770 bx lr 08001fe4 : listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8001fe4: b480 push {r7} 8001fe6: b085 sub sp, #20 8001fe8: af00 add r7, sp, #0 8001fea: 6078 str r0, [r7, #4] 8001fec: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8001fee: 687b ldr r3, [r7, #4] 8001ff0: 685b ldr r3, [r3, #4] 8001ff2: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8001ff4: 683b ldr r3, [r7, #0] 8001ff6: 68fa ldr r2, [r7, #12] 8001ff8: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8001ffa: 68fb ldr r3, [r7, #12] 8001ffc: 689a ldr r2, [r3, #8] 8001ffe: 683b ldr r3, [r7, #0] 8002000: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8002002: 68fb ldr r3, [r7, #12] 8002004: 689b ldr r3, [r3, #8] 8002006: 683a ldr r2, [r7, #0] 8002008: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 800200a: 68fb ldr r3, [r7, #12] 800200c: 683a ldr r2, [r7, #0] 800200e: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8002010: 683b ldr r3, [r7, #0] 8002012: 687a ldr r2, [r7, #4] 8002014: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8002016: 687b ldr r3, [r7, #4] 8002018: 681b ldr r3, [r3, #0] 800201a: 1c5a adds r2, r3, #1 800201c: 687b ldr r3, [r7, #4] 800201e: 601a str r2, [r3, #0] } 8002020: bf00 nop 8002022: 3714 adds r7, #20 8002024: 46bd mov sp, r7 8002026: f85d 7b04 ldr.w r7, [sp], #4 800202a: 4770 bx lr 0800202c : ( pxList->uxNumberOfItems )++; } /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 800202c: b480 push {r7} 800202e: b085 sub sp, #20 8002030: af00 add r7, sp, #0 8002032: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8002034: 687b ldr r3, [r7, #4] 8002036: 691b ldr r3, [r3, #16] 8002038: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 800203a: 687b ldr r3, [r7, #4] 800203c: 685b ldr r3, [r3, #4] 800203e: 687a ldr r2, [r7, #4] 8002040: 6892 ldr r2, [r2, #8] 8002042: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8002044: 687b ldr r3, [r7, #4] 8002046: 689b ldr r3, [r3, #8] 8002048: 687a ldr r2, [r7, #4] 800204a: 6852 ldr r2, [r2, #4] 800204c: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 800204e: 68fb ldr r3, [r7, #12] 8002050: 685b ldr r3, [r3, #4] 8002052: 687a ldr r2, [r7, #4] 8002054: 429a cmp r2, r3 8002056: d103 bne.n 8002060 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8002058: 687b ldr r3, [r7, #4] 800205a: 689a ldr r2, [r3, #8] 800205c: 68fb ldr r3, [r7, #12] 800205e: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8002060: 687b ldr r3, [r7, #4] 8002062: 2200 movs r2, #0 8002064: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8002066: 68fb ldr r3, [r7, #12] 8002068: 681b ldr r3, [r3, #0] 800206a: 1e5a subs r2, r3, #1 800206c: 68fb ldr r3, [r7, #12] 800206e: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8002070: 68fb ldr r3, [r7, #12] 8002072: 681b ldr r3, [r3, #0] } 8002074: 4618 mov r0, r3 8002076: 3714 adds r7, #20 8002078: 46bd mov sp, r7 800207a: f85d 7b04 ldr.w r7, [sp], #4 800207e: 4770 bx lr 08002080 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8002080: b580 push {r7, lr} 8002082: b086 sub sp, #24 8002084: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 8002086: 2300 movs r3, #0 8002088: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800208a: 4b4f ldr r3, [pc, #316] @ (80021c8 ) 800208c: 681b ldr r3, [r3, #0] 800208e: 2b00 cmp r3, #0 8002090: f040 808f bne.w 80021b2 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 8002094: 4b4d ldr r3, [pc, #308] @ (80021cc ) 8002096: 681b ldr r3, [r3, #0] 8002098: 3301 adds r3, #1 800209a: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 800209c: 4a4b ldr r2, [pc, #300] @ (80021cc ) 800209e: 693b ldr r3, [r7, #16] 80020a0: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 80020a2: 693b ldr r3, [r7, #16] 80020a4: 2b00 cmp r3, #0 80020a6: d121 bne.n 80020ec { taskSWITCH_DELAYED_LISTS(); 80020a8: 4b49 ldr r3, [pc, #292] @ (80021d0 ) 80020aa: 681b ldr r3, [r3, #0] 80020ac: 681b ldr r3, [r3, #0] 80020ae: 2b00 cmp r3, #0 80020b0: d00b beq.n 80020ca portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 80020b2: f04f 0350 mov.w r3, #80 @ 0x50 80020b6: f383 8811 msr BASEPRI, r3 80020ba: f3bf 8f6f isb sy 80020be: f3bf 8f4f dsb sy 80020c2: 603b str r3, [r7, #0] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 80020c4: bf00 nop 80020c6: bf00 nop 80020c8: e7fd b.n 80020c6 80020ca: 4b41 ldr r3, [pc, #260] @ (80021d0 ) 80020cc: 681b ldr r3, [r3, #0] 80020ce: 60fb str r3, [r7, #12] 80020d0: 4b40 ldr r3, [pc, #256] @ (80021d4 ) 80020d2: 681b ldr r3, [r3, #0] 80020d4: 4a3e ldr r2, [pc, #248] @ (80021d0 ) 80020d6: 6013 str r3, [r2, #0] 80020d8: 4a3e ldr r2, [pc, #248] @ (80021d4 ) 80020da: 68fb ldr r3, [r7, #12] 80020dc: 6013 str r3, [r2, #0] 80020de: 4b3e ldr r3, [pc, #248] @ (80021d8 ) 80020e0: 681b ldr r3, [r3, #0] 80020e2: 3301 adds r3, #1 80020e4: 4a3c ldr r2, [pc, #240] @ (80021d8 ) 80020e6: 6013 str r3, [r2, #0] 80020e8: f000 f906 bl 80022f8 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 80020ec: 4b3b ldr r3, [pc, #236] @ (80021dc ) 80020ee: 681b ldr r3, [r3, #0] 80020f0: 693a ldr r2, [r7, #16] 80020f2: 429a cmp r2, r3 80020f4: d348 bcc.n 8002188 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80020f6: 4b36 ldr r3, [pc, #216] @ (80021d0 ) 80020f8: 681b ldr r3, [r3, #0] 80020fa: 681b ldr r3, [r3, #0] 80020fc: 2b00 cmp r3, #0 80020fe: d104 bne.n 800210a /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8002100: 4b36 ldr r3, [pc, #216] @ (80021dc ) 8002102: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8002106: 601a str r2, [r3, #0] break; 8002108: e03e b.n 8002188 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800210a: 4b31 ldr r3, [pc, #196] @ (80021d0 ) 800210c: 681b ldr r3, [r3, #0] 800210e: 68db ldr r3, [r3, #12] 8002110: 68db ldr r3, [r3, #12] 8002112: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8002114: 68bb ldr r3, [r7, #8] 8002116: 685b ldr r3, [r3, #4] 8002118: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 800211a: 693a ldr r2, [r7, #16] 800211c: 687b ldr r3, [r7, #4] 800211e: 429a cmp r2, r3 8002120: d203 bcs.n 800212a /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8002122: 4a2e ldr r2, [pc, #184] @ (80021dc ) 8002124: 687b ldr r3, [r7, #4] 8002126: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8002128: e02e b.n 8002188 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800212a: 68bb ldr r3, [r7, #8] 800212c: 3304 adds r3, #4 800212e: 4618 mov r0, r3 8002130: f7ff ff7c bl 800202c /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8002134: 68bb ldr r3, [r7, #8] 8002136: 6a9b ldr r3, [r3, #40] @ 0x28 8002138: 2b00 cmp r3, #0 800213a: d004 beq.n 8002146 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800213c: 68bb ldr r3, [r7, #8] 800213e: 3318 adds r3, #24 8002140: 4618 mov r0, r3 8002142: f7ff ff73 bl 800202c mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 8002146: 68bb ldr r3, [r7, #8] 8002148: 6adb ldr r3, [r3, #44] @ 0x2c 800214a: 2201 movs r2, #1 800214c: 409a lsls r2, r3 800214e: 4b24 ldr r3, [pc, #144] @ (80021e0 ) 8002150: 681b ldr r3, [r3, #0] 8002152: 4313 orrs r3, r2 8002154: 4a22 ldr r2, [pc, #136] @ (80021e0 ) 8002156: 6013 str r3, [r2, #0] 8002158: 68bb ldr r3, [r7, #8] 800215a: 6ada ldr r2, [r3, #44] @ 0x2c 800215c: 4613 mov r3, r2 800215e: 009b lsls r3, r3, #2 8002160: 4413 add r3, r2 8002162: 009b lsls r3, r3, #2 8002164: 4a1f ldr r2, [pc, #124] @ (80021e4 ) 8002166: 441a add r2, r3 8002168: 68bb ldr r3, [r7, #8] 800216a: 3304 adds r3, #4 800216c: 4619 mov r1, r3 800216e: 4610 mov r0, r2 8002170: f7ff ff38 bl 8001fe4 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8002174: 68bb ldr r3, [r7, #8] 8002176: 6ada ldr r2, [r3, #44] @ 0x2c 8002178: 4b1b ldr r3, [pc, #108] @ (80021e8 ) 800217a: 681b ldr r3, [r3, #0] 800217c: 6adb ldr r3, [r3, #44] @ 0x2c 800217e: 429a cmp r2, r3 8002180: d3b9 bcc.n 80020f6 { xSwitchRequired = pdTRUE; 8002182: 2301 movs r3, #1 8002184: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8002186: e7b6 b.n 80020f6 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8002188: 4b17 ldr r3, [pc, #92] @ (80021e8 ) 800218a: 681b ldr r3, [r3, #0] 800218c: 6ada ldr r2, [r3, #44] @ 0x2c 800218e: 4915 ldr r1, [pc, #84] @ (80021e4 ) 8002190: 4613 mov r3, r2 8002192: 009b lsls r3, r3, #2 8002194: 4413 add r3, r2 8002196: 009b lsls r3, r3, #2 8002198: 440b add r3, r1 800219a: 681b ldr r3, [r3, #0] 800219c: 2b01 cmp r3, #1 800219e: d901 bls.n 80021a4 { xSwitchRequired = pdTRUE; 80021a0: 2301 movs r3, #1 80021a2: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 80021a4: 4b11 ldr r3, [pc, #68] @ (80021ec ) 80021a6: 681b ldr r3, [r3, #0] 80021a8: 2b00 cmp r3, #0 80021aa: d007 beq.n 80021bc { xSwitchRequired = pdTRUE; 80021ac: 2301 movs r3, #1 80021ae: 617b str r3, [r7, #20] 80021b0: e004 b.n 80021bc } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 80021b2: 4b0f ldr r3, [pc, #60] @ (80021f0 ) 80021b4: 681b ldr r3, [r3, #0] 80021b6: 3301 adds r3, #1 80021b8: 4a0d ldr r2, [pc, #52] @ (80021f0 ) 80021ba: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 80021bc: 697b ldr r3, [r7, #20] } 80021be: 4618 mov r0, r3 80021c0: 3718 adds r7, #24 80021c2: 46bd mov sp, r7 80021c4: bd80 pop {r7, pc} 80021c6: bf00 nop 80021c8: 20000130 .word 0x20000130 80021cc: 20000118 .word 0x20000118 80021d0: 20000110 .word 0x20000110 80021d4: 20000114 .word 0x20000114 80021d8: 20000128 .word 0x20000128 80021dc: 2000012c .word 0x2000012c 80021e0: 2000011c .word 0x2000011c 80021e4: 20000084 .word 0x20000084 80021e8: 20000080 .word 0x20000080 80021ec: 20000124 .word 0x20000124 80021f0: 20000120 .word 0x20000120 080021f4 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 80021f4: b580 push {r7, lr} 80021f6: b088 sub sp, #32 80021f8: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 80021fa: 4b3a ldr r3, [pc, #232] @ (80022e4 ) 80021fc: 681b ldr r3, [r3, #0] 80021fe: 2b00 cmp r3, #0 8002200: d003 beq.n 800220a { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8002202: 4b39 ldr r3, [pc, #228] @ (80022e8 ) 8002204: 2201 movs r2, #1 8002206: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 8002208: e067 b.n 80022da xYieldPending = pdFALSE; 800220a: 4b37 ldr r3, [pc, #220] @ (80022e8 ) 800220c: 2200 movs r2, #0 800220e: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8002210: 4b36 ldr r3, [pc, #216] @ (80022ec ) 8002212: 681b ldr r3, [r3, #0] 8002214: 6b1b ldr r3, [r3, #48] @ 0x30 8002216: 61fb str r3, [r7, #28] 8002218: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5 800221c: 61bb str r3, [r7, #24] 800221e: 69fb ldr r3, [r7, #28] 8002220: 681b ldr r3, [r3, #0] 8002222: 69ba ldr r2, [r7, #24] 8002224: 429a cmp r2, r3 8002226: d111 bne.n 800224c 8002228: 69fb ldr r3, [r7, #28] 800222a: 3304 adds r3, #4 800222c: 681b ldr r3, [r3, #0] 800222e: 69ba ldr r2, [r7, #24] 8002230: 429a cmp r2, r3 8002232: d10b bne.n 800224c 8002234: 69fb ldr r3, [r7, #28] 8002236: 3308 adds r3, #8 8002238: 681b ldr r3, [r3, #0] 800223a: 69ba ldr r2, [r7, #24] 800223c: 429a cmp r2, r3 800223e: d105 bne.n 800224c 8002240: 69fb ldr r3, [r7, #28] 8002242: 330c adds r3, #12 8002244: 681b ldr r3, [r3, #0] 8002246: 69ba ldr r2, [r7, #24] 8002248: 429a cmp r2, r3 800224a: d008 beq.n 800225e 800224c: 4b27 ldr r3, [pc, #156] @ (80022ec ) 800224e: 681a ldr r2, [r3, #0] 8002250: 4b26 ldr r3, [pc, #152] @ (80022ec ) 8002252: 681b ldr r3, [r3, #0] 8002254: 3334 adds r3, #52 @ 0x34 8002256: 4619 mov r1, r3 8002258: 4610 mov r0, r2 800225a: f7fe f95f bl 800051c taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800225e: 4b24 ldr r3, [pc, #144] @ (80022f0 ) 8002260: 681b ldr r3, [r3, #0] 8002262: 60fb str r3, [r7, #12] __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); 8002264: 68fb ldr r3, [r7, #12] 8002266: fab3 f383 clz r3, r3 800226a: 72fb strb r3, [r7, #11] return ucReturn; 800226c: 7afb ldrb r3, [r7, #11] 800226e: f1c3 031f rsb r3, r3, #31 8002272: 617b str r3, [r7, #20] 8002274: 491f ldr r1, [pc, #124] @ (80022f4 ) 8002276: 697a ldr r2, [r7, #20] 8002278: 4613 mov r3, r2 800227a: 009b lsls r3, r3, #2 800227c: 4413 add r3, r2 800227e: 009b lsls r3, r3, #2 8002280: 440b add r3, r1 8002282: 681b ldr r3, [r3, #0] 8002284: 2b00 cmp r3, #0 8002286: d10b bne.n 80022a0 __asm volatile 8002288: f04f 0350 mov.w r3, #80 @ 0x50 800228c: f383 8811 msr BASEPRI, r3 8002290: f3bf 8f6f isb sy 8002294: f3bf 8f4f dsb sy 8002298: 607b str r3, [r7, #4] } 800229a: bf00 nop 800229c: bf00 nop 800229e: e7fd b.n 800229c 80022a0: 697a ldr r2, [r7, #20] 80022a2: 4613 mov r3, r2 80022a4: 009b lsls r3, r3, #2 80022a6: 4413 add r3, r2 80022a8: 009b lsls r3, r3, #2 80022aa: 4a12 ldr r2, [pc, #72] @ (80022f4 ) 80022ac: 4413 add r3, r2 80022ae: 613b str r3, [r7, #16] 80022b0: 693b ldr r3, [r7, #16] 80022b2: 685b ldr r3, [r3, #4] 80022b4: 685a ldr r2, [r3, #4] 80022b6: 693b ldr r3, [r7, #16] 80022b8: 605a str r2, [r3, #4] 80022ba: 693b ldr r3, [r7, #16] 80022bc: 685a ldr r2, [r3, #4] 80022be: 693b ldr r3, [r7, #16] 80022c0: 3308 adds r3, #8 80022c2: 429a cmp r2, r3 80022c4: d104 bne.n 80022d0 80022c6: 693b ldr r3, [r7, #16] 80022c8: 685b ldr r3, [r3, #4] 80022ca: 685a ldr r2, [r3, #4] 80022cc: 693b ldr r3, [r7, #16] 80022ce: 605a str r2, [r3, #4] 80022d0: 693b ldr r3, [r7, #16] 80022d2: 685b ldr r3, [r3, #4] 80022d4: 68db ldr r3, [r3, #12] 80022d6: 4a05 ldr r2, [pc, #20] @ (80022ec ) 80022d8: 6013 str r3, [r2, #0] } 80022da: bf00 nop 80022dc: 3720 adds r7, #32 80022de: 46bd mov sp, r7 80022e0: bd80 pop {r7, pc} 80022e2: bf00 nop 80022e4: 20000130 .word 0x20000130 80022e8: 20000124 .word 0x20000124 80022ec: 20000080 .word 0x20000080 80022f0: 2000011c .word 0x2000011c 80022f4: 20000084 .word 0x20000084 080022f8 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 80022f8: b480 push {r7} 80022fa: b083 sub sp, #12 80022fc: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80022fe: 4b0c ldr r3, [pc, #48] @ (8002330 ) 8002300: 681b ldr r3, [r3, #0] 8002302: 681b ldr r3, [r3, #0] 8002304: 2b00 cmp r3, #0 8002306: d104 bne.n 8002312 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8002308: 4b0a ldr r3, [pc, #40] @ (8002334 ) 800230a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800230e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8002310: e008 b.n 8002324 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8002312: 4b07 ldr r3, [pc, #28] @ (8002330 ) 8002314: 681b ldr r3, [r3, #0] 8002316: 68db ldr r3, [r3, #12] 8002318: 68db ldr r3, [r3, #12] 800231a: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800231c: 687b ldr r3, [r7, #4] 800231e: 685b ldr r3, [r3, #4] 8002320: 4a04 ldr r2, [pc, #16] @ (8002334 ) 8002322: 6013 str r3, [r2, #0] } 8002324: bf00 nop 8002326: 370c adds r7, #12 8002328: 46bd mov sp, r7 800232a: f85d 7b04 ldr.w r7, [sp], #4 800232e: 4770 bx lr 8002330: 20000110 .word 0x20000110 8002334: 2000012c .word 0x2000012c ... 08002340 : } /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8002340: 4b07 ldr r3, [pc, #28] @ (8002360 ) 8002342: 6819 ldr r1, [r3, #0] 8002344: 6808 ldr r0, [r1, #0] 8002346: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800234a: f380 8809 msr PSP, r0 800234e: f3bf 8f6f isb sy 8002352: f04f 0000 mov.w r0, #0 8002356: f380 8811 msr BASEPRI, r0 800235a: 4770 bx lr 800235c: f3af 8000 nop.w 08002360 : 8002360: 20000080 .word 0x20000080 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8002364: bf00 nop 8002366: bf00 nop ... 08002370 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8002370: f3ef 8009 mrs r0, PSP 8002374: f3bf 8f6f isb sy 8002378: 4b15 ldr r3, [pc, #84] @ (80023d0 ) 800237a: 681a ldr r2, [r3, #0] 800237c: f01e 0f10 tst.w lr, #16 8002380: bf08 it eq 8002382: ed20 8a10 vstmdbeq r0!, {s16-s31} 8002386: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800238a: 6010 str r0, [r2, #0] 800238c: e92d 0009 stmdb sp!, {r0, r3} 8002390: f04f 0050 mov.w r0, #80 @ 0x50 8002394: f380 8811 msr BASEPRI, r0 8002398: f3bf 8f4f dsb sy 800239c: f3bf 8f6f isb sy 80023a0: f7ff ff28 bl 80021f4 80023a4: f04f 0000 mov.w r0, #0 80023a8: f380 8811 msr BASEPRI, r0 80023ac: bc09 pop {r0, r3} 80023ae: 6819 ldr r1, [r3, #0] 80023b0: 6808 ldr r0, [r1, #0] 80023b2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80023b6: f01e 0f10 tst.w lr, #16 80023ba: bf08 it eq 80023bc: ecb0 8a10 vldmiaeq r0!, {s16-s31} 80023c0: f380 8809 msr PSP, r0 80023c4: f3bf 8f6f isb sy 80023c8: 4770 bx lr 80023ca: bf00 nop 80023cc: f3af 8000 nop.w 080023d0 : 80023d0: 20000080 .word 0x20000080 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 80023d4: bf00 nop 80023d6: bf00 nop 080023d8 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 80023d8: b580 push {r7, lr} 80023da: b082 sub sp, #8 80023dc: af00 add r7, sp, #0 __asm volatile 80023de: f04f 0350 mov.w r3, #80 @ 0x50 80023e2: f383 8811 msr BASEPRI, r3 80023e6: f3bf 8f6f isb sy 80023ea: f3bf 8f4f dsb sy 80023ee: 607b str r3, [r7, #4] } 80023f0: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 80023f2: f7ff fe45 bl 8002080 80023f6: 4603 mov r3, r0 80023f8: 2b00 cmp r3, #0 80023fa: d003 beq.n 8002404 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 80023fc: 4b06 ldr r3, [pc, #24] @ (8002418 ) 80023fe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8002402: 601a str r2, [r3, #0] 8002404: 2300 movs r3, #0 8002406: 603b str r3, [r7, #0] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8002408: 683b ldr r3, [r7, #0] 800240a: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 800240e: bf00 nop } } portENABLE_INTERRUPTS(); } 8002410: bf00 nop 8002412: 3708 adds r7, #8 8002414: 46bd mov sp, r7 8002416: bd80 pop {r7, pc} 8002418: e000ed04 .word 0xe000ed04 0800241c : 800241c: 4402 add r2, r0 800241e: 4603 mov r3, r0 8002420: 4293 cmp r3, r2 8002422: d100 bne.n 8002426 8002424: 4770 bx lr 8002426: f803 1b01 strb.w r1, [r3], #1 800242a: e7f9 b.n 8002420 0800242c <__libc_init_array>: 800242c: b570 push {r4, r5, r6, lr} 800242e: 4d0d ldr r5, [pc, #52] @ (8002464 <__libc_init_array+0x38>) 8002430: 4c0d ldr r4, [pc, #52] @ (8002468 <__libc_init_array+0x3c>) 8002432: 1b64 subs r4, r4, r5 8002434: 10a4 asrs r4, r4, #2 8002436: 2600 movs r6, #0 8002438: 42a6 cmp r6, r4 800243a: d109 bne.n 8002450 <__libc_init_array+0x24> 800243c: 4d0b ldr r5, [pc, #44] @ (800246c <__libc_init_array+0x40>) 800243e: 4c0c ldr r4, [pc, #48] @ (8002470 <__libc_init_array+0x44>) 8002440: f000 f818 bl 8002474 <_init> 8002444: 1b64 subs r4, r4, r5 8002446: 10a4 asrs r4, r4, #2 8002448: 2600 movs r6, #0 800244a: 42a6 cmp r6, r4 800244c: d105 bne.n 800245a <__libc_init_array+0x2e> 800244e: bd70 pop {r4, r5, r6, pc} 8002450: f855 3b04 ldr.w r3, [r5], #4 8002454: 4798 blx r3 8002456: 3601 adds r6, #1 8002458: e7ee b.n 8002438 <__libc_init_array+0xc> 800245a: f855 3b04 ldr.w r3, [r5], #4 800245e: 4798 blx r3 8002460: 3601 adds r6, #1 8002462: e7f2 b.n 800244a <__libc_init_array+0x1e> 8002464: 080024ac .word 0x080024ac 8002468: 080024ac .word 0x080024ac 800246c: 080024ac .word 0x080024ac 8002470: 080024b0 .word 0x080024b0 08002474 <_init>: 8002474: b5f8 push {r3, r4, r5, r6, r7, lr} 8002476: bf00 nop 8002478: bcf8 pop {r3, r4, r5, r6, r7} 800247a: bc08 pop {r3} 800247c: 469e mov lr, r3 800247e: 4770 bx lr 08002480 <_fini>: 8002480: b5f8 push {r3, r4, r5, r6, r7, lr} 8002482: bf00 nop 8002484: bcf8 pop {r3, r4, r5, r6, r7} 8002486: bc08 pop {r3} 8002488: 469e mov lr, r3 800248a: 4770 bx lr