TrafficLightsPlus.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001ac 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007dbc 080001b0 080001b0 000011b0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000018 08007f6c 08007f6c 00008f6c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007f84 08007f84 00009010 2**0 CONTENTS, READONLY 4 .ARM 00000008 08007f84 08007f84 00008f84 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08007f8c 08007f8c 00009010 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007f8c 08007f8c 00008f8c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08007f90 08007f90 00008f90 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000010 20000000 08007f94 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .ccmram 00000000 10000000 10000000 00009010 2**0 CONTENTS 10 .bss 000007a4 20000010 20000010 00009010 2**2 ALLOC 11 ._user_heap_stack 00000604 200007b4 200007b4 00009010 2**0 ALLOC 12 .ARM.attributes 00000030 00000000 00000000 00009010 2**0 CONTENTS, READONLY 13 .debug_info 0002508f 00000000 00000000 00009040 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_abbrev 00004eb9 00000000 00000000 0002e0cf 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00002098 00000000 00000000 00032f88 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 0000195d 00000000 00000000 00035020 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00028e4c 00000000 00000000 0003697d 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 00025485 00000000 00000000 0005f7c9 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000f428b 00000000 00000000 00084c4e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00178ed9 2**0 CONTENTS, READONLY 21 .debug_frame 00008c0c 00000000 00000000 00178f1c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 00000051 00000000 00000000 00181b28 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001b0 <__do_global_dtors_aux>: 80001b0: b510 push {r4, lr} 80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>) 80001b4: 7823 ldrb r3, [r4, #0] 80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16> 80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>) 80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12> 80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>) 80001be: f3af 8000 nop.w 80001c2: 2301 movs r3, #1 80001c4: 7023 strb r3, [r4, #0] 80001c6: bd10 pop {r4, pc} 80001c8: 20000010 .word 0x20000010 80001cc: 00000000 .word 0x00000000 80001d0: 08007f54 .word 0x08007f54 080001d4 : 80001d4: b508 push {r3, lr} 80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 ) 80001d8: b11b cbz r3, 80001e2 80001da: 4903 ldr r1, [pc, #12] @ (80001e8 ) 80001dc: 4803 ldr r0, [pc, #12] @ (80001ec ) 80001de: f3af 8000 nop.w 80001e2: bd08 pop {r3, pc} 80001e4: 00000000 .word 0x00000000 80001e8: 20000014 .word 0x20000014 80001ec: 08007f54 .word 0x08007f54 080001f0 <__aeabi_uldivmod>: 80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18> 80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18> 80001f4: 2900 cmp r1, #0 80001f6: bf08 it eq 80001f8: 2800 cmpeq r0, #0 80001fa: bf1c itt ne 80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000204: f000 b988 b.w 8000518 <__aeabi_idiv0> 8000208: f1ad 0c08 sub.w ip, sp, #8 800020c: e96d ce04 strd ip, lr, [sp, #-16]! 8000210: f000 f806 bl 8000220 <__udivmoddi4> 8000214: f8dd e004 ldr.w lr, [sp, #4] 8000218: e9dd 2302 ldrd r2, r3, [sp, #8] 800021c: b004 add sp, #16 800021e: 4770 bx lr 08000220 <__udivmoddi4>: 8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000224: 9d08 ldr r5, [sp, #32] 8000226: 468e mov lr, r1 8000228: 4604 mov r4, r0 800022a: 4688 mov r8, r1 800022c: 2b00 cmp r3, #0 800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6> 8000230: 428a cmp r2, r1 8000232: 4617 mov r7, r2 8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc> 8000236: fab2 f682 clz r6, r2 800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30> 800023c: f1c6 0320 rsb r3, r6, #32 8000240: fa01 f806 lsl.w r8, r1, r6 8000244: fa20 f303 lsr.w r3, r0, r3 8000248: 40b7 lsls r7, r6 800024a: ea43 0808 orr.w r8, r3, r8 800024e: 40b4 lsls r4, r6 8000250: ea4f 4e17 mov.w lr, r7, lsr #16 8000254: fa1f fc87 uxth.w ip, r7 8000258: fbb8 f1fe udiv r1, r8, lr 800025c: 0c23 lsrs r3, r4, #16 800025e: fb0e 8811 mls r8, lr, r1, r8 8000262: ea43 4308 orr.w r3, r3, r8, lsl #16 8000266: fb01 f20c mul.w r2, r1, ip 800026a: 429a cmp r2, r3 800026c: d909 bls.n 8000282 <__udivmoddi4+0x62> 800026e: 18fb adds r3, r7, r3 8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c> 8000278: 429a cmp r2, r3 800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c> 800027e: 3902 subs r1, #2 8000280: 443b add r3, r7 8000282: 1a9a subs r2, r3, r2 8000284: b2a3 uxth r3, r4 8000286: fbb2 f0fe udiv r0, r2, lr 800028a: fb0e 2210 mls r2, lr, r0, r2 800028e: ea43 4302 orr.w r3, r3, r2, lsl #16 8000292: fb00 fc0c mul.w ip, r0, ip 8000296: 459c cmp ip, r3 8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e> 800029a: 18fb adds r3, r7, r3 800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230> 80002a4: 459c cmp ip, r3 80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230> 80002aa: 443b add r3, r7 80002ac: 3802 subs r0, #2 80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16 80002b2: eba3 030c sub.w r3, r3, ip 80002b6: 2100 movs r1, #0 80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2> 80002ba: 40f3 lsrs r3, r6 80002bc: 2200 movs r2, #0 80002be: e9c5 3200 strd r3, r2, [r5] 80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002c6: 428b cmp r3, r1 80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6> 80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0> 80002cc: e9c5 0100 strd r0, r1, [r5] 80002d0: 2100 movs r1, #0 80002d2: 4608 mov r0, r1 80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2> 80002d6: fab3 f183 clz r1, r3 80002da: 2900 cmp r1, #0 80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c> 80002de: 4573 cmp r3, lr 80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8> 80002e2: 4282 cmp r2, r0 80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2> 80002e8: 1a84 subs r4, r0, r2 80002ea: eb6e 0203 sbc.w r2, lr, r3 80002ee: 2001 movs r0, #1 80002f0: 4690 mov r8, r2 80002f2: 2d00 cmp r5, #0 80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2> 80002f6: e9c5 4800 strd r4, r8, [r5] 80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2> 80002fc: 2a00 cmp r2, #0 80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202> 8000302: fab2 f682 clz r6, r2 8000306: 2e00 cmp r6, #0 8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234> 800030c: 1a8a subs r2, r1, r2 800030e: 0c03 lsrs r3, r0, #16 8000310: ea4f 4e17 mov.w lr, r7, lsr #16 8000314: b280 uxth r0, r0 8000316: b2bc uxth r4, r7 8000318: 2101 movs r1, #1 800031a: fbb2 fcfe udiv ip, r2, lr 800031e: fb0e 221c mls r2, lr, ip, r2 8000322: ea43 4302 orr.w r3, r3, r2, lsl #16 8000326: fb04 f20c mul.w r2, r4, ip 800032a: 429a cmp r2, r3 800032c: d907 bls.n 800033e <__udivmoddi4+0x11e> 800032e: 18fb adds r3, r7, r3 8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c> 8000336: 429a cmp r2, r3 8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc> 800033c: 46c4 mov ip, r8 800033e: 1a9b subs r3, r3, r2 8000340: fbb3 f2fe udiv r2, r3, lr 8000344: fb0e 3312 mls r3, lr, r2, r3 8000348: ea40 4303 orr.w r3, r0, r3, lsl #16 800034c: fb02 f404 mul.w r4, r2, r4 8000350: 429c cmp r4, r3 8000352: d907 bls.n 8000364 <__udivmoddi4+0x144> 8000354: 18fb adds r3, r7, r3 8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142> 800035c: 429c cmp r4, r3 800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6> 8000362: 4602 mov r2, r0 8000364: 1b1b subs r3, r3, r4 8000366: ea42 400c orr.w r0, r2, ip, lsl #16 800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98> 800036c: f1c1 0620 rsb r6, r1, #32 8000370: 408b lsls r3, r1 8000372: fa22 f706 lsr.w r7, r2, r6 8000376: 431f orrs r7, r3 8000378: fa0e f401 lsl.w r4, lr, r1 800037c: fa20 f306 lsr.w r3, r0, r6 8000380: fa2e fe06 lsr.w lr, lr, r6 8000384: ea4f 4917 mov.w r9, r7, lsr #16 8000388: 4323 orrs r3, r4 800038a: fa00 f801 lsl.w r8, r0, r1 800038e: fa1f fc87 uxth.w ip, r7 8000392: fbbe f0f9 udiv r0, lr, r9 8000396: 0c1c lsrs r4, r3, #16 8000398: fb09 ee10 mls lr, r9, r0, lr 800039c: ea44 440e orr.w r4, r4, lr, lsl #16 80003a0: fb00 fe0c mul.w lr, r0, ip 80003a4: 45a6 cmp lr, r4 80003a6: fa02 f201 lsl.w r2, r2, r1 80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0> 80003ac: 193c adds r4, r7, r4 80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce> 80003b6: 45a6 cmp lr, r4 80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce> 80003bc: 3802 subs r0, #2 80003be: 443c add r4, r7 80003c0: eba4 040e sub.w r4, r4, lr 80003c4: fa1f fe83 uxth.w lr, r3 80003c8: fbb4 f3f9 udiv r3, r4, r9 80003cc: fb09 4413 mls r4, r9, r3, r4 80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003d4: fb03 fc0c mul.w ip, r3, ip 80003d8: 45a4 cmp ip, r4 80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce> 80003dc: 193c adds r4, r7, r4 80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca> 80003e6: 45a4 cmp ip, r4 80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca> 80003ea: 3b02 subs r3, #2 80003ec: 443c add r4, r7 80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16 80003f2: eba4 040c sub.w r4, r4, ip 80003f6: fba0 ec02 umull lr, ip, r0, r2 80003fa: 4564 cmp r4, ip 80003fc: 4673 mov r3, lr 80003fe: 46e1 mov r9, ip 8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8> 8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4> 8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe> 8000406: ebb8 0203 subs.w r2, r8, r3 800040a: eb64 0409 sbc.w r4, r4, r9 800040e: fa04 f606 lsl.w r6, r4, r6 8000412: fa22 f301 lsr.w r3, r2, r1 8000416: 431e orrs r6, r3 8000418: 40cc lsrs r4, r1 800041a: e9c5 6400 strd r6, r4, [r5] 800041e: 2100 movs r1, #0 8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2> 8000422: fbb1 fcf2 udiv ip, r1, r2 8000426: 0c01 lsrs r1, r0, #16 8000428: ea41 410e orr.w r1, r1, lr, lsl #16 800042c: b280 uxth r0, r0 800042e: ea40 4201 orr.w r2, r0, r1, lsl #16 8000432: 463b mov r3, r7 8000434: 4638 mov r0, r7 8000436: 463c mov r4, r7 8000438: 46b8 mov r8, r7 800043a: 46be mov lr, r7 800043c: 2620 movs r6, #32 800043e: fbb1 f1f7 udiv r1, r1, r7 8000442: eba2 0208 sub.w r2, r2, r8 8000446: ea41 410c orr.w r1, r1, ip, lsl #16 800044a: e766 b.n 800031a <__udivmoddi4+0xfa> 800044c: 4601 mov r1, r0 800044e: e718 b.n 8000282 <__udivmoddi4+0x62> 8000450: 4610 mov r0, r2 8000452: e72c b.n 80002ae <__udivmoddi4+0x8e> 8000454: f1c6 0220 rsb r2, r6, #32 8000458: fa2e f302 lsr.w r3, lr, r2 800045c: 40b7 lsls r7, r6 800045e: 40b1 lsls r1, r6 8000460: fa20 f202 lsr.w r2, r0, r2 8000464: ea4f 4e17 mov.w lr, r7, lsr #16 8000468: 430a orrs r2, r1 800046a: fbb3 f8fe udiv r8, r3, lr 800046e: b2bc uxth r4, r7 8000470: fb0e 3318 mls r3, lr, r8, r3 8000474: 0c11 lsrs r1, r2, #16 8000476: ea41 4103 orr.w r1, r1, r3, lsl #16 800047a: fb08 f904 mul.w r9, r8, r4 800047e: 40b0 lsls r0, r6 8000480: 4589 cmp r9, r1 8000482: ea4f 4310 mov.w r3, r0, lsr #16 8000486: b280 uxth r0, r0 8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8> 800048a: 1879 adds r1, r7, r1 800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276> 8000492: 4589 cmp r9, r1 8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6> 8000496: eba1 0109 sub.w r1, r1, r9 800049a: fbb1 f9fe udiv r9, r1, lr 800049e: fb09 f804 mul.w r8, r9, r4 80004a2: fb0e 1119 mls r1, lr, r9, r1 80004a6: b292 uxth r2, r2 80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16 80004ac: 4542 cmp r2, r8 80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4> 80004b0: 18ba adds r2, r7, r2 80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222> 80004b8: 4542 cmp r2, r8 80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222> 80004bc: f1a9 0102 sub.w r1, r9, #2 80004c0: 443a add r2, r7 80004c2: e7be b.n 8000442 <__udivmoddi4+0x222> 80004c4: 45f0 cmp r8, lr 80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4> 80004c8: ebbe 0302 subs.w r3, lr, r2 80004cc: eb6c 0c07 sbc.w ip, ip, r7 80004d0: 3801 subs r0, #1 80004d2: 46e1 mov r9, ip 80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4> 80004d6: eba7 0909 sub.w r9, r7, r9 80004da: 4449 add r1, r9 80004dc: f1a8 0c02 sub.w ip, r8, #2 80004e0: fbb1 f9fe udiv r9, r1, lr 80004e4: fb09 f804 mul.w r8, r9, r4 80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282> 80004ea: 4673 mov r3, lr 80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce> 80004ee: 4650 mov r0, sl 80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0> 80004f2: 4608 mov r0, r1 80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2> 80004f6: 443b add r3, r7 80004f8: 3a02 subs r2, #2 80004fa: e733 b.n 8000364 <__udivmoddi4+0x144> 80004fc: f1ac 0c02 sub.w ip, ip, #2 8000500: 443b add r3, r7 8000502: e71c b.n 800033e <__udivmoddi4+0x11e> 8000504: 4649 mov r1, r9 8000506: e79c b.n 8000442 <__udivmoddi4+0x222> 8000508: eba1 0109 sub.w r1, r1, r9 800050c: 46c4 mov ip, r8 800050e: fbb1 f9fe udiv r9, r1, lr 8000512: fb09 f804 mul.w r8, r9, r4 8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282> 08000518 <__aeabi_idiv0>: 8000518: 4770 bx lr 800051a: bf00 nop 0800051c : uint8_t trafflight_index = 0; void starttick(void) { 800051c: b580 push {r7, lr} 800051e: af00 add r7, sp, #0 trafftick_last = HAL_GetTick(); 8000520: f001 f8e0 bl 80016e4 8000524: 4603 mov r3, r0 8000526: 4a04 ldr r2, [pc, #16] @ (8000538 ) 8000528: 6013 str r3, [r2, #0] walktick_last = HAL_GetTick(); 800052a: f001 f8db bl 80016e4 800052e: 4603 mov r3, r0 8000530: 4a02 ldr r2, [pc, #8] @ (800053c ) 8000532: 6013 str r3, [r2, #0] } 8000534: bf00 nop 8000536: bd80 pop {r7, pc} 8000538: 2000002c .word 0x2000002c 800053c: 20000030 .word 0x20000030 08000540 : void trafflight(int traffSPD, int walkSPD) { 8000540: b580 push {r7, lr} 8000542: b084 sub sp, #16 8000544: af00 add r7, sp, #0 8000546: 6078 str r0, [r7, #4] 8000548: 6039 str r1, [r7, #0] uint32_t trafftick_curr = HAL_GetTick(); 800054a: f001 f8cb bl 80016e4 800054e: 60f8 str r0, [r7, #12] if ((trafftick_curr - trafftick_last) >= traffSPD) { 8000550: 4b2b ldr r3, [pc, #172] @ (8000600 ) 8000552: 681b ldr r3, [r3, #0] 8000554: 68fa ldr r2, [r7, #12] 8000556: 1ad2 subs r2, r2, r3 8000558: 687b ldr r3, [r7, #4] 800055a: 429a cmp r2, r3 800055c: d33d bcc.n 80005da HAL_GPIO_WritePin(R_Prt, R_Pin, GPIO_PIN_RESET); 800055e: 2200 movs r2, #0 8000560: 2104 movs r1, #4 8000562: 4828 ldr r0, [pc, #160] @ (8000604 ) 8000564: f001 fd60 bl 8002028 HAL_GPIO_WritePin(Y_Prt, Y_Pin, GPIO_PIN_RESET); 8000568: 2200 movs r2, #0 800056a: 2108 movs r1, #8 800056c: 4825 ldr r0, [pc, #148] @ (8000604 ) 800056e: f001 fd5b bl 8002028 HAL_GPIO_WritePin(G_Prt, G_Pin, GPIO_PIN_RESET); 8000572: 2200 movs r2, #0 8000574: 2110 movs r1, #16 8000576: 4823 ldr r0, [pc, #140] @ (8000604 ) 8000578: f001 fd56 bl 8002028 switch (trafflight_index) { 800057c: 4b22 ldr r3, [pc, #136] @ (8000608 ) 800057e: 781b ldrb r3, [r3, #0] 8000580: 2b02 cmp r3, #2 8000582: d012 beq.n 80005aa 8000584: 2b02 cmp r3, #2 8000586: dc16 bgt.n 80005b6 8000588: 2b00 cmp r3, #0 800058a: d002 beq.n 8000592 800058c: 2b01 cmp r3, #1 800058e: d006 beq.n 800059e 8000590: e011 b.n 80005b6 case 0: HAL_GPIO_WritePin(R_Prt, R_Pin, GPIO_PIN_SET); 8000592: 2201 movs r2, #1 8000594: 2104 movs r1, #4 8000596: 481b ldr r0, [pc, #108] @ (8000604 ) 8000598: f001 fd46 bl 8002028 break; 800059c: e00b b.n 80005b6 case 1: HAL_GPIO_WritePin(Y_Prt, Y_Pin, GPIO_PIN_SET); 800059e: 2201 movs r2, #1 80005a0: 2108 movs r1, #8 80005a2: 4818 ldr r0, [pc, #96] @ (8000604 ) 80005a4: f001 fd40 bl 8002028 break; 80005a8: e005 b.n 80005b6 case 2: HAL_GPIO_WritePin(G_Prt, G_Pin, GPIO_PIN_SET); 80005aa: 2201 movs r2, #1 80005ac: 2110 movs r1, #16 80005ae: 4815 ldr r0, [pc, #84] @ (8000604 ) 80005b0: f001 fd3a bl 8002028 break; 80005b4: bf00 nop } trafflight_index = (trafflight_index + 1) % 3; 80005b6: 4b14 ldr r3, [pc, #80] @ (8000608 ) 80005b8: 781b ldrb r3, [r3, #0] 80005ba: 1c5a adds r2, r3, #1 80005bc: 4b13 ldr r3, [pc, #76] @ (800060c ) 80005be: fb83 3102 smull r3, r1, r3, r2 80005c2: 17d3 asrs r3, r2, #31 80005c4: 1ac9 subs r1, r1, r3 80005c6: 460b mov r3, r1 80005c8: 005b lsls r3, r3, #1 80005ca: 440b add r3, r1 80005cc: 1ad1 subs r1, r2, r3 80005ce: b2ca uxtb r2, r1 80005d0: 4b0d ldr r3, [pc, #52] @ (8000608 ) 80005d2: 701a strb r2, [r3, #0] trafftick_last = trafftick_curr; 80005d4: 4a0a ldr r2, [pc, #40] @ (8000600 ) 80005d6: 68fb ldr r3, [r7, #12] 80005d8: 6013 str r3, [r2, #0] } if ((trafftick_curr - walktick_last) >= walkSPD) { 80005da: 4b0d ldr r3, [pc, #52] @ (8000610 ) 80005dc: 681b ldr r3, [r3, #0] 80005de: 68fa ldr r2, [r7, #12] 80005e0: 1ad2 subs r2, r2, r3 80005e2: 683b ldr r3, [r7, #0] 80005e4: 429a cmp r2, r3 80005e6: d306 bcc.n 80005f6 HAL_GPIO_TogglePin(W_Prt, W_Pin); 80005e8: 2120 movs r1, #32 80005ea: 4806 ldr r0, [pc, #24] @ (8000604 ) 80005ec: f001 fd35 bl 800205a walktick_last = trafftick_curr; 80005f0: 4a07 ldr r2, [pc, #28] @ (8000610 ) 80005f2: 68fb ldr r3, [r7, #12] 80005f4: 6013 str r3, [r2, #0] } } 80005f6: bf00 nop 80005f8: 3710 adds r7, #16 80005fa: 46bd mov sp, r7 80005fc: bd80 pop {r7, pc} 80005fe: bf00 nop 8000600: 2000002c .word 0x2000002c 8000604: 40021000 .word 0x40021000 8000608: 20000034 .word 0x20000034 800060c: 55555556 .word 0x55555556 8000610: 20000030 .word 0x20000030 08000614 : } /* USER CODE END 2 */ /* USER CODE BEGIN 4 */ __weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000614: b480 push {r7} 8000616: b083 sub sp, #12 8000618: af00 add r7, sp, #0 800061a: 6078 str r0, [r7, #4] 800061c: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800061e: bf00 nop 8000620: 370c adds r7, #12 8000622: 46bd mov sp, r7 8000624: f85d 7b04 ldr.w r7, [sp], #4 8000628: 4770 bx lr 0800062a
: /** * @brief The application entry point. * @retval int */ int main(void) { 800062a: b580 push {r7, lr} 800062c: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 800062e: f001 f823 bl 8001678 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000632: f000 f81b bl 800066c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000636: f000 fa89 bl 8000b4c MX_CRC_Init(); 800063a: f000 f881 bl 8000740 MX_DMA2D_Init(); 800063e: f000 f893 bl 8000768 MX_FMC_Init(); 8000642: f000 fa33 bl 8000aac MX_I2C3_Init(); 8000646: f000 f8c1 bl 80007cc MX_LTDC_Init(); 800064a: f000 f8ff bl 800084c MX_SPI5_Init(); 800064e: f000 f97d bl 800094c MX_TIM1_Init(); 8000652: f000 f9b1 bl 80009b8 MX_USART1_UART_Init(); 8000656: f000 f9ff bl 8000a58 /* We should never get here as control is now taken by the scheduler */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ starttick(); 800065a: f7ff ff5f bl 800051c while (1) { trafflight(2*1000, 10*1000); 800065e: f242 7110 movw r1, #10000 @ 0x2710 8000662: f44f 60fa mov.w r0, #2000 @ 0x7d0 8000666: f7ff ff6b bl 8000540 800066a: e7f8 b.n 800065e 0800066c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800066c: b580 push {r7, lr} 800066e: b094 sub sp, #80 @ 0x50 8000670: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8000672: f107 0320 add.w r3, r7, #32 8000676: 2230 movs r2, #48 @ 0x30 8000678: 2100 movs r1, #0 800067a: 4618 mov r0, r3 800067c: f007 fc30 bl 8007ee0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8000680: f107 030c add.w r3, r7, #12 8000684: 2200 movs r2, #0 8000686: 601a str r2, [r3, #0] 8000688: 605a str r2, [r3, #4] 800068a: 609a str r2, [r3, #8] 800068c: 60da str r2, [r3, #12] 800068e: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000690: 2300 movs r3, #0 8000692: 60bb str r3, [r7, #8] 8000694: 4b28 ldr r3, [pc, #160] @ (8000738 ) 8000696: 6c1b ldr r3, [r3, #64] @ 0x40 8000698: 4a27 ldr r2, [pc, #156] @ (8000738 ) 800069a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 800069e: 6413 str r3, [r2, #64] @ 0x40 80006a0: 4b25 ldr r3, [pc, #148] @ (8000738 ) 80006a2: 6c1b ldr r3, [r3, #64] @ 0x40 80006a4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80006a8: 60bb str r3, [r7, #8] 80006aa: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 80006ac: 2300 movs r3, #0 80006ae: 607b str r3, [r7, #4] 80006b0: 4b22 ldr r3, [pc, #136] @ (800073c ) 80006b2: 681b ldr r3, [r3, #0] 80006b4: f423 4340 bic.w r3, r3, #49152 @ 0xc000 80006b8: 4a20 ldr r2, [pc, #128] @ (800073c ) 80006ba: f443 4380 orr.w r3, r3, #16384 @ 0x4000 80006be: 6013 str r3, [r2, #0] 80006c0: 4b1e ldr r3, [pc, #120] @ (800073c ) 80006c2: 681b ldr r3, [r3, #0] 80006c4: f403 4340 and.w r3, r3, #49152 @ 0xc000 80006c8: 607b str r3, [r7, #4] 80006ca: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 80006cc: 2301 movs r3, #1 80006ce: 623b str r3, [r7, #32] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 80006d0: f44f 3380 mov.w r3, #65536 @ 0x10000 80006d4: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 80006d6: 2302 movs r3, #2 80006d8: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 80006da: f44f 0380 mov.w r3, #4194304 @ 0x400000 80006de: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLM = 4; 80006e0: 2304 movs r3, #4 80006e2: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLN = 72; 80006e4: 2348 movs r3, #72 @ 0x48 80006e6: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 80006e8: 2302 movs r3, #2 80006ea: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLQ = 3; 80006ec: 2303 movs r3, #3 80006ee: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80006f0: f107 0320 add.w r3, r7, #32 80006f4: 4618 mov r0, r3 80006f6: f003 ff41 bl 800457c 80006fa: 4603 mov r3, r0 80006fc: 2b00 cmp r3, #0 80006fe: d001 beq.n 8000704 { Error_Handler(); 8000700: f000 fb5a bl 8000db8 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8000704: 230f movs r3, #15 8000706: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000708: 2302 movs r3, #2 800070a: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 800070c: 2300 movs r3, #0 800070e: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000710: f44f 5380 mov.w r3, #4096 @ 0x1000 8000714: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8000716: 2300 movs r3, #0 8000718: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 800071a: f107 030c add.w r3, r7, #12 800071e: 2102 movs r1, #2 8000720: 4618 mov r0, r3 8000722: f004 f9a3 bl 8004a6c 8000726: 4603 mov r3, r0 8000728: 2b00 cmp r3, #0 800072a: d001 beq.n 8000730 { Error_Handler(); 800072c: f000 fb44 bl 8000db8 } } 8000730: bf00 nop 8000732: 3750 adds r7, #80 @ 0x50 8000734: 46bd mov sp, r7 8000736: bd80 pop {r7, pc} 8000738: 40023800 .word 0x40023800 800073c: 40007000 .word 0x40007000 08000740 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 8000740: b580 push {r7, lr} 8000742: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 8000744: 4b06 ldr r3, [pc, #24] @ (8000760 ) 8000746: 4a07 ldr r2, [pc, #28] @ (8000764 ) 8000748: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 800074a: 4805 ldr r0, [pc, #20] @ (8000760 ) 800074c: f001 f8b8 bl 80018c0 8000750: 4603 mov r3, r0 8000752: 2b00 cmp r3, #0 8000754: d001 beq.n 800075a { Error_Handler(); 8000756: f000 fb2f bl 8000db8 } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 800075a: bf00 nop 800075c: bd80 pop {r7, pc} 800075e: bf00 nop 8000760: 20000038 .word 0x20000038 8000764: 40023000 .word 0x40023000 08000768 : * @brief DMA2D Initialization Function * @param None * @retval None */ static void MX_DMA2D_Init(void) { 8000768: b580 push {r7, lr} 800076a: af00 add r7, sp, #0 /* USER CODE END DMA2D_Init 0 */ /* USER CODE BEGIN DMA2D_Init 1 */ /* USER CODE END DMA2D_Init 1 */ hdma2d.Instance = DMA2D; 800076c: 4b15 ldr r3, [pc, #84] @ (80007c4 ) 800076e: 4a16 ldr r2, [pc, #88] @ (80007c8 ) 8000770: 601a str r2, [r3, #0] hdma2d.Init.Mode = DMA2D_M2M; 8000772: 4b14 ldr r3, [pc, #80] @ (80007c4 ) 8000774: 2200 movs r2, #0 8000776: 605a str r2, [r3, #4] hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; 8000778: 4b12 ldr r3, [pc, #72] @ (80007c4 ) 800077a: 2200 movs r2, #0 800077c: 609a str r2, [r3, #8] hdma2d.Init.OutputOffset = 0; 800077e: 4b11 ldr r3, [pc, #68] @ (80007c4 ) 8000780: 2200 movs r2, #0 8000782: 60da str r2, [r3, #12] hdma2d.LayerCfg[1].InputOffset = 0; 8000784: 4b0f ldr r3, [pc, #60] @ (80007c4 ) 8000786: 2200 movs r2, #0 8000788: 629a str r2, [r3, #40] @ 0x28 hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; 800078a: 4b0e ldr r3, [pc, #56] @ (80007c4 ) 800078c: 2200 movs r2, #0 800078e: 62da str r2, [r3, #44] @ 0x2c hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; 8000790: 4b0c ldr r3, [pc, #48] @ (80007c4 ) 8000792: 2200 movs r2, #0 8000794: 631a str r2, [r3, #48] @ 0x30 hdma2d.LayerCfg[1].InputAlpha = 0; 8000796: 4b0b ldr r3, [pc, #44] @ (80007c4 ) 8000798: 2200 movs r2, #0 800079a: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) 800079c: 4809 ldr r0, [pc, #36] @ (80007c4 ) 800079e: f001 f8ab bl 80018f8 80007a2: 4603 mov r3, r0 80007a4: 2b00 cmp r3, #0 80007a6: d001 beq.n 80007ac { Error_Handler(); 80007a8: f000 fb06 bl 8000db8 } if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) 80007ac: 2101 movs r1, #1 80007ae: 4805 ldr r0, [pc, #20] @ (80007c4 ) 80007b0: f001 f9fc bl 8001bac 80007b4: 4603 mov r3, r0 80007b6: 2b00 cmp r3, #0 80007b8: d001 beq.n 80007be { Error_Handler(); 80007ba: f000 fafd bl 8000db8 } /* USER CODE BEGIN DMA2D_Init 2 */ /* USER CODE END DMA2D_Init 2 */ } 80007be: bf00 nop 80007c0: bd80 pop {r7, pc} 80007c2: bf00 nop 80007c4: 20000040 .word 0x20000040 80007c8: 4002b000 .word 0x4002b000 080007cc : * @brief I2C3 Initialization Function * @param None * @retval None */ static void MX_I2C3_Init(void) { 80007cc: b580 push {r7, lr} 80007ce: af00 add r7, sp, #0 /* USER CODE END I2C3_Init 0 */ /* USER CODE BEGIN I2C3_Init 1 */ /* USER CODE END I2C3_Init 1 */ hi2c3.Instance = I2C3; 80007d0: 4b1b ldr r3, [pc, #108] @ (8000840 ) 80007d2: 4a1c ldr r2, [pc, #112] @ (8000844 ) 80007d4: 601a str r2, [r3, #0] hi2c3.Init.ClockSpeed = 100000; 80007d6: 4b1a ldr r3, [pc, #104] @ (8000840 ) 80007d8: 4a1b ldr r2, [pc, #108] @ (8000848 ) 80007da: 605a str r2, [r3, #4] hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2; 80007dc: 4b18 ldr r3, [pc, #96] @ (8000840 ) 80007de: 2200 movs r2, #0 80007e0: 609a str r2, [r3, #8] hi2c3.Init.OwnAddress1 = 0; 80007e2: 4b17 ldr r3, [pc, #92] @ (8000840 ) 80007e4: 2200 movs r2, #0 80007e6: 60da str r2, [r3, #12] hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 80007e8: 4b15 ldr r3, [pc, #84] @ (8000840 ) 80007ea: f44f 4280 mov.w r2, #16384 @ 0x4000 80007ee: 611a str r2, [r3, #16] hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 80007f0: 4b13 ldr r3, [pc, #76] @ (8000840 ) 80007f2: 2200 movs r2, #0 80007f4: 615a str r2, [r3, #20] hi2c3.Init.OwnAddress2 = 0; 80007f6: 4b12 ldr r3, [pc, #72] @ (8000840 ) 80007f8: 2200 movs r2, #0 80007fa: 619a str r2, [r3, #24] hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 80007fc: 4b10 ldr r3, [pc, #64] @ (8000840 ) 80007fe: 2200 movs r2, #0 8000800: 61da str r2, [r3, #28] hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 8000802: 4b0f ldr r3, [pc, #60] @ (8000840 ) 8000804: 2200 movs r2, #0 8000806: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c3) != HAL_OK) 8000808: 480d ldr r0, [pc, #52] @ (8000840 ) 800080a: f003 f9e7 bl 8003bdc 800080e: 4603 mov r3, r0 8000810: 2b00 cmp r3, #0 8000812: d001 beq.n 8000818 { Error_Handler(); 8000814: f000 fad0 bl 8000db8 } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000818: 2100 movs r1, #0 800081a: 4809 ldr r0, [pc, #36] @ (8000840 ) 800081c: f003 fb22 bl 8003e64 8000820: 4603 mov r3, r0 8000822: 2b00 cmp r3, #0 8000824: d001 beq.n 800082a { Error_Handler(); 8000826: f000 fac7 bl 8000db8 } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) 800082a: 2100 movs r1, #0 800082c: 4804 ldr r0, [pc, #16] @ (8000840 ) 800082e: f003 fb55 bl 8003edc 8000832: 4603 mov r3, r0 8000834: 2b00 cmp r3, #0 8000836: d001 beq.n 800083c { Error_Handler(); 8000838: f000 fabe bl 8000db8 } /* USER CODE BEGIN I2C3_Init 2 */ /* USER CODE END I2C3_Init 2 */ } 800083c: bf00 nop 800083e: bd80 pop {r7, pc} 8000840: 20000080 .word 0x20000080 8000844: 40005c00 .word 0x40005c00 8000848: 000186a0 .word 0x000186a0 0800084c : * @brief LTDC Initialization Function * @param None * @retval None */ static void MX_LTDC_Init(void) { 800084c: b580 push {r7, lr} 800084e: b08e sub sp, #56 @ 0x38 8000850: af00 add r7, sp, #0 /* USER CODE BEGIN LTDC_Init 0 */ /* USER CODE END LTDC_Init 0 */ LTDC_LayerCfgTypeDef pLayerCfg = {0}; 8000852: 1d3b adds r3, r7, #4 8000854: 2234 movs r2, #52 @ 0x34 8000856: 2100 movs r1, #0 8000858: 4618 mov r0, r3 800085a: f007 fb41 bl 8007ee0 /* USER CODE BEGIN LTDC_Init 1 */ /* USER CODE END LTDC_Init 1 */ hltdc.Instance = LTDC; 800085e: 4b39 ldr r3, [pc, #228] @ (8000944 ) 8000860: 4a39 ldr r2, [pc, #228] @ (8000948 ) 8000862: 601a str r2, [r3, #0] hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; 8000864: 4b37 ldr r3, [pc, #220] @ (8000944 ) 8000866: 2200 movs r2, #0 8000868: 605a str r2, [r3, #4] hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; 800086a: 4b36 ldr r3, [pc, #216] @ (8000944 ) 800086c: 2200 movs r2, #0 800086e: 609a str r2, [r3, #8] hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; 8000870: 4b34 ldr r3, [pc, #208] @ (8000944 ) 8000872: 2200 movs r2, #0 8000874: 60da str r2, [r3, #12] hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; 8000876: 4b33 ldr r3, [pc, #204] @ (8000944 ) 8000878: 2200 movs r2, #0 800087a: 611a str r2, [r3, #16] hltdc.Init.HorizontalSync = 9; 800087c: 4b31 ldr r3, [pc, #196] @ (8000944 ) 800087e: 2209 movs r2, #9 8000880: 615a str r2, [r3, #20] hltdc.Init.VerticalSync = 1; 8000882: 4b30 ldr r3, [pc, #192] @ (8000944 ) 8000884: 2201 movs r2, #1 8000886: 619a str r2, [r3, #24] hltdc.Init.AccumulatedHBP = 29; 8000888: 4b2e ldr r3, [pc, #184] @ (8000944 ) 800088a: 221d movs r2, #29 800088c: 61da str r2, [r3, #28] hltdc.Init.AccumulatedVBP = 3; 800088e: 4b2d ldr r3, [pc, #180] @ (8000944 ) 8000890: 2203 movs r2, #3 8000892: 621a str r2, [r3, #32] hltdc.Init.AccumulatedActiveW = 269; 8000894: 4b2b ldr r3, [pc, #172] @ (8000944 ) 8000896: f240 120d movw r2, #269 @ 0x10d 800089a: 625a str r2, [r3, #36] @ 0x24 hltdc.Init.AccumulatedActiveH = 323; 800089c: 4b29 ldr r3, [pc, #164] @ (8000944 ) 800089e: f240 1243 movw r2, #323 @ 0x143 80008a2: 629a str r2, [r3, #40] @ 0x28 hltdc.Init.TotalWidth = 279; 80008a4: 4b27 ldr r3, [pc, #156] @ (8000944 ) 80008a6: f240 1217 movw r2, #279 @ 0x117 80008aa: 62da str r2, [r3, #44] @ 0x2c hltdc.Init.TotalHeigh = 327; 80008ac: 4b25 ldr r3, [pc, #148] @ (8000944 ) 80008ae: f240 1247 movw r2, #327 @ 0x147 80008b2: 631a str r2, [r3, #48] @ 0x30 hltdc.Init.Backcolor.Blue = 0; 80008b4: 4b23 ldr r3, [pc, #140] @ (8000944 ) 80008b6: 2200 movs r2, #0 80008b8: f883 2034 strb.w r2, [r3, #52] @ 0x34 hltdc.Init.Backcolor.Green = 0; 80008bc: 4b21 ldr r3, [pc, #132] @ (8000944 ) 80008be: 2200 movs r2, #0 80008c0: f883 2035 strb.w r2, [r3, #53] @ 0x35 hltdc.Init.Backcolor.Red = 0; 80008c4: 4b1f ldr r3, [pc, #124] @ (8000944 ) 80008c6: 2200 movs r2, #0 80008c8: f883 2036 strb.w r2, [r3, #54] @ 0x36 if (HAL_LTDC_Init(&hltdc) != HAL_OK) 80008cc: 481d ldr r0, [pc, #116] @ (8000944 ) 80008ce: f003 fb44 bl 8003f5a 80008d2: 4603 mov r3, r0 80008d4: 2b00 cmp r3, #0 80008d6: d001 beq.n 80008dc { Error_Handler(); 80008d8: f000 fa6e bl 8000db8 } pLayerCfg.WindowX0 = 0; 80008dc: 2300 movs r3, #0 80008de: 607b str r3, [r7, #4] pLayerCfg.WindowX1 = 240; 80008e0: 23f0 movs r3, #240 @ 0xf0 80008e2: 60bb str r3, [r7, #8] pLayerCfg.WindowY0 = 0; 80008e4: 2300 movs r3, #0 80008e6: 60fb str r3, [r7, #12] pLayerCfg.WindowY1 = 320; 80008e8: f44f 73a0 mov.w r3, #320 @ 0x140 80008ec: 613b str r3, [r7, #16] pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; 80008ee: 2302 movs r3, #2 80008f0: 617b str r3, [r7, #20] pLayerCfg.Alpha = 255; 80008f2: 23ff movs r3, #255 @ 0xff 80008f4: 61bb str r3, [r7, #24] pLayerCfg.Alpha0 = 0; 80008f6: 2300 movs r3, #0 80008f8: 61fb str r3, [r7, #28] pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; 80008fa: f44f 63c0 mov.w r3, #1536 @ 0x600 80008fe: 623b str r3, [r7, #32] pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; 8000900: 2307 movs r3, #7 8000902: 627b str r3, [r7, #36] @ 0x24 pLayerCfg.FBStartAdress = 0xD0000000; 8000904: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000 8000908: 62bb str r3, [r7, #40] @ 0x28 pLayerCfg.ImageWidth = 240; 800090a: 23f0 movs r3, #240 @ 0xf0 800090c: 62fb str r3, [r7, #44] @ 0x2c pLayerCfg.ImageHeight = 320; 800090e: f44f 73a0 mov.w r3, #320 @ 0x140 8000912: 633b str r3, [r7, #48] @ 0x30 pLayerCfg.Backcolor.Blue = 0; 8000914: 2300 movs r3, #0 8000916: f887 3034 strb.w r3, [r7, #52] @ 0x34 pLayerCfg.Backcolor.Green = 0; 800091a: 2300 movs r3, #0 800091c: f887 3035 strb.w r3, [r7, #53] @ 0x35 pLayerCfg.Backcolor.Red = 0; 8000920: 2300 movs r3, #0 8000922: f887 3036 strb.w r3, [r7, #54] @ 0x36 if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) 8000926: 1d3b adds r3, r7, #4 8000928: 2200 movs r2, #0 800092a: 4619 mov r1, r3 800092c: 4805 ldr r0, [pc, #20] @ (8000944 ) 800092e: f003 fc73 bl 8004218 8000932: 4603 mov r3, r0 8000934: 2b00 cmp r3, #0 8000936: d001 beq.n 800093c { Error_Handler(); 8000938: f000 fa3e bl 8000db8 } /* USER CODE BEGIN LTDC_Init 2 */ /* USER CODE END LTDC_Init 2 */ } 800093c: bf00 nop 800093e: 3738 adds r7, #56 @ 0x38 8000940: 46bd mov sp, r7 8000942: bd80 pop {r7, pc} 8000944: 200000d4 .word 0x200000d4 8000948: 40016800 .word 0x40016800 0800094c : * @brief SPI5 Initialization Function * @param None * @retval None */ static void MX_SPI5_Init(void) { 800094c: b580 push {r7, lr} 800094e: af00 add r7, sp, #0 /* USER CODE BEGIN SPI5_Init 1 */ /* USER CODE END SPI5_Init 1 */ /* SPI5 parameter configuration*/ hspi5.Instance = SPI5; 8000950: 4b17 ldr r3, [pc, #92] @ (80009b0 ) 8000952: 4a18 ldr r2, [pc, #96] @ (80009b4 ) 8000954: 601a str r2, [r3, #0] hspi5.Init.Mode = SPI_MODE_MASTER; 8000956: 4b16 ldr r3, [pc, #88] @ (80009b0 ) 8000958: f44f 7282 mov.w r2, #260 @ 0x104 800095c: 605a str r2, [r3, #4] hspi5.Init.Direction = SPI_DIRECTION_2LINES; 800095e: 4b14 ldr r3, [pc, #80] @ (80009b0 ) 8000960: 2200 movs r2, #0 8000962: 609a str r2, [r3, #8] hspi5.Init.DataSize = SPI_DATASIZE_8BIT; 8000964: 4b12 ldr r3, [pc, #72] @ (80009b0 ) 8000966: 2200 movs r2, #0 8000968: 60da str r2, [r3, #12] hspi5.Init.CLKPolarity = SPI_POLARITY_LOW; 800096a: 4b11 ldr r3, [pc, #68] @ (80009b0 ) 800096c: 2200 movs r2, #0 800096e: 611a str r2, [r3, #16] hspi5.Init.CLKPhase = SPI_PHASE_1EDGE; 8000970: 4b0f ldr r3, [pc, #60] @ (80009b0 ) 8000972: 2200 movs r2, #0 8000974: 615a str r2, [r3, #20] hspi5.Init.NSS = SPI_NSS_SOFT; 8000976: 4b0e ldr r3, [pc, #56] @ (80009b0 ) 8000978: f44f 7200 mov.w r2, #512 @ 0x200 800097c: 619a str r2, [r3, #24] hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; 800097e: 4b0c ldr r3, [pc, #48] @ (80009b0 ) 8000980: 2218 movs r2, #24 8000982: 61da str r2, [r3, #28] hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB; 8000984: 4b0a ldr r3, [pc, #40] @ (80009b0 ) 8000986: 2200 movs r2, #0 8000988: 621a str r2, [r3, #32] hspi5.Init.TIMode = SPI_TIMODE_DISABLE; 800098a: 4b09 ldr r3, [pc, #36] @ (80009b0 ) 800098c: 2200 movs r2, #0 800098e: 625a str r2, [r3, #36] @ 0x24 hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000990: 4b07 ldr r3, [pc, #28] @ (80009b0 ) 8000992: 2200 movs r2, #0 8000994: 629a str r2, [r3, #40] @ 0x28 hspi5.Init.CRCPolynomial = 10; 8000996: 4b06 ldr r3, [pc, #24] @ (80009b0 ) 8000998: 220a movs r2, #10 800099a: 62da str r2, [r3, #44] @ 0x2c if (HAL_SPI_Init(&hspi5) != HAL_OK) 800099c: 4804 ldr r0, [pc, #16] @ (80009b0 ) 800099e: f004 fcab bl 80052f8 80009a2: 4603 mov r3, r0 80009a4: 2b00 cmp r3, #0 80009a6: d001 beq.n 80009ac { Error_Handler(); 80009a8: f000 fa06 bl 8000db8 } /* USER CODE BEGIN SPI5_Init 2 */ /* USER CODE END SPI5_Init 2 */ } 80009ac: bf00 nop 80009ae: bd80 pop {r7, pc} 80009b0: 2000017c .word 0x2000017c 80009b4: 40015000 .word 0x40015000 080009b8 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 80009b8: b580 push {r7, lr} 80009ba: b086 sub sp, #24 80009bc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80009be: f107 0308 add.w r3, r7, #8 80009c2: 2200 movs r2, #0 80009c4: 601a str r2, [r3, #0] 80009c6: 605a str r2, [r3, #4] 80009c8: 609a str r2, [r3, #8] 80009ca: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 80009cc: 463b mov r3, r7 80009ce: 2200 movs r2, #0 80009d0: 601a str r2, [r3, #0] 80009d2: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 80009d4: 4b1e ldr r3, [pc, #120] @ (8000a50 ) 80009d6: 4a1f ldr r2, [pc, #124] @ (8000a54 ) 80009d8: 601a str r2, [r3, #0] htim1.Init.Prescaler = 0; 80009da: 4b1d ldr r3, [pc, #116] @ (8000a50 ) 80009dc: 2200 movs r2, #0 80009de: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 80009e0: 4b1b ldr r3, [pc, #108] @ (8000a50 ) 80009e2: 2200 movs r2, #0 80009e4: 609a str r2, [r3, #8] htim1.Init.Period = 65535; 80009e6: 4b1a ldr r3, [pc, #104] @ (8000a50 ) 80009e8: f64f 72ff movw r2, #65535 @ 0xffff 80009ec: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80009ee: 4b18 ldr r3, [pc, #96] @ (8000a50 ) 80009f0: 2200 movs r2, #0 80009f2: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 80009f4: 4b16 ldr r3, [pc, #88] @ (8000a50 ) 80009f6: 2200 movs r2, #0 80009f8: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80009fa: 4b15 ldr r3, [pc, #84] @ (8000a50 ) 80009fc: 2200 movs r2, #0 80009fe: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8000a00: 4813 ldr r0, [pc, #76] @ (8000a50 ) 8000a02: f004 fd02 bl 800540a 8000a06: 4603 mov r3, r0 8000a08: 2b00 cmp r3, #0 8000a0a: d001 beq.n 8000a10 { Error_Handler(); 8000a0c: f000 f9d4 bl 8000db8 } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000a10: f44f 5380 mov.w r3, #4096 @ 0x1000 8000a14: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8000a16: f107 0308 add.w r3, r7, #8 8000a1a: 4619 mov r1, r3 8000a1c: 480c ldr r0, [pc, #48] @ (8000a50 ) 8000a1e: f004 fea3 bl 8005768 8000a22: 4603 mov r3, r0 8000a24: 2b00 cmp r3, #0 8000a26: d001 beq.n 8000a2c { Error_Handler(); 8000a28: f000 f9c6 bl 8000db8 } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8000a2c: 2300 movs r3, #0 8000a2e: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 8000a30: 2300 movs r3, #0 8000a32: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 8000a34: 463b mov r3, r7 8000a36: 4619 mov r1, r3 8000a38: 4805 ldr r0, [pc, #20] @ (8000a50 ) 8000a3a: f005 f8c5 bl 8005bc8 8000a3e: 4603 mov r3, r0 8000a40: 2b00 cmp r3, #0 8000a42: d001 beq.n 8000a48 { Error_Handler(); 8000a44: f000 f9b8 bl 8000db8 } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ } 8000a48: bf00 nop 8000a4a: 3718 adds r7, #24 8000a4c: 46bd mov sp, r7 8000a4e: bd80 pop {r7, pc} 8000a50: 200001d4 .word 0x200001d4 8000a54: 40010000 .word 0x40010000 08000a58 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8000a58: b580 push {r7, lr} 8000a5a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 8000a5c: 4b11 ldr r3, [pc, #68] @ (8000aa4 ) 8000a5e: 4a12 ldr r2, [pc, #72] @ (8000aa8 ) 8000a60: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8000a62: 4b10 ldr r3, [pc, #64] @ (8000aa4 ) 8000a64: f44f 32e1 mov.w r2, #115200 @ 0x1c200 8000a68: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 8000a6a: 4b0e ldr r3, [pc, #56] @ (8000aa4 ) 8000a6c: 2200 movs r2, #0 8000a6e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 8000a70: 4b0c ldr r3, [pc, #48] @ (8000aa4 ) 8000a72: 2200 movs r2, #0 8000a74: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 8000a76: 4b0b ldr r3, [pc, #44] @ (8000aa4 ) 8000a78: 2200 movs r2, #0 8000a7a: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 8000a7c: 4b09 ldr r3, [pc, #36] @ (8000aa4 ) 8000a7e: 220c movs r2, #12 8000a80: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 8000a82: 4b08 ldr r3, [pc, #32] @ (8000aa4 ) 8000a84: 2200 movs r2, #0 8000a86: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000a88: 4b06 ldr r3, [pc, #24] @ (8000aa4 ) 8000a8a: 2200 movs r2, #0 8000a8c: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8000a8e: 4805 ldr r0, [pc, #20] @ (8000aa4 ) 8000a90: f005 f92a bl 8005ce8 8000a94: 4603 mov r3, r0 8000a96: 2b00 cmp r3, #0 8000a98: d001 beq.n 8000a9e { Error_Handler(); 8000a9a: f000 f98d bl 8000db8 } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000a9e: bf00 nop 8000aa0: bd80 pop {r7, pc} 8000aa2: bf00 nop 8000aa4: 2000021c .word 0x2000021c 8000aa8: 40011000 .word 0x40011000 08000aac : /* FMC initialization function */ static void MX_FMC_Init(void) { 8000aac: b580 push {r7, lr} 8000aae: b088 sub sp, #32 8000ab0: af00 add r7, sp, #0 /* USER CODE BEGIN FMC_Init 0 */ /* USER CODE END FMC_Init 0 */ FMC_SDRAM_TimingTypeDef SdramTiming = {0}; 8000ab2: 1d3b adds r3, r7, #4 8000ab4: 2200 movs r2, #0 8000ab6: 601a str r2, [r3, #0] 8000ab8: 605a str r2, [r3, #4] 8000aba: 609a str r2, [r3, #8] 8000abc: 60da str r2, [r3, #12] 8000abe: 611a str r2, [r3, #16] 8000ac0: 615a str r2, [r3, #20] 8000ac2: 619a str r2, [r3, #24] /* USER CODE END FMC_Init 1 */ /** Perform the SDRAM1 memory initialization sequence */ hsdram1.Instance = FMC_SDRAM_DEVICE; 8000ac4: 4b1f ldr r3, [pc, #124] @ (8000b44 ) 8000ac6: 4a20 ldr r2, [pc, #128] @ (8000b48 ) 8000ac8: 601a str r2, [r3, #0] /* hsdram1.Init */ hsdram1.Init.SDBank = FMC_SDRAM_BANK2; 8000aca: 4b1e ldr r3, [pc, #120] @ (8000b44 ) 8000acc: 2201 movs r2, #1 8000ace: 605a str r2, [r3, #4] hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; 8000ad0: 4b1c ldr r3, [pc, #112] @ (8000b44 ) 8000ad2: 2200 movs r2, #0 8000ad4: 609a str r2, [r3, #8] hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; 8000ad6: 4b1b ldr r3, [pc, #108] @ (8000b44 ) 8000ad8: 2204 movs r2, #4 8000ada: 60da str r2, [r3, #12] hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; 8000adc: 4b19 ldr r3, [pc, #100] @ (8000b44 ) 8000ade: 2210 movs r2, #16 8000ae0: 611a str r2, [r3, #16] hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 8000ae2: 4b18 ldr r3, [pc, #96] @ (8000b44 ) 8000ae4: 2240 movs r2, #64 @ 0x40 8000ae6: 615a str r2, [r3, #20] hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; 8000ae8: 4b16 ldr r3, [pc, #88] @ (8000b44 ) 8000aea: f44f 72c0 mov.w r2, #384 @ 0x180 8000aee: 619a str r2, [r3, #24] hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 8000af0: 4b14 ldr r3, [pc, #80] @ (8000b44 ) 8000af2: 2200 movs r2, #0 8000af4: 61da str r2, [r3, #28] hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; 8000af6: 4b13 ldr r3, [pc, #76] @ (8000b44 ) 8000af8: f44f 6200 mov.w r2, #2048 @ 0x800 8000afc: 621a str r2, [r3, #32] hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; 8000afe: 4b11 ldr r3, [pc, #68] @ (8000b44 ) 8000b00: 2200 movs r2, #0 8000b02: 625a str r2, [r3, #36] @ 0x24 hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; 8000b04: 4b0f ldr r3, [pc, #60] @ (8000b44 ) 8000b06: f44f 5200 mov.w r2, #8192 @ 0x2000 8000b0a: 629a str r2, [r3, #40] @ 0x28 /* SdramTiming */ SdramTiming.LoadToActiveDelay = 2; 8000b0c: 2302 movs r3, #2 8000b0e: 607b str r3, [r7, #4] SdramTiming.ExitSelfRefreshDelay = 7; 8000b10: 2307 movs r3, #7 8000b12: 60bb str r3, [r7, #8] SdramTiming.SelfRefreshTime = 4; 8000b14: 2304 movs r3, #4 8000b16: 60fb str r3, [r7, #12] SdramTiming.RowCycleDelay = 7; 8000b18: 2307 movs r3, #7 8000b1a: 613b str r3, [r7, #16] SdramTiming.WriteRecoveryTime = 3; 8000b1c: 2303 movs r3, #3 8000b1e: 617b str r3, [r7, #20] SdramTiming.RPDelay = 2; 8000b20: 2302 movs r3, #2 8000b22: 61bb str r3, [r7, #24] SdramTiming.RCDDelay = 2; 8000b24: 2302 movs r3, #2 8000b26: 61fb str r3, [r7, #28] if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) 8000b28: 1d3b adds r3, r7, #4 8000b2a: 4619 mov r1, r3 8000b2c: 4805 ldr r0, [pc, #20] @ (8000b44 ) 8000b2e: f004 fbaf bl 8005290 8000b32: 4603 mov r3, r0 8000b34: 2b00 cmp r3, #0 8000b36: d001 beq.n 8000b3c { Error_Handler( ); 8000b38: f000 f93e bl 8000db8 } /* USER CODE BEGIN FMC_Init 2 */ /* USER CODE END FMC_Init 2 */ } 8000b3c: bf00 nop 8000b3e: 3720 adds r7, #32 8000b40: 46bd mov sp, r7 8000b42: bd80 pop {r7, pc} 8000b44: 20000264 .word 0x20000264 8000b48: a0000140 .word 0xa0000140 08000b4c : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000b4c: b580 push {r7, lr} 8000b4e: b08e sub sp, #56 @ 0x38 8000b50: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000b52: f107 0324 add.w r3, r7, #36 @ 0x24 8000b56: 2200 movs r2, #0 8000b58: 601a str r2, [r3, #0] 8000b5a: 605a str r2, [r3, #4] 8000b5c: 609a str r2, [r3, #8] 8000b5e: 60da str r2, [r3, #12] 8000b60: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); 8000b62: 2300 movs r3, #0 8000b64: 623b str r3, [r7, #32] 8000b66: 4b84 ldr r3, [pc, #528] @ (8000d78 ) 8000b68: 6b1b ldr r3, [r3, #48] @ 0x30 8000b6a: 4a83 ldr r2, [pc, #524] @ (8000d78 ) 8000b6c: f043 0310 orr.w r3, r3, #16 8000b70: 6313 str r3, [r2, #48] @ 0x30 8000b72: 4b81 ldr r3, [pc, #516] @ (8000d78 ) 8000b74: 6b1b ldr r3, [r3, #48] @ 0x30 8000b76: f003 0310 and.w r3, r3, #16 8000b7a: 623b str r3, [r7, #32] 8000b7c: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000b7e: 2300 movs r3, #0 8000b80: 61fb str r3, [r7, #28] 8000b82: 4b7d ldr r3, [pc, #500] @ (8000d78 ) 8000b84: 6b1b ldr r3, [r3, #48] @ 0x30 8000b86: 4a7c ldr r2, [pc, #496] @ (8000d78 ) 8000b88: f043 0304 orr.w r3, r3, #4 8000b8c: 6313 str r3, [r2, #48] @ 0x30 8000b8e: 4b7a ldr r3, [pc, #488] @ (8000d78 ) 8000b90: 6b1b ldr r3, [r3, #48] @ 0x30 8000b92: f003 0304 and.w r3, r3, #4 8000b96: 61fb str r3, [r7, #28] 8000b98: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000b9a: 2300 movs r3, #0 8000b9c: 61bb str r3, [r7, #24] 8000b9e: 4b76 ldr r3, [pc, #472] @ (8000d78 ) 8000ba0: 6b1b ldr r3, [r3, #48] @ 0x30 8000ba2: 4a75 ldr r2, [pc, #468] @ (8000d78 ) 8000ba4: f043 0320 orr.w r3, r3, #32 8000ba8: 6313 str r3, [r2, #48] @ 0x30 8000baa: 4b73 ldr r3, [pc, #460] @ (8000d78 ) 8000bac: 6b1b ldr r3, [r3, #48] @ 0x30 8000bae: f003 0320 and.w r3, r3, #32 8000bb2: 61bb str r3, [r7, #24] 8000bb4: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000bb6: 2300 movs r3, #0 8000bb8: 617b str r3, [r7, #20] 8000bba: 4b6f ldr r3, [pc, #444] @ (8000d78 ) 8000bbc: 6b1b ldr r3, [r3, #48] @ 0x30 8000bbe: 4a6e ldr r2, [pc, #440] @ (8000d78 ) 8000bc0: f043 0380 orr.w r3, r3, #128 @ 0x80 8000bc4: 6313 str r3, [r2, #48] @ 0x30 8000bc6: 4b6c ldr r3, [pc, #432] @ (8000d78 ) 8000bc8: 6b1b ldr r3, [r3, #48] @ 0x30 8000bca: f003 0380 and.w r3, r3, #128 @ 0x80 8000bce: 617b str r3, [r7, #20] 8000bd0: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000bd2: 2300 movs r3, #0 8000bd4: 613b str r3, [r7, #16] 8000bd6: 4b68 ldr r3, [pc, #416] @ (8000d78 ) 8000bd8: 6b1b ldr r3, [r3, #48] @ 0x30 8000bda: 4a67 ldr r2, [pc, #412] @ (8000d78 ) 8000bdc: f043 0301 orr.w r3, r3, #1 8000be0: 6313 str r3, [r2, #48] @ 0x30 8000be2: 4b65 ldr r3, [pc, #404] @ (8000d78 ) 8000be4: 6b1b ldr r3, [r3, #48] @ 0x30 8000be6: f003 0301 and.w r3, r3, #1 8000bea: 613b str r3, [r7, #16] 8000bec: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000bee: 2300 movs r3, #0 8000bf0: 60fb str r3, [r7, #12] 8000bf2: 4b61 ldr r3, [pc, #388] @ (8000d78 ) 8000bf4: 6b1b ldr r3, [r3, #48] @ 0x30 8000bf6: 4a60 ldr r2, [pc, #384] @ (8000d78 ) 8000bf8: f043 0302 orr.w r3, r3, #2 8000bfc: 6313 str r3, [r2, #48] @ 0x30 8000bfe: 4b5e ldr r3, [pc, #376] @ (8000d78 ) 8000c00: 6b1b ldr r3, [r3, #48] @ 0x30 8000c02: f003 0302 and.w r3, r3, #2 8000c06: 60fb str r3, [r7, #12] 8000c08: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000c0a: 2300 movs r3, #0 8000c0c: 60bb str r3, [r7, #8] 8000c0e: 4b5a ldr r3, [pc, #360] @ (8000d78 ) 8000c10: 6b1b ldr r3, [r3, #48] @ 0x30 8000c12: 4a59 ldr r2, [pc, #356] @ (8000d78 ) 8000c14: f043 0340 orr.w r3, r3, #64 @ 0x40 8000c18: 6313 str r3, [r2, #48] @ 0x30 8000c1a: 4b57 ldr r3, [pc, #348] @ (8000d78 ) 8000c1c: 6b1b ldr r3, [r3, #48] @ 0x30 8000c1e: f003 0340 and.w r3, r3, #64 @ 0x40 8000c22: 60bb str r3, [r7, #8] 8000c24: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000c26: 2300 movs r3, #0 8000c28: 607b str r3, [r7, #4] 8000c2a: 4b53 ldr r3, [pc, #332] @ (8000d78 ) 8000c2c: 6b1b ldr r3, [r3, #48] @ 0x30 8000c2e: 4a52 ldr r2, [pc, #328] @ (8000d78 ) 8000c30: f043 0308 orr.w r3, r3, #8 8000c34: 6313 str r3, [r2, #48] @ 0x30 8000c36: 4b50 ldr r3, [pc, #320] @ (8000d78 ) 8000c38: 6b1b ldr r3, [r3, #48] @ 0x30 8000c3a: f003 0308 and.w r3, r3, #8 8000c3e: 607b str r3, [r7, #4] 8000c40: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOE, RedLight_Pin|YellowLight_Pin|GreenLight_Pin|WalkLight_Pin, GPIO_PIN_RESET); 8000c42: 2200 movs r2, #0 8000c44: 213c movs r1, #60 @ 0x3c 8000c46: 484d ldr r0, [pc, #308] @ (8000d7c ) 8000c48: f001 f9ee bl 8002028 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET); 8000c4c: 2200 movs r2, #0 8000c4e: 2116 movs r1, #22 8000c50: 484b ldr r0, [pc, #300] @ (8000d80 ) 8000c52: f001 f9e9 bl 8002028 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET); 8000c56: 2200 movs r2, #0 8000c58: 2180 movs r1, #128 @ 0x80 8000c5a: 484a ldr r0, [pc, #296] @ (8000d84 ) 8000c5c: f001 f9e4 bl 8002028 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET); 8000c60: 2200 movs r2, #0 8000c62: f44f 5140 mov.w r1, #12288 @ 0x3000 8000c66: 4848 ldr r0, [pc, #288] @ (8000d88 ) 8000c68: f001 f9de bl 8002028 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET); 8000c6c: 2200 movs r2, #0 8000c6e: f44f 41c0 mov.w r1, #24576 @ 0x6000 8000c72: 4846 ldr r0, [pc, #280] @ (8000d8c ) 8000c74: f001 f9d8 bl 8002028 /*Configure GPIO pins : RedLight_Pin YellowLight_Pin GreenLight_Pin WalkLight_Pin */ GPIO_InitStruct.Pin = RedLight_Pin|YellowLight_Pin|GreenLight_Pin|WalkLight_Pin; 8000c78: 233c movs r3, #60 @ 0x3c 8000c7a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c7c: 2301 movs r3, #1 8000c7e: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c80: 2300 movs r3, #0 8000c82: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c84: 2300 movs r3, #0 8000c86: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 8000c88: f107 0324 add.w r3, r7, #36 @ 0x24 8000c8c: 4619 mov r1, r3 8000c8e: 483b ldr r0, [pc, #236] @ (8000d7c ) 8000c90: f001 f81e bl 8001cd0 /*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */ GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin; 8000c94: 2316 movs r3, #22 8000c96: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c98: 2301 movs r3, #1 8000c9a: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c9c: 2300 movs r3, #0 8000c9e: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000ca0: 2300 movs r3, #0 8000ca2: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000ca4: f107 0324 add.w r3, r7, #36 @ 0x24 8000ca8: 4619 mov r1, r3 8000caa: 4835 ldr r0, [pc, #212] @ (8000d80 ) 8000cac: f001 f810 bl 8001cd0 /*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */ GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin; 8000cb0: f248 0307 movw r3, #32775 @ 0x8007 8000cb4: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; 8000cb6: f44f 1390 mov.w r3, #1179648 @ 0x120000 8000cba: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cbc: 2300 movs r3, #0 8000cbe: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000cc0: f107 0324 add.w r3, r7, #36 @ 0x24 8000cc4: 4619 mov r1, r3 8000cc6: 482f ldr r0, [pc, #188] @ (8000d84 ) 8000cc8: f001 f802 bl 8001cd0 /*Configure GPIO pin : ACP_RST_Pin */ GPIO_InitStruct.Pin = ACP_RST_Pin; 8000ccc: 2380 movs r3, #128 @ 0x80 8000cce: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000cd0: 2301 movs r3, #1 8000cd2: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cd4: 2300 movs r3, #0 8000cd6: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000cd8: 2300 movs r3, #0 8000cda: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct); 8000cdc: f107 0324 add.w r3, r7, #36 @ 0x24 8000ce0: 4619 mov r1, r3 8000ce2: 4828 ldr r0, [pc, #160] @ (8000d84 ) 8000ce4: f000 fff4 bl 8001cd0 /*Configure GPIO pin : OTG_FS_OC_Pin */ GPIO_InitStruct.Pin = OTG_FS_OC_Pin; 8000ce8: 2320 movs r3, #32 8000cea: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; 8000cec: f44f 1390 mov.w r3, #1179648 @ 0x120000 8000cf0: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cf2: 2300 movs r3, #0 8000cf4: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct); 8000cf6: f107 0324 add.w r3, r7, #36 @ 0x24 8000cfa: 4619 mov r1, r3 8000cfc: 4820 ldr r0, [pc, #128] @ (8000d80 ) 8000cfe: f000 ffe7 bl 8001cd0 /*Configure GPIO pin : BOOT1_Pin */ GPIO_InitStruct.Pin = BOOT1_Pin; 8000d02: 2304 movs r3, #4 8000d04: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000d06: 2300 movs r3, #0 8000d08: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d0a: 2300 movs r3, #0 8000d0c: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct); 8000d0e: f107 0324 add.w r3, r7, #36 @ 0x24 8000d12: 4619 mov r1, r3 8000d14: 481e ldr r0, [pc, #120] @ (8000d90 ) 8000d16: f000 ffdb bl 8001cd0 /*Configure GPIO pin : TE_Pin */ GPIO_InitStruct.Pin = TE_Pin; 8000d1a: f44f 6300 mov.w r3, #2048 @ 0x800 8000d1e: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000d20: 2300 movs r3, #0 8000d22: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d24: 2300 movs r3, #0 8000d26: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct); 8000d28: f107 0324 add.w r3, r7, #36 @ 0x24 8000d2c: 4619 mov r1, r3 8000d2e: 4816 ldr r0, [pc, #88] @ (8000d88 ) 8000d30: f000 ffce bl 8001cd0 /*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */ GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin; 8000d34: f44f 5340 mov.w r3, #12288 @ 0x3000 8000d38: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d3a: 2301 movs r3, #1 8000d3c: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d3e: 2300 movs r3, #0 8000d40: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d42: 2300 movs r3, #0 8000d44: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000d46: f107 0324 add.w r3, r7, #36 @ 0x24 8000d4a: 4619 mov r1, r3 8000d4c: 480e ldr r0, [pc, #56] @ (8000d88 ) 8000d4e: f000 ffbf bl 8001cd0 /*Configure GPIO pins : LD3_Pin LD4_Pin */ GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin; 8000d52: f44f 43c0 mov.w r3, #24576 @ 0x6000 8000d56: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000d58: 2301 movs r3, #1 8000d5a: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000d5c: 2300 movs r3, #0 8000d5e: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000d60: 2300 movs r3, #0 8000d62: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000d64: f107 0324 add.w r3, r7, #36 @ 0x24 8000d68: 4619 mov r1, r3 8000d6a: 4808 ldr r0, [pc, #32] @ (8000d8c ) 8000d6c: f000 ffb0 bl 8001cd0 /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000d70: bf00 nop 8000d72: 3738 adds r7, #56 @ 0x38 8000d74: 46bd mov sp, r7 8000d76: bd80 pop {r7, pc} 8000d78: 40023800 .word 0x40023800 8000d7c: 40021000 .word 0x40021000 8000d80: 40020800 .word 0x40020800 8000d84: 40020000 .word 0x40020000 8000d88: 40020c00 .word 0x40020c00 8000d8c: 40021800 .word 0x40021800 8000d90: 40020400 .word 0x40020400 08000d94 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8000d94: b580 push {r7, lr} 8000d96: b082 sub sp, #8 8000d98: af00 add r7, sp, #0 8000d9a: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) 8000d9c: 687b ldr r3, [r7, #4] 8000d9e: 681b ldr r3, [r3, #0] 8000da0: 4a04 ldr r2, [pc, #16] @ (8000db4 ) 8000da2: 4293 cmp r3, r2 8000da4: d101 bne.n 8000daa { HAL_IncTick(); 8000da6: f000 fc89 bl 80016bc } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8000daa: bf00 nop 8000dac: 3708 adds r7, #8 8000dae: 46bd mov sp, r7 8000db0: bd80 pop {r7, pc} 8000db2: bf00 nop 8000db4: 40001000 .word 0x40001000 08000db8 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000db8: b480 push {r7} 8000dba: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000dbc: b672 cpsid i } 8000dbe: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000dc0: bf00 nop 8000dc2: e7fd b.n 8000dc0 08000dc4 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000dc4: b580 push {r7, lr} 8000dc6: b082 sub sp, #8 8000dc8: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000dca: 2300 movs r3, #0 8000dcc: 607b str r3, [r7, #4] 8000dce: 4b12 ldr r3, [pc, #72] @ (8000e18 ) 8000dd0: 6c5b ldr r3, [r3, #68] @ 0x44 8000dd2: 4a11 ldr r2, [pc, #68] @ (8000e18 ) 8000dd4: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000dd8: 6453 str r3, [r2, #68] @ 0x44 8000dda: 4b0f ldr r3, [pc, #60] @ (8000e18 ) 8000ddc: 6c5b ldr r3, [r3, #68] @ 0x44 8000dde: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000de2: 607b str r3, [r7, #4] 8000de4: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000de6: 2300 movs r3, #0 8000de8: 603b str r3, [r7, #0] 8000dea: 4b0b ldr r3, [pc, #44] @ (8000e18 ) 8000dec: 6c1b ldr r3, [r3, #64] @ 0x40 8000dee: 4a0a ldr r2, [pc, #40] @ (8000e18 ) 8000df0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000df4: 6413 str r3, [r2, #64] @ 0x40 8000df6: 4b08 ldr r3, [pc, #32] @ (8000e18 ) 8000df8: 6c1b ldr r3, [r3, #64] @ 0x40 8000dfa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000dfe: 603b str r3, [r7, #0] 8000e00: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8000e02: 2200 movs r2, #0 8000e04: 210f movs r1, #15 8000e06: f06f 0001 mvn.w r0, #1 8000e0a: f000 fd2f bl 800186c /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000e0e: bf00 nop 8000e10: 3708 adds r7, #8 8000e12: 46bd mov sp, r7 8000e14: bd80 pop {r7, pc} 8000e16: bf00 nop 8000e18: 40023800 .word 0x40023800 08000e1c : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8000e1c: b480 push {r7} 8000e1e: b085 sub sp, #20 8000e20: af00 add r7, sp, #0 8000e22: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8000e24: 687b ldr r3, [r7, #4] 8000e26: 681b ldr r3, [r3, #0] 8000e28: 4a0b ldr r2, [pc, #44] @ (8000e58 ) 8000e2a: 4293 cmp r3, r2 8000e2c: d10d bne.n 8000e4a { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8000e2e: 2300 movs r3, #0 8000e30: 60fb str r3, [r7, #12] 8000e32: 4b0a ldr r3, [pc, #40] @ (8000e5c ) 8000e34: 6b1b ldr r3, [r3, #48] @ 0x30 8000e36: 4a09 ldr r2, [pc, #36] @ (8000e5c ) 8000e38: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8000e3c: 6313 str r3, [r2, #48] @ 0x30 8000e3e: 4b07 ldr r3, [pc, #28] @ (8000e5c ) 8000e40: 6b1b ldr r3, [r3, #48] @ 0x30 8000e42: f403 5380 and.w r3, r3, #4096 @ 0x1000 8000e46: 60fb str r3, [r7, #12] 8000e48: 68fb ldr r3, [r7, #12] /* USER CODE END CRC_MspInit 1 */ } } 8000e4a: bf00 nop 8000e4c: 3714 adds r7, #20 8000e4e: 46bd mov sp, r7 8000e50: f85d 7b04 ldr.w r7, [sp], #4 8000e54: 4770 bx lr 8000e56: bf00 nop 8000e58: 40023000 .word 0x40023000 8000e5c: 40023800 .word 0x40023800 08000e60 : * This function configures the hardware resources used in this example * @param hdma2d: DMA2D handle pointer * @retval None */ void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) { 8000e60: b580 push {r7, lr} 8000e62: b084 sub sp, #16 8000e64: af00 add r7, sp, #0 8000e66: 6078 str r0, [r7, #4] if(hdma2d->Instance==DMA2D) 8000e68: 687b ldr r3, [r7, #4] 8000e6a: 681b ldr r3, [r3, #0] 8000e6c: 4a0e ldr r2, [pc, #56] @ (8000ea8 ) 8000e6e: 4293 cmp r3, r2 8000e70: d115 bne.n 8000e9e { /* USER CODE BEGIN DMA2D_MspInit 0 */ /* USER CODE END DMA2D_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DMA2D_CLK_ENABLE(); 8000e72: 2300 movs r3, #0 8000e74: 60fb str r3, [r7, #12] 8000e76: 4b0d ldr r3, [pc, #52] @ (8000eac ) 8000e78: 6b1b ldr r3, [r3, #48] @ 0x30 8000e7a: 4a0c ldr r2, [pc, #48] @ (8000eac ) 8000e7c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8000e80: 6313 str r3, [r2, #48] @ 0x30 8000e82: 4b0a ldr r3, [pc, #40] @ (8000eac ) 8000e84: 6b1b ldr r3, [r3, #48] @ 0x30 8000e86: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8000e8a: 60fb str r3, [r7, #12] 8000e8c: 68fb ldr r3, [r7, #12] /* DMA2D interrupt Init */ HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0); 8000e8e: 2200 movs r2, #0 8000e90: 2105 movs r1, #5 8000e92: 205a movs r0, #90 @ 0x5a 8000e94: f000 fcea bl 800186c HAL_NVIC_EnableIRQ(DMA2D_IRQn); 8000e98: 205a movs r0, #90 @ 0x5a 8000e9a: f000 fd03 bl 80018a4 /* USER CODE END DMA2D_MspInit 1 */ } } 8000e9e: bf00 nop 8000ea0: 3710 adds r7, #16 8000ea2: 46bd mov sp, r7 8000ea4: bd80 pop {r7, pc} 8000ea6: bf00 nop 8000ea8: 4002b000 .word 0x4002b000 8000eac: 40023800 .word 0x40023800 08000eb0 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8000eb0: b580 push {r7, lr} 8000eb2: b08a sub sp, #40 @ 0x28 8000eb4: af00 add r7, sp, #0 8000eb6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000eb8: f107 0314 add.w r3, r7, #20 8000ebc: 2200 movs r2, #0 8000ebe: 601a str r2, [r3, #0] 8000ec0: 605a str r2, [r3, #4] 8000ec2: 609a str r2, [r3, #8] 8000ec4: 60da str r2, [r3, #12] 8000ec6: 611a str r2, [r3, #16] if(hi2c->Instance==I2C3) 8000ec8: 687b ldr r3, [r7, #4] 8000eca: 681b ldr r3, [r3, #0] 8000ecc: 4a29 ldr r2, [pc, #164] @ (8000f74 ) 8000ece: 4293 cmp r3, r2 8000ed0: d14b bne.n 8000f6a { /* USER CODE BEGIN I2C3_MspInit 0 */ /* USER CODE END I2C3_MspInit 0 */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ed2: 2300 movs r3, #0 8000ed4: 613b str r3, [r7, #16] 8000ed6: 4b28 ldr r3, [pc, #160] @ (8000f78 ) 8000ed8: 6b1b ldr r3, [r3, #48] @ 0x30 8000eda: 4a27 ldr r2, [pc, #156] @ (8000f78 ) 8000edc: f043 0304 orr.w r3, r3, #4 8000ee0: 6313 str r3, [r2, #48] @ 0x30 8000ee2: 4b25 ldr r3, [pc, #148] @ (8000f78 ) 8000ee4: 6b1b ldr r3, [r3, #48] @ 0x30 8000ee6: f003 0304 and.w r3, r3, #4 8000eea: 613b str r3, [r7, #16] 8000eec: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000eee: 2300 movs r3, #0 8000ef0: 60fb str r3, [r7, #12] 8000ef2: 4b21 ldr r3, [pc, #132] @ (8000f78 ) 8000ef4: 6b1b ldr r3, [r3, #48] @ 0x30 8000ef6: 4a20 ldr r2, [pc, #128] @ (8000f78 ) 8000ef8: f043 0301 orr.w r3, r3, #1 8000efc: 6313 str r3, [r2, #48] @ 0x30 8000efe: 4b1e ldr r3, [pc, #120] @ (8000f78 ) 8000f00: 6b1b ldr r3, [r3, #48] @ 0x30 8000f02: f003 0301 and.w r3, r3, #1 8000f06: 60fb str r3, [r7, #12] 8000f08: 68fb ldr r3, [r7, #12] /**I2C3 GPIO Configuration PC9 ------> I2C3_SDA PA8 ------> I2C3_SCL */ GPIO_InitStruct.Pin = I2C3_SDA_Pin; 8000f0a: f44f 7300 mov.w r3, #512 @ 0x200 8000f0e: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000f10: 2312 movs r3, #18 8000f12: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000f14: 2301 movs r3, #1 8000f16: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f18: 2300 movs r3, #0 8000f1a: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; 8000f1c: 2304 movs r3, #4 8000f1e: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct); 8000f20: f107 0314 add.w r3, r7, #20 8000f24: 4619 mov r1, r3 8000f26: 4815 ldr r0, [pc, #84] @ (8000f7c ) 8000f28: f000 fed2 bl 8001cd0 GPIO_InitStruct.Pin = I2C3_SCL_Pin; 8000f2c: f44f 7380 mov.w r3, #256 @ 0x100 8000f30: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000f32: 2312 movs r3, #18 8000f34: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000f36: 2301 movs r3, #1 8000f38: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000f3a: 2300 movs r3, #0 8000f3c: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; 8000f3e: 2304 movs r3, #4 8000f40: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct); 8000f42: f107 0314 add.w r3, r7, #20 8000f46: 4619 mov r1, r3 8000f48: 480d ldr r0, [pc, #52] @ (8000f80 ) 8000f4a: f000 fec1 bl 8001cd0 /* Peripheral clock enable */ __HAL_RCC_I2C3_CLK_ENABLE(); 8000f4e: 2300 movs r3, #0 8000f50: 60bb str r3, [r7, #8] 8000f52: 4b09 ldr r3, [pc, #36] @ (8000f78 ) 8000f54: 6c1b ldr r3, [r3, #64] @ 0x40 8000f56: 4a08 ldr r2, [pc, #32] @ (8000f78 ) 8000f58: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8000f5c: 6413 str r3, [r2, #64] @ 0x40 8000f5e: 4b06 ldr r3, [pc, #24] @ (8000f78 ) 8000f60: 6c1b ldr r3, [r3, #64] @ 0x40 8000f62: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8000f66: 60bb str r3, [r7, #8] 8000f68: 68bb ldr r3, [r7, #8] /* USER CODE END I2C3_MspInit 1 */ } } 8000f6a: bf00 nop 8000f6c: 3728 adds r7, #40 @ 0x28 8000f6e: 46bd mov sp, r7 8000f70: bd80 pop {r7, pc} 8000f72: bf00 nop 8000f74: 40005c00 .word 0x40005c00 8000f78: 40023800 .word 0x40023800 8000f7c: 40020800 .word 0x40020800 8000f80: 40020000 .word 0x40020000 08000f84 : * This function configures the hardware resources used in this example * @param hltdc: LTDC handle pointer * @retval None */ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) { 8000f84: b580 push {r7, lr} 8000f86: b09a sub sp, #104 @ 0x68 8000f88: af00 add r7, sp, #0 8000f8a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f8c: f107 0354 add.w r3, r7, #84 @ 0x54 8000f90: 2200 movs r2, #0 8000f92: 601a str r2, [r3, #0] 8000f94: 605a str r2, [r3, #4] 8000f96: 609a str r2, [r3, #8] 8000f98: 60da str r2, [r3, #12] 8000f9a: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000f9c: f107 0324 add.w r3, r7, #36 @ 0x24 8000fa0: 2230 movs r2, #48 @ 0x30 8000fa2: 2100 movs r1, #0 8000fa4: 4618 mov r0, r3 8000fa6: f006 ff9b bl 8007ee0 if(hltdc->Instance==LTDC) 8000faa: 687b ldr r3, [r7, #4] 8000fac: 681b ldr r3, [r3, #0] 8000fae: 4a85 ldr r2, [pc, #532] @ (80011c4 ) 8000fb0: 4293 cmp r3, r2 8000fb2: f040 8102 bne.w 80011ba /* USER CODE END LTDC_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; 8000fb6: 2308 movs r3, #8 8000fb8: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.PLLSAI.PLLSAIN = 50; 8000fba: 2332 movs r3, #50 @ 0x32 8000fbc: 637b str r3, [r7, #52] @ 0x34 PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; 8000fbe: 2302 movs r3, #2 8000fc0: 63fb str r3, [r7, #60] @ 0x3c PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; 8000fc2: 2300 movs r3, #0 8000fc4: 64bb str r3, [r7, #72] @ 0x48 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000fc6: f107 0324 add.w r3, r7, #36 @ 0x24 8000fca: 4618 mov r0, r3 8000fcc: f003 ffa0 bl 8004f10 8000fd0: 4603 mov r3, r0 8000fd2: 2b00 cmp r3, #0 8000fd4: d001 beq.n 8000fda { Error_Handler(); 8000fd6: f7ff feef bl 8000db8 } /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); 8000fda: 2300 movs r3, #0 8000fdc: 623b str r3, [r7, #32] 8000fde: 4b7a ldr r3, [pc, #488] @ (80011c8 ) 8000fe0: 6c5b ldr r3, [r3, #68] @ 0x44 8000fe2: 4a79 ldr r2, [pc, #484] @ (80011c8 ) 8000fe4: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8000fe8: 6453 str r3, [r2, #68] @ 0x44 8000fea: 4b77 ldr r3, [pc, #476] @ (80011c8 ) 8000fec: 6c5b ldr r3, [r3, #68] @ 0x44 8000fee: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8000ff2: 623b str r3, [r7, #32] 8000ff4: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000ff6: 2300 movs r3, #0 8000ff8: 61fb str r3, [r7, #28] 8000ffa: 4b73 ldr r3, [pc, #460] @ (80011c8 ) 8000ffc: 6b1b ldr r3, [r3, #48] @ 0x30 8000ffe: 4a72 ldr r2, [pc, #456] @ (80011c8 ) 8001000: f043 0320 orr.w r3, r3, #32 8001004: 6313 str r3, [r2, #48] @ 0x30 8001006: 4b70 ldr r3, [pc, #448] @ (80011c8 ) 8001008: 6b1b ldr r3, [r3, #48] @ 0x30 800100a: f003 0320 and.w r3, r3, #32 800100e: 61fb str r3, [r7, #28] 8001010: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001012: 2300 movs r3, #0 8001014: 61bb str r3, [r7, #24] 8001016: 4b6c ldr r3, [pc, #432] @ (80011c8 ) 8001018: 6b1b ldr r3, [r3, #48] @ 0x30 800101a: 4a6b ldr r2, [pc, #428] @ (80011c8 ) 800101c: f043 0301 orr.w r3, r3, #1 8001020: 6313 str r3, [r2, #48] @ 0x30 8001022: 4b69 ldr r3, [pc, #420] @ (80011c8 ) 8001024: 6b1b ldr r3, [r3, #48] @ 0x30 8001026: f003 0301 and.w r3, r3, #1 800102a: 61bb str r3, [r7, #24] 800102c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 800102e: 2300 movs r3, #0 8001030: 617b str r3, [r7, #20] 8001032: 4b65 ldr r3, [pc, #404] @ (80011c8 ) 8001034: 6b1b ldr r3, [r3, #48] @ 0x30 8001036: 4a64 ldr r2, [pc, #400] @ (80011c8 ) 8001038: f043 0302 orr.w r3, r3, #2 800103c: 6313 str r3, [r2, #48] @ 0x30 800103e: 4b62 ldr r3, [pc, #392] @ (80011c8 ) 8001040: 6b1b ldr r3, [r3, #48] @ 0x30 8001042: f003 0302 and.w r3, r3, #2 8001046: 617b str r3, [r7, #20] 8001048: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOG_CLK_ENABLE(); 800104a: 2300 movs r3, #0 800104c: 613b str r3, [r7, #16] 800104e: 4b5e ldr r3, [pc, #376] @ (80011c8 ) 8001050: 6b1b ldr r3, [r3, #48] @ 0x30 8001052: 4a5d ldr r2, [pc, #372] @ (80011c8 ) 8001054: f043 0340 orr.w r3, r3, #64 @ 0x40 8001058: 6313 str r3, [r2, #48] @ 0x30 800105a: 4b5b ldr r3, [pc, #364] @ (80011c8 ) 800105c: 6b1b ldr r3, [r3, #48] @ 0x30 800105e: f003 0340 and.w r3, r3, #64 @ 0x40 8001062: 613b str r3, [r7, #16] 8001064: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8001066: 2300 movs r3, #0 8001068: 60fb str r3, [r7, #12] 800106a: 4b57 ldr r3, [pc, #348] @ (80011c8 ) 800106c: 6b1b ldr r3, [r3, #48] @ 0x30 800106e: 4a56 ldr r2, [pc, #344] @ (80011c8 ) 8001070: f043 0304 orr.w r3, r3, #4 8001074: 6313 str r3, [r2, #48] @ 0x30 8001076: 4b54 ldr r3, [pc, #336] @ (80011c8 ) 8001078: 6b1b ldr r3, [r3, #48] @ 0x30 800107a: f003 0304 and.w r3, r3, #4 800107e: 60fb str r3, [r7, #12] 8001080: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8001082: 2300 movs r3, #0 8001084: 60bb str r3, [r7, #8] 8001086: 4b50 ldr r3, [pc, #320] @ (80011c8 ) 8001088: 6b1b ldr r3, [r3, #48] @ 0x30 800108a: 4a4f ldr r2, [pc, #316] @ (80011c8 ) 800108c: f043 0308 orr.w r3, r3, #8 8001090: 6313 str r3, [r2, #48] @ 0x30 8001092: 4b4d ldr r3, [pc, #308] @ (80011c8 ) 8001094: 6b1b ldr r3, [r3, #48] @ 0x30 8001096: f003 0308 and.w r3, r3, #8 800109a: 60bb str r3, [r7, #8] 800109c: 68bb ldr r3, [r7, #8] PG11 ------> LTDC_B3 PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 */ GPIO_InitStruct.Pin = ENABLE_Pin; 800109e: f44f 6380 mov.w r3, #1024 @ 0x400 80010a2: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010a4: 2302 movs r3, #2 80010a6: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010a8: 2300 movs r3, #0 80010aa: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010ac: 2300 movs r3, #0 80010ae: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 80010b0: 230e movs r3, #14 80010b2: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct); 80010b4: f107 0354 add.w r3, r7, #84 @ 0x54 80010b8: 4619 mov r1, r3 80010ba: 4844 ldr r0, [pc, #272] @ (80011cc ) 80010bc: f000 fe08 bl 8001cd0 GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin 80010c0: f641 0358 movw r3, #6232 @ 0x1858 80010c4: 657b str r3, [r7, #84] @ 0x54 |R5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010c6: 2302 movs r3, #2 80010c8: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010ca: 2300 movs r3, #0 80010cc: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010ce: 2300 movs r3, #0 80010d0: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 80010d2: 230e movs r3, #14 80010d4: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80010d6: f107 0354 add.w r3, r7, #84 @ 0x54 80010da: 4619 mov r1, r3 80010dc: 483c ldr r0, [pc, #240] @ (80011d0 ) 80010de: f000 fdf7 bl 8001cd0 GPIO_InitStruct.Pin = R3_Pin|R6_Pin; 80010e2: 2303 movs r3, #3 80010e4: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010e6: 2302 movs r3, #2 80010e8: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010ea: 2300 movs r3, #0 80010ec: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010ee: 2300 movs r3, #0 80010f0: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 80010f2: 2309 movs r3, #9 80010f4: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80010f6: f107 0354 add.w r3, r7, #84 @ 0x54 80010fa: 4619 mov r1, r3 80010fc: 4835 ldr r0, [pc, #212] @ (80011d4 ) 80010fe: f000 fde7 bl 8001cd0 GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin; 8001102: f44f 6370 mov.w r3, #3840 @ 0xf00 8001106: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001108: 2302 movs r3, #2 800110a: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800110c: 2300 movs r3, #0 800110e: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001110: 2300 movs r3, #0 8001112: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001114: 230e movs r3, #14 8001116: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001118: f107 0354 add.w r3, r7, #84 @ 0x54 800111c: 4619 mov r1, r3 800111e: 482d ldr r0, [pc, #180] @ (80011d4 ) 8001120: f000 fdd6 bl 8001cd0 GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin; 8001124: f44f 630c mov.w r3, #2240 @ 0x8c0 8001128: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800112a: 2302 movs r3, #2 800112c: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800112e: 2300 movs r3, #0 8001130: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001132: 2300 movs r3, #0 8001134: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001136: 230e movs r3, #14 8001138: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800113a: f107 0354 add.w r3, r7, #84 @ 0x54 800113e: 4619 mov r1, r3 8001140: 4825 ldr r0, [pc, #148] @ (80011d8 ) 8001142: f000 fdc5 bl 8001cd0 GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin; 8001146: f44f 6398 mov.w r3, #1216 @ 0x4c0 800114a: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800114c: 2302 movs r3, #2 800114e: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001150: 2300 movs r3, #0 8001152: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001154: 2300 movs r3, #0 8001156: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001158: 230e movs r3, #14 800115a: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 800115c: f107 0354 add.w r3, r7, #84 @ 0x54 8001160: 4619 mov r1, r3 8001162: 481e ldr r0, [pc, #120] @ (80011dc ) 8001164: f000 fdb4 bl 8001cd0 GPIO_InitStruct.Pin = G7_Pin|B2_Pin; 8001168: 2348 movs r3, #72 @ 0x48 800116a: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800116c: 2302 movs r3, #2 800116e: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001170: 2300 movs r3, #0 8001172: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001174: 2300 movs r3, #0 8001176: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001178: 230e movs r3, #14 800117a: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800117c: f107 0354 add.w r3, r7, #84 @ 0x54 8001180: 4619 mov r1, r3 8001182: 4817 ldr r0, [pc, #92] @ (80011e0 ) 8001184: f000 fda4 bl 8001cd0 GPIO_InitStruct.Pin = G3_Pin|B4_Pin; 8001188: f44f 53a0 mov.w r3, #5120 @ 0x1400 800118c: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800118e: 2302 movs r3, #2 8001190: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001192: 2300 movs r3, #0 8001194: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001196: 2300 movs r3, #0 8001198: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 800119a: 2309 movs r3, #9 800119c: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800119e: f107 0354 add.w r3, r7, #84 @ 0x54 80011a2: 4619 mov r1, r3 80011a4: 480c ldr r0, [pc, #48] @ (80011d8 ) 80011a6: f000 fd93 bl 8001cd0 /* LTDC interrupt Init */ HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0); 80011aa: 2200 movs r2, #0 80011ac: 2105 movs r1, #5 80011ae: 2058 movs r0, #88 @ 0x58 80011b0: f000 fb5c bl 800186c HAL_NVIC_EnableIRQ(LTDC_IRQn); 80011b4: 2058 movs r0, #88 @ 0x58 80011b6: f000 fb75 bl 80018a4 /* USER CODE END LTDC_MspInit 1 */ } } 80011ba: bf00 nop 80011bc: 3768 adds r7, #104 @ 0x68 80011be: 46bd mov sp, r7 80011c0: bd80 pop {r7, pc} 80011c2: bf00 nop 80011c4: 40016800 .word 0x40016800 80011c8: 40023800 .word 0x40023800 80011cc: 40021400 .word 0x40021400 80011d0: 40020000 .word 0x40020000 80011d4: 40020400 .word 0x40020400 80011d8: 40021800 .word 0x40021800 80011dc: 40020800 .word 0x40020800 80011e0: 40020c00 .word 0x40020c00 080011e4 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 80011e4: b580 push {r7, lr} 80011e6: b08a sub sp, #40 @ 0x28 80011e8: af00 add r7, sp, #0 80011ea: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80011ec: f107 0314 add.w r3, r7, #20 80011f0: 2200 movs r2, #0 80011f2: 601a str r2, [r3, #0] 80011f4: 605a str r2, [r3, #4] 80011f6: 609a str r2, [r3, #8] 80011f8: 60da str r2, [r3, #12] 80011fa: 611a str r2, [r3, #16] if(hspi->Instance==SPI5) 80011fc: 687b ldr r3, [r7, #4] 80011fe: 681b ldr r3, [r3, #0] 8001200: 4a19 ldr r2, [pc, #100] @ (8001268 ) 8001202: 4293 cmp r3, r2 8001204: d12c bne.n 8001260 { /* USER CODE BEGIN SPI5_MspInit 0 */ /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); 8001206: 2300 movs r3, #0 8001208: 613b str r3, [r7, #16] 800120a: 4b18 ldr r3, [pc, #96] @ (800126c ) 800120c: 6c5b ldr r3, [r3, #68] @ 0x44 800120e: 4a17 ldr r2, [pc, #92] @ (800126c ) 8001210: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001214: 6453 str r3, [r2, #68] @ 0x44 8001216: 4b15 ldr r3, [pc, #84] @ (800126c ) 8001218: 6c5b ldr r3, [r3, #68] @ 0x44 800121a: f403 1380 and.w r3, r3, #1048576 @ 0x100000 800121e: 613b str r3, [r7, #16] 8001220: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOF_CLK_ENABLE(); 8001222: 2300 movs r3, #0 8001224: 60fb str r3, [r7, #12] 8001226: 4b11 ldr r3, [pc, #68] @ (800126c ) 8001228: 6b1b ldr r3, [r3, #48] @ 0x30 800122a: 4a10 ldr r2, [pc, #64] @ (800126c ) 800122c: f043 0320 orr.w r3, r3, #32 8001230: 6313 str r3, [r2, #48] @ 0x30 8001232: 4b0e ldr r3, [pc, #56] @ (800126c ) 8001234: 6b1b ldr r3, [r3, #48] @ 0x30 8001236: f003 0320 and.w r3, r3, #32 800123a: 60fb str r3, [r7, #12] 800123c: 68fb ldr r3, [r7, #12] /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO PF9 ------> SPI5_MOSI */ GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin; 800123e: f44f 7360 mov.w r3, #896 @ 0x380 8001242: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001244: 2302 movs r3, #2 8001246: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001248: 2300 movs r3, #0 800124a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800124c: 2300 movs r3, #0 800124e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; 8001250: 2305 movs r3, #5 8001252: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8001254: f107 0314 add.w r3, r7, #20 8001258: 4619 mov r1, r3 800125a: 4805 ldr r0, [pc, #20] @ (8001270 ) 800125c: f000 fd38 bl 8001cd0 /* USER CODE END SPI5_MspInit 1 */ } } 8001260: bf00 nop 8001262: 3728 adds r7, #40 @ 0x28 8001264: 46bd mov sp, r7 8001266: bd80 pop {r7, pc} 8001268: 40015000 .word 0x40015000 800126c: 40023800 .word 0x40023800 8001270: 40021400 .word 0x40021400 08001274 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8001274: b480 push {r7} 8001276: b085 sub sp, #20 8001278: af00 add r7, sp, #0 800127a: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 800127c: 687b ldr r3, [r7, #4] 800127e: 681b ldr r3, [r3, #0] 8001280: 4a0b ldr r2, [pc, #44] @ (80012b0 ) 8001282: 4293 cmp r3, r2 8001284: d10d bne.n 80012a2 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8001286: 2300 movs r3, #0 8001288: 60fb str r3, [r7, #12] 800128a: 4b0a ldr r3, [pc, #40] @ (80012b4 ) 800128c: 6c5b ldr r3, [r3, #68] @ 0x44 800128e: 4a09 ldr r2, [pc, #36] @ (80012b4 ) 8001290: f043 0301 orr.w r3, r3, #1 8001294: 6453 str r3, [r2, #68] @ 0x44 8001296: 4b07 ldr r3, [pc, #28] @ (80012b4 ) 8001298: 6c5b ldr r3, [r3, #68] @ 0x44 800129a: f003 0301 and.w r3, r3, #1 800129e: 60fb str r3, [r7, #12] 80012a0: 68fb ldr r3, [r7, #12] /* USER CODE END TIM1_MspInit 1 */ } } 80012a2: bf00 nop 80012a4: 3714 adds r7, #20 80012a6: 46bd mov sp, r7 80012a8: f85d 7b04 ldr.w r7, [sp], #4 80012ac: 4770 bx lr 80012ae: bf00 nop 80012b0: 40010000 .word 0x40010000 80012b4: 40023800 .word 0x40023800 080012b8 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 80012b8: b580 push {r7, lr} 80012ba: b08a sub sp, #40 @ 0x28 80012bc: af00 add r7, sp, #0 80012be: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 80012c0: f107 0314 add.w r3, r7, #20 80012c4: 2200 movs r2, #0 80012c6: 601a str r2, [r3, #0] 80012c8: 605a str r2, [r3, #4] 80012ca: 609a str r2, [r3, #8] 80012cc: 60da str r2, [r3, #12] 80012ce: 611a str r2, [r3, #16] if(huart->Instance==USART1) 80012d0: 687b ldr r3, [r7, #4] 80012d2: 681b ldr r3, [r3, #0] 80012d4: 4a19 ldr r2, [pc, #100] @ (800133c ) 80012d6: 4293 cmp r3, r2 80012d8: d12c bne.n 8001334 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 80012da: 2300 movs r3, #0 80012dc: 613b str r3, [r7, #16] 80012de: 4b18 ldr r3, [pc, #96] @ (8001340 ) 80012e0: 6c5b ldr r3, [r3, #68] @ 0x44 80012e2: 4a17 ldr r2, [pc, #92] @ (8001340 ) 80012e4: f043 0310 orr.w r3, r3, #16 80012e8: 6453 str r3, [r2, #68] @ 0x44 80012ea: 4b15 ldr r3, [pc, #84] @ (8001340 ) 80012ec: 6c5b ldr r3, [r3, #68] @ 0x44 80012ee: f003 0310 and.w r3, r3, #16 80012f2: 613b str r3, [r7, #16] 80012f4: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 80012f6: 2300 movs r3, #0 80012f8: 60fb str r3, [r7, #12] 80012fa: 4b11 ldr r3, [pc, #68] @ (8001340 ) 80012fc: 6b1b ldr r3, [r3, #48] @ 0x30 80012fe: 4a10 ldr r2, [pc, #64] @ (8001340 ) 8001300: f043 0301 orr.w r3, r3, #1 8001304: 6313 str r3, [r2, #48] @ 0x30 8001306: 4b0e ldr r3, [pc, #56] @ (8001340 ) 8001308: 6b1b ldr r3, [r3, #48] @ 0x30 800130a: f003 0301 and.w r3, r3, #1 800130e: 60fb str r3, [r7, #12] 8001310: 68fb ldr r3, [r7, #12] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; 8001312: f44f 63c0 mov.w r3, #1536 @ 0x600 8001316: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001318: 2302 movs r3, #2 800131a: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 800131c: 2300 movs r3, #0 800131e: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001320: 2303 movs r3, #3 8001322: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001324: 2307 movs r3, #7 8001326: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8001328: f107 0314 add.w r3, r7, #20 800132c: 4619 mov r1, r3 800132e: 4805 ldr r0, [pc, #20] @ (8001344 ) 8001330: f000 fcce bl 8001cd0 /* USER CODE END USART1_MspInit 1 */ } } 8001334: bf00 nop 8001336: 3728 adds r7, #40 @ 0x28 8001338: 46bd mov sp, r7 800133a: bd80 pop {r7, pc} 800133c: 40011000 .word 0x40011000 8001340: 40023800 .word 0x40023800 8001344: 40020000 .word 0x40020000 08001348 : } static uint32_t FMC_Initialized = 0; static void HAL_FMC_MspInit(void){ 8001348: b580 push {r7, lr} 800134a: b086 sub sp, #24 800134c: af00 add r7, sp, #0 /* USER CODE BEGIN FMC_MspInit 0 */ /* USER CODE END FMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 800134e: 1d3b adds r3, r7, #4 8001350: 2200 movs r2, #0 8001352: 601a str r2, [r3, #0] 8001354: 605a str r2, [r3, #4] 8001356: 609a str r2, [r3, #8] 8001358: 60da str r2, [r3, #12] 800135a: 611a str r2, [r3, #16] if (FMC_Initialized) { 800135c: 4b3b ldr r3, [pc, #236] @ (800144c ) 800135e: 681b ldr r3, [r3, #0] 8001360: 2b00 cmp r3, #0 8001362: d16f bne.n 8001444 return; } FMC_Initialized = 1; 8001364: 4b39 ldr r3, [pc, #228] @ (800144c ) 8001366: 2201 movs r2, #1 8001368: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); 800136a: 2300 movs r3, #0 800136c: 603b str r3, [r7, #0] 800136e: 4b38 ldr r3, [pc, #224] @ (8001450 ) 8001370: 6b9b ldr r3, [r3, #56] @ 0x38 8001372: 4a37 ldr r2, [pc, #220] @ (8001450 ) 8001374: f043 0301 orr.w r3, r3, #1 8001378: 6393 str r3, [r2, #56] @ 0x38 800137a: 4b35 ldr r3, [pc, #212] @ (8001450 ) 800137c: 6b9b ldr r3, [r3, #56] @ 0x38 800137e: f003 0301 and.w r3, r3, #1 8001382: 603b str r3, [r7, #0] 8001384: 683b ldr r3, [r7, #0] PB5 ------> FMC_SDCKE1 PB6 ------> FMC_SDNE1 PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin 8001386: f64f 033f movw r3, #63551 @ 0xf83f 800138a: 607b str r3, [r7, #4] |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin |A7_Pin|A8_Pin|A9_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800138c: 2302 movs r3, #2 800138e: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001390: 2300 movs r3, #0 8001392: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001394: 2303 movs r3, #3 8001396: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 8001398: 230c movs r3, #12 800139a: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 800139c: 1d3b adds r3, r7, #4 800139e: 4619 mov r1, r3 80013a0: 482c ldr r0, [pc, #176] @ (8001454 ) 80013a2: f000 fc95 bl 8001cd0 GPIO_InitStruct.Pin = SDNWE_Pin; 80013a6: 2301 movs r3, #1 80013a8: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013aa: 2302 movs r3, #2 80013ac: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013ae: 2300 movs r3, #0 80013b0: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013b2: 2303 movs r3, #3 80013b4: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 80013b6: 230c movs r3, #12 80013b8: 617b str r3, [r7, #20] HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct); 80013ba: 1d3b adds r3, r7, #4 80013bc: 4619 mov r1, r3 80013be: 4826 ldr r0, [pc, #152] @ (8001458 ) 80013c0: f000 fc86 bl 8001cd0 GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin 80013c4: f248 1333 movw r3, #33075 @ 0x8133 80013c8: 607b str r3, [r7, #4] |SDCLK_Pin|SDNCAS_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013ca: 2302 movs r3, #2 80013cc: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013ce: 2300 movs r3, #0 80013d0: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013d2: 2303 movs r3, #3 80013d4: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 80013d6: 230c movs r3, #12 80013d8: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 80013da: 1d3b adds r3, r7, #4 80013dc: 4619 mov r1, r3 80013de: 481f ldr r0, [pc, #124] @ (800145c ) 80013e0: f000 fc76 bl 8001cd0 GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin 80013e4: f64f 7383 movw r3, #65411 @ 0xff83 80013e8: 607b str r3, [r7, #4] |D8_Pin|D9_Pin|D10_Pin|D11_Pin |D12_Pin|NBL0_Pin|NBL1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80013ea: 2302 movs r3, #2 80013ec: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013ee: 2300 movs r3, #0 80013f0: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013f2: 2303 movs r3, #3 80013f4: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 80013f6: 230c movs r3, #12 80013f8: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 80013fa: 1d3b adds r3, r7, #4 80013fc: 4619 mov r1, r3 80013fe: 4818 ldr r0, [pc, #96] @ (8001460 ) 8001400: f000 fc66 bl 8001cd0 GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin 8001404: f24c 7303 movw r3, #50947 @ 0xc703 8001408: 607b str r3, [r7, #4] |D1_Pin|D2_Pin|D3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800140a: 2302 movs r3, #2 800140c: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 800140e: 2300 movs r3, #0 8001410: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001412: 2303 movs r3, #3 8001414: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 8001416: 230c movs r3, #12 8001418: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800141a: 1d3b adds r3, r7, #4 800141c: 4619 mov r1, r3 800141e: 4811 ldr r0, [pc, #68] @ (8001464 ) 8001420: f000 fc56 bl 8001cd0 GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin; 8001424: 2360 movs r3, #96 @ 0x60 8001426: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001428: 2302 movs r3, #2 800142a: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 800142c: 2300 movs r3, #0 800142e: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001430: 2303 movs r3, #3 8001432: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 8001434: 230c movs r3, #12 8001436: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001438: 1d3b adds r3, r7, #4 800143a: 4619 mov r1, r3 800143c: 480a ldr r0, [pc, #40] @ (8001468 ) 800143e: f000 fc47 bl 8001cd0 8001442: e000 b.n 8001446 return; 8001444: bf00 nop /* USER CODE BEGIN FMC_MspInit 1 */ /* USER CODE END FMC_MspInit 1 */ } 8001446: 3718 adds r7, #24 8001448: 46bd mov sp, r7 800144a: bd80 pop {r7, pc} 800144c: 20000298 .word 0x20000298 8001450: 40023800 .word 0x40023800 8001454: 40021400 .word 0x40021400 8001458: 40020800 .word 0x40020800 800145c: 40021800 .word 0x40021800 8001460: 40021000 .word 0x40021000 8001464: 40020c00 .word 0x40020c00 8001468: 40020400 .word 0x40020400 0800146c : void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ 800146c: b580 push {r7, lr} 800146e: b082 sub sp, #8 8001470: af00 add r7, sp, #0 8001472: 6078 str r0, [r7, #4] /* USER CODE BEGIN SDRAM_MspInit 0 */ /* USER CODE END SDRAM_MspInit 0 */ HAL_FMC_MspInit(); 8001474: f7ff ff68 bl 8001348 /* USER CODE BEGIN SDRAM_MspInit 1 */ /* USER CODE END SDRAM_MspInit 1 */ } 8001478: bf00 nop 800147a: 3708 adds r7, #8 800147c: 46bd mov sp, r7 800147e: bd80 pop {r7, pc} 08001480 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8001480: b580 push {r7, lr} 8001482: b08e sub sp, #56 @ 0x38 8001484: af00 add r7, sp, #0 8001486: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock, uwAPB1Prescaler = 0U; 8001488: 2300 movs r3, #0 800148a: 62fb str r3, [r7, #44] @ 0x2c uint32_t uwPrescalerValue = 0U; 800148c: 2300 movs r3, #0 800148e: 62bb str r3, [r7, #40] @ 0x28 uint32_t pFLatency; HAL_StatusTypeDef status; /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8001490: 2300 movs r3, #0 8001492: 60fb str r3, [r7, #12] 8001494: 4b33 ldr r3, [pc, #204] @ (8001564 ) 8001496: 6c1b ldr r3, [r3, #64] @ 0x40 8001498: 4a32 ldr r2, [pc, #200] @ (8001564 ) 800149a: f043 0310 orr.w r3, r3, #16 800149e: 6413 str r3, [r2, #64] @ 0x40 80014a0: 4b30 ldr r3, [pc, #192] @ (8001564 ) 80014a2: 6c1b ldr r3, [r3, #64] @ 0x40 80014a4: f003 0310 and.w r3, r3, #16 80014a8: 60fb str r3, [r7, #12] 80014aa: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 80014ac: f107 0210 add.w r2, r7, #16 80014b0: f107 0314 add.w r3, r7, #20 80014b4: 4611 mov r1, r2 80014b6: 4618 mov r0, r3 80014b8: f003 fcf8 bl 8004eac /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 80014bc: 6a3b ldr r3, [r7, #32] 80014be: 62fb str r3, [r7, #44] @ 0x2c /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 80014c0: 6afb ldr r3, [r7, #44] @ 0x2c 80014c2: 2b00 cmp r3, #0 80014c4: d103 bne.n 80014ce { uwTimclock = HAL_RCC_GetPCLK1Freq(); 80014c6: f003 fcc9 bl 8004e5c 80014ca: 6378 str r0, [r7, #52] @ 0x34 80014cc: e004 b.n 80014d8 } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 80014ce: f003 fcc5 bl 8004e5c 80014d2: 4603 mov r3, r0 80014d4: 005b lsls r3, r3, #1 80014d6: 637b str r3, [r7, #52] @ 0x34 } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 80014d8: 6b7b ldr r3, [r7, #52] @ 0x34 80014da: 4a23 ldr r2, [pc, #140] @ (8001568 ) 80014dc: fba2 2303 umull r2, r3, r2, r3 80014e0: 0c9b lsrs r3, r3, #18 80014e2: 3b01 subs r3, #1 80014e4: 62bb str r3, [r7, #40] @ 0x28 /* Initialize TIM6 */ htim6.Instance = TIM6; 80014e6: 4b21 ldr r3, [pc, #132] @ (800156c ) 80014e8: 4a21 ldr r2, [pc, #132] @ (8001570 ) 80014ea: 601a str r2, [r3, #0] * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 80014ec: 4b1f ldr r3, [pc, #124] @ (800156c ) 80014ee: f240 32e7 movw r2, #999 @ 0x3e7 80014f2: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 80014f4: 4a1d ldr r2, [pc, #116] @ (800156c ) 80014f6: 6abb ldr r3, [r7, #40] @ 0x28 80014f8: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 80014fa: 4b1c ldr r3, [pc, #112] @ (800156c ) 80014fc: 2200 movs r2, #0 80014fe: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001500: 4b1a ldr r3, [pc, #104] @ (800156c ) 8001502: 2200 movs r2, #0 8001504: 609a str r2, [r3, #8] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001506: 4b19 ldr r3, [pc, #100] @ (800156c ) 8001508: 2200 movs r2, #0 800150a: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim6); 800150c: 4817 ldr r0, [pc, #92] @ (800156c ) 800150e: f003 ff7c bl 800540a 8001512: 4603 mov r3, r0 8001514: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 8001518: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 800151c: 2b00 cmp r3, #0 800151e: d11b bne.n 8001558 { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim6); 8001520: 4812 ldr r0, [pc, #72] @ (800156c ) 8001522: f003 ffc1 bl 80054a8 8001526: 4603 mov r3, r0 8001528: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 800152c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8001530: 2b00 cmp r3, #0 8001532: d111 bne.n 8001558 { /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 8001534: 2036 movs r0, #54 @ 0x36 8001536: f000 f9b5 bl 80018a4 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 800153a: 687b ldr r3, [r7, #4] 800153c: 2b0f cmp r3, #15 800153e: d808 bhi.n 8001552 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); 8001540: 2200 movs r2, #0 8001542: 6879 ldr r1, [r7, #4] 8001544: 2036 movs r0, #54 @ 0x36 8001546: f000 f991 bl 800186c uwTickPrio = TickPriority; 800154a: 4a0a ldr r2, [pc, #40] @ (8001574 ) 800154c: 687b ldr r3, [r7, #4] 800154e: 6013 str r3, [r2, #0] 8001550: e002 b.n 8001558 } else { status = HAL_ERROR; 8001552: 2301 movs r3, #1 8001554: f887 3033 strb.w r3, [r7, #51] @ 0x33 } } } /* Return function status */ return status; 8001558: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 } 800155c: 4618 mov r0, r3 800155e: 3738 adds r7, #56 @ 0x38 8001560: 46bd mov sp, r7 8001562: bd80 pop {r7, pc} 8001564: 40023800 .word 0x40023800 8001568: 431bde83 .word 0x431bde83 800156c: 2000029c .word 0x2000029c 8001570: 40001000 .word 0x40001000 8001574: 20000004 .word 0x20000004 08001578 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001578: b480 push {r7} 800157a: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 800157c: bf00 nop 800157e: e7fd b.n 800157c 08001580 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001580: b480 push {r7} 8001582: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8001584: bf00 nop 8001586: e7fd b.n 8001584 08001588 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001588: b480 push {r7} 800158a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 800158c: bf00 nop 800158e: e7fd b.n 800158c 08001590 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001590: b480 push {r7} 8001592: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001594: bf00 nop 8001596: e7fd b.n 8001594 08001598 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001598: b480 push {r7} 800159a: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 800159c: bf00 nop 800159e: e7fd b.n 800159c 080015a0 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 80015a0: b480 push {r7} 80015a2: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 80015a4: bf00 nop 80015a6: 46bd mov sp, r7 80015a8: f85d 7b04 ldr.w r7, [sp], #4 80015ac: 4770 bx lr ... 080015b0 : /** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 80015b0: b580 push {r7, lr} 80015b2: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 80015b4: 4802 ldr r0, [pc, #8] @ (80015c0 ) 80015b6: f003 ffe7 bl 8005588 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 80015ba: bf00 nop 80015bc: bd80 pop {r7, pc} 80015be: bf00 nop 80015c0: 2000029c .word 0x2000029c 080015c4 : /** * @brief This function handles USB On The Go HS global interrupt. */ void OTG_HS_IRQHandler(void) { 80015c4: b580 push {r7, lr} 80015c6: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_HS_IRQn 0 */ /* USER CODE END OTG_HS_IRQn 0 */ HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS); 80015c8: 4802 ldr r0, [pc, #8] @ (80015d4 ) 80015ca: f000 fd60 bl 800208e /* USER CODE BEGIN OTG_HS_IRQn 1 */ /* USER CODE END OTG_HS_IRQn 1 */ } 80015ce: bf00 nop 80015d0: bd80 pop {r7, pc} 80015d2: bf00 nop 80015d4: 200003d4 .word 0x200003d4 080015d8 : /** * @brief This function handles LTDC global interrupt. */ void LTDC_IRQHandler(void) { 80015d8: b580 push {r7, lr} 80015da: af00 add r7, sp, #0 /* USER CODE BEGIN LTDC_IRQn 0 */ /* USER CODE END LTDC_IRQn 0 */ HAL_LTDC_IRQHandler(&hltdc); 80015dc: 4802 ldr r0, [pc, #8] @ (80015e8 ) 80015de: f002 fd59 bl 8004094 /* USER CODE BEGIN LTDC_IRQn 1 */ /* USER CODE END LTDC_IRQn 1 */ } 80015e2: bf00 nop 80015e4: bd80 pop {r7, pc} 80015e6: bf00 nop 80015e8: 200000d4 .word 0x200000d4 080015ec : /** * @brief This function handles DMA2D global interrupt. */ void DMA2D_IRQHandler(void) { 80015ec: b580 push {r7, lr} 80015ee: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2D_IRQn 0 */ /* USER CODE END DMA2D_IRQn 0 */ HAL_DMA2D_IRQHandler(&hdma2d); 80015f0: 4802 ldr r0, [pc, #8] @ (80015fc ) 80015f2: f000 f9ca bl 800198a /* USER CODE BEGIN DMA2D_IRQn 1 */ /* USER CODE END DMA2D_IRQn 1 */ } 80015f6: bf00 nop 80015f8: bd80 pop {r7, pc} 80015fa: bf00 nop 80015fc: 20000040 .word 0x20000040 08001600 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001600: b480 push {r7} 8001602: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001604: 4b06 ldr r3, [pc, #24] @ (8001620 ) 8001606: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800160a: 4a05 ldr r2, [pc, #20] @ (8001620 ) 800160c: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001610: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001614: bf00 nop 8001616: 46bd mov sp, r7 8001618: f85d 7b04 ldr.w r7, [sp], #4 800161c: 4770 bx lr 800161e: bf00 nop 8001620: e000ed00 .word 0xe000ed00 08001624 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001624: f8df d034 ldr.w sp, [pc, #52] @ 800165c /* Call the clock system initialization function.*/ bl SystemInit 8001628: f7ff ffea bl 8001600 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 800162c: 480c ldr r0, [pc, #48] @ (8001660 ) ldr r1, =_edata 800162e: 490d ldr r1, [pc, #52] @ (8001664 ) ldr r2, =_sidata 8001630: 4a0d ldr r2, [pc, #52] @ (8001668 ) movs r3, #0 8001632: 2300 movs r3, #0 b LoopCopyDataInit 8001634: e002 b.n 800163c 08001636 : CopyDataInit: ldr r4, [r2, r3] 8001636: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 8001638: 50c4 str r4, [r0, r3] adds r3, r3, #4 800163a: 3304 adds r3, #4 0800163c : LoopCopyDataInit: adds r4, r0, r3 800163c: 18c4 adds r4, r0, r3 cmp r4, r1 800163e: 428c cmp r4, r1 bcc CopyDataInit 8001640: d3f9 bcc.n 8001636 /* Zero fill the bss segment. */ ldr r2, =_sbss 8001642: 4a0a ldr r2, [pc, #40] @ (800166c ) ldr r4, =_ebss 8001644: 4c0a ldr r4, [pc, #40] @ (8001670 ) movs r3, #0 8001646: 2300 movs r3, #0 b LoopFillZerobss 8001648: e001 b.n 800164e 0800164a : FillZerobss: str r3, [r2] 800164a: 6013 str r3, [r2, #0] adds r2, r2, #4 800164c: 3204 adds r2, #4 0800164e : LoopFillZerobss: cmp r2, r4 800164e: 42a2 cmp r2, r4 bcc FillZerobss 8001650: d3fb bcc.n 800164a /* Call static constructors */ bl __libc_init_array 8001652: f006 fc4d bl 8007ef0 <__libc_init_array> /* Call the application's entry point.*/ bl main 8001656: f7fe ffe8 bl 800062a
bx lr 800165a: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 800165c: 20030000 .word 0x20030000 ldr r0, =_sdata 8001660: 20000000 .word 0x20000000 ldr r1, =_edata 8001664: 20000010 .word 0x20000010 ldr r2, =_sidata 8001668: 08007f94 .word 0x08007f94 ldr r2, =_sbss 800166c: 20000010 .word 0x20000010 ldr r4, =_ebss 8001670: 200007b4 .word 0x200007b4 08001674 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8001674: e7fe b.n 8001674 ... 08001678 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8001678: b580 push {r7, lr} 800167a: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 800167c: 4b0e ldr r3, [pc, #56] @ (80016b8 ) 800167e: 681b ldr r3, [r3, #0] 8001680: 4a0d ldr r2, [pc, #52] @ (80016b8 ) 8001682: f443 7300 orr.w r3, r3, #512 @ 0x200 8001686: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 8001688: 4b0b ldr r3, [pc, #44] @ (80016b8 ) 800168a: 681b ldr r3, [r3, #0] 800168c: 4a0a ldr r2, [pc, #40] @ (80016b8 ) 800168e: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001692: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001694: 4b08 ldr r3, [pc, #32] @ (80016b8 ) 8001696: 681b ldr r3, [r3, #0] 8001698: 4a07 ldr r2, [pc, #28] @ (80016b8 ) 800169a: f443 7380 orr.w r3, r3, #256 @ 0x100 800169e: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 80016a0: 2003 movs r0, #3 80016a2: f000 f8d8 bl 8001856 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 80016a6: 2000 movs r0, #0 80016a8: f7ff feea bl 8001480 /* Init the low level hardware */ HAL_MspInit(); 80016ac: f7ff fb8a bl 8000dc4 /* Return function status */ return HAL_OK; 80016b0: 2300 movs r3, #0 } 80016b2: 4618 mov r0, r3 80016b4: bd80 pop {r7, pc} 80016b6: bf00 nop 80016b8: 40023c00 .word 0x40023c00 080016bc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80016bc: b480 push {r7} 80016be: af00 add r7, sp, #0 uwTick += uwTickFreq; 80016c0: 4b06 ldr r3, [pc, #24] @ (80016dc ) 80016c2: 781b ldrb r3, [r3, #0] 80016c4: 461a mov r2, r3 80016c6: 4b06 ldr r3, [pc, #24] @ (80016e0 ) 80016c8: 681b ldr r3, [r3, #0] 80016ca: 4413 add r3, r2 80016cc: 4a04 ldr r2, [pc, #16] @ (80016e0 ) 80016ce: 6013 str r3, [r2, #0] } 80016d0: bf00 nop 80016d2: 46bd mov sp, r7 80016d4: f85d 7b04 ldr.w r7, [sp], #4 80016d8: 4770 bx lr 80016da: bf00 nop 80016dc: 20000008 .word 0x20000008 80016e0: 200002e4 .word 0x200002e4 080016e4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80016e4: b480 push {r7} 80016e6: af00 add r7, sp, #0 return uwTick; 80016e8: 4b03 ldr r3, [pc, #12] @ (80016f8 ) 80016ea: 681b ldr r3, [r3, #0] } 80016ec: 4618 mov r0, r3 80016ee: 46bd mov sp, r7 80016f0: f85d 7b04 ldr.w r7, [sp], #4 80016f4: 4770 bx lr 80016f6: bf00 nop 80016f8: 200002e4 .word 0x200002e4 080016fc <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80016fc: b480 push {r7} 80016fe: b085 sub sp, #20 8001700: af00 add r7, sp, #0 8001702: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8001704: 687b ldr r3, [r7, #4] 8001706: f003 0307 and.w r3, r3, #7 800170a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 800170c: 4b0c ldr r3, [pc, #48] @ (8001740 <__NVIC_SetPriorityGrouping+0x44>) 800170e: 68db ldr r3, [r3, #12] 8001710: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8001712: 68ba ldr r2, [r7, #8] 8001714: f64f 03ff movw r3, #63743 @ 0xf8ff 8001718: 4013 ands r3, r2 800171a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 800171c: 68fb ldr r3, [r7, #12] 800171e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8001720: 68bb ldr r3, [r7, #8] 8001722: 4313 orrs r3, r2 reg_value = (reg_value | 8001724: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 8001728: f443 3300 orr.w r3, r3, #131072 @ 0x20000 800172c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 800172e: 4a04 ldr r2, [pc, #16] @ (8001740 <__NVIC_SetPriorityGrouping+0x44>) 8001730: 68bb ldr r3, [r7, #8] 8001732: 60d3 str r3, [r2, #12] } 8001734: bf00 nop 8001736: 3714 adds r7, #20 8001738: 46bd mov sp, r7 800173a: f85d 7b04 ldr.w r7, [sp], #4 800173e: 4770 bx lr 8001740: e000ed00 .word 0xe000ed00 08001744 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001744: b480 push {r7} 8001746: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001748: 4b04 ldr r3, [pc, #16] @ (800175c <__NVIC_GetPriorityGrouping+0x18>) 800174a: 68db ldr r3, [r3, #12] 800174c: 0a1b lsrs r3, r3, #8 800174e: f003 0307 and.w r3, r3, #7 } 8001752: 4618 mov r0, r3 8001754: 46bd mov sp, r7 8001756: f85d 7b04 ldr.w r7, [sp], #4 800175a: 4770 bx lr 800175c: e000ed00 .word 0xe000ed00 08001760 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 8001760: b480 push {r7} 8001762: b083 sub sp, #12 8001764: af00 add r7, sp, #0 8001766: 4603 mov r3, r0 8001768: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 800176a: f997 3007 ldrsb.w r3, [r7, #7] 800176e: 2b00 cmp r3, #0 8001770: db0b blt.n 800178a <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8001772: 79fb ldrb r3, [r7, #7] 8001774: f003 021f and.w r2, r3, #31 8001778: 4907 ldr r1, [pc, #28] @ (8001798 <__NVIC_EnableIRQ+0x38>) 800177a: f997 3007 ldrsb.w r3, [r7, #7] 800177e: 095b lsrs r3, r3, #5 8001780: 2001 movs r0, #1 8001782: fa00 f202 lsl.w r2, r0, r2 8001786: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 800178a: bf00 nop 800178c: 370c adds r7, #12 800178e: 46bd mov sp, r7 8001790: f85d 7b04 ldr.w r7, [sp], #4 8001794: 4770 bx lr 8001796: bf00 nop 8001798: e000e100 .word 0xe000e100 0800179c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 800179c: b480 push {r7} 800179e: b083 sub sp, #12 80017a0: af00 add r7, sp, #0 80017a2: 4603 mov r3, r0 80017a4: 6039 str r1, [r7, #0] 80017a6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 80017a8: f997 3007 ldrsb.w r3, [r7, #7] 80017ac: 2b00 cmp r3, #0 80017ae: db0a blt.n 80017c6 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80017b0: 683b ldr r3, [r7, #0] 80017b2: b2da uxtb r2, r3 80017b4: 490c ldr r1, [pc, #48] @ (80017e8 <__NVIC_SetPriority+0x4c>) 80017b6: f997 3007 ldrsb.w r3, [r7, #7] 80017ba: 0112 lsls r2, r2, #4 80017bc: b2d2 uxtb r2, r2 80017be: 440b add r3, r1 80017c0: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 80017c4: e00a b.n 80017dc <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80017c6: 683b ldr r3, [r7, #0] 80017c8: b2da uxtb r2, r3 80017ca: 4908 ldr r1, [pc, #32] @ (80017ec <__NVIC_SetPriority+0x50>) 80017cc: 79fb ldrb r3, [r7, #7] 80017ce: f003 030f and.w r3, r3, #15 80017d2: 3b04 subs r3, #4 80017d4: 0112 lsls r2, r2, #4 80017d6: b2d2 uxtb r2, r2 80017d8: 440b add r3, r1 80017da: 761a strb r2, [r3, #24] } 80017dc: bf00 nop 80017de: 370c adds r7, #12 80017e0: 46bd mov sp, r7 80017e2: f85d 7b04 ldr.w r7, [sp], #4 80017e6: 4770 bx lr 80017e8: e000e100 .word 0xe000e100 80017ec: e000ed00 .word 0xe000ed00 080017f0 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80017f0: b480 push {r7} 80017f2: b089 sub sp, #36 @ 0x24 80017f4: af00 add r7, sp, #0 80017f6: 60f8 str r0, [r7, #12] 80017f8: 60b9 str r1, [r7, #8] 80017fa: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80017fc: 68fb ldr r3, [r7, #12] 80017fe: f003 0307 and.w r3, r3, #7 8001802: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 8001804: 69fb ldr r3, [r7, #28] 8001806: f1c3 0307 rsb r3, r3, #7 800180a: 2b04 cmp r3, #4 800180c: bf28 it cs 800180e: 2304 movcs r3, #4 8001810: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 8001812: 69fb ldr r3, [r7, #28] 8001814: 3304 adds r3, #4 8001816: 2b06 cmp r3, #6 8001818: d902 bls.n 8001820 800181a: 69fb ldr r3, [r7, #28] 800181c: 3b03 subs r3, #3 800181e: e000 b.n 8001822 8001820: 2300 movs r3, #0 8001822: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001824: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8001828: 69bb ldr r3, [r7, #24] 800182a: fa02 f303 lsl.w r3, r2, r3 800182e: 43da mvns r2, r3 8001830: 68bb ldr r3, [r7, #8] 8001832: 401a ands r2, r3 8001834: 697b ldr r3, [r7, #20] 8001836: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 8001838: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 800183c: 697b ldr r3, [r7, #20] 800183e: fa01 f303 lsl.w r3, r1, r3 8001842: 43d9 mvns r1, r3 8001844: 687b ldr r3, [r7, #4] 8001846: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001848: 4313 orrs r3, r2 ); } 800184a: 4618 mov r0, r3 800184c: 3724 adds r7, #36 @ 0x24 800184e: 46bd mov sp, r7 8001850: f85d 7b04 ldr.w r7, [sp], #4 8001854: 4770 bx lr 08001856 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001856: b580 push {r7, lr} 8001858: b082 sub sp, #8 800185a: af00 add r7, sp, #0 800185c: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800185e: 6878 ldr r0, [r7, #4] 8001860: f7ff ff4c bl 80016fc <__NVIC_SetPriorityGrouping> } 8001864: bf00 nop 8001866: 3708 adds r7, #8 8001868: 46bd mov sp, r7 800186a: bd80 pop {r7, pc} 0800186c : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 800186c: b580 push {r7, lr} 800186e: b086 sub sp, #24 8001870: af00 add r7, sp, #0 8001872: 4603 mov r3, r0 8001874: 60b9 str r1, [r7, #8] 8001876: 607a str r2, [r7, #4] 8001878: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 800187a: 2300 movs r3, #0 800187c: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800187e: f7ff ff61 bl 8001744 <__NVIC_GetPriorityGrouping> 8001882: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001884: 687a ldr r2, [r7, #4] 8001886: 68b9 ldr r1, [r7, #8] 8001888: 6978 ldr r0, [r7, #20] 800188a: f7ff ffb1 bl 80017f0 800188e: 4602 mov r2, r0 8001890: f997 300f ldrsb.w r3, [r7, #15] 8001894: 4611 mov r1, r2 8001896: 4618 mov r0, r3 8001898: f7ff ff80 bl 800179c <__NVIC_SetPriority> } 800189c: bf00 nop 800189e: 3718 adds r7, #24 80018a0: 46bd mov sp, r7 80018a2: bd80 pop {r7, pc} 080018a4 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80018a4: b580 push {r7, lr} 80018a6: b082 sub sp, #8 80018a8: af00 add r7, sp, #0 80018aa: 4603 mov r3, r0 80018ac: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80018ae: f997 3007 ldrsb.w r3, [r7, #7] 80018b2: 4618 mov r0, r3 80018b4: f7ff ff54 bl 8001760 <__NVIC_EnableIRQ> } 80018b8: bf00 nop 80018ba: 3708 adds r7, #8 80018bc: 46bd mov sp, r7 80018be: bd80 pop {r7, pc} 080018c0 : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 80018c0: b580 push {r7, lr} 80018c2: b082 sub sp, #8 80018c4: af00 add r7, sp, #0 80018c6: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 80018c8: 687b ldr r3, [r7, #4] 80018ca: 2b00 cmp r3, #0 80018cc: d101 bne.n 80018d2 { return HAL_ERROR; 80018ce: 2301 movs r3, #1 80018d0: e00e b.n 80018f0 } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 80018d2: 687b ldr r3, [r7, #4] 80018d4: 795b ldrb r3, [r3, #5] 80018d6: b2db uxtb r3, r3 80018d8: 2b00 cmp r3, #0 80018da: d105 bne.n 80018e8 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 80018dc: 687b ldr r3, [r7, #4] 80018de: 2200 movs r2, #0 80018e0: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 80018e2: 6878 ldr r0, [r7, #4] 80018e4: f7ff fa9a bl 8000e1c } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 80018e8: 687b ldr r3, [r7, #4] 80018ea: 2201 movs r2, #1 80018ec: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 80018ee: 2300 movs r3, #0 } 80018f0: 4618 mov r0, r3 80018f2: 3708 adds r7, #8 80018f4: 46bd mov sp, r7 80018f6: bd80 pop {r7, pc} 080018f8 : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) { 80018f8: b580 push {r7, lr} 80018fa: b082 sub sp, #8 80018fc: af00 add r7, sp, #0 80018fe: 6078 str r0, [r7, #4] /* Check the DMA2D peripheral state */ if (hdma2d == NULL) 8001900: 687b ldr r3, [r7, #4] 8001902: 2b00 cmp r3, #0 8001904: d101 bne.n 800190a { return HAL_ERROR; 8001906: 2301 movs r3, #1 8001908: e03b b.n 8001982 /* Init the low level hardware */ hdma2d->MspInitCallback(hdma2d); } #else if (hdma2d->State == HAL_DMA2D_STATE_RESET) 800190a: 687b ldr r3, [r7, #4] 800190c: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 8001910: b2db uxtb r3, r3 8001912: 2b00 cmp r3, #0 8001914: d106 bne.n 8001924 { /* Allocate lock resource and initialize it */ hdma2d->Lock = HAL_UNLOCKED; 8001916: 687b ldr r3, [r7, #4] 8001918: 2200 movs r2, #0 800191a: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Init the low level hardware */ HAL_DMA2D_MspInit(hdma2d); 800191e: 6878 ldr r0, [r7, #4] 8001920: f7ff fa9e bl 8000e60 } #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; 8001924: 687b ldr r3, [r7, #4] 8001926: 2202 movs r2, #2 8001928: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* DMA2D CR register configuration -------------------------------------------*/ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); 800192c: 687b ldr r3, [r7, #4] 800192e: 681b ldr r3, [r3, #0] 8001930: 681b ldr r3, [r3, #0] 8001932: f423 3140 bic.w r1, r3, #196608 @ 0x30000 8001936: 687b ldr r3, [r7, #4] 8001938: 685a ldr r2, [r3, #4] 800193a: 687b ldr r3, [r7, #4] 800193c: 681b ldr r3, [r3, #0] 800193e: 430a orrs r2, r1 8001940: 601a str r2, [r3, #0] /* DMA2D OPFCCR register configuration ---------------------------------------*/ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); 8001942: 687b ldr r3, [r7, #4] 8001944: 681b ldr r3, [r3, #0] 8001946: 6b5b ldr r3, [r3, #52] @ 0x34 8001948: f023 0107 bic.w r1, r3, #7 800194c: 687b ldr r3, [r7, #4] 800194e: 689a ldr r2, [r3, #8] 8001950: 687b ldr r3, [r7, #4] 8001952: 681b ldr r3, [r3, #0] 8001954: 430a orrs r2, r1 8001956: 635a str r2, [r3, #52] @ 0x34 /* DMA2D OOR register configuration ------------------------------------------*/ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); 8001958: 687b ldr r3, [r7, #4] 800195a: 681b ldr r3, [r3, #0] 800195c: 6c1b ldr r3, [r3, #64] @ 0x40 800195e: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 8001962: f023 033f bic.w r3, r3, #63 @ 0x3f 8001966: 687a ldr r2, [r7, #4] 8001968: 68d1 ldr r1, [r2, #12] 800196a: 687a ldr r2, [r7, #4] 800196c: 6812 ldr r2, [r2, #0] 800196e: 430b orrs r3, r1 8001970: 6413 str r3, [r2, #64] @ 0x40 /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; 8001972: 687b ldr r3, [r7, #4] 8001974: 2200 movs r2, #0 8001976: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; 8001978: 687b ldr r3, [r7, #4] 800197a: 2201 movs r2, #1 800197c: f883 2039 strb.w r2, [r3, #57] @ 0x39 return HAL_OK; 8001980: 2300 movs r3, #0 } 8001982: 4618 mov r0, r3 8001984: 3708 adds r7, #8 8001986: 46bd mov sp, r7 8001988: bd80 pop {r7, pc} 0800198a : * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) { 800198a: b580 push {r7, lr} 800198c: b084 sub sp, #16 800198e: af00 add r7, sp, #0 8001990: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); 8001992: 687b ldr r3, [r7, #4] 8001994: 681b ldr r3, [r3, #0] 8001996: 685b ldr r3, [r3, #4] 8001998: 60fb str r3, [r7, #12] uint32_t crflags = READ_REG(hdma2d->Instance->CR); 800199a: 687b ldr r3, [r7, #4] 800199c: 681b ldr r3, [r3, #0] 800199e: 681b ldr r3, [r3, #0] 80019a0: 60bb str r3, [r7, #8] /* Transfer Error Interrupt management ***************************************/ if ((isrflags & DMA2D_FLAG_TE) != 0U) 80019a2: 68fb ldr r3, [r7, #12] 80019a4: f003 0301 and.w r3, r3, #1 80019a8: 2b00 cmp r3, #0 80019aa: d026 beq.n 80019fa { if ((crflags & DMA2D_IT_TE) != 0U) 80019ac: 68bb ldr r3, [r7, #8] 80019ae: f403 7380 and.w r3, r3, #256 @ 0x100 80019b2: 2b00 cmp r3, #0 80019b4: d021 beq.n 80019fa { /* Disable the transfer Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); 80019b6: 687b ldr r3, [r7, #4] 80019b8: 681b ldr r3, [r3, #0] 80019ba: 681a ldr r2, [r3, #0] 80019bc: 687b ldr r3, [r7, #4] 80019be: 681b ldr r3, [r3, #0] 80019c0: f422 7280 bic.w r2, r2, #256 @ 0x100 80019c4: 601a str r2, [r3, #0] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; 80019c6: 687b ldr r3, [r7, #4] 80019c8: 6bdb ldr r3, [r3, #60] @ 0x3c 80019ca: f043 0201 orr.w r2, r3, #1 80019ce: 687b ldr r3, [r7, #4] 80019d0: 63da str r2, [r3, #60] @ 0x3c /* Clear the transfer error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); 80019d2: 687b ldr r3, [r7, #4] 80019d4: 681b ldr r3, [r3, #0] 80019d6: 2201 movs r2, #1 80019d8: 609a str r2, [r3, #8] /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 80019da: 687b ldr r3, [r7, #4] 80019dc: 2204 movs r2, #4 80019de: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 80019e2: 687b ldr r3, [r7, #4] 80019e4: 2200 movs r2, #0 80019e6: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 80019ea: 687b ldr r3, [r7, #4] 80019ec: 695b ldr r3, [r3, #20] 80019ee: 2b00 cmp r3, #0 80019f0: d003 beq.n 80019fa { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 80019f2: 687b ldr r3, [r7, #4] 80019f4: 695b ldr r3, [r3, #20] 80019f6: 6878 ldr r0, [r7, #4] 80019f8: 4798 blx r3 } } } /* Configuration Error Interrupt management **********************************/ if ((isrflags & DMA2D_FLAG_CE) != 0U) 80019fa: 68fb ldr r3, [r7, #12] 80019fc: f003 0320 and.w r3, r3, #32 8001a00: 2b00 cmp r3, #0 8001a02: d026 beq.n 8001a52 { if ((crflags & DMA2D_IT_CE) != 0U) 8001a04: 68bb ldr r3, [r7, #8] 8001a06: f403 5300 and.w r3, r3, #8192 @ 0x2000 8001a0a: 2b00 cmp r3, #0 8001a0c: d021 beq.n 8001a52 { /* Disable the Configuration Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); 8001a0e: 687b ldr r3, [r7, #4] 8001a10: 681b ldr r3, [r3, #0] 8001a12: 681a ldr r2, [r3, #0] 8001a14: 687b ldr r3, [r7, #4] 8001a16: 681b ldr r3, [r3, #0] 8001a18: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8001a1c: 601a str r2, [r3, #0] /* Clear the Configuration error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); 8001a1e: 687b ldr r3, [r7, #4] 8001a20: 681b ldr r3, [r3, #0] 8001a22: 2220 movs r2, #32 8001a24: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; 8001a26: 687b ldr r3, [r7, #4] 8001a28: 6bdb ldr r3, [r3, #60] @ 0x3c 8001a2a: f043 0202 orr.w r2, r3, #2 8001a2e: 687b ldr r3, [r7, #4] 8001a30: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 8001a32: 687b ldr r3, [r7, #4] 8001a34: 2204 movs r2, #4 8001a36: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001a3a: 687b ldr r3, [r7, #4] 8001a3c: 2200 movs r2, #0 8001a3e: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 8001a42: 687b ldr r3, [r7, #4] 8001a44: 695b ldr r3, [r3, #20] 8001a46: 2b00 cmp r3, #0 8001a48: d003 beq.n 8001a52 { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 8001a4a: 687b ldr r3, [r7, #4] 8001a4c: 695b ldr r3, [r3, #20] 8001a4e: 6878 ldr r0, [r7, #4] 8001a50: 4798 blx r3 } } } /* CLUT access Error Interrupt management ***********************************/ if ((isrflags & DMA2D_FLAG_CAE) != 0U) 8001a52: 68fb ldr r3, [r7, #12] 8001a54: f003 0308 and.w r3, r3, #8 8001a58: 2b00 cmp r3, #0 8001a5a: d026 beq.n 8001aaa { if ((crflags & DMA2D_IT_CAE) != 0U) 8001a5c: 68bb ldr r3, [r7, #8] 8001a5e: f403 6300 and.w r3, r3, #2048 @ 0x800 8001a62: 2b00 cmp r3, #0 8001a64: d021 beq.n 8001aaa { /* Disable the CLUT access error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); 8001a66: 687b ldr r3, [r7, #4] 8001a68: 681b ldr r3, [r3, #0] 8001a6a: 681a ldr r2, [r3, #0] 8001a6c: 687b ldr r3, [r7, #4] 8001a6e: 681b ldr r3, [r3, #0] 8001a70: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001a74: 601a str r2, [r3, #0] /* Clear the CLUT access error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); 8001a76: 687b ldr r3, [r7, #4] 8001a78: 681b ldr r3, [r3, #0] 8001a7a: 2208 movs r2, #8 8001a7c: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; 8001a7e: 687b ldr r3, [r7, #4] 8001a80: 6bdb ldr r3, [r3, #60] @ 0x3c 8001a82: f043 0204 orr.w r2, r3, #4 8001a86: 687b ldr r3, [r7, #4] 8001a88: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 8001a8a: 687b ldr r3, [r7, #4] 8001a8c: 2204 movs r2, #4 8001a8e: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001a92: 687b ldr r3, [r7, #4] 8001a94: 2200 movs r2, #0 8001a96: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 8001a9a: 687b ldr r3, [r7, #4] 8001a9c: 695b ldr r3, [r3, #20] 8001a9e: 2b00 cmp r3, #0 8001aa0: d003 beq.n 8001aaa { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 8001aa2: 687b ldr r3, [r7, #4] 8001aa4: 695b ldr r3, [r3, #20] 8001aa6: 6878 ldr r0, [r7, #4] 8001aa8: 4798 blx r3 } } } /* Transfer watermark Interrupt management **********************************/ if ((isrflags & DMA2D_FLAG_TW) != 0U) 8001aaa: 68fb ldr r3, [r7, #12] 8001aac: f003 0304 and.w r3, r3, #4 8001ab0: 2b00 cmp r3, #0 8001ab2: d013 beq.n 8001adc { if ((crflags & DMA2D_IT_TW) != 0U) 8001ab4: 68bb ldr r3, [r7, #8] 8001ab6: f403 6380 and.w r3, r3, #1024 @ 0x400 8001aba: 2b00 cmp r3, #0 8001abc: d00e beq.n 8001adc { /* Disable the transfer watermark interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); 8001abe: 687b ldr r3, [r7, #4] 8001ac0: 681b ldr r3, [r3, #0] 8001ac2: 681a ldr r2, [r3, #0] 8001ac4: 687b ldr r3, [r7, #4] 8001ac6: 681b ldr r3, [r3, #0] 8001ac8: f422 6280 bic.w r2, r2, #1024 @ 0x400 8001acc: 601a str r2, [r3, #0] /* Clear the transfer watermark flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); 8001ace: 687b ldr r3, [r7, #4] 8001ad0: 681b ldr r3, [r3, #0] 8001ad2: 2204 movs r2, #4 8001ad4: 609a str r2, [r3, #8] /* Transfer watermark Callback */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) hdma2d->LineEventCallback(hdma2d); #else HAL_DMA2D_LineEventCallback(hdma2d); 8001ad6: 6878 ldr r0, [r7, #4] 8001ad8: f000 f853 bl 8001b82 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } } /* Transfer Complete Interrupt management ************************************/ if ((isrflags & DMA2D_FLAG_TC) != 0U) 8001adc: 68fb ldr r3, [r7, #12] 8001ade: f003 0302 and.w r3, r3, #2 8001ae2: 2b00 cmp r3, #0 8001ae4: d024 beq.n 8001b30 { if ((crflags & DMA2D_IT_TC) != 0U) 8001ae6: 68bb ldr r3, [r7, #8] 8001ae8: f403 7300 and.w r3, r3, #512 @ 0x200 8001aec: 2b00 cmp r3, #0 8001aee: d01f beq.n 8001b30 { /* Disable the transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); 8001af0: 687b ldr r3, [r7, #4] 8001af2: 681b ldr r3, [r3, #0] 8001af4: 681a ldr r2, [r3, #0] 8001af6: 687b ldr r3, [r7, #4] 8001af8: 681b ldr r3, [r3, #0] 8001afa: f422 7200 bic.w r2, r2, #512 @ 0x200 8001afe: 601a str r2, [r3, #0] /* Clear the transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); 8001b00: 687b ldr r3, [r7, #4] 8001b02: 681b ldr r3, [r3, #0] 8001b04: 2202 movs r2, #2 8001b06: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; 8001b08: 687b ldr r3, [r7, #4] 8001b0a: 6bda ldr r2, [r3, #60] @ 0x3c 8001b0c: 687b ldr r3, [r7, #4] 8001b0e: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; 8001b10: 687b ldr r3, [r7, #4] 8001b12: 2201 movs r2, #1 8001b14: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001b18: 687b ldr r3, [r7, #4] 8001b1a: 2200 movs r2, #0 8001b1c: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferCpltCallback != NULL) 8001b20: 687b ldr r3, [r7, #4] 8001b22: 691b ldr r3, [r3, #16] 8001b24: 2b00 cmp r3, #0 8001b26: d003 beq.n 8001b30 { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); 8001b28: 687b ldr r3, [r7, #4] 8001b2a: 691b ldr r3, [r3, #16] 8001b2c: 6878 ldr r0, [r7, #4] 8001b2e: 4798 blx r3 } } } /* CLUT Transfer Complete Interrupt management ******************************/ if ((isrflags & DMA2D_FLAG_CTC) != 0U) 8001b30: 68fb ldr r3, [r7, #12] 8001b32: f003 0310 and.w r3, r3, #16 8001b36: 2b00 cmp r3, #0 8001b38: d01f beq.n 8001b7a { if ((crflags & DMA2D_IT_CTC) != 0U) 8001b3a: 68bb ldr r3, [r7, #8] 8001b3c: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001b40: 2b00 cmp r3, #0 8001b42: d01a beq.n 8001b7a { /* Disable the CLUT transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); 8001b44: 687b ldr r3, [r7, #4] 8001b46: 681b ldr r3, [r3, #0] 8001b48: 681a ldr r2, [r3, #0] 8001b4a: 687b ldr r3, [r7, #4] 8001b4c: 681b ldr r3, [r3, #0] 8001b4e: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8001b52: 601a str r2, [r3, #0] /* Clear the CLUT transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); 8001b54: 687b ldr r3, [r7, #4] 8001b56: 681b ldr r3, [r3, #0] 8001b58: 2210 movs r2, #16 8001b5a: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; 8001b5c: 687b ldr r3, [r7, #4] 8001b5e: 6bda ldr r2, [r3, #60] @ 0x3c 8001b60: 687b ldr r3, [r7, #4] 8001b62: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; 8001b64: 687b ldr r3, [r7, #4] 8001b66: 2201 movs r2, #1 8001b68: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001b6c: 687b ldr r3, [r7, #4] 8001b6e: 2200 movs r2, #0 8001b70: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* CLUT Transfer complete Callback */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) hdma2d->CLUTLoadingCpltCallback(hdma2d); #else HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); 8001b74: 6878 ldr r0, [r7, #4] 8001b76: f000 f80e bl 8001b96 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } } } 8001b7a: bf00 nop 8001b7c: 3710 adds r7, #16 8001b7e: 46bd mov sp, r7 8001b80: bd80 pop {r7, pc} 08001b82 : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) { 8001b82: b480 push {r7} 8001b84: b083 sub sp, #12 8001b86: af00 add r7, sp, #0 8001b88: 6078 str r0, [r7, #4] UNUSED(hdma2d); /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_LineEventCallback can be implemented in the user file. */ } 8001b8a: bf00 nop 8001b8c: 370c adds r7, #12 8001b8e: 46bd mov sp, r7 8001b90: f85d 7b04 ldr.w r7, [sp], #4 8001b94: 4770 bx lr 08001b96 : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) { 8001b96: b480 push {r7} 8001b98: b083 sub sp, #12 8001b9a: af00 add r7, sp, #0 8001b9c: 6078 str r0, [r7, #4] UNUSED(hdma2d); /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. */ } 8001b9e: bf00 nop 8001ba0: 370c adds r7, #12 8001ba2: 46bd mov sp, r7 8001ba4: f85d 7b04 ldr.w r7, [sp], #4 8001ba8: 4770 bx lr ... 08001bac : * This parameter can be one of the following values: * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { 8001bac: b480 push {r7} 8001bae: b087 sub sp, #28 8001bb0: af00 add r7, sp, #0 8001bb2: 6078 str r0, [r7, #4] 8001bb4: 6039 str r1, [r7, #0] uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); if (hdma2d->Init.Mode != DMA2D_R2M) 8001bb6: 687b ldr r3, [r7, #4] 8001bb8: 685b ldr r3, [r3, #4] 8001bba: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } } /* Process locked */ __HAL_LOCK(hdma2d); 8001bbe: 687b ldr r3, [r7, #4] 8001bc0: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8001bc4: 2b01 cmp r3, #1 8001bc6: d101 bne.n 8001bcc 8001bc8: 2302 movs r3, #2 8001bca: e079 b.n 8001cc0 8001bcc: 687b ldr r3, [r7, #4] 8001bce: 2201 movs r2, #1 8001bd0: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; 8001bd4: 687b ldr r3, [r7, #4] 8001bd6: 2202 movs r2, #2 8001bd8: f883 2039 strb.w r2, [r3, #57] @ 0x39 pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; 8001bdc: 683b ldr r3, [r7, #0] 8001bde: 011b lsls r3, r3, #4 8001be0: 3318 adds r3, #24 8001be2: 687a ldr r2, [r7, #4] 8001be4: 4413 add r3, r2 8001be6: 613b str r3, [r7, #16] /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); 8001be8: 693b ldr r3, [r7, #16] 8001bea: 685a ldr r2, [r3, #4] 8001bec: 693b ldr r3, [r7, #16] 8001bee: 689b ldr r3, [r3, #8] 8001bf0: 041b lsls r3, r3, #16 8001bf2: 4313 orrs r3, r2 8001bf4: 617b str r3, [r7, #20] regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; 8001bf6: 4b35 ldr r3, [pc, #212] @ (8001ccc ) 8001bf8: 60fb str r3, [r7, #12] if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001bfa: 693b ldr r3, [r7, #16] 8001bfc: 685b ldr r3, [r3, #4] 8001bfe: 2b0a cmp r3, #10 8001c00: d003 beq.n 8001c0a 8001c02: 693b ldr r3, [r7, #16] 8001c04: 685b ldr r3, [r3, #4] 8001c06: 2b09 cmp r3, #9 8001c08: d107 bne.n 8001c1a { regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); 8001c0a: 693b ldr r3, [r7, #16] 8001c0c: 68db ldr r3, [r3, #12] 8001c0e: f003 437f and.w r3, r3, #4278190080 @ 0xff000000 8001c12: 697a ldr r2, [r7, #20] 8001c14: 4313 orrs r3, r2 8001c16: 617b str r3, [r7, #20] 8001c18: e005 b.n 8001c26 } else { regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); 8001c1a: 693b ldr r3, [r7, #16] 8001c1c: 68db ldr r3, [r3, #12] 8001c1e: 061b lsls r3, r3, #24 8001c20: 697a ldr r2, [r7, #20] 8001c22: 4313 orrs r3, r2 8001c24: 617b str r3, [r7, #20] } /* Configure the background DMA2D layer */ if (LayerIdx == DMA2D_BACKGROUND_LAYER) 8001c26: 683b ldr r3, [r7, #0] 8001c28: 2b00 cmp r3, #0 8001c2a: d120 bne.n 8001c6e { /* Write DMA2D BGPFCCR register */ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); 8001c2c: 687b ldr r3, [r7, #4] 8001c2e: 681b ldr r3, [r3, #0] 8001c30: 6a5a ldr r2, [r3, #36] @ 0x24 8001c32: 68fb ldr r3, [r7, #12] 8001c34: 43db mvns r3, r3 8001c36: ea02 0103 and.w r1, r2, r3 8001c3a: 687b ldr r3, [r7, #4] 8001c3c: 681b ldr r3, [r3, #0] 8001c3e: 697a ldr r2, [r7, #20] 8001c40: 430a orrs r2, r1 8001c42: 625a str r2, [r3, #36] @ 0x24 /* DMA2D BGOR register configuration -------------------------------------*/ WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); 8001c44: 687b ldr r3, [r7, #4] 8001c46: 681b ldr r3, [r3, #0] 8001c48: 693a ldr r2, [r7, #16] 8001c4a: 6812 ldr r2, [r2, #0] 8001c4c: 619a str r2, [r3, #24] /* DMA2D BGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001c4e: 693b ldr r3, [r7, #16] 8001c50: 685b ldr r3, [r3, #4] 8001c52: 2b0a cmp r3, #10 8001c54: d003 beq.n 8001c5e 8001c56: 693b ldr r3, [r7, #16] 8001c58: 685b ldr r3, [r3, #4] 8001c5a: 2b09 cmp r3, #9 8001c5c: d127 bne.n 8001cae { WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ 8001c5e: 693b ldr r3, [r7, #16] 8001c60: 68da ldr r2, [r3, #12] 8001c62: 687b ldr r3, [r7, #4] 8001c64: 681b ldr r3, [r3, #0] 8001c66: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000 8001c6a: 629a str r2, [r3, #40] @ 0x28 8001c6c: e01f b.n 8001cae else { /* Write DMA2D FGPFCCR register */ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); 8001c6e: 687b ldr r3, [r7, #4] 8001c70: 681b ldr r3, [r3, #0] 8001c72: 69da ldr r2, [r3, #28] 8001c74: 68fb ldr r3, [r7, #12] 8001c76: 43db mvns r3, r3 8001c78: ea02 0103 and.w r1, r2, r3 8001c7c: 687b ldr r3, [r7, #4] 8001c7e: 681b ldr r3, [r3, #0] 8001c80: 697a ldr r2, [r7, #20] 8001c82: 430a orrs r2, r1 8001c84: 61da str r2, [r3, #28] /* DMA2D FGOR register configuration -------------------------------------*/ WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); 8001c86: 687b ldr r3, [r7, #4] 8001c88: 681b ldr r3, [r3, #0] 8001c8a: 693a ldr r2, [r7, #16] 8001c8c: 6812 ldr r2, [r2, #0] 8001c8e: 611a str r2, [r3, #16] /* DMA2D FGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001c90: 693b ldr r3, [r7, #16] 8001c92: 685b ldr r3, [r3, #4] 8001c94: 2b0a cmp r3, #10 8001c96: d003 beq.n 8001ca0 8001c98: 693b ldr r3, [r7, #16] 8001c9a: 685b ldr r3, [r3, #4] 8001c9c: 2b09 cmp r3, #9 8001c9e: d106 bne.n 8001cae { WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ 8001ca0: 693b ldr r3, [r7, #16] 8001ca2: 68da ldr r2, [r3, #12] 8001ca4: 687b ldr r3, [r7, #4] 8001ca6: 681b ldr r3, [r3, #0] 8001ca8: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000 8001cac: 621a str r2, [r3, #32] DMA2D_FGCOLR_RED)); } } /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; 8001cae: 687b ldr r3, [r7, #4] 8001cb0: 2201 movs r2, #1 8001cb2: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process unlocked */ __HAL_UNLOCK(hdma2d); 8001cb6: 687b ldr r3, [r7, #4] 8001cb8: 2200 movs r2, #0 8001cba: f883 2038 strb.w r2, [r3, #56] @ 0x38 return HAL_OK; 8001cbe: 2300 movs r3, #0 } 8001cc0: 4618 mov r0, r3 8001cc2: 371c adds r7, #28 8001cc4: 46bd mov sp, r7 8001cc6: f85d 7b04 ldr.w r7, [sp], #4 8001cca: 4770 bx lr 8001ccc: ff03000f .word 0xff03000f 08001cd0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001cd0: b480 push {r7} 8001cd2: b089 sub sp, #36 @ 0x24 8001cd4: af00 add r7, sp, #0 8001cd6: 6078 str r0, [r7, #4] 8001cd8: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8001cda: 2300 movs r3, #0 8001cdc: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8001cde: 2300 movs r3, #0 8001ce0: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8001ce2: 2300 movs r3, #0 8001ce4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8001ce6: 2300 movs r3, #0 8001ce8: 61fb str r3, [r7, #28] 8001cea: e177 b.n 8001fdc { /* Get the IO position */ ioposition = 0x01U << position; 8001cec: 2201 movs r2, #1 8001cee: 69fb ldr r3, [r7, #28] 8001cf0: fa02 f303 lsl.w r3, r2, r3 8001cf4: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001cf6: 683b ldr r3, [r7, #0] 8001cf8: 681b ldr r3, [r3, #0] 8001cfa: 697a ldr r2, [r7, #20] 8001cfc: 4013 ands r3, r2 8001cfe: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8001d00: 693a ldr r2, [r7, #16] 8001d02: 697b ldr r3, [r7, #20] 8001d04: 429a cmp r2, r3 8001d06: f040 8166 bne.w 8001fd6 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001d0a: 683b ldr r3, [r7, #0] 8001d0c: 685b ldr r3, [r3, #4] 8001d0e: f003 0303 and.w r3, r3, #3 8001d12: 2b01 cmp r3, #1 8001d14: d005 beq.n 8001d22 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001d16: 683b ldr r3, [r7, #0] 8001d18: 685b ldr r3, [r3, #4] 8001d1a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001d1e: 2b02 cmp r3, #2 8001d20: d130 bne.n 8001d84 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001d22: 687b ldr r3, [r7, #4] 8001d24: 689b ldr r3, [r3, #8] 8001d26: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001d28: 69fb ldr r3, [r7, #28] 8001d2a: 005b lsls r3, r3, #1 8001d2c: 2203 movs r2, #3 8001d2e: fa02 f303 lsl.w r3, r2, r3 8001d32: 43db mvns r3, r3 8001d34: 69ba ldr r2, [r7, #24] 8001d36: 4013 ands r3, r2 8001d38: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001d3a: 683b ldr r3, [r7, #0] 8001d3c: 68da ldr r2, [r3, #12] 8001d3e: 69fb ldr r3, [r7, #28] 8001d40: 005b lsls r3, r3, #1 8001d42: fa02 f303 lsl.w r3, r2, r3 8001d46: 69ba ldr r2, [r7, #24] 8001d48: 4313 orrs r3, r2 8001d4a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001d4c: 687b ldr r3, [r7, #4] 8001d4e: 69ba ldr r2, [r7, #24] 8001d50: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001d52: 687b ldr r3, [r7, #4] 8001d54: 685b ldr r3, [r3, #4] 8001d56: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001d58: 2201 movs r2, #1 8001d5a: 69fb ldr r3, [r7, #28] 8001d5c: fa02 f303 lsl.w r3, r2, r3 8001d60: 43db mvns r3, r3 8001d62: 69ba ldr r2, [r7, #24] 8001d64: 4013 ands r3, r2 8001d66: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001d68: 683b ldr r3, [r7, #0] 8001d6a: 685b ldr r3, [r3, #4] 8001d6c: 091b lsrs r3, r3, #4 8001d6e: f003 0201 and.w r2, r3, #1 8001d72: 69fb ldr r3, [r7, #28] 8001d74: fa02 f303 lsl.w r3, r2, r3 8001d78: 69ba ldr r2, [r7, #24] 8001d7a: 4313 orrs r3, r2 8001d7c: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001d7e: 687b ldr r3, [r7, #4] 8001d80: 69ba ldr r2, [r7, #24] 8001d82: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001d84: 683b ldr r3, [r7, #0] 8001d86: 685b ldr r3, [r3, #4] 8001d88: f003 0303 and.w r3, r3, #3 8001d8c: 2b03 cmp r3, #3 8001d8e: d017 beq.n 8001dc0 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001d90: 687b ldr r3, [r7, #4] 8001d92: 68db ldr r3, [r3, #12] 8001d94: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001d96: 69fb ldr r3, [r7, #28] 8001d98: 005b lsls r3, r3, #1 8001d9a: 2203 movs r2, #3 8001d9c: fa02 f303 lsl.w r3, r2, r3 8001da0: 43db mvns r3, r3 8001da2: 69ba ldr r2, [r7, #24] 8001da4: 4013 ands r3, r2 8001da6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001da8: 683b ldr r3, [r7, #0] 8001daa: 689a ldr r2, [r3, #8] 8001dac: 69fb ldr r3, [r7, #28] 8001dae: 005b lsls r3, r3, #1 8001db0: fa02 f303 lsl.w r3, r2, r3 8001db4: 69ba ldr r2, [r7, #24] 8001db6: 4313 orrs r3, r2 8001db8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001dba: 687b ldr r3, [r7, #4] 8001dbc: 69ba ldr r2, [r7, #24] 8001dbe: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001dc0: 683b ldr r3, [r7, #0] 8001dc2: 685b ldr r3, [r3, #4] 8001dc4: f003 0303 and.w r3, r3, #3 8001dc8: 2b02 cmp r3, #2 8001dca: d123 bne.n 8001e14 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001dcc: 69fb ldr r3, [r7, #28] 8001dce: 08da lsrs r2, r3, #3 8001dd0: 687b ldr r3, [r7, #4] 8001dd2: 3208 adds r2, #8 8001dd4: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001dd8: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8001dda: 69fb ldr r3, [r7, #28] 8001ddc: f003 0307 and.w r3, r3, #7 8001de0: 009b lsls r3, r3, #2 8001de2: 220f movs r2, #15 8001de4: fa02 f303 lsl.w r3, r2, r3 8001de8: 43db mvns r3, r3 8001dea: 69ba ldr r2, [r7, #24] 8001dec: 4013 ands r3, r2 8001dee: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8001df0: 683b ldr r3, [r7, #0] 8001df2: 691a ldr r2, [r3, #16] 8001df4: 69fb ldr r3, [r7, #28] 8001df6: f003 0307 and.w r3, r3, #7 8001dfa: 009b lsls r3, r3, #2 8001dfc: fa02 f303 lsl.w r3, r2, r3 8001e00: 69ba ldr r2, [r7, #24] 8001e02: 4313 orrs r3, r2 8001e04: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001e06: 69fb ldr r3, [r7, #28] 8001e08: 08da lsrs r2, r3, #3 8001e0a: 687b ldr r3, [r7, #4] 8001e0c: 3208 adds r2, #8 8001e0e: 69b9 ldr r1, [r7, #24] 8001e10: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001e14: 687b ldr r3, [r7, #4] 8001e16: 681b ldr r3, [r3, #0] 8001e18: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8001e1a: 69fb ldr r3, [r7, #28] 8001e1c: 005b lsls r3, r3, #1 8001e1e: 2203 movs r2, #3 8001e20: fa02 f303 lsl.w r3, r2, r3 8001e24: 43db mvns r3, r3 8001e26: 69ba ldr r2, [r7, #24] 8001e28: 4013 ands r3, r2 8001e2a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001e2c: 683b ldr r3, [r7, #0] 8001e2e: 685b ldr r3, [r3, #4] 8001e30: f003 0203 and.w r2, r3, #3 8001e34: 69fb ldr r3, [r7, #28] 8001e36: 005b lsls r3, r3, #1 8001e38: fa02 f303 lsl.w r3, r2, r3 8001e3c: 69ba ldr r2, [r7, #24] 8001e3e: 4313 orrs r3, r2 8001e40: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001e42: 687b ldr r3, [r7, #4] 8001e44: 69ba ldr r2, [r7, #24] 8001e46: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001e48: 683b ldr r3, [r7, #0] 8001e4a: 685b ldr r3, [r3, #4] 8001e4c: f403 3340 and.w r3, r3, #196608 @ 0x30000 8001e50: 2b00 cmp r3, #0 8001e52: f000 80c0 beq.w 8001fd6 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001e56: 2300 movs r3, #0 8001e58: 60fb str r3, [r7, #12] 8001e5a: 4b66 ldr r3, [pc, #408] @ (8001ff4 ) 8001e5c: 6c5b ldr r3, [r3, #68] @ 0x44 8001e5e: 4a65 ldr r2, [pc, #404] @ (8001ff4 ) 8001e60: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001e64: 6453 str r3, [r2, #68] @ 0x44 8001e66: 4b63 ldr r3, [pc, #396] @ (8001ff4 ) 8001e68: 6c5b ldr r3, [r3, #68] @ 0x44 8001e6a: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001e6e: 60fb str r3, [r7, #12] 8001e70: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001e72: 4a61 ldr r2, [pc, #388] @ (8001ff8 ) 8001e74: 69fb ldr r3, [r7, #28] 8001e76: 089b lsrs r3, r3, #2 8001e78: 3302 adds r3, #2 8001e7a: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001e7e: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001e80: 69fb ldr r3, [r7, #28] 8001e82: f003 0303 and.w r3, r3, #3 8001e86: 009b lsls r3, r3, #2 8001e88: 220f movs r2, #15 8001e8a: fa02 f303 lsl.w r3, r2, r3 8001e8e: 43db mvns r3, r3 8001e90: 69ba ldr r2, [r7, #24] 8001e92: 4013 ands r3, r2 8001e94: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001e96: 687b ldr r3, [r7, #4] 8001e98: 4a58 ldr r2, [pc, #352] @ (8001ffc ) 8001e9a: 4293 cmp r3, r2 8001e9c: d037 beq.n 8001f0e 8001e9e: 687b ldr r3, [r7, #4] 8001ea0: 4a57 ldr r2, [pc, #348] @ (8002000 ) 8001ea2: 4293 cmp r3, r2 8001ea4: d031 beq.n 8001f0a 8001ea6: 687b ldr r3, [r7, #4] 8001ea8: 4a56 ldr r2, [pc, #344] @ (8002004 ) 8001eaa: 4293 cmp r3, r2 8001eac: d02b beq.n 8001f06 8001eae: 687b ldr r3, [r7, #4] 8001eb0: 4a55 ldr r2, [pc, #340] @ (8002008 ) 8001eb2: 4293 cmp r3, r2 8001eb4: d025 beq.n 8001f02 8001eb6: 687b ldr r3, [r7, #4] 8001eb8: 4a54 ldr r2, [pc, #336] @ (800200c ) 8001eba: 4293 cmp r3, r2 8001ebc: d01f beq.n 8001efe 8001ebe: 687b ldr r3, [r7, #4] 8001ec0: 4a53 ldr r2, [pc, #332] @ (8002010 ) 8001ec2: 4293 cmp r3, r2 8001ec4: d019 beq.n 8001efa 8001ec6: 687b ldr r3, [r7, #4] 8001ec8: 4a52 ldr r2, [pc, #328] @ (8002014 ) 8001eca: 4293 cmp r3, r2 8001ecc: d013 beq.n 8001ef6 8001ece: 687b ldr r3, [r7, #4] 8001ed0: 4a51 ldr r2, [pc, #324] @ (8002018 ) 8001ed2: 4293 cmp r3, r2 8001ed4: d00d beq.n 8001ef2 8001ed6: 687b ldr r3, [r7, #4] 8001ed8: 4a50 ldr r2, [pc, #320] @ (800201c ) 8001eda: 4293 cmp r3, r2 8001edc: d007 beq.n 8001eee 8001ede: 687b ldr r3, [r7, #4] 8001ee0: 4a4f ldr r2, [pc, #316] @ (8002020 ) 8001ee2: 4293 cmp r3, r2 8001ee4: d101 bne.n 8001eea 8001ee6: 2309 movs r3, #9 8001ee8: e012 b.n 8001f10 8001eea: 230a movs r3, #10 8001eec: e010 b.n 8001f10 8001eee: 2308 movs r3, #8 8001ef0: e00e b.n 8001f10 8001ef2: 2307 movs r3, #7 8001ef4: e00c b.n 8001f10 8001ef6: 2306 movs r3, #6 8001ef8: e00a b.n 8001f10 8001efa: 2305 movs r3, #5 8001efc: e008 b.n 8001f10 8001efe: 2304 movs r3, #4 8001f00: e006 b.n 8001f10 8001f02: 2303 movs r3, #3 8001f04: e004 b.n 8001f10 8001f06: 2302 movs r3, #2 8001f08: e002 b.n 8001f10 8001f0a: 2301 movs r3, #1 8001f0c: e000 b.n 8001f10 8001f0e: 2300 movs r3, #0 8001f10: 69fa ldr r2, [r7, #28] 8001f12: f002 0203 and.w r2, r2, #3 8001f16: 0092 lsls r2, r2, #2 8001f18: 4093 lsls r3, r2 8001f1a: 69ba ldr r2, [r7, #24] 8001f1c: 4313 orrs r3, r2 8001f1e: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001f20: 4935 ldr r1, [pc, #212] @ (8001ff8 ) 8001f22: 69fb ldr r3, [r7, #28] 8001f24: 089b lsrs r3, r3, #2 8001f26: 3302 adds r3, #2 8001f28: 69ba ldr r2, [r7, #24] 8001f2a: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8001f2e: 4b3d ldr r3, [pc, #244] @ (8002024 ) 8001f30: 689b ldr r3, [r3, #8] 8001f32: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f34: 693b ldr r3, [r7, #16] 8001f36: 43db mvns r3, r3 8001f38: 69ba ldr r2, [r7, #24] 8001f3a: 4013 ands r3, r2 8001f3c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001f3e: 683b ldr r3, [r7, #0] 8001f40: 685b ldr r3, [r3, #4] 8001f42: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001f46: 2b00 cmp r3, #0 8001f48: d003 beq.n 8001f52 { temp |= iocurrent; 8001f4a: 69ba ldr r2, [r7, #24] 8001f4c: 693b ldr r3, [r7, #16] 8001f4e: 4313 orrs r3, r2 8001f50: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8001f52: 4a34 ldr r2, [pc, #208] @ (8002024 ) 8001f54: 69bb ldr r3, [r7, #24] 8001f56: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8001f58: 4b32 ldr r3, [pc, #200] @ (8002024 ) 8001f5a: 68db ldr r3, [r3, #12] 8001f5c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f5e: 693b ldr r3, [r7, #16] 8001f60: 43db mvns r3, r3 8001f62: 69ba ldr r2, [r7, #24] 8001f64: 4013 ands r3, r2 8001f66: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001f68: 683b ldr r3, [r7, #0] 8001f6a: 685b ldr r3, [r3, #4] 8001f6c: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001f70: 2b00 cmp r3, #0 8001f72: d003 beq.n 8001f7c { temp |= iocurrent; 8001f74: 69ba ldr r2, [r7, #24] 8001f76: 693b ldr r3, [r7, #16] 8001f78: 4313 orrs r3, r2 8001f7a: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8001f7c: 4a29 ldr r2, [pc, #164] @ (8002024 ) 8001f7e: 69bb ldr r3, [r7, #24] 8001f80: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8001f82: 4b28 ldr r3, [pc, #160] @ (8002024 ) 8001f84: 685b ldr r3, [r3, #4] 8001f86: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f88: 693b ldr r3, [r7, #16] 8001f8a: 43db mvns r3, r3 8001f8c: 69ba ldr r2, [r7, #24] 8001f8e: 4013 ands r3, r2 8001f90: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001f92: 683b ldr r3, [r7, #0] 8001f94: 685b ldr r3, [r3, #4] 8001f96: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001f9a: 2b00 cmp r3, #0 8001f9c: d003 beq.n 8001fa6 { temp |= iocurrent; 8001f9e: 69ba ldr r2, [r7, #24] 8001fa0: 693b ldr r3, [r7, #16] 8001fa2: 4313 orrs r3, r2 8001fa4: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8001fa6: 4a1f ldr r2, [pc, #124] @ (8002024 ) 8001fa8: 69bb ldr r3, [r7, #24] 8001faa: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001fac: 4b1d ldr r3, [pc, #116] @ (8002024 ) 8001fae: 681b ldr r3, [r3, #0] 8001fb0: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001fb2: 693b ldr r3, [r7, #16] 8001fb4: 43db mvns r3, r3 8001fb6: 69ba ldr r2, [r7, #24] 8001fb8: 4013 ands r3, r2 8001fba: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001fbc: 683b ldr r3, [r7, #0] 8001fbe: 685b ldr r3, [r3, #4] 8001fc0: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001fc4: 2b00 cmp r3, #0 8001fc6: d003 beq.n 8001fd0 { temp |= iocurrent; 8001fc8: 69ba ldr r2, [r7, #24] 8001fca: 693b ldr r3, [r7, #16] 8001fcc: 4313 orrs r3, r2 8001fce: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8001fd0: 4a14 ldr r2, [pc, #80] @ (8002024 ) 8001fd2: 69bb ldr r3, [r7, #24] 8001fd4: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8001fd6: 69fb ldr r3, [r7, #28] 8001fd8: 3301 adds r3, #1 8001fda: 61fb str r3, [r7, #28] 8001fdc: 69fb ldr r3, [r7, #28] 8001fde: 2b0f cmp r3, #15 8001fe0: f67f ae84 bls.w 8001cec } } } } 8001fe4: bf00 nop 8001fe6: bf00 nop 8001fe8: 3724 adds r7, #36 @ 0x24 8001fea: 46bd mov sp, r7 8001fec: f85d 7b04 ldr.w r7, [sp], #4 8001ff0: 4770 bx lr 8001ff2: bf00 nop 8001ff4: 40023800 .word 0x40023800 8001ff8: 40013800 .word 0x40013800 8001ffc: 40020000 .word 0x40020000 8002000: 40020400 .word 0x40020400 8002004: 40020800 .word 0x40020800 8002008: 40020c00 .word 0x40020c00 800200c: 40021000 .word 0x40021000 8002010: 40021400 .word 0x40021400 8002014: 40021800 .word 0x40021800 8002018: 40021c00 .word 0x40021c00 800201c: 40022000 .word 0x40022000 8002020: 40022400 .word 0x40022400 8002024: 40013c00 .word 0x40013c00 08002028 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002028: b480 push {r7} 800202a: b083 sub sp, #12 800202c: af00 add r7, sp, #0 800202e: 6078 str r0, [r7, #4] 8002030: 460b mov r3, r1 8002032: 807b strh r3, [r7, #2] 8002034: 4613 mov r3, r2 8002036: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002038: 787b ldrb r3, [r7, #1] 800203a: 2b00 cmp r3, #0 800203c: d003 beq.n 8002046 { GPIOx->BSRR = GPIO_Pin; 800203e: 887a ldrh r2, [r7, #2] 8002040: 687b ldr r3, [r7, #4] 8002042: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002044: e003 b.n 800204e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002046: 887b ldrh r3, [r7, #2] 8002048: 041a lsls r2, r3, #16 800204a: 687b ldr r3, [r7, #4] 800204c: 619a str r2, [r3, #24] } 800204e: bf00 nop 8002050: 370c adds r7, #12 8002052: 46bd mov sp, r7 8002054: f85d 7b04 ldr.w r7, [sp], #4 8002058: 4770 bx lr 0800205a : * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 800205a: b480 push {r7} 800205c: b085 sub sp, #20 800205e: af00 add r7, sp, #0 8002060: 6078 str r0, [r7, #4] 8002062: 460b mov r3, r1 8002064: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); /* get current Output Data Register value */ odr = GPIOx->ODR; 8002066: 687b ldr r3, [r7, #4] 8002068: 695b ldr r3, [r3, #20] 800206a: 60fb str r3, [r7, #12] /* Set selected pins that were at low level, and reset ones that were high */ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); 800206c: 887a ldrh r2, [r7, #2] 800206e: 68fb ldr r3, [r7, #12] 8002070: 4013 ands r3, r2 8002072: 041a lsls r2, r3, #16 8002074: 68fb ldr r3, [r7, #12] 8002076: 43d9 mvns r1, r3 8002078: 887b ldrh r3, [r7, #2] 800207a: 400b ands r3, r1 800207c: 431a orrs r2, r3 800207e: 687b ldr r3, [r7, #4] 8002080: 619a str r2, [r3, #24] } 8002082: bf00 nop 8002084: 3714 adds r7, #20 8002086: 46bd mov sp, r7 8002088: f85d 7b04 ldr.w r7, [sp], #4 800208c: 4770 bx lr 0800208e : * @brief Handle HCD interrupt request. * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { 800208e: b580 push {r7, lr} 8002090: b086 sub sp, #24 8002092: af00 add r7, sp, #0 8002094: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8002096: 687b ldr r3, [r7, #4] 8002098: 681b ldr r3, [r3, #0] 800209a: 613b str r3, [r7, #16] uint32_t USBx_BASE = (uint32_t)USBx; 800209c: 693b ldr r3, [r7, #16] 800209e: 60fb str r3, [r7, #12] uint32_t i; uint32_t interrupt; /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) 80020a0: 687b ldr r3, [r7, #4] 80020a2: 681b ldr r3, [r3, #0] 80020a4: 4618 mov r0, r3 80020a6: f004 fab7 bl 8006618 80020aa: 4603 mov r3, r0 80020ac: 2b01 cmp r3, #1 80020ae: f040 80fb bne.w 80022a8 { /* Avoid spurious interrupt */ if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) 80020b2: 687b ldr r3, [r7, #4] 80020b4: 681b ldr r3, [r3, #0] 80020b6: 4618 mov r0, r3 80020b8: f004 fa7a bl 80065b0 80020bc: 4603 mov r3, r0 80020be: 2b00 cmp r3, #0 80020c0: f000 80f1 beq.w 80022a6 { return; } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 80020c4: 687b ldr r3, [r7, #4] 80020c6: 681b ldr r3, [r3, #0] 80020c8: 4618 mov r0, r3 80020ca: f004 fa71 bl 80065b0 80020ce: 4603 mov r3, r0 80020d0: f403 1300 and.w r3, r3, #2097152 @ 0x200000 80020d4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 80020d8: d104 bne.n 80020e4 { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 80020da: 687b ldr r3, [r7, #4] 80020dc: 681b ldr r3, [r3, #0] 80020de: f44f 1200 mov.w r2, #2097152 @ 0x200000 80020e2: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) 80020e4: 687b ldr r3, [r7, #4] 80020e6: 681b ldr r3, [r3, #0] 80020e8: 4618 mov r0, r3 80020ea: f004 fa61 bl 80065b0 80020ee: 4603 mov r3, r0 80020f0: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80020f4: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80020f8: d104 bne.n 8002104 { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); 80020fa: 687b ldr r3, [r7, #4] 80020fc: 681b ldr r3, [r3, #0] 80020fe: f44f 1280 mov.w r2, #1048576 @ 0x100000 8002102: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) 8002104: 687b ldr r3, [r7, #4] 8002106: 681b ldr r3, [r3, #0] 8002108: 4618 mov r0, r3 800210a: f004 fa51 bl 80065b0 800210e: 4603 mov r3, r0 8002110: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8002114: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 8002118: d104 bne.n 8002124 { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); 800211a: 687b ldr r3, [r7, #4] 800211c: 681b ldr r3, [r3, #0] 800211e: f04f 6280 mov.w r2, #67108864 @ 0x4000000 8002122: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) 8002124: 687b ldr r3, [r7, #4] 8002126: 681b ldr r3, [r3, #0] 8002128: 4618 mov r0, r3 800212a: f004 fa41 bl 80065b0 800212e: 4603 mov r3, r0 8002130: f003 0302 and.w r3, r3, #2 8002134: 2b02 cmp r3, #2 8002136: d103 bne.n 8002140 { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); 8002138: 687b ldr r3, [r7, #4] 800213a: 681b ldr r3, [r3, #0] 800213c: 2202 movs r2, #2 800213e: 615a str r2, [r3, #20] } /* Handle Host Disconnect Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) 8002140: 687b ldr r3, [r7, #4] 8002142: 681b ldr r3, [r3, #0] 8002144: 4618 mov r0, r3 8002146: f004 fa33 bl 80065b0 800214a: 4603 mov r3, r0 800214c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8002150: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8002154: d120 bne.n 8002198 { __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); 8002156: 687b ldr r3, [r7, #4] 8002158: 681b ldr r3, [r3, #0] 800215a: f04f 5200 mov.w r2, #536870912 @ 0x20000000 800215e: 615a str r2, [r3, #20] if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) 8002160: 68fb ldr r3, [r7, #12] 8002162: f503 6388 add.w r3, r3, #1088 @ 0x440 8002166: 681b ldr r3, [r3, #0] 8002168: f003 0301 and.w r3, r3, #1 800216c: 2b00 cmp r3, #0 800216e: d113 bne.n 8002198 { /* Flush USB Fifo */ (void)USB_FlushTxFifo(USBx, 0x10U); 8002170: 2110 movs r1, #16 8002172: 6938 ldr r0, [r7, #16] 8002174: f004 f964 bl 8006440 (void)USB_FlushRxFifo(USBx); 8002178: 6938 ldr r0, [r7, #16] 800217a: f004 f993 bl 80064a4 if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) 800217e: 687b ldr r3, [r7, #4] 8002180: 7a5b ldrb r3, [r3, #9] 8002182: 2b02 cmp r3, #2 8002184: d105 bne.n 8002192 { /* Restore FS Clock */ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); 8002186: 687b ldr r3, [r7, #4] 8002188: 681b ldr r3, [r3, #0] 800218a: 2101 movs r1, #1 800218c: 4618 mov r0, r3 800218e: f004 fa51 bl 8006634 /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->DisconnectCallback(hhcd); #else HAL_HCD_Disconnect_Callback(hhcd); 8002192: 6878 ldr r0, [r7, #4] 8002194: f005 fe20 bl 8007dd8 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Handle Host Port Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) 8002198: 687b ldr r3, [r7, #4] 800219a: 681b ldr r3, [r3, #0] 800219c: 4618 mov r0, r3 800219e: f004 fa07 bl 80065b0 80021a2: 4603 mov r3, r0 80021a4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 80021a8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 80021ac: d102 bne.n 80021b4 { HCD_Port_IRQHandler(hhcd); 80021ae: 6878 ldr r0, [r7, #4] 80021b0: f001 fca1 bl 8003af6 } /* Handle Host SOF Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) 80021b4: 687b ldr r3, [r7, #4] 80021b6: 681b ldr r3, [r3, #0] 80021b8: 4618 mov r0, r3 80021ba: f004 f9f9 bl 80065b0 80021be: 4603 mov r3, r0 80021c0: f003 0308 and.w r3, r3, #8 80021c4: 2b08 cmp r3, #8 80021c6: d106 bne.n 80021d6 { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->SOFCallback(hhcd); #else HAL_HCD_SOF_Callback(hhcd); 80021c8: 6878 ldr r0, [r7, #4] 80021ca: f005 fde9 bl 8007da0 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); 80021ce: 687b ldr r3, [r7, #4] 80021d0: 681b ldr r3, [r3, #0] 80021d2: 2208 movs r2, #8 80021d4: 615a str r2, [r3, #20] } /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) 80021d6: 687b ldr r3, [r7, #4] 80021d8: 681b ldr r3, [r3, #0] 80021da: 4618 mov r0, r3 80021dc: f004 f9e8 bl 80065b0 80021e0: 4603 mov r3, r0 80021e2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80021e6: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80021ea: d139 bne.n 8002260 { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); 80021ec: 687b ldr r3, [r7, #4] 80021ee: 681b ldr r3, [r3, #0] 80021f0: 4618 mov r0, r3 80021f2: f004 fa5c bl 80066ae 80021f6: 60b8 str r0, [r7, #8] for (i = 0U; i < hhcd->Init.Host_channels; i++) 80021f8: 2300 movs r3, #0 80021fa: 617b str r3, [r7, #20] 80021fc: e025 b.n 800224a { if ((interrupt & (1UL << (i & 0xFU))) != 0U) 80021fe: 697b ldr r3, [r7, #20] 8002200: f003 030f and.w r3, r3, #15 8002204: 68ba ldr r2, [r7, #8] 8002206: fa22 f303 lsr.w r3, r2, r3 800220a: f003 0301 and.w r3, r3, #1 800220e: 2b00 cmp r3, #0 8002210: d018 beq.n 8002244 { if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) 8002212: 697b ldr r3, [r7, #20] 8002214: 015a lsls r2, r3, #5 8002216: 68fb ldr r3, [r7, #12] 8002218: 4413 add r3, r2 800221a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800221e: 681b ldr r3, [r3, #0] 8002220: f403 4300 and.w r3, r3, #32768 @ 0x8000 8002224: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8002228: d106 bne.n 8002238 { HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); 800222a: 697b ldr r3, [r7, #20] 800222c: b2db uxtb r3, r3 800222e: 4619 mov r1, r3 8002230: 6878 ldr r0, [r7, #4] 8002232: f000 f859 bl 80022e8 8002236: e005 b.n 8002244 } else { HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); 8002238: 697b ldr r3, [r7, #20] 800223a: b2db uxtb r3, r3 800223c: 4619 mov r1, r3 800223e: 6878 ldr r0, [r7, #4] 8002240: f000 febb bl 8002fba for (i = 0U; i < hhcd->Init.Host_channels; i++) 8002244: 697b ldr r3, [r7, #20] 8002246: 3301 adds r3, #1 8002248: 617b str r3, [r7, #20] 800224a: 687b ldr r3, [r7, #4] 800224c: 795b ldrb r3, [r3, #5] 800224e: 461a mov r2, r3 8002250: 697b ldr r3, [r7, #20] 8002252: 4293 cmp r3, r2 8002254: d3d3 bcc.n 80021fe } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); 8002256: 687b ldr r3, [r7, #4] 8002258: 681b ldr r3, [r3, #0] 800225a: f04f 7200 mov.w r2, #33554432 @ 0x2000000 800225e: 615a str r2, [r3, #20] } /* Handle Rx Queue Level Interrupts */ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) 8002260: 687b ldr r3, [r7, #4] 8002262: 681b ldr r3, [r3, #0] 8002264: 4618 mov r0, r3 8002266: f004 f9a3 bl 80065b0 800226a: 4603 mov r3, r0 800226c: f003 0310 and.w r3, r3, #16 8002270: 2b10 cmp r3, #16 8002272: d101 bne.n 8002278 8002274: 2301 movs r3, #1 8002276: e000 b.n 800227a 8002278: 2300 movs r3, #0 800227a: 2b00 cmp r3, #0 800227c: d014 beq.n 80022a8 { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800227e: 687b ldr r3, [r7, #4] 8002280: 681b ldr r3, [r3, #0] 8002282: 699a ldr r2, [r3, #24] 8002284: 687b ldr r3, [r7, #4] 8002286: 681b ldr r3, [r3, #0] 8002288: f022 0210 bic.w r2, r2, #16 800228c: 619a str r2, [r3, #24] HCD_RXQLVL_IRQHandler(hhcd); 800228e: 6878 ldr r0, [r7, #4] 8002290: f001 fb52 bl 8003938 USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002294: 687b ldr r3, [r7, #4] 8002296: 681b ldr r3, [r3, #0] 8002298: 699a ldr r2, [r3, #24] 800229a: 687b ldr r3, [r7, #4] 800229c: 681b ldr r3, [r3, #0] 800229e: f042 0210 orr.w r2, r2, #16 80022a2: 619a str r2, [r3, #24] 80022a4: e000 b.n 80022a8 return; 80022a6: bf00 nop } } } 80022a8: 3718 adds r7, #24 80022aa: 46bd mov sp, r7 80022ac: bd80 pop {r7, pc} 080022ae : * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) { 80022ae: b580 push {r7, lr} 80022b0: b082 sub sp, #8 80022b2: af00 add r7, sp, #0 80022b4: 6078 str r0, [r7, #4] __HAL_LOCK(hhcd); 80022b6: 687b ldr r3, [r7, #4] 80022b8: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4 80022bc: 2b01 cmp r3, #1 80022be: d101 bne.n 80022c4 80022c0: 2302 movs r3, #2 80022c2: e00d b.n 80022e0 80022c4: 687b ldr r3, [r7, #4] 80022c6: 2201 movs r2, #1 80022c8: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4 (void)USB_StopHost(hhcd->Instance); 80022cc: 687b ldr r3, [r7, #4] 80022ce: 681b ldr r3, [r3, #0] 80022d0: 4618 mov r0, r3 80022d2: f004 fb1d bl 8006910 __HAL_UNLOCK(hhcd); 80022d6: 687b ldr r3, [r7, #4] 80022d8: 2200 movs r2, #0 80022da: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4 return HAL_OK; 80022de: 2300 movs r3, #0 } 80022e0: 4618 mov r0, r3 80022e2: 3708 adds r7, #8 80022e4: 46bd mov sp, r7 80022e6: bd80 pop {r7, pc} 080022e8 : * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { 80022e8: b580 push {r7, lr} 80022ea: b086 sub sp, #24 80022ec: af00 add r7, sp, #0 80022ee: 6078 str r0, [r7, #4] 80022f0: 460b mov r3, r1 80022f2: 70fb strb r3, [r7, #3] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 80022fa: 697b ldr r3, [r7, #20] 80022fc: 613b str r3, [r7, #16] uint32_t tmpreg; if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) 80022fe: 687b ldr r3, [r7, #4] 8002300: 681b ldr r3, [r3, #0] 8002302: 78fa ldrb r2, [r7, #3] 8002304: 4611 mov r1, r2 8002306: 4618 mov r0, r3 8002308: f004 f965 bl 80065d6 800230c: 4603 mov r3, r0 800230e: f003 0304 and.w r3, r3, #4 8002312: 2b04 cmp r3, #4 8002314: d11a bne.n 800234c { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); 8002316: 78fb ldrb r3, [r7, #3] 8002318: 015a lsls r2, r3, #5 800231a: 693b ldr r3, [r7, #16] 800231c: 4413 add r3, r2 800231e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002322: 461a mov r2, r3 8002324: 2304 movs r3, #4 8002326: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 8002328: 78fa ldrb r2, [r7, #3] 800232a: 6879 ldr r1, [r7, #4] 800232c: 4613 mov r3, r2 800232e: 011b lsls r3, r3, #4 8002330: 1a9b subs r3, r3, r2 8002332: 009b lsls r3, r3, #2 8002334: 440b add r3, r1 8002336: 334d adds r3, #77 @ 0x4d 8002338: 2207 movs r2, #7 800233a: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800233c: 687b ldr r3, [r7, #4] 800233e: 681b ldr r3, [r3, #0] 8002340: 78fa ldrb r2, [r7, #3] 8002342: 4611 mov r1, r2 8002344: 4618 mov r0, r3 8002346: f004 f9c3 bl 80066d0 800234a: e09e b.n 800248a } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) 800234c: 687b ldr r3, [r7, #4] 800234e: 681b ldr r3, [r3, #0] 8002350: 78fa ldrb r2, [r7, #3] 8002352: 4611 mov r1, r2 8002354: 4618 mov r0, r3 8002356: f004 f93e bl 80065d6 800235a: 4603 mov r3, r0 800235c: f403 7380 and.w r3, r3, #256 @ 0x100 8002360: f5b3 7f80 cmp.w r3, #256 @ 0x100 8002364: d11b bne.n 800239e { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); 8002366: 78fb ldrb r3, [r7, #3] 8002368: 015a lsls r2, r3, #5 800236a: 693b ldr r3, [r7, #16] 800236c: 4413 add r3, r2 800236e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002372: 461a mov r2, r3 8002374: f44f 7380 mov.w r3, #256 @ 0x100 8002378: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_BBLERR; 800237a: 78fa ldrb r2, [r7, #3] 800237c: 6879 ldr r1, [r7, #4] 800237e: 4613 mov r3, r2 8002380: 011b lsls r3, r3, #4 8002382: 1a9b subs r3, r3, r2 8002384: 009b lsls r3, r3, #2 8002386: 440b add r3, r1 8002388: 334d adds r3, #77 @ 0x4d 800238a: 2208 movs r2, #8 800238c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800238e: 687b ldr r3, [r7, #4] 8002390: 681b ldr r3, [r3, #0] 8002392: 78fa ldrb r2, [r7, #3] 8002394: 4611 mov r1, r2 8002396: 4618 mov r0, r3 8002398: f004 f99a bl 80066d0 800239c: e075 b.n 800248a } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) 800239e: 687b ldr r3, [r7, #4] 80023a0: 681b ldr r3, [r3, #0] 80023a2: 78fa ldrb r2, [r7, #3] 80023a4: 4611 mov r1, r2 80023a6: 4618 mov r0, r3 80023a8: f004 f915 bl 80065d6 80023ac: 4603 mov r3, r0 80023ae: f003 0308 and.w r3, r3, #8 80023b2: 2b08 cmp r3, #8 80023b4: d11a bne.n 80023ec { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); 80023b6: 78fb ldrb r3, [r7, #3] 80023b8: 015a lsls r2, r3, #5 80023ba: 693b ldr r3, [r7, #16] 80023bc: 4413 add r3, r2 80023be: f503 63a0 add.w r3, r3, #1280 @ 0x500 80023c2: 461a mov r2, r3 80023c4: 2308 movs r3, #8 80023c6: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_STALL; 80023c8: 78fa ldrb r2, [r7, #3] 80023ca: 6879 ldr r1, [r7, #4] 80023cc: 4613 mov r3, r2 80023ce: 011b lsls r3, r3, #4 80023d0: 1a9b subs r3, r3, r2 80023d2: 009b lsls r3, r3, #2 80023d4: 440b add r3, r1 80023d6: 334d adds r3, #77 @ 0x4d 80023d8: 2206 movs r2, #6 80023da: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80023dc: 687b ldr r3, [r7, #4] 80023de: 681b ldr r3, [r3, #0] 80023e0: 78fa ldrb r2, [r7, #3] 80023e2: 4611 mov r1, r2 80023e4: 4618 mov r0, r3 80023e6: f004 f973 bl 80066d0 80023ea: e04e b.n 800248a } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) 80023ec: 687b ldr r3, [r7, #4] 80023ee: 681b ldr r3, [r3, #0] 80023f0: 78fa ldrb r2, [r7, #3] 80023f2: 4611 mov r1, r2 80023f4: 4618 mov r0, r3 80023f6: f004 f8ee bl 80065d6 80023fa: 4603 mov r3, r0 80023fc: f403 6380 and.w r3, r3, #1024 @ 0x400 8002400: f5b3 6f80 cmp.w r3, #1024 @ 0x400 8002404: d11b bne.n 800243e { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); 8002406: 78fb ldrb r3, [r7, #3] 8002408: 015a lsls r2, r3, #5 800240a: 693b ldr r3, [r7, #16] 800240c: 4413 add r3, r2 800240e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002412: 461a mov r2, r3 8002414: f44f 6380 mov.w r3, #1024 @ 0x400 8002418: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_DATATGLERR; 800241a: 78fa ldrb r2, [r7, #3] 800241c: 6879 ldr r1, [r7, #4] 800241e: 4613 mov r3, r2 8002420: 011b lsls r3, r3, #4 8002422: 1a9b subs r3, r3, r2 8002424: 009b lsls r3, r3, #2 8002426: 440b add r3, r1 8002428: 334d adds r3, #77 @ 0x4d 800242a: 2209 movs r2, #9 800242c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800242e: 687b ldr r3, [r7, #4] 8002430: 681b ldr r3, [r3, #0] 8002432: 78fa ldrb r2, [r7, #3] 8002434: 4611 mov r1, r2 8002436: 4618 mov r0, r3 8002438: f004 f94a bl 80066d0 800243c: e025 b.n 800248a } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) 800243e: 687b ldr r3, [r7, #4] 8002440: 681b ldr r3, [r3, #0] 8002442: 78fa ldrb r2, [r7, #3] 8002444: 4611 mov r1, r2 8002446: 4618 mov r0, r3 8002448: f004 f8c5 bl 80065d6 800244c: 4603 mov r3, r0 800244e: f003 0380 and.w r3, r3, #128 @ 0x80 8002452: 2b80 cmp r3, #128 @ 0x80 8002454: d119 bne.n 800248a { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); 8002456: 78fb ldrb r3, [r7, #3] 8002458: 015a lsls r2, r3, #5 800245a: 693b ldr r3, [r7, #16] 800245c: 4413 add r3, r2 800245e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002462: 461a mov r2, r3 8002464: 2380 movs r3, #128 @ 0x80 8002466: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 8002468: 78fa ldrb r2, [r7, #3] 800246a: 6879 ldr r1, [r7, #4] 800246c: 4613 mov r3, r2 800246e: 011b lsls r3, r3, #4 8002470: 1a9b subs r3, r3, r2 8002472: 009b lsls r3, r3, #2 8002474: 440b add r3, r1 8002476: 334d adds r3, #77 @ 0x4d 8002478: 2207 movs r2, #7 800247a: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800247c: 687b ldr r3, [r7, #4] 800247e: 681b ldr r3, [r3, #0] 8002480: 78fa ldrb r2, [r7, #3] 8002482: 4611 mov r1, r2 8002484: 4618 mov r0, r3 8002486: f004 f923 bl 80066d0 else { /* ... */ } if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) 800248a: 687b ldr r3, [r7, #4] 800248c: 681b ldr r3, [r3, #0] 800248e: 78fa ldrb r2, [r7, #3] 8002490: 4611 mov r1, r2 8002492: 4618 mov r0, r3 8002494: f004 f89f bl 80065d6 8002498: 4603 mov r3, r0 800249a: f403 7300 and.w r3, r3, #512 @ 0x200 800249e: f5b3 7f00 cmp.w r3, #512 @ 0x200 80024a2: d112 bne.n 80024ca { (void)USB_HC_Halt(hhcd->Instance, chnum); 80024a4: 687b ldr r3, [r7, #4] 80024a6: 681b ldr r3, [r3, #0] 80024a8: 78fa ldrb r2, [r7, #3] 80024aa: 4611 mov r1, r2 80024ac: 4618 mov r0, r3 80024ae: f004 f90f bl 80066d0 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); 80024b2: 78fb ldrb r3, [r7, #3] 80024b4: 015a lsls r2, r3, #5 80024b6: 693b ldr r3, [r7, #16] 80024b8: 4413 add r3, r2 80024ba: f503 63a0 add.w r3, r3, #1280 @ 0x500 80024be: 461a mov r2, r3 80024c0: f44f 7300 mov.w r3, #512 @ 0x200 80024c4: 6093 str r3, [r2, #8] 80024c6: f000 bd75 b.w 8002fb4 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) 80024ca: 687b ldr r3, [r7, #4] 80024cc: 681b ldr r3, [r3, #0] 80024ce: 78fa ldrb r2, [r7, #3] 80024d0: 4611 mov r1, r2 80024d2: 4618 mov r0, r3 80024d4: f004 f87f bl 80065d6 80024d8: 4603 mov r3, r0 80024da: f003 0301 and.w r3, r3, #1 80024de: 2b01 cmp r3, #1 80024e0: f040 8128 bne.w 8002734 { /* Clear any pending ACK IT */ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 80024e4: 78fb ldrb r3, [r7, #3] 80024e6: 015a lsls r2, r3, #5 80024e8: 693b ldr r3, [r7, #16] 80024ea: 4413 add r3, r2 80024ec: f503 63a0 add.w r3, r3, #1280 @ 0x500 80024f0: 461a mov r2, r3 80024f2: 2320 movs r3, #32 80024f4: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_csplit == 1U) 80024f6: 78fa ldrb r2, [r7, #3] 80024f8: 6879 ldr r1, [r7, #4] 80024fa: 4613 mov r3, r2 80024fc: 011b lsls r3, r3, #4 80024fe: 1a9b subs r3, r3, r2 8002500: 009b lsls r3, r3, #2 8002502: 440b add r3, r1 8002504: 331b adds r3, #27 8002506: 781b ldrb r3, [r3, #0] 8002508: 2b01 cmp r3, #1 800250a: d119 bne.n 8002540 { hhcd->hc[chnum].do_csplit = 0U; 800250c: 78fa ldrb r2, [r7, #3] 800250e: 6879 ldr r1, [r7, #4] 8002510: 4613 mov r3, r2 8002512: 011b lsls r3, r3, #4 8002514: 1a9b subs r3, r3, r2 8002516: 009b lsls r3, r3, #2 8002518: 440b add r3, r1 800251a: 331b adds r3, #27 800251c: 2200 movs r2, #0 800251e: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8002520: 78fb ldrb r3, [r7, #3] 8002522: 015a lsls r2, r3, #5 8002524: 693b ldr r3, [r7, #16] 8002526: 4413 add r3, r2 8002528: f503 63a0 add.w r3, r3, #1280 @ 0x500 800252c: 685b ldr r3, [r3, #4] 800252e: 78fa ldrb r2, [r7, #3] 8002530: 0151 lsls r1, r2, #5 8002532: 693a ldr r2, [r7, #16] 8002534: 440a add r2, r1 8002536: f502 62a0 add.w r2, r2, #1280 @ 0x500 800253a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800253e: 6053 str r3, [r2, #4] } if (hhcd->Init.dma_enable != 0U) 8002540: 687b ldr r3, [r7, #4] 8002542: 799b ldrb r3, [r3, #6] 8002544: 2b00 cmp r3, #0 8002546: d01b beq.n 8002580 { hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); 8002548: 78fa ldrb r2, [r7, #3] 800254a: 6879 ldr r1, [r7, #4] 800254c: 4613 mov r3, r2 800254e: 011b lsls r3, r3, #4 8002550: 1a9b subs r3, r3, r2 8002552: 009b lsls r3, r3, #2 8002554: 440b add r3, r1 8002556: 3330 adds r3, #48 @ 0x30 8002558: 6819 ldr r1, [r3, #0] 800255a: 78fb ldrb r3, [r7, #3] 800255c: 015a lsls r2, r3, #5 800255e: 693b ldr r3, [r7, #16] 8002560: 4413 add r3, r2 8002562: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002566: 691b ldr r3, [r3, #16] 8002568: f3c3 0312 ubfx r3, r3, #0, #19 800256c: 78fa ldrb r2, [r7, #3] 800256e: 1ac9 subs r1, r1, r3 8002570: 6878 ldr r0, [r7, #4] 8002572: 4613 mov r3, r2 8002574: 011b lsls r3, r3, #4 8002576: 1a9b subs r3, r3, r2 8002578: 009b lsls r3, r3, #2 800257a: 4403 add r3, r0 800257c: 3338 adds r3, #56 @ 0x38 800257e: 6019 str r1, [r3, #0] } hhcd->hc[chnum].state = HC_XFRC; 8002580: 78fa ldrb r2, [r7, #3] 8002582: 6879 ldr r1, [r7, #4] 8002584: 4613 mov r3, r2 8002586: 011b lsls r3, r3, #4 8002588: 1a9b subs r3, r3, r2 800258a: 009b lsls r3, r3, #2 800258c: 440b add r3, r1 800258e: 334d adds r3, #77 @ 0x4d 8002590: 2201 movs r2, #1 8002592: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt = 0U; 8002594: 78fa ldrb r2, [r7, #3] 8002596: 6879 ldr r1, [r7, #4] 8002598: 4613 mov r3, r2 800259a: 011b lsls r3, r3, #4 800259c: 1a9b subs r3, r3, r2 800259e: 009b lsls r3, r3, #2 80025a0: 440b add r3, r1 80025a2: 3344 adds r3, #68 @ 0x44 80025a4: 2200 movs r2, #0 80025a6: 601a str r2, [r3, #0] __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); 80025a8: 78fb ldrb r3, [r7, #3] 80025aa: 015a lsls r2, r3, #5 80025ac: 693b ldr r3, [r7, #16] 80025ae: 4413 add r3, r2 80025b0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80025b4: 461a mov r2, r3 80025b6: 2301 movs r3, #1 80025b8: 6093 str r3, [r2, #8] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 80025ba: 78fa ldrb r2, [r7, #3] 80025bc: 6879 ldr r1, [r7, #4] 80025be: 4613 mov r3, r2 80025c0: 011b lsls r3, r3, #4 80025c2: 1a9b subs r3, r3, r2 80025c4: 009b lsls r3, r3, #2 80025c6: 440b add r3, r1 80025c8: 3326 adds r3, #38 @ 0x26 80025ca: 781b ldrb r3, [r3, #0] 80025cc: 2b00 cmp r3, #0 80025ce: d00a beq.n 80025e6 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 80025d0: 78fa ldrb r2, [r7, #3] 80025d2: 6879 ldr r1, [r7, #4] 80025d4: 4613 mov r3, r2 80025d6: 011b lsls r3, r3, #4 80025d8: 1a9b subs r3, r3, r2 80025da: 009b lsls r3, r3, #2 80025dc: 440b add r3, r1 80025de: 3326 adds r3, #38 @ 0x26 80025e0: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 80025e2: 2b02 cmp r3, #2 80025e4: d110 bne.n 8002608 { (void)USB_HC_Halt(hhcd->Instance, chnum); 80025e6: 687b ldr r3, [r7, #4] 80025e8: 681b ldr r3, [r3, #0] 80025ea: 78fa ldrb r2, [r7, #3] 80025ec: 4611 mov r1, r2 80025ee: 4618 mov r0, r3 80025f0: f004 f86e bl 80066d0 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 80025f4: 78fb ldrb r3, [r7, #3] 80025f6: 015a lsls r2, r3, #5 80025f8: 693b ldr r3, [r7, #16] 80025fa: 4413 add r3, r2 80025fc: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002600: 461a mov r2, r3 8002602: 2310 movs r3, #16 8002604: 6093 str r3, [r2, #8] 8002606: e03d b.n 8002684 } else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || 8002608: 78fa ldrb r2, [r7, #3] 800260a: 6879 ldr r1, [r7, #4] 800260c: 4613 mov r3, r2 800260e: 011b lsls r3, r3, #4 8002610: 1a9b subs r3, r3, r2 8002612: 009b lsls r3, r3, #2 8002614: 440b add r3, r1 8002616: 3326 adds r3, #38 @ 0x26 8002618: 781b ldrb r3, [r3, #0] 800261a: 2b03 cmp r3, #3 800261c: d00a beq.n 8002634 (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) 800261e: 78fa ldrb r2, [r7, #3] 8002620: 6879 ldr r1, [r7, #4] 8002622: 4613 mov r3, r2 8002624: 011b lsls r3, r3, #4 8002626: 1a9b subs r3, r3, r2 8002628: 009b lsls r3, r3, #2 800262a: 440b add r3, r1 800262c: 3326 adds r3, #38 @ 0x26 800262e: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || 8002630: 2b01 cmp r3, #1 8002632: d127 bne.n 8002684 { USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; 8002634: 78fb ldrb r3, [r7, #3] 8002636: 015a lsls r2, r3, #5 8002638: 693b ldr r3, [r7, #16] 800263a: 4413 add r3, r2 800263c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002640: 681b ldr r3, [r3, #0] 8002642: 78fa ldrb r2, [r7, #3] 8002644: 0151 lsls r1, r2, #5 8002646: 693a ldr r2, [r7, #16] 8002648: 440a add r2, r1 800264a: f502 62a0 add.w r2, r2, #1280 @ 0x500 800264e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 8002652: 6013 str r3, [r2, #0] hhcd->hc[chnum].urb_state = URB_DONE; 8002654: 78fa ldrb r2, [r7, #3] 8002656: 6879 ldr r1, [r7, #4] 8002658: 4613 mov r3, r2 800265a: 011b lsls r3, r3, #4 800265c: 1a9b subs r3, r3, r2 800265e: 009b lsls r3, r3, #2 8002660: 440b add r3, r1 8002662: 334c adds r3, #76 @ 0x4c 8002664: 2201 movs r2, #1 8002666: 701a strb r2, [r3, #0] #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 8002668: 78fa ldrb r2, [r7, #3] 800266a: 6879 ldr r1, [r7, #4] 800266c: 4613 mov r3, r2 800266e: 011b lsls r3, r3, #4 8002670: 1a9b subs r3, r3, r2 8002672: 009b lsls r3, r3, #2 8002674: 440b add r3, r1 8002676: 334c adds r3, #76 @ 0x4c 8002678: 781a ldrb r2, [r3, #0] 800267a: 78fb ldrb r3, [r7, #3] 800267c: 4619 mov r1, r3 800267e: 6878 ldr r0, [r7, #4] 8002680: f005 fbb8 bl 8007df4 else { /* ... */ } if (hhcd->Init.dma_enable == 1U) 8002684: 687b ldr r3, [r7, #4] 8002686: 799b ldrb r3, [r3, #6] 8002688: 2b01 cmp r3, #1 800268a: d13b bne.n 8002704 { if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) 800268c: 78fa ldrb r2, [r7, #3] 800268e: 6879 ldr r1, [r7, #4] 8002690: 4613 mov r3, r2 8002692: 011b lsls r3, r3, #4 8002694: 1a9b subs r3, r3, r2 8002696: 009b lsls r3, r3, #2 8002698: 440b add r3, r1 800269a: 3338 adds r3, #56 @ 0x38 800269c: 6819 ldr r1, [r3, #0] 800269e: 78fa ldrb r2, [r7, #3] 80026a0: 6878 ldr r0, [r7, #4] 80026a2: 4613 mov r3, r2 80026a4: 011b lsls r3, r3, #4 80026a6: 1a9b subs r3, r3, r2 80026a8: 009b lsls r3, r3, #2 80026aa: 4403 add r3, r0 80026ac: 3328 adds r3, #40 @ 0x28 80026ae: 881b ldrh r3, [r3, #0] 80026b0: 440b add r3, r1 80026b2: 1e59 subs r1, r3, #1 80026b4: 78fa ldrb r2, [r7, #3] 80026b6: 6878 ldr r0, [r7, #4] 80026b8: 4613 mov r3, r2 80026ba: 011b lsls r3, r3, #4 80026bc: 1a9b subs r3, r3, r2 80026be: 009b lsls r3, r3, #2 80026c0: 4403 add r3, r0 80026c2: 3328 adds r3, #40 @ 0x28 80026c4: 881b ldrh r3, [r3, #0] 80026c6: fbb1 f3f3 udiv r3, r1, r3 80026ca: f003 0301 and.w r3, r3, #1 80026ce: 2b00 cmp r3, #0 80026d0: f000 8470 beq.w 8002fb4 { hhcd->hc[chnum].toggle_in ^= 1U; 80026d4: 78fa ldrb r2, [r7, #3] 80026d6: 6879 ldr r1, [r7, #4] 80026d8: 4613 mov r3, r2 80026da: 011b lsls r3, r3, #4 80026dc: 1a9b subs r3, r3, r2 80026de: 009b lsls r3, r3, #2 80026e0: 440b add r3, r1 80026e2: 333c adds r3, #60 @ 0x3c 80026e4: 781b ldrb r3, [r3, #0] 80026e6: 78fa ldrb r2, [r7, #3] 80026e8: f083 0301 eor.w r3, r3, #1 80026ec: b2d8 uxtb r0, r3 80026ee: 6879 ldr r1, [r7, #4] 80026f0: 4613 mov r3, r2 80026f2: 011b lsls r3, r3, #4 80026f4: 1a9b subs r3, r3, r2 80026f6: 009b lsls r3, r3, #2 80026f8: 440b add r3, r1 80026fa: 333c adds r3, #60 @ 0x3c 80026fc: 4602 mov r2, r0 80026fe: 701a strb r2, [r3, #0] 8002700: f000 bc58 b.w 8002fb4 } } else { hhcd->hc[chnum].toggle_in ^= 1U; 8002704: 78fa ldrb r2, [r7, #3] 8002706: 6879 ldr r1, [r7, #4] 8002708: 4613 mov r3, r2 800270a: 011b lsls r3, r3, #4 800270c: 1a9b subs r3, r3, r2 800270e: 009b lsls r3, r3, #2 8002710: 440b add r3, r1 8002712: 333c adds r3, #60 @ 0x3c 8002714: 781b ldrb r3, [r3, #0] 8002716: 78fa ldrb r2, [r7, #3] 8002718: f083 0301 eor.w r3, r3, #1 800271c: b2d8 uxtb r0, r3 800271e: 6879 ldr r1, [r7, #4] 8002720: 4613 mov r3, r2 8002722: 011b lsls r3, r3, #4 8002724: 1a9b subs r3, r3, r2 8002726: 009b lsls r3, r3, #2 8002728: 440b add r3, r1 800272a: 333c adds r3, #60 @ 0x3c 800272c: 4602 mov r2, r0 800272e: 701a strb r2, [r3, #0] 8002730: f000 bc40 b.w 8002fb4 } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) 8002734: 687b ldr r3, [r7, #4] 8002736: 681b ldr r3, [r3, #0] 8002738: 78fa ldrb r2, [r7, #3] 800273a: 4611 mov r1, r2 800273c: 4618 mov r0, r3 800273e: f003 ff4a bl 80065d6 8002742: 4603 mov r3, r0 8002744: f003 0320 and.w r3, r3, #32 8002748: 2b20 cmp r3, #32 800274a: d131 bne.n 80027b0 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 800274c: 78fb ldrb r3, [r7, #3] 800274e: 015a lsls r2, r3, #5 8002750: 693b ldr r3, [r7, #16] 8002752: 4413 add r3, r2 8002754: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002758: 461a mov r2, r3 800275a: 2320 movs r3, #32 800275c: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_ssplit == 1U) 800275e: 78fa ldrb r2, [r7, #3] 8002760: 6879 ldr r1, [r7, #4] 8002762: 4613 mov r3, r2 8002764: 011b lsls r3, r3, #4 8002766: 1a9b subs r3, r3, r2 8002768: 009b lsls r3, r3, #2 800276a: 440b add r3, r1 800276c: 331a adds r3, #26 800276e: 781b ldrb r3, [r3, #0] 8002770: 2b01 cmp r3, #1 8002772: f040 841f bne.w 8002fb4 { hhcd->hc[chnum].do_csplit = 1U; 8002776: 78fa ldrb r2, [r7, #3] 8002778: 6879 ldr r1, [r7, #4] 800277a: 4613 mov r3, r2 800277c: 011b lsls r3, r3, #4 800277e: 1a9b subs r3, r3, r2 8002780: 009b lsls r3, r3, #2 8002782: 440b add r3, r1 8002784: 331b adds r3, #27 8002786: 2201 movs r2, #1 8002788: 701a strb r2, [r3, #0] hhcd->hc[chnum].state = HC_ACK; 800278a: 78fa ldrb r2, [r7, #3] 800278c: 6879 ldr r1, [r7, #4] 800278e: 4613 mov r3, r2 8002790: 011b lsls r3, r3, #4 8002792: 1a9b subs r3, r3, r2 8002794: 009b lsls r3, r3, #2 8002796: 440b add r3, r1 8002798: 334d adds r3, #77 @ 0x4d 800279a: 2203 movs r2, #3 800279c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800279e: 687b ldr r3, [r7, #4] 80027a0: 681b ldr r3, [r3, #0] 80027a2: 78fa ldrb r2, [r7, #3] 80027a4: 4611 mov r1, r2 80027a6: 4618 mov r0, r3 80027a8: f003 ff92 bl 80066d0 80027ac: f000 bc02 b.w 8002fb4 } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) 80027b0: 687b ldr r3, [r7, #4] 80027b2: 681b ldr r3, [r3, #0] 80027b4: 78fa ldrb r2, [r7, #3] 80027b6: 4611 mov r1, r2 80027b8: 4618 mov r0, r3 80027ba: f003 ff0c bl 80065d6 80027be: 4603 mov r3, r0 80027c0: f003 0302 and.w r3, r3, #2 80027c4: 2b02 cmp r3, #2 80027c6: f040 8305 bne.w 8002dd4 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); 80027ca: 78fb ldrb r3, [r7, #3] 80027cc: 015a lsls r2, r3, #5 80027ce: 693b ldr r3, [r7, #16] 80027d0: 4413 add r3, r2 80027d2: f503 63a0 add.w r3, r3, #1280 @ 0x500 80027d6: 461a mov r2, r3 80027d8: 2302 movs r3, #2 80027da: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].state == HC_XFRC) 80027dc: 78fa ldrb r2, [r7, #3] 80027de: 6879 ldr r1, [r7, #4] 80027e0: 4613 mov r3, r2 80027e2: 011b lsls r3, r3, #4 80027e4: 1a9b subs r3, r3, r2 80027e6: 009b lsls r3, r3, #2 80027e8: 440b add r3, r1 80027ea: 334d adds r3, #77 @ 0x4d 80027ec: 781b ldrb r3, [r3, #0] 80027ee: 2b01 cmp r3, #1 80027f0: d114 bne.n 800281c { hhcd->hc[chnum].state = HC_HALTED; 80027f2: 78fa ldrb r2, [r7, #3] 80027f4: 6879 ldr r1, [r7, #4] 80027f6: 4613 mov r3, r2 80027f8: 011b lsls r3, r3, #4 80027fa: 1a9b subs r3, r3, r2 80027fc: 009b lsls r3, r3, #2 80027fe: 440b add r3, r1 8002800: 334d adds r3, #77 @ 0x4d 8002802: 2202 movs r2, #2 8002804: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_DONE; 8002806: 78fa ldrb r2, [r7, #3] 8002808: 6879 ldr r1, [r7, #4] 800280a: 4613 mov r3, r2 800280c: 011b lsls r3, r3, #4 800280e: 1a9b subs r3, r3, r2 8002810: 009b lsls r3, r3, #2 8002812: 440b add r3, r1 8002814: 334c adds r3, #76 @ 0x4c 8002816: 2201 movs r2, #1 8002818: 701a strb r2, [r3, #0] 800281a: e2cc b.n 8002db6 } else if (hhcd->hc[chnum].state == HC_STALL) 800281c: 78fa ldrb r2, [r7, #3] 800281e: 6879 ldr r1, [r7, #4] 8002820: 4613 mov r3, r2 8002822: 011b lsls r3, r3, #4 8002824: 1a9b subs r3, r3, r2 8002826: 009b lsls r3, r3, #2 8002828: 440b add r3, r1 800282a: 334d adds r3, #77 @ 0x4d 800282c: 781b ldrb r3, [r3, #0] 800282e: 2b06 cmp r3, #6 8002830: d114 bne.n 800285c { hhcd->hc[chnum].state = HC_HALTED; 8002832: 78fa ldrb r2, [r7, #3] 8002834: 6879 ldr r1, [r7, #4] 8002836: 4613 mov r3, r2 8002838: 011b lsls r3, r3, #4 800283a: 1a9b subs r3, r3, r2 800283c: 009b lsls r3, r3, #2 800283e: 440b add r3, r1 8002840: 334d adds r3, #77 @ 0x4d 8002842: 2202 movs r2, #2 8002844: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_STALL; 8002846: 78fa ldrb r2, [r7, #3] 8002848: 6879 ldr r1, [r7, #4] 800284a: 4613 mov r3, r2 800284c: 011b lsls r3, r3, #4 800284e: 1a9b subs r3, r3, r2 8002850: 009b lsls r3, r3, #2 8002852: 440b add r3, r1 8002854: 334c adds r3, #76 @ 0x4c 8002856: 2205 movs r2, #5 8002858: 701a strb r2, [r3, #0] 800285a: e2ac b.n 8002db6 } else if ((hhcd->hc[chnum].state == HC_XACTERR) || 800285c: 78fa ldrb r2, [r7, #3] 800285e: 6879 ldr r1, [r7, #4] 8002860: 4613 mov r3, r2 8002862: 011b lsls r3, r3, #4 8002864: 1a9b subs r3, r3, r2 8002866: 009b lsls r3, r3, #2 8002868: 440b add r3, r1 800286a: 334d adds r3, #77 @ 0x4d 800286c: 781b ldrb r3, [r3, #0] 800286e: 2b07 cmp r3, #7 8002870: d00b beq.n 800288a (hhcd->hc[chnum].state == HC_DATATGLERR)) 8002872: 78fa ldrb r2, [r7, #3] 8002874: 6879 ldr r1, [r7, #4] 8002876: 4613 mov r3, r2 8002878: 011b lsls r3, r3, #4 800287a: 1a9b subs r3, r3, r2 800287c: 009b lsls r3, r3, #2 800287e: 440b add r3, r1 8002880: 334d adds r3, #77 @ 0x4d 8002882: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].state == HC_XACTERR) || 8002884: 2b09 cmp r3, #9 8002886: f040 80a6 bne.w 80029d6 { hhcd->hc[chnum].state = HC_HALTED; 800288a: 78fa ldrb r2, [r7, #3] 800288c: 6879 ldr r1, [r7, #4] 800288e: 4613 mov r3, r2 8002890: 011b lsls r3, r3, #4 8002892: 1a9b subs r3, r3, r2 8002894: 009b lsls r3, r3, #2 8002896: 440b add r3, r1 8002898: 334d adds r3, #77 @ 0x4d 800289a: 2202 movs r2, #2 800289c: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 800289e: 78fa ldrb r2, [r7, #3] 80028a0: 6879 ldr r1, [r7, #4] 80028a2: 4613 mov r3, r2 80028a4: 011b lsls r3, r3, #4 80028a6: 1a9b subs r3, r3, r2 80028a8: 009b lsls r3, r3, #2 80028aa: 440b add r3, r1 80028ac: 3344 adds r3, #68 @ 0x44 80028ae: 681b ldr r3, [r3, #0] 80028b0: 1c59 adds r1, r3, #1 80028b2: 6878 ldr r0, [r7, #4] 80028b4: 4613 mov r3, r2 80028b6: 011b lsls r3, r3, #4 80028b8: 1a9b subs r3, r3, r2 80028ba: 009b lsls r3, r3, #2 80028bc: 4403 add r3, r0 80028be: 3344 adds r3, #68 @ 0x44 80028c0: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 80028c2: 78fa ldrb r2, [r7, #3] 80028c4: 6879 ldr r1, [r7, #4] 80028c6: 4613 mov r3, r2 80028c8: 011b lsls r3, r3, #4 80028ca: 1a9b subs r3, r3, r2 80028cc: 009b lsls r3, r3, #2 80028ce: 440b add r3, r1 80028d0: 3344 adds r3, #68 @ 0x44 80028d2: 681b ldr r3, [r3, #0] 80028d4: 2b02 cmp r3, #2 80028d6: d943 bls.n 8002960 { hhcd->hc[chnum].ErrCnt = 0U; 80028d8: 78fa ldrb r2, [r7, #3] 80028da: 6879 ldr r1, [r7, #4] 80028dc: 4613 mov r3, r2 80028de: 011b lsls r3, r3, #4 80028e0: 1a9b subs r3, r3, r2 80028e2: 009b lsls r3, r3, #2 80028e4: 440b add r3, r1 80028e6: 3344 adds r3, #68 @ 0x44 80028e8: 2200 movs r2, #0 80028ea: 601a str r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 1U) 80028ec: 78fa ldrb r2, [r7, #3] 80028ee: 6879 ldr r1, [r7, #4] 80028f0: 4613 mov r3, r2 80028f2: 011b lsls r3, r3, #4 80028f4: 1a9b subs r3, r3, r2 80028f6: 009b lsls r3, r3, #2 80028f8: 440b add r3, r1 80028fa: 331a adds r3, #26 80028fc: 781b ldrb r3, [r3, #0] 80028fe: 2b01 cmp r3, #1 8002900: d123 bne.n 800294a { hhcd->hc[chnum].do_csplit = 0U; 8002902: 78fa ldrb r2, [r7, #3] 8002904: 6879 ldr r1, [r7, #4] 8002906: 4613 mov r3, r2 8002908: 011b lsls r3, r3, #4 800290a: 1a9b subs r3, r3, r2 800290c: 009b lsls r3, r3, #2 800290e: 440b add r3, r1 8002910: 331b adds r3, #27 8002912: 2200 movs r2, #0 8002914: 701a strb r2, [r3, #0] hhcd->hc[chnum].ep_ss_schedule = 0U; 8002916: 78fa ldrb r2, [r7, #3] 8002918: 6879 ldr r1, [r7, #4] 800291a: 4613 mov r3, r2 800291c: 011b lsls r3, r3, #4 800291e: 1a9b subs r3, r3, r2 8002920: 009b lsls r3, r3, #2 8002922: 440b add r3, r1 8002924: 331c adds r3, #28 8002926: 2200 movs r2, #0 8002928: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 800292a: 78fb ldrb r3, [r7, #3] 800292c: 015a lsls r2, r3, #5 800292e: 693b ldr r3, [r7, #16] 8002930: 4413 add r3, r2 8002932: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002936: 685b ldr r3, [r3, #4] 8002938: 78fa ldrb r2, [r7, #3] 800293a: 0151 lsls r1, r2, #5 800293c: 693a ldr r2, [r7, #16] 800293e: 440a add r2, r1 8002940: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002944: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002948: 6053 str r3, [r2, #4] } hhcd->hc[chnum].urb_state = URB_ERROR; 800294a: 78fa ldrb r2, [r7, #3] 800294c: 6879 ldr r1, [r7, #4] 800294e: 4613 mov r3, r2 8002950: 011b lsls r3, r3, #4 8002952: 1a9b subs r3, r3, r2 8002954: 009b lsls r3, r3, #2 8002956: 440b add r3, r1 8002958: 334c adds r3, #76 @ 0x4c 800295a: 2204 movs r2, #4 800295c: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800295e: e229 b.n 8002db4 } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002960: 78fa ldrb r2, [r7, #3] 8002962: 6879 ldr r1, [r7, #4] 8002964: 4613 mov r3, r2 8002966: 011b lsls r3, r3, #4 8002968: 1a9b subs r3, r3, r2 800296a: 009b lsls r3, r3, #2 800296c: 440b add r3, r1 800296e: 334c adds r3, #76 @ 0x4c 8002970: 2202 movs r2, #2 8002972: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002974: 78fa ldrb r2, [r7, #3] 8002976: 6879 ldr r1, [r7, #4] 8002978: 4613 mov r3, r2 800297a: 011b lsls r3, r3, #4 800297c: 1a9b subs r3, r3, r2 800297e: 009b lsls r3, r3, #2 8002980: 440b add r3, r1 8002982: 3326 adds r3, #38 @ 0x26 8002984: 781b ldrb r3, [r3, #0] 8002986: 2b00 cmp r3, #0 8002988: d00b beq.n 80029a2 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 800298a: 78fa ldrb r2, [r7, #3] 800298c: 6879 ldr r1, [r7, #4] 800298e: 4613 mov r3, r2 8002990: 011b lsls r3, r3, #4 8002992: 1a9b subs r3, r3, r2 8002994: 009b lsls r3, r3, #2 8002996: 440b add r3, r1 8002998: 3326 adds r3, #38 @ 0x26 800299a: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 800299c: 2b02 cmp r3, #2 800299e: f040 8209 bne.w 8002db4 { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 80029a2: 78fb ldrb r3, [r7, #3] 80029a4: 015a lsls r2, r3, #5 80029a6: 693b ldr r3, [r7, #16] 80029a8: 4413 add r3, r2 80029aa: f503 63a0 add.w r3, r3, #1280 @ 0x500 80029ae: 681b ldr r3, [r3, #0] 80029b0: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 80029b2: 68fb ldr r3, [r7, #12] 80029b4: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80029b8: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 80029ba: 68fb ldr r3, [r7, #12] 80029bc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80029c0: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 80029c2: 78fb ldrb r3, [r7, #3] 80029c4: 015a lsls r2, r3, #5 80029c6: 693b ldr r3, [r7, #16] 80029c8: 4413 add r3, r2 80029ca: f503 63a0 add.w r3, r3, #1280 @ 0x500 80029ce: 461a mov r2, r3 80029d0: 68fb ldr r3, [r7, #12] 80029d2: 6013 str r3, [r2, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 80029d4: e1ee b.n 8002db4 } } } else if (hhcd->hc[chnum].state == HC_NYET) 80029d6: 78fa ldrb r2, [r7, #3] 80029d8: 6879 ldr r1, [r7, #4] 80029da: 4613 mov r3, r2 80029dc: 011b lsls r3, r3, #4 80029de: 1a9b subs r3, r3, r2 80029e0: 009b lsls r3, r3, #2 80029e2: 440b add r3, r1 80029e4: 334d adds r3, #77 @ 0x4d 80029e6: 781b ldrb r3, [r3, #0] 80029e8: 2b05 cmp r3, #5 80029ea: f040 80c8 bne.w 8002b7e { hhcd->hc[chnum].state = HC_HALTED; 80029ee: 78fa ldrb r2, [r7, #3] 80029f0: 6879 ldr r1, [r7, #4] 80029f2: 4613 mov r3, r2 80029f4: 011b lsls r3, r3, #4 80029f6: 1a9b subs r3, r3, r2 80029f8: 009b lsls r3, r3, #2 80029fa: 440b add r3, r1 80029fc: 334d adds r3, #77 @ 0x4d 80029fe: 2202 movs r2, #2 8002a00: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 8002a02: 78fa ldrb r2, [r7, #3] 8002a04: 6879 ldr r1, [r7, #4] 8002a06: 4613 mov r3, r2 8002a08: 011b lsls r3, r3, #4 8002a0a: 1a9b subs r3, r3, r2 8002a0c: 009b lsls r3, r3, #2 8002a0e: 440b add r3, r1 8002a10: 331b adds r3, #27 8002a12: 781b ldrb r3, [r3, #0] 8002a14: 2b01 cmp r3, #1 8002a16: f040 81ce bne.w 8002db6 { if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) 8002a1a: 78fa ldrb r2, [r7, #3] 8002a1c: 6879 ldr r1, [r7, #4] 8002a1e: 4613 mov r3, r2 8002a20: 011b lsls r3, r3, #4 8002a22: 1a9b subs r3, r3, r2 8002a24: 009b lsls r3, r3, #2 8002a26: 440b add r3, r1 8002a28: 3326 adds r3, #38 @ 0x26 8002a2a: 781b ldrb r3, [r3, #0] 8002a2c: 2b03 cmp r3, #3 8002a2e: d16b bne.n 8002b08 { hhcd->hc[chnum].NyetErrCnt++; 8002a30: 78fa ldrb r2, [r7, #3] 8002a32: 6879 ldr r1, [r7, #4] 8002a34: 4613 mov r3, r2 8002a36: 011b lsls r3, r3, #4 8002a38: 1a9b subs r3, r3, r2 8002a3a: 009b lsls r3, r3, #2 8002a3c: 440b add r3, r1 8002a3e: 3348 adds r3, #72 @ 0x48 8002a40: 681b ldr r3, [r3, #0] 8002a42: 1c59 adds r1, r3, #1 8002a44: 6878 ldr r0, [r7, #4] 8002a46: 4613 mov r3, r2 8002a48: 011b lsls r3, r3, #4 8002a4a: 1a9b subs r3, r3, r2 8002a4c: 009b lsls r3, r3, #2 8002a4e: 4403 add r3, r0 8002a50: 3348 adds r3, #72 @ 0x48 8002a52: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].NyetErrCnt > 2U) 8002a54: 78fa ldrb r2, [r7, #3] 8002a56: 6879 ldr r1, [r7, #4] 8002a58: 4613 mov r3, r2 8002a5a: 011b lsls r3, r3, #4 8002a5c: 1a9b subs r3, r3, r2 8002a5e: 009b lsls r3, r3, #2 8002a60: 440b add r3, r1 8002a62: 3348 adds r3, #72 @ 0x48 8002a64: 681b ldr r3, [r3, #0] 8002a66: 2b02 cmp r3, #2 8002a68: d943 bls.n 8002af2 { hhcd->hc[chnum].NyetErrCnt = 0U; 8002a6a: 78fa ldrb r2, [r7, #3] 8002a6c: 6879 ldr r1, [r7, #4] 8002a6e: 4613 mov r3, r2 8002a70: 011b lsls r3, r3, #4 8002a72: 1a9b subs r3, r3, r2 8002a74: 009b lsls r3, r3, #2 8002a76: 440b add r3, r1 8002a78: 3348 adds r3, #72 @ 0x48 8002a7a: 2200 movs r2, #0 8002a7c: 601a str r2, [r3, #0] hhcd->hc[chnum].do_csplit = 0U; 8002a7e: 78fa ldrb r2, [r7, #3] 8002a80: 6879 ldr r1, [r7, #4] 8002a82: 4613 mov r3, r2 8002a84: 011b lsls r3, r3, #4 8002a86: 1a9b subs r3, r3, r2 8002a88: 009b lsls r3, r3, #2 8002a8a: 440b add r3, r1 8002a8c: 331b adds r3, #27 8002a8e: 2200 movs r2, #0 8002a90: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt < 3U) 8002a92: 78fa ldrb r2, [r7, #3] 8002a94: 6879 ldr r1, [r7, #4] 8002a96: 4613 mov r3, r2 8002a98: 011b lsls r3, r3, #4 8002a9a: 1a9b subs r3, r3, r2 8002a9c: 009b lsls r3, r3, #2 8002a9e: 440b add r3, r1 8002aa0: 3344 adds r3, #68 @ 0x44 8002aa2: 681b ldr r3, [r3, #0] 8002aa4: 2b02 cmp r3, #2 8002aa6: d809 bhi.n 8002abc { hhcd->hc[chnum].ep_ss_schedule = 1U; 8002aa8: 78fa ldrb r2, [r7, #3] 8002aaa: 6879 ldr r1, [r7, #4] 8002aac: 4613 mov r3, r2 8002aae: 011b lsls r3, r3, #4 8002ab0: 1a9b subs r3, r3, r2 8002ab2: 009b lsls r3, r3, #2 8002ab4: 440b add r3, r1 8002ab6: 331c adds r3, #28 8002ab8: 2201 movs r2, #1 8002aba: 701a strb r2, [r3, #0] } __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8002abc: 78fb ldrb r3, [r7, #3] 8002abe: 015a lsls r2, r3, #5 8002ac0: 693b ldr r3, [r7, #16] 8002ac2: 4413 add r3, r2 8002ac4: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002ac8: 685b ldr r3, [r3, #4] 8002aca: 78fa ldrb r2, [r7, #3] 8002acc: 0151 lsls r1, r2, #5 8002ace: 693a ldr r2, [r7, #16] 8002ad0: 440a add r2, r1 8002ad2: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002ad6: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002ada: 6053 str r3, [r2, #4] hhcd->hc[chnum].urb_state = URB_ERROR; 8002adc: 78fa ldrb r2, [r7, #3] 8002ade: 6879 ldr r1, [r7, #4] 8002ae0: 4613 mov r3, r2 8002ae2: 011b lsls r3, r3, #4 8002ae4: 1a9b subs r3, r3, r2 8002ae6: 009b lsls r3, r3, #2 8002ae8: 440b add r3, r1 8002aea: 334c adds r3, #76 @ 0x4c 8002aec: 2204 movs r2, #4 8002aee: 701a strb r2, [r3, #0] 8002af0: e014 b.n 8002b1c } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002af2: 78fa ldrb r2, [r7, #3] 8002af4: 6879 ldr r1, [r7, #4] 8002af6: 4613 mov r3, r2 8002af8: 011b lsls r3, r3, #4 8002afa: 1a9b subs r3, r3, r2 8002afc: 009b lsls r3, r3, #2 8002afe: 440b add r3, r1 8002b00: 334c adds r3, #76 @ 0x4c 8002b02: 2202 movs r2, #2 8002b04: 701a strb r2, [r3, #0] 8002b06: e009 b.n 8002b1c } } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002b08: 78fa ldrb r2, [r7, #3] 8002b0a: 6879 ldr r1, [r7, #4] 8002b0c: 4613 mov r3, r2 8002b0e: 011b lsls r3, r3, #4 8002b10: 1a9b subs r3, r3, r2 8002b12: 009b lsls r3, r3, #2 8002b14: 440b add r3, r1 8002b16: 334c adds r3, #76 @ 0x4c 8002b18: 2202 movs r2, #2 8002b1a: 701a strb r2, [r3, #0] } if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002b1c: 78fa ldrb r2, [r7, #3] 8002b1e: 6879 ldr r1, [r7, #4] 8002b20: 4613 mov r3, r2 8002b22: 011b lsls r3, r3, #4 8002b24: 1a9b subs r3, r3, r2 8002b26: 009b lsls r3, r3, #2 8002b28: 440b add r3, r1 8002b2a: 3326 adds r3, #38 @ 0x26 8002b2c: 781b ldrb r3, [r3, #0] 8002b2e: 2b00 cmp r3, #0 8002b30: d00b beq.n 8002b4a (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002b32: 78fa ldrb r2, [r7, #3] 8002b34: 6879 ldr r1, [r7, #4] 8002b36: 4613 mov r3, r2 8002b38: 011b lsls r3, r3, #4 8002b3a: 1a9b subs r3, r3, r2 8002b3c: 009b lsls r3, r3, #2 8002b3e: 440b add r3, r1 8002b40: 3326 adds r3, #38 @ 0x26 8002b42: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002b44: 2b02 cmp r3, #2 8002b46: f040 8136 bne.w 8002db6 { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002b4a: 78fb ldrb r3, [r7, #3] 8002b4c: 015a lsls r2, r3, #5 8002b4e: 693b ldr r3, [r7, #16] 8002b50: 4413 add r3, r2 8002b52: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002b56: 681b ldr r3, [r3, #0] 8002b58: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002b5a: 68fb ldr r3, [r7, #12] 8002b5c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002b60: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002b62: 68fb ldr r3, [r7, #12] 8002b64: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002b68: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002b6a: 78fb ldrb r3, [r7, #3] 8002b6c: 015a lsls r2, r3, #5 8002b6e: 693b ldr r3, [r7, #16] 8002b70: 4413 add r3, r2 8002b72: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002b76: 461a mov r2, r3 8002b78: 68fb ldr r3, [r7, #12] 8002b7a: 6013 str r3, [r2, #0] 8002b7c: e11b b.n 8002db6 } } } else if (hhcd->hc[chnum].state == HC_ACK) 8002b7e: 78fa ldrb r2, [r7, #3] 8002b80: 6879 ldr r1, [r7, #4] 8002b82: 4613 mov r3, r2 8002b84: 011b lsls r3, r3, #4 8002b86: 1a9b subs r3, r3, r2 8002b88: 009b lsls r3, r3, #2 8002b8a: 440b add r3, r1 8002b8c: 334d adds r3, #77 @ 0x4d 8002b8e: 781b ldrb r3, [r3, #0] 8002b90: 2b03 cmp r3, #3 8002b92: f040 8081 bne.w 8002c98 { hhcd->hc[chnum].state = HC_HALTED; 8002b96: 78fa ldrb r2, [r7, #3] 8002b98: 6879 ldr r1, [r7, #4] 8002b9a: 4613 mov r3, r2 8002b9c: 011b lsls r3, r3, #4 8002b9e: 1a9b subs r3, r3, r2 8002ba0: 009b lsls r3, r3, #2 8002ba2: 440b add r3, r1 8002ba4: 334d adds r3, #77 @ 0x4d 8002ba6: 2202 movs r2, #2 8002ba8: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 8002baa: 78fa ldrb r2, [r7, #3] 8002bac: 6879 ldr r1, [r7, #4] 8002bae: 4613 mov r3, r2 8002bb0: 011b lsls r3, r3, #4 8002bb2: 1a9b subs r3, r3, r2 8002bb4: 009b lsls r3, r3, #2 8002bb6: 440b add r3, r1 8002bb8: 331b adds r3, #27 8002bba: 781b ldrb r3, [r3, #0] 8002bbc: 2b01 cmp r3, #1 8002bbe: f040 80fa bne.w 8002db6 { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002bc2: 78fa ldrb r2, [r7, #3] 8002bc4: 6879 ldr r1, [r7, #4] 8002bc6: 4613 mov r3, r2 8002bc8: 011b lsls r3, r3, #4 8002bca: 1a9b subs r3, r3, r2 8002bcc: 009b lsls r3, r3, #2 8002bce: 440b add r3, r1 8002bd0: 334c adds r3, #76 @ 0x4c 8002bd2: 2202 movs r2, #2 8002bd4: 701a strb r2, [r3, #0] /* Set Complete split and re-activate the channel */ USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; 8002bd6: 78fb ldrb r3, [r7, #3] 8002bd8: 015a lsls r2, r3, #5 8002bda: 693b ldr r3, [r7, #16] 8002bdc: 4413 add r3, r2 8002bde: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002be2: 685b ldr r3, [r3, #4] 8002be4: 78fa ldrb r2, [r7, #3] 8002be6: 0151 lsls r1, r2, #5 8002be8: 693a ldr r2, [r7, #16] 8002bea: 440a add r2, r1 8002bec: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002bf0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8002bf4: 6053 str r3, [r2, #4] USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; 8002bf6: 78fb ldrb r3, [r7, #3] 8002bf8: 015a lsls r2, r3, #5 8002bfa: 693b ldr r3, [r7, #16] 8002bfc: 4413 add r3, r2 8002bfe: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c02: 68db ldr r3, [r3, #12] 8002c04: 78fa ldrb r2, [r7, #3] 8002c06: 0151 lsls r1, r2, #5 8002c08: 693a ldr r2, [r7, #16] 8002c0a: 440a add r2, r1 8002c0c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002c10: f043 0340 orr.w r3, r3, #64 @ 0x40 8002c14: 60d3 str r3, [r2, #12] USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; 8002c16: 78fb ldrb r3, [r7, #3] 8002c18: 015a lsls r2, r3, #5 8002c1a: 693b ldr r3, [r7, #16] 8002c1c: 4413 add r3, r2 8002c1e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c22: 68db ldr r3, [r3, #12] 8002c24: 78fa ldrb r2, [r7, #3] 8002c26: 0151 lsls r1, r2, #5 8002c28: 693a ldr r2, [r7, #16] 8002c2a: 440a add r2, r1 8002c2c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002c30: f023 0320 bic.w r3, r3, #32 8002c34: 60d3 str r3, [r2, #12] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002c36: 78fa ldrb r2, [r7, #3] 8002c38: 6879 ldr r1, [r7, #4] 8002c3a: 4613 mov r3, r2 8002c3c: 011b lsls r3, r3, #4 8002c3e: 1a9b subs r3, r3, r2 8002c40: 009b lsls r3, r3, #2 8002c42: 440b add r3, r1 8002c44: 3326 adds r3, #38 @ 0x26 8002c46: 781b ldrb r3, [r3, #0] 8002c48: 2b00 cmp r3, #0 8002c4a: d00b beq.n 8002c64 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002c4c: 78fa ldrb r2, [r7, #3] 8002c4e: 6879 ldr r1, [r7, #4] 8002c50: 4613 mov r3, r2 8002c52: 011b lsls r3, r3, #4 8002c54: 1a9b subs r3, r3, r2 8002c56: 009b lsls r3, r3, #2 8002c58: 440b add r3, r1 8002c5a: 3326 adds r3, #38 @ 0x26 8002c5c: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002c5e: 2b02 cmp r3, #2 8002c60: f040 80a9 bne.w 8002db6 { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002c64: 78fb ldrb r3, [r7, #3] 8002c66: 015a lsls r2, r3, #5 8002c68: 693b ldr r3, [r7, #16] 8002c6a: 4413 add r3, r2 8002c6c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c70: 681b ldr r3, [r3, #0] 8002c72: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002c74: 68fb ldr r3, [r7, #12] 8002c76: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002c7a: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002c7c: 68fb ldr r3, [r7, #12] 8002c7e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002c82: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002c84: 78fb ldrb r3, [r7, #3] 8002c86: 015a lsls r2, r3, #5 8002c88: 693b ldr r3, [r7, #16] 8002c8a: 4413 add r3, r2 8002c8c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c90: 461a mov r2, r3 8002c92: 68fb ldr r3, [r7, #12] 8002c94: 6013 str r3, [r2, #0] 8002c96: e08e b.n 8002db6 } } } else if (hhcd->hc[chnum].state == HC_NAK) 8002c98: 78fa ldrb r2, [r7, #3] 8002c9a: 6879 ldr r1, [r7, #4] 8002c9c: 4613 mov r3, r2 8002c9e: 011b lsls r3, r3, #4 8002ca0: 1a9b subs r3, r3, r2 8002ca2: 009b lsls r3, r3, #2 8002ca4: 440b add r3, r1 8002ca6: 334d adds r3, #77 @ 0x4d 8002ca8: 781b ldrb r3, [r3, #0] 8002caa: 2b04 cmp r3, #4 8002cac: d143 bne.n 8002d36 { hhcd->hc[chnum].state = HC_HALTED; 8002cae: 78fa ldrb r2, [r7, #3] 8002cb0: 6879 ldr r1, [r7, #4] 8002cb2: 4613 mov r3, r2 8002cb4: 011b lsls r3, r3, #4 8002cb6: 1a9b subs r3, r3, r2 8002cb8: 009b lsls r3, r3, #2 8002cba: 440b add r3, r1 8002cbc: 334d adds r3, #77 @ 0x4d 8002cbe: 2202 movs r2, #2 8002cc0: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002cc2: 78fa ldrb r2, [r7, #3] 8002cc4: 6879 ldr r1, [r7, #4] 8002cc6: 4613 mov r3, r2 8002cc8: 011b lsls r3, r3, #4 8002cca: 1a9b subs r3, r3, r2 8002ccc: 009b lsls r3, r3, #2 8002cce: 440b add r3, r1 8002cd0: 334c adds r3, #76 @ 0x4c 8002cd2: 2202 movs r2, #2 8002cd4: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002cd6: 78fa ldrb r2, [r7, #3] 8002cd8: 6879 ldr r1, [r7, #4] 8002cda: 4613 mov r3, r2 8002cdc: 011b lsls r3, r3, #4 8002cde: 1a9b subs r3, r3, r2 8002ce0: 009b lsls r3, r3, #2 8002ce2: 440b add r3, r1 8002ce4: 3326 adds r3, #38 @ 0x26 8002ce6: 781b ldrb r3, [r3, #0] 8002ce8: 2b00 cmp r3, #0 8002cea: d00a beq.n 8002d02 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002cec: 78fa ldrb r2, [r7, #3] 8002cee: 6879 ldr r1, [r7, #4] 8002cf0: 4613 mov r3, r2 8002cf2: 011b lsls r3, r3, #4 8002cf4: 1a9b subs r3, r3, r2 8002cf6: 009b lsls r3, r3, #2 8002cf8: 440b add r3, r1 8002cfa: 3326 adds r3, #38 @ 0x26 8002cfc: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002cfe: 2b02 cmp r3, #2 8002d00: d159 bne.n 8002db6 { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002d02: 78fb ldrb r3, [r7, #3] 8002d04: 015a lsls r2, r3, #5 8002d06: 693b ldr r3, [r7, #16] 8002d08: 4413 add r3, r2 8002d0a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002d0e: 681b ldr r3, [r3, #0] 8002d10: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002d12: 68fb ldr r3, [r7, #12] 8002d14: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002d18: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002d1a: 68fb ldr r3, [r7, #12] 8002d1c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002d20: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002d22: 78fb ldrb r3, [r7, #3] 8002d24: 015a lsls r2, r3, #5 8002d26: 693b ldr r3, [r7, #16] 8002d28: 4413 add r3, r2 8002d2a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002d2e: 461a mov r2, r3 8002d30: 68fb ldr r3, [r7, #12] 8002d32: 6013 str r3, [r2, #0] 8002d34: e03f b.n 8002db6 } } else if (hhcd->hc[chnum].state == HC_BBLERR) 8002d36: 78fa ldrb r2, [r7, #3] 8002d38: 6879 ldr r1, [r7, #4] 8002d3a: 4613 mov r3, r2 8002d3c: 011b lsls r3, r3, #4 8002d3e: 1a9b subs r3, r3, r2 8002d40: 009b lsls r3, r3, #2 8002d42: 440b add r3, r1 8002d44: 334d adds r3, #77 @ 0x4d 8002d46: 781b ldrb r3, [r3, #0] 8002d48: 2b08 cmp r3, #8 8002d4a: d126 bne.n 8002d9a { hhcd->hc[chnum].state = HC_HALTED; 8002d4c: 78fa ldrb r2, [r7, #3] 8002d4e: 6879 ldr r1, [r7, #4] 8002d50: 4613 mov r3, r2 8002d52: 011b lsls r3, r3, #4 8002d54: 1a9b subs r3, r3, r2 8002d56: 009b lsls r3, r3, #2 8002d58: 440b add r3, r1 8002d5a: 334d adds r3, #77 @ 0x4d 8002d5c: 2202 movs r2, #2 8002d5e: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 8002d60: 78fa ldrb r2, [r7, #3] 8002d62: 6879 ldr r1, [r7, #4] 8002d64: 4613 mov r3, r2 8002d66: 011b lsls r3, r3, #4 8002d68: 1a9b subs r3, r3, r2 8002d6a: 009b lsls r3, r3, #2 8002d6c: 440b add r3, r1 8002d6e: 3344 adds r3, #68 @ 0x44 8002d70: 681b ldr r3, [r3, #0] 8002d72: 1c59 adds r1, r3, #1 8002d74: 6878 ldr r0, [r7, #4] 8002d76: 4613 mov r3, r2 8002d78: 011b lsls r3, r3, #4 8002d7a: 1a9b subs r3, r3, r2 8002d7c: 009b lsls r3, r3, #2 8002d7e: 4403 add r3, r0 8002d80: 3344 adds r3, #68 @ 0x44 8002d82: 6019 str r1, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 8002d84: 78fa ldrb r2, [r7, #3] 8002d86: 6879 ldr r1, [r7, #4] 8002d88: 4613 mov r3, r2 8002d8a: 011b lsls r3, r3, #4 8002d8c: 1a9b subs r3, r3, r2 8002d8e: 009b lsls r3, r3, #2 8002d90: 440b add r3, r1 8002d92: 334c adds r3, #76 @ 0x4c 8002d94: 2204 movs r2, #4 8002d96: 701a strb r2, [r3, #0] 8002d98: e00d b.n 8002db6 } else { if (hhcd->hc[chnum].state == HC_HALTED) 8002d9a: 78fa ldrb r2, [r7, #3] 8002d9c: 6879 ldr r1, [r7, #4] 8002d9e: 4613 mov r3, r2 8002da0: 011b lsls r3, r3, #4 8002da2: 1a9b subs r3, r3, r2 8002da4: 009b lsls r3, r3, #2 8002da6: 440b add r3, r1 8002da8: 334d adds r3, #77 @ 0x4d 8002daa: 781b ldrb r3, [r3, #0] 8002dac: 2b02 cmp r3, #2 8002dae: f000 8100 beq.w 8002fb2 8002db2: e000 b.n 8002db6 if (hhcd->hc[chnum].ErrCnt > 2U) 8002db4: bf00 nop } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 8002db6: 78fa ldrb r2, [r7, #3] 8002db8: 6879 ldr r1, [r7, #4] 8002dba: 4613 mov r3, r2 8002dbc: 011b lsls r3, r3, #4 8002dbe: 1a9b subs r3, r3, r2 8002dc0: 009b lsls r3, r3, #2 8002dc2: 440b add r3, r1 8002dc4: 334c adds r3, #76 @ 0x4c 8002dc6: 781a ldrb r2, [r3, #0] 8002dc8: 78fb ldrb r3, [r7, #3] 8002dca: 4619 mov r1, r3 8002dcc: 6878 ldr r0, [r7, #4] 8002dce: f005 f811 bl 8007df4 8002dd2: e0ef b.n 8002fb4 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 8002dd4: 687b ldr r3, [r7, #4] 8002dd6: 681b ldr r3, [r3, #0] 8002dd8: 78fa ldrb r2, [r7, #3] 8002dda: 4611 mov r1, r2 8002ddc: 4618 mov r0, r3 8002dde: f003 fbfa bl 80065d6 8002de2: 4603 mov r3, r0 8002de4: f003 0340 and.w r3, r3, #64 @ 0x40 8002de8: 2b40 cmp r3, #64 @ 0x40 8002dea: d12f bne.n 8002e4c { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 8002dec: 78fb ldrb r3, [r7, #3] 8002dee: 015a lsls r2, r3, #5 8002df0: 693b ldr r3, [r7, #16] 8002df2: 4413 add r3, r2 8002df4: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002df8: 461a mov r2, r3 8002dfa: 2340 movs r3, #64 @ 0x40 8002dfc: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_NYET; 8002dfe: 78fa ldrb r2, [r7, #3] 8002e00: 6879 ldr r1, [r7, #4] 8002e02: 4613 mov r3, r2 8002e04: 011b lsls r3, r3, #4 8002e06: 1a9b subs r3, r3, r2 8002e08: 009b lsls r3, r3, #2 8002e0a: 440b add r3, r1 8002e0c: 334d adds r3, #77 @ 0x4d 8002e0e: 2205 movs r2, #5 8002e10: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 0U) 8002e12: 78fa ldrb r2, [r7, #3] 8002e14: 6879 ldr r1, [r7, #4] 8002e16: 4613 mov r3, r2 8002e18: 011b lsls r3, r3, #4 8002e1a: 1a9b subs r3, r3, r2 8002e1c: 009b lsls r3, r3, #2 8002e1e: 440b add r3, r1 8002e20: 331a adds r3, #26 8002e22: 781b ldrb r3, [r3, #0] 8002e24: 2b00 cmp r3, #0 8002e26: d109 bne.n 8002e3c { hhcd->hc[chnum].ErrCnt = 0U; 8002e28: 78fa ldrb r2, [r7, #3] 8002e2a: 6879 ldr r1, [r7, #4] 8002e2c: 4613 mov r3, r2 8002e2e: 011b lsls r3, r3, #4 8002e30: 1a9b subs r3, r3, r2 8002e32: 009b lsls r3, r3, #2 8002e34: 440b add r3, r1 8002e36: 3344 adds r3, #68 @ 0x44 8002e38: 2200 movs r2, #0 8002e3a: 601a str r2, [r3, #0] } (void)USB_HC_Halt(hhcd->Instance, chnum); 8002e3c: 687b ldr r3, [r7, #4] 8002e3e: 681b ldr r3, [r3, #0] 8002e40: 78fa ldrb r2, [r7, #3] 8002e42: 4611 mov r1, r2 8002e44: 4618 mov r0, r3 8002e46: f003 fc43 bl 80066d0 8002e4a: e0b3 b.n 8002fb4 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) 8002e4c: 687b ldr r3, [r7, #4] 8002e4e: 681b ldr r3, [r3, #0] 8002e50: 78fa ldrb r2, [r7, #3] 8002e52: 4611 mov r1, r2 8002e54: 4618 mov r0, r3 8002e56: f003 fbbe bl 80065d6 8002e5a: 4603 mov r3, r0 8002e5c: f003 0310 and.w r3, r3, #16 8002e60: 2b10 cmp r3, #16 8002e62: f040 80a7 bne.w 8002fb4 { if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) 8002e66: 78fa ldrb r2, [r7, #3] 8002e68: 6879 ldr r1, [r7, #4] 8002e6a: 4613 mov r3, r2 8002e6c: 011b lsls r3, r3, #4 8002e6e: 1a9b subs r3, r3, r2 8002e70: 009b lsls r3, r3, #2 8002e72: 440b add r3, r1 8002e74: 3326 adds r3, #38 @ 0x26 8002e76: 781b ldrb r3, [r3, #0] 8002e78: 2b03 cmp r3, #3 8002e7a: d11b bne.n 8002eb4 { hhcd->hc[chnum].ErrCnt = 0U; 8002e7c: 78fa ldrb r2, [r7, #3] 8002e7e: 6879 ldr r1, [r7, #4] 8002e80: 4613 mov r3, r2 8002e82: 011b lsls r3, r3, #4 8002e84: 1a9b subs r3, r3, r2 8002e86: 009b lsls r3, r3, #2 8002e88: 440b add r3, r1 8002e8a: 3344 adds r3, #68 @ 0x44 8002e8c: 2200 movs r2, #0 8002e8e: 601a str r2, [r3, #0] hhcd->hc[chnum].state = HC_NAK; 8002e90: 78fa ldrb r2, [r7, #3] 8002e92: 6879 ldr r1, [r7, #4] 8002e94: 4613 mov r3, r2 8002e96: 011b lsls r3, r3, #4 8002e98: 1a9b subs r3, r3, r2 8002e9a: 009b lsls r3, r3, #2 8002e9c: 440b add r3, r1 8002e9e: 334d adds r3, #77 @ 0x4d 8002ea0: 2204 movs r2, #4 8002ea2: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002ea4: 687b ldr r3, [r7, #4] 8002ea6: 681b ldr r3, [r3, #0] 8002ea8: 78fa ldrb r2, [r7, #3] 8002eaa: 4611 mov r1, r2 8002eac: 4618 mov r0, r3 8002eae: f003 fc0f bl 80066d0 8002eb2: e03f b.n 8002f34 } else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002eb4: 78fa ldrb r2, [r7, #3] 8002eb6: 6879 ldr r1, [r7, #4] 8002eb8: 4613 mov r3, r2 8002eba: 011b lsls r3, r3, #4 8002ebc: 1a9b subs r3, r3, r2 8002ebe: 009b lsls r3, r3, #2 8002ec0: 440b add r3, r1 8002ec2: 3326 adds r3, #38 @ 0x26 8002ec4: 781b ldrb r3, [r3, #0] 8002ec6: 2b00 cmp r3, #0 8002ec8: d00a beq.n 8002ee0 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002eca: 78fa ldrb r2, [r7, #3] 8002ecc: 6879 ldr r1, [r7, #4] 8002ece: 4613 mov r3, r2 8002ed0: 011b lsls r3, r3, #4 8002ed2: 1a9b subs r3, r3, r2 8002ed4: 009b lsls r3, r3, #2 8002ed6: 440b add r3, r1 8002ed8: 3326 adds r3, #38 @ 0x26 8002eda: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002edc: 2b02 cmp r3, #2 8002ede: d129 bne.n 8002f34 { hhcd->hc[chnum].ErrCnt = 0U; 8002ee0: 78fa ldrb r2, [r7, #3] 8002ee2: 6879 ldr r1, [r7, #4] 8002ee4: 4613 mov r3, r2 8002ee6: 011b lsls r3, r3, #4 8002ee8: 1a9b subs r3, r3, r2 8002eea: 009b lsls r3, r3, #2 8002eec: 440b add r3, r1 8002eee: 3344 adds r3, #68 @ 0x44 8002ef0: 2200 movs r2, #0 8002ef2: 601a str r2, [r3, #0] if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) 8002ef4: 687b ldr r3, [r7, #4] 8002ef6: 799b ldrb r3, [r3, #6] 8002ef8: 2b00 cmp r3, #0 8002efa: d00a beq.n 8002f12 8002efc: 78fa ldrb r2, [r7, #3] 8002efe: 6879 ldr r1, [r7, #4] 8002f00: 4613 mov r3, r2 8002f02: 011b lsls r3, r3, #4 8002f04: 1a9b subs r3, r3, r2 8002f06: 009b lsls r3, r3, #2 8002f08: 440b add r3, r1 8002f0a: 331b adds r3, #27 8002f0c: 781b ldrb r3, [r3, #0] 8002f0e: 2b01 cmp r3, #1 8002f10: d110 bne.n 8002f34 { hhcd->hc[chnum].state = HC_NAK; 8002f12: 78fa ldrb r2, [r7, #3] 8002f14: 6879 ldr r1, [r7, #4] 8002f16: 4613 mov r3, r2 8002f18: 011b lsls r3, r3, #4 8002f1a: 1a9b subs r3, r3, r2 8002f1c: 009b lsls r3, r3, #2 8002f1e: 440b add r3, r1 8002f20: 334d adds r3, #77 @ 0x4d 8002f22: 2204 movs r2, #4 8002f24: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002f26: 687b ldr r3, [r7, #4] 8002f28: 681b ldr r3, [r3, #0] 8002f2a: 78fa ldrb r2, [r7, #3] 8002f2c: 4611 mov r1, r2 8002f2e: 4618 mov r0, r3 8002f30: f003 fbce bl 80066d0 else { /* ... */ } if (hhcd->hc[chnum].do_csplit == 1U) 8002f34: 78fa ldrb r2, [r7, #3] 8002f36: 6879 ldr r1, [r7, #4] 8002f38: 4613 mov r3, r2 8002f3a: 011b lsls r3, r3, #4 8002f3c: 1a9b subs r3, r3, r2 8002f3e: 009b lsls r3, r3, #2 8002f40: 440b add r3, r1 8002f42: 331b adds r3, #27 8002f44: 781b ldrb r3, [r3, #0] 8002f46: 2b01 cmp r3, #1 8002f48: d129 bne.n 8002f9e { hhcd->hc[chnum].do_csplit = 0U; 8002f4a: 78fa ldrb r2, [r7, #3] 8002f4c: 6879 ldr r1, [r7, #4] 8002f4e: 4613 mov r3, r2 8002f50: 011b lsls r3, r3, #4 8002f52: 1a9b subs r3, r3, r2 8002f54: 009b lsls r3, r3, #2 8002f56: 440b add r3, r1 8002f58: 331b adds r3, #27 8002f5a: 2200 movs r2, #0 8002f5c: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8002f5e: 78fb ldrb r3, [r7, #3] 8002f60: 015a lsls r2, r3, #5 8002f62: 693b ldr r3, [r7, #16] 8002f64: 4413 add r3, r2 8002f66: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002f6a: 685b ldr r3, [r3, #4] 8002f6c: 78fa ldrb r2, [r7, #3] 8002f6e: 0151 lsls r1, r2, #5 8002f70: 693a ldr r2, [r7, #16] 8002f72: 440a add r2, r1 8002f74: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002f78: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002f7c: 6053 str r3, [r2, #4] __HAL_HCD_UNMASK_ACK_HC_INT(chnum); 8002f7e: 78fb ldrb r3, [r7, #3] 8002f80: 015a lsls r2, r3, #5 8002f82: 693b ldr r3, [r7, #16] 8002f84: 4413 add r3, r2 8002f86: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002f8a: 68db ldr r3, [r3, #12] 8002f8c: 78fa ldrb r2, [r7, #3] 8002f8e: 0151 lsls r1, r2, #5 8002f90: 693a ldr r2, [r7, #16] 8002f92: 440a add r2, r1 8002f94: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002f98: f043 0320 orr.w r3, r3, #32 8002f9c: 60d3 str r3, [r2, #12] } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 8002f9e: 78fb ldrb r3, [r7, #3] 8002fa0: 015a lsls r2, r3, #5 8002fa2: 693b ldr r3, [r7, #16] 8002fa4: 4413 add r3, r2 8002fa6: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002faa: 461a mov r2, r3 8002fac: 2310 movs r3, #16 8002fae: 6093 str r3, [r2, #8] 8002fb0: e000 b.n 8002fb4 return; 8002fb2: bf00 nop } else { /* ... */ } } 8002fb4: 3718 adds r7, #24 8002fb6: 46bd mov sp, r7 8002fb8: bd80 pop {r7, pc} 08002fba : * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { 8002fba: b580 push {r7, lr} 8002fbc: b086 sub sp, #24 8002fbe: af00 add r7, sp, #0 8002fc0: 6078 str r0, [r7, #4] 8002fc2: 460b mov r3, r1 8002fc4: 70fb strb r3, [r7, #3] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 681b ldr r3, [r3, #0] 8002fca: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002fcc: 697b ldr r3, [r7, #20] 8002fce: 613b str r3, [r7, #16] uint32_t tmpreg; uint32_t num_packets; if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) 8002fd0: 687b ldr r3, [r7, #4] 8002fd2: 681b ldr r3, [r3, #0] 8002fd4: 78fa ldrb r2, [r7, #3] 8002fd6: 4611 mov r1, r2 8002fd8: 4618 mov r0, r3 8002fda: f003 fafc bl 80065d6 8002fde: 4603 mov r3, r0 8002fe0: f003 0304 and.w r3, r3, #4 8002fe4: 2b04 cmp r3, #4 8002fe6: d11b bne.n 8003020 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); 8002fe8: 78fb ldrb r3, [r7, #3] 8002fea: 015a lsls r2, r3, #5 8002fec: 693b ldr r3, [r7, #16] 8002fee: 4413 add r3, r2 8002ff0: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002ff4: 461a mov r2, r3 8002ff6: 2304 movs r3, #4 8002ff8: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 8002ffa: 78fa ldrb r2, [r7, #3] 8002ffc: 6879 ldr r1, [r7, #4] 8002ffe: 4613 mov r3, r2 8003000: 011b lsls r3, r3, #4 8003002: 1a9b subs r3, r3, r2 8003004: 009b lsls r3, r3, #2 8003006: 440b add r3, r1 8003008: 334d adds r3, #77 @ 0x4d 800300a: 2207 movs r2, #7 800300c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800300e: 687b ldr r3, [r7, #4] 8003010: 681b ldr r3, [r3, #0] 8003012: 78fa ldrb r2, [r7, #3] 8003014: 4611 mov r1, r2 8003016: 4618 mov r0, r3 8003018: f003 fb5a bl 80066d0 800301c: f000 bc89 b.w 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) 8003020: 687b ldr r3, [r7, #4] 8003022: 681b ldr r3, [r3, #0] 8003024: 78fa ldrb r2, [r7, #3] 8003026: 4611 mov r1, r2 8003028: 4618 mov r0, r3 800302a: f003 fad4 bl 80065d6 800302e: 4603 mov r3, r0 8003030: f003 0320 and.w r3, r3, #32 8003034: 2b20 cmp r3, #32 8003036: f040 8082 bne.w 800313e { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 800303a: 78fb ldrb r3, [r7, #3] 800303c: 015a lsls r2, r3, #5 800303e: 693b ldr r3, [r7, #16] 8003040: 4413 add r3, r2 8003042: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003046: 461a mov r2, r3 8003048: 2320 movs r3, #32 800304a: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_ping == 1U) 800304c: 78fa ldrb r2, [r7, #3] 800304e: 6879 ldr r1, [r7, #4] 8003050: 4613 mov r3, r2 8003052: 011b lsls r3, r3, #4 8003054: 1a9b subs r3, r3, r2 8003056: 009b lsls r3, r3, #2 8003058: 440b add r3, r1 800305a: 3319 adds r3, #25 800305c: 781b ldrb r3, [r3, #0] 800305e: 2b01 cmp r3, #1 8003060: d124 bne.n 80030ac { hhcd->hc[chnum].do_ping = 0U; 8003062: 78fa ldrb r2, [r7, #3] 8003064: 6879 ldr r1, [r7, #4] 8003066: 4613 mov r3, r2 8003068: 011b lsls r3, r3, #4 800306a: 1a9b subs r3, r3, r2 800306c: 009b lsls r3, r3, #2 800306e: 440b add r3, r1 8003070: 3319 adds r3, #25 8003072: 2200 movs r2, #0 8003074: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 8003076: 78fa ldrb r2, [r7, #3] 8003078: 6879 ldr r1, [r7, #4] 800307a: 4613 mov r3, r2 800307c: 011b lsls r3, r3, #4 800307e: 1a9b subs r3, r3, r2 8003080: 009b lsls r3, r3, #2 8003082: 440b add r3, r1 8003084: 334c adds r3, #76 @ 0x4c 8003086: 2202 movs r2, #2 8003088: 701a strb r2, [r3, #0] hhcd->hc[chnum].state = HC_ACK; 800308a: 78fa ldrb r2, [r7, #3] 800308c: 6879 ldr r1, [r7, #4] 800308e: 4613 mov r3, r2 8003090: 011b lsls r3, r3, #4 8003092: 1a9b subs r3, r3, r2 8003094: 009b lsls r3, r3, #2 8003096: 440b add r3, r1 8003098: 334d adds r3, #77 @ 0x4d 800309a: 2203 movs r2, #3 800309c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800309e: 687b ldr r3, [r7, #4] 80030a0: 681b ldr r3, [r3, #0] 80030a2: 78fa ldrb r2, [r7, #3] 80030a4: 4611 mov r1, r2 80030a6: 4618 mov r0, r3 80030a8: f003 fb12 bl 80066d0 } if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) 80030ac: 78fa ldrb r2, [r7, #3] 80030ae: 6879 ldr r1, [r7, #4] 80030b0: 4613 mov r3, r2 80030b2: 011b lsls r3, r3, #4 80030b4: 1a9b subs r3, r3, r2 80030b6: 009b lsls r3, r3, #2 80030b8: 440b add r3, r1 80030ba: 331a adds r3, #26 80030bc: 781b ldrb r3, [r3, #0] 80030be: 2b01 cmp r3, #1 80030c0: f040 8437 bne.w 8003932 80030c4: 78fa ldrb r2, [r7, #3] 80030c6: 6879 ldr r1, [r7, #4] 80030c8: 4613 mov r3, r2 80030ca: 011b lsls r3, r3, #4 80030cc: 1a9b subs r3, r3, r2 80030ce: 009b lsls r3, r3, #2 80030d0: 440b add r3, r1 80030d2: 331b adds r3, #27 80030d4: 781b ldrb r3, [r3, #0] 80030d6: 2b00 cmp r3, #0 80030d8: f040 842b bne.w 8003932 { if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) 80030dc: 78fa ldrb r2, [r7, #3] 80030de: 6879 ldr r1, [r7, #4] 80030e0: 4613 mov r3, r2 80030e2: 011b lsls r3, r3, #4 80030e4: 1a9b subs r3, r3, r2 80030e6: 009b lsls r3, r3, #2 80030e8: 440b add r3, r1 80030ea: 3326 adds r3, #38 @ 0x26 80030ec: 781b ldrb r3, [r3, #0] 80030ee: 2b01 cmp r3, #1 80030f0: d009 beq.n 8003106 { hhcd->hc[chnum].do_csplit = 1U; 80030f2: 78fa ldrb r2, [r7, #3] 80030f4: 6879 ldr r1, [r7, #4] 80030f6: 4613 mov r3, r2 80030f8: 011b lsls r3, r3, #4 80030fa: 1a9b subs r3, r3, r2 80030fc: 009b lsls r3, r3, #2 80030fe: 440b add r3, r1 8003100: 331b adds r3, #27 8003102: 2201 movs r2, #1 8003104: 701a strb r2, [r3, #0] } hhcd->hc[chnum].state = HC_ACK; 8003106: 78fa ldrb r2, [r7, #3] 8003108: 6879 ldr r1, [r7, #4] 800310a: 4613 mov r3, r2 800310c: 011b lsls r3, r3, #4 800310e: 1a9b subs r3, r3, r2 8003110: 009b lsls r3, r3, #2 8003112: 440b add r3, r1 8003114: 334d adds r3, #77 @ 0x4d 8003116: 2203 movs r2, #3 8003118: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800311a: 687b ldr r3, [r7, #4] 800311c: 681b ldr r3, [r3, #0] 800311e: 78fa ldrb r2, [r7, #3] 8003120: 4611 mov r1, r2 8003122: 4618 mov r0, r3 8003124: f003 fad4 bl 80066d0 /* reset error_count */ hhcd->hc[chnum].ErrCnt = 0U; 8003128: 78fa ldrb r2, [r7, #3] 800312a: 6879 ldr r1, [r7, #4] 800312c: 4613 mov r3, r2 800312e: 011b lsls r3, r3, #4 8003130: 1a9b subs r3, r3, r2 8003132: 009b lsls r3, r3, #2 8003134: 440b add r3, r1 8003136: 3344 adds r3, #68 @ 0x44 8003138: 2200 movs r2, #0 800313a: 601a str r2, [r3, #0] 800313c: e3f9 b.n 8003932 } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) 800313e: 687b ldr r3, [r7, #4] 8003140: 681b ldr r3, [r3, #0] 8003142: 78fa ldrb r2, [r7, #3] 8003144: 4611 mov r1, r2 8003146: 4618 mov r0, r3 8003148: f003 fa45 bl 80065d6 800314c: 4603 mov r3, r0 800314e: f403 7300 and.w r3, r3, #512 @ 0x200 8003152: f5b3 7f00 cmp.w r3, #512 @ 0x200 8003156: d111 bne.n 800317c { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); 8003158: 78fb ldrb r3, [r7, #3] 800315a: 015a lsls r2, r3, #5 800315c: 693b ldr r3, [r7, #16] 800315e: 4413 add r3, r2 8003160: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003164: 461a mov r2, r3 8003166: f44f 7300 mov.w r3, #512 @ 0x200 800316a: 6093 str r3, [r2, #8] (void)USB_HC_Halt(hhcd->Instance, chnum); 800316c: 687b ldr r3, [r7, #4] 800316e: 681b ldr r3, [r3, #0] 8003170: 78fa ldrb r2, [r7, #3] 8003172: 4611 mov r1, r2 8003174: 4618 mov r0, r3 8003176: f003 faab bl 80066d0 800317a: e3da b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) 800317c: 687b ldr r3, [r7, #4] 800317e: 681b ldr r3, [r3, #0] 8003180: 78fa ldrb r2, [r7, #3] 8003182: 4611 mov r1, r2 8003184: 4618 mov r0, r3 8003186: f003 fa26 bl 80065d6 800318a: 4603 mov r3, r0 800318c: f003 0301 and.w r3, r3, #1 8003190: 2b01 cmp r3, #1 8003192: d168 bne.n 8003266 { hhcd->hc[chnum].ErrCnt = 0U; 8003194: 78fa ldrb r2, [r7, #3] 8003196: 6879 ldr r1, [r7, #4] 8003198: 4613 mov r3, r2 800319a: 011b lsls r3, r3, #4 800319c: 1a9b subs r3, r3, r2 800319e: 009b lsls r3, r3, #2 80031a0: 440b add r3, r1 80031a2: 3344 adds r3, #68 @ 0x44 80031a4: 2200 movs r2, #0 80031a6: 601a str r2, [r3, #0] /* transaction completed with NYET state, update do ping state */ if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 80031a8: 687b ldr r3, [r7, #4] 80031aa: 681b ldr r3, [r3, #0] 80031ac: 78fa ldrb r2, [r7, #3] 80031ae: 4611 mov r1, r2 80031b0: 4618 mov r0, r3 80031b2: f003 fa10 bl 80065d6 80031b6: 4603 mov r3, r0 80031b8: f003 0340 and.w r3, r3, #64 @ 0x40 80031bc: 2b40 cmp r3, #64 @ 0x40 80031be: d112 bne.n 80031e6 { hhcd->hc[chnum].do_ping = 1U; 80031c0: 78fa ldrb r2, [r7, #3] 80031c2: 6879 ldr r1, [r7, #4] 80031c4: 4613 mov r3, r2 80031c6: 011b lsls r3, r3, #4 80031c8: 1a9b subs r3, r3, r2 80031ca: 009b lsls r3, r3, #2 80031cc: 440b add r3, r1 80031ce: 3319 adds r3, #25 80031d0: 2201 movs r2, #1 80031d2: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 80031d4: 78fb ldrb r3, [r7, #3] 80031d6: 015a lsls r2, r3, #5 80031d8: 693b ldr r3, [r7, #16] 80031da: 4413 add r3, r2 80031dc: f503 63a0 add.w r3, r3, #1280 @ 0x500 80031e0: 461a mov r2, r3 80031e2: 2340 movs r3, #64 @ 0x40 80031e4: 6093 str r3, [r2, #8] } if (hhcd->hc[chnum].do_csplit != 0U) 80031e6: 78fa ldrb r2, [r7, #3] 80031e8: 6879 ldr r1, [r7, #4] 80031ea: 4613 mov r3, r2 80031ec: 011b lsls r3, r3, #4 80031ee: 1a9b subs r3, r3, r2 80031f0: 009b lsls r3, r3, #2 80031f2: 440b add r3, r1 80031f4: 331b adds r3, #27 80031f6: 781b ldrb r3, [r3, #0] 80031f8: 2b00 cmp r3, #0 80031fa: d019 beq.n 8003230 { hhcd->hc[chnum].do_csplit = 0U; 80031fc: 78fa ldrb r2, [r7, #3] 80031fe: 6879 ldr r1, [r7, #4] 8003200: 4613 mov r3, r2 8003202: 011b lsls r3, r3, #4 8003204: 1a9b subs r3, r3, r2 8003206: 009b lsls r3, r3, #2 8003208: 440b add r3, r1 800320a: 331b adds r3, #27 800320c: 2200 movs r2, #0 800320e: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8003210: 78fb ldrb r3, [r7, #3] 8003212: 015a lsls r2, r3, #5 8003214: 693b ldr r3, [r7, #16] 8003216: 4413 add r3, r2 8003218: f503 63a0 add.w r3, r3, #1280 @ 0x500 800321c: 685b ldr r3, [r3, #4] 800321e: 78fa ldrb r2, [r7, #3] 8003220: 0151 lsls r1, r2, #5 8003222: 693a ldr r2, [r7, #16] 8003224: 440a add r2, r1 8003226: f502 62a0 add.w r2, r2, #1280 @ 0x500 800322a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800322e: 6053 str r3, [r2, #4] } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); 8003230: 78fb ldrb r3, [r7, #3] 8003232: 015a lsls r2, r3, #5 8003234: 693b ldr r3, [r7, #16] 8003236: 4413 add r3, r2 8003238: f503 63a0 add.w r3, r3, #1280 @ 0x500 800323c: 461a mov r2, r3 800323e: 2301 movs r3, #1 8003240: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XFRC; 8003242: 78fa ldrb r2, [r7, #3] 8003244: 6879 ldr r1, [r7, #4] 8003246: 4613 mov r3, r2 8003248: 011b lsls r3, r3, #4 800324a: 1a9b subs r3, r3, r2 800324c: 009b lsls r3, r3, #2 800324e: 440b add r3, r1 8003250: 334d adds r3, #77 @ 0x4d 8003252: 2201 movs r2, #1 8003254: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003256: 687b ldr r3, [r7, #4] 8003258: 681b ldr r3, [r3, #0] 800325a: 78fa ldrb r2, [r7, #3] 800325c: 4611 mov r1, r2 800325e: 4618 mov r0, r3 8003260: f003 fa36 bl 80066d0 8003264: e365 b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 8003266: 687b ldr r3, [r7, #4] 8003268: 681b ldr r3, [r3, #0] 800326a: 78fa ldrb r2, [r7, #3] 800326c: 4611 mov r1, r2 800326e: 4618 mov r0, r3 8003270: f003 f9b1 bl 80065d6 8003274: 4603 mov r3, r0 8003276: f003 0340 and.w r3, r3, #64 @ 0x40 800327a: 2b40 cmp r3, #64 @ 0x40 800327c: d139 bne.n 80032f2 { hhcd->hc[chnum].state = HC_NYET; 800327e: 78fa ldrb r2, [r7, #3] 8003280: 6879 ldr r1, [r7, #4] 8003282: 4613 mov r3, r2 8003284: 011b lsls r3, r3, #4 8003286: 1a9b subs r3, r3, r2 8003288: 009b lsls r3, r3, #2 800328a: 440b add r3, r1 800328c: 334d adds r3, #77 @ 0x4d 800328e: 2205 movs r2, #5 8003290: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 0U) 8003292: 78fa ldrb r2, [r7, #3] 8003294: 6879 ldr r1, [r7, #4] 8003296: 4613 mov r3, r2 8003298: 011b lsls r3, r3, #4 800329a: 1a9b subs r3, r3, r2 800329c: 009b lsls r3, r3, #2 800329e: 440b add r3, r1 80032a0: 331a adds r3, #26 80032a2: 781b ldrb r3, [r3, #0] 80032a4: 2b00 cmp r3, #0 80032a6: d109 bne.n 80032bc { hhcd->hc[chnum].do_ping = 1U; 80032a8: 78fa ldrb r2, [r7, #3] 80032aa: 6879 ldr r1, [r7, #4] 80032ac: 4613 mov r3, r2 80032ae: 011b lsls r3, r3, #4 80032b0: 1a9b subs r3, r3, r2 80032b2: 009b lsls r3, r3, #2 80032b4: 440b add r3, r1 80032b6: 3319 adds r3, #25 80032b8: 2201 movs r2, #1 80032ba: 701a strb r2, [r3, #0] } hhcd->hc[chnum].ErrCnt = 0U; 80032bc: 78fa ldrb r2, [r7, #3] 80032be: 6879 ldr r1, [r7, #4] 80032c0: 4613 mov r3, r2 80032c2: 011b lsls r3, r3, #4 80032c4: 1a9b subs r3, r3, r2 80032c6: 009b lsls r3, r3, #2 80032c8: 440b add r3, r1 80032ca: 3344 adds r3, #68 @ 0x44 80032cc: 2200 movs r2, #0 80032ce: 601a str r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80032d0: 687b ldr r3, [r7, #4] 80032d2: 681b ldr r3, [r3, #0] 80032d4: 78fa ldrb r2, [r7, #3] 80032d6: 4611 mov r1, r2 80032d8: 4618 mov r0, r3 80032da: f003 f9f9 bl 80066d0 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 80032de: 78fb ldrb r3, [r7, #3] 80032e0: 015a lsls r2, r3, #5 80032e2: 693b ldr r3, [r7, #16] 80032e4: 4413 add r3, r2 80032e6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80032ea: 461a mov r2, r3 80032ec: 2340 movs r3, #64 @ 0x40 80032ee: 6093 str r3, [r2, #8] 80032f0: e31f b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) 80032f2: 687b ldr r3, [r7, #4] 80032f4: 681b ldr r3, [r3, #0] 80032f6: 78fa ldrb r2, [r7, #3] 80032f8: 4611 mov r1, r2 80032fa: 4618 mov r0, r3 80032fc: f003 f96b bl 80065d6 8003300: 4603 mov r3, r0 8003302: f003 0308 and.w r3, r3, #8 8003306: 2b08 cmp r3, #8 8003308: d11a bne.n 8003340 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); 800330a: 78fb ldrb r3, [r7, #3] 800330c: 015a lsls r2, r3, #5 800330e: 693b ldr r3, [r7, #16] 8003310: 4413 add r3, r2 8003312: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003316: 461a mov r2, r3 8003318: 2308 movs r3, #8 800331a: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_STALL; 800331c: 78fa ldrb r2, [r7, #3] 800331e: 6879 ldr r1, [r7, #4] 8003320: 4613 mov r3, r2 8003322: 011b lsls r3, r3, #4 8003324: 1a9b subs r3, r3, r2 8003326: 009b lsls r3, r3, #2 8003328: 440b add r3, r1 800332a: 334d adds r3, #77 @ 0x4d 800332c: 2206 movs r2, #6 800332e: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003330: 687b ldr r3, [r7, #4] 8003332: 681b ldr r3, [r3, #0] 8003334: 78fa ldrb r2, [r7, #3] 8003336: 4611 mov r1, r2 8003338: 4618 mov r0, r3 800333a: f003 f9c9 bl 80066d0 800333e: e2f8 b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) 8003340: 687b ldr r3, [r7, #4] 8003342: 681b ldr r3, [r3, #0] 8003344: 78fa ldrb r2, [r7, #3] 8003346: 4611 mov r1, r2 8003348: 4618 mov r0, r3 800334a: f003 f944 bl 80065d6 800334e: 4603 mov r3, r0 8003350: f003 0310 and.w r3, r3, #16 8003354: 2b10 cmp r3, #16 8003356: d144 bne.n 80033e2 { hhcd->hc[chnum].ErrCnt = 0U; 8003358: 78fa ldrb r2, [r7, #3] 800335a: 6879 ldr r1, [r7, #4] 800335c: 4613 mov r3, r2 800335e: 011b lsls r3, r3, #4 8003360: 1a9b subs r3, r3, r2 8003362: 009b lsls r3, r3, #2 8003364: 440b add r3, r1 8003366: 3344 adds r3, #68 @ 0x44 8003368: 2200 movs r2, #0 800336a: 601a str r2, [r3, #0] hhcd->hc[chnum].state = HC_NAK; 800336c: 78fa ldrb r2, [r7, #3] 800336e: 6879 ldr r1, [r7, #4] 8003370: 4613 mov r3, r2 8003372: 011b lsls r3, r3, #4 8003374: 1a9b subs r3, r3, r2 8003376: 009b lsls r3, r3, #2 8003378: 440b add r3, r1 800337a: 334d adds r3, #77 @ 0x4d 800337c: 2204 movs r2, #4 800337e: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ping == 0U) 8003380: 78fa ldrb r2, [r7, #3] 8003382: 6879 ldr r1, [r7, #4] 8003384: 4613 mov r3, r2 8003386: 011b lsls r3, r3, #4 8003388: 1a9b subs r3, r3, r2 800338a: 009b lsls r3, r3, #2 800338c: 440b add r3, r1 800338e: 3319 adds r3, #25 8003390: 781b ldrb r3, [r3, #0] 8003392: 2b00 cmp r3, #0 8003394: d114 bne.n 80033c0 { if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) 8003396: 78fa ldrb r2, [r7, #3] 8003398: 6879 ldr r1, [r7, #4] 800339a: 4613 mov r3, r2 800339c: 011b lsls r3, r3, #4 800339e: 1a9b subs r3, r3, r2 80033a0: 009b lsls r3, r3, #2 80033a2: 440b add r3, r1 80033a4: 3318 adds r3, #24 80033a6: 781b ldrb r3, [r3, #0] 80033a8: 2b00 cmp r3, #0 80033aa: d109 bne.n 80033c0 { hhcd->hc[chnum].do_ping = 1U; 80033ac: 78fa ldrb r2, [r7, #3] 80033ae: 6879 ldr r1, [r7, #4] 80033b0: 4613 mov r3, r2 80033b2: 011b lsls r3, r3, #4 80033b4: 1a9b subs r3, r3, r2 80033b6: 009b lsls r3, r3, #2 80033b8: 440b add r3, r1 80033ba: 3319 adds r3, #25 80033bc: 2201 movs r2, #1 80033be: 701a strb r2, [r3, #0] } } (void)USB_HC_Halt(hhcd->Instance, chnum); 80033c0: 687b ldr r3, [r7, #4] 80033c2: 681b ldr r3, [r3, #0] 80033c4: 78fa ldrb r2, [r7, #3] 80033c6: 4611 mov r1, r2 80033c8: 4618 mov r0, r3 80033ca: f003 f981 bl 80066d0 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 80033ce: 78fb ldrb r3, [r7, #3] 80033d0: 015a lsls r2, r3, #5 80033d2: 693b ldr r3, [r7, #16] 80033d4: 4413 add r3, r2 80033d6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80033da: 461a mov r2, r3 80033dc: 2310 movs r3, #16 80033de: 6093 str r3, [r2, #8] 80033e0: e2a7 b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) 80033e2: 687b ldr r3, [r7, #4] 80033e4: 681b ldr r3, [r3, #0] 80033e6: 78fa ldrb r2, [r7, #3] 80033e8: 4611 mov r1, r2 80033ea: 4618 mov r0, r3 80033ec: f003 f8f3 bl 80065d6 80033f0: 4603 mov r3, r0 80033f2: f003 0380 and.w r3, r3, #128 @ 0x80 80033f6: 2b80 cmp r3, #128 @ 0x80 80033f8: f040 8083 bne.w 8003502 { if (hhcd->Init.dma_enable == 0U) 80033fc: 687b ldr r3, [r7, #4] 80033fe: 799b ldrb r3, [r3, #6] 8003400: 2b00 cmp r3, #0 8003402: d111 bne.n 8003428 { hhcd->hc[chnum].state = HC_XACTERR; 8003404: 78fa ldrb r2, [r7, #3] 8003406: 6879 ldr r1, [r7, #4] 8003408: 4613 mov r3, r2 800340a: 011b lsls r3, r3, #4 800340c: 1a9b subs r3, r3, r2 800340e: 009b lsls r3, r3, #2 8003410: 440b add r3, r1 8003412: 334d adds r3, #77 @ 0x4d 8003414: 2207 movs r2, #7 8003416: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003418: 687b ldr r3, [r7, #4] 800341a: 681b ldr r3, [r3, #0] 800341c: 78fa ldrb r2, [r7, #3] 800341e: 4611 mov r1, r2 8003420: 4618 mov r0, r3 8003422: f003 f955 bl 80066d0 8003426: e062 b.n 80034ee } else { hhcd->hc[chnum].ErrCnt++; 8003428: 78fa ldrb r2, [r7, #3] 800342a: 6879 ldr r1, [r7, #4] 800342c: 4613 mov r3, r2 800342e: 011b lsls r3, r3, #4 8003430: 1a9b subs r3, r3, r2 8003432: 009b lsls r3, r3, #2 8003434: 440b add r3, r1 8003436: 3344 adds r3, #68 @ 0x44 8003438: 681b ldr r3, [r3, #0] 800343a: 1c59 adds r1, r3, #1 800343c: 6878 ldr r0, [r7, #4] 800343e: 4613 mov r3, r2 8003440: 011b lsls r3, r3, #4 8003442: 1a9b subs r3, r3, r2 8003444: 009b lsls r3, r3, #2 8003446: 4403 add r3, r0 8003448: 3344 adds r3, #68 @ 0x44 800344a: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800344c: 78fa ldrb r2, [r7, #3] 800344e: 6879 ldr r1, [r7, #4] 8003450: 4613 mov r3, r2 8003452: 011b lsls r3, r3, #4 8003454: 1a9b subs r3, r3, r2 8003456: 009b lsls r3, r3, #2 8003458: 440b add r3, r1 800345a: 3344 adds r3, #68 @ 0x44 800345c: 681b ldr r3, [r3, #0] 800345e: 2b02 cmp r3, #2 8003460: d922 bls.n 80034a8 { hhcd->hc[chnum].ErrCnt = 0U; 8003462: 78fa ldrb r2, [r7, #3] 8003464: 6879 ldr r1, [r7, #4] 8003466: 4613 mov r3, r2 8003468: 011b lsls r3, r3, #4 800346a: 1a9b subs r3, r3, r2 800346c: 009b lsls r3, r3, #2 800346e: 440b add r3, r1 8003470: 3344 adds r3, #68 @ 0x44 8003472: 2200 movs r2, #0 8003474: 601a str r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 8003476: 78fa ldrb r2, [r7, #3] 8003478: 6879 ldr r1, [r7, #4] 800347a: 4613 mov r3, r2 800347c: 011b lsls r3, r3, #4 800347e: 1a9b subs r3, r3, r2 8003480: 009b lsls r3, r3, #2 8003482: 440b add r3, r1 8003484: 334c adds r3, #76 @ 0x4c 8003486: 2204 movs r2, #4 8003488: 701a strb r2, [r3, #0] #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 800348a: 78fa ldrb r2, [r7, #3] 800348c: 6879 ldr r1, [r7, #4] 800348e: 4613 mov r3, r2 8003490: 011b lsls r3, r3, #4 8003492: 1a9b subs r3, r3, r2 8003494: 009b lsls r3, r3, #2 8003496: 440b add r3, r1 8003498: 334c adds r3, #76 @ 0x4c 800349a: 781a ldrb r2, [r3, #0] 800349c: 78fb ldrb r3, [r7, #3] 800349e: 4619 mov r1, r3 80034a0: 6878 ldr r0, [r7, #4] 80034a2: f004 fca7 bl 8007df4 80034a6: e022 b.n 80034ee #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 80034a8: 78fa ldrb r2, [r7, #3] 80034aa: 6879 ldr r1, [r7, #4] 80034ac: 4613 mov r3, r2 80034ae: 011b lsls r3, r3, #4 80034b0: 1a9b subs r3, r3, r2 80034b2: 009b lsls r3, r3, #2 80034b4: 440b add r3, r1 80034b6: 334c adds r3, #76 @ 0x4c 80034b8: 2202 movs r2, #2 80034ba: 701a strb r2, [r3, #0] /* Re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 80034bc: 78fb ldrb r3, [r7, #3] 80034be: 015a lsls r2, r3, #5 80034c0: 693b ldr r3, [r7, #16] 80034c2: 4413 add r3, r2 80034c4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80034c8: 681b ldr r3, [r3, #0] 80034ca: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 80034cc: 68fb ldr r3, [r7, #12] 80034ce: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80034d2: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 80034d4: 68fb ldr r3, [r7, #12] 80034d6: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80034da: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 80034dc: 78fb ldrb r3, [r7, #3] 80034de: 015a lsls r2, r3, #5 80034e0: 693b ldr r3, [r7, #16] 80034e2: 4413 add r3, r2 80034e4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80034e8: 461a mov r2, r3 80034ea: 68fb ldr r3, [r7, #12] 80034ec: 6013 str r3, [r2, #0] } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); 80034ee: 78fb ldrb r3, [r7, #3] 80034f0: 015a lsls r2, r3, #5 80034f2: 693b ldr r3, [r7, #16] 80034f4: 4413 add r3, r2 80034f6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80034fa: 461a mov r2, r3 80034fc: 2380 movs r3, #128 @ 0x80 80034fe: 6093 str r3, [r2, #8] 8003500: e217 b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) 8003502: 687b ldr r3, [r7, #4] 8003504: 681b ldr r3, [r3, #0] 8003506: 78fa ldrb r2, [r7, #3] 8003508: 4611 mov r1, r2 800350a: 4618 mov r0, r3 800350c: f003 f863 bl 80065d6 8003510: 4603 mov r3, r0 8003512: f403 6380 and.w r3, r3, #1024 @ 0x400 8003516: f5b3 6f80 cmp.w r3, #1024 @ 0x400 800351a: d11b bne.n 8003554 { hhcd->hc[chnum].state = HC_DATATGLERR; 800351c: 78fa ldrb r2, [r7, #3] 800351e: 6879 ldr r1, [r7, #4] 8003520: 4613 mov r3, r2 8003522: 011b lsls r3, r3, #4 8003524: 1a9b subs r3, r3, r2 8003526: 009b lsls r3, r3, #2 8003528: 440b add r3, r1 800352a: 334d adds r3, #77 @ 0x4d 800352c: 2209 movs r2, #9 800352e: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003530: 687b ldr r3, [r7, #4] 8003532: 681b ldr r3, [r3, #0] 8003534: 78fa ldrb r2, [r7, #3] 8003536: 4611 mov r1, r2 8003538: 4618 mov r0, r3 800353a: f003 f8c9 bl 80066d0 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); 800353e: 78fb ldrb r3, [r7, #3] 8003540: 015a lsls r2, r3, #5 8003542: 693b ldr r3, [r7, #16] 8003544: 4413 add r3, r2 8003546: f503 63a0 add.w r3, r3, #1280 @ 0x500 800354a: 461a mov r2, r3 800354c: f44f 6380 mov.w r3, #1024 @ 0x400 8003550: 6093 str r3, [r2, #8] 8003552: e1ee b.n 8003932 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) 8003554: 687b ldr r3, [r7, #4] 8003556: 681b ldr r3, [r3, #0] 8003558: 78fa ldrb r2, [r7, #3] 800355a: 4611 mov r1, r2 800355c: 4618 mov r0, r3 800355e: f003 f83a bl 80065d6 8003562: 4603 mov r3, r0 8003564: f003 0302 and.w r3, r3, #2 8003568: 2b02 cmp r3, #2 800356a: f040 81df bne.w 800392c { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); 800356e: 78fb ldrb r3, [r7, #3] 8003570: 015a lsls r2, r3, #5 8003572: 693b ldr r3, [r7, #16] 8003574: 4413 add r3, r2 8003576: f503 63a0 add.w r3, r3, #1280 @ 0x500 800357a: 461a mov r2, r3 800357c: 2302 movs r3, #2 800357e: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].state == HC_XFRC) 8003580: 78fa ldrb r2, [r7, #3] 8003582: 6879 ldr r1, [r7, #4] 8003584: 4613 mov r3, r2 8003586: 011b lsls r3, r3, #4 8003588: 1a9b subs r3, r3, r2 800358a: 009b lsls r3, r3, #2 800358c: 440b add r3, r1 800358e: 334d adds r3, #77 @ 0x4d 8003590: 781b ldrb r3, [r3, #0] 8003592: 2b01 cmp r3, #1 8003594: f040 8093 bne.w 80036be { hhcd->hc[chnum].state = HC_HALTED; 8003598: 78fa ldrb r2, [r7, #3] 800359a: 6879 ldr r1, [r7, #4] 800359c: 4613 mov r3, r2 800359e: 011b lsls r3, r3, #4 80035a0: 1a9b subs r3, r3, r2 80035a2: 009b lsls r3, r3, #2 80035a4: 440b add r3, r1 80035a6: 334d adds r3, #77 @ 0x4d 80035a8: 2202 movs r2, #2 80035aa: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_DONE; 80035ac: 78fa ldrb r2, [r7, #3] 80035ae: 6879 ldr r1, [r7, #4] 80035b0: 4613 mov r3, r2 80035b2: 011b lsls r3, r3, #4 80035b4: 1a9b subs r3, r3, r2 80035b6: 009b lsls r3, r3, #2 80035b8: 440b add r3, r1 80035ba: 334c adds r3, #76 @ 0x4c 80035bc: 2201 movs r2, #1 80035be: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || 80035c0: 78fa ldrb r2, [r7, #3] 80035c2: 6879 ldr r1, [r7, #4] 80035c4: 4613 mov r3, r2 80035c6: 011b lsls r3, r3, #4 80035c8: 1a9b subs r3, r3, r2 80035ca: 009b lsls r3, r3, #2 80035cc: 440b add r3, r1 80035ce: 3326 adds r3, #38 @ 0x26 80035d0: 781b ldrb r3, [r3, #0] 80035d2: 2b02 cmp r3, #2 80035d4: d00b beq.n 80035ee (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) 80035d6: 78fa ldrb r2, [r7, #3] 80035d8: 6879 ldr r1, [r7, #4] 80035da: 4613 mov r3, r2 80035dc: 011b lsls r3, r3, #4 80035de: 1a9b subs r3, r3, r2 80035e0: 009b lsls r3, r3, #2 80035e2: 440b add r3, r1 80035e4: 3326 adds r3, #38 @ 0x26 80035e6: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || 80035e8: 2b03 cmp r3, #3 80035ea: f040 8190 bne.w 800390e { if (hhcd->Init.dma_enable == 0U) 80035ee: 687b ldr r3, [r7, #4] 80035f0: 799b ldrb r3, [r3, #6] 80035f2: 2b00 cmp r3, #0 80035f4: d115 bne.n 8003622 { hhcd->hc[chnum].toggle_out ^= 1U; 80035f6: 78fa ldrb r2, [r7, #3] 80035f8: 6879 ldr r1, [r7, #4] 80035fa: 4613 mov r3, r2 80035fc: 011b lsls r3, r3, #4 80035fe: 1a9b subs r3, r3, r2 8003600: 009b lsls r3, r3, #2 8003602: 440b add r3, r1 8003604: 333d adds r3, #61 @ 0x3d 8003606: 781b ldrb r3, [r3, #0] 8003608: 78fa ldrb r2, [r7, #3] 800360a: f083 0301 eor.w r3, r3, #1 800360e: b2d8 uxtb r0, r3 8003610: 6879 ldr r1, [r7, #4] 8003612: 4613 mov r3, r2 8003614: 011b lsls r3, r3, #4 8003616: 1a9b subs r3, r3, r2 8003618: 009b lsls r3, r3, #2 800361a: 440b add r3, r1 800361c: 333d adds r3, #61 @ 0x3d 800361e: 4602 mov r2, r0 8003620: 701a strb r2, [r3, #0] } if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) 8003622: 687b ldr r3, [r7, #4] 8003624: 799b ldrb r3, [r3, #6] 8003626: 2b01 cmp r3, #1 8003628: f040 8171 bne.w 800390e 800362c: 78fa ldrb r2, [r7, #3] 800362e: 6879 ldr r1, [r7, #4] 8003630: 4613 mov r3, r2 8003632: 011b lsls r3, r3, #4 8003634: 1a9b subs r3, r3, r2 8003636: 009b lsls r3, r3, #2 8003638: 440b add r3, r1 800363a: 3334 adds r3, #52 @ 0x34 800363c: 681b ldr r3, [r3, #0] 800363e: 2b00 cmp r3, #0 8003640: f000 8165 beq.w 800390e { num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; 8003644: 78fa ldrb r2, [r7, #3] 8003646: 6879 ldr r1, [r7, #4] 8003648: 4613 mov r3, r2 800364a: 011b lsls r3, r3, #4 800364c: 1a9b subs r3, r3, r2 800364e: 009b lsls r3, r3, #2 8003650: 440b add r3, r1 8003652: 3334 adds r3, #52 @ 0x34 8003654: 6819 ldr r1, [r3, #0] 8003656: 78fa ldrb r2, [r7, #3] 8003658: 6878 ldr r0, [r7, #4] 800365a: 4613 mov r3, r2 800365c: 011b lsls r3, r3, #4 800365e: 1a9b subs r3, r3, r2 8003660: 009b lsls r3, r3, #2 8003662: 4403 add r3, r0 8003664: 3328 adds r3, #40 @ 0x28 8003666: 881b ldrh r3, [r3, #0] 8003668: 440b add r3, r1 800366a: 1e59 subs r1, r3, #1 800366c: 78fa ldrb r2, [r7, #3] 800366e: 6878 ldr r0, [r7, #4] 8003670: 4613 mov r3, r2 8003672: 011b lsls r3, r3, #4 8003674: 1a9b subs r3, r3, r2 8003676: 009b lsls r3, r3, #2 8003678: 4403 add r3, r0 800367a: 3328 adds r3, #40 @ 0x28 800367c: 881b ldrh r3, [r3, #0] 800367e: fbb1 f3f3 udiv r3, r1, r3 8003682: 60bb str r3, [r7, #8] if ((num_packets & 1U) != 0U) 8003684: 68bb ldr r3, [r7, #8] 8003686: f003 0301 and.w r3, r3, #1 800368a: 2b00 cmp r3, #0 800368c: f000 813f beq.w 800390e { hhcd->hc[chnum].toggle_out ^= 1U; 8003690: 78fa ldrb r2, [r7, #3] 8003692: 6879 ldr r1, [r7, #4] 8003694: 4613 mov r3, r2 8003696: 011b lsls r3, r3, #4 8003698: 1a9b subs r3, r3, r2 800369a: 009b lsls r3, r3, #2 800369c: 440b add r3, r1 800369e: 333d adds r3, #61 @ 0x3d 80036a0: 781b ldrb r3, [r3, #0] 80036a2: 78fa ldrb r2, [r7, #3] 80036a4: f083 0301 eor.w r3, r3, #1 80036a8: b2d8 uxtb r0, r3 80036aa: 6879 ldr r1, [r7, #4] 80036ac: 4613 mov r3, r2 80036ae: 011b lsls r3, r3, #4 80036b0: 1a9b subs r3, r3, r2 80036b2: 009b lsls r3, r3, #2 80036b4: 440b add r3, r1 80036b6: 333d adds r3, #61 @ 0x3d 80036b8: 4602 mov r2, r0 80036ba: 701a strb r2, [r3, #0] 80036bc: e127 b.n 800390e } } } } else if (hhcd->hc[chnum].state == HC_ACK) 80036be: 78fa ldrb r2, [r7, #3] 80036c0: 6879 ldr r1, [r7, #4] 80036c2: 4613 mov r3, r2 80036c4: 011b lsls r3, r3, #4 80036c6: 1a9b subs r3, r3, r2 80036c8: 009b lsls r3, r3, #2 80036ca: 440b add r3, r1 80036cc: 334d adds r3, #77 @ 0x4d 80036ce: 781b ldrb r3, [r3, #0] 80036d0: 2b03 cmp r3, #3 80036d2: d120 bne.n 8003716 { hhcd->hc[chnum].state = HC_HALTED; 80036d4: 78fa ldrb r2, [r7, #3] 80036d6: 6879 ldr r1, [r7, #4] 80036d8: 4613 mov r3, r2 80036da: 011b lsls r3, r3, #4 80036dc: 1a9b subs r3, r3, r2 80036de: 009b lsls r3, r3, #2 80036e0: 440b add r3, r1 80036e2: 334d adds r3, #77 @ 0x4d 80036e4: 2202 movs r2, #2 80036e6: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 80036e8: 78fa ldrb r2, [r7, #3] 80036ea: 6879 ldr r1, [r7, #4] 80036ec: 4613 mov r3, r2 80036ee: 011b lsls r3, r3, #4 80036f0: 1a9b subs r3, r3, r2 80036f2: 009b lsls r3, r3, #2 80036f4: 440b add r3, r1 80036f6: 331b adds r3, #27 80036f8: 781b ldrb r3, [r3, #0] 80036fa: 2b01 cmp r3, #1 80036fc: f040 8107 bne.w 800390e { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8003700: 78fa ldrb r2, [r7, #3] 8003702: 6879 ldr r1, [r7, #4] 8003704: 4613 mov r3, r2 8003706: 011b lsls r3, r3, #4 8003708: 1a9b subs r3, r3, r2 800370a: 009b lsls r3, r3, #2 800370c: 440b add r3, r1 800370e: 334c adds r3, #76 @ 0x4c 8003710: 2202 movs r2, #2 8003712: 701a strb r2, [r3, #0] 8003714: e0fb b.n 800390e } } else if (hhcd->hc[chnum].state == HC_NAK) 8003716: 78fa ldrb r2, [r7, #3] 8003718: 6879 ldr r1, [r7, #4] 800371a: 4613 mov r3, r2 800371c: 011b lsls r3, r3, #4 800371e: 1a9b subs r3, r3, r2 8003720: 009b lsls r3, r3, #2 8003722: 440b add r3, r1 8003724: 334d adds r3, #77 @ 0x4d 8003726: 781b ldrb r3, [r3, #0] 8003728: 2b04 cmp r3, #4 800372a: d13a bne.n 80037a2 { hhcd->hc[chnum].state = HC_HALTED; 800372c: 78fa ldrb r2, [r7, #3] 800372e: 6879 ldr r1, [r7, #4] 8003730: 4613 mov r3, r2 8003732: 011b lsls r3, r3, #4 8003734: 1a9b subs r3, r3, r2 8003736: 009b lsls r3, r3, #2 8003738: 440b add r3, r1 800373a: 334d adds r3, #77 @ 0x4d 800373c: 2202 movs r2, #2 800373e: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 8003740: 78fa ldrb r2, [r7, #3] 8003742: 6879 ldr r1, [r7, #4] 8003744: 4613 mov r3, r2 8003746: 011b lsls r3, r3, #4 8003748: 1a9b subs r3, r3, r2 800374a: 009b lsls r3, r3, #2 800374c: 440b add r3, r1 800374e: 334c adds r3, #76 @ 0x4c 8003750: 2202 movs r2, #2 8003752: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 8003754: 78fa ldrb r2, [r7, #3] 8003756: 6879 ldr r1, [r7, #4] 8003758: 4613 mov r3, r2 800375a: 011b lsls r3, r3, #4 800375c: 1a9b subs r3, r3, r2 800375e: 009b lsls r3, r3, #2 8003760: 440b add r3, r1 8003762: 331b adds r3, #27 8003764: 781b ldrb r3, [r3, #0] 8003766: 2b01 cmp r3, #1 8003768: f040 80d1 bne.w 800390e { hhcd->hc[chnum].do_csplit = 0U; 800376c: 78fa ldrb r2, [r7, #3] 800376e: 6879 ldr r1, [r7, #4] 8003770: 4613 mov r3, r2 8003772: 011b lsls r3, r3, #4 8003774: 1a9b subs r3, r3, r2 8003776: 009b lsls r3, r3, #2 8003778: 440b add r3, r1 800377a: 331b adds r3, #27 800377c: 2200 movs r2, #0 800377e: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8003780: 78fb ldrb r3, [r7, #3] 8003782: 015a lsls r2, r3, #5 8003784: 693b ldr r3, [r7, #16] 8003786: 4413 add r3, r2 8003788: f503 63a0 add.w r3, r3, #1280 @ 0x500 800378c: 685b ldr r3, [r3, #4] 800378e: 78fa ldrb r2, [r7, #3] 8003790: 0151 lsls r1, r2, #5 8003792: 693a ldr r2, [r7, #16] 8003794: 440a add r2, r1 8003796: f502 62a0 add.w r2, r2, #1280 @ 0x500 800379a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800379e: 6053 str r3, [r2, #4] 80037a0: e0b5 b.n 800390e } } else if (hhcd->hc[chnum].state == HC_NYET) 80037a2: 78fa ldrb r2, [r7, #3] 80037a4: 6879 ldr r1, [r7, #4] 80037a6: 4613 mov r3, r2 80037a8: 011b lsls r3, r3, #4 80037aa: 1a9b subs r3, r3, r2 80037ac: 009b lsls r3, r3, #2 80037ae: 440b add r3, r1 80037b0: 334d adds r3, #77 @ 0x4d 80037b2: 781b ldrb r3, [r3, #0] 80037b4: 2b05 cmp r3, #5 80037b6: d114 bne.n 80037e2 { hhcd->hc[chnum].state = HC_HALTED; 80037b8: 78fa ldrb r2, [r7, #3] 80037ba: 6879 ldr r1, [r7, #4] 80037bc: 4613 mov r3, r2 80037be: 011b lsls r3, r3, #4 80037c0: 1a9b subs r3, r3, r2 80037c2: 009b lsls r3, r3, #2 80037c4: 440b add r3, r1 80037c6: 334d adds r3, #77 @ 0x4d 80037c8: 2202 movs r2, #2 80037ca: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 80037cc: 78fa ldrb r2, [r7, #3] 80037ce: 6879 ldr r1, [r7, #4] 80037d0: 4613 mov r3, r2 80037d2: 011b lsls r3, r3, #4 80037d4: 1a9b subs r3, r3, r2 80037d6: 009b lsls r3, r3, #2 80037d8: 440b add r3, r1 80037da: 334c adds r3, #76 @ 0x4c 80037dc: 2202 movs r2, #2 80037de: 701a strb r2, [r3, #0] 80037e0: e095 b.n 800390e } else if (hhcd->hc[chnum].state == HC_STALL) 80037e2: 78fa ldrb r2, [r7, #3] 80037e4: 6879 ldr r1, [r7, #4] 80037e6: 4613 mov r3, r2 80037e8: 011b lsls r3, r3, #4 80037ea: 1a9b subs r3, r3, r2 80037ec: 009b lsls r3, r3, #2 80037ee: 440b add r3, r1 80037f0: 334d adds r3, #77 @ 0x4d 80037f2: 781b ldrb r3, [r3, #0] 80037f4: 2b06 cmp r3, #6 80037f6: d114 bne.n 8003822 { hhcd->hc[chnum].state = HC_HALTED; 80037f8: 78fa ldrb r2, [r7, #3] 80037fa: 6879 ldr r1, [r7, #4] 80037fc: 4613 mov r3, r2 80037fe: 011b lsls r3, r3, #4 8003800: 1a9b subs r3, r3, r2 8003802: 009b lsls r3, r3, #2 8003804: 440b add r3, r1 8003806: 334d adds r3, #77 @ 0x4d 8003808: 2202 movs r2, #2 800380a: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_STALL; 800380c: 78fa ldrb r2, [r7, #3] 800380e: 6879 ldr r1, [r7, #4] 8003810: 4613 mov r3, r2 8003812: 011b lsls r3, r3, #4 8003814: 1a9b subs r3, r3, r2 8003816: 009b lsls r3, r3, #2 8003818: 440b add r3, r1 800381a: 334c adds r3, #76 @ 0x4c 800381c: 2205 movs r2, #5 800381e: 701a strb r2, [r3, #0] 8003820: e075 b.n 800390e } else if ((hhcd->hc[chnum].state == HC_XACTERR) || 8003822: 78fa ldrb r2, [r7, #3] 8003824: 6879 ldr r1, [r7, #4] 8003826: 4613 mov r3, r2 8003828: 011b lsls r3, r3, #4 800382a: 1a9b subs r3, r3, r2 800382c: 009b lsls r3, r3, #2 800382e: 440b add r3, r1 8003830: 334d adds r3, #77 @ 0x4d 8003832: 781b ldrb r3, [r3, #0] 8003834: 2b07 cmp r3, #7 8003836: d00a beq.n 800384e (hhcd->hc[chnum].state == HC_DATATGLERR)) 8003838: 78fa ldrb r2, [r7, #3] 800383a: 6879 ldr r1, [r7, #4] 800383c: 4613 mov r3, r2 800383e: 011b lsls r3, r3, #4 8003840: 1a9b subs r3, r3, r2 8003842: 009b lsls r3, r3, #2 8003844: 440b add r3, r1 8003846: 334d adds r3, #77 @ 0x4d 8003848: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].state == HC_XACTERR) || 800384a: 2b09 cmp r3, #9 800384c: d170 bne.n 8003930 { hhcd->hc[chnum].state = HC_HALTED; 800384e: 78fa ldrb r2, [r7, #3] 8003850: 6879 ldr r1, [r7, #4] 8003852: 4613 mov r3, r2 8003854: 011b lsls r3, r3, #4 8003856: 1a9b subs r3, r3, r2 8003858: 009b lsls r3, r3, #2 800385a: 440b add r3, r1 800385c: 334d adds r3, #77 @ 0x4d 800385e: 2202 movs r2, #2 8003860: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 8003862: 78fa ldrb r2, [r7, #3] 8003864: 6879 ldr r1, [r7, #4] 8003866: 4613 mov r3, r2 8003868: 011b lsls r3, r3, #4 800386a: 1a9b subs r3, r3, r2 800386c: 009b lsls r3, r3, #2 800386e: 440b add r3, r1 8003870: 3344 adds r3, #68 @ 0x44 8003872: 681b ldr r3, [r3, #0] 8003874: 1c59 adds r1, r3, #1 8003876: 6878 ldr r0, [r7, #4] 8003878: 4613 mov r3, r2 800387a: 011b lsls r3, r3, #4 800387c: 1a9b subs r3, r3, r2 800387e: 009b lsls r3, r3, #2 8003880: 4403 add r3, r0 8003882: 3344 adds r3, #68 @ 0x44 8003884: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 8003886: 78fa ldrb r2, [r7, #3] 8003888: 6879 ldr r1, [r7, #4] 800388a: 4613 mov r3, r2 800388c: 011b lsls r3, r3, #4 800388e: 1a9b subs r3, r3, r2 8003890: 009b lsls r3, r3, #2 8003892: 440b add r3, r1 8003894: 3344 adds r3, #68 @ 0x44 8003896: 681b ldr r3, [r3, #0] 8003898: 2b02 cmp r3, #2 800389a: d914 bls.n 80038c6 { hhcd->hc[chnum].ErrCnt = 0U; 800389c: 78fa ldrb r2, [r7, #3] 800389e: 6879 ldr r1, [r7, #4] 80038a0: 4613 mov r3, r2 80038a2: 011b lsls r3, r3, #4 80038a4: 1a9b subs r3, r3, r2 80038a6: 009b lsls r3, r3, #2 80038a8: 440b add r3, r1 80038aa: 3344 adds r3, #68 @ 0x44 80038ac: 2200 movs r2, #0 80038ae: 601a str r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 80038b0: 78fa ldrb r2, [r7, #3] 80038b2: 6879 ldr r1, [r7, #4] 80038b4: 4613 mov r3, r2 80038b6: 011b lsls r3, r3, #4 80038b8: 1a9b subs r3, r3, r2 80038ba: 009b lsls r3, r3, #2 80038bc: 440b add r3, r1 80038be: 334c adds r3, #76 @ 0x4c 80038c0: 2204 movs r2, #4 80038c2: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 80038c4: e022 b.n 800390c } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 80038c6: 78fa ldrb r2, [r7, #3] 80038c8: 6879 ldr r1, [r7, #4] 80038ca: 4613 mov r3, r2 80038cc: 011b lsls r3, r3, #4 80038ce: 1a9b subs r3, r3, r2 80038d0: 009b lsls r3, r3, #2 80038d2: 440b add r3, r1 80038d4: 334c adds r3, #76 @ 0x4c 80038d6: 2202 movs r2, #2 80038d8: 701a strb r2, [r3, #0] /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 80038da: 78fb ldrb r3, [r7, #3] 80038dc: 015a lsls r2, r3, #5 80038de: 693b ldr r3, [r7, #16] 80038e0: 4413 add r3, r2 80038e2: f503 63a0 add.w r3, r3, #1280 @ 0x500 80038e6: 681b ldr r3, [r3, #0] 80038e8: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 80038ea: 68fb ldr r3, [r7, #12] 80038ec: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80038f0: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 80038f2: 68fb ldr r3, [r7, #12] 80038f4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80038f8: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 80038fa: 78fb ldrb r3, [r7, #3] 80038fc: 015a lsls r2, r3, #5 80038fe: 693b ldr r3, [r7, #16] 8003900: 4413 add r3, r2 8003902: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003906: 461a mov r2, r3 8003908: 68fb ldr r3, [r7, #12] 800390a: 6013 str r3, [r2, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800390c: bf00 nop } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 800390e: 78fa ldrb r2, [r7, #3] 8003910: 6879 ldr r1, [r7, #4] 8003912: 4613 mov r3, r2 8003914: 011b lsls r3, r3, #4 8003916: 1a9b subs r3, r3, r2 8003918: 009b lsls r3, r3, #2 800391a: 440b add r3, r1 800391c: 334c adds r3, #76 @ 0x4c 800391e: 781a ldrb r2, [r3, #0] 8003920: 78fb ldrb r3, [r7, #3] 8003922: 4619 mov r1, r3 8003924: 6878 ldr r0, [r7, #4] 8003926: f004 fa65 bl 8007df4 800392a: e002 b.n 8003932 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { return; 800392c: bf00 nop 800392e: e000 b.n 8003932 return; 8003930: bf00 nop } } 8003932: 3718 adds r7, #24 8003934: 46bd mov sp, r7 8003936: bd80 pop {r7, pc} 08003938 : * @brief Handle Rx Queue Level interrupt requests. * @param hhcd HCD handle * @retval none */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { 8003938: b580 push {r7, lr} 800393a: b08a sub sp, #40 @ 0x28 800393c: af00 add r7, sp, #0 800393e: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8003940: 687b ldr r3, [r7, #4] 8003942: 681b ldr r3, [r3, #0] 8003944: 627b str r3, [r7, #36] @ 0x24 uint32_t USBx_BASE = (uint32_t)USBx; 8003946: 6a7b ldr r3, [r7, #36] @ 0x24 8003948: 623b str r3, [r7, #32] uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; 800394a: 687b ldr r3, [r7, #4] 800394c: 681b ldr r3, [r3, #0] 800394e: 6a1b ldr r3, [r3, #32] 8003950: 61fb str r3, [r7, #28] chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; 8003952: 69fb ldr r3, [r7, #28] 8003954: f003 030f and.w r3, r3, #15 8003958: 61bb str r3, [r7, #24] pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; 800395a: 69fb ldr r3, [r7, #28] 800395c: 0c5b lsrs r3, r3, #17 800395e: f003 030f and.w r3, r3, #15 8003962: 617b str r3, [r7, #20] pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; 8003964: 69fb ldr r3, [r7, #28] 8003966: 091b lsrs r3, r3, #4 8003968: f3c3 030a ubfx r3, r3, #0, #11 800396c: 613b str r3, [r7, #16] switch (pktsts) 800396e: 697b ldr r3, [r7, #20] 8003970: 2b02 cmp r3, #2 8003972: d004 beq.n 800397e 8003974: 697b ldr r3, [r7, #20] 8003976: 2b05 cmp r3, #5 8003978: f000 80b6 beq.w 8003ae8 break; case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_CH_HALTED: default: break; 800397c: e0b7 b.n 8003aee if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) 800397e: 693b ldr r3, [r7, #16] 8003980: 2b00 cmp r3, #0 8003982: f000 80b3 beq.w 8003aec 8003986: 6879 ldr r1, [r7, #4] 8003988: 69ba ldr r2, [r7, #24] 800398a: 4613 mov r3, r2 800398c: 011b lsls r3, r3, #4 800398e: 1a9b subs r3, r3, r2 8003990: 009b lsls r3, r3, #2 8003992: 440b add r3, r1 8003994: 332c adds r3, #44 @ 0x2c 8003996: 681b ldr r3, [r3, #0] 8003998: 2b00 cmp r3, #0 800399a: f000 80a7 beq.w 8003aec if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) 800399e: 6879 ldr r1, [r7, #4] 80039a0: 69ba ldr r2, [r7, #24] 80039a2: 4613 mov r3, r2 80039a4: 011b lsls r3, r3, #4 80039a6: 1a9b subs r3, r3, r2 80039a8: 009b lsls r3, r3, #2 80039aa: 440b add r3, r1 80039ac: 3338 adds r3, #56 @ 0x38 80039ae: 681a ldr r2, [r3, #0] 80039b0: 693b ldr r3, [r7, #16] 80039b2: 18d1 adds r1, r2, r3 80039b4: 6878 ldr r0, [r7, #4] 80039b6: 69ba ldr r2, [r7, #24] 80039b8: 4613 mov r3, r2 80039ba: 011b lsls r3, r3, #4 80039bc: 1a9b subs r3, r3, r2 80039be: 009b lsls r3, r3, #2 80039c0: 4403 add r3, r0 80039c2: 3334 adds r3, #52 @ 0x34 80039c4: 681b ldr r3, [r3, #0] 80039c6: 4299 cmp r1, r3 80039c8: f200 8083 bhi.w 8003ad2 (void)USB_ReadPacket(hhcd->Instance, 80039cc: 687b ldr r3, [r7, #4] 80039ce: 6818 ldr r0, [r3, #0] 80039d0: 6879 ldr r1, [r7, #4] 80039d2: 69ba ldr r2, [r7, #24] 80039d4: 4613 mov r3, r2 80039d6: 011b lsls r3, r3, #4 80039d8: 1a9b subs r3, r3, r2 80039da: 009b lsls r3, r3, #2 80039dc: 440b add r3, r1 80039de: 332c adds r3, #44 @ 0x2c 80039e0: 681b ldr r3, [r3, #0] 80039e2: 693a ldr r2, [r7, #16] 80039e4: b292 uxth r2, r2 80039e6: 4619 mov r1, r3 80039e8: f002 fd8a bl 8006500 hhcd->hc[chnum].xfer_buff += pktcnt; 80039ec: 6879 ldr r1, [r7, #4] 80039ee: 69ba ldr r2, [r7, #24] 80039f0: 4613 mov r3, r2 80039f2: 011b lsls r3, r3, #4 80039f4: 1a9b subs r3, r3, r2 80039f6: 009b lsls r3, r3, #2 80039f8: 440b add r3, r1 80039fa: 332c adds r3, #44 @ 0x2c 80039fc: 681a ldr r2, [r3, #0] 80039fe: 693b ldr r3, [r7, #16] 8003a00: 18d1 adds r1, r2, r3 8003a02: 6878 ldr r0, [r7, #4] 8003a04: 69ba ldr r2, [r7, #24] 8003a06: 4613 mov r3, r2 8003a08: 011b lsls r3, r3, #4 8003a0a: 1a9b subs r3, r3, r2 8003a0c: 009b lsls r3, r3, #2 8003a0e: 4403 add r3, r0 8003a10: 332c adds r3, #44 @ 0x2c 8003a12: 6019 str r1, [r3, #0] hhcd->hc[chnum].xfer_count += pktcnt; 8003a14: 6879 ldr r1, [r7, #4] 8003a16: 69ba ldr r2, [r7, #24] 8003a18: 4613 mov r3, r2 8003a1a: 011b lsls r3, r3, #4 8003a1c: 1a9b subs r3, r3, r2 8003a1e: 009b lsls r3, r3, #2 8003a20: 440b add r3, r1 8003a22: 3338 adds r3, #56 @ 0x38 8003a24: 681a ldr r2, [r3, #0] 8003a26: 693b ldr r3, [r7, #16] 8003a28: 18d1 adds r1, r2, r3 8003a2a: 6878 ldr r0, [r7, #4] 8003a2c: 69ba ldr r2, [r7, #24] 8003a2e: 4613 mov r3, r2 8003a30: 011b lsls r3, r3, #4 8003a32: 1a9b subs r3, r3, r2 8003a34: 009b lsls r3, r3, #2 8003a36: 4403 add r3, r0 8003a38: 3338 adds r3, #56 @ 0x38 8003a3a: 6019 str r1, [r3, #0] xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; 8003a3c: 69bb ldr r3, [r7, #24] 8003a3e: 015a lsls r2, r3, #5 8003a40: 6a3b ldr r3, [r7, #32] 8003a42: 4413 add r3, r2 8003a44: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a48: 691b ldr r3, [r3, #16] 8003a4a: 0cdb lsrs r3, r3, #19 8003a4c: f3c3 0309 ubfx r3, r3, #0, #10 8003a50: 60fb str r3, [r7, #12] if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) 8003a52: 6879 ldr r1, [r7, #4] 8003a54: 69ba ldr r2, [r7, #24] 8003a56: 4613 mov r3, r2 8003a58: 011b lsls r3, r3, #4 8003a5a: 1a9b subs r3, r3, r2 8003a5c: 009b lsls r3, r3, #2 8003a5e: 440b add r3, r1 8003a60: 3328 adds r3, #40 @ 0x28 8003a62: 881b ldrh r3, [r3, #0] 8003a64: 461a mov r2, r3 8003a66: 693b ldr r3, [r7, #16] 8003a68: 4293 cmp r3, r2 8003a6a: d13f bne.n 8003aec 8003a6c: 68fb ldr r3, [r7, #12] 8003a6e: 2b00 cmp r3, #0 8003a70: d03c beq.n 8003aec tmpreg = USBx_HC(chnum)->HCCHAR; 8003a72: 69bb ldr r3, [r7, #24] 8003a74: 015a lsls r2, r3, #5 8003a76: 6a3b ldr r3, [r7, #32] 8003a78: 4413 add r3, r2 8003a7a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a7e: 681b ldr r3, [r3, #0] 8003a80: 60bb str r3, [r7, #8] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8003a82: 68bb ldr r3, [r7, #8] 8003a84: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8003a88: 60bb str r3, [r7, #8] tmpreg |= USB_OTG_HCCHAR_CHENA; 8003a8a: 68bb ldr r3, [r7, #8] 8003a8c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8003a90: 60bb str r3, [r7, #8] USBx_HC(chnum)->HCCHAR = tmpreg; 8003a92: 69bb ldr r3, [r7, #24] 8003a94: 015a lsls r2, r3, #5 8003a96: 6a3b ldr r3, [r7, #32] 8003a98: 4413 add r3, r2 8003a9a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a9e: 461a mov r2, r3 8003aa0: 68bb ldr r3, [r7, #8] 8003aa2: 6013 str r3, [r2, #0] hhcd->hc[chnum].toggle_in ^= 1U; 8003aa4: 6879 ldr r1, [r7, #4] 8003aa6: 69ba ldr r2, [r7, #24] 8003aa8: 4613 mov r3, r2 8003aaa: 011b lsls r3, r3, #4 8003aac: 1a9b subs r3, r3, r2 8003aae: 009b lsls r3, r3, #2 8003ab0: 440b add r3, r1 8003ab2: 333c adds r3, #60 @ 0x3c 8003ab4: 781b ldrb r3, [r3, #0] 8003ab6: f083 0301 eor.w r3, r3, #1 8003aba: b2d8 uxtb r0, r3 8003abc: 6879 ldr r1, [r7, #4] 8003abe: 69ba ldr r2, [r7, #24] 8003ac0: 4613 mov r3, r2 8003ac2: 011b lsls r3, r3, #4 8003ac4: 1a9b subs r3, r3, r2 8003ac6: 009b lsls r3, r3, #2 8003ac8: 440b add r3, r1 8003aca: 333c adds r3, #60 @ 0x3c 8003acc: 4602 mov r2, r0 8003ace: 701a strb r2, [r3, #0] break; 8003ad0: e00c b.n 8003aec hhcd->hc[chnum].urb_state = URB_ERROR; 8003ad2: 6879 ldr r1, [r7, #4] 8003ad4: 69ba ldr r2, [r7, #24] 8003ad6: 4613 mov r3, r2 8003ad8: 011b lsls r3, r3, #4 8003ada: 1a9b subs r3, r3, r2 8003adc: 009b lsls r3, r3, #2 8003ade: 440b add r3, r1 8003ae0: 334c adds r3, #76 @ 0x4c 8003ae2: 2204 movs r2, #4 8003ae4: 701a strb r2, [r3, #0] break; 8003ae6: e001 b.n 8003aec break; 8003ae8: bf00 nop 8003aea: e000 b.n 8003aee break; 8003aec: bf00 nop } } 8003aee: bf00 nop 8003af0: 3728 adds r7, #40 @ 0x28 8003af2: 46bd mov sp, r7 8003af4: bd80 pop {r7, pc} 08003af6 : * @brief Handle Host Port interrupt requests. * @param hhcd HCD handle * @retval None */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { 8003af6: b580 push {r7, lr} 8003af8: b086 sub sp, #24 8003afa: af00 add r7, sp, #0 8003afc: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8003afe: 687b ldr r3, [r7, #4] 8003b00: 681b ldr r3, [r3, #0] 8003b02: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003b04: 697b ldr r3, [r7, #20] 8003b06: 613b str r3, [r7, #16] __IO uint32_t hprt0; __IO uint32_t hprt0_dup; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; 8003b08: 693b ldr r3, [r7, #16] 8003b0a: f503 6388 add.w r3, r3, #1088 @ 0x440 8003b0e: 681b ldr r3, [r3, #0] 8003b10: 60fb str r3, [r7, #12] hprt0_dup = USBx_HPRT0; 8003b12: 693b ldr r3, [r7, #16] 8003b14: f503 6388 add.w r3, r3, #1088 @ 0x440 8003b18: 681b ldr r3, [r3, #0] 8003b1a: 60bb str r3, [r7, #8] hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ 8003b1c: 68bb ldr r3, [r7, #8] 8003b1e: f023 032e bic.w r3, r3, #46 @ 0x2e 8003b22: 60bb str r3, [r7, #8] USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); /* Check whether Port Connect detected */ if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) 8003b24: 68fb ldr r3, [r7, #12] 8003b26: f003 0302 and.w r3, r3, #2 8003b2a: 2b02 cmp r3, #2 8003b2c: d10b bne.n 8003b46 { if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) 8003b2e: 68fb ldr r3, [r7, #12] 8003b30: f003 0301 and.w r3, r3, #1 8003b34: 2b01 cmp r3, #1 8003b36: d102 bne.n 8003b3e { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->ConnectCallback(hhcd); #else HAL_HCD_Connect_Callback(hhcd); 8003b38: 6878 ldr r0, [r7, #4] 8003b3a: f004 f93f bl 8007dbc #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } hprt0_dup |= USB_OTG_HPRT_PCDET; 8003b3e: 68bb ldr r3, [r7, #8] 8003b40: f043 0302 orr.w r3, r3, #2 8003b44: 60bb str r3, [r7, #8] } /* Check whether Port Enable Changed */ if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) 8003b46: 68fb ldr r3, [r7, #12] 8003b48: f003 0308 and.w r3, r3, #8 8003b4c: 2b08 cmp r3, #8 8003b4e: d132 bne.n 8003bb6 { hprt0_dup |= USB_OTG_HPRT_PENCHNG; 8003b50: 68bb ldr r3, [r7, #8] 8003b52: f043 0308 orr.w r3, r3, #8 8003b56: 60bb str r3, [r7, #8] if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) 8003b58: 68fb ldr r3, [r7, #12] 8003b5a: f003 0304 and.w r3, r3, #4 8003b5e: 2b04 cmp r3, #4 8003b60: d126 bne.n 8003bb0 { if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) 8003b62: 687b ldr r3, [r7, #4] 8003b64: 7a5b ldrb r3, [r3, #9] 8003b66: 2b02 cmp r3, #2 8003b68: d113 bne.n 8003b92 { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) 8003b6a: 68fb ldr r3, [r7, #12] 8003b6c: f403 23c0 and.w r3, r3, #393216 @ 0x60000 8003b70: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003b74: d106 bne.n 8003b84 { (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); 8003b76: 687b ldr r3, [r7, #4] 8003b78: 681b ldr r3, [r3, #0] 8003b7a: 2102 movs r1, #2 8003b7c: 4618 mov r0, r3 8003b7e: f002 fd59 bl 8006634 8003b82: e011 b.n 8003ba8 } else { (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); 8003b84: 687b ldr r3, [r7, #4] 8003b86: 681b ldr r3, [r3, #0] 8003b88: 2101 movs r1, #1 8003b8a: 4618 mov r0, r3 8003b8c: f002 fd52 bl 8006634 8003b90: e00a b.n 8003ba8 } } else { if (hhcd->Init.speed == HCD_SPEED_FULL) 8003b92: 687b ldr r3, [r7, #4] 8003b94: 79db ldrb r3, [r3, #7] 8003b96: 2b01 cmp r3, #1 8003b98: d106 bne.n 8003ba8 { USBx_HOST->HFIR = HFIR_60_MHZ; 8003b9a: 693b ldr r3, [r7, #16] 8003b9c: f503 6380 add.w r3, r3, #1024 @ 0x400 8003ba0: 461a mov r2, r3 8003ba2: f64e 2360 movw r3, #60000 @ 0xea60 8003ba6: 6053 str r3, [r2, #4] } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortEnabledCallback(hhcd); #else HAL_HCD_PortEnabled_Callback(hhcd); 8003ba8: 6878 ldr r0, [r7, #4] 8003baa: f004 f935 bl 8007e18 8003bae: e002 b.n 8003bb6 else { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortDisabledCallback(hhcd); #else HAL_HCD_PortDisabled_Callback(hhcd); 8003bb0: 6878 ldr r0, [r7, #4] 8003bb2: f004 f93f bl 8007e34 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Check for an overcurrent */ if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) 8003bb6: 68fb ldr r3, [r7, #12] 8003bb8: f003 0320 and.w r3, r3, #32 8003bbc: 2b20 cmp r3, #32 8003bbe: d103 bne.n 8003bc8 { hprt0_dup |= USB_OTG_HPRT_POCCHNG; 8003bc0: 68bb ldr r3, [r7, #8] 8003bc2: f043 0320 orr.w r3, r3, #32 8003bc6: 60bb str r3, [r7, #8] } /* Clear Port Interrupts */ USBx_HPRT0 = hprt0_dup; 8003bc8: 693b ldr r3, [r7, #16] 8003bca: f503 6388 add.w r3, r3, #1088 @ 0x440 8003bce: 461a mov r2, r3 8003bd0: 68bb ldr r3, [r7, #8] 8003bd2: 6013 str r3, [r2, #0] } 8003bd4: bf00 nop 8003bd6: 3718 adds r7, #24 8003bd8: 46bd mov sp, r7 8003bda: bd80 pop {r7, pc} 08003bdc : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8003bdc: b580 push {r7, lr} 8003bde: b084 sub sp, #16 8003be0: af00 add r7, sp, #0 8003be2: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8003be4: 687b ldr r3, [r7, #4] 8003be6: 2b00 cmp r3, #0 8003be8: d101 bne.n 8003bee { return HAL_ERROR; 8003bea: 2301 movs r3, #1 8003bec: e12b b.n 8003e46 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8003bee: 687b ldr r3, [r7, #4] 8003bf0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003bf4: b2db uxtb r3, r3 8003bf6: 2b00 cmp r3, #0 8003bf8: d106 bne.n 8003c08 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8003bfa: 687b ldr r3, [r7, #4] 8003bfc: 2200 movs r2, #0 8003bfe: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8003c02: 6878 ldr r0, [r7, #4] 8003c04: f7fd f954 bl 8000eb0 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8003c08: 687b ldr r3, [r7, #4] 8003c0a: 2224 movs r2, #36 @ 0x24 8003c0c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003c10: 687b ldr r3, [r7, #4] 8003c12: 681b ldr r3, [r3, #0] 8003c14: 681a ldr r2, [r3, #0] 8003c16: 687b ldr r3, [r7, #4] 8003c18: 681b ldr r3, [r3, #0] 8003c1a: f022 0201 bic.w r2, r2, #1 8003c1e: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8003c20: 687b ldr r3, [r7, #4] 8003c22: 681b ldr r3, [r3, #0] 8003c24: 681a ldr r2, [r3, #0] 8003c26: 687b ldr r3, [r7, #4] 8003c28: 681b ldr r3, [r3, #0] 8003c2a: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8003c2e: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8003c30: 687b ldr r3, [r7, #4] 8003c32: 681b ldr r3, [r3, #0] 8003c34: 681a ldr r2, [r3, #0] 8003c36: 687b ldr r3, [r7, #4] 8003c38: 681b ldr r3, [r3, #0] 8003c3a: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8003c3e: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8003c40: f001 f90c bl 8004e5c 8003c44: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8003c46: 687b ldr r3, [r7, #4] 8003c48: 685b ldr r3, [r3, #4] 8003c4a: 4a81 ldr r2, [pc, #516] @ (8003e50 ) 8003c4c: 4293 cmp r3, r2 8003c4e: d807 bhi.n 8003c60 8003c50: 68fb ldr r3, [r7, #12] 8003c52: 4a80 ldr r2, [pc, #512] @ (8003e54 ) 8003c54: 4293 cmp r3, r2 8003c56: bf94 ite ls 8003c58: 2301 movls r3, #1 8003c5a: 2300 movhi r3, #0 8003c5c: b2db uxtb r3, r3 8003c5e: e006 b.n 8003c6e 8003c60: 68fb ldr r3, [r7, #12] 8003c62: 4a7d ldr r2, [pc, #500] @ (8003e58 ) 8003c64: 4293 cmp r3, r2 8003c66: bf94 ite ls 8003c68: 2301 movls r3, #1 8003c6a: 2300 movhi r3, #0 8003c6c: b2db uxtb r3, r3 8003c6e: 2b00 cmp r3, #0 8003c70: d001 beq.n 8003c76 { return HAL_ERROR; 8003c72: 2301 movs r3, #1 8003c74: e0e7 b.n 8003e46 } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8003c76: 68fb ldr r3, [r7, #12] 8003c78: 4a78 ldr r2, [pc, #480] @ (8003e5c ) 8003c7a: fba2 2303 umull r2, r3, r2, r3 8003c7e: 0c9b lsrs r3, r3, #18 8003c80: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8003c82: 687b ldr r3, [r7, #4] 8003c84: 681b ldr r3, [r3, #0] 8003c86: 685b ldr r3, [r3, #4] 8003c88: f023 013f bic.w r1, r3, #63 @ 0x3f 8003c8c: 687b ldr r3, [r7, #4] 8003c8e: 681b ldr r3, [r3, #0] 8003c90: 68ba ldr r2, [r7, #8] 8003c92: 430a orrs r2, r1 8003c94: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8003c96: 687b ldr r3, [r7, #4] 8003c98: 681b ldr r3, [r3, #0] 8003c9a: 6a1b ldr r3, [r3, #32] 8003c9c: f023 013f bic.w r1, r3, #63 @ 0x3f 8003ca0: 687b ldr r3, [r7, #4] 8003ca2: 685b ldr r3, [r3, #4] 8003ca4: 4a6a ldr r2, [pc, #424] @ (8003e50 ) 8003ca6: 4293 cmp r3, r2 8003ca8: d802 bhi.n 8003cb0 8003caa: 68bb ldr r3, [r7, #8] 8003cac: 3301 adds r3, #1 8003cae: e009 b.n 8003cc4 8003cb0: 68bb ldr r3, [r7, #8] 8003cb2: f44f 7296 mov.w r2, #300 @ 0x12c 8003cb6: fb02 f303 mul.w r3, r2, r3 8003cba: 4a69 ldr r2, [pc, #420] @ (8003e60 ) 8003cbc: fba2 2303 umull r2, r3, r2, r3 8003cc0: 099b lsrs r3, r3, #6 8003cc2: 3301 adds r3, #1 8003cc4: 687a ldr r2, [r7, #4] 8003cc6: 6812 ldr r2, [r2, #0] 8003cc8: 430b orrs r3, r1 8003cca: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8003ccc: 687b ldr r3, [r7, #4] 8003cce: 681b ldr r3, [r3, #0] 8003cd0: 69db ldr r3, [r3, #28] 8003cd2: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8003cd6: f022 02ff bic.w r2, r2, #255 @ 0xff 8003cda: 687b ldr r3, [r7, #4] 8003cdc: 685b ldr r3, [r3, #4] 8003cde: 495c ldr r1, [pc, #368] @ (8003e50 ) 8003ce0: 428b cmp r3, r1 8003ce2: d819 bhi.n 8003d18 8003ce4: 68fb ldr r3, [r7, #12] 8003ce6: 1e59 subs r1, r3, #1 8003ce8: 687b ldr r3, [r7, #4] 8003cea: 685b ldr r3, [r3, #4] 8003cec: 005b lsls r3, r3, #1 8003cee: fbb1 f3f3 udiv r3, r1, r3 8003cf2: 1c59 adds r1, r3, #1 8003cf4: f640 73fc movw r3, #4092 @ 0xffc 8003cf8: 400b ands r3, r1 8003cfa: 2b00 cmp r3, #0 8003cfc: d00a beq.n 8003d14 8003cfe: 68fb ldr r3, [r7, #12] 8003d00: 1e59 subs r1, r3, #1 8003d02: 687b ldr r3, [r7, #4] 8003d04: 685b ldr r3, [r3, #4] 8003d06: 005b lsls r3, r3, #1 8003d08: fbb1 f3f3 udiv r3, r1, r3 8003d0c: 3301 adds r3, #1 8003d0e: f3c3 030b ubfx r3, r3, #0, #12 8003d12: e051 b.n 8003db8 8003d14: 2304 movs r3, #4 8003d16: e04f b.n 8003db8 8003d18: 687b ldr r3, [r7, #4] 8003d1a: 689b ldr r3, [r3, #8] 8003d1c: 2b00 cmp r3, #0 8003d1e: d111 bne.n 8003d44 8003d20: 68fb ldr r3, [r7, #12] 8003d22: 1e58 subs r0, r3, #1 8003d24: 687b ldr r3, [r7, #4] 8003d26: 6859 ldr r1, [r3, #4] 8003d28: 460b mov r3, r1 8003d2a: 005b lsls r3, r3, #1 8003d2c: 440b add r3, r1 8003d2e: fbb0 f3f3 udiv r3, r0, r3 8003d32: 3301 adds r3, #1 8003d34: f3c3 030b ubfx r3, r3, #0, #12 8003d38: 2b00 cmp r3, #0 8003d3a: bf0c ite eq 8003d3c: 2301 moveq r3, #1 8003d3e: 2300 movne r3, #0 8003d40: b2db uxtb r3, r3 8003d42: e012 b.n 8003d6a 8003d44: 68fb ldr r3, [r7, #12] 8003d46: 1e58 subs r0, r3, #1 8003d48: 687b ldr r3, [r7, #4] 8003d4a: 6859 ldr r1, [r3, #4] 8003d4c: 460b mov r3, r1 8003d4e: 009b lsls r3, r3, #2 8003d50: 440b add r3, r1 8003d52: 0099 lsls r1, r3, #2 8003d54: 440b add r3, r1 8003d56: fbb0 f3f3 udiv r3, r0, r3 8003d5a: 3301 adds r3, #1 8003d5c: f3c3 030b ubfx r3, r3, #0, #12 8003d60: 2b00 cmp r3, #0 8003d62: bf0c ite eq 8003d64: 2301 moveq r3, #1 8003d66: 2300 movne r3, #0 8003d68: b2db uxtb r3, r3 8003d6a: 2b00 cmp r3, #0 8003d6c: d001 beq.n 8003d72 8003d6e: 2301 movs r3, #1 8003d70: e022 b.n 8003db8 8003d72: 687b ldr r3, [r7, #4] 8003d74: 689b ldr r3, [r3, #8] 8003d76: 2b00 cmp r3, #0 8003d78: d10e bne.n 8003d98 8003d7a: 68fb ldr r3, [r7, #12] 8003d7c: 1e58 subs r0, r3, #1 8003d7e: 687b ldr r3, [r7, #4] 8003d80: 6859 ldr r1, [r3, #4] 8003d82: 460b mov r3, r1 8003d84: 005b lsls r3, r3, #1 8003d86: 440b add r3, r1 8003d88: fbb0 f3f3 udiv r3, r0, r3 8003d8c: 3301 adds r3, #1 8003d8e: f3c3 030b ubfx r3, r3, #0, #12 8003d92: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003d96: e00f b.n 8003db8 8003d98: 68fb ldr r3, [r7, #12] 8003d9a: 1e58 subs r0, r3, #1 8003d9c: 687b ldr r3, [r7, #4] 8003d9e: 6859 ldr r1, [r3, #4] 8003da0: 460b mov r3, r1 8003da2: 009b lsls r3, r3, #2 8003da4: 440b add r3, r1 8003da6: 0099 lsls r1, r3, #2 8003da8: 440b add r3, r1 8003daa: fbb0 f3f3 udiv r3, r0, r3 8003dae: 3301 adds r3, #1 8003db0: f3c3 030b ubfx r3, r3, #0, #12 8003db4: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8003db8: 6879 ldr r1, [r7, #4] 8003dba: 6809 ldr r1, [r1, #0] 8003dbc: 4313 orrs r3, r2 8003dbe: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8003dc0: 687b ldr r3, [r7, #4] 8003dc2: 681b ldr r3, [r3, #0] 8003dc4: 681b ldr r3, [r3, #0] 8003dc6: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8003dca: 687b ldr r3, [r7, #4] 8003dcc: 69da ldr r2, [r3, #28] 8003dce: 687b ldr r3, [r7, #4] 8003dd0: 6a1b ldr r3, [r3, #32] 8003dd2: 431a orrs r2, r3 8003dd4: 687b ldr r3, [r7, #4] 8003dd6: 681b ldr r3, [r3, #0] 8003dd8: 430a orrs r2, r1 8003dda: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8003ddc: 687b ldr r3, [r7, #4] 8003dde: 681b ldr r3, [r3, #0] 8003de0: 689b ldr r3, [r3, #8] 8003de2: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8003de6: f023 03ff bic.w r3, r3, #255 @ 0xff 8003dea: 687a ldr r2, [r7, #4] 8003dec: 6911 ldr r1, [r2, #16] 8003dee: 687a ldr r2, [r7, #4] 8003df0: 68d2 ldr r2, [r2, #12] 8003df2: 4311 orrs r1, r2 8003df4: 687a ldr r2, [r7, #4] 8003df6: 6812 ldr r2, [r2, #0] 8003df8: 430b orrs r3, r1 8003dfa: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8003dfc: 687b ldr r3, [r7, #4] 8003dfe: 681b ldr r3, [r3, #0] 8003e00: 68db ldr r3, [r3, #12] 8003e02: f023 01ff bic.w r1, r3, #255 @ 0xff 8003e06: 687b ldr r3, [r7, #4] 8003e08: 695a ldr r2, [r3, #20] 8003e0a: 687b ldr r3, [r7, #4] 8003e0c: 699b ldr r3, [r3, #24] 8003e0e: 431a orrs r2, r3 8003e10: 687b ldr r3, [r7, #4] 8003e12: 681b ldr r3, [r3, #0] 8003e14: 430a orrs r2, r1 8003e16: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8003e18: 687b ldr r3, [r7, #4] 8003e1a: 681b ldr r3, [r3, #0] 8003e1c: 681a ldr r2, [r3, #0] 8003e1e: 687b ldr r3, [r7, #4] 8003e20: 681b ldr r3, [r3, #0] 8003e22: f042 0201 orr.w r2, r2, #1 8003e26: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003e28: 687b ldr r3, [r7, #4] 8003e2a: 2200 movs r2, #0 8003e2c: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8003e2e: 687b ldr r3, [r7, #4] 8003e30: 2220 movs r2, #32 8003e32: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8003e36: 687b ldr r3, [r7, #4] 8003e38: 2200 movs r2, #0 8003e3a: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8003e3c: 687b ldr r3, [r7, #4] 8003e3e: 2200 movs r2, #0 8003e40: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8003e44: 2300 movs r3, #0 } 8003e46: 4618 mov r0, r3 8003e48: 3710 adds r7, #16 8003e4a: 46bd mov sp, r7 8003e4c: bd80 pop {r7, pc} 8003e4e: bf00 nop 8003e50: 000186a0 .word 0x000186a0 8003e54: 001e847f .word 0x001e847f 8003e58: 003d08ff .word 0x003d08ff 8003e5c: 431bde83 .word 0x431bde83 8003e60: 10624dd3 .word 0x10624dd3 08003e64 : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter new state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8003e64: b480 push {r7} 8003e66: b083 sub sp, #12 8003e68: af00 add r7, sp, #0 8003e6a: 6078 str r0, [r7, #4] 8003e6c: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8003e6e: 687b ldr r3, [r7, #4] 8003e70: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003e74: b2db uxtb r3, r3 8003e76: 2b20 cmp r3, #32 8003e78: d129 bne.n 8003ece { hi2c->State = HAL_I2C_STATE_BUSY; 8003e7a: 687b ldr r3, [r7, #4] 8003e7c: 2224 movs r2, #36 @ 0x24 8003e7e: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003e82: 687b ldr r3, [r7, #4] 8003e84: 681b ldr r3, [r3, #0] 8003e86: 681a ldr r2, [r3, #0] 8003e88: 687b ldr r3, [r7, #4] 8003e8a: 681b ldr r3, [r3, #0] 8003e8c: f022 0201 bic.w r2, r2, #1 8003e90: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); 8003e92: 687b ldr r3, [r7, #4] 8003e94: 681b ldr r3, [r3, #0] 8003e96: 6a5a ldr r2, [r3, #36] @ 0x24 8003e98: 687b ldr r3, [r7, #4] 8003e9a: 681b ldr r3, [r3, #0] 8003e9c: f022 0210 bic.w r2, r2, #16 8003ea0: 625a str r2, [r3, #36] @ 0x24 /* Disable the analog filter */ hi2c->Instance->FLTR |= AnalogFilter; 8003ea2: 687b ldr r3, [r7, #4] 8003ea4: 681b ldr r3, [r3, #0] 8003ea6: 6a59 ldr r1, [r3, #36] @ 0x24 8003ea8: 687b ldr r3, [r7, #4] 8003eaa: 681b ldr r3, [r3, #0] 8003eac: 683a ldr r2, [r7, #0] 8003eae: 430a orrs r2, r1 8003eb0: 625a str r2, [r3, #36] @ 0x24 __HAL_I2C_ENABLE(hi2c); 8003eb2: 687b ldr r3, [r7, #4] 8003eb4: 681b ldr r3, [r3, #0] 8003eb6: 681a ldr r2, [r3, #0] 8003eb8: 687b ldr r3, [r7, #4] 8003eba: 681b ldr r3, [r3, #0] 8003ebc: f042 0201 orr.w r2, r2, #1 8003ec0: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003ec2: 687b ldr r3, [r7, #4] 8003ec4: 2220 movs r2, #32 8003ec6: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8003eca: 2300 movs r3, #0 8003ecc: e000 b.n 8003ed0 } else { return HAL_BUSY; 8003ece: 2302 movs r3, #2 } } 8003ed0: 4618 mov r0, r3 8003ed2: 370c adds r7, #12 8003ed4: 46bd mov sp, r7 8003ed6: f85d 7b04 ldr.w r7, [sp], #4 8003eda: 4770 bx lr 08003edc : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8003edc: b480 push {r7} 8003ede: b085 sub sp, #20 8003ee0: af00 add r7, sp, #0 8003ee2: 6078 str r0, [r7, #4] 8003ee4: 6039 str r1, [r7, #0] uint16_t tmpreg = 0; 8003ee6: 2300 movs r3, #0 8003ee8: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8003eea: 687b ldr r3, [r7, #4] 8003eec: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003ef0: b2db uxtb r3, r3 8003ef2: 2b20 cmp r3, #32 8003ef4: d12a bne.n 8003f4c { hi2c->State = HAL_I2C_STATE_BUSY; 8003ef6: 687b ldr r3, [r7, #4] 8003ef8: 2224 movs r2, #36 @ 0x24 8003efa: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003efe: 687b ldr r3, [r7, #4] 8003f00: 681b ldr r3, [r3, #0] 8003f02: 681a ldr r2, [r3, #0] 8003f04: 687b ldr r3, [r7, #4] 8003f06: 681b ldr r3, [r3, #0] 8003f08: f022 0201 bic.w r2, r2, #1 8003f0c: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->FLTR; 8003f0e: 687b ldr r3, [r7, #4] 8003f10: 681b ldr r3, [r3, #0] 8003f12: 6a5b ldr r3, [r3, #36] @ 0x24 8003f14: 81fb strh r3, [r7, #14] /* Reset I2Cx DNF bit [3:0] */ tmpreg &= ~(I2C_FLTR_DNF); 8003f16: 89fb ldrh r3, [r7, #14] 8003f18: f023 030f bic.w r3, r3, #15 8003f1c: 81fb strh r3, [r7, #14] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter; 8003f1e: 683b ldr r3, [r7, #0] 8003f20: b29a uxth r2, r3 8003f22: 89fb ldrh r3, [r7, #14] 8003f24: 4313 orrs r3, r2 8003f26: 81fb strh r3, [r7, #14] /* Store the new register value */ hi2c->Instance->FLTR = tmpreg; 8003f28: 687b ldr r3, [r7, #4] 8003f2a: 681b ldr r3, [r3, #0] 8003f2c: 89fa ldrh r2, [r7, #14] 8003f2e: 625a str r2, [r3, #36] @ 0x24 __HAL_I2C_ENABLE(hi2c); 8003f30: 687b ldr r3, [r7, #4] 8003f32: 681b ldr r3, [r3, #0] 8003f34: 681a ldr r2, [r3, #0] 8003f36: 687b ldr r3, [r7, #4] 8003f38: 681b ldr r3, [r3, #0] 8003f3a: f042 0201 orr.w r2, r2, #1 8003f3e: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003f40: 687b ldr r3, [r7, #4] 8003f42: 2220 movs r2, #32 8003f44: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8003f48: 2300 movs r3, #0 8003f4a: e000 b.n 8003f4e } else { return HAL_BUSY; 8003f4c: 2302 movs r3, #2 } } 8003f4e: 4618 mov r0, r3 8003f50: 3714 adds r7, #20 8003f52: 46bd mov sp, r7 8003f54: f85d 7b04 ldr.w r7, [sp], #4 8003f58: 4770 bx lr 08003f5a : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { 8003f5a: b580 push {r7, lr} 8003f5c: b084 sub sp, #16 8003f5e: af00 add r7, sp, #0 8003f60: 6078 str r0, [r7, #4] uint32_t tmp; uint32_t tmp1; /* Check the LTDC peripheral state */ if (hltdc == NULL) 8003f62: 687b ldr r3, [r7, #4] 8003f64: 2b00 cmp r3, #0 8003f66: d101 bne.n 8003f6c { return HAL_ERROR; 8003f68: 2301 movs r3, #1 8003f6a: e08f b.n 800408c } /* Init the low level hardware */ hltdc->MspInitCallback(hltdc); } #else if (hltdc->State == HAL_LTDC_STATE_RESET) 8003f6c: 687b ldr r3, [r7, #4] 8003f6e: f893 30a1 ldrb.w r3, [r3, #161] @ 0xa1 8003f72: b2db uxtb r3, r3 8003f74: 2b00 cmp r3, #0 8003f76: d106 bne.n 8003f86 { /* Allocate lock resource and initialize it */ hltdc->Lock = HAL_UNLOCKED; 8003f78: 687b ldr r3, [r7, #4] 8003f7a: 2200 movs r2, #0 8003f7c: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 /* Init the low level hardware */ HAL_LTDC_MspInit(hltdc); 8003f80: 6878 ldr r0, [r7, #4] 8003f82: f7fc ffff bl 8000f84 } #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; 8003f86: 687b ldr r3, [r7, #4] 8003f88: 2202 movs r2, #2 8003f8a: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Configure the HS, VS, DE and PC polarity */ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); 8003f8e: 687b ldr r3, [r7, #4] 8003f90: 681b ldr r3, [r3, #0] 8003f92: 699a ldr r2, [r3, #24] 8003f94: 687b ldr r3, [r7, #4] 8003f96: 681b ldr r3, [r3, #0] 8003f98: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000 8003f9c: 619a str r2, [r3, #24] hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003f9e: 687b ldr r3, [r7, #4] 8003fa0: 681b ldr r3, [r3, #0] 8003fa2: 6999 ldr r1, [r3, #24] 8003fa4: 687b ldr r3, [r7, #4] 8003fa6: 685a ldr r2, [r3, #4] 8003fa8: 687b ldr r3, [r7, #4] 8003faa: 689b ldr r3, [r3, #8] 8003fac: 431a orrs r2, r3 hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); 8003fae: 687b ldr r3, [r7, #4] 8003fb0: 68db ldr r3, [r3, #12] hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003fb2: 431a orrs r2, r3 hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); 8003fb4: 687b ldr r3, [r7, #4] 8003fb6: 691b ldr r3, [r3, #16] 8003fb8: 431a orrs r2, r3 hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003fba: 687b ldr r3, [r7, #4] 8003fbc: 681b ldr r3, [r3, #0] 8003fbe: 430a orrs r2, r1 8003fc0: 619a str r2, [r3, #24] /* Set Synchronization size */ tmp = (hltdc->Init.HorizontalSync << 16U); 8003fc2: 687b ldr r3, [r7, #4] 8003fc4: 695b ldr r3, [r3, #20] 8003fc6: 041b lsls r3, r3, #16 8003fc8: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); 8003fca: 687b ldr r3, [r7, #4] 8003fcc: 6999 ldr r1, [r3, #24] 8003fce: 687b ldr r3, [r7, #4] 8003fd0: 681b ldr r3, [r3, #0] 8003fd2: 68fa ldr r2, [r7, #12] 8003fd4: 430a orrs r2, r1 8003fd6: 609a str r2, [r3, #8] /* Set Accumulated Back porch */ tmp = (hltdc->Init.AccumulatedHBP << 16U); 8003fd8: 687b ldr r3, [r7, #4] 8003fda: 69db ldr r3, [r3, #28] 8003fdc: 041b lsls r3, r3, #16 8003fde: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); 8003fe0: 687b ldr r3, [r7, #4] 8003fe2: 6a19 ldr r1, [r3, #32] 8003fe4: 687b ldr r3, [r7, #4] 8003fe6: 681b ldr r3, [r3, #0] 8003fe8: 68fa ldr r2, [r7, #12] 8003fea: 430a orrs r2, r1 8003fec: 60da str r2, [r3, #12] /* Set Accumulated Active Width */ tmp = (hltdc->Init.AccumulatedActiveW << 16U); 8003fee: 687b ldr r3, [r7, #4] 8003ff0: 6a5b ldr r3, [r3, #36] @ 0x24 8003ff2: 041b lsls r3, r3, #16 8003ff4: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); 8003ff6: 687b ldr r3, [r7, #4] 8003ff8: 6a99 ldr r1, [r3, #40] @ 0x28 8003ffa: 687b ldr r3, [r7, #4] 8003ffc: 681b ldr r3, [r3, #0] 8003ffe: 68fa ldr r2, [r7, #12] 8004000: 430a orrs r2, r1 8004002: 611a str r2, [r3, #16] /* Set Total Width */ tmp = (hltdc->Init.TotalWidth << 16U); 8004004: 687b ldr r3, [r7, #4] 8004006: 6adb ldr r3, [r3, #44] @ 0x2c 8004008: 041b lsls r3, r3, #16 800400a: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); 800400c: 687b ldr r3, [r7, #4] 800400e: 6b19 ldr r1, [r3, #48] @ 0x30 8004010: 687b ldr r3, [r7, #4] 8004012: 681b ldr r3, [r3, #0] 8004014: 68fa ldr r2, [r7, #12] 8004016: 430a orrs r2, r1 8004018: 615a str r2, [r3, #20] /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); 800401a: 687b ldr r3, [r7, #4] 800401c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8004020: 021b lsls r3, r3, #8 8004022: 60fb str r3, [r7, #12] tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); 8004024: 687b ldr r3, [r7, #4] 8004026: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 800402a: 041b lsls r3, r3, #16 800402c: 60bb str r3, [r7, #8] hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); 800402e: 687b ldr r3, [r7, #4] 8004030: 681b ldr r3, [r3, #0] 8004032: 6ada ldr r2, [r3, #44] @ 0x2c 8004034: 687b ldr r3, [r7, #4] 8004036: 681b ldr r3, [r3, #0] 8004038: f002 427f and.w r2, r2, #4278190080 @ 0xff000000 800403c: 62da str r2, [r3, #44] @ 0x2c hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); 800403e: 687b ldr r3, [r7, #4] 8004040: 681b ldr r3, [r3, #0] 8004042: 6ad9 ldr r1, [r3, #44] @ 0x2c 8004044: 68ba ldr r2, [r7, #8] 8004046: 68fb ldr r3, [r7, #12] 8004048: 4313 orrs r3, r2 800404a: 687a ldr r2, [r7, #4] 800404c: f892 2034 ldrb.w r2, [r2, #52] @ 0x34 8004050: 431a orrs r2, r3 8004052: 687b ldr r3, [r7, #4] 8004054: 681b ldr r3, [r3, #0] 8004056: 430a orrs r2, r1 8004058: 62da str r2, [r3, #44] @ 0x2c /* Enable the Transfer Error and FIFO underrun interrupts */ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); 800405a: 687b ldr r3, [r7, #4] 800405c: 681b ldr r3, [r3, #0] 800405e: 6b5a ldr r2, [r3, #52] @ 0x34 8004060: 687b ldr r3, [r7, #4] 8004062: 681b ldr r3, [r3, #0] 8004064: f042 0206 orr.w r2, r2, #6 8004068: 635a str r2, [r3, #52] @ 0x34 /* Enable LTDC by setting LTDCEN bit */ __HAL_LTDC_ENABLE(hltdc); 800406a: 687b ldr r3, [r7, #4] 800406c: 681b ldr r3, [r3, #0] 800406e: 699a ldr r2, [r3, #24] 8004070: 687b ldr r3, [r7, #4] 8004072: 681b ldr r3, [r3, #0] 8004074: f042 0201 orr.w r2, r2, #1 8004078: 619a str r2, [r3, #24] /* Initialize the error code */ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; 800407a: 687b ldr r3, [r7, #4] 800407c: 2200 movs r2, #0 800407e: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; 8004082: 687b ldr r3, [r7, #4] 8004084: 2201 movs r2, #1 8004086: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 return HAL_OK; 800408a: 2300 movs r3, #0 } 800408c: 4618 mov r0, r3 800408e: 3710 adds r7, #16 8004090: 46bd mov sp, r7 8004092: bd80 pop {r7, pc} 08004094 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) { 8004094: b580 push {r7, lr} 8004096: b084 sub sp, #16 8004098: af00 add r7, sp, #0 800409a: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(hltdc->Instance->ISR); 800409c: 687b ldr r3, [r7, #4] 800409e: 681b ldr r3, [r3, #0] 80040a0: 6b9b ldr r3, [r3, #56] @ 0x38 80040a2: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hltdc->Instance->IER); 80040a4: 687b ldr r3, [r7, #4] 80040a6: 681b ldr r3, [r3, #0] 80040a8: 6b5b ldr r3, [r3, #52] @ 0x34 80040aa: 60bb str r3, [r7, #8] /* Transfer Error Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) 80040ac: 68fb ldr r3, [r7, #12] 80040ae: f003 0304 and.w r3, r3, #4 80040b2: 2b00 cmp r3, #0 80040b4: d023 beq.n 80040fe 80040b6: 68bb ldr r3, [r7, #8] 80040b8: f003 0304 and.w r3, r3, #4 80040bc: 2b00 cmp r3, #0 80040be: d01e beq.n 80040fe { /* Disable the transfer Error interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); 80040c0: 687b ldr r3, [r7, #4] 80040c2: 681b ldr r3, [r3, #0] 80040c4: 6b5a ldr r2, [r3, #52] @ 0x34 80040c6: 687b ldr r3, [r7, #4] 80040c8: 681b ldr r3, [r3, #0] 80040ca: f022 0204 bic.w r2, r2, #4 80040ce: 635a str r2, [r3, #52] @ 0x34 /* Clear the transfer error flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); 80040d0: 687b ldr r3, [r7, #4] 80040d2: 681b ldr r3, [r3, #0] 80040d4: 2204 movs r2, #4 80040d6: 63da str r2, [r3, #60] @ 0x3c /* Update error code */ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; 80040d8: 687b ldr r3, [r7, #4] 80040da: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 80040de: f043 0201 orr.w r2, r3, #1 80040e2: 687b ldr r3, [r7, #4] 80040e4: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_ERROR; 80040e8: 687b ldr r3, [r7, #4] 80040ea: 2204 movs r2, #4 80040ec: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 80040f0: 687b ldr r3, [r7, #4] 80040f2: 2200 movs r2, #0 80040f4: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ hltdc->ErrorCallback(hltdc); #else /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); 80040f8: 6878 ldr r0, [r7, #4] 80040fa: f000 f86f bl 80041dc #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* FIFO underrun Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) 80040fe: 68fb ldr r3, [r7, #12] 8004100: f003 0302 and.w r3, r3, #2 8004104: 2b00 cmp r3, #0 8004106: d023 beq.n 8004150 8004108: 68bb ldr r3, [r7, #8] 800410a: f003 0302 and.w r3, r3, #2 800410e: 2b00 cmp r3, #0 8004110: d01e beq.n 8004150 { /* Disable the FIFO underrun interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); 8004112: 687b ldr r3, [r7, #4] 8004114: 681b ldr r3, [r3, #0] 8004116: 6b5a ldr r2, [r3, #52] @ 0x34 8004118: 687b ldr r3, [r7, #4] 800411a: 681b ldr r3, [r3, #0] 800411c: f022 0202 bic.w r2, r2, #2 8004120: 635a str r2, [r3, #52] @ 0x34 /* Clear the FIFO underrun flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); 8004122: 687b ldr r3, [r7, #4] 8004124: 681b ldr r3, [r3, #0] 8004126: 2202 movs r2, #2 8004128: 63da str r2, [r3, #60] @ 0x3c /* Update error code */ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; 800412a: 687b ldr r3, [r7, #4] 800412c: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 8004130: f043 0202 orr.w r2, r3, #2 8004134: 687b ldr r3, [r7, #4] 8004136: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_ERROR; 800413a: 687b ldr r3, [r7, #4] 800413c: 2204 movs r2, #4 800413e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 8004142: 687b ldr r3, [r7, #4] 8004144: 2200 movs r2, #0 8004146: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ hltdc->ErrorCallback(hltdc); #else /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); 800414a: 6878 ldr r0, [r7, #4] 800414c: f000 f846 bl 80041dc #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Line Interrupt management ************************************************/ if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) 8004150: 68fb ldr r3, [r7, #12] 8004152: f003 0301 and.w r3, r3, #1 8004156: 2b00 cmp r3, #0 8004158: d01b beq.n 8004192 800415a: 68bb ldr r3, [r7, #8] 800415c: f003 0301 and.w r3, r3, #1 8004160: 2b00 cmp r3, #0 8004162: d016 beq.n 8004192 { /* Disable the Line interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); 8004164: 687b ldr r3, [r7, #4] 8004166: 681b ldr r3, [r3, #0] 8004168: 6b5a ldr r2, [r3, #52] @ 0x34 800416a: 687b ldr r3, [r7, #4] 800416c: 681b ldr r3, [r3, #0] 800416e: f022 0201 bic.w r2, r2, #1 8004172: 635a str r2, [r3, #52] @ 0x34 /* Clear the Line interrupt flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); 8004174: 687b ldr r3, [r7, #4] 8004176: 681b ldr r3, [r3, #0] 8004178: 2201 movs r2, #1 800417a: 63da str r2, [r3, #60] @ 0x3c /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; 800417c: 687b ldr r3, [r7, #4] 800417e: 2201 movs r2, #1 8004180: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 8004184: 687b ldr r3, [r7, #4] 8004186: 2200 movs r2, #0 8004188: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered Line Event callback */ hltdc->LineEventCallback(hltdc); #else /*Call Legacy Line Event callback */ HAL_LTDC_LineEventCallback(hltdc); 800418c: 6878 ldr r0, [r7, #4] 800418e: f000 f82f bl 80041f0 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Register reload Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) 8004192: 68fb ldr r3, [r7, #12] 8004194: f003 0308 and.w r3, r3, #8 8004198: 2b00 cmp r3, #0 800419a: d01b beq.n 80041d4 800419c: 68bb ldr r3, [r7, #8] 800419e: f003 0308 and.w r3, r3, #8 80041a2: 2b00 cmp r3, #0 80041a4: d016 beq.n 80041d4 { /* Disable the register reload interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); 80041a6: 687b ldr r3, [r7, #4] 80041a8: 681b ldr r3, [r3, #0] 80041aa: 6b5a ldr r2, [r3, #52] @ 0x34 80041ac: 687b ldr r3, [r7, #4] 80041ae: 681b ldr r3, [r3, #0] 80041b0: f022 0208 bic.w r2, r2, #8 80041b4: 635a str r2, [r3, #52] @ 0x34 /* Clear the register reload flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); 80041b6: 687b ldr r3, [r7, #4] 80041b8: 681b ldr r3, [r3, #0] 80041ba: 2208 movs r2, #8 80041bc: 63da str r2, [r3, #60] @ 0x3c /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; 80041be: 687b ldr r3, [r7, #4] 80041c0: 2201 movs r2, #1 80041c2: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 80041c6: 687b ldr r3, [r7, #4] 80041c8: 2200 movs r2, #0 80041ca: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered reload Event callback */ hltdc->ReloadEventCallback(hltdc); #else /*Call Legacy Reload Event callback */ HAL_LTDC_ReloadEventCallback(hltdc); 80041ce: 6878 ldr r0, [r7, #4] 80041d0: f000 f818 bl 8004204 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } } 80041d4: bf00 nop 80041d6: 3710 adds r7, #16 80041d8: 46bd mov sp, r7 80041da: bd80 pop {r7, pc} 080041dc : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) { 80041dc: b480 push {r7} 80041de: b083 sub sp, #12 80041e0: af00 add r7, sp, #0 80041e2: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ErrorCallback could be implemented in the user file */ } 80041e4: bf00 nop 80041e6: 370c adds r7, #12 80041e8: 46bd mov sp, r7 80041ea: f85d 7b04 ldr.w r7, [sp], #4 80041ee: 4770 bx lr 080041f0 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) { 80041f0: b480 push {r7} 80041f2: b083 sub sp, #12 80041f4: af00 add r7, sp, #0 80041f6: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_LineEventCallback could be implemented in the user file */ } 80041f8: bf00 nop 80041fa: 370c adds r7, #12 80041fc: 46bd mov sp, r7 80041fe: f85d 7b04 ldr.w r7, [sp], #4 8004202: 4770 bx lr 08004204 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) { 8004204: b480 push {r7} 8004206: b083 sub sp, #12 8004208: af00 add r7, sp, #0 800420a: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ReloadEvenCallback could be implemented in the user file */ } 800420c: bf00 nop 800420e: 370c adds r7, #12 8004210: 46bd mov sp, r7 8004212: f85d 7b04 ldr.w r7, [sp], #4 8004216: 4770 bx lr 08004218 : * This parameter can be one of the following values: * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { 8004218: b5b0 push {r4, r5, r7, lr} 800421a: b084 sub sp, #16 800421c: af00 add r7, sp, #0 800421e: 60f8 str r0, [r7, #12] 8004220: 60b9 str r1, [r7, #8] 8004222: 607a str r2, [r7, #4] assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); 8004224: 68fb ldr r3, [r7, #12] 8004226: f893 30a0 ldrb.w r3, [r3, #160] @ 0xa0 800422a: 2b01 cmp r3, #1 800422c: d101 bne.n 8004232 800422e: 2302 movs r3, #2 8004230: e02c b.n 800428c 8004232: 68fb ldr r3, [r7, #12] 8004234: 2201 movs r2, #1 8004236: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; 800423a: 68fb ldr r3, [r7, #12] 800423c: 2202 movs r2, #2 800423e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Copy new layer configuration into handle structure */ hltdc->LayerCfg[LayerIdx] = *pLayerCfg; 8004242: 68fa ldr r2, [r7, #12] 8004244: 687b ldr r3, [r7, #4] 8004246: 2134 movs r1, #52 @ 0x34 8004248: fb01 f303 mul.w r3, r1, r3 800424c: 4413 add r3, r2 800424e: f103 0238 add.w r2, r3, #56 @ 0x38 8004252: 68bb ldr r3, [r7, #8] 8004254: 4614 mov r4, r2 8004256: 461d mov r5, r3 8004258: cd0f ldmia r5!, {r0, r1, r2, r3} 800425a: c40f stmia r4!, {r0, r1, r2, r3} 800425c: cd0f ldmia r5!, {r0, r1, r2, r3} 800425e: c40f stmia r4!, {r0, r1, r2, r3} 8004260: cd0f ldmia r5!, {r0, r1, r2, r3} 8004262: c40f stmia r4!, {r0, r1, r2, r3} 8004264: 682b ldr r3, [r5, #0] 8004266: 6023 str r3, [r4, #0] /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); 8004268: 687a ldr r2, [r7, #4] 800426a: 68b9 ldr r1, [r7, #8] 800426c: 68f8 ldr r0, [r7, #12] 800426e: f000 f811 bl 8004294 /* Set the Immediate Reload type */ hltdc->Instance->SRCR = LTDC_SRCR_IMR; 8004272: 68fb ldr r3, [r7, #12] 8004274: 681b ldr r3, [r3, #0] 8004276: 2201 movs r2, #1 8004278: 625a str r2, [r3, #36] @ 0x24 /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; 800427a: 68fb ldr r3, [r7, #12] 800427c: 2201 movs r2, #1 800427e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 8004282: 68fb ldr r3, [r7, #12] 8004284: 2200 movs r2, #0 8004286: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 return HAL_OK; 800428a: 2300 movs r3, #0 } 800428c: 4618 mov r0, r3 800428e: 3710 adds r7, #16 8004290: 46bd mov sp, r7 8004292: bdb0 pop {r4, r5, r7, pc} 08004294 : * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval None */ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { 8004294: b480 push {r7} 8004296: b089 sub sp, #36 @ 0x24 8004298: af00 add r7, sp, #0 800429a: 60f8 str r0, [r7, #12] 800429c: 60b9 str r1, [r7, #8] 800429e: 607a str r2, [r7, #4] uint32_t tmp; uint32_t tmp1; uint32_t tmp2; /* Configure the horizontal start and stop position */ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); 80042a0: 68bb ldr r3, [r7, #8] 80042a2: 685a ldr r2, [r3, #4] 80042a4: 68fb ldr r3, [r7, #12] 80042a6: 681b ldr r3, [r3, #0] 80042a8: 68db ldr r3, [r3, #12] 80042aa: 0c1b lsrs r3, r3, #16 80042ac: f3c3 030b ubfx r3, r3, #0, #12 80042b0: 4413 add r3, r2 80042b2: 041b lsls r3, r3, #16 80042b4: 61fb str r3, [r7, #28] LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); 80042b6: 68fb ldr r3, [r7, #12] 80042b8: 681b ldr r3, [r3, #0] 80042ba: 461a mov r2, r3 80042bc: 687b ldr r3, [r7, #4] 80042be: 01db lsls r3, r3, #7 80042c0: 4413 add r3, r2 80042c2: 3384 adds r3, #132 @ 0x84 80042c4: 685b ldr r3, [r3, #4] 80042c6: 68fa ldr r2, [r7, #12] 80042c8: 6812 ldr r2, [r2, #0] 80042ca: 4611 mov r1, r2 80042cc: 687a ldr r2, [r7, #4] 80042ce: 01d2 lsls r2, r2, #7 80042d0: 440a add r2, r1 80042d2: 3284 adds r2, #132 @ 0x84 80042d4: f403 4370 and.w r3, r3, #61440 @ 0xf000 80042d8: 6053 str r3, [r2, #4] LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042da: 68bb ldr r3, [r7, #8] 80042dc: 681a ldr r2, [r3, #0] ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 80042de: 68fb ldr r3, [r7, #12] 80042e0: 681b ldr r3, [r3, #0] 80042e2: 68db ldr r3, [r3, #12] 80042e4: 0c1b lsrs r3, r3, #16 80042e6: f3c3 030b ubfx r3, r3, #0, #12 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042ea: 4413 add r3, r2 ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 80042ec: 1c5a adds r2, r3, #1 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042ee: 68fb ldr r3, [r7, #12] 80042f0: 681b ldr r3, [r3, #0] 80042f2: 4619 mov r1, r3 80042f4: 687b ldr r3, [r7, #4] 80042f6: 01db lsls r3, r3, #7 80042f8: 440b add r3, r1 80042fa: 3384 adds r3, #132 @ 0x84 80042fc: 4619 mov r1, r3 ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 80042fe: 69fb ldr r3, [r7, #28] 8004300: 4313 orrs r3, r2 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 8004302: 604b str r3, [r1, #4] /* Configure the vertical start and stop position */ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); 8004304: 68bb ldr r3, [r7, #8] 8004306: 68da ldr r2, [r3, #12] 8004308: 68fb ldr r3, [r7, #12] 800430a: 681b ldr r3, [r3, #0] 800430c: 68db ldr r3, [r3, #12] 800430e: f3c3 030a ubfx r3, r3, #0, #11 8004312: 4413 add r3, r2 8004314: 041b lsls r3, r3, #16 8004316: 61fb str r3, [r7, #28] LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); 8004318: 68fb ldr r3, [r7, #12] 800431a: 681b ldr r3, [r3, #0] 800431c: 461a mov r2, r3 800431e: 687b ldr r3, [r7, #4] 8004320: 01db lsls r3, r3, #7 8004322: 4413 add r3, r2 8004324: 3384 adds r3, #132 @ 0x84 8004326: 689b ldr r3, [r3, #8] 8004328: 68fa ldr r2, [r7, #12] 800432a: 6812 ldr r2, [r2, #0] 800432c: 4611 mov r1, r2 800432e: 687a ldr r2, [r7, #4] 8004330: 01d2 lsls r2, r2, #7 8004332: 440a add r2, r1 8004334: 3284 adds r2, #132 @ 0x84 8004336: f403 4370 and.w r3, r3, #61440 @ 0xf000 800433a: 6093 str r3, [r2, #8] LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); 800433c: 68bb ldr r3, [r7, #8] 800433e: 689a ldr r2, [r3, #8] 8004340: 68fb ldr r3, [r7, #12] 8004342: 681b ldr r3, [r3, #0] 8004344: 68db ldr r3, [r3, #12] 8004346: f3c3 030a ubfx r3, r3, #0, #11 800434a: 4413 add r3, r2 800434c: 1c5a adds r2, r3, #1 800434e: 68fb ldr r3, [r7, #12] 8004350: 681b ldr r3, [r3, #0] 8004352: 4619 mov r1, r3 8004354: 687b ldr r3, [r7, #4] 8004356: 01db lsls r3, r3, #7 8004358: 440b add r3, r1 800435a: 3384 adds r3, #132 @ 0x84 800435c: 4619 mov r1, r3 800435e: 69fb ldr r3, [r7, #28] 8004360: 4313 orrs r3, r2 8004362: 608b str r3, [r1, #8] /* Specifies the pixel format */ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); 8004364: 68fb ldr r3, [r7, #12] 8004366: 681b ldr r3, [r3, #0] 8004368: 461a mov r2, r3 800436a: 687b ldr r3, [r7, #4] 800436c: 01db lsls r3, r3, #7 800436e: 4413 add r3, r2 8004370: 3384 adds r3, #132 @ 0x84 8004372: 691b ldr r3, [r3, #16] 8004374: 68fa ldr r2, [r7, #12] 8004376: 6812 ldr r2, [r2, #0] 8004378: 4611 mov r1, r2 800437a: 687a ldr r2, [r7, #4] 800437c: 01d2 lsls r2, r2, #7 800437e: 440a add r2, r1 8004380: 3284 adds r2, #132 @ 0x84 8004382: f023 0307 bic.w r3, r3, #7 8004386: 6113 str r3, [r2, #16] LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); 8004388: 68fb ldr r3, [r7, #12] 800438a: 681b ldr r3, [r3, #0] 800438c: 461a mov r2, r3 800438e: 687b ldr r3, [r7, #4] 8004390: 01db lsls r3, r3, #7 8004392: 4413 add r3, r2 8004394: 3384 adds r3, #132 @ 0x84 8004396: 461a mov r2, r3 8004398: 68bb ldr r3, [r7, #8] 800439a: 691b ldr r3, [r3, #16] 800439c: 6113 str r3, [r2, #16] /* Configure the default color values */ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); 800439e: 68bb ldr r3, [r7, #8] 80043a0: f893 3031 ldrb.w r3, [r3, #49] @ 0x31 80043a4: 021b lsls r3, r3, #8 80043a6: 61fb str r3, [r7, #28] tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); 80043a8: 68bb ldr r3, [r7, #8] 80043aa: f893 3032 ldrb.w r3, [r3, #50] @ 0x32 80043ae: 041b lsls r3, r3, #16 80043b0: 61bb str r3, [r7, #24] tmp2 = (pLayerCfg->Alpha0 << 24U); 80043b2: 68bb ldr r3, [r7, #8] 80043b4: 699b ldr r3, [r3, #24] 80043b6: 061b lsls r3, r3, #24 80043b8: 617b str r3, [r7, #20] WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); 80043ba: 68bb ldr r3, [r7, #8] 80043bc: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 80043c0: 461a mov r2, r3 80043c2: 69fb ldr r3, [r7, #28] 80043c4: 431a orrs r2, r3 80043c6: 69bb ldr r3, [r7, #24] 80043c8: 431a orrs r2, r3 80043ca: 68fb ldr r3, [r7, #12] 80043cc: 681b ldr r3, [r3, #0] 80043ce: 4619 mov r1, r3 80043d0: 687b ldr r3, [r7, #4] 80043d2: 01db lsls r3, r3, #7 80043d4: 440b add r3, r1 80043d6: 3384 adds r3, #132 @ 0x84 80043d8: 4619 mov r1, r3 80043da: 697b ldr r3, [r7, #20] 80043dc: 4313 orrs r3, r2 80043de: 618b str r3, [r1, #24] /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); 80043e0: 68fb ldr r3, [r7, #12] 80043e2: 681b ldr r3, [r3, #0] 80043e4: 461a mov r2, r3 80043e6: 687b ldr r3, [r7, #4] 80043e8: 01db lsls r3, r3, #7 80043ea: 4413 add r3, r2 80043ec: 3384 adds r3, #132 @ 0x84 80043ee: 695b ldr r3, [r3, #20] 80043f0: 68fa ldr r2, [r7, #12] 80043f2: 6812 ldr r2, [r2, #0] 80043f4: 4611 mov r1, r2 80043f6: 687a ldr r2, [r7, #4] 80043f8: 01d2 lsls r2, r2, #7 80043fa: 440a add r2, r1 80043fc: 3284 adds r2, #132 @ 0x84 80043fe: f023 03ff bic.w r3, r3, #255 @ 0xff 8004402: 6153 str r3, [r2, #20] LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); 8004404: 68fb ldr r3, [r7, #12] 8004406: 681b ldr r3, [r3, #0] 8004408: 461a mov r2, r3 800440a: 687b ldr r3, [r7, #4] 800440c: 01db lsls r3, r3, #7 800440e: 4413 add r3, r2 8004410: 3384 adds r3, #132 @ 0x84 8004412: 461a mov r2, r3 8004414: 68bb ldr r3, [r7, #8] 8004416: 695b ldr r3, [r3, #20] 8004418: 6153 str r3, [r2, #20] /* Specifies the blending factors */ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); 800441a: 68fb ldr r3, [r7, #12] 800441c: 681b ldr r3, [r3, #0] 800441e: 461a mov r2, r3 8004420: 687b ldr r3, [r7, #4] 8004422: 01db lsls r3, r3, #7 8004424: 4413 add r3, r2 8004426: 3384 adds r3, #132 @ 0x84 8004428: 69db ldr r3, [r3, #28] 800442a: 68fa ldr r2, [r7, #12] 800442c: 6812 ldr r2, [r2, #0] 800442e: 4611 mov r1, r2 8004430: 687a ldr r2, [r7, #4] 8004432: 01d2 lsls r2, r2, #7 8004434: 440a add r2, r1 8004436: 3284 adds r2, #132 @ 0x84 8004438: f423 63e0 bic.w r3, r3, #1792 @ 0x700 800443c: f023 0307 bic.w r3, r3, #7 8004440: 61d3 str r3, [r2, #28] LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); 8004442: 68bb ldr r3, [r7, #8] 8004444: 69da ldr r2, [r3, #28] 8004446: 68bb ldr r3, [r7, #8] 8004448: 6a1b ldr r3, [r3, #32] 800444a: 68f9 ldr r1, [r7, #12] 800444c: 6809 ldr r1, [r1, #0] 800444e: 4608 mov r0, r1 8004450: 6879 ldr r1, [r7, #4] 8004452: 01c9 lsls r1, r1, #7 8004454: 4401 add r1, r0 8004456: 3184 adds r1, #132 @ 0x84 8004458: 4313 orrs r3, r2 800445a: 61cb str r3, [r1, #28] /* Configure the color frame buffer start address */ WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); 800445c: 68fb ldr r3, [r7, #12] 800445e: 681b ldr r3, [r3, #0] 8004460: 461a mov r2, r3 8004462: 687b ldr r3, [r7, #4] 8004464: 01db lsls r3, r3, #7 8004466: 4413 add r3, r2 8004468: 3384 adds r3, #132 @ 0x84 800446a: 461a mov r2, r3 800446c: 68bb ldr r3, [r7, #8] 800446e: 6a5b ldr r3, [r3, #36] @ 0x24 8004470: 6293 str r3, [r2, #40] @ 0x28 if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) 8004472: 68bb ldr r3, [r7, #8] 8004474: 691b ldr r3, [r3, #16] 8004476: 2b00 cmp r3, #0 8004478: d102 bne.n 8004480 { tmp = 4U; 800447a: 2304 movs r3, #4 800447c: 61fb str r3, [r7, #28] 800447e: e01b b.n 80044b8 } else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) 8004480: 68bb ldr r3, [r7, #8] 8004482: 691b ldr r3, [r3, #16] 8004484: 2b01 cmp r3, #1 8004486: d102 bne.n 800448e { tmp = 3U; 8004488: 2303 movs r3, #3 800448a: 61fb str r3, [r7, #28] 800448c: e014 b.n 80044b8 } else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ 800448e: 68bb ldr r3, [r7, #8] 8004490: 691b ldr r3, [r3, #16] 8004492: 2b04 cmp r3, #4 8004494: d00b beq.n 80044ae (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ 8004496: 68bb ldr r3, [r7, #8] 8004498: 691b ldr r3, [r3, #16] else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ 800449a: 2b02 cmp r3, #2 800449c: d007 beq.n 80044ae (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ 800449e: 68bb ldr r3, [r7, #8] 80044a0: 691b ldr r3, [r3, #16] (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ 80044a2: 2b03 cmp r3, #3 80044a4: d003 beq.n 80044ae (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) 80044a6: 68bb ldr r3, [r7, #8] 80044a8: 691b ldr r3, [r3, #16] (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ 80044aa: 2b07 cmp r3, #7 80044ac: d102 bne.n 80044b4 { tmp = 2U; 80044ae: 2302 movs r3, #2 80044b0: 61fb str r3, [r7, #28] 80044b2: e001 b.n 80044b8 } else { tmp = 1U; 80044b4: 2301 movs r3, #1 80044b6: 61fb str r3, [r7, #28] } /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); 80044b8: 68fb ldr r3, [r7, #12] 80044ba: 681b ldr r3, [r3, #0] 80044bc: 461a mov r2, r3 80044be: 687b ldr r3, [r7, #4] 80044c0: 01db lsls r3, r3, #7 80044c2: 4413 add r3, r2 80044c4: 3384 adds r3, #132 @ 0x84 80044c6: 6adb ldr r3, [r3, #44] @ 0x2c 80044c8: 68fa ldr r2, [r7, #12] 80044ca: 6812 ldr r2, [r2, #0] 80044cc: 4611 mov r1, r2 80044ce: 687a ldr r2, [r7, #4] 80044d0: 01d2 lsls r2, r2, #7 80044d2: 440a add r2, r1 80044d4: 3284 adds r2, #132 @ 0x84 80044d6: f003 23e0 and.w r3, r3, #3758153728 @ 0xe000e000 80044da: 62d3 str r3, [r2, #44] @ 0x2c LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ 80044dc: 68bb ldr r3, [r7, #8] 80044de: 6a9b ldr r3, [r3, #40] @ 0x28 80044e0: 69fa ldr r2, [r7, #28] 80044e2: fb02 f303 mul.w r3, r2, r3 80044e6: 041a lsls r2, r3, #16 (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); 80044e8: 68bb ldr r3, [r7, #8] 80044ea: 6859 ldr r1, [r3, #4] 80044ec: 68bb ldr r3, [r7, #8] 80044ee: 681b ldr r3, [r3, #0] 80044f0: 1acb subs r3, r1, r3 80044f2: 69f9 ldr r1, [r7, #28] 80044f4: fb01 f303 mul.w r3, r1, r3 80044f8: 3303 adds r3, #3 LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ 80044fa: 68f9 ldr r1, [r7, #12] 80044fc: 6809 ldr r1, [r1, #0] 80044fe: 4608 mov r0, r1 8004500: 6879 ldr r1, [r7, #4] 8004502: 01c9 lsls r1, r1, #7 8004504: 4401 add r1, r0 8004506: 3184 adds r1, #132 @ 0x84 8004508: 4313 orrs r3, r2 800450a: 62cb str r3, [r1, #44] @ 0x2c /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); 800450c: 68fb ldr r3, [r7, #12] 800450e: 681b ldr r3, [r3, #0] 8004510: 461a mov r2, r3 8004512: 687b ldr r3, [r7, #4] 8004514: 01db lsls r3, r3, #7 8004516: 4413 add r3, r2 8004518: 3384 adds r3, #132 @ 0x84 800451a: 6b1b ldr r3, [r3, #48] @ 0x30 800451c: 68fa ldr r2, [r7, #12] 800451e: 6812 ldr r2, [r2, #0] 8004520: 4611 mov r1, r2 8004522: 687a ldr r2, [r7, #4] 8004524: 01d2 lsls r2, r2, #7 8004526: 440a add r2, r1 8004528: 3284 adds r2, #132 @ 0x84 800452a: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 800452e: f023 0307 bic.w r3, r3, #7 8004532: 6313 str r3, [r2, #48] @ 0x30 LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); 8004534: 68fb ldr r3, [r7, #12] 8004536: 681b ldr r3, [r3, #0] 8004538: 461a mov r2, r3 800453a: 687b ldr r3, [r7, #4] 800453c: 01db lsls r3, r3, #7 800453e: 4413 add r3, r2 8004540: 3384 adds r3, #132 @ 0x84 8004542: 461a mov r2, r3 8004544: 68bb ldr r3, [r7, #8] 8004546: 6adb ldr r3, [r3, #44] @ 0x2c 8004548: 6313 str r3, [r2, #48] @ 0x30 /* Enable LTDC_Layer by setting LEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; 800454a: 68fb ldr r3, [r7, #12] 800454c: 681b ldr r3, [r3, #0] 800454e: 461a mov r2, r3 8004550: 687b ldr r3, [r7, #4] 8004552: 01db lsls r3, r3, #7 8004554: 4413 add r3, r2 8004556: 3384 adds r3, #132 @ 0x84 8004558: 681b ldr r3, [r3, #0] 800455a: 68fa ldr r2, [r7, #12] 800455c: 6812 ldr r2, [r2, #0] 800455e: 4611 mov r1, r2 8004560: 687a ldr r2, [r7, #4] 8004562: 01d2 lsls r2, r2, #7 8004564: 440a add r2, r1 8004566: 3284 adds r2, #132 @ 0x84 8004568: f043 0301 orr.w r3, r3, #1 800456c: 6013 str r3, [r2, #0] } 800456e: bf00 nop 8004570: 3724 adds r7, #36 @ 0x24 8004572: 46bd mov sp, r7 8004574: f85d 7b04 ldr.w r7, [sp], #4 8004578: 4770 bx lr ... 0800457c : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 800457c: b580 push {r7, lr} 800457e: b086 sub sp, #24 8004580: af00 add r7, sp, #0 8004582: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004584: 687b ldr r3, [r7, #4] 8004586: 2b00 cmp r3, #0 8004588: d101 bne.n 800458e { return HAL_ERROR; 800458a: 2301 movs r3, #1 800458c: e267 b.n 8004a5e } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 800458e: 687b ldr r3, [r7, #4] 8004590: 681b ldr r3, [r3, #0] 8004592: f003 0301 and.w r3, r3, #1 8004596: 2b00 cmp r3, #0 8004598: d075 beq.n 8004686 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 800459a: 4b88 ldr r3, [pc, #544] @ (80047bc ) 800459c: 689b ldr r3, [r3, #8] 800459e: f003 030c and.w r3, r3, #12 80045a2: 2b04 cmp r3, #4 80045a4: d00c beq.n 80045c0 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 80045a6: 4b85 ldr r3, [pc, #532] @ (80047bc ) 80045a8: 689b ldr r3, [r3, #8] 80045aa: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 80045ae: 2b08 cmp r3, #8 80045b0: d112 bne.n 80045d8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 80045b2: 4b82 ldr r3, [pc, #520] @ (80047bc ) 80045b4: 685b ldr r3, [r3, #4] 80045b6: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80045ba: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 80045be: d10b bne.n 80045d8 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 80045c0: 4b7e ldr r3, [pc, #504] @ (80047bc ) 80045c2: 681b ldr r3, [r3, #0] 80045c4: f403 3300 and.w r3, r3, #131072 @ 0x20000 80045c8: 2b00 cmp r3, #0 80045ca: d05b beq.n 8004684 80045cc: 687b ldr r3, [r7, #4] 80045ce: 685b ldr r3, [r3, #4] 80045d0: 2b00 cmp r3, #0 80045d2: d157 bne.n 8004684 { return HAL_ERROR; 80045d4: 2301 movs r3, #1 80045d6: e242 b.n 8004a5e } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 80045d8: 687b ldr r3, [r7, #4] 80045da: 685b ldr r3, [r3, #4] 80045dc: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 80045e0: d106 bne.n 80045f0 80045e2: 4b76 ldr r3, [pc, #472] @ (80047bc ) 80045e4: 681b ldr r3, [r3, #0] 80045e6: 4a75 ldr r2, [pc, #468] @ (80047bc ) 80045e8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80045ec: 6013 str r3, [r2, #0] 80045ee: e01d b.n 800462c 80045f0: 687b ldr r3, [r7, #4] 80045f2: 685b ldr r3, [r3, #4] 80045f4: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80045f8: d10c bne.n 8004614 80045fa: 4b70 ldr r3, [pc, #448] @ (80047bc ) 80045fc: 681b ldr r3, [r3, #0] 80045fe: 4a6f ldr r2, [pc, #444] @ (80047bc ) 8004600: f443 2380 orr.w r3, r3, #262144 @ 0x40000 8004604: 6013 str r3, [r2, #0] 8004606: 4b6d ldr r3, [pc, #436] @ (80047bc ) 8004608: 681b ldr r3, [r3, #0] 800460a: 4a6c ldr r2, [pc, #432] @ (80047bc ) 800460c: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8004610: 6013 str r3, [r2, #0] 8004612: e00b b.n 800462c 8004614: 4b69 ldr r3, [pc, #420] @ (80047bc ) 8004616: 681b ldr r3, [r3, #0] 8004618: 4a68 ldr r2, [pc, #416] @ (80047bc ) 800461a: f423 3380 bic.w r3, r3, #65536 @ 0x10000 800461e: 6013 str r3, [r2, #0] 8004620: 4b66 ldr r3, [pc, #408] @ (80047bc ) 8004622: 681b ldr r3, [r3, #0] 8004624: 4a65 ldr r2, [pc, #404] @ (80047bc ) 8004626: f423 2380 bic.w r3, r3, #262144 @ 0x40000 800462a: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 800462c: 687b ldr r3, [r7, #4] 800462e: 685b ldr r3, [r3, #4] 8004630: 2b00 cmp r3, #0 8004632: d013 beq.n 800465c { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004634: f7fd f856 bl 80016e4 8004638: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800463a: e008 b.n 800464e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800463c: f7fd f852 bl 80016e4 8004640: 4602 mov r2, r0 8004642: 693b ldr r3, [r7, #16] 8004644: 1ad3 subs r3, r2, r3 8004646: 2b64 cmp r3, #100 @ 0x64 8004648: d901 bls.n 800464e { return HAL_TIMEOUT; 800464a: 2303 movs r3, #3 800464c: e207 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 800464e: 4b5b ldr r3, [pc, #364] @ (80047bc ) 8004650: 681b ldr r3, [r3, #0] 8004652: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004656: 2b00 cmp r3, #0 8004658: d0f0 beq.n 800463c 800465a: e014 b.n 8004686 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800465c: f7fd f842 bl 80016e4 8004660: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004662: e008 b.n 8004676 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8004664: f7fd f83e bl 80016e4 8004668: 4602 mov r2, r0 800466a: 693b ldr r3, [r7, #16] 800466c: 1ad3 subs r3, r2, r3 800466e: 2b64 cmp r3, #100 @ 0x64 8004670: d901 bls.n 8004676 { return HAL_TIMEOUT; 8004672: 2303 movs r3, #3 8004674: e1f3 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 8004676: 4b51 ldr r3, [pc, #324] @ (80047bc ) 8004678: 681b ldr r3, [r3, #0] 800467a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800467e: 2b00 cmp r3, #0 8004680: d1f0 bne.n 8004664 8004682: e000 b.n 8004686 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004684: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004686: 687b ldr r3, [r7, #4] 8004688: 681b ldr r3, [r3, #0] 800468a: f003 0302 and.w r3, r3, #2 800468e: 2b00 cmp r3, #0 8004690: d063 beq.n 800475a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 8004692: 4b4a ldr r3, [pc, #296] @ (80047bc ) 8004694: 689b ldr r3, [r3, #8] 8004696: f003 030c and.w r3, r3, #12 800469a: 2b00 cmp r3, #0 800469c: d00b beq.n 80046b6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 800469e: 4b47 ldr r3, [pc, #284] @ (80047bc ) 80046a0: 689b ldr r3, [r3, #8] 80046a2: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 80046a6: 2b08 cmp r3, #8 80046a8: d11c bne.n 80046e4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 80046aa: 4b44 ldr r3, [pc, #272] @ (80047bc ) 80046ac: 685b ldr r3, [r3, #4] 80046ae: f403 0380 and.w r3, r3, #4194304 @ 0x400000 80046b2: 2b00 cmp r3, #0 80046b4: d116 bne.n 80046e4 { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80046b6: 4b41 ldr r3, [pc, #260] @ (80047bc ) 80046b8: 681b ldr r3, [r3, #0] 80046ba: f003 0302 and.w r3, r3, #2 80046be: 2b00 cmp r3, #0 80046c0: d005 beq.n 80046ce 80046c2: 687b ldr r3, [r7, #4] 80046c4: 68db ldr r3, [r3, #12] 80046c6: 2b01 cmp r3, #1 80046c8: d001 beq.n 80046ce { return HAL_ERROR; 80046ca: 2301 movs r3, #1 80046cc: e1c7 b.n 8004a5e } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80046ce: 4b3b ldr r3, [pc, #236] @ (80047bc ) 80046d0: 681b ldr r3, [r3, #0] 80046d2: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80046d6: 687b ldr r3, [r7, #4] 80046d8: 691b ldr r3, [r3, #16] 80046da: 00db lsls r3, r3, #3 80046dc: 4937 ldr r1, [pc, #220] @ (80047bc ) 80046de: 4313 orrs r3, r2 80046e0: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 80046e2: e03a b.n 800475a } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 80046e4: 687b ldr r3, [r7, #4] 80046e6: 68db ldr r3, [r3, #12] 80046e8: 2b00 cmp r3, #0 80046ea: d020 beq.n 800472e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80046ec: 4b34 ldr r3, [pc, #208] @ (80047c0 ) 80046ee: 2201 movs r2, #1 80046f0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80046f2: f7fc fff7 bl 80016e4 80046f6: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80046f8: e008 b.n 800470c { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80046fa: f7fc fff3 bl 80016e4 80046fe: 4602 mov r2, r0 8004700: 693b ldr r3, [r7, #16] 8004702: 1ad3 subs r3, r2, r3 8004704: 2b02 cmp r3, #2 8004706: d901 bls.n 800470c { return HAL_TIMEOUT; 8004708: 2303 movs r3, #3 800470a: e1a8 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 800470c: 4b2b ldr r3, [pc, #172] @ (80047bc ) 800470e: 681b ldr r3, [r3, #0] 8004710: f003 0302 and.w r3, r3, #2 8004714: 2b00 cmp r3, #0 8004716: d0f0 beq.n 80046fa } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004718: 4b28 ldr r3, [pc, #160] @ (80047bc ) 800471a: 681b ldr r3, [r3, #0] 800471c: f023 02f8 bic.w r2, r3, #248 @ 0xf8 8004720: 687b ldr r3, [r7, #4] 8004722: 691b ldr r3, [r3, #16] 8004724: 00db lsls r3, r3, #3 8004726: 4925 ldr r1, [pc, #148] @ (80047bc ) 8004728: 4313 orrs r3, r2 800472a: 600b str r3, [r1, #0] 800472c: e015 b.n 800475a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 800472e: 4b24 ldr r3, [pc, #144] @ (80047c0 ) 8004730: 2200 movs r2, #0 8004732: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004734: f7fc ffd6 bl 80016e4 8004738: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800473a: e008 b.n 800474e { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 800473c: f7fc ffd2 bl 80016e4 8004740: 4602 mov r2, r0 8004742: 693b ldr r3, [r7, #16] 8004744: 1ad3 subs r3, r2, r3 8004746: 2b02 cmp r3, #2 8004748: d901 bls.n 800474e { return HAL_TIMEOUT; 800474a: 2303 movs r3, #3 800474c: e187 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 800474e: 4b1b ldr r3, [pc, #108] @ (80047bc ) 8004750: 681b ldr r3, [r3, #0] 8004752: f003 0302 and.w r3, r3, #2 8004756: 2b00 cmp r3, #0 8004758: d1f0 bne.n 800473c } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 800475a: 687b ldr r3, [r7, #4] 800475c: 681b ldr r3, [r3, #0] 800475e: f003 0308 and.w r3, r3, #8 8004762: 2b00 cmp r3, #0 8004764: d036 beq.n 80047d4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 8004766: 687b ldr r3, [r7, #4] 8004768: 695b ldr r3, [r3, #20] 800476a: 2b00 cmp r3, #0 800476c: d016 beq.n 800479c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 800476e: 4b15 ldr r3, [pc, #84] @ (80047c4 ) 8004770: 2201 movs r2, #1 8004772: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004774: f7fc ffb6 bl 80016e4 8004778: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800477a: e008 b.n 800478e { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 800477c: f7fc ffb2 bl 80016e4 8004780: 4602 mov r2, r0 8004782: 693b ldr r3, [r7, #16] 8004784: 1ad3 subs r3, r2, r3 8004786: 2b02 cmp r3, #2 8004788: d901 bls.n 800478e { return HAL_TIMEOUT; 800478a: 2303 movs r3, #3 800478c: e167 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 800478e: 4b0b ldr r3, [pc, #44] @ (80047bc ) 8004790: 6f5b ldr r3, [r3, #116] @ 0x74 8004792: f003 0302 and.w r3, r3, #2 8004796: 2b00 cmp r3, #0 8004798: d0f0 beq.n 800477c 800479a: e01b b.n 80047d4 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 800479c: 4b09 ldr r3, [pc, #36] @ (80047c4 ) 800479e: 2200 movs r2, #0 80047a0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80047a2: f7fc ff9f bl 80016e4 80047a6: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80047a8: e00e b.n 80047c8 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 80047aa: f7fc ff9b bl 80016e4 80047ae: 4602 mov r2, r0 80047b0: 693b ldr r3, [r7, #16] 80047b2: 1ad3 subs r3, r2, r3 80047b4: 2b02 cmp r3, #2 80047b6: d907 bls.n 80047c8 { return HAL_TIMEOUT; 80047b8: 2303 movs r3, #3 80047ba: e150 b.n 8004a5e 80047bc: 40023800 .word 0x40023800 80047c0: 42470000 .word 0x42470000 80047c4: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 80047c8: 4b88 ldr r3, [pc, #544] @ (80049ec ) 80047ca: 6f5b ldr r3, [r3, #116] @ 0x74 80047cc: f003 0302 and.w r3, r3, #2 80047d0: 2b00 cmp r3, #0 80047d2: d1ea bne.n 80047aa } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 80047d4: 687b ldr r3, [r7, #4] 80047d6: 681b ldr r3, [r3, #0] 80047d8: f003 0304 and.w r3, r3, #4 80047dc: 2b00 cmp r3, #0 80047de: f000 8097 beq.w 8004910 { FlagStatus pwrclkchanged = RESET; 80047e2: 2300 movs r3, #0 80047e4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80047e6: 4b81 ldr r3, [pc, #516] @ (80049ec ) 80047e8: 6c1b ldr r3, [r3, #64] @ 0x40 80047ea: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80047ee: 2b00 cmp r3, #0 80047f0: d10f bne.n 8004812 { __HAL_RCC_PWR_CLK_ENABLE(); 80047f2: 2300 movs r3, #0 80047f4: 60bb str r3, [r7, #8] 80047f6: 4b7d ldr r3, [pc, #500] @ (80049ec ) 80047f8: 6c1b ldr r3, [r3, #64] @ 0x40 80047fa: 4a7c ldr r2, [pc, #496] @ (80049ec ) 80047fc: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8004800: 6413 str r3, [r2, #64] @ 0x40 8004802: 4b7a ldr r3, [pc, #488] @ (80049ec ) 8004804: 6c1b ldr r3, [r3, #64] @ 0x40 8004806: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800480a: 60bb str r3, [r7, #8] 800480c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 800480e: 2301 movs r3, #1 8004810: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004812: 4b77 ldr r3, [pc, #476] @ (80049f0 ) 8004814: 681b ldr r3, [r3, #0] 8004816: f403 7380 and.w r3, r3, #256 @ 0x100 800481a: 2b00 cmp r3, #0 800481c: d118 bne.n 8004850 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 800481e: 4b74 ldr r3, [pc, #464] @ (80049f0 ) 8004820: 681b ldr r3, [r3, #0] 8004822: 4a73 ldr r2, [pc, #460] @ (80049f0 ) 8004824: f443 7380 orr.w r3, r3, #256 @ 0x100 8004828: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 800482a: f7fc ff5b bl 80016e4 800482e: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004830: e008 b.n 8004844 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8004832: f7fc ff57 bl 80016e4 8004836: 4602 mov r2, r0 8004838: 693b ldr r3, [r7, #16] 800483a: 1ad3 subs r3, r2, r3 800483c: 2b02 cmp r3, #2 800483e: d901 bls.n 8004844 { return HAL_TIMEOUT; 8004840: 2303 movs r3, #3 8004842: e10c b.n 8004a5e while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 8004844: 4b6a ldr r3, [pc, #424] @ (80049f0 ) 8004846: 681b ldr r3, [r3, #0] 8004848: f403 7380 and.w r3, r3, #256 @ 0x100 800484c: 2b00 cmp r3, #0 800484e: d0f0 beq.n 8004832 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004850: 687b ldr r3, [r7, #4] 8004852: 689b ldr r3, [r3, #8] 8004854: 2b01 cmp r3, #1 8004856: d106 bne.n 8004866 8004858: 4b64 ldr r3, [pc, #400] @ (80049ec ) 800485a: 6f1b ldr r3, [r3, #112] @ 0x70 800485c: 4a63 ldr r2, [pc, #396] @ (80049ec ) 800485e: f043 0301 orr.w r3, r3, #1 8004862: 6713 str r3, [r2, #112] @ 0x70 8004864: e01c b.n 80048a0 8004866: 687b ldr r3, [r7, #4] 8004868: 689b ldr r3, [r3, #8] 800486a: 2b05 cmp r3, #5 800486c: d10c bne.n 8004888 800486e: 4b5f ldr r3, [pc, #380] @ (80049ec ) 8004870: 6f1b ldr r3, [r3, #112] @ 0x70 8004872: 4a5e ldr r2, [pc, #376] @ (80049ec ) 8004874: f043 0304 orr.w r3, r3, #4 8004878: 6713 str r3, [r2, #112] @ 0x70 800487a: 4b5c ldr r3, [pc, #368] @ (80049ec ) 800487c: 6f1b ldr r3, [r3, #112] @ 0x70 800487e: 4a5b ldr r2, [pc, #364] @ (80049ec ) 8004880: f043 0301 orr.w r3, r3, #1 8004884: 6713 str r3, [r2, #112] @ 0x70 8004886: e00b b.n 80048a0 8004888: 4b58 ldr r3, [pc, #352] @ (80049ec ) 800488a: 6f1b ldr r3, [r3, #112] @ 0x70 800488c: 4a57 ldr r2, [pc, #348] @ (80049ec ) 800488e: f023 0301 bic.w r3, r3, #1 8004892: 6713 str r3, [r2, #112] @ 0x70 8004894: 4b55 ldr r3, [pc, #340] @ (80049ec ) 8004896: 6f1b ldr r3, [r3, #112] @ 0x70 8004898: 4a54 ldr r2, [pc, #336] @ (80049ec ) 800489a: f023 0304 bic.w r3, r3, #4 800489e: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 80048a0: 687b ldr r3, [r7, #4] 80048a2: 689b ldr r3, [r3, #8] 80048a4: 2b00 cmp r3, #0 80048a6: d015 beq.n 80048d4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80048a8: f7fc ff1c bl 80016e4 80048ac: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80048ae: e00a b.n 80048c6 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80048b0: f7fc ff18 bl 80016e4 80048b4: 4602 mov r2, r0 80048b6: 693b ldr r3, [r7, #16] 80048b8: 1ad3 subs r3, r2, r3 80048ba: f241 3288 movw r2, #5000 @ 0x1388 80048be: 4293 cmp r3, r2 80048c0: d901 bls.n 80048c6 { return HAL_TIMEOUT; 80048c2: 2303 movs r3, #3 80048c4: e0cb b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80048c6: 4b49 ldr r3, [pc, #292] @ (80049ec ) 80048c8: 6f1b ldr r3, [r3, #112] @ 0x70 80048ca: f003 0302 and.w r3, r3, #2 80048ce: 2b00 cmp r3, #0 80048d0: d0ee beq.n 80048b0 80048d2: e014 b.n 80048fe } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 80048d4: f7fc ff06 bl 80016e4 80048d8: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80048da: e00a b.n 80048f2 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80048dc: f7fc ff02 bl 80016e4 80048e0: 4602 mov r2, r0 80048e2: 693b ldr r3, [r7, #16] 80048e4: 1ad3 subs r3, r2, r3 80048e6: f241 3288 movw r2, #5000 @ 0x1388 80048ea: 4293 cmp r3, r2 80048ec: d901 bls.n 80048f2 { return HAL_TIMEOUT; 80048ee: 2303 movs r3, #3 80048f0: e0b5 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80048f2: 4b3e ldr r3, [pc, #248] @ (80049ec ) 80048f4: 6f1b ldr r3, [r3, #112] @ 0x70 80048f6: f003 0302 and.w r3, r3, #2 80048fa: 2b00 cmp r3, #0 80048fc: d1ee bne.n 80048dc } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80048fe: 7dfb ldrb r3, [r7, #23] 8004900: 2b01 cmp r3, #1 8004902: d105 bne.n 8004910 { __HAL_RCC_PWR_CLK_DISABLE(); 8004904: 4b39 ldr r3, [pc, #228] @ (80049ec ) 8004906: 6c1b ldr r3, [r3, #64] @ 0x40 8004908: 4a38 ldr r2, [pc, #224] @ (80049ec ) 800490a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 800490e: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 8004910: 687b ldr r3, [r7, #4] 8004912: 699b ldr r3, [r3, #24] 8004914: 2b00 cmp r3, #0 8004916: f000 80a1 beq.w 8004a5c { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 800491a: 4b34 ldr r3, [pc, #208] @ (80049ec ) 800491c: 689b ldr r3, [r3, #8] 800491e: f003 030c and.w r3, r3, #12 8004922: 2b08 cmp r3, #8 8004924: d05c beq.n 80049e0 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 8004926: 687b ldr r3, [r7, #4] 8004928: 699b ldr r3, [r3, #24] 800492a: 2b02 cmp r3, #2 800492c: d141 bne.n 80049b2 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800492e: 4b31 ldr r3, [pc, #196] @ (80049f4 ) 8004930: 2200 movs r2, #0 8004932: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004934: f7fc fed6 bl 80016e4 8004938: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800493a: e008 b.n 800494e { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800493c: f7fc fed2 bl 80016e4 8004940: 4602 mov r2, r0 8004942: 693b ldr r3, [r7, #16] 8004944: 1ad3 subs r3, r2, r3 8004946: 2b02 cmp r3, #2 8004948: d901 bls.n 800494e { return HAL_TIMEOUT; 800494a: 2303 movs r3, #3 800494c: e087 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800494e: 4b27 ldr r3, [pc, #156] @ (80049ec ) 8004950: 681b ldr r3, [r3, #0] 8004952: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004956: 2b00 cmp r3, #0 8004958: d1f0 bne.n 800493c } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 800495a: 687b ldr r3, [r7, #4] 800495c: 69da ldr r2, [r3, #28] 800495e: 687b ldr r3, [r7, #4] 8004960: 6a1b ldr r3, [r3, #32] 8004962: 431a orrs r2, r3 8004964: 687b ldr r3, [r7, #4] 8004966: 6a5b ldr r3, [r3, #36] @ 0x24 8004968: 019b lsls r3, r3, #6 800496a: 431a orrs r2, r3 800496c: 687b ldr r3, [r7, #4] 800496e: 6a9b ldr r3, [r3, #40] @ 0x28 8004970: 085b lsrs r3, r3, #1 8004972: 3b01 subs r3, #1 8004974: 041b lsls r3, r3, #16 8004976: 431a orrs r2, r3 8004978: 687b ldr r3, [r7, #4] 800497a: 6adb ldr r3, [r3, #44] @ 0x2c 800497c: 061b lsls r3, r3, #24 800497e: 491b ldr r1, [pc, #108] @ (80049ec ) 8004980: 4313 orrs r3, r2 8004982: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8004984: 4b1b ldr r3, [pc, #108] @ (80049f4 ) 8004986: 2201 movs r2, #1 8004988: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800498a: f7fc feab bl 80016e4 800498e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004990: e008 b.n 80049a4 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004992: f7fc fea7 bl 80016e4 8004996: 4602 mov r2, r0 8004998: 693b ldr r3, [r7, #16] 800499a: 1ad3 subs r3, r2, r3 800499c: 2b02 cmp r3, #2 800499e: d901 bls.n 80049a4 { return HAL_TIMEOUT; 80049a0: 2303 movs r3, #3 80049a2: e05c b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 80049a4: 4b11 ldr r3, [pc, #68] @ (80049ec ) 80049a6: 681b ldr r3, [r3, #0] 80049a8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80049ac: 2b00 cmp r3, #0 80049ae: d0f0 beq.n 8004992 80049b0: e054 b.n 8004a5c } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80049b2: 4b10 ldr r3, [pc, #64] @ (80049f4 ) 80049b4: 2200 movs r2, #0 80049b6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80049b8: f7fc fe94 bl 80016e4 80049bc: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80049be: e008 b.n 80049d2 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80049c0: f7fc fe90 bl 80016e4 80049c4: 4602 mov r2, r0 80049c6: 693b ldr r3, [r7, #16] 80049c8: 1ad3 subs r3, r2, r3 80049ca: 2b02 cmp r3, #2 80049cc: d901 bls.n 80049d2 { return HAL_TIMEOUT; 80049ce: 2303 movs r3, #3 80049d0: e045 b.n 8004a5e while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80049d2: 4b06 ldr r3, [pc, #24] @ (80049ec ) 80049d4: 681b ldr r3, [r3, #0] 80049d6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 80049da: 2b00 cmp r3, #0 80049dc: d1f0 bne.n 80049c0 80049de: e03d b.n 8004a5c } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 80049e0: 687b ldr r3, [r7, #4] 80049e2: 699b ldr r3, [r3, #24] 80049e4: 2b01 cmp r3, #1 80049e6: d107 bne.n 80049f8 { return HAL_ERROR; 80049e8: 2301 movs r3, #1 80049ea: e038 b.n 8004a5e 80049ec: 40023800 .word 0x40023800 80049f0: 40007000 .word 0x40007000 80049f4: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80049f8: 4b1b ldr r3, [pc, #108] @ (8004a68 ) 80049fa: 685b ldr r3, [r3, #4] 80049fc: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80049fe: 687b ldr r3, [r7, #4] 8004a00: 699b ldr r3, [r3, #24] 8004a02: 2b01 cmp r3, #1 8004a04: d028 beq.n 8004a58 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004a06: 68fb ldr r3, [r7, #12] 8004a08: f403 0280 and.w r2, r3, #4194304 @ 0x400000 8004a0c: 687b ldr r3, [r7, #4] 8004a0e: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 8004a10: 429a cmp r2, r3 8004a12: d121 bne.n 8004a58 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8004a14: 68fb ldr r3, [r7, #12] 8004a16: f003 023f and.w r2, r3, #63 @ 0x3f 8004a1a: 687b ldr r3, [r7, #4] 8004a1c: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 8004a1e: 429a cmp r2, r3 8004a20: d11a bne.n 8004a58 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8004a22: 68fa ldr r2, [r7, #12] 8004a24: f647 73c0 movw r3, #32704 @ 0x7fc0 8004a28: 4013 ands r3, r2 8004a2a: 687a ldr r2, [r7, #4] 8004a2c: 6a52 ldr r2, [r2, #36] @ 0x24 8004a2e: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 8004a30: 4293 cmp r3, r2 8004a32: d111 bne.n 8004a58 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8004a34: 68fb ldr r3, [r7, #12] 8004a36: f403 3240 and.w r2, r3, #196608 @ 0x30000 8004a3a: 687b ldr r3, [r7, #4] 8004a3c: 6a9b ldr r3, [r3, #40] @ 0x28 8004a3e: 085b lsrs r3, r3, #1 8004a40: 3b01 subs r3, #1 8004a42: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 8004a44: 429a cmp r2, r3 8004a46: d107 bne.n 8004a58 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) 8004a48: 68fb ldr r3, [r7, #12] 8004a4a: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8004a4e: 687b ldr r3, [r7, #4] 8004a50: 6adb ldr r3, [r3, #44] @ 0x2c 8004a52: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8004a54: 429a cmp r2, r3 8004a56: d001 beq.n 8004a5c #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8004a58: 2301 movs r3, #1 8004a5a: e000 b.n 8004a5e } } } } return HAL_OK; 8004a5c: 2300 movs r3, #0 } 8004a5e: 4618 mov r0, r3 8004a60: 3718 adds r7, #24 8004a62: 46bd mov sp, r7 8004a64: bd80 pop {r7, pc} 8004a66: bf00 nop 8004a68: 40023800 .word 0x40023800 08004a6c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004a6c: b580 push {r7, lr} 8004a6e: b084 sub sp, #16 8004a70: af00 add r7, sp, #0 8004a72: 6078 str r0, [r7, #4] 8004a74: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8004a76: 687b ldr r3, [r7, #4] 8004a78: 2b00 cmp r3, #0 8004a7a: d101 bne.n 8004a80 { return HAL_ERROR; 8004a7c: 2301 movs r3, #1 8004a7e: e0cc b.n 8004c1a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004a80: 4b68 ldr r3, [pc, #416] @ (8004c24 ) 8004a82: 681b ldr r3, [r3, #0] 8004a84: f003 030f and.w r3, r3, #15 8004a88: 683a ldr r2, [r7, #0] 8004a8a: 429a cmp r2, r3 8004a8c: d90c bls.n 8004aa8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004a8e: 4b65 ldr r3, [pc, #404] @ (8004c24 ) 8004a90: 683a ldr r2, [r7, #0] 8004a92: b2d2 uxtb r2, r2 8004a94: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004a96: 4b63 ldr r3, [pc, #396] @ (8004c24 ) 8004a98: 681b ldr r3, [r3, #0] 8004a9a: f003 030f and.w r3, r3, #15 8004a9e: 683a ldr r2, [r7, #0] 8004aa0: 429a cmp r2, r3 8004aa2: d001 beq.n 8004aa8 { return HAL_ERROR; 8004aa4: 2301 movs r3, #1 8004aa6: e0b8 b.n 8004c1a } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004aa8: 687b ldr r3, [r7, #4] 8004aaa: 681b ldr r3, [r3, #0] 8004aac: f003 0302 and.w r3, r3, #2 8004ab0: 2b00 cmp r3, #0 8004ab2: d020 beq.n 8004af6 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004ab4: 687b ldr r3, [r7, #4] 8004ab6: 681b ldr r3, [r3, #0] 8004ab8: f003 0304 and.w r3, r3, #4 8004abc: 2b00 cmp r3, #0 8004abe: d005 beq.n 8004acc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004ac0: 4b59 ldr r3, [pc, #356] @ (8004c28 ) 8004ac2: 689b ldr r3, [r3, #8] 8004ac4: 4a58 ldr r2, [pc, #352] @ (8004c28 ) 8004ac6: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8004aca: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004acc: 687b ldr r3, [r7, #4] 8004ace: 681b ldr r3, [r3, #0] 8004ad0: f003 0308 and.w r3, r3, #8 8004ad4: 2b00 cmp r3, #0 8004ad6: d005 beq.n 8004ae4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004ad8: 4b53 ldr r3, [pc, #332] @ (8004c28 ) 8004ada: 689b ldr r3, [r3, #8] 8004adc: 4a52 ldr r2, [pc, #328] @ (8004c28 ) 8004ade: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004ae2: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004ae4: 4b50 ldr r3, [pc, #320] @ (8004c28 ) 8004ae6: 689b ldr r3, [r3, #8] 8004ae8: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004aec: 687b ldr r3, [r7, #4] 8004aee: 689b ldr r3, [r3, #8] 8004af0: 494d ldr r1, [pc, #308] @ (8004c28 ) 8004af2: 4313 orrs r3, r2 8004af4: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004af6: 687b ldr r3, [r7, #4] 8004af8: 681b ldr r3, [r3, #0] 8004afa: f003 0301 and.w r3, r3, #1 8004afe: 2b00 cmp r3, #0 8004b00: d044 beq.n 8004b8c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004b02: 687b ldr r3, [r7, #4] 8004b04: 685b ldr r3, [r3, #4] 8004b06: 2b01 cmp r3, #1 8004b08: d107 bne.n 8004b1a { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004b0a: 4b47 ldr r3, [pc, #284] @ (8004c28 ) 8004b0c: 681b ldr r3, [r3, #0] 8004b0e: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004b12: 2b00 cmp r3, #0 8004b14: d119 bne.n 8004b4a { return HAL_ERROR; 8004b16: 2301 movs r3, #1 8004b18: e07f b.n 8004c1a } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004b1a: 687b ldr r3, [r7, #4] 8004b1c: 685b ldr r3, [r3, #4] 8004b1e: 2b02 cmp r3, #2 8004b20: d003 beq.n 8004b2a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004b22: 687b ldr r3, [r7, #4] 8004b24: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004b26: 2b03 cmp r3, #3 8004b28: d107 bne.n 8004b3a { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004b2a: 4b3f ldr r3, [pc, #252] @ (8004c28 ) 8004b2c: 681b ldr r3, [r3, #0] 8004b2e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004b32: 2b00 cmp r3, #0 8004b34: d109 bne.n 8004b4a { return HAL_ERROR; 8004b36: 2301 movs r3, #1 8004b38: e06f b.n 8004c1a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004b3a: 4b3b ldr r3, [pc, #236] @ (8004c28 ) 8004b3c: 681b ldr r3, [r3, #0] 8004b3e: f003 0302 and.w r3, r3, #2 8004b42: 2b00 cmp r3, #0 8004b44: d101 bne.n 8004b4a { return HAL_ERROR; 8004b46: 2301 movs r3, #1 8004b48: e067 b.n 8004c1a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004b4a: 4b37 ldr r3, [pc, #220] @ (8004c28 ) 8004b4c: 689b ldr r3, [r3, #8] 8004b4e: f023 0203 bic.w r2, r3, #3 8004b52: 687b ldr r3, [r7, #4] 8004b54: 685b ldr r3, [r3, #4] 8004b56: 4934 ldr r1, [pc, #208] @ (8004c28 ) 8004b58: 4313 orrs r3, r2 8004b5a: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004b5c: f7fc fdc2 bl 80016e4 8004b60: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004b62: e00a b.n 8004b7a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004b64: f7fc fdbe bl 80016e4 8004b68: 4602 mov r2, r0 8004b6a: 68fb ldr r3, [r7, #12] 8004b6c: 1ad3 subs r3, r2, r3 8004b6e: f241 3288 movw r2, #5000 @ 0x1388 8004b72: 4293 cmp r3, r2 8004b74: d901 bls.n 8004b7a { return HAL_TIMEOUT; 8004b76: 2303 movs r3, #3 8004b78: e04f b.n 8004c1a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004b7a: 4b2b ldr r3, [pc, #172] @ (8004c28 ) 8004b7c: 689b ldr r3, [r3, #8] 8004b7e: f003 020c and.w r2, r3, #12 8004b82: 687b ldr r3, [r7, #4] 8004b84: 685b ldr r3, [r3, #4] 8004b86: 009b lsls r3, r3, #2 8004b88: 429a cmp r2, r3 8004b8a: d1eb bne.n 8004b64 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004b8c: 4b25 ldr r3, [pc, #148] @ (8004c24 ) 8004b8e: 681b ldr r3, [r3, #0] 8004b90: f003 030f and.w r3, r3, #15 8004b94: 683a ldr r2, [r7, #0] 8004b96: 429a cmp r2, r3 8004b98: d20c bcs.n 8004bb4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004b9a: 4b22 ldr r3, [pc, #136] @ (8004c24 ) 8004b9c: 683a ldr r2, [r7, #0] 8004b9e: b2d2 uxtb r2, r2 8004ba0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004ba2: 4b20 ldr r3, [pc, #128] @ (8004c24 ) 8004ba4: 681b ldr r3, [r3, #0] 8004ba6: f003 030f and.w r3, r3, #15 8004baa: 683a ldr r2, [r7, #0] 8004bac: 429a cmp r2, r3 8004bae: d001 beq.n 8004bb4 { return HAL_ERROR; 8004bb0: 2301 movs r3, #1 8004bb2: e032 b.n 8004c1a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004bb4: 687b ldr r3, [r7, #4] 8004bb6: 681b ldr r3, [r3, #0] 8004bb8: f003 0304 and.w r3, r3, #4 8004bbc: 2b00 cmp r3, #0 8004bbe: d008 beq.n 8004bd2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004bc0: 4b19 ldr r3, [pc, #100] @ (8004c28 ) 8004bc2: 689b ldr r3, [r3, #8] 8004bc4: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8004bc8: 687b ldr r3, [r7, #4] 8004bca: 68db ldr r3, [r3, #12] 8004bcc: 4916 ldr r1, [pc, #88] @ (8004c28 ) 8004bce: 4313 orrs r3, r2 8004bd0: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004bd2: 687b ldr r3, [r7, #4] 8004bd4: 681b ldr r3, [r3, #0] 8004bd6: f003 0308 and.w r3, r3, #8 8004bda: 2b00 cmp r3, #0 8004bdc: d009 beq.n 8004bf2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004bde: 4b12 ldr r3, [pc, #72] @ (8004c28 ) 8004be0: 689b ldr r3, [r3, #8] 8004be2: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8004be6: 687b ldr r3, [r7, #4] 8004be8: 691b ldr r3, [r3, #16] 8004bea: 00db lsls r3, r3, #3 8004bec: 490e ldr r1, [pc, #56] @ (8004c28 ) 8004bee: 4313 orrs r3, r2 8004bf0: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004bf2: f000 f821 bl 8004c38 8004bf6: 4602 mov r2, r0 8004bf8: 4b0b ldr r3, [pc, #44] @ (8004c28 ) 8004bfa: 689b ldr r3, [r3, #8] 8004bfc: 091b lsrs r3, r3, #4 8004bfe: f003 030f and.w r3, r3, #15 8004c02: 490a ldr r1, [pc, #40] @ (8004c2c ) 8004c04: 5ccb ldrb r3, [r1, r3] 8004c06: fa22 f303 lsr.w r3, r2, r3 8004c0a: 4a09 ldr r2, [pc, #36] @ (8004c30 ) 8004c0c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8004c0e: 4b09 ldr r3, [pc, #36] @ (8004c34 ) 8004c10: 681b ldr r3, [r3, #0] 8004c12: 4618 mov r0, r3 8004c14: f7fc fc34 bl 8001480 return HAL_OK; 8004c18: 2300 movs r3, #0 } 8004c1a: 4618 mov r0, r3 8004c1c: 3710 adds r7, #16 8004c1e: 46bd mov sp, r7 8004c20: bd80 pop {r7, pc} 8004c22: bf00 nop 8004c24: 40023c00 .word 0x40023c00 8004c28: 40023800 .word 0x40023800 8004c2c: 08007f6c .word 0x08007f6c 8004c30: 20000000 .word 0x20000000 8004c34: 20000004 .word 0x20000004 08004c38 : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { 8004c38: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004c3c: b094 sub sp, #80 @ 0x50 8004c3e: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004c40: 2300 movs r3, #0 8004c42: 647b str r3, [r7, #68] @ 0x44 uint32_t pllvco = 0U; 8004c44: 2300 movs r3, #0 8004c46: 64fb str r3, [r7, #76] @ 0x4c uint32_t pllp = 0U; 8004c48: 2300 movs r3, #0 8004c4a: 643b str r3, [r7, #64] @ 0x40 uint32_t sysclockfreq = 0U; 8004c4c: 2300 movs r3, #0 8004c4e: 64bb str r3, [r7, #72] @ 0x48 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004c50: 4b79 ldr r3, [pc, #484] @ (8004e38 ) 8004c52: 689b ldr r3, [r3, #8] 8004c54: f003 030c and.w r3, r3, #12 8004c58: 2b08 cmp r3, #8 8004c5a: d00d beq.n 8004c78 8004c5c: 2b08 cmp r3, #8 8004c5e: f200 80e1 bhi.w 8004e24 8004c62: 2b00 cmp r3, #0 8004c64: d002 beq.n 8004c6c 8004c66: 2b04 cmp r3, #4 8004c68: d003 beq.n 8004c72 8004c6a: e0db b.n 8004e24 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004c6c: 4b73 ldr r3, [pc, #460] @ (8004e3c ) 8004c6e: 64bb str r3, [r7, #72] @ 0x48 break; 8004c70: e0db b.n 8004e2a } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004c72: 4b73 ldr r3, [pc, #460] @ (8004e40 ) 8004c74: 64bb str r3, [r7, #72] @ 0x48 break; 8004c76: e0d8 b.n 8004e2a } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004c78: 4b6f ldr r3, [pc, #444] @ (8004e38 ) 8004c7a: 685b ldr r3, [r3, #4] 8004c7c: f003 033f and.w r3, r3, #63 @ 0x3f 8004c80: 647b str r3, [r7, #68] @ 0x44 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004c82: 4b6d ldr r3, [pc, #436] @ (8004e38 ) 8004c84: 685b ldr r3, [r3, #4] 8004c86: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c8a: 2b00 cmp r3, #0 8004c8c: d063 beq.n 8004d56 { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004c8e: 4b6a ldr r3, [pc, #424] @ (8004e38 ) 8004c90: 685b ldr r3, [r3, #4] 8004c92: 099b lsrs r3, r3, #6 8004c94: 2200 movs r2, #0 8004c96: 63bb str r3, [r7, #56] @ 0x38 8004c98: 63fa str r2, [r7, #60] @ 0x3c 8004c9a: 6bbb ldr r3, [r7, #56] @ 0x38 8004c9c: f3c3 0308 ubfx r3, r3, #0, #9 8004ca0: 633b str r3, [r7, #48] @ 0x30 8004ca2: 2300 movs r3, #0 8004ca4: 637b str r3, [r7, #52] @ 0x34 8004ca6: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004caa: 4622 mov r2, r4 8004cac: 462b mov r3, r5 8004cae: f04f 0000 mov.w r0, #0 8004cb2: f04f 0100 mov.w r1, #0 8004cb6: 0159 lsls r1, r3, #5 8004cb8: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004cbc: 0150 lsls r0, r2, #5 8004cbe: 4602 mov r2, r0 8004cc0: 460b mov r3, r1 8004cc2: 4621 mov r1, r4 8004cc4: 1a51 subs r1, r2, r1 8004cc6: 6139 str r1, [r7, #16] 8004cc8: 4629 mov r1, r5 8004cca: eb63 0301 sbc.w r3, r3, r1 8004cce: 617b str r3, [r7, #20] 8004cd0: f04f 0200 mov.w r2, #0 8004cd4: f04f 0300 mov.w r3, #0 8004cd8: e9d7 ab04 ldrd sl, fp, [r7, #16] 8004cdc: 4659 mov r1, fp 8004cde: 018b lsls r3, r1, #6 8004ce0: 4651 mov r1, sl 8004ce2: ea43 6391 orr.w r3, r3, r1, lsr #26 8004ce6: 4651 mov r1, sl 8004ce8: 018a lsls r2, r1, #6 8004cea: 4651 mov r1, sl 8004cec: ebb2 0801 subs.w r8, r2, r1 8004cf0: 4659 mov r1, fp 8004cf2: eb63 0901 sbc.w r9, r3, r1 8004cf6: f04f 0200 mov.w r2, #0 8004cfa: f04f 0300 mov.w r3, #0 8004cfe: ea4f 03c9 mov.w r3, r9, lsl #3 8004d02: ea43 7358 orr.w r3, r3, r8, lsr #29 8004d06: ea4f 02c8 mov.w r2, r8, lsl #3 8004d0a: 4690 mov r8, r2 8004d0c: 4699 mov r9, r3 8004d0e: 4623 mov r3, r4 8004d10: eb18 0303 adds.w r3, r8, r3 8004d14: 60bb str r3, [r7, #8] 8004d16: 462b mov r3, r5 8004d18: eb49 0303 adc.w r3, r9, r3 8004d1c: 60fb str r3, [r7, #12] 8004d1e: f04f 0200 mov.w r2, #0 8004d22: f04f 0300 mov.w r3, #0 8004d26: e9d7 4502 ldrd r4, r5, [r7, #8] 8004d2a: 4629 mov r1, r5 8004d2c: 024b lsls r3, r1, #9 8004d2e: 4621 mov r1, r4 8004d30: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004d34: 4621 mov r1, r4 8004d36: 024a lsls r2, r1, #9 8004d38: 4610 mov r0, r2 8004d3a: 4619 mov r1, r3 8004d3c: 6c7b ldr r3, [r7, #68] @ 0x44 8004d3e: 2200 movs r2, #0 8004d40: 62bb str r3, [r7, #40] @ 0x28 8004d42: 62fa str r2, [r7, #44] @ 0x2c 8004d44: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8004d48: f7fb fa52 bl 80001f0 <__aeabi_uldivmod> 8004d4c: 4602 mov r2, r0 8004d4e: 460b mov r3, r1 8004d50: 4613 mov r3, r2 8004d52: 64fb str r3, [r7, #76] @ 0x4c 8004d54: e058 b.n 8004e08 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004d56: 4b38 ldr r3, [pc, #224] @ (8004e38 ) 8004d58: 685b ldr r3, [r3, #4] 8004d5a: 099b lsrs r3, r3, #6 8004d5c: 2200 movs r2, #0 8004d5e: 4618 mov r0, r3 8004d60: 4611 mov r1, r2 8004d62: f3c0 0308 ubfx r3, r0, #0, #9 8004d66: 623b str r3, [r7, #32] 8004d68: 2300 movs r3, #0 8004d6a: 627b str r3, [r7, #36] @ 0x24 8004d6c: e9d7 8908 ldrd r8, r9, [r7, #32] 8004d70: 4642 mov r2, r8 8004d72: 464b mov r3, r9 8004d74: f04f 0000 mov.w r0, #0 8004d78: f04f 0100 mov.w r1, #0 8004d7c: 0159 lsls r1, r3, #5 8004d7e: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004d82: 0150 lsls r0, r2, #5 8004d84: 4602 mov r2, r0 8004d86: 460b mov r3, r1 8004d88: 4641 mov r1, r8 8004d8a: ebb2 0a01 subs.w sl, r2, r1 8004d8e: 4649 mov r1, r9 8004d90: eb63 0b01 sbc.w fp, r3, r1 8004d94: f04f 0200 mov.w r2, #0 8004d98: f04f 0300 mov.w r3, #0 8004d9c: ea4f 138b mov.w r3, fp, lsl #6 8004da0: ea43 639a orr.w r3, r3, sl, lsr #26 8004da4: ea4f 128a mov.w r2, sl, lsl #6 8004da8: ebb2 040a subs.w r4, r2, sl 8004dac: eb63 050b sbc.w r5, r3, fp 8004db0: f04f 0200 mov.w r2, #0 8004db4: f04f 0300 mov.w r3, #0 8004db8: 00eb lsls r3, r5, #3 8004dba: ea43 7354 orr.w r3, r3, r4, lsr #29 8004dbe: 00e2 lsls r2, r4, #3 8004dc0: 4614 mov r4, r2 8004dc2: 461d mov r5, r3 8004dc4: 4643 mov r3, r8 8004dc6: 18e3 adds r3, r4, r3 8004dc8: 603b str r3, [r7, #0] 8004dca: 464b mov r3, r9 8004dcc: eb45 0303 adc.w r3, r5, r3 8004dd0: 607b str r3, [r7, #4] 8004dd2: f04f 0200 mov.w r2, #0 8004dd6: f04f 0300 mov.w r3, #0 8004dda: e9d7 4500 ldrd r4, r5, [r7] 8004dde: 4629 mov r1, r5 8004de0: 028b lsls r3, r1, #10 8004de2: 4621 mov r1, r4 8004de4: ea43 5391 orr.w r3, r3, r1, lsr #22 8004de8: 4621 mov r1, r4 8004dea: 028a lsls r2, r1, #10 8004dec: 4610 mov r0, r2 8004dee: 4619 mov r1, r3 8004df0: 6c7b ldr r3, [r7, #68] @ 0x44 8004df2: 2200 movs r2, #0 8004df4: 61bb str r3, [r7, #24] 8004df6: 61fa str r2, [r7, #28] 8004df8: e9d7 2306 ldrd r2, r3, [r7, #24] 8004dfc: f7fb f9f8 bl 80001f0 <__aeabi_uldivmod> 8004e00: 4602 mov r2, r0 8004e02: 460b mov r3, r1 8004e04: 4613 mov r3, r2 8004e06: 64fb str r3, [r7, #76] @ 0x4c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004e08: 4b0b ldr r3, [pc, #44] @ (8004e38 ) 8004e0a: 685b ldr r3, [r3, #4] 8004e0c: 0c1b lsrs r3, r3, #16 8004e0e: f003 0303 and.w r3, r3, #3 8004e12: 3301 adds r3, #1 8004e14: 005b lsls r3, r3, #1 8004e16: 643b str r3, [r7, #64] @ 0x40 sysclockfreq = pllvco / pllp; 8004e18: 6cfa ldr r2, [r7, #76] @ 0x4c 8004e1a: 6c3b ldr r3, [r7, #64] @ 0x40 8004e1c: fbb2 f3f3 udiv r3, r2, r3 8004e20: 64bb str r3, [r7, #72] @ 0x48 break; 8004e22: e002 b.n 8004e2a } default: { sysclockfreq = HSI_VALUE; 8004e24: 4b05 ldr r3, [pc, #20] @ (8004e3c ) 8004e26: 64bb str r3, [r7, #72] @ 0x48 break; 8004e28: bf00 nop } } return sysclockfreq; 8004e2a: 6cbb ldr r3, [r7, #72] @ 0x48 } 8004e2c: 4618 mov r0, r3 8004e2e: 3750 adds r7, #80 @ 0x50 8004e30: 46bd mov sp, r7 8004e32: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004e36: bf00 nop 8004e38: 40023800 .word 0x40023800 8004e3c: 00f42400 .word 0x00f42400 8004e40: 007a1200 .word 0x007a1200 08004e44 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8004e44: b480 push {r7} 8004e46: af00 add r7, sp, #0 return SystemCoreClock; 8004e48: 4b03 ldr r3, [pc, #12] @ (8004e58 ) 8004e4a: 681b ldr r3, [r3, #0] } 8004e4c: 4618 mov r0, r3 8004e4e: 46bd mov sp, r7 8004e50: f85d 7b04 ldr.w r7, [sp], #4 8004e54: 4770 bx lr 8004e56: bf00 nop 8004e58: 20000000 .word 0x20000000 08004e5c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004e5c: b580 push {r7, lr} 8004e5e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004e60: f7ff fff0 bl 8004e44 8004e64: 4602 mov r2, r0 8004e66: 4b05 ldr r3, [pc, #20] @ (8004e7c ) 8004e68: 689b ldr r3, [r3, #8] 8004e6a: 0a9b lsrs r3, r3, #10 8004e6c: f003 0307 and.w r3, r3, #7 8004e70: 4903 ldr r1, [pc, #12] @ (8004e80 ) 8004e72: 5ccb ldrb r3, [r1, r3] 8004e74: fa22 f303 lsr.w r3, r2, r3 } 8004e78: 4618 mov r0, r3 8004e7a: bd80 pop {r7, pc} 8004e7c: 40023800 .word 0x40023800 8004e80: 08007f7c .word 0x08007f7c 08004e84 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004e84: b580 push {r7, lr} 8004e86: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004e88: f7ff ffdc bl 8004e44 8004e8c: 4602 mov r2, r0 8004e8e: 4b05 ldr r3, [pc, #20] @ (8004ea4 ) 8004e90: 689b ldr r3, [r3, #8] 8004e92: 0b5b lsrs r3, r3, #13 8004e94: f003 0307 and.w r3, r3, #7 8004e98: 4903 ldr r1, [pc, #12] @ (8004ea8 ) 8004e9a: 5ccb ldrb r3, [r1, r3] 8004e9c: fa22 f303 lsr.w r3, r2, r3 } 8004ea0: 4618 mov r0, r3 8004ea2: bd80 pop {r7, pc} 8004ea4: 40023800 .word 0x40023800 8004ea8: 08007f7c .word 0x08007f7c 08004eac : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8004eac: b480 push {r7} 8004eae: b083 sub sp, #12 8004eb0: af00 add r7, sp, #0 8004eb2: 6078 str r0, [r7, #4] 8004eb4: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8004eb6: 687b ldr r3, [r7, #4] 8004eb8: 220f movs r2, #15 8004eba: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8004ebc: 4b12 ldr r3, [pc, #72] @ (8004f08 ) 8004ebe: 689b ldr r3, [r3, #8] 8004ec0: f003 0203 and.w r2, r3, #3 8004ec4: 687b ldr r3, [r7, #4] 8004ec6: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8004ec8: 4b0f ldr r3, [pc, #60] @ (8004f08 ) 8004eca: 689b ldr r3, [r3, #8] 8004ecc: f003 02f0 and.w r2, r3, #240 @ 0xf0 8004ed0: 687b ldr r3, [r7, #4] 8004ed2: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8004ed4: 4b0c ldr r3, [pc, #48] @ (8004f08 ) 8004ed6: 689b ldr r3, [r3, #8] 8004ed8: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8004edc: 687b ldr r3, [r7, #4] 8004ede: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); 8004ee0: 4b09 ldr r3, [pc, #36] @ (8004f08 ) 8004ee2: 689b ldr r3, [r3, #8] 8004ee4: 08db lsrs r3, r3, #3 8004ee6: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8004eea: 687b ldr r3, [r7, #4] 8004eec: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8004eee: 4b07 ldr r3, [pc, #28] @ (8004f0c ) 8004ef0: 681b ldr r3, [r3, #0] 8004ef2: f003 020f and.w r2, r3, #15 8004ef6: 683b ldr r3, [r7, #0] 8004ef8: 601a str r2, [r3, #0] } 8004efa: bf00 nop 8004efc: 370c adds r7, #12 8004efe: 46bd mov sp, r7 8004f00: f85d 7b04 ldr.w r7, [sp], #4 8004f04: 4770 bx lr 8004f06: bf00 nop 8004f08: 40023800 .word 0x40023800 8004f0c: 40023c00 .word 0x40023c00 08004f10 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004f10: b580 push {r7, lr} 8004f12: b086 sub sp, #24 8004f14: af00 add r7, sp, #0 8004f16: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004f18: 2300 movs r3, #0 8004f1a: 617b str r3, [r7, #20] uint32_t tmpreg1 = 0U; 8004f1c: 2300 movs r3, #0 8004f1e: 613b str r3, [r7, #16] /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*----------------------- Common configuration SAI/I2S ---------------------*/ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division factor is common parameters for both peripherals */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 8004f20: 687b ldr r3, [r7, #4] 8004f22: 681b ldr r3, [r3, #0] 8004f24: f003 0301 and.w r3, r3, #1 8004f28: 2b00 cmp r3, #0 8004f2a: d10b bne.n 8004f44 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || 8004f2c: 687b ldr r3, [r7, #4] 8004f2e: 681b ldr r3, [r3, #0] 8004f30: f003 0302 and.w r3, r3, #2 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 8004f34: 2b00 cmp r3, #0 8004f36: d105 bne.n 8004f44 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) 8004f38: 687b ldr r3, [r7, #4] 8004f3a: 681b ldr r3, [r3, #0] 8004f3c: f003 0340 and.w r3, r3, #64 @ 0x40 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || 8004f40: 2b00 cmp r3, #0 8004f42: d075 beq.n 8005030 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004f44: 4b91 ldr r3, [pc, #580] @ (800518c ) 8004f46: 2200 movs r2, #0 8004f48: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004f4a: f7fc fbcb bl 80016e4 8004f4e: 6178 str r0, [r7, #20] /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004f50: e008 b.n 8004f64 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004f52: f7fc fbc7 bl 80016e4 8004f56: 4602 mov r2, r0 8004f58: 697b ldr r3, [r7, #20] 8004f5a: 1ad3 subs r3, r2, r3 8004f5c: 2b02 cmp r3, #2 8004f5e: d901 bls.n 8004f64 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004f60: 2303 movs r3, #3 8004f62: e189 b.n 8005278 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004f64: 4b8a ldr r3, [pc, #552] @ (8005190 ) 8004f66: 681b ldr r3, [r3, #0] 8004f68: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004f6c: 2b00 cmp r3, #0 8004f6e: d1f0 bne.n 8004f52 } /*---------------------------- I2S configuration -------------------------*/ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added only for I2S configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) 8004f70: 687b ldr r3, [r7, #4] 8004f72: 681b ldr r3, [r3, #0] 8004f74: f003 0301 and.w r3, r3, #1 8004f78: 2b00 cmp r3, #0 8004f7a: d009 beq.n 8004f90 /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); 8004f7c: 687b ldr r3, [r7, #4] 8004f7e: 685b ldr r3, [r3, #4] 8004f80: 019a lsls r2, r3, #6 8004f82: 687b ldr r3, [r7, #4] 8004f84: 689b ldr r3, [r3, #8] 8004f86: 071b lsls r3, r3, #28 8004f88: 4981 ldr r1, [pc, #516] @ (8005190 ) 8004f8a: 4313 orrs r3, r2 8004f8c: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /*---------------------------- SAI configuration -------------------------*/ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must be added only for SAI configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) 8004f90: 687b ldr r3, [r7, #4] 8004f92: 681b ldr r3, [r3, #0] 8004f94: f003 0302 and.w r3, r3, #2 8004f98: 2b00 cmp r3, #0 8004f9a: d01f beq.n 8004fdc /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004f9c: 4b7c ldr r3, [pc, #496] @ (8005190 ) 8004f9e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004fa2: 0f1b lsrs r3, r3, #28 8004fa4: f003 0307 and.w r3, r3, #7 8004fa8: 613b str r3, [r7, #16] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); 8004faa: 687b ldr r3, [r7, #4] 8004fac: 685b ldr r3, [r3, #4] 8004fae: 019a lsls r2, r3, #6 8004fb0: 687b ldr r3, [r7, #4] 8004fb2: 68db ldr r3, [r3, #12] 8004fb4: 061b lsls r3, r3, #24 8004fb6: 431a orrs r2, r3 8004fb8: 693b ldr r3, [r7, #16] 8004fba: 071b lsls r3, r3, #28 8004fbc: 4974 ldr r1, [pc, #464] @ (8005190 ) 8004fbe: 4313 orrs r3, r2 8004fc0: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004fc4: 4b72 ldr r3, [pc, #456] @ (8005190 ) 8004fc6: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004fca: f023 021f bic.w r2, r3, #31 8004fce: 687b ldr r3, [r7, #4] 8004fd0: 69db ldr r3, [r3, #28] 8004fd2: 3b01 subs r3, #1 8004fd4: 496e ldr r1, [pc, #440] @ (8005190 ) 8004fd6: 4313 orrs r3, r2 8004fd8: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004fdc: 687b ldr r3, [r7, #4] 8004fde: 681b ldr r3, [r3, #0] 8004fe0: f003 0340 and.w r3, r3, #64 @ 0x40 8004fe4: 2b00 cmp r3, #0 8004fe6: d00d beq.n 8005004 /* Check for Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Configure the PLLI2S multiplication and division factors */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, 8004fe8: 687b ldr r3, [r7, #4] 8004fea: 685b ldr r3, [r3, #4] 8004fec: 019a lsls r2, r3, #6 8004fee: 687b ldr r3, [r7, #4] 8004ff0: 68db ldr r3, [r3, #12] 8004ff2: 061b lsls r3, r3, #24 8004ff4: 431a orrs r2, r3 8004ff6: 687b ldr r3, [r7, #4] 8004ff8: 689b ldr r3, [r3, #8] 8004ffa: 071b lsls r3, r3, #28 8004ffc: 4964 ldr r1, [pc, #400] @ (8005190 ) 8004ffe: 4313 orrs r3, r2 8005000: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8005004: 4b61 ldr r3, [pc, #388] @ (800518c ) 8005006: 2201 movs r2, #1 8005008: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800500a: f7fc fb6b bl 80016e4 800500e: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8005010: e008 b.n 8005024 { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8005012: f7fc fb67 bl 80016e4 8005016: 4602 mov r2, r0 8005018: 697b ldr r3, [r7, #20] 800501a: 1ad3 subs r3, r2, r3 800501c: 2b02 cmp r3, #2 800501e: d901 bls.n 8005024 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8005020: 2303 movs r3, #3 8005022: e129 b.n 8005278 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8005024: 4b5a ldr r3, [pc, #360] @ (8005190 ) 8005026: 681b ldr r3, [r3, #0] 8005028: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 800502c: 2b00 cmp r3, #0 800502e: d0f0 beq.n 8005012 /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division factor is common parameters for both peripherals */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 8005030: 687b ldr r3, [r7, #4] 8005032: 681b ldr r3, [r3, #0] 8005034: f003 0304 and.w r3, r3, #4 8005038: 2b00 cmp r3, #0 800503a: d105 bne.n 8005048 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) 800503c: 687b ldr r3, [r7, #4] 800503e: 681b ldr r3, [r3, #0] 8005040: f003 0308 and.w r3, r3, #8 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 8005044: 2b00 cmp r3, #0 8005046: d079 beq.n 800513c { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8005048: 4b52 ldr r3, [pc, #328] @ (8005194 ) 800504a: 2200 movs r2, #0 800504c: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 800504e: f7fc fb49 bl 80016e4 8005052: 6178 str r0, [r7, #20] /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8005054: e008 b.n 8005068 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 8005056: f7fc fb45 bl 80016e4 800505a: 4602 mov r2, r0 800505c: 697b ldr r3, [r7, #20] 800505e: 1ad3 subs r3, r2, r3 8005060: 2b02 cmp r3, #2 8005062: d901 bls.n 8005068 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8005064: 2303 movs r3, #3 8005066: e107 b.n 8005278 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8005068: 4b49 ldr r3, [pc, #292] @ (8005190 ) 800506a: 681b ldr r3, [r3, #0] 800506c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005070: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 8005074: d0ef beq.n 8005056 } /*---------------------------- SAI configuration -------------------------*/ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must be added only for SAI configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) 8005076: 687b ldr r3, [r7, #4] 8005078: 681b ldr r3, [r3, #0] 800507a: f003 0304 and.w r3, r3, #4 800507e: 2b00 cmp r3, #0 8005080: d020 beq.n 80050c4 { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); 8005082: 4b43 ldr r3, [pc, #268] @ (8005190 ) 8005084: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005088: 0f1b lsrs r3, r3, #28 800508a: f003 0307 and.w r3, r3, #7 800508e: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); 8005090: 687b ldr r3, [r7, #4] 8005092: 691b ldr r3, [r3, #16] 8005094: 019a lsls r2, r3, #6 8005096: 687b ldr r3, [r7, #4] 8005098: 695b ldr r3, [r3, #20] 800509a: 061b lsls r3, r3, #24 800509c: 431a orrs r2, r3 800509e: 693b ldr r3, [r7, #16] 80050a0: 071b lsls r3, r3, #28 80050a2: 493b ldr r1, [pc, #236] @ (8005190 ) 80050a4: 4313 orrs r3, r2 80050a6: f8c1 3088 str.w r3, [r1, #136] @ 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 80050aa: 4b39 ldr r3, [pc, #228] @ (8005190 ) 80050ac: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80050b0: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 80050b4: 687b ldr r3, [r7, #4] 80050b6: 6a1b ldr r3, [r3, #32] 80050b8: 3b01 subs r3, #1 80050ba: 021b lsls r3, r3, #8 80050bc: 4934 ldr r1, [pc, #208] @ (8005190 ) 80050be: 4313 orrs r3, r2 80050c0: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*---------------------------- LTDC configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) 80050c4: 687b ldr r3, [r7, #4] 80050c6: 681b ldr r3, [r3, #0] 80050c8: f003 0308 and.w r3, r3, #8 80050cc: 2b00 cmp r3, #0 80050ce: d01e beq.n 800510e { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 80050d0: 4b2f ldr r3, [pc, #188] @ (8005190 ) 80050d2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 80050d6: 0e1b lsrs r3, r3, #24 80050d8: f003 030f and.w r3, r3, #15 80050dc: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); 80050de: 687b ldr r3, [r7, #4] 80050e0: 691b ldr r3, [r3, #16] 80050e2: 019a lsls r2, r3, #6 80050e4: 693b ldr r3, [r7, #16] 80050e6: 061b lsls r3, r3, #24 80050e8: 431a orrs r2, r3 80050ea: 687b ldr r3, [r7, #4] 80050ec: 699b ldr r3, [r3, #24] 80050ee: 071b lsls r3, r3, #28 80050f0: 4927 ldr r1, [pc, #156] @ (8005190 ) 80050f2: 4313 orrs r3, r2 80050f4: f8c1 3088 str.w r3, [r1, #136] @ 0x88 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); 80050f8: 4b25 ldr r3, [pc, #148] @ (8005190 ) 80050fa: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80050fe: f423 3240 bic.w r2, r3, #196608 @ 0x30000 8005102: 687b ldr r3, [r7, #4] 8005104: 6a5b ldr r3, [r3, #36] @ 0x24 8005106: 4922 ldr r1, [pc, #136] @ (8005190 ) 8005108: 4313 orrs r3, r2 800510a: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 800510e: 4b21 ldr r3, [pc, #132] @ (8005194 ) 8005110: 2201 movs r2, #1 8005112: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005114: f7fc fae6 bl 80016e4 8005118: 6178 str r0, [r7, #20] /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 800511a: e008 b.n 800512e { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 800511c: f7fc fae2 bl 80016e4 8005120: 4602 mov r2, r0 8005122: 697b ldr r3, [r7, #20] 8005124: 1ad3 subs r3, r2, r3 8005126: 2b02 cmp r3, #2 8005128: d901 bls.n 800512e { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800512a: 2303 movs r3, #3 800512c: e0a4 b.n 8005278 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 800512e: 4b18 ldr r3, [pc, #96] @ (8005190 ) 8005130: 681b ldr r3, [r3, #0] 8005132: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005136: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800513a: d1ef bne.n 800511c } } /*--------------------------------------------------------------------------*/ /*---------------------------- RTC configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 800513c: 687b ldr r3, [r7, #4] 800513e: 681b ldr r3, [r3, #0] 8005140: f003 0320 and.w r3, r3, #32 8005144: 2b00 cmp r3, #0 8005146: f000 808b beq.w 8005260 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 800514a: 2300 movs r3, #0 800514c: 60fb str r3, [r7, #12] 800514e: 4b10 ldr r3, [pc, #64] @ (8005190 ) 8005150: 6c1b ldr r3, [r3, #64] @ 0x40 8005152: 4a0f ldr r2, [pc, #60] @ (8005190 ) 8005154: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005158: 6413 str r3, [r2, #64] @ 0x40 800515a: 4b0d ldr r3, [pc, #52] @ (8005190 ) 800515c: 6c1b ldr r3, [r3, #64] @ 0x40 800515e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8005162: 60fb str r3, [r7, #12] 8005164: 68fb ldr r3, [r7, #12] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 8005166: 4b0c ldr r3, [pc, #48] @ (8005198 ) 8005168: 681b ldr r3, [r3, #0] 800516a: 4a0b ldr r2, [pc, #44] @ (8005198 ) 800516c: f443 7380 orr.w r3, r3, #256 @ 0x100 8005170: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005172: f7fc fab7 bl 80016e4 8005176: 6178 str r0, [r7, #20] while ((PWR->CR & PWR_CR_DBP) == RESET) 8005178: e010 b.n 800519c { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800517a: f7fc fab3 bl 80016e4 800517e: 4602 mov r2, r0 8005180: 697b ldr r3, [r7, #20] 8005182: 1ad3 subs r3, r2, r3 8005184: 2b02 cmp r3, #2 8005186: d909 bls.n 800519c { return HAL_TIMEOUT; 8005188: 2303 movs r3, #3 800518a: e075 b.n 8005278 800518c: 42470068 .word 0x42470068 8005190: 40023800 .word 0x40023800 8005194: 42470070 .word 0x42470070 8005198: 40007000 .word 0x40007000 while ((PWR->CR & PWR_CR_DBP) == RESET) 800519c: 4b38 ldr r3, [pc, #224] @ (8005280 ) 800519e: 681b ldr r3, [r3, #0] 80051a0: f403 7380 and.w r3, r3, #256 @ 0x100 80051a4: 2b00 cmp r3, #0 80051a6: d0e8 beq.n 800517a } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 80051a8: 4b36 ldr r3, [pc, #216] @ (8005284 ) 80051aa: 6f1b ldr r3, [r3, #112] @ 0x70 80051ac: f403 7340 and.w r3, r3, #768 @ 0x300 80051b0: 613b str r3, [r7, #16] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 80051b2: 693b ldr r3, [r7, #16] 80051b4: 2b00 cmp r3, #0 80051b6: d02f beq.n 8005218 80051b8: 687b ldr r3, [r7, #4] 80051ba: 6a9b ldr r3, [r3, #40] @ 0x28 80051bc: f403 7340 and.w r3, r3, #768 @ 0x300 80051c0: 693a ldr r2, [r7, #16] 80051c2: 429a cmp r2, r3 80051c4: d028 beq.n 8005218 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 80051c6: 4b2f ldr r3, [pc, #188] @ (8005284 ) 80051c8: 6f1b ldr r3, [r3, #112] @ 0x70 80051ca: f423 7340 bic.w r3, r3, #768 @ 0x300 80051ce: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80051d0: 4b2d ldr r3, [pc, #180] @ (8005288 ) 80051d2: 2201 movs r2, #1 80051d4: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 80051d6: 4b2c ldr r3, [pc, #176] @ (8005288 ) 80051d8: 2200 movs r2, #0 80051da: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 80051dc: 4a29 ldr r2, [pc, #164] @ (8005284 ) 80051de: 693b ldr r3, [r7, #16] 80051e0: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 80051e2: 4b28 ldr r3, [pc, #160] @ (8005284 ) 80051e4: 6f1b ldr r3, [r3, #112] @ 0x70 80051e6: f003 0301 and.w r3, r3, #1 80051ea: 2b01 cmp r3, #1 80051ec: d114 bne.n 8005218 { /* Get tick */ tickstart = HAL_GetTick(); 80051ee: f7fc fa79 bl 80016e4 80051f2: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80051f4: e00a b.n 800520c { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80051f6: f7fc fa75 bl 80016e4 80051fa: 4602 mov r2, r0 80051fc: 697b ldr r3, [r7, #20] 80051fe: 1ad3 subs r3, r2, r3 8005200: f241 3288 movw r2, #5000 @ 0x1388 8005204: 4293 cmp r3, r2 8005206: d901 bls.n 800520c { return HAL_TIMEOUT; 8005208: 2303 movs r3, #3 800520a: e035 b.n 8005278 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800520c: 4b1d ldr r3, [pc, #116] @ (8005284 ) 800520e: 6f1b ldr r3, [r3, #112] @ 0x70 8005210: f003 0302 and.w r3, r3, #2 8005214: 2b00 cmp r3, #0 8005216: d0ee beq.n 80051f6 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 8005218: 687b ldr r3, [r7, #4] 800521a: 6a9b ldr r3, [r3, #40] @ 0x28 800521c: f403 7340 and.w r3, r3, #768 @ 0x300 8005220: f5b3 7f40 cmp.w r3, #768 @ 0x300 8005224: d10d bne.n 8005242 8005226: 4b17 ldr r3, [pc, #92] @ (8005284 ) 8005228: 689b ldr r3, [r3, #8] 800522a: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 800522e: 687b ldr r3, [r7, #4] 8005230: 6a9b ldr r3, [r3, #40] @ 0x28 8005232: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 8005236: f423 7340 bic.w r3, r3, #768 @ 0x300 800523a: 4912 ldr r1, [pc, #72] @ (8005284 ) 800523c: 4313 orrs r3, r2 800523e: 608b str r3, [r1, #8] 8005240: e005 b.n 800524e 8005242: 4b10 ldr r3, [pc, #64] @ (8005284 ) 8005244: 689b ldr r3, [r3, #8] 8005246: 4a0f ldr r2, [pc, #60] @ (8005284 ) 8005248: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 800524c: 6093 str r3, [r2, #8] 800524e: 4b0d ldr r3, [pc, #52] @ (8005284 ) 8005250: 6f1a ldr r2, [r3, #112] @ 0x70 8005252: 687b ldr r3, [r7, #4] 8005254: 6a9b ldr r3, [r3, #40] @ 0x28 8005256: f3c3 030b ubfx r3, r3, #0, #12 800525a: 490a ldr r1, [pc, #40] @ (8005284 ) 800525c: 4313 orrs r3, r2 800525e: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8005260: 687b ldr r3, [r7, #4] 8005262: 681b ldr r3, [r3, #0] 8005264: f003 0310 and.w r3, r3, #16 8005268: 2b00 cmp r3, #0 800526a: d004 beq.n 8005276 { __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 800526c: 687b ldr r3, [r7, #4] 800526e: f893 202c ldrb.w r2, [r3, #44] @ 0x2c 8005272: 4b06 ldr r3, [pc, #24] @ (800528c ) 8005274: 601a str r2, [r3, #0] } return HAL_OK; 8005276: 2300 movs r3, #0 } 8005278: 4618 mov r0, r3 800527a: 3718 adds r7, #24 800527c: 46bd mov sp, r7 800527e: bd80 pop {r7, pc} 8005280: 40007000 .word 0x40007000 8005284: 40023800 .word 0x40023800 8005288: 42470e40 .word 0x42470e40 800528c: 424711e0 .word 0x424711e0 08005290 : * the configuration information for SDRAM module. * @param Timing Pointer to SDRAM control timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) { 8005290: b580 push {r7, lr} 8005292: b082 sub sp, #8 8005294: af00 add r7, sp, #0 8005296: 6078 str r0, [r7, #4] 8005298: 6039 str r1, [r7, #0] /* Check the SDRAM handle parameter */ if (hsdram == NULL) 800529a: 687b ldr r3, [r7, #4] 800529c: 2b00 cmp r3, #0 800529e: d101 bne.n 80052a4 { return HAL_ERROR; 80052a0: 2301 movs r3, #1 80052a2: e025 b.n 80052f0 } if (hsdram->State == HAL_SDRAM_STATE_RESET) 80052a4: 687b ldr r3, [r7, #4] 80052a6: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 80052aa: b2db uxtb r3, r3 80052ac: 2b00 cmp r3, #0 80052ae: d106 bne.n 80052be { /* Allocate lock resource and initialize it */ hsdram->Lock = HAL_UNLOCKED; 80052b0: 687b ldr r3, [r7, #4] 80052b2: 2200 movs r2, #0 80052b4: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Init the low level hardware */ hsdram->MspInitCallback(hsdram); #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); 80052b8: 6878 ldr r0, [r7, #4] 80052ba: f7fc f8d7 bl 800146c #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /* Initialize the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_BUSY; 80052be: 687b ldr r3, [r7, #4] 80052c0: 2202 movs r2, #2 80052c2: f883 202c strb.w r2, [r3, #44] @ 0x2c /* Initialize SDRAM control Interface */ (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); 80052c6: 687b ldr r3, [r7, #4] 80052c8: 681a ldr r2, [r3, #0] 80052ca: 687b ldr r3, [r7, #4] 80052cc: 3304 adds r3, #4 80052ce: 4619 mov r1, r3 80052d0: 4610 mov r0, r2 80052d2: f000 ffcd bl 8006270 /* Initialize SDRAM timing Interface */ (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 80052d6: 687b ldr r3, [r7, #4] 80052d8: 6818 ldr r0, [r3, #0] 80052da: 687b ldr r3, [r7, #4] 80052dc: 685b ldr r3, [r3, #4] 80052de: 461a mov r2, r3 80052e0: 6839 ldr r1, [r7, #0] 80052e2: f001 f822 bl 800632a /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; 80052e6: 687b ldr r3, [r7, #4] 80052e8: 2201 movs r2, #1 80052ea: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 80052ee: 2300 movs r3, #0 } 80052f0: 4618 mov r0, r3 80052f2: 3708 adds r7, #8 80052f4: 46bd mov sp, r7 80052f6: bd80 pop {r7, pc} 080052f8 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 80052f8: b580 push {r7, lr} 80052fa: b082 sub sp, #8 80052fc: af00 add r7, sp, #0 80052fe: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) 8005300: 687b ldr r3, [r7, #4] 8005302: 2b00 cmp r3, #0 8005304: d101 bne.n 800530a { return HAL_ERROR; 8005306: 2301 movs r3, #1 8005308: e07b b.n 8005402 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 800530a: 687b ldr r3, [r7, #4] 800530c: 6a5b ldr r3, [r3, #36] @ 0x24 800530e: 2b00 cmp r3, #0 8005310: d108 bne.n 8005324 { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 8005312: 687b ldr r3, [r7, #4] 8005314: 685b ldr r3, [r3, #4] 8005316: f5b3 7f82 cmp.w r3, #260 @ 0x104 800531a: d009 beq.n 8005330 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 800531c: 687b ldr r3, [r7, #4] 800531e: 2200 movs r2, #0 8005320: 61da str r2, [r3, #28] 8005322: e005 b.n 8005330 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 8005324: 687b ldr r3, [r7, #4] 8005326: 2200 movs r2, #0 8005328: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 800532a: 687b ldr r3, [r7, #4] 800532c: 2200 movs r2, #0 800532e: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8005330: 687b ldr r3, [r7, #4] 8005332: 2200 movs r2, #0 8005334: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 8005336: 687b ldr r3, [r7, #4] 8005338: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 800533c: b2db uxtb r3, r3 800533e: 2b00 cmp r3, #0 8005340: d106 bne.n 8005350 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 8005342: 687b ldr r3, [r7, #4] 8005344: 2200 movs r2, #0 8005346: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 800534a: 6878 ldr r0, [r7, #4] 800534c: f7fb ff4a bl 80011e4 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 8005350: 687b ldr r3, [r7, #4] 8005352: 2202 movs r2, #2 8005354: f883 2051 strb.w r2, [r3, #81] @ 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8005358: 687b ldr r3, [r7, #4] 800535a: 681b ldr r3, [r3, #0] 800535c: 681a ldr r2, [r3, #0] 800535e: 687b ldr r3, [r7, #4] 8005360: 681b ldr r3, [r3, #0] 8005362: f022 0240 bic.w r2, r2, #64 @ 0x40 8005366: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8005368: 687b ldr r3, [r7, #4] 800536a: 685b ldr r3, [r3, #4] 800536c: f403 7282 and.w r2, r3, #260 @ 0x104 8005370: 687b ldr r3, [r7, #4] 8005372: 689b ldr r3, [r3, #8] 8005374: f403 4304 and.w r3, r3, #33792 @ 0x8400 8005378: 431a orrs r2, r3 800537a: 687b ldr r3, [r7, #4] 800537c: 68db ldr r3, [r3, #12] 800537e: f403 6300 and.w r3, r3, #2048 @ 0x800 8005382: 431a orrs r2, r3 8005384: 687b ldr r3, [r7, #4] 8005386: 691b ldr r3, [r3, #16] 8005388: f003 0302 and.w r3, r3, #2 800538c: 431a orrs r2, r3 800538e: 687b ldr r3, [r7, #4] 8005390: 695b ldr r3, [r3, #20] 8005392: f003 0301 and.w r3, r3, #1 8005396: 431a orrs r2, r3 8005398: 687b ldr r3, [r7, #4] 800539a: 699b ldr r3, [r3, #24] 800539c: f403 7300 and.w r3, r3, #512 @ 0x200 80053a0: 431a orrs r2, r3 80053a2: 687b ldr r3, [r7, #4] 80053a4: 69db ldr r3, [r3, #28] 80053a6: f003 0338 and.w r3, r3, #56 @ 0x38 80053aa: 431a orrs r2, r3 80053ac: 687b ldr r3, [r7, #4] 80053ae: 6a1b ldr r3, [r3, #32] 80053b0: f003 0380 and.w r3, r3, #128 @ 0x80 80053b4: ea42 0103 orr.w r1, r2, r3 80053b8: 687b ldr r3, [r7, #4] 80053ba: 6a9b ldr r3, [r3, #40] @ 0x28 80053bc: f403 5200 and.w r2, r3, #8192 @ 0x2000 80053c0: 687b ldr r3, [r7, #4] 80053c2: 681b ldr r3, [r3, #0] 80053c4: 430a orrs r2, r1 80053c6: 601a str r2, [r3, #0] (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management, TI Mode */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); 80053c8: 687b ldr r3, [r7, #4] 80053ca: 699b ldr r3, [r3, #24] 80053cc: 0c1b lsrs r3, r3, #16 80053ce: f003 0104 and.w r1, r3, #4 80053d2: 687b ldr r3, [r7, #4] 80053d4: 6a5b ldr r3, [r3, #36] @ 0x24 80053d6: f003 0210 and.w r2, r3, #16 80053da: 687b ldr r3, [r7, #4] 80053dc: 681b ldr r3, [r3, #0] 80053de: 430a orrs r2, r1 80053e0: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 80053e2: 687b ldr r3, [r7, #4] 80053e4: 681b ldr r3, [r3, #0] 80053e6: 69da ldr r2, [r3, #28] 80053e8: 687b ldr r3, [r7, #4] 80053ea: 681b ldr r3, [r3, #0] 80053ec: f422 6200 bic.w r2, r2, #2048 @ 0x800 80053f0: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80053f2: 687b ldr r3, [r7, #4] 80053f4: 2200 movs r2, #0 80053f6: 655a str r2, [r3, #84] @ 0x54 hspi->State = HAL_SPI_STATE_READY; 80053f8: 687b ldr r3, [r7, #4] 80053fa: 2201 movs r2, #1 80053fc: f883 2051 strb.w r2, [r3, #81] @ 0x51 return HAL_OK; 8005400: 2300 movs r3, #0 } 8005402: 4618 mov r0, r3 8005404: 3708 adds r7, #8 8005406: 46bd mov sp, r7 8005408: bd80 pop {r7, pc} 0800540a : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 800540a: b580 push {r7, lr} 800540c: b082 sub sp, #8 800540e: af00 add r7, sp, #0 8005410: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005412: 687b ldr r3, [r7, #4] 8005414: 2b00 cmp r3, #0 8005416: d101 bne.n 800541c { return HAL_ERROR; 8005418: 2301 movs r3, #1 800541a: e041 b.n 80054a0 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800541c: 687b ldr r3, [r7, #4] 800541e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8005422: b2db uxtb r3, r3 8005424: 2b00 cmp r3, #0 8005426: d106 bne.n 8005436 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005428: 687b ldr r3, [r7, #4] 800542a: 2200 movs r2, #0 800542c: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 8005430: 6878 ldr r0, [r7, #4] 8005432: f7fb ff1f bl 8001274 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005436: 687b ldr r3, [r7, #4] 8005438: 2202 movs r2, #2 800543a: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800543e: 687b ldr r3, [r7, #4] 8005440: 681a ldr r2, [r3, #0] 8005442: 687b ldr r3, [r7, #4] 8005444: 3304 adds r3, #4 8005446: 4619 mov r1, r3 8005448: 4610 mov r0, r2 800544a: f000 fa7d bl 8005948 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800544e: 687b ldr r3, [r7, #4] 8005450: 2201 movs r2, #1 8005452: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005456: 687b ldr r3, [r7, #4] 8005458: 2201 movs r2, #1 800545a: f883 203e strb.w r2, [r3, #62] @ 0x3e 800545e: 687b ldr r3, [r7, #4] 8005460: 2201 movs r2, #1 8005462: f883 203f strb.w r2, [r3, #63] @ 0x3f 8005466: 687b ldr r3, [r7, #4] 8005468: 2201 movs r2, #1 800546a: f883 2040 strb.w r2, [r3, #64] @ 0x40 800546e: 687b ldr r3, [r7, #4] 8005470: 2201 movs r2, #1 8005472: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005476: 687b ldr r3, [r7, #4] 8005478: 2201 movs r2, #1 800547a: f883 2042 strb.w r2, [r3, #66] @ 0x42 800547e: 687b ldr r3, [r7, #4] 8005480: 2201 movs r2, #1 8005482: f883 2043 strb.w r2, [r3, #67] @ 0x43 8005486: 687b ldr r3, [r7, #4] 8005488: 2201 movs r2, #1 800548a: f883 2044 strb.w r2, [r3, #68] @ 0x44 800548e: 687b ldr r3, [r7, #4] 8005490: 2201 movs r2, #1 8005492: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005496: 687b ldr r3, [r7, #4] 8005498: 2201 movs r2, #1 800549a: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 800549e: 2300 movs r3, #0 } 80054a0: 4618 mov r0, r3 80054a2: 3708 adds r7, #8 80054a4: 46bd mov sp, r7 80054a6: bd80 pop {r7, pc} 080054a8 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 80054a8: b480 push {r7} 80054aa: b085 sub sp, #20 80054ac: af00 add r7, sp, #0 80054ae: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 80054b0: 687b ldr r3, [r7, #4] 80054b2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80054b6: b2db uxtb r3, r3 80054b8: 2b01 cmp r3, #1 80054ba: d001 beq.n 80054c0 { return HAL_ERROR; 80054bc: 2301 movs r3, #1 80054be: e04e b.n 800555e } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80054c0: 687b ldr r3, [r7, #4] 80054c2: 2202 movs r2, #2 80054c4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 80054c8: 687b ldr r3, [r7, #4] 80054ca: 681b ldr r3, [r3, #0] 80054cc: 68da ldr r2, [r3, #12] 80054ce: 687b ldr r3, [r7, #4] 80054d0: 681b ldr r3, [r3, #0] 80054d2: f042 0201 orr.w r2, r2, #1 80054d6: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80054d8: 687b ldr r3, [r7, #4] 80054da: 681b ldr r3, [r3, #0] 80054dc: 4a23 ldr r2, [pc, #140] @ (800556c ) 80054de: 4293 cmp r3, r2 80054e0: d022 beq.n 8005528 80054e2: 687b ldr r3, [r7, #4] 80054e4: 681b ldr r3, [r3, #0] 80054e6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80054ea: d01d beq.n 8005528 80054ec: 687b ldr r3, [r7, #4] 80054ee: 681b ldr r3, [r3, #0] 80054f0: 4a1f ldr r2, [pc, #124] @ (8005570 ) 80054f2: 4293 cmp r3, r2 80054f4: d018 beq.n 8005528 80054f6: 687b ldr r3, [r7, #4] 80054f8: 681b ldr r3, [r3, #0] 80054fa: 4a1e ldr r2, [pc, #120] @ (8005574 ) 80054fc: 4293 cmp r3, r2 80054fe: d013 beq.n 8005528 8005500: 687b ldr r3, [r7, #4] 8005502: 681b ldr r3, [r3, #0] 8005504: 4a1c ldr r2, [pc, #112] @ (8005578 ) 8005506: 4293 cmp r3, r2 8005508: d00e beq.n 8005528 800550a: 687b ldr r3, [r7, #4] 800550c: 681b ldr r3, [r3, #0] 800550e: 4a1b ldr r2, [pc, #108] @ (800557c ) 8005510: 4293 cmp r3, r2 8005512: d009 beq.n 8005528 8005514: 687b ldr r3, [r7, #4] 8005516: 681b ldr r3, [r3, #0] 8005518: 4a19 ldr r2, [pc, #100] @ (8005580 ) 800551a: 4293 cmp r3, r2 800551c: d004 beq.n 8005528 800551e: 687b ldr r3, [r7, #4] 8005520: 681b ldr r3, [r3, #0] 8005522: 4a18 ldr r2, [pc, #96] @ (8005584 ) 8005524: 4293 cmp r3, r2 8005526: d111 bne.n 800554c { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005528: 687b ldr r3, [r7, #4] 800552a: 681b ldr r3, [r3, #0] 800552c: 689b ldr r3, [r3, #8] 800552e: f003 0307 and.w r3, r3, #7 8005532: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005534: 68fb ldr r3, [r7, #12] 8005536: 2b06 cmp r3, #6 8005538: d010 beq.n 800555c { __HAL_TIM_ENABLE(htim); 800553a: 687b ldr r3, [r7, #4] 800553c: 681b ldr r3, [r3, #0] 800553e: 681a ldr r2, [r3, #0] 8005540: 687b ldr r3, [r7, #4] 8005542: 681b ldr r3, [r3, #0] 8005544: f042 0201 orr.w r2, r2, #1 8005548: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800554a: e007 b.n 800555c } } else { __HAL_TIM_ENABLE(htim); 800554c: 687b ldr r3, [r7, #4] 800554e: 681b ldr r3, [r3, #0] 8005550: 681a ldr r2, [r3, #0] 8005552: 687b ldr r3, [r7, #4] 8005554: 681b ldr r3, [r3, #0] 8005556: f042 0201 orr.w r2, r2, #1 800555a: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 800555c: 2300 movs r3, #0 } 800555e: 4618 mov r0, r3 8005560: 3714 adds r7, #20 8005562: 46bd mov sp, r7 8005564: f85d 7b04 ldr.w r7, [sp], #4 8005568: 4770 bx lr 800556a: bf00 nop 800556c: 40010000 .word 0x40010000 8005570: 40000400 .word 0x40000400 8005574: 40000800 .word 0x40000800 8005578: 40000c00 .word 0x40000c00 800557c: 40010400 .word 0x40010400 8005580: 40014000 .word 0x40014000 8005584: 40001800 .word 0x40001800 08005588 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005588: b580 push {r7, lr} 800558a: b084 sub sp, #16 800558c: af00 add r7, sp, #0 800558e: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8005590: 687b ldr r3, [r7, #4] 8005592: 681b ldr r3, [r3, #0] 8005594: 68db ldr r3, [r3, #12] 8005596: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8005598: 687b ldr r3, [r7, #4] 800559a: 681b ldr r3, [r3, #0] 800559c: 691b ldr r3, [r3, #16] 800559e: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 80055a0: 68bb ldr r3, [r7, #8] 80055a2: f003 0302 and.w r3, r3, #2 80055a6: 2b00 cmp r3, #0 80055a8: d020 beq.n 80055ec { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 80055aa: 68fb ldr r3, [r7, #12] 80055ac: f003 0302 and.w r3, r3, #2 80055b0: 2b00 cmp r3, #0 80055b2: d01b beq.n 80055ec { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 80055b4: 687b ldr r3, [r7, #4] 80055b6: 681b ldr r3, [r3, #0] 80055b8: f06f 0202 mvn.w r2, #2 80055bc: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 80055be: 687b ldr r3, [r7, #4] 80055c0: 2201 movs r2, #1 80055c2: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 80055c4: 687b ldr r3, [r7, #4] 80055c6: 681b ldr r3, [r3, #0] 80055c8: 699b ldr r3, [r3, #24] 80055ca: f003 0303 and.w r3, r3, #3 80055ce: 2b00 cmp r3, #0 80055d0: d003 beq.n 80055da { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80055d2: 6878 ldr r0, [r7, #4] 80055d4: f000 f999 bl 800590a 80055d8: e005 b.n 80055e6 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80055da: 6878 ldr r0, [r7, #4] 80055dc: f000 f98b bl 80058f6 HAL_TIM_PWM_PulseFinishedCallback(htim); 80055e0: 6878 ldr r0, [r7, #4] 80055e2: f000 f99c bl 800591e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80055e6: 687b ldr r3, [r7, #4] 80055e8: 2200 movs r2, #0 80055ea: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80055ec: 68bb ldr r3, [r7, #8] 80055ee: f003 0304 and.w r3, r3, #4 80055f2: 2b00 cmp r3, #0 80055f4: d020 beq.n 8005638 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80055f6: 68fb ldr r3, [r7, #12] 80055f8: f003 0304 and.w r3, r3, #4 80055fc: 2b00 cmp r3, #0 80055fe: d01b beq.n 8005638 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8005600: 687b ldr r3, [r7, #4] 8005602: 681b ldr r3, [r3, #0] 8005604: f06f 0204 mvn.w r2, #4 8005608: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 800560a: 687b ldr r3, [r7, #4] 800560c: 2202 movs r2, #2 800560e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8005610: 687b ldr r3, [r7, #4] 8005612: 681b ldr r3, [r3, #0] 8005614: 699b ldr r3, [r3, #24] 8005616: f403 7340 and.w r3, r3, #768 @ 0x300 800561a: 2b00 cmp r3, #0 800561c: d003 beq.n 8005626 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800561e: 6878 ldr r0, [r7, #4] 8005620: f000 f973 bl 800590a 8005624: e005 b.n 8005632 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005626: 6878 ldr r0, [r7, #4] 8005628: f000 f965 bl 80058f6 HAL_TIM_PWM_PulseFinishedCallback(htim); 800562c: 6878 ldr r0, [r7, #4] 800562e: f000 f976 bl 800591e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005632: 687b ldr r3, [r7, #4] 8005634: 2200 movs r2, #0 8005636: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8005638: 68bb ldr r3, [r7, #8] 800563a: f003 0308 and.w r3, r3, #8 800563e: 2b00 cmp r3, #0 8005640: d020 beq.n 8005684 { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8005642: 68fb ldr r3, [r7, #12] 8005644: f003 0308 and.w r3, r3, #8 8005648: 2b00 cmp r3, #0 800564a: d01b beq.n 8005684 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 800564c: 687b ldr r3, [r7, #4] 800564e: 681b ldr r3, [r3, #0] 8005650: f06f 0208 mvn.w r2, #8 8005654: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8005656: 687b ldr r3, [r7, #4] 8005658: 2204 movs r2, #4 800565a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 800565c: 687b ldr r3, [r7, #4] 800565e: 681b ldr r3, [r3, #0] 8005660: 69db ldr r3, [r3, #28] 8005662: f003 0303 and.w r3, r3, #3 8005666: 2b00 cmp r3, #0 8005668: d003 beq.n 8005672 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800566a: 6878 ldr r0, [r7, #4] 800566c: f000 f94d bl 800590a 8005670: e005 b.n 800567e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005672: 6878 ldr r0, [r7, #4] 8005674: f000 f93f bl 80058f6 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005678: 6878 ldr r0, [r7, #4] 800567a: f000 f950 bl 800591e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800567e: 687b ldr r3, [r7, #4] 8005680: 2200 movs r2, #0 8005682: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8005684: 68bb ldr r3, [r7, #8] 8005686: f003 0310 and.w r3, r3, #16 800568a: 2b00 cmp r3, #0 800568c: d020 beq.n 80056d0 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 800568e: 68fb ldr r3, [r7, #12] 8005690: f003 0310 and.w r3, r3, #16 8005694: 2b00 cmp r3, #0 8005696: d01b beq.n 80056d0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8005698: 687b ldr r3, [r7, #4] 800569a: 681b ldr r3, [r3, #0] 800569c: f06f 0210 mvn.w r2, #16 80056a0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 80056a2: 687b ldr r3, [r7, #4] 80056a4: 2208 movs r2, #8 80056a6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 80056a8: 687b ldr r3, [r7, #4] 80056aa: 681b ldr r3, [r3, #0] 80056ac: 69db ldr r3, [r3, #28] 80056ae: f403 7340 and.w r3, r3, #768 @ 0x300 80056b2: 2b00 cmp r3, #0 80056b4: d003 beq.n 80056be { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80056b6: 6878 ldr r0, [r7, #4] 80056b8: f000 f927 bl 800590a 80056bc: e005 b.n 80056ca { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80056be: 6878 ldr r0, [r7, #4] 80056c0: f000 f919 bl 80058f6 HAL_TIM_PWM_PulseFinishedCallback(htim); 80056c4: 6878 ldr r0, [r7, #4] 80056c6: f000 f92a bl 800591e #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80056ca: 687b ldr r3, [r7, #4] 80056cc: 2200 movs r2, #0 80056ce: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 80056d0: 68bb ldr r3, [r7, #8] 80056d2: f003 0301 and.w r3, r3, #1 80056d6: 2b00 cmp r3, #0 80056d8: d00c beq.n 80056f4 { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 80056da: 68fb ldr r3, [r7, #12] 80056dc: f003 0301 and.w r3, r3, #1 80056e0: 2b00 cmp r3, #0 80056e2: d007 beq.n 80056f4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 80056e4: 687b ldr r3, [r7, #4] 80056e6: 681b ldr r3, [r3, #0] 80056e8: f06f 0201 mvn.w r2, #1 80056ec: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80056ee: 6878 ldr r0, [r7, #4] 80056f0: f7fb fb50 bl 8000d94 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 80056f4: 68bb ldr r3, [r7, #8] 80056f6: f003 0380 and.w r3, r3, #128 @ 0x80 80056fa: 2b00 cmp r3, #0 80056fc: d00c beq.n 8005718 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80056fe: 68fb ldr r3, [r7, #12] 8005700: f003 0380 and.w r3, r3, #128 @ 0x80 8005704: 2b00 cmp r3, #0 8005706: d007 beq.n 8005718 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 8005708: 687b ldr r3, [r7, #4] 800570a: 681b ldr r3, [r3, #0] 800570c: f06f 0280 mvn.w r2, #128 @ 0x80 8005710: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8005712: 6878 ldr r0, [r7, #4] 8005714: f000 fade bl 8005cd4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8005718: 68bb ldr r3, [r7, #8] 800571a: f003 0340 and.w r3, r3, #64 @ 0x40 800571e: 2b00 cmp r3, #0 8005720: d00c beq.n 800573c { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8005722: 68fb ldr r3, [r7, #12] 8005724: f003 0340 and.w r3, r3, #64 @ 0x40 8005728: 2b00 cmp r3, #0 800572a: d007 beq.n 800573c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 800572c: 687b ldr r3, [r7, #4] 800572e: 681b ldr r3, [r3, #0] 8005730: f06f 0240 mvn.w r2, #64 @ 0x40 8005734: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8005736: 6878 ldr r0, [r7, #4] 8005738: f000 f8fb bl 8005932 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 800573c: 68bb ldr r3, [r7, #8] 800573e: f003 0320 and.w r3, r3, #32 8005742: 2b00 cmp r3, #0 8005744: d00c beq.n 8005760 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8005746: 68fb ldr r3, [r7, #12] 8005748: f003 0320 and.w r3, r3, #32 800574c: 2b00 cmp r3, #0 800574e: d007 beq.n 8005760 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8005750: 687b ldr r3, [r7, #4] 8005752: 681b ldr r3, [r3, #0] 8005754: f06f 0220 mvn.w r2, #32 8005758: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 800575a: 6878 ldr r0, [r7, #4] 800575c: f000 fab0 bl 8005cc0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8005760: bf00 nop 8005762: 3710 adds r7, #16 8005764: 46bd mov sp, r7 8005766: bd80 pop {r7, pc} 08005768 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8005768: b580 push {r7, lr} 800576a: b084 sub sp, #16 800576c: af00 add r7, sp, #0 800576e: 6078 str r0, [r7, #4] 8005770: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005772: 2300 movs r3, #0 8005774: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8005776: 687b ldr r3, [r7, #4] 8005778: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 800577c: 2b01 cmp r3, #1 800577e: d101 bne.n 8005784 8005780: 2302 movs r3, #2 8005782: e0b4 b.n 80058ee 8005784: 687b ldr r3, [r7, #4] 8005786: 2201 movs r2, #1 8005788: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 800578c: 687b ldr r3, [r7, #4] 800578e: 2202 movs r2, #2 8005790: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8005794: 687b ldr r3, [r7, #4] 8005796: 681b ldr r3, [r3, #0] 8005798: 689b ldr r3, [r3, #8] 800579a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 800579c: 68bb ldr r3, [r7, #8] 800579e: f023 0377 bic.w r3, r3, #119 @ 0x77 80057a2: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 80057a4: 68bb ldr r3, [r7, #8] 80057a6: f423 437f bic.w r3, r3, #65280 @ 0xff00 80057aa: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 80057ac: 687b ldr r3, [r7, #4] 80057ae: 681b ldr r3, [r3, #0] 80057b0: 68ba ldr r2, [r7, #8] 80057b2: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 80057b4: 683b ldr r3, [r7, #0] 80057b6: 681b ldr r3, [r3, #0] 80057b8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80057bc: d03e beq.n 800583c 80057be: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 80057c2: f200 8087 bhi.w 80058d4 80057c6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80057ca: f000 8086 beq.w 80058da 80057ce: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 80057d2: d87f bhi.n 80058d4 80057d4: 2b70 cmp r3, #112 @ 0x70 80057d6: d01a beq.n 800580e 80057d8: 2b70 cmp r3, #112 @ 0x70 80057da: d87b bhi.n 80058d4 80057dc: 2b60 cmp r3, #96 @ 0x60 80057de: d050 beq.n 8005882 80057e0: 2b60 cmp r3, #96 @ 0x60 80057e2: d877 bhi.n 80058d4 80057e4: 2b50 cmp r3, #80 @ 0x50 80057e6: d03c beq.n 8005862 80057e8: 2b50 cmp r3, #80 @ 0x50 80057ea: d873 bhi.n 80058d4 80057ec: 2b40 cmp r3, #64 @ 0x40 80057ee: d058 beq.n 80058a2 80057f0: 2b40 cmp r3, #64 @ 0x40 80057f2: d86f bhi.n 80058d4 80057f4: 2b30 cmp r3, #48 @ 0x30 80057f6: d064 beq.n 80058c2 80057f8: 2b30 cmp r3, #48 @ 0x30 80057fa: d86b bhi.n 80058d4 80057fc: 2b20 cmp r3, #32 80057fe: d060 beq.n 80058c2 8005800: 2b20 cmp r3, #32 8005802: d867 bhi.n 80058d4 8005804: 2b00 cmp r3, #0 8005806: d05c beq.n 80058c2 8005808: 2b10 cmp r3, #16 800580a: d05a beq.n 80058c2 800580c: e062 b.n 80058d4 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800580e: 687b ldr r3, [r7, #4] 8005810: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8005812: 683b ldr r3, [r7, #0] 8005814: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8005816: 683b ldr r3, [r7, #0] 8005818: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 800581a: 683b ldr r3, [r7, #0] 800581c: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800581e: f000 f9b3 bl 8005b88 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8005822: 687b ldr r3, [r7, #4] 8005824: 681b ldr r3, [r3, #0] 8005826: 689b ldr r3, [r3, #8] 8005828: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 800582a: 68bb ldr r3, [r7, #8] 800582c: f043 0377 orr.w r3, r3, #119 @ 0x77 8005830: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005832: 687b ldr r3, [r7, #4] 8005834: 681b ldr r3, [r3, #0] 8005836: 68ba ldr r2, [r7, #8] 8005838: 609a str r2, [r3, #8] break; 800583a: e04f b.n 80058dc assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 800583c: 687b ldr r3, [r7, #4] 800583e: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8005840: 683b ldr r3, [r7, #0] 8005842: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8005844: 683b ldr r3, [r7, #0] 8005846: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8005848: 683b ldr r3, [r7, #0] 800584a: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800584c: f000 f99c bl 8005b88 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8005850: 687b ldr r3, [r7, #4] 8005852: 681b ldr r3, [r3, #0] 8005854: 689a ldr r2, [r3, #8] 8005856: 687b ldr r3, [r7, #4] 8005858: 681b ldr r3, [r3, #0] 800585a: f442 4280 orr.w r2, r2, #16384 @ 0x4000 800585e: 609a str r2, [r3, #8] break; 8005860: e03c b.n 80058dc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8005862: 687b ldr r3, [r7, #4] 8005864: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8005866: 683b ldr r3, [r7, #0] 8005868: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800586a: 683b ldr r3, [r7, #0] 800586c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800586e: 461a mov r2, r3 8005870: f000 f910 bl 8005a94 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8005874: 687b ldr r3, [r7, #4] 8005876: 681b ldr r3, [r3, #0] 8005878: 2150 movs r1, #80 @ 0x50 800587a: 4618 mov r0, r3 800587c: f000 f969 bl 8005b52 break; 8005880: e02c b.n 80058dc /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8005882: 687b ldr r3, [r7, #4] 8005884: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8005886: 683b ldr r3, [r7, #0] 8005888: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800588a: 683b ldr r3, [r7, #0] 800588c: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800588e: 461a mov r2, r3 8005890: f000 f92f bl 8005af2 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8005894: 687b ldr r3, [r7, #4] 8005896: 681b ldr r3, [r3, #0] 8005898: 2160 movs r1, #96 @ 0x60 800589a: 4618 mov r0, r3 800589c: f000 f959 bl 8005b52 break; 80058a0: e01c b.n 80058dc /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 80058a2: 687b ldr r3, [r7, #4] 80058a4: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 80058a6: 683b ldr r3, [r7, #0] 80058a8: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 80058aa: 683b ldr r3, [r7, #0] 80058ac: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 80058ae: 461a mov r2, r3 80058b0: f000 f8f0 bl 8005a94 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 80058b4: 687b ldr r3, [r7, #4] 80058b6: 681b ldr r3, [r3, #0] 80058b8: 2140 movs r1, #64 @ 0x40 80058ba: 4618 mov r0, r3 80058bc: f000 f949 bl 8005b52 break; 80058c0: e00c b.n 80058dc case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 80058c2: 687b ldr r3, [r7, #4] 80058c4: 681a ldr r2, [r3, #0] 80058c6: 683b ldr r3, [r7, #0] 80058c8: 681b ldr r3, [r3, #0] 80058ca: 4619 mov r1, r3 80058cc: 4610 mov r0, r2 80058ce: f000 f940 bl 8005b52 break; 80058d2: e003 b.n 80058dc } default: status = HAL_ERROR; 80058d4: 2301 movs r3, #1 80058d6: 73fb strb r3, [r7, #15] break; 80058d8: e000 b.n 80058dc break; 80058da: bf00 nop } htim->State = HAL_TIM_STATE_READY; 80058dc: 687b ldr r3, [r7, #4] 80058de: 2201 movs r2, #1 80058e0: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 80058e4: 687b ldr r3, [r7, #4] 80058e6: 2200 movs r2, #0 80058e8: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80058ec: 7bfb ldrb r3, [r7, #15] } 80058ee: 4618 mov r0, r3 80058f0: 3710 adds r7, #16 80058f2: 46bd mov sp, r7 80058f4: bd80 pop {r7, pc} 080058f6 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80058f6: b480 push {r7} 80058f8: b083 sub sp, #12 80058fa: af00 add r7, sp, #0 80058fc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80058fe: bf00 nop 8005900: 370c adds r7, #12 8005902: 46bd mov sp, r7 8005904: f85d 7b04 ldr.w r7, [sp], #4 8005908: 4770 bx lr 0800590a : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 800590a: b480 push {r7} 800590c: b083 sub sp, #12 800590e: af00 add r7, sp, #0 8005910: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 8005912: bf00 nop 8005914: 370c adds r7, #12 8005916: 46bd mov sp, r7 8005918: f85d 7b04 ldr.w r7, [sp], #4 800591c: 4770 bx lr 0800591e : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 800591e: b480 push {r7} 8005920: b083 sub sp, #12 8005922: af00 add r7, sp, #0 8005924: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 8005926: bf00 nop 8005928: 370c adds r7, #12 800592a: 46bd mov sp, r7 800592c: f85d 7b04 ldr.w r7, [sp], #4 8005930: 4770 bx lr 08005932 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 8005932: b480 push {r7} 8005934: b083 sub sp, #12 8005936: af00 add r7, sp, #0 8005938: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 800593a: bf00 nop 800593c: 370c adds r7, #12 800593e: 46bd mov sp, r7 8005940: f85d 7b04 ldr.w r7, [sp], #4 8005944: 4770 bx lr ... 08005948 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005948: b480 push {r7} 800594a: b085 sub sp, #20 800594c: af00 add r7, sp, #0 800594e: 6078 str r0, [r7, #4] 8005950: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8005952: 687b ldr r3, [r7, #4] 8005954: 681b ldr r3, [r3, #0] 8005956: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005958: 687b ldr r3, [r7, #4] 800595a: 4a43 ldr r2, [pc, #268] @ (8005a68 ) 800595c: 4293 cmp r3, r2 800595e: d013 beq.n 8005988 8005960: 687b ldr r3, [r7, #4] 8005962: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005966: d00f beq.n 8005988 8005968: 687b ldr r3, [r7, #4] 800596a: 4a40 ldr r2, [pc, #256] @ (8005a6c ) 800596c: 4293 cmp r3, r2 800596e: d00b beq.n 8005988 8005970: 687b ldr r3, [r7, #4] 8005972: 4a3f ldr r2, [pc, #252] @ (8005a70 ) 8005974: 4293 cmp r3, r2 8005976: d007 beq.n 8005988 8005978: 687b ldr r3, [r7, #4] 800597a: 4a3e ldr r2, [pc, #248] @ (8005a74 ) 800597c: 4293 cmp r3, r2 800597e: d003 beq.n 8005988 8005980: 687b ldr r3, [r7, #4] 8005982: 4a3d ldr r2, [pc, #244] @ (8005a78 ) 8005984: 4293 cmp r3, r2 8005986: d108 bne.n 800599a { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005988: 68fb ldr r3, [r7, #12] 800598a: f023 0370 bic.w r3, r3, #112 @ 0x70 800598e: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005990: 683b ldr r3, [r7, #0] 8005992: 685b ldr r3, [r3, #4] 8005994: 68fa ldr r2, [r7, #12] 8005996: 4313 orrs r3, r2 8005998: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 800599a: 687b ldr r3, [r7, #4] 800599c: 4a32 ldr r2, [pc, #200] @ (8005a68 ) 800599e: 4293 cmp r3, r2 80059a0: d02b beq.n 80059fa 80059a2: 687b ldr r3, [r7, #4] 80059a4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80059a8: d027 beq.n 80059fa 80059aa: 687b ldr r3, [r7, #4] 80059ac: 4a2f ldr r2, [pc, #188] @ (8005a6c ) 80059ae: 4293 cmp r3, r2 80059b0: d023 beq.n 80059fa 80059b2: 687b ldr r3, [r7, #4] 80059b4: 4a2e ldr r2, [pc, #184] @ (8005a70 ) 80059b6: 4293 cmp r3, r2 80059b8: d01f beq.n 80059fa 80059ba: 687b ldr r3, [r7, #4] 80059bc: 4a2d ldr r2, [pc, #180] @ (8005a74 ) 80059be: 4293 cmp r3, r2 80059c0: d01b beq.n 80059fa 80059c2: 687b ldr r3, [r7, #4] 80059c4: 4a2c ldr r2, [pc, #176] @ (8005a78 ) 80059c6: 4293 cmp r3, r2 80059c8: d017 beq.n 80059fa 80059ca: 687b ldr r3, [r7, #4] 80059cc: 4a2b ldr r2, [pc, #172] @ (8005a7c ) 80059ce: 4293 cmp r3, r2 80059d0: d013 beq.n 80059fa 80059d2: 687b ldr r3, [r7, #4] 80059d4: 4a2a ldr r2, [pc, #168] @ (8005a80 ) 80059d6: 4293 cmp r3, r2 80059d8: d00f beq.n 80059fa 80059da: 687b ldr r3, [r7, #4] 80059dc: 4a29 ldr r2, [pc, #164] @ (8005a84 ) 80059de: 4293 cmp r3, r2 80059e0: d00b beq.n 80059fa 80059e2: 687b ldr r3, [r7, #4] 80059e4: 4a28 ldr r2, [pc, #160] @ (8005a88 ) 80059e6: 4293 cmp r3, r2 80059e8: d007 beq.n 80059fa 80059ea: 687b ldr r3, [r7, #4] 80059ec: 4a27 ldr r2, [pc, #156] @ (8005a8c ) 80059ee: 4293 cmp r3, r2 80059f0: d003 beq.n 80059fa 80059f2: 687b ldr r3, [r7, #4] 80059f4: 4a26 ldr r2, [pc, #152] @ (8005a90 ) 80059f6: 4293 cmp r3, r2 80059f8: d108 bne.n 8005a0c { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80059fa: 68fb ldr r3, [r7, #12] 80059fc: f423 7340 bic.w r3, r3, #768 @ 0x300 8005a00: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 8005a02: 683b ldr r3, [r7, #0] 8005a04: 68db ldr r3, [r3, #12] 8005a06: 68fa ldr r2, [r7, #12] 8005a08: 4313 orrs r3, r2 8005a0a: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8005a0c: 68fb ldr r3, [r7, #12] 8005a0e: f023 0280 bic.w r2, r3, #128 @ 0x80 8005a12: 683b ldr r3, [r7, #0] 8005a14: 695b ldr r3, [r3, #20] 8005a16: 4313 orrs r3, r2 8005a18: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8005a1a: 683b ldr r3, [r7, #0] 8005a1c: 689a ldr r2, [r3, #8] 8005a1e: 687b ldr r3, [r7, #4] 8005a20: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 8005a22: 683b ldr r3, [r7, #0] 8005a24: 681a ldr r2, [r3, #0] 8005a26: 687b ldr r3, [r7, #4] 8005a28: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 8005a2a: 687b ldr r3, [r7, #4] 8005a2c: 4a0e ldr r2, [pc, #56] @ (8005a68 ) 8005a2e: 4293 cmp r3, r2 8005a30: d003 beq.n 8005a3a 8005a32: 687b ldr r3, [r7, #4] 8005a34: 4a10 ldr r2, [pc, #64] @ (8005a78 ) 8005a36: 4293 cmp r3, r2 8005a38: d103 bne.n 8005a42 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 8005a3a: 683b ldr r3, [r7, #0] 8005a3c: 691a ldr r2, [r3, #16] 8005a3e: 687b ldr r3, [r7, #4] 8005a40: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 8005a42: 687b ldr r3, [r7, #4] 8005a44: 681b ldr r3, [r3, #0] 8005a46: f043 0204 orr.w r2, r3, #4 8005a4a: 687b ldr r3, [r7, #4] 8005a4c: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8005a4e: 687b ldr r3, [r7, #4] 8005a50: 2201 movs r2, #1 8005a52: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005a54: 687b ldr r3, [r7, #4] 8005a56: 68fa ldr r2, [r7, #12] 8005a58: 601a str r2, [r3, #0] } 8005a5a: bf00 nop 8005a5c: 3714 adds r7, #20 8005a5e: 46bd mov sp, r7 8005a60: f85d 7b04 ldr.w r7, [sp], #4 8005a64: 4770 bx lr 8005a66: bf00 nop 8005a68: 40010000 .word 0x40010000 8005a6c: 40000400 .word 0x40000400 8005a70: 40000800 .word 0x40000800 8005a74: 40000c00 .word 0x40000c00 8005a78: 40010400 .word 0x40010400 8005a7c: 40014000 .word 0x40014000 8005a80: 40014400 .word 0x40014400 8005a84: 40014800 .word 0x40014800 8005a88: 40001800 .word 0x40001800 8005a8c: 40001c00 .word 0x40001c00 8005a90: 40002000 .word 0x40002000 08005a94 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005a94: b480 push {r7} 8005a96: b087 sub sp, #28 8005a98: af00 add r7, sp, #0 8005a9a: 60f8 str r0, [r7, #12] 8005a9c: 60b9 str r1, [r7, #8] 8005a9e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005aa0: 68fb ldr r3, [r7, #12] 8005aa2: 6a1b ldr r3, [r3, #32] 8005aa4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8005aa6: 68fb ldr r3, [r7, #12] 8005aa8: 6a1b ldr r3, [r3, #32] 8005aaa: f023 0201 bic.w r2, r3, #1 8005aae: 68fb ldr r3, [r7, #12] 8005ab0: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005ab2: 68fb ldr r3, [r7, #12] 8005ab4: 699b ldr r3, [r3, #24] 8005ab6: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005ab8: 693b ldr r3, [r7, #16] 8005aba: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005abe: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8005ac0: 687b ldr r3, [r7, #4] 8005ac2: 011b lsls r3, r3, #4 8005ac4: 693a ldr r2, [r7, #16] 8005ac6: 4313 orrs r3, r2 8005ac8: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005aca: 697b ldr r3, [r7, #20] 8005acc: f023 030a bic.w r3, r3, #10 8005ad0: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8005ad2: 697a ldr r2, [r7, #20] 8005ad4: 68bb ldr r3, [r7, #8] 8005ad6: 4313 orrs r3, r2 8005ad8: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8005ada: 68fb ldr r3, [r7, #12] 8005adc: 693a ldr r2, [r7, #16] 8005ade: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005ae0: 68fb ldr r3, [r7, #12] 8005ae2: 697a ldr r2, [r7, #20] 8005ae4: 621a str r2, [r3, #32] } 8005ae6: bf00 nop 8005ae8: 371c adds r7, #28 8005aea: 46bd mov sp, r7 8005aec: f85d 7b04 ldr.w r7, [sp], #4 8005af0: 4770 bx lr 08005af2 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005af2: b480 push {r7} 8005af4: b087 sub sp, #28 8005af6: af00 add r7, sp, #0 8005af8: 60f8 str r0, [r7, #12] 8005afa: 60b9 str r1, [r7, #8] 8005afc: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8005afe: 68fb ldr r3, [r7, #12] 8005b00: 6a1b ldr r3, [r3, #32] 8005b02: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8005b04: 68fb ldr r3, [r7, #12] 8005b06: 6a1b ldr r3, [r3, #32] 8005b08: f023 0210 bic.w r2, r3, #16 8005b0c: 68fb ldr r3, [r7, #12] 8005b0e: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005b10: 68fb ldr r3, [r7, #12] 8005b12: 699b ldr r3, [r3, #24] 8005b14: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8005b16: 693b ldr r3, [r7, #16] 8005b18: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005b1c: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8005b1e: 687b ldr r3, [r7, #4] 8005b20: 031b lsls r3, r3, #12 8005b22: 693a ldr r2, [r7, #16] 8005b24: 4313 orrs r3, r2 8005b26: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8005b28: 697b ldr r3, [r7, #20] 8005b2a: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8005b2e: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8005b30: 68bb ldr r3, [r7, #8] 8005b32: 011b lsls r3, r3, #4 8005b34: 697a ldr r2, [r7, #20] 8005b36: 4313 orrs r3, r2 8005b38: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8005b3a: 68fb ldr r3, [r7, #12] 8005b3c: 693a ldr r2, [r7, #16] 8005b3e: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005b40: 68fb ldr r3, [r7, #12] 8005b42: 697a ldr r2, [r7, #20] 8005b44: 621a str r2, [r3, #32] } 8005b46: bf00 nop 8005b48: 371c adds r7, #28 8005b4a: 46bd mov sp, r7 8005b4c: f85d 7b04 ldr.w r7, [sp], #4 8005b50: 4770 bx lr 08005b52 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8005b52: b480 push {r7} 8005b54: b085 sub sp, #20 8005b56: af00 add r7, sp, #0 8005b58: 6078 str r0, [r7, #4] 8005b5a: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8005b5c: 687b ldr r3, [r7, #4] 8005b5e: 689b ldr r3, [r3, #8] 8005b60: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8005b62: 68fb ldr r3, [r7, #12] 8005b64: f023 0370 bic.w r3, r3, #112 @ 0x70 8005b68: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8005b6a: 683a ldr r2, [r7, #0] 8005b6c: 68fb ldr r3, [r7, #12] 8005b6e: 4313 orrs r3, r2 8005b70: f043 0307 orr.w r3, r3, #7 8005b74: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005b76: 687b ldr r3, [r7, #4] 8005b78: 68fa ldr r2, [r7, #12] 8005b7a: 609a str r2, [r3, #8] } 8005b7c: bf00 nop 8005b7e: 3714 adds r7, #20 8005b80: 46bd mov sp, r7 8005b82: f85d 7b04 ldr.w r7, [sp], #4 8005b86: 4770 bx lr 08005b88 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005b88: b480 push {r7} 8005b8a: b087 sub sp, #28 8005b8c: af00 add r7, sp, #0 8005b8e: 60f8 str r0, [r7, #12] 8005b90: 60b9 str r1, [r7, #8] 8005b92: 607a str r2, [r7, #4] 8005b94: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8005b96: 68fb ldr r3, [r7, #12] 8005b98: 689b ldr r3, [r3, #8] 8005b9a: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005b9c: 697b ldr r3, [r7, #20] 8005b9e: f423 437f bic.w r3, r3, #65280 @ 0xff00 8005ba2: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8005ba4: 683b ldr r3, [r7, #0] 8005ba6: 021a lsls r2, r3, #8 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 431a orrs r2, r3 8005bac: 68bb ldr r3, [r7, #8] 8005bae: 4313 orrs r3, r2 8005bb0: 697a ldr r2, [r7, #20] 8005bb2: 4313 orrs r3, r2 8005bb4: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005bb6: 68fb ldr r3, [r7, #12] 8005bb8: 697a ldr r2, [r7, #20] 8005bba: 609a str r2, [r3, #8] } 8005bbc: bf00 nop 8005bbe: 371c adds r7, #28 8005bc0: 46bd mov sp, r7 8005bc2: f85d 7b04 ldr.w r7, [sp], #4 8005bc6: 4770 bx lr 08005bc8 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005bc8: b480 push {r7} 8005bca: b085 sub sp, #20 8005bcc: af00 add r7, sp, #0 8005bce: 6078 str r0, [r7, #4] 8005bd0: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005bd2: 687b ldr r3, [r7, #4] 8005bd4: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005bd8: 2b01 cmp r3, #1 8005bda: d101 bne.n 8005be0 8005bdc: 2302 movs r3, #2 8005bde: e05a b.n 8005c96 8005be0: 687b ldr r3, [r7, #4] 8005be2: 2201 movs r2, #1 8005be4: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005be8: 687b ldr r3, [r7, #4] 8005bea: 2202 movs r2, #2 8005bec: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 681b ldr r3, [r3, #0] 8005bf4: 685b ldr r3, [r3, #4] 8005bf6: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005bf8: 687b ldr r3, [r7, #4] 8005bfa: 681b ldr r3, [r3, #0] 8005bfc: 689b ldr r3, [r3, #8] 8005bfe: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005c00: 68fb ldr r3, [r7, #12] 8005c02: f023 0370 bic.w r3, r3, #112 @ 0x70 8005c06: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005c08: 683b ldr r3, [r7, #0] 8005c0a: 681b ldr r3, [r3, #0] 8005c0c: 68fa ldr r2, [r7, #12] 8005c0e: 4313 orrs r3, r2 8005c10: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005c12: 687b ldr r3, [r7, #4] 8005c14: 681b ldr r3, [r3, #0] 8005c16: 68fa ldr r2, [r7, #12] 8005c18: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005c1a: 687b ldr r3, [r7, #4] 8005c1c: 681b ldr r3, [r3, #0] 8005c1e: 4a21 ldr r2, [pc, #132] @ (8005ca4 ) 8005c20: 4293 cmp r3, r2 8005c22: d022 beq.n 8005c6a 8005c24: 687b ldr r3, [r7, #4] 8005c26: 681b ldr r3, [r3, #0] 8005c28: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005c2c: d01d beq.n 8005c6a 8005c2e: 687b ldr r3, [r7, #4] 8005c30: 681b ldr r3, [r3, #0] 8005c32: 4a1d ldr r2, [pc, #116] @ (8005ca8 ) 8005c34: 4293 cmp r3, r2 8005c36: d018 beq.n 8005c6a 8005c38: 687b ldr r3, [r7, #4] 8005c3a: 681b ldr r3, [r3, #0] 8005c3c: 4a1b ldr r2, [pc, #108] @ (8005cac ) 8005c3e: 4293 cmp r3, r2 8005c40: d013 beq.n 8005c6a 8005c42: 687b ldr r3, [r7, #4] 8005c44: 681b ldr r3, [r3, #0] 8005c46: 4a1a ldr r2, [pc, #104] @ (8005cb0 ) 8005c48: 4293 cmp r3, r2 8005c4a: d00e beq.n 8005c6a 8005c4c: 687b ldr r3, [r7, #4] 8005c4e: 681b ldr r3, [r3, #0] 8005c50: 4a18 ldr r2, [pc, #96] @ (8005cb4 ) 8005c52: 4293 cmp r3, r2 8005c54: d009 beq.n 8005c6a 8005c56: 687b ldr r3, [r7, #4] 8005c58: 681b ldr r3, [r3, #0] 8005c5a: 4a17 ldr r2, [pc, #92] @ (8005cb8 ) 8005c5c: 4293 cmp r3, r2 8005c5e: d004 beq.n 8005c6a 8005c60: 687b ldr r3, [r7, #4] 8005c62: 681b ldr r3, [r3, #0] 8005c64: 4a15 ldr r2, [pc, #84] @ (8005cbc ) 8005c66: 4293 cmp r3, r2 8005c68: d10c bne.n 8005c84 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005c6a: 68bb ldr r3, [r7, #8] 8005c6c: f023 0380 bic.w r3, r3, #128 @ 0x80 8005c70: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005c72: 683b ldr r3, [r7, #0] 8005c74: 685b ldr r3, [r3, #4] 8005c76: 68ba ldr r2, [r7, #8] 8005c78: 4313 orrs r3, r2 8005c7a: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005c7c: 687b ldr r3, [r7, #4] 8005c7e: 681b ldr r3, [r3, #0] 8005c80: 68ba ldr r2, [r7, #8] 8005c82: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005c84: 687b ldr r3, [r7, #4] 8005c86: 2201 movs r2, #1 8005c88: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005c8c: 687b ldr r3, [r7, #4] 8005c8e: 2200 movs r2, #0 8005c90: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005c94: 2300 movs r3, #0 } 8005c96: 4618 mov r0, r3 8005c98: 3714 adds r7, #20 8005c9a: 46bd mov sp, r7 8005c9c: f85d 7b04 ldr.w r7, [sp], #4 8005ca0: 4770 bx lr 8005ca2: bf00 nop 8005ca4: 40010000 .word 0x40010000 8005ca8: 40000400 .word 0x40000400 8005cac: 40000800 .word 0x40000800 8005cb0: 40000c00 .word 0x40000c00 8005cb4: 40010400 .word 0x40010400 8005cb8: 40014000 .word 0x40014000 8005cbc: 40001800 .word 0x40001800 08005cc0 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8005cc0: b480 push {r7} 8005cc2: b083 sub sp, #12 8005cc4: af00 add r7, sp, #0 8005cc6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8005cc8: bf00 nop 8005cca: 370c adds r7, #12 8005ccc: 46bd mov sp, r7 8005cce: f85d 7b04 ldr.w r7, [sp], #4 8005cd2: 4770 bx lr 08005cd4 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8005cd4: b480 push {r7} 8005cd6: b083 sub sp, #12 8005cd8: af00 add r7, sp, #0 8005cda: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8005cdc: bf00 nop 8005cde: 370c adds r7, #12 8005ce0: 46bd mov sp, r7 8005ce2: f85d 7b04 ldr.w r7, [sp], #4 8005ce6: 4770 bx lr 08005ce8 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005ce8: b580 push {r7, lr} 8005cea: b082 sub sp, #8 8005cec: af00 add r7, sp, #0 8005cee: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005cf0: 687b ldr r3, [r7, #4] 8005cf2: 2b00 cmp r3, #0 8005cf4: d101 bne.n 8005cfa { return HAL_ERROR; 8005cf6: 2301 movs r3, #1 8005cf8: e042 b.n 8005d80 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005cfa: 687b ldr r3, [r7, #4] 8005cfc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005d00: b2db uxtb r3, r3 8005d02: 2b00 cmp r3, #0 8005d04: d106 bne.n 8005d14 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005d06: 687b ldr r3, [r7, #4] 8005d08: 2200 movs r2, #0 8005d0a: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005d0e: 6878 ldr r0, [r7, #4] 8005d10: f7fb fad2 bl 80012b8 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005d14: 687b ldr r3, [r7, #4] 8005d16: 2224 movs r2, #36 @ 0x24 8005d18: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005d1c: 687b ldr r3, [r7, #4] 8005d1e: 681b ldr r3, [r3, #0] 8005d20: 68da ldr r2, [r3, #12] 8005d22: 687b ldr r3, [r7, #4] 8005d24: 681b ldr r3, [r3, #0] 8005d26: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005d2a: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005d2c: 6878 ldr r0, [r7, #4] 8005d2e: f000 f82b bl 8005d88 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005d32: 687b ldr r3, [r7, #4] 8005d34: 681b ldr r3, [r3, #0] 8005d36: 691a ldr r2, [r3, #16] 8005d38: 687b ldr r3, [r7, #4] 8005d3a: 681b ldr r3, [r3, #0] 8005d3c: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005d40: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005d42: 687b ldr r3, [r7, #4] 8005d44: 681b ldr r3, [r3, #0] 8005d46: 695a ldr r2, [r3, #20] 8005d48: 687b ldr r3, [r7, #4] 8005d4a: 681b ldr r3, [r3, #0] 8005d4c: f022 022a bic.w r2, r2, #42 @ 0x2a 8005d50: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005d52: 687b ldr r3, [r7, #4] 8005d54: 681b ldr r3, [r3, #0] 8005d56: 68da ldr r2, [r3, #12] 8005d58: 687b ldr r3, [r7, #4] 8005d5a: 681b ldr r3, [r3, #0] 8005d5c: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005d60: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005d62: 687b ldr r3, [r7, #4] 8005d64: 2200 movs r2, #0 8005d66: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005d68: 687b ldr r3, [r7, #4] 8005d6a: 2220 movs r2, #32 8005d6c: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005d70: 687b ldr r3, [r7, #4] 8005d72: 2220 movs r2, #32 8005d74: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005d78: 687b ldr r3, [r7, #4] 8005d7a: 2200 movs r2, #0 8005d7c: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005d7e: 2300 movs r3, #0 } 8005d80: 4618 mov r0, r3 8005d82: 3708 adds r7, #8 8005d84: 46bd mov sp, r7 8005d86: bd80 pop {r7, pc} 08005d88 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8005d88: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8005d8c: b0c0 sub sp, #256 @ 0x100 8005d8e: af00 add r7, sp, #0 8005d90: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005d94: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d98: 681b ldr r3, [r3, #0] 8005d9a: 691b ldr r3, [r3, #16] 8005d9c: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8005da0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005da4: 68d9 ldr r1, [r3, #12] 8005da6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005daa: 681a ldr r2, [r3, #0] 8005dac: ea40 0301 orr.w r3, r0, r1 8005db0: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8005db2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005db6: 689a ldr r2, [r3, #8] 8005db8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dbc: 691b ldr r3, [r3, #16] 8005dbe: 431a orrs r2, r3 8005dc0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dc4: 695b ldr r3, [r3, #20] 8005dc6: 431a orrs r2, r3 8005dc8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dcc: 69db ldr r3, [r3, #28] 8005dce: 4313 orrs r3, r2 8005dd0: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8005dd4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dd8: 681b ldr r3, [r3, #0] 8005dda: 68db ldr r3, [r3, #12] 8005ddc: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8005de0: f021 010c bic.w r1, r1, #12 8005de4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005de8: 681a ldr r2, [r3, #0] 8005dea: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8005dee: 430b orrs r3, r1 8005df0: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8005df2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005df6: 681b ldr r3, [r3, #0] 8005df8: 695b ldr r3, [r3, #20] 8005dfa: f423 7040 bic.w r0, r3, #768 @ 0x300 8005dfe: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e02: 6999 ldr r1, [r3, #24] 8005e04: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e08: 681a ldr r2, [r3, #0] 8005e0a: ea40 0301 orr.w r3, r0, r1 8005e0e: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8005e10: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e14: 681a ldr r2, [r3, #0] 8005e16: 4b8f ldr r3, [pc, #572] @ (8006054 ) 8005e18: 429a cmp r2, r3 8005e1a: d005 beq.n 8005e28 8005e1c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e20: 681a ldr r2, [r3, #0] 8005e22: 4b8d ldr r3, [pc, #564] @ (8006058 ) 8005e24: 429a cmp r2, r3 8005e26: d104 bne.n 8005e32 { pclk = HAL_RCC_GetPCLK2Freq(); 8005e28: f7ff f82c bl 8004e84 8005e2c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8005e30: e003 b.n 8005e3a pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8005e32: f7ff f813 bl 8004e5c 8005e36: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8005e3a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e3e: 69db ldr r3, [r3, #28] 8005e40: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8005e44: f040 810c bne.w 8006060 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8005e48: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005e4c: 2200 movs r2, #0 8005e4e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8005e52: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8005e56: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8005e5a: 4622 mov r2, r4 8005e5c: 462b mov r3, r5 8005e5e: 1891 adds r1, r2, r2 8005e60: 65b9 str r1, [r7, #88] @ 0x58 8005e62: 415b adcs r3, r3 8005e64: 65fb str r3, [r7, #92] @ 0x5c 8005e66: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8005e6a: 4621 mov r1, r4 8005e6c: eb12 0801 adds.w r8, r2, r1 8005e70: 4629 mov r1, r5 8005e72: eb43 0901 adc.w r9, r3, r1 8005e76: f04f 0200 mov.w r2, #0 8005e7a: f04f 0300 mov.w r3, #0 8005e7e: ea4f 03c9 mov.w r3, r9, lsl #3 8005e82: ea43 7358 orr.w r3, r3, r8, lsr #29 8005e86: ea4f 02c8 mov.w r2, r8, lsl #3 8005e8a: 4690 mov r8, r2 8005e8c: 4699 mov r9, r3 8005e8e: 4623 mov r3, r4 8005e90: eb18 0303 adds.w r3, r8, r3 8005e94: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8005e98: 462b mov r3, r5 8005e9a: eb49 0303 adc.w r3, r9, r3 8005e9e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8005ea2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005ea6: 685b ldr r3, [r3, #4] 8005ea8: 2200 movs r2, #0 8005eaa: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8005eae: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8005eb2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8005eb6: 460b mov r3, r1 8005eb8: 18db adds r3, r3, r3 8005eba: 653b str r3, [r7, #80] @ 0x50 8005ebc: 4613 mov r3, r2 8005ebe: eb42 0303 adc.w r3, r2, r3 8005ec2: 657b str r3, [r7, #84] @ 0x54 8005ec4: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8005ec8: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8005ecc: f7fa f990 bl 80001f0 <__aeabi_uldivmod> 8005ed0: 4602 mov r2, r0 8005ed2: 460b mov r3, r1 8005ed4: 4b61 ldr r3, [pc, #388] @ (800605c ) 8005ed6: fba3 2302 umull r2, r3, r3, r2 8005eda: 095b lsrs r3, r3, #5 8005edc: 011c lsls r4, r3, #4 8005ede: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005ee2: 2200 movs r2, #0 8005ee4: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005ee8: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8005eec: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8005ef0: 4642 mov r2, r8 8005ef2: 464b mov r3, r9 8005ef4: 1891 adds r1, r2, r2 8005ef6: 64b9 str r1, [r7, #72] @ 0x48 8005ef8: 415b adcs r3, r3 8005efa: 64fb str r3, [r7, #76] @ 0x4c 8005efc: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8005f00: 4641 mov r1, r8 8005f02: eb12 0a01 adds.w sl, r2, r1 8005f06: 4649 mov r1, r9 8005f08: eb43 0b01 adc.w fp, r3, r1 8005f0c: f04f 0200 mov.w r2, #0 8005f10: f04f 0300 mov.w r3, #0 8005f14: ea4f 03cb mov.w r3, fp, lsl #3 8005f18: ea43 735a orr.w r3, r3, sl, lsr #29 8005f1c: ea4f 02ca mov.w r2, sl, lsl #3 8005f20: 4692 mov sl, r2 8005f22: 469b mov fp, r3 8005f24: 4643 mov r3, r8 8005f26: eb1a 0303 adds.w r3, sl, r3 8005f2a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8005f2e: 464b mov r3, r9 8005f30: eb4b 0303 adc.w r3, fp, r3 8005f34: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8005f38: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005f3c: 685b ldr r3, [r3, #4] 8005f3e: 2200 movs r2, #0 8005f40: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005f44: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8005f48: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8005f4c: 460b mov r3, r1 8005f4e: 18db adds r3, r3, r3 8005f50: 643b str r3, [r7, #64] @ 0x40 8005f52: 4613 mov r3, r2 8005f54: eb42 0303 adc.w r3, r2, r3 8005f58: 647b str r3, [r7, #68] @ 0x44 8005f5a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8005f5e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8005f62: f7fa f945 bl 80001f0 <__aeabi_uldivmod> 8005f66: 4602 mov r2, r0 8005f68: 460b mov r3, r1 8005f6a: 4611 mov r1, r2 8005f6c: 4b3b ldr r3, [pc, #236] @ (800605c ) 8005f6e: fba3 2301 umull r2, r3, r3, r1 8005f72: 095b lsrs r3, r3, #5 8005f74: 2264 movs r2, #100 @ 0x64 8005f76: fb02 f303 mul.w r3, r2, r3 8005f7a: 1acb subs r3, r1, r3 8005f7c: 00db lsls r3, r3, #3 8005f7e: f103 0232 add.w r2, r3, #50 @ 0x32 8005f82: 4b36 ldr r3, [pc, #216] @ (800605c ) 8005f84: fba3 2302 umull r2, r3, r3, r2 8005f88: 095b lsrs r3, r3, #5 8005f8a: 005b lsls r3, r3, #1 8005f8c: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8005f90: 441c add r4, r3 8005f92: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005f96: 2200 movs r2, #0 8005f98: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005f9c: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8005fa0: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8005fa4: 4642 mov r2, r8 8005fa6: 464b mov r3, r9 8005fa8: 1891 adds r1, r2, r2 8005faa: 63b9 str r1, [r7, #56] @ 0x38 8005fac: 415b adcs r3, r3 8005fae: 63fb str r3, [r7, #60] @ 0x3c 8005fb0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8005fb4: 4641 mov r1, r8 8005fb6: 1851 adds r1, r2, r1 8005fb8: 6339 str r1, [r7, #48] @ 0x30 8005fba: 4649 mov r1, r9 8005fbc: 414b adcs r3, r1 8005fbe: 637b str r3, [r7, #52] @ 0x34 8005fc0: f04f 0200 mov.w r2, #0 8005fc4: f04f 0300 mov.w r3, #0 8005fc8: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8005fcc: 4659 mov r1, fp 8005fce: 00cb lsls r3, r1, #3 8005fd0: 4651 mov r1, sl 8005fd2: ea43 7351 orr.w r3, r3, r1, lsr #29 8005fd6: 4651 mov r1, sl 8005fd8: 00ca lsls r2, r1, #3 8005fda: 4610 mov r0, r2 8005fdc: 4619 mov r1, r3 8005fde: 4603 mov r3, r0 8005fe0: 4642 mov r2, r8 8005fe2: 189b adds r3, r3, r2 8005fe4: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8005fe8: 464b mov r3, r9 8005fea: 460a mov r2, r1 8005fec: eb42 0303 adc.w r3, r2, r3 8005ff0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005ff4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005ff8: 685b ldr r3, [r3, #4] 8005ffa: 2200 movs r2, #0 8005ffc: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8006000: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8006004: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8006008: 460b mov r3, r1 800600a: 18db adds r3, r3, r3 800600c: 62bb str r3, [r7, #40] @ 0x28 800600e: 4613 mov r3, r2 8006010: eb42 0303 adc.w r3, r2, r3 8006014: 62fb str r3, [r7, #44] @ 0x2c 8006016: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 800601a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 800601e: f7fa f8e7 bl 80001f0 <__aeabi_uldivmod> 8006022: 4602 mov r2, r0 8006024: 460b mov r3, r1 8006026: 4b0d ldr r3, [pc, #52] @ (800605c ) 8006028: fba3 1302 umull r1, r3, r3, r2 800602c: 095b lsrs r3, r3, #5 800602e: 2164 movs r1, #100 @ 0x64 8006030: fb01 f303 mul.w r3, r1, r3 8006034: 1ad3 subs r3, r2, r3 8006036: 00db lsls r3, r3, #3 8006038: 3332 adds r3, #50 @ 0x32 800603a: 4a08 ldr r2, [pc, #32] @ (800605c ) 800603c: fba2 2303 umull r2, r3, r2, r3 8006040: 095b lsrs r3, r3, #5 8006042: f003 0207 and.w r2, r3, #7 8006046: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800604a: 681b ldr r3, [r3, #0] 800604c: 4422 add r2, r4 800604e: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006050: e106 b.n 8006260 8006052: bf00 nop 8006054: 40011000 .word 0x40011000 8006058: 40011400 .word 0x40011400 800605c: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006060: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006064: 2200 movs r2, #0 8006066: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 800606a: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 800606e: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 8006072: 4642 mov r2, r8 8006074: 464b mov r3, r9 8006076: 1891 adds r1, r2, r2 8006078: 6239 str r1, [r7, #32] 800607a: 415b adcs r3, r3 800607c: 627b str r3, [r7, #36] @ 0x24 800607e: e9d7 2308 ldrd r2, r3, [r7, #32] 8006082: 4641 mov r1, r8 8006084: 1854 adds r4, r2, r1 8006086: 4649 mov r1, r9 8006088: eb43 0501 adc.w r5, r3, r1 800608c: f04f 0200 mov.w r2, #0 8006090: f04f 0300 mov.w r3, #0 8006094: 00eb lsls r3, r5, #3 8006096: ea43 7354 orr.w r3, r3, r4, lsr #29 800609a: 00e2 lsls r2, r4, #3 800609c: 4614 mov r4, r2 800609e: 461d mov r5, r3 80060a0: 4643 mov r3, r8 80060a2: 18e3 adds r3, r4, r3 80060a4: f8c7 3098 str.w r3, [r7, #152] @ 0x98 80060a8: 464b mov r3, r9 80060aa: eb45 0303 adc.w r3, r5, r3 80060ae: f8c7 309c str.w r3, [r7, #156] @ 0x9c 80060b2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80060b6: 685b ldr r3, [r3, #4] 80060b8: 2200 movs r2, #0 80060ba: f8c7 3090 str.w r3, [r7, #144] @ 0x90 80060be: f8c7 2094 str.w r2, [r7, #148] @ 0x94 80060c2: f04f 0200 mov.w r2, #0 80060c6: f04f 0300 mov.w r3, #0 80060ca: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 80060ce: 4629 mov r1, r5 80060d0: 008b lsls r3, r1, #2 80060d2: 4621 mov r1, r4 80060d4: ea43 7391 orr.w r3, r3, r1, lsr #30 80060d8: 4621 mov r1, r4 80060da: 008a lsls r2, r1, #2 80060dc: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 80060e0: f7fa f886 bl 80001f0 <__aeabi_uldivmod> 80060e4: 4602 mov r2, r0 80060e6: 460b mov r3, r1 80060e8: 4b60 ldr r3, [pc, #384] @ (800626c ) 80060ea: fba3 2302 umull r2, r3, r3, r2 80060ee: 095b lsrs r3, r3, #5 80060f0: 011c lsls r4, r3, #4 80060f2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80060f6: 2200 movs r2, #0 80060f8: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80060fc: f8c7 208c str.w r2, [r7, #140] @ 0x8c 8006100: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 8006104: 4642 mov r2, r8 8006106: 464b mov r3, r9 8006108: 1891 adds r1, r2, r2 800610a: 61b9 str r1, [r7, #24] 800610c: 415b adcs r3, r3 800610e: 61fb str r3, [r7, #28] 8006110: e9d7 2306 ldrd r2, r3, [r7, #24] 8006114: 4641 mov r1, r8 8006116: 1851 adds r1, r2, r1 8006118: 6139 str r1, [r7, #16] 800611a: 4649 mov r1, r9 800611c: 414b adcs r3, r1 800611e: 617b str r3, [r7, #20] 8006120: f04f 0200 mov.w r2, #0 8006124: f04f 0300 mov.w r3, #0 8006128: e9d7 ab04 ldrd sl, fp, [r7, #16] 800612c: 4659 mov r1, fp 800612e: 00cb lsls r3, r1, #3 8006130: 4651 mov r1, sl 8006132: ea43 7351 orr.w r3, r3, r1, lsr #29 8006136: 4651 mov r1, sl 8006138: 00ca lsls r2, r1, #3 800613a: 4610 mov r0, r2 800613c: 4619 mov r1, r3 800613e: 4603 mov r3, r0 8006140: 4642 mov r2, r8 8006142: 189b adds r3, r3, r2 8006144: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006148: 464b mov r3, r9 800614a: 460a mov r2, r1 800614c: eb42 0303 adc.w r3, r2, r3 8006150: f8c7 3084 str.w r3, [r7, #132] @ 0x84 8006154: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006158: 685b ldr r3, [r3, #4] 800615a: 2200 movs r2, #0 800615c: 67bb str r3, [r7, #120] @ 0x78 800615e: 67fa str r2, [r7, #124] @ 0x7c 8006160: f04f 0200 mov.w r2, #0 8006164: f04f 0300 mov.w r3, #0 8006168: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 800616c: 4649 mov r1, r9 800616e: 008b lsls r3, r1, #2 8006170: 4641 mov r1, r8 8006172: ea43 7391 orr.w r3, r3, r1, lsr #30 8006176: 4641 mov r1, r8 8006178: 008a lsls r2, r1, #2 800617a: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 800617e: f7fa f837 bl 80001f0 <__aeabi_uldivmod> 8006182: 4602 mov r2, r0 8006184: 460b mov r3, r1 8006186: 4611 mov r1, r2 8006188: 4b38 ldr r3, [pc, #224] @ (800626c ) 800618a: fba3 2301 umull r2, r3, r3, r1 800618e: 095b lsrs r3, r3, #5 8006190: 2264 movs r2, #100 @ 0x64 8006192: fb02 f303 mul.w r3, r2, r3 8006196: 1acb subs r3, r1, r3 8006198: 011b lsls r3, r3, #4 800619a: 3332 adds r3, #50 @ 0x32 800619c: 4a33 ldr r2, [pc, #204] @ (800626c ) 800619e: fba2 2303 umull r2, r3, r2, r3 80061a2: 095b lsrs r3, r3, #5 80061a4: f003 03f0 and.w r3, r3, #240 @ 0xf0 80061a8: 441c add r4, r3 80061aa: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80061ae: 2200 movs r2, #0 80061b0: 673b str r3, [r7, #112] @ 0x70 80061b2: 677a str r2, [r7, #116] @ 0x74 80061b4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 80061b8: 4642 mov r2, r8 80061ba: 464b mov r3, r9 80061bc: 1891 adds r1, r2, r2 80061be: 60b9 str r1, [r7, #8] 80061c0: 415b adcs r3, r3 80061c2: 60fb str r3, [r7, #12] 80061c4: e9d7 2302 ldrd r2, r3, [r7, #8] 80061c8: 4641 mov r1, r8 80061ca: 1851 adds r1, r2, r1 80061cc: 6039 str r1, [r7, #0] 80061ce: 4649 mov r1, r9 80061d0: 414b adcs r3, r1 80061d2: 607b str r3, [r7, #4] 80061d4: f04f 0200 mov.w r2, #0 80061d8: f04f 0300 mov.w r3, #0 80061dc: e9d7 ab00 ldrd sl, fp, [r7] 80061e0: 4659 mov r1, fp 80061e2: 00cb lsls r3, r1, #3 80061e4: 4651 mov r1, sl 80061e6: ea43 7351 orr.w r3, r3, r1, lsr #29 80061ea: 4651 mov r1, sl 80061ec: 00ca lsls r2, r1, #3 80061ee: 4610 mov r0, r2 80061f0: 4619 mov r1, r3 80061f2: 4603 mov r3, r0 80061f4: 4642 mov r2, r8 80061f6: 189b adds r3, r3, r2 80061f8: 66bb str r3, [r7, #104] @ 0x68 80061fa: 464b mov r3, r9 80061fc: 460a mov r2, r1 80061fe: eb42 0303 adc.w r3, r2, r3 8006202: 66fb str r3, [r7, #108] @ 0x6c 8006204: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006208: 685b ldr r3, [r3, #4] 800620a: 2200 movs r2, #0 800620c: 663b str r3, [r7, #96] @ 0x60 800620e: 667a str r2, [r7, #100] @ 0x64 8006210: f04f 0200 mov.w r2, #0 8006214: f04f 0300 mov.w r3, #0 8006218: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 800621c: 4649 mov r1, r9 800621e: 008b lsls r3, r1, #2 8006220: 4641 mov r1, r8 8006222: ea43 7391 orr.w r3, r3, r1, lsr #30 8006226: 4641 mov r1, r8 8006228: 008a lsls r2, r1, #2 800622a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 800622e: f7f9 ffdf bl 80001f0 <__aeabi_uldivmod> 8006232: 4602 mov r2, r0 8006234: 460b mov r3, r1 8006236: 4b0d ldr r3, [pc, #52] @ (800626c ) 8006238: fba3 1302 umull r1, r3, r3, r2 800623c: 095b lsrs r3, r3, #5 800623e: 2164 movs r1, #100 @ 0x64 8006240: fb01 f303 mul.w r3, r1, r3 8006244: 1ad3 subs r3, r2, r3 8006246: 011b lsls r3, r3, #4 8006248: 3332 adds r3, #50 @ 0x32 800624a: 4a08 ldr r2, [pc, #32] @ (800626c ) 800624c: fba2 2303 umull r2, r3, r2, r3 8006250: 095b lsrs r3, r3, #5 8006252: f003 020f and.w r2, r3, #15 8006256: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800625a: 681b ldr r3, [r3, #0] 800625c: 4422 add r2, r4 800625e: 609a str r2, [r3, #8] } 8006260: bf00 nop 8006262: f507 7780 add.w r7, r7, #256 @ 0x100 8006266: 46bd mov sp, r7 8006268: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800626c: 51eb851f .word 0x51eb851f 08006270 : * @param Device Pointer to SDRAM device instance * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { 8006270: b480 push {r7} 8006272: b083 sub sp, #12 8006274: af00 add r7, sp, #0 8006276: 6078 str r0, [r7, #4] 8006278: 6039 str r1, [r7, #0] assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); /* Set SDRAM bank configuration parameters */ if (Init->SDBank == FMC_SDRAM_BANK1) 800627a: 683b ldr r3, [r7, #0] 800627c: 681b ldr r3, [r3, #0] 800627e: 2b00 cmp r3, #0 8006280: d123 bne.n 80062ca { MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], 8006282: 687b ldr r3, [r7, #4] 8006284: 681b ldr r3, [r3, #0] 8006286: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 800628a: f023 037f bic.w r3, r3, #127 @ 0x7f 800628e: 683a ldr r2, [r7, #0] 8006290: 6851 ldr r1, [r2, #4] 8006292: 683a ldr r2, [r7, #0] 8006294: 6892 ldr r2, [r2, #8] 8006296: 4311 orrs r1, r2 8006298: 683a ldr r2, [r7, #0] 800629a: 68d2 ldr r2, [r2, #12] 800629c: 4311 orrs r1, r2 800629e: 683a ldr r2, [r7, #0] 80062a0: 6912 ldr r2, [r2, #16] 80062a2: 4311 orrs r1, r2 80062a4: 683a ldr r2, [r7, #0] 80062a6: 6952 ldr r2, [r2, #20] 80062a8: 4311 orrs r1, r2 80062aa: 683a ldr r2, [r7, #0] 80062ac: 6992 ldr r2, [r2, #24] 80062ae: 4311 orrs r1, r2 80062b0: 683a ldr r2, [r7, #0] 80062b2: 69d2 ldr r2, [r2, #28] 80062b4: 4311 orrs r1, r2 80062b6: 683a ldr r2, [r7, #0] 80062b8: 6a12 ldr r2, [r2, #32] 80062ba: 4311 orrs r1, r2 80062bc: 683a ldr r2, [r7, #0] 80062be: 6a52 ldr r2, [r2, #36] @ 0x24 80062c0: 430a orrs r2, r1 80062c2: 431a orrs r2, r3 80062c4: 687b ldr r3, [r7, #4] 80062c6: 601a str r2, [r3, #0] 80062c8: e028 b.n 800631c Init->ReadBurst | Init->ReadPipeDelay)); } else /* FMC_Bank2_SDRAM */ { MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], 80062ca: 687b ldr r3, [r7, #4] 80062cc: 681b ldr r3, [r3, #0] 80062ce: f423 42f8 bic.w r2, r3, #31744 @ 0x7c00 80062d2: 683b ldr r3, [r7, #0] 80062d4: 69d9 ldr r1, [r3, #28] 80062d6: 683b ldr r3, [r7, #0] 80062d8: 6a1b ldr r3, [r3, #32] 80062da: 4319 orrs r1, r3 80062dc: 683b ldr r3, [r7, #0] 80062de: 6a5b ldr r3, [r3, #36] @ 0x24 80062e0: 430b orrs r3, r1 80062e2: 431a orrs r2, r3 80062e4: 687b ldr r3, [r7, #4] 80062e6: 601a str r2, [r3, #0] FMC_SDCR1_RPIPE, (Init->SDClockPeriod | Init->ReadBurst | Init->ReadPipeDelay)); MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], 80062e8: 687b ldr r3, [r7, #4] 80062ea: 685b ldr r3, [r3, #4] 80062ec: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 80062f0: f023 037f bic.w r3, r3, #127 @ 0x7f 80062f4: 683a ldr r2, [r7, #0] 80062f6: 6851 ldr r1, [r2, #4] 80062f8: 683a ldr r2, [r7, #0] 80062fa: 6892 ldr r2, [r2, #8] 80062fc: 4311 orrs r1, r2 80062fe: 683a ldr r2, [r7, #0] 8006300: 68d2 ldr r2, [r2, #12] 8006302: 4311 orrs r1, r2 8006304: 683a ldr r2, [r7, #0] 8006306: 6912 ldr r2, [r2, #16] 8006308: 4311 orrs r1, r2 800630a: 683a ldr r2, [r7, #0] 800630c: 6952 ldr r2, [r2, #20] 800630e: 4311 orrs r1, r2 8006310: 683a ldr r2, [r7, #0] 8006312: 6992 ldr r2, [r2, #24] 8006314: 430a orrs r2, r1 8006316: 431a orrs r2, r3 8006318: 687b ldr r3, [r7, #4] 800631a: 605a str r2, [r3, #4] Init->InternalBankNumber | Init->CASLatency | Init->WriteProtection)); } return HAL_OK; 800631c: 2300 movs r3, #0 } 800631e: 4618 mov r0, r3 8006320: 370c adds r7, #12 8006322: 46bd mov sp, r7 8006324: f85d 7b04 ldr.w r7, [sp], #4 8006328: 4770 bx lr 0800632a : * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { 800632a: b480 push {r7} 800632c: b085 sub sp, #20 800632e: af00 add r7, sp, #0 8006330: 60f8 str r0, [r7, #12] 8006332: 60b9 str r1, [r7, #8] 8006334: 607a str r2, [r7, #4] assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Set SDRAM device timing parameters */ if (Bank == FMC_SDRAM_BANK1) 8006336: 687b ldr r3, [r7, #4] 8006338: 2b00 cmp r3, #0 800633a: d128 bne.n 800638e { MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], 800633c: 68fb ldr r3, [r7, #12] 800633e: 689b ldr r3, [r3, #8] 8006340: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000 8006344: 68bb ldr r3, [r7, #8] 8006346: 681b ldr r3, [r3, #0] 8006348: 1e59 subs r1, r3, #1 800634a: 68bb ldr r3, [r7, #8] 800634c: 685b ldr r3, [r3, #4] 800634e: 3b01 subs r3, #1 8006350: 011b lsls r3, r3, #4 8006352: 4319 orrs r1, r3 8006354: 68bb ldr r3, [r7, #8] 8006356: 689b ldr r3, [r3, #8] 8006358: 3b01 subs r3, #1 800635a: 021b lsls r3, r3, #8 800635c: 4319 orrs r1, r3 800635e: 68bb ldr r3, [r7, #8] 8006360: 68db ldr r3, [r3, #12] 8006362: 3b01 subs r3, #1 8006364: 031b lsls r3, r3, #12 8006366: 4319 orrs r1, r3 8006368: 68bb ldr r3, [r7, #8] 800636a: 691b ldr r3, [r3, #16] 800636c: 3b01 subs r3, #1 800636e: 041b lsls r3, r3, #16 8006370: 4319 orrs r1, r3 8006372: 68bb ldr r3, [r7, #8] 8006374: 695b ldr r3, [r3, #20] 8006376: 3b01 subs r3, #1 8006378: 051b lsls r3, r3, #20 800637a: 4319 orrs r1, r3 800637c: 68bb ldr r3, [r7, #8] 800637e: 699b ldr r3, [r3, #24] 8006380: 3b01 subs r3, #1 8006382: 061b lsls r3, r3, #24 8006384: 430b orrs r3, r1 8006386: 431a orrs r2, r3 8006388: 68fb ldr r3, [r7, #12] 800638a: 609a str r2, [r3, #8] 800638c: e02f b.n 80063ee (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } else /* FMC_Bank2_SDRAM */ { MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], 800638e: 68fb ldr r3, [r7, #12] 8006390: 689b ldr r3, [r3, #8] 8006392: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 8006396: f423 4370 bic.w r3, r3, #61440 @ 0xf000 800639a: 68ba ldr r2, [r7, #8] 800639c: 68d2 ldr r2, [r2, #12] 800639e: 3a01 subs r2, #1 80063a0: 0311 lsls r1, r2, #12 80063a2: 68ba ldr r2, [r7, #8] 80063a4: 6952 ldr r2, [r2, #20] 80063a6: 3a01 subs r2, #1 80063a8: 0512 lsls r2, r2, #20 80063aa: 430a orrs r2, r1 80063ac: 431a orrs r2, r3 80063ae: 68fb ldr r3, [r7, #12] 80063b0: 609a str r2, [r3, #8] FMC_SDTR1_TRC | FMC_SDTR1_TRP, (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], 80063b2: 68fb ldr r3, [r7, #12] 80063b4: 68db ldr r3, [r3, #12] 80063b6: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000 80063ba: 68bb ldr r3, [r7, #8] 80063bc: 681b ldr r3, [r3, #0] 80063be: 1e59 subs r1, r3, #1 80063c0: 68bb ldr r3, [r7, #8] 80063c2: 685b ldr r3, [r3, #4] 80063c4: 3b01 subs r3, #1 80063c6: 011b lsls r3, r3, #4 80063c8: 4319 orrs r1, r3 80063ca: 68bb ldr r3, [r7, #8] 80063cc: 689b ldr r3, [r3, #8] 80063ce: 3b01 subs r3, #1 80063d0: 021b lsls r3, r3, #8 80063d2: 4319 orrs r1, r3 80063d4: 68bb ldr r3, [r7, #8] 80063d6: 691b ldr r3, [r3, #16] 80063d8: 3b01 subs r3, #1 80063da: 041b lsls r3, r3, #16 80063dc: 4319 orrs r1, r3 80063de: 68bb ldr r3, [r7, #8] 80063e0: 699b ldr r3, [r3, #24] 80063e2: 3b01 subs r3, #1 80063e4: 061b lsls r3, r3, #24 80063e6: 430b orrs r3, r1 80063e8: 431a orrs r2, r3 80063ea: 68fb ldr r3, [r7, #12] 80063ec: 60da str r2, [r3, #12] (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } return HAL_OK; 80063ee: 2300 movs r3, #0 } 80063f0: 4618 mov r0, r3 80063f2: 3714 adds r7, #20 80063f4: 46bd mov sp, r7 80063f6: f85d 7b04 ldr.w r7, [sp], #4 80063fa: 4770 bx lr 080063fc : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80063fc: b480 push {r7} 80063fe: b083 sub sp, #12 8006400: af00 add r7, sp, #0 8006402: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 8006404: 687b ldr r3, [r7, #4] 8006406: 689b ldr r3, [r3, #8] 8006408: f043 0201 orr.w r2, r3, #1 800640c: 687b ldr r3, [r7, #4] 800640e: 609a str r2, [r3, #8] return HAL_OK; 8006410: 2300 movs r3, #0 } 8006412: 4618 mov r0, r3 8006414: 370c adds r7, #12 8006416: 46bd mov sp, r7 8006418: f85d 7b04 ldr.w r7, [sp], #4 800641c: 4770 bx lr 0800641e : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 800641e: b480 push {r7} 8006420: b083 sub sp, #12 8006422: af00 add r7, sp, #0 8006424: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 8006426: 687b ldr r3, [r7, #4] 8006428: 689b ldr r3, [r3, #8] 800642a: f023 0201 bic.w r2, r3, #1 800642e: 687b ldr r3, [r7, #4] 8006430: 609a str r2, [r3, #8] return HAL_OK; 8006432: 2300 movs r3, #0 } 8006434: 4618 mov r0, r3 8006436: 370c adds r7, #12 8006438: 46bd mov sp, r7 800643a: f85d 7b04 ldr.w r7, [sp], #4 800643e: 4770 bx lr 08006440 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 8006440: b480 push {r7} 8006442: b085 sub sp, #20 8006444: af00 add r7, sp, #0 8006446: 6078 str r0, [r7, #4] 8006448: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 800644a: 2300 movs r3, #0 800644c: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 800644e: 68fb ldr r3, [r7, #12] 8006450: 3301 adds r3, #1 8006452: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006454: 68fb ldr r3, [r7, #12] 8006456: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800645a: d901 bls.n 8006460 { return HAL_TIMEOUT; 800645c: 2303 movs r3, #3 800645e: e01b b.n 8006498 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006460: 687b ldr r3, [r7, #4] 8006462: 691b ldr r3, [r3, #16] 8006464: 2b00 cmp r3, #0 8006466: daf2 bge.n 800644e /* Flush TX Fifo */ count = 0U; 8006468: 2300 movs r3, #0 800646a: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 800646c: 683b ldr r3, [r7, #0] 800646e: 019b lsls r3, r3, #6 8006470: f043 0220 orr.w r2, r3, #32 8006474: 687b ldr r3, [r7, #4] 8006476: 611a str r2, [r3, #16] do { count++; 8006478: 68fb ldr r3, [r7, #12] 800647a: 3301 adds r3, #1 800647c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800647e: 68fb ldr r3, [r7, #12] 8006480: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006484: d901 bls.n 800648a { return HAL_TIMEOUT; 8006486: 2303 movs r3, #3 8006488: e006 b.n 8006498 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 800648a: 687b ldr r3, [r7, #4] 800648c: 691b ldr r3, [r3, #16] 800648e: f003 0320 and.w r3, r3, #32 8006492: 2b20 cmp r3, #32 8006494: d0f0 beq.n 8006478 return HAL_OK; 8006496: 2300 movs r3, #0 } 8006498: 4618 mov r0, r3 800649a: 3714 adds r7, #20 800649c: 46bd mov sp, r7 800649e: f85d 7b04 ldr.w r7, [sp], #4 80064a2: 4770 bx lr 080064a4 : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 80064a4: b480 push {r7} 80064a6: b085 sub sp, #20 80064a8: af00 add r7, sp, #0 80064aa: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 80064ac: 2300 movs r3, #0 80064ae: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 80064b0: 68fb ldr r3, [r7, #12] 80064b2: 3301 adds r3, #1 80064b4: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80064b6: 68fb ldr r3, [r7, #12] 80064b8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80064bc: d901 bls.n 80064c2 { return HAL_TIMEOUT; 80064be: 2303 movs r3, #3 80064c0: e018 b.n 80064f4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 80064c2: 687b ldr r3, [r7, #4] 80064c4: 691b ldr r3, [r3, #16] 80064c6: 2b00 cmp r3, #0 80064c8: daf2 bge.n 80064b0 /* Flush RX Fifo */ count = 0U; 80064ca: 2300 movs r3, #0 80064cc: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 80064ce: 687b ldr r3, [r7, #4] 80064d0: 2210 movs r2, #16 80064d2: 611a str r2, [r3, #16] do { count++; 80064d4: 68fb ldr r3, [r7, #12] 80064d6: 3301 adds r3, #1 80064d8: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 80064da: 68fb ldr r3, [r7, #12] 80064dc: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 80064e0: d901 bls.n 80064e6 { return HAL_TIMEOUT; 80064e2: 2303 movs r3, #3 80064e4: e006 b.n 80064f4 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 80064e6: 687b ldr r3, [r7, #4] 80064e8: 691b ldr r3, [r3, #16] 80064ea: f003 0310 and.w r3, r3, #16 80064ee: 2b10 cmp r3, #16 80064f0: d0f0 beq.n 80064d4 return HAL_OK; 80064f2: 2300 movs r3, #0 } 80064f4: 4618 mov r0, r3 80064f6: 3714 adds r7, #20 80064f8: 46bd mov sp, r7 80064fa: f85d 7b04 ldr.w r7, [sp], #4 80064fe: 4770 bx lr 08006500 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 8006500: b480 push {r7} 8006502: b08b sub sp, #44 @ 0x2c 8006504: af00 add r7, sp, #0 8006506: 60f8 str r0, [r7, #12] 8006508: 60b9 str r1, [r7, #8] 800650a: 4613 mov r3, r2 800650c: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 800650e: 68fb ldr r3, [r7, #12] 8006510: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 8006512: 68bb ldr r3, [r7, #8] 8006514: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 8006516: 88fb ldrh r3, [r7, #6] 8006518: 089b lsrs r3, r3, #2 800651a: b29b uxth r3, r3 800651c: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 800651e: 88fb ldrh r3, [r7, #6] 8006520: f003 0303 and.w r3, r3, #3 8006524: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 8006526: 2300 movs r3, #0 8006528: 623b str r3, [r7, #32] 800652a: e014 b.n 8006556 { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 800652c: 69bb ldr r3, [r7, #24] 800652e: f503 5380 add.w r3, r3, #4096 @ 0x1000 8006532: 681a ldr r2, [r3, #0] 8006534: 6a7b ldr r3, [r7, #36] @ 0x24 8006536: 601a str r2, [r3, #0] pDest++; 8006538: 6a7b ldr r3, [r7, #36] @ 0x24 800653a: 3301 adds r3, #1 800653c: 627b str r3, [r7, #36] @ 0x24 pDest++; 800653e: 6a7b ldr r3, [r7, #36] @ 0x24 8006540: 3301 adds r3, #1 8006542: 627b str r3, [r7, #36] @ 0x24 pDest++; 8006544: 6a7b ldr r3, [r7, #36] @ 0x24 8006546: 3301 adds r3, #1 8006548: 627b str r3, [r7, #36] @ 0x24 pDest++; 800654a: 6a7b ldr r3, [r7, #36] @ 0x24 800654c: 3301 adds r3, #1 800654e: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8006550: 6a3b ldr r3, [r7, #32] 8006552: 3301 adds r3, #1 8006554: 623b str r3, [r7, #32] 8006556: 6a3a ldr r2, [r7, #32] 8006558: 697b ldr r3, [r7, #20] 800655a: 429a cmp r2, r3 800655c: d3e6 bcc.n 800652c } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 800655e: 8bfb ldrh r3, [r7, #30] 8006560: 2b00 cmp r3, #0 8006562: d01e beq.n 80065a2 { i = 0U; 8006564: 2300 movs r3, #0 8006566: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8006568: 69bb ldr r3, [r7, #24] 800656a: f503 5380 add.w r3, r3, #4096 @ 0x1000 800656e: 461a mov r2, r3 8006570: f107 0310 add.w r3, r7, #16 8006574: 6812 ldr r2, [r2, #0] 8006576: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8006578: 693a ldr r2, [r7, #16] 800657a: 6a3b ldr r3, [r7, #32] 800657c: b2db uxtb r3, r3 800657e: 00db lsls r3, r3, #3 8006580: fa22 f303 lsr.w r3, r2, r3 8006584: b2da uxtb r2, r3 8006586: 6a7b ldr r3, [r7, #36] @ 0x24 8006588: 701a strb r2, [r3, #0] i++; 800658a: 6a3b ldr r3, [r7, #32] 800658c: 3301 adds r3, #1 800658e: 623b str r3, [r7, #32] pDest++; 8006590: 6a7b ldr r3, [r7, #36] @ 0x24 8006592: 3301 adds r3, #1 8006594: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 8006596: 8bfb ldrh r3, [r7, #30] 8006598: 3b01 subs r3, #1 800659a: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 800659c: 8bfb ldrh r3, [r7, #30] 800659e: 2b00 cmp r3, #0 80065a0: d1ea bne.n 8006578 } return ((void *)pDest); 80065a2: 6a7b ldr r3, [r7, #36] @ 0x24 } 80065a4: 4618 mov r0, r3 80065a6: 372c adds r7, #44 @ 0x2c 80065a8: 46bd mov sp, r7 80065aa: f85d 7b04 ldr.w r7, [sp], #4 80065ae: 4770 bx lr 080065b0 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 80065b0: b480 push {r7} 80065b2: b085 sub sp, #20 80065b4: af00 add r7, sp, #0 80065b6: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 80065b8: 687b ldr r3, [r7, #4] 80065ba: 695b ldr r3, [r3, #20] 80065bc: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 80065be: 687b ldr r3, [r7, #4] 80065c0: 699b ldr r3, [r3, #24] 80065c2: 68fa ldr r2, [r7, #12] 80065c4: 4013 ands r3, r2 80065c6: 60fb str r3, [r7, #12] return tmpreg; 80065c8: 68fb ldr r3, [r7, #12] } 80065ca: 4618 mov r0, r3 80065cc: 3714 adds r7, #20 80065ce: 46bd mov sp, r7 80065d0: f85d 7b04 ldr.w r7, [sp], #4 80065d4: 4770 bx lr 080065d6 : * @param USBx Selected device * @param chnum Channel number * @retval USB Channel Interrupt status */ uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) { 80065d6: b480 push {r7} 80065d8: b085 sub sp, #20 80065da: af00 add r7, sp, #0 80065dc: 6078 str r0, [r7, #4] 80065de: 460b mov r3, r1 80065e0: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80065e2: 687b ldr r3, [r7, #4] 80065e4: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_HC(chnum)->HCINT; 80065e6: 78fb ldrb r3, [r7, #3] 80065e8: 015a lsls r2, r3, #5 80065ea: 68fb ldr r3, [r7, #12] 80065ec: 4413 add r3, r2 80065ee: f503 63a0 add.w r3, r3, #1280 @ 0x500 80065f2: 689b ldr r3, [r3, #8] 80065f4: 60bb str r3, [r7, #8] tmpreg &= USBx_HC(chnum)->HCINTMSK; 80065f6: 78fb ldrb r3, [r7, #3] 80065f8: 015a lsls r2, r3, #5 80065fa: 68fb ldr r3, [r7, #12] 80065fc: 4413 add r3, r2 80065fe: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006602: 68db ldr r3, [r3, #12] 8006604: 68ba ldr r2, [r7, #8] 8006606: 4013 ands r3, r2 8006608: 60bb str r3, [r7, #8] return tmpreg; 800660a: 68bb ldr r3, [r7, #8] } 800660c: 4618 mov r0, r3 800660e: 3714 adds r7, #20 8006610: 46bd mov sp, r7 8006612: f85d 7b04 ldr.w r7, [sp], #4 8006616: 4770 bx lr 08006618 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 8006618: b480 push {r7} 800661a: b083 sub sp, #12 800661c: af00 add r7, sp, #0 800661e: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 8006620: 687b ldr r3, [r7, #4] 8006622: 695b ldr r3, [r3, #20] 8006624: f003 0301 and.w r3, r3, #1 } 8006628: 4618 mov r0, r3 800662a: 370c adds r7, #12 800662c: 46bd mov sp, r7 800662e: f85d 7b04 ldr.w r7, [sp], #4 8006632: 4770 bx lr 08006634 : * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { 8006634: b480 push {r7} 8006636: b085 sub sp, #20 8006638: af00 add r7, sp, #0 800663a: 6078 str r0, [r7, #4] 800663c: 460b mov r3, r1 800663e: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8006640: 687b ldr r3, [r7, #4] 8006642: 60fb str r3, [r7, #12] USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); 8006644: 68fb ldr r3, [r7, #12] 8006646: f503 6380 add.w r3, r3, #1024 @ 0x400 800664a: 681b ldr r3, [r3, #0] 800664c: 68fa ldr r2, [r7, #12] 800664e: f502 6280 add.w r2, r2, #1024 @ 0x400 8006652: f023 0303 bic.w r3, r3, #3 8006656: 6013 str r3, [r2, #0] USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; 8006658: 68fb ldr r3, [r7, #12] 800665a: f503 6380 add.w r3, r3, #1024 @ 0x400 800665e: 681a ldr r2, [r3, #0] 8006660: 78fb ldrb r3, [r7, #3] 8006662: f003 0303 and.w r3, r3, #3 8006666: 68f9 ldr r1, [r7, #12] 8006668: f501 6180 add.w r1, r1, #1024 @ 0x400 800666c: 4313 orrs r3, r2 800666e: 600b str r3, [r1, #0] if (freq == HCFG_48_MHZ) 8006670: 78fb ldrb r3, [r7, #3] 8006672: 2b01 cmp r3, #1 8006674: d107 bne.n 8006686 { USBx_HOST->HFIR = HFIR_48_MHZ; 8006676: 68fb ldr r3, [r7, #12] 8006678: f503 6380 add.w r3, r3, #1024 @ 0x400 800667c: 461a mov r2, r3 800667e: f64b 3380 movw r3, #48000 @ 0xbb80 8006682: 6053 str r3, [r2, #4] 8006684: e00c b.n 80066a0 } else if (freq == HCFG_6_MHZ) 8006686: 78fb ldrb r3, [r7, #3] 8006688: 2b02 cmp r3, #2 800668a: d107 bne.n 800669c { USBx_HOST->HFIR = HFIR_6_MHZ; 800668c: 68fb ldr r3, [r7, #12] 800668e: f503 6380 add.w r3, r3, #1024 @ 0x400 8006692: 461a mov r2, r3 8006694: f241 7370 movw r3, #6000 @ 0x1770 8006698: 6053 str r3, [r2, #4] 800669a: e001 b.n 80066a0 } else { return HAL_ERROR; 800669c: 2301 movs r3, #1 800669e: e000 b.n 80066a2 } return HAL_OK; 80066a0: 2300 movs r3, #0 } 80066a2: 4618 mov r0, r3 80066a4: 3714 adds r7, #20 80066a6: 46bd mov sp, r7 80066a8: f85d 7b04 ldr.w r7, [sp], #4 80066ac: 4770 bx lr 080066ae : * @brief Read all host channel interrupts status * @param USBx Selected device * @retval HAL state */ uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 80066ae: b480 push {r7} 80066b0: b085 sub sp, #20 80066b2: af00 add r7, sp, #0 80066b4: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 80066b6: 687b ldr r3, [r7, #4] 80066b8: 60fb str r3, [r7, #12] return ((USBx_HOST->HAINT) & 0xFFFFU); 80066ba: 68fb ldr r3, [r7, #12] 80066bc: f503 6380 add.w r3, r3, #1024 @ 0x400 80066c0: 695b ldr r3, [r3, #20] 80066c2: b29b uxth r3, r3 } 80066c4: 4618 mov r0, r3 80066c6: 3714 adds r7, #20 80066c8: 46bd mov sp, r7 80066ca: f85d 7b04 ldr.w r7, [sp], #4 80066ce: 4770 bx lr 080066d0 : * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { 80066d0: b480 push {r7} 80066d2: b089 sub sp, #36 @ 0x24 80066d4: af00 add r7, sp, #0 80066d6: 6078 str r0, [r7, #4] 80066d8: 460b mov r3, r1 80066da: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80066dc: 687b ldr r3, [r7, #4] 80066de: 61fb str r3, [r7, #28] uint32_t hcnum = (uint32_t)hc_num; 80066e0: 78fb ldrb r3, [r7, #3] 80066e2: 61bb str r3, [r7, #24] __IO uint32_t count = 0U; 80066e4: 2300 movs r3, #0 80066e6: 60bb str r3, [r7, #8] uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; 80066e8: 69bb ldr r3, [r7, #24] 80066ea: 015a lsls r2, r3, #5 80066ec: 69fb ldr r3, [r7, #28] 80066ee: 4413 add r3, r2 80066f0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80066f4: 681b ldr r3, [r3, #0] 80066f6: 0c9b lsrs r3, r3, #18 80066f8: f003 0303 and.w r3, r3, #3 80066fc: 617b str r3, [r7, #20] uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; 80066fe: 69bb ldr r3, [r7, #24] 8006700: 015a lsls r2, r3, #5 8006702: 69fb ldr r3, [r7, #28] 8006704: 4413 add r3, r2 8006706: f503 63a0 add.w r3, r3, #1280 @ 0x500 800670a: 681b ldr r3, [r3, #0] 800670c: 0fdb lsrs r3, r3, #31 800670e: f003 0301 and.w r3, r3, #1 8006712: 613b str r3, [r7, #16] uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; 8006714: 69bb ldr r3, [r7, #24] 8006716: 015a lsls r2, r3, #5 8006718: 69fb ldr r3, [r7, #28] 800671a: 4413 add r3, r2 800671c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006720: 685b ldr r3, [r3, #4] 8006722: 0fdb lsrs r3, r3, #31 8006724: f003 0301 and.w r3, r3, #1 8006728: 60fb str r3, [r7, #12] /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. At the end of the next uframe/frame (in the worst case), the core generates a channel halted and disables the channel automatically. */ if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && 800672a: 687b ldr r3, [r7, #4] 800672c: 689b ldr r3, [r3, #8] 800672e: f003 0320 and.w r3, r3, #32 8006732: 2b20 cmp r3, #32 8006734: d10d bne.n 8006752 8006736: 68fb ldr r3, [r7, #12] 8006738: 2b00 cmp r3, #0 800673a: d10a bne.n 8006752 800673c: 693b ldr r3, [r7, #16] 800673e: 2b00 cmp r3, #0 8006740: d005 beq.n 800674e ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) 8006742: 697b ldr r3, [r7, #20] 8006744: 2b01 cmp r3, #1 8006746: d002 beq.n 800674e 8006748: 697b ldr r3, [r7, #20] 800674a: 2b03 cmp r3, #3 800674c: d101 bne.n 8006752 { return HAL_OK; 800674e: 2300 movs r3, #0 8006750: e0d8 b.n 8006904 } /* Check for space in the request queue to issue the halt. */ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) 8006752: 697b ldr r3, [r7, #20] 8006754: 2b00 cmp r3, #0 8006756: d002 beq.n 800675e 8006758: 697b ldr r3, [r7, #20] 800675a: 2b02 cmp r3, #2 800675c: d173 bne.n 8006846 { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 800675e: 69bb ldr r3, [r7, #24] 8006760: 015a lsls r2, r3, #5 8006762: 69fb ldr r3, [r7, #28] 8006764: 4413 add r3, r2 8006766: f503 63a0 add.w r3, r3, #1280 @ 0x500 800676a: 681b ldr r3, [r3, #0] 800676c: 69ba ldr r2, [r7, #24] 800676e: 0151 lsls r1, r2, #5 8006770: 69fa ldr r2, [r7, #28] 8006772: 440a add r2, r1 8006774: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006778: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800677c: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 800677e: 687b ldr r3, [r7, #4] 8006780: 689b ldr r3, [r3, #8] 8006782: f003 0320 and.w r3, r3, #32 8006786: 2b00 cmp r3, #0 8006788: d14a bne.n 8006820 { if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) 800678a: 687b ldr r3, [r7, #4] 800678c: 6adb ldr r3, [r3, #44] @ 0x2c 800678e: f403 037f and.w r3, r3, #16711680 @ 0xff0000 8006792: 2b00 cmp r3, #0 8006794: d133 bne.n 80067fe { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 8006796: 69bb ldr r3, [r7, #24] 8006798: 015a lsls r2, r3, #5 800679a: 69fb ldr r3, [r7, #28] 800679c: 4413 add r3, r2 800679e: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067a2: 681b ldr r3, [r3, #0] 80067a4: 69ba ldr r2, [r7, #24] 80067a6: 0151 lsls r1, r2, #5 80067a8: 69fa ldr r2, [r7, #28] 80067aa: 440a add r2, r1 80067ac: f502 62a0 add.w r2, r2, #1280 @ 0x500 80067b0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 80067b4: 6013 str r3, [r2, #0] USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 80067b6: 69bb ldr r3, [r7, #24] 80067b8: 015a lsls r2, r3, #5 80067ba: 69fb ldr r3, [r7, #28] 80067bc: 4413 add r3, r2 80067be: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067c2: 681b ldr r3, [r3, #0] 80067c4: 69ba ldr r2, [r7, #24] 80067c6: 0151 lsls r1, r2, #5 80067c8: 69fa ldr r2, [r7, #28] 80067ca: 440a add r2, r1 80067cc: f502 62a0 add.w r2, r2, #1280 @ 0x500 80067d0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80067d4: 6013 str r3, [r2, #0] do { count++; 80067d6: 68bb ldr r3, [r7, #8] 80067d8: 3301 adds r3, #1 80067da: 60bb str r3, [r7, #8] if (count > 1000U) 80067dc: 68bb ldr r3, [r7, #8] 80067de: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80067e2: d82e bhi.n 8006842 { break; } } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 80067e4: 69bb ldr r3, [r7, #24] 80067e6: 015a lsls r2, r3, #5 80067e8: 69fb ldr r3, [r7, #28] 80067ea: 4413 add r3, r2 80067ec: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067f0: 681b ldr r3, [r3, #0] 80067f2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80067f6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80067fa: d0ec beq.n 80067d6 if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 80067fc: e081 b.n 8006902 } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 80067fe: 69bb ldr r3, [r7, #24] 8006800: 015a lsls r2, r3, #5 8006802: 69fb ldr r3, [r7, #28] 8006804: 4413 add r3, r2 8006806: f503 63a0 add.w r3, r3, #1280 @ 0x500 800680a: 681b ldr r3, [r3, #0] 800680c: 69ba ldr r2, [r7, #24] 800680e: 0151 lsls r1, r2, #5 8006810: 69fa ldr r2, [r7, #28] 8006812: 440a add r2, r1 8006814: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006818: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800681c: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 800681e: e070 b.n 8006902 } } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 8006820: 69bb ldr r3, [r7, #24] 8006822: 015a lsls r2, r3, #5 8006824: 69fb ldr r3, [r7, #28] 8006826: 4413 add r3, r2 8006828: f503 63a0 add.w r3, r3, #1280 @ 0x500 800682c: 681b ldr r3, [r3, #0] 800682e: 69ba ldr r2, [r7, #24] 8006830: 0151 lsls r1, r2, #5 8006832: 69fa ldr r2, [r7, #28] 8006834: 440a add r2, r1 8006836: f502 62a0 add.w r2, r2, #1280 @ 0x500 800683a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800683e: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 8006840: e05f b.n 8006902 break; 8006842: bf00 nop if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 8006844: e05d b.n 8006902 } } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 8006846: 69bb ldr r3, [r7, #24] 8006848: 015a lsls r2, r3, #5 800684a: 69fb ldr r3, [r7, #28] 800684c: 4413 add r3, r2 800684e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006852: 681b ldr r3, [r3, #0] 8006854: 69ba ldr r2, [r7, #24] 8006856: 0151 lsls r1, r2, #5 8006858: 69fa ldr r2, [r7, #28] 800685a: 440a add r2, r1 800685c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006860: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8006864: 6013 str r3, [r2, #0] if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) 8006866: 69fb ldr r3, [r7, #28] 8006868: f503 6380 add.w r3, r3, #1024 @ 0x400 800686c: 691b ldr r3, [r3, #16] 800686e: f403 037f and.w r3, r3, #16711680 @ 0xff0000 8006872: 2b00 cmp r3, #0 8006874: d133 bne.n 80068de { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 8006876: 69bb ldr r3, [r7, #24] 8006878: 015a lsls r2, r3, #5 800687a: 69fb ldr r3, [r7, #28] 800687c: 4413 add r3, r2 800687e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006882: 681b ldr r3, [r3, #0] 8006884: 69ba ldr r2, [r7, #24] 8006886: 0151 lsls r1, r2, #5 8006888: 69fa ldr r2, [r7, #28] 800688a: 440a add r2, r1 800688c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006890: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8006894: 6013 str r3, [r2, #0] USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 8006896: 69bb ldr r3, [r7, #24] 8006898: 015a lsls r2, r3, #5 800689a: 69fb ldr r3, [r7, #28] 800689c: 4413 add r3, r2 800689e: f503 63a0 add.w r3, r3, #1280 @ 0x500 80068a2: 681b ldr r3, [r3, #0] 80068a4: 69ba ldr r2, [r7, #24] 80068a6: 0151 lsls r1, r2, #5 80068a8: 69fa ldr r2, [r7, #28] 80068aa: 440a add r2, r1 80068ac: f502 62a0 add.w r2, r2, #1280 @ 0x500 80068b0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80068b4: 6013 str r3, [r2, #0] do { count++; 80068b6: 68bb ldr r3, [r7, #8] 80068b8: 3301 adds r3, #1 80068ba: 60bb str r3, [r7, #8] if (count > 1000U) 80068bc: 68bb ldr r3, [r7, #8] 80068be: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80068c2: d81d bhi.n 8006900 { break; } } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 80068c4: 69bb ldr r3, [r7, #24] 80068c6: 015a lsls r2, r3, #5 80068c8: 69fb ldr r3, [r7, #28] 80068ca: 4413 add r3, r2 80068cc: f503 63a0 add.w r3, r3, #1280 @ 0x500 80068d0: 681b ldr r3, [r3, #0] 80068d2: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80068d6: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80068da: d0ec beq.n 80068b6 80068dc: e011 b.n 8006902 } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 80068de: 69bb ldr r3, [r7, #24] 80068e0: 015a lsls r2, r3, #5 80068e2: 69fb ldr r3, [r7, #28] 80068e4: 4413 add r3, r2 80068e6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80068ea: 681b ldr r3, [r3, #0] 80068ec: 69ba ldr r2, [r7, #24] 80068ee: 0151 lsls r1, r2, #5 80068f0: 69fa ldr r2, [r7, #28] 80068f2: 440a add r2, r1 80068f4: f502 62a0 add.w r2, r2, #1280 @ 0x500 80068f8: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80068fc: 6013 str r3, [r2, #0] 80068fe: e000 b.n 8006902 break; 8006900: bf00 nop } } return HAL_OK; 8006902: 2300 movs r3, #0 } 8006904: 4618 mov r0, r3 8006906: 3724 adds r7, #36 @ 0x24 8006908: 46bd mov sp, r7 800690a: f85d 7b04 ldr.w r7, [sp], #4 800690e: 4770 bx lr 08006910 : * @brief Stop Host Core * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { 8006910: b580 push {r7, lr} 8006912: b088 sub sp, #32 8006914: af00 add r7, sp, #0 8006916: 6078 str r0, [r7, #4] HAL_StatusTypeDef ret = HAL_OK; 8006918: 2300 movs r3, #0 800691a: 77fb strb r3, [r7, #31] uint32_t USBx_BASE = (uint32_t)USBx; 800691c: 687b ldr r3, [r7, #4] 800691e: 617b str r3, [r7, #20] __IO uint32_t count = 0U; 8006920: 2300 movs r3, #0 8006922: 60fb str r3, [r7, #12] uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); 8006924: 6878 ldr r0, [r7, #4] 8006926: f7ff fd7a bl 800641e /* Flush USB FIFO */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 800692a: 2110 movs r1, #16 800692c: 6878 ldr r0, [r7, #4] 800692e: f7ff fd87 bl 8006440 8006932: 4603 mov r3, r0 8006934: 2b00 cmp r3, #0 8006936: d001 beq.n 800693c { ret = HAL_ERROR; 8006938: 2301 movs r3, #1 800693a: 77fb strb r3, [r7, #31] } if (USB_FlushRxFifo(USBx) != HAL_OK) 800693c: 6878 ldr r0, [r7, #4] 800693e: f7ff fdb1 bl 80064a4 8006942: 4603 mov r3, r0 8006944: 2b00 cmp r3, #0 8006946: d001 beq.n 800694c { ret = HAL_ERROR; 8006948: 2301 movs r3, #1 800694a: 77fb strb r3, [r7, #31] } /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) 800694c: 2300 movs r3, #0 800694e: 61bb str r3, [r7, #24] 8006950: e01f b.n 8006992 { value = USBx_HC(i)->HCCHAR; 8006952: 69bb ldr r3, [r7, #24] 8006954: 015a lsls r2, r3, #5 8006956: 697b ldr r3, [r7, #20] 8006958: 4413 add r3, r2 800695a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800695e: 681b ldr r3, [r3, #0] 8006960: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHDIS; 8006962: 693b ldr r3, [r7, #16] 8006964: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8006968: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_CHENA; 800696a: 693b ldr r3, [r7, #16] 800696c: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8006970: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_EPDIR; 8006972: 693b ldr r3, [r7, #16] 8006974: f423 4300 bic.w r3, r3, #32768 @ 0x8000 8006978: 613b str r3, [r7, #16] USBx_HC(i)->HCCHAR = value; 800697a: 69bb ldr r3, [r7, #24] 800697c: 015a lsls r2, r3, #5 800697e: 697b ldr r3, [r7, #20] 8006980: 4413 add r3, r2 8006982: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006986: 461a mov r2, r3 8006988: 693b ldr r3, [r7, #16] 800698a: 6013 str r3, [r2, #0] for (i = 0U; i <= 15U; i++) 800698c: 69bb ldr r3, [r7, #24] 800698e: 3301 adds r3, #1 8006990: 61bb str r3, [r7, #24] 8006992: 69bb ldr r3, [r7, #24] 8006994: 2b0f cmp r3, #15 8006996: d9dc bls.n 8006952 } /* Halt all channels to put them into a known state. */ for (i = 0U; i <= 15U; i++) 8006998: 2300 movs r3, #0 800699a: 61bb str r3, [r7, #24] 800699c: e034 b.n 8006a08 { value = USBx_HC(i)->HCCHAR; 800699e: 69bb ldr r3, [r7, #24] 80069a0: 015a lsls r2, r3, #5 80069a2: 697b ldr r3, [r7, #20] 80069a4: 4413 add r3, r2 80069a6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80069aa: 681b ldr r3, [r3, #0] 80069ac: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHDIS; 80069ae: 693b ldr r3, [r7, #16] 80069b0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 80069b4: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHENA; 80069b6: 693b ldr r3, [r7, #16] 80069b8: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80069bc: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_EPDIR; 80069be: 693b ldr r3, [r7, #16] 80069c0: f423 4300 bic.w r3, r3, #32768 @ 0x8000 80069c4: 613b str r3, [r7, #16] USBx_HC(i)->HCCHAR = value; 80069c6: 69bb ldr r3, [r7, #24] 80069c8: 015a lsls r2, r3, #5 80069ca: 697b ldr r3, [r7, #20] 80069cc: 4413 add r3, r2 80069ce: f503 63a0 add.w r3, r3, #1280 @ 0x500 80069d2: 461a mov r2, r3 80069d4: 693b ldr r3, [r7, #16] 80069d6: 6013 str r3, [r2, #0] do { count++; 80069d8: 68fb ldr r3, [r7, #12] 80069da: 3301 adds r3, #1 80069dc: 60fb str r3, [r7, #12] if (count > 1000U) 80069de: 68fb ldr r3, [r7, #12] 80069e0: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 80069e4: d80c bhi.n 8006a00 { break; } } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 80069e6: 69bb ldr r3, [r7, #24] 80069e8: 015a lsls r2, r3, #5 80069ea: 697b ldr r3, [r7, #20] 80069ec: 4413 add r3, r2 80069ee: f503 63a0 add.w r3, r3, #1280 @ 0x500 80069f2: 681b ldr r3, [r3, #0] 80069f4: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80069f8: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80069fc: d0ec beq.n 80069d8 80069fe: e000 b.n 8006a02 break; 8006a00: bf00 nop for (i = 0U; i <= 15U; i++) 8006a02: 69bb ldr r3, [r7, #24] 8006a04: 3301 adds r3, #1 8006a06: 61bb str r3, [r7, #24] 8006a08: 69bb ldr r3, [r7, #24] 8006a0a: 2b0f cmp r3, #15 8006a0c: d9c7 bls.n 800699e } /* Clear any pending Host interrupts */ USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; 8006a0e: 697b ldr r3, [r7, #20] 8006a10: f503 6380 add.w r3, r3, #1024 @ 0x400 8006a14: 461a mov r2, r3 8006a16: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 8006a1a: 6153 str r3, [r2, #20] USBx->GINTSTS = CLEAR_INTERRUPT_MASK; 8006a1c: 687b ldr r3, [r7, #4] 8006a1e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8006a22: 615a str r2, [r3, #20] (void)USB_EnableGlobalInt(USBx); 8006a24: 6878 ldr r0, [r7, #4] 8006a26: f7ff fce9 bl 80063fc return ret; 8006a2a: 7ffb ldrb r3, [r7, #31] } 8006a2c: 4618 mov r0, r3 8006a2e: 3720 adds r7, #32 8006a30: 46bd mov sp, r7 8006a32: bd80 pop {r7, pc} 08006a34 : * Increment Host Timer tick * @param phost: Host Handle * @retval None */ void USBH_LL_IncTimer(USBH_HandleTypeDef *phost) { 8006a34: b580 push {r7, lr} 8006a36: b082 sub sp, #8 8006a38: af00 add r7, sp, #0 8006a3a: 6078 str r0, [r7, #4] phost->Timer++; 8006a3c: 687b ldr r3, [r7, #4] 8006a3e: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4 8006a42: 1c5a adds r2, r3, #1 8006a44: 687b ldr r3, [r7, #4] 8006a46: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4 USBH_HandleSof(phost); 8006a4a: 6878 ldr r0, [r7, #4] 8006a4c: f000 f804 bl 8006a58 } 8006a50: bf00 nop 8006a52: 3708 adds r7, #8 8006a54: 46bd mov sp, r7 8006a56: bd80 pop {r7, pc} 08006a58 : * Call SOF process * @param phost: Host Handle * @retval None */ static void USBH_HandleSof(USBH_HandleTypeDef *phost) { 8006a58: b580 push {r7, lr} 8006a5a: b082 sub sp, #8 8006a5c: af00 add r7, sp, #0 8006a5e: 6078 str r0, [r7, #4] if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL)) 8006a60: 687b ldr r3, [r7, #4] 8006a62: 781b ldrb r3, [r3, #0] 8006a64: b2db uxtb r3, r3 8006a66: 2b0b cmp r3, #11 8006a68: d10a bne.n 8006a80 8006a6a: 687b ldr r3, [r7, #4] 8006a6c: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c 8006a70: 2b00 cmp r3, #0 8006a72: d005 beq.n 8006a80 { phost->pActiveClass->SOFProcess(phost); 8006a74: 687b ldr r3, [r7, #4] 8006a76: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c 8006a7a: 699b ldr r3, [r3, #24] 8006a7c: 6878 ldr r0, [r7, #4] 8006a7e: 4798 blx r3 } } 8006a80: bf00 nop 8006a82: 3708 adds r7, #8 8006a84: 46bd mov sp, r7 8006a86: bd80 pop {r7, pc} 08006a88 : * Port Enabled * @param phost: Host Handle * @retval None */ void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost) { 8006a88: b580 push {r7, lr} 8006a8a: b082 sub sp, #8 8006a8c: af00 add r7, sp, #0 8006a8e: 6078 str r0, [r7, #4] phost->device.PortEnabled = 1U; 8006a90: 687b ldr r3, [r7, #4] 8006a92: 2201 movs r2, #1 8006a94: f883 2323 strb.w r2, [r3, #803] @ 0x323 #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006a98: 2300 movs r3, #0 8006a9a: 2200 movs r2, #0 8006a9c: 2101 movs r1, #1 8006a9e: 6878 ldr r0, [r7, #4] 8006aa0: f000 f85b bl 8006b5a #endif /* (USBH_USE_OS == 1U) */ return; 8006aa4: bf00 nop } 8006aa6: 3708 adds r7, #8 8006aa8: 46bd mov sp, r7 8006aaa: bd80 pop {r7, pc} 08006aac : * Port Disabled * @param phost: Host Handle * @retval None */ void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost) { 8006aac: b480 push {r7} 8006aae: b083 sub sp, #12 8006ab0: af00 add r7, sp, #0 8006ab2: 6078 str r0, [r7, #4] phost->device.PortEnabled = 0U; 8006ab4: 687b ldr r3, [r7, #4] 8006ab6: 2200 movs r2, #0 8006ab8: f883 2323 strb.w r2, [r3, #803] @ 0x323 phost->device.is_disconnected = 1U; 8006abc: 687b ldr r3, [r7, #4] 8006abe: 2201 movs r2, #1 8006ac0: f883 2321 strb.w r2, [r3, #801] @ 0x321 return; 8006ac4: bf00 nop } 8006ac6: 370c adds r7, #12 8006ac8: 46bd mov sp, r7 8006aca: f85d 7b04 ldr.w r7, [sp], #4 8006ace: 4770 bx lr 08006ad0 : * Handle USB Host connection event * @param phost: Host Handle * @retval USBH_Status */ USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost) { 8006ad0: b580 push {r7, lr} 8006ad2: b082 sub sp, #8 8006ad4: af00 add r7, sp, #0 8006ad6: 6078 str r0, [r7, #4] phost->device.is_connected = 1U; 8006ad8: 687b ldr r3, [r7, #4] 8006ada: 2201 movs r2, #1 8006adc: f883 2320 strb.w r2, [r3, #800] @ 0x320 phost->device.is_disconnected = 0U; 8006ae0: 687b ldr r3, [r7, #4] 8006ae2: 2200 movs r2, #0 8006ae4: f883 2321 strb.w r2, [r3, #801] @ 0x321 phost->device.is_ReEnumerated = 0U; 8006ae8: 687b ldr r3, [r7, #4] 8006aea: 2200 movs r2, #0 8006aec: f883 2322 strb.w r2, [r3, #802] @ 0x322 #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006af0: 2300 movs r3, #0 8006af2: 2200 movs r2, #0 8006af4: 2101 movs r1, #1 8006af6: 6878 ldr r0, [r7, #4] 8006af8: f000 f82f bl 8006b5a #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006afc: 2300 movs r3, #0 } 8006afe: 4618 mov r0, r3 8006b00: 3708 adds r7, #8 8006b02: 46bd mov sp, r7 8006b04: bd80 pop {r7, pc} 08006b06 : * Handle USB Host disconnection event * @param phost: Host Handle * @retval USBH_Status */ USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost) { 8006b06: b580 push {r7, lr} 8006b08: b082 sub sp, #8 8006b0a: af00 add r7, sp, #0 8006b0c: 6078 str r0, [r7, #4] /* update device connection states */ phost->device.is_disconnected = 1U; 8006b0e: 687b ldr r3, [r7, #4] 8006b10: 2201 movs r2, #1 8006b12: f883 2321 strb.w r2, [r3, #801] @ 0x321 phost->device.is_connected = 0U; 8006b16: 687b ldr r3, [r7, #4] 8006b18: 2200 movs r2, #0 8006b1a: f883 2320 strb.w r2, [r3, #800] @ 0x320 phost->device.PortEnabled = 0U; 8006b1e: 687b ldr r3, [r7, #4] 8006b20: 2200 movs r2, #0 8006b22: f883 2323 strb.w r2, [r3, #803] @ 0x323 /* Stop Host */ (void)USBH_LL_Stop(phost); 8006b26: 6878 ldr r0, [r7, #4] 8006b28: f001 f992 bl 8007e50 /* FRee Control Pipes */ (void)USBH_FreePipe(phost, phost->Control.pipe_in); 8006b2c: 687b ldr r3, [r7, #4] 8006b2e: 791b ldrb r3, [r3, #4] 8006b30: 4619 mov r1, r3 8006b32: 6878 ldr r0, [r7, #4] 8006b34: f000 f847 bl 8006bc6 (void)USBH_FreePipe(phost, phost->Control.pipe_out); 8006b38: 687b ldr r3, [r7, #4] 8006b3a: 795b ldrb r3, [r3, #5] 8006b3c: 4619 mov r1, r3 8006b3e: 6878 ldr r0, [r7, #4] 8006b40: f000 f841 bl 8006bc6 #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006b44: 2300 movs r3, #0 8006b46: 2200 movs r2, #0 8006b48: 2101 movs r1, #1 8006b4a: 6878 ldr r0, [r7, #4] 8006b4c: f000 f805 bl 8006b5a #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006b50: 2300 movs r3, #0 } 8006b52: 4618 mov r0, r3 8006b54: 3708 adds r7, #8 8006b56: 46bd mov sp, r7 8006b58: bd80 pop {r7, pc} 08006b5a : * @param timeout message event timeout * @param priority message event priority * @retval None */ void USBH_OS_PutMessage(USBH_HandleTypeDef *phost, USBH_OSEventTypeDef message, uint32_t timeout, uint32_t priority) { 8006b5a: b580 push {r7, lr} 8006b5c: b086 sub sp, #24 8006b5e: af00 add r7, sp, #0 8006b60: 60f8 str r0, [r7, #12] 8006b62: 607a str r2, [r7, #4] 8006b64: 603b str r3, [r7, #0] 8006b66: 460b mov r3, r1 8006b68: 72fb strb r3, [r7, #11] phost->os_msg = (uint32_t)message; 8006b6a: 7afa ldrb r2, [r7, #11] 8006b6c: 68fb ldr r3, [r7, #12] 8006b6e: f8c3 23e0 str.w r2, [r3, #992] @ 0x3e0 #if (osCMSIS < 0x20000U) UNUSED(priority); /* Calculate the number of available spaces */ uint32_t available_spaces = MSGQUEUE_OBJECTS - osMessageWaiting(phost->os_event); 8006b72: 68fb ldr r3, [r7, #12] 8006b74: f8d3 33d8 ldr.w r3, [r3, #984] @ 0x3d8 8006b78: 4618 mov r0, r3 8006b7a: f000 f895 bl 8006ca8 8006b7e: 4603 mov r3, r0 8006b80: f1c3 0310 rsb r3, r3, #16 8006b84: 617b str r3, [r7, #20] if (available_spaces != 0U) 8006b86: 697b ldr r3, [r7, #20] 8006b88: 2b00 cmp r3, #0 8006b8a: d009 beq.n 8006ba0 { (void)osMessagePut(phost->os_event, phost->os_msg, timeout); 8006b8c: 68fb ldr r3, [r7, #12] 8006b8e: f8d3 03d8 ldr.w r0, [r3, #984] @ 0x3d8 8006b92: 68fb ldr r3, [r7, #12] 8006b94: f8d3 33e0 ldr.w r3, [r3, #992] @ 0x3e0 8006b98: 687a ldr r2, [r7, #4] 8006b9a: 4619 mov r1, r3 8006b9c: f000 f844 bl 8006c28 if (osMessageQueueGetSpace(phost->os_event) != 0U) { (void)osMessageQueuePut(phost->os_event, &phost->os_msg, priority, timeout); } #endif /* (osCMSIS < 0x20000U) */ } 8006ba0: bf00 nop 8006ba2: 3718 adds r7, #24 8006ba4: 46bd mov sp, r7 8006ba6: bd80 pop {r7, pc} 08006ba8 : * Notify URB state Change * @param phost: Host handle * @retval USBH Status */ USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost) { 8006ba8: b580 push {r7, lr} 8006baa: b082 sub sp, #8 8006bac: af00 add r7, sp, #0 8006bae: 6078 str r0, [r7, #4] #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006bb0: 2300 movs r3, #0 8006bb2: 2200 movs r2, #0 8006bb4: 2101 movs r1, #1 8006bb6: 6878 ldr r0, [r7, #4] 8006bb8: f7ff ffcf bl 8006b5a #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006bbc: 2300 movs r3, #0 } 8006bbe: 4618 mov r0, r3 8006bc0: 3708 adds r7, #8 8006bc2: 46bd mov sp, r7 8006bc4: bd80 pop {r7, pc} 08006bc6 : * @param phost: Host Handle * @param idx: Pipe number to be freed * @retval USBH Status */ USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx) { 8006bc6: b480 push {r7} 8006bc8: b083 sub sp, #12 8006bca: af00 add r7, sp, #0 8006bcc: 6078 str r0, [r7, #4] 8006bce: 460b mov r3, r1 8006bd0: 70fb strb r3, [r7, #3] if (idx < USBH_MAX_PIPES_NBR) 8006bd2: 78fb ldrb r3, [r7, #3] 8006bd4: 2b0f cmp r3, #15 8006bd6: d80d bhi.n 8006bf4 { phost->Pipes[idx] &= 0x7FFFU; 8006bd8: 78fb ldrb r3, [r7, #3] 8006bda: 687a ldr r2, [r7, #4] 8006bdc: 33e0 adds r3, #224 @ 0xe0 8006bde: 009b lsls r3, r3, #2 8006be0: 4413 add r3, r2 8006be2: 685a ldr r2, [r3, #4] 8006be4: 78fb ldrb r3, [r7, #3] 8006be6: f3c2 020e ubfx r2, r2, #0, #15 8006bea: 6879 ldr r1, [r7, #4] 8006bec: 33e0 adds r3, #224 @ 0xe0 8006bee: 009b lsls r3, r3, #2 8006bf0: 440b add r3, r1 8006bf2: 605a str r2, [r3, #4] } return USBH_OK; 8006bf4: 2300 movs r3, #0 } 8006bf6: 4618 mov r0, r3 8006bf8: 370c adds r7, #12 8006bfa: 46bd mov sp, r7 8006bfc: f85d 7b04 ldr.w r7, [sp], #4 8006c00: 4770 bx lr 08006c02 : #endif /* Determine whether we are in thread mode or handler mode. */ static int inHandlerMode (void) { 8006c02: b480 push {r7} 8006c04: b083 sub sp, #12 8006c06: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8006c08: f3ef 8305 mrs r3, IPSR 8006c0c: 607b str r3, [r7, #4] return(result); 8006c0e: 687b ldr r3, [r7, #4] return __get_IPSR() != 0; 8006c10: 2b00 cmp r3, #0 8006c12: bf14 ite ne 8006c14: 2301 movne r3, #1 8006c16: 2300 moveq r3, #0 8006c18: b2db uxtb r3, r3 } 8006c1a: 4618 mov r0, r3 8006c1c: 370c adds r7, #12 8006c1e: 46bd mov sp, r7 8006c20: f85d 7b04 ldr.w r7, [sp], #4 8006c24: 4770 bx lr ... 08006c28 : * @param millisec timeout value or 0 in case of no time-out. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. */ osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { 8006c28: b580 push {r7, lr} 8006c2a: b086 sub sp, #24 8006c2c: af00 add r7, sp, #0 8006c2e: 60f8 str r0, [r7, #12] 8006c30: 60b9 str r1, [r7, #8] 8006c32: 607a str r2, [r7, #4] portBASE_TYPE taskWoken = pdFALSE; 8006c34: 2300 movs r3, #0 8006c36: 613b str r3, [r7, #16] TickType_t ticks; ticks = millisec / portTICK_PERIOD_MS; 8006c38: 687b ldr r3, [r7, #4] 8006c3a: 617b str r3, [r7, #20] if (ticks == 0) { 8006c3c: 697b ldr r3, [r7, #20] 8006c3e: 2b00 cmp r3, #0 8006c40: d101 bne.n 8006c46 ticks = 1; 8006c42: 2301 movs r3, #1 8006c44: 617b str r3, [r7, #20] } if (inHandlerMode()) { 8006c46: f7ff ffdc bl 8006c02 8006c4a: 4603 mov r3, r0 8006c4c: 2b00 cmp r3, #0 8006c4e: d018 beq.n 8006c82 if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { 8006c50: f107 0210 add.w r2, r7, #16 8006c54: f107 0108 add.w r1, r7, #8 8006c58: 2300 movs r3, #0 8006c5a: 68f8 ldr r0, [r7, #12] 8006c5c: f000 f9c4 bl 8006fe8 8006c60: 4603 mov r3, r0 8006c62: 2b01 cmp r3, #1 8006c64: d001 beq.n 8006c6a return osErrorOS; 8006c66: 23ff movs r3, #255 @ 0xff 8006c68: e018 b.n 8006c9c } portEND_SWITCHING_ISR(taskWoken); 8006c6a: 693b ldr r3, [r7, #16] 8006c6c: 2b00 cmp r3, #0 8006c6e: d014 beq.n 8006c9a 8006c70: 4b0c ldr r3, [pc, #48] @ (8006ca4 ) 8006c72: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006c76: 601a str r2, [r3, #0] 8006c78: f3bf 8f4f dsb sy 8006c7c: f3bf 8f6f isb sy 8006c80: e00b b.n 8006c9a } else { if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { 8006c82: f107 0108 add.w r1, r7, #8 8006c86: 2300 movs r3, #0 8006c88: 697a ldr r2, [r7, #20] 8006c8a: 68f8 ldr r0, [r7, #12] 8006c8c: f000 f8aa bl 8006de4 8006c90: 4603 mov r3, r0 8006c92: 2b01 cmp r3, #1 8006c94: d001 beq.n 8006c9a return osErrorOS; 8006c96: 23ff movs r3, #255 @ 0xff 8006c98: e000 b.n 8006c9c } } return osOK; 8006c9a: 2300 movs r3, #0 } 8006c9c: 4618 mov r0, r3 8006c9e: 3718 adds r7, #24 8006ca0: 46bd mov sp, r7 8006ca2: bd80 pop {r7, pc} 8006ca4: e000ed04 .word 0xe000ed04 08006ca8 : * @brief Get the number of messaged stored in a queue. * @param queue_id message queue ID obtained with \ref osMessageCreate. * @retval number of messages stored in a queue. */ uint32_t osMessageWaiting(osMessageQId queue_id) { 8006ca8: b580 push {r7, lr} 8006caa: b082 sub sp, #8 8006cac: af00 add r7, sp, #0 8006cae: 6078 str r0, [r7, #4] if (inHandlerMode()) { 8006cb0: f7ff ffa7 bl 8006c02 8006cb4: 4603 mov r3, r0 8006cb6: 2b00 cmp r3, #0 8006cb8: d004 beq.n 8006cc4 return uxQueueMessagesWaitingFromISR(queue_id); 8006cba: 6878 ldr r0, [r7, #4] 8006cbc: f000 fa51 bl 8007162 8006cc0: 4603 mov r3, r0 8006cc2: e003 b.n 8006ccc } else { return uxQueueMessagesWaiting(queue_id); 8006cc4: 6878 ldr r0, [r7, #4] 8006cc6: f000 fa2d bl 8007124 8006cca: 4603 mov r3, r0 } } 8006ccc: 4618 mov r0, r3 8006cce: 3708 adds r7, #8 8006cd0: 46bd mov sp, r7 8006cd2: bd80 pop {r7, pc} 08006cd4 : listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8006cd4: b480 push {r7} 8006cd6: b085 sub sp, #20 8006cd8: af00 add r7, sp, #0 8006cda: 6078 str r0, [r7, #4] 8006cdc: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8006cde: 687b ldr r3, [r7, #4] 8006ce0: 685b ldr r3, [r3, #4] 8006ce2: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8006ce4: 683b ldr r3, [r7, #0] 8006ce6: 68fa ldr r2, [r7, #12] 8006ce8: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8006cea: 68fb ldr r3, [r7, #12] 8006cec: 689a ldr r2, [r3, #8] 8006cee: 683b ldr r3, [r7, #0] 8006cf0: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8006cf2: 68fb ldr r3, [r7, #12] 8006cf4: 689b ldr r3, [r3, #8] 8006cf6: 683a ldr r2, [r7, #0] 8006cf8: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8006cfa: 68fb ldr r3, [r7, #12] 8006cfc: 683a ldr r2, [r7, #0] 8006cfe: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8006d00: 683b ldr r3, [r7, #0] 8006d02: 687a ldr r2, [r7, #4] 8006d04: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8006d06: 687b ldr r3, [r7, #4] 8006d08: 681b ldr r3, [r3, #0] 8006d0a: 1c5a adds r2, r3, #1 8006d0c: 687b ldr r3, [r7, #4] 8006d0e: 601a str r2, [r3, #0] } 8006d10: bf00 nop 8006d12: 3714 adds r7, #20 8006d14: 46bd mov sp, r7 8006d16: f85d 7b04 ldr.w r7, [sp], #4 8006d1a: 4770 bx lr 08006d1c : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8006d1c: b480 push {r7} 8006d1e: b085 sub sp, #20 8006d20: af00 add r7, sp, #0 8006d22: 6078 str r0, [r7, #4] 8006d24: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8006d26: 683b ldr r3, [r7, #0] 8006d28: 681b ldr r3, [r3, #0] 8006d2a: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8006d2c: 68bb ldr r3, [r7, #8] 8006d2e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006d32: d103 bne.n 8006d3c { pxIterator = pxList->xListEnd.pxPrevious; 8006d34: 687b ldr r3, [r7, #4] 8006d36: 691b ldr r3, [r3, #16] 8006d38: 60fb str r3, [r7, #12] 8006d3a: e00c b.n 8006d56 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8006d3c: 687b ldr r3, [r7, #4] 8006d3e: 3308 adds r3, #8 8006d40: 60fb str r3, [r7, #12] 8006d42: e002 b.n 8006d4a 8006d44: 68fb ldr r3, [r7, #12] 8006d46: 685b ldr r3, [r3, #4] 8006d48: 60fb str r3, [r7, #12] 8006d4a: 68fb ldr r3, [r7, #12] 8006d4c: 685b ldr r3, [r3, #4] 8006d4e: 681b ldr r3, [r3, #0] 8006d50: 68ba ldr r2, [r7, #8] 8006d52: 429a cmp r2, r3 8006d54: d2f6 bcs.n 8006d44 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8006d56: 68fb ldr r3, [r7, #12] 8006d58: 685a ldr r2, [r3, #4] 8006d5a: 683b ldr r3, [r7, #0] 8006d5c: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8006d5e: 683b ldr r3, [r7, #0] 8006d60: 685b ldr r3, [r3, #4] 8006d62: 683a ldr r2, [r7, #0] 8006d64: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8006d66: 683b ldr r3, [r7, #0] 8006d68: 68fa ldr r2, [r7, #12] 8006d6a: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8006d6c: 68fb ldr r3, [r7, #12] 8006d6e: 683a ldr r2, [r7, #0] 8006d70: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8006d72: 683b ldr r3, [r7, #0] 8006d74: 687a ldr r2, [r7, #4] 8006d76: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8006d78: 687b ldr r3, [r7, #4] 8006d7a: 681b ldr r3, [r3, #0] 8006d7c: 1c5a adds r2, r3, #1 8006d7e: 687b ldr r3, [r7, #4] 8006d80: 601a str r2, [r3, #0] } 8006d82: bf00 nop 8006d84: 3714 adds r7, #20 8006d86: 46bd mov sp, r7 8006d88: f85d 7b04 ldr.w r7, [sp], #4 8006d8c: 4770 bx lr 08006d8e : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8006d8e: b480 push {r7} 8006d90: b085 sub sp, #20 8006d92: af00 add r7, sp, #0 8006d94: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8006d96: 687b ldr r3, [r7, #4] 8006d98: 691b ldr r3, [r3, #16] 8006d9a: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8006d9c: 687b ldr r3, [r7, #4] 8006d9e: 685b ldr r3, [r3, #4] 8006da0: 687a ldr r2, [r7, #4] 8006da2: 6892 ldr r2, [r2, #8] 8006da4: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8006da6: 687b ldr r3, [r7, #4] 8006da8: 689b ldr r3, [r3, #8] 8006daa: 687a ldr r2, [r7, #4] 8006dac: 6852 ldr r2, [r2, #4] 8006dae: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8006db0: 68fb ldr r3, [r7, #12] 8006db2: 685b ldr r3, [r3, #4] 8006db4: 687a ldr r2, [r7, #4] 8006db6: 429a cmp r2, r3 8006db8: d103 bne.n 8006dc2 { pxList->pxIndex = pxItemToRemove->pxPrevious; 8006dba: 687b ldr r3, [r7, #4] 8006dbc: 689a ldr r2, [r3, #8] 8006dbe: 68fb ldr r3, [r7, #12] 8006dc0: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8006dc2: 687b ldr r3, [r7, #4] 8006dc4: 2200 movs r2, #0 8006dc6: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8006dc8: 68fb ldr r3, [r7, #12] 8006dca: 681b ldr r3, [r3, #0] 8006dcc: 1e5a subs r2, r3, #1 8006dce: 68fb ldr r3, [r7, #12] 8006dd0: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8006dd2: 68fb ldr r3, [r7, #12] 8006dd4: 681b ldr r3, [r3, #0] } 8006dd6: 4618 mov r0, r3 8006dd8: 3714 adds r7, #20 8006dda: 46bd mov sp, r7 8006ddc: f85d 7b04 ldr.w r7, [sp], #4 8006de0: 4770 bx lr ... 08006de4 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8006de4: b580 push {r7, lr} 8006de6: b08e sub sp, #56 @ 0x38 8006de8: af00 add r7, sp, #0 8006dea: 60f8 str r0, [r7, #12] 8006dec: 60b9 str r1, [r7, #8] 8006dee: 607a str r2, [r7, #4] 8006df0: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8006df2: 2300 movs r3, #0 8006df4: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8006df6: 68fb ldr r3, [r7, #12] 8006df8: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8006dfa: 6b3b ldr r3, [r7, #48] @ 0x30 8006dfc: 2b00 cmp r3, #0 8006dfe: d10b bne.n 8006e18 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8006e00: f04f 0350 mov.w r3, #80 @ 0x50 8006e04: f383 8811 msr BASEPRI, r3 8006e08: f3bf 8f6f isb sy 8006e0c: f3bf 8f4f dsb sy 8006e10: 62bb str r3, [r7, #40] @ 0x28 " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8006e12: bf00 nop 8006e14: bf00 nop 8006e16: e7fd b.n 8006e14 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8006e18: 68bb ldr r3, [r7, #8] 8006e1a: 2b00 cmp r3, #0 8006e1c: d103 bne.n 8006e26 8006e1e: 6b3b ldr r3, [r7, #48] @ 0x30 8006e20: 6c1b ldr r3, [r3, #64] @ 0x40 8006e22: 2b00 cmp r3, #0 8006e24: d101 bne.n 8006e2a 8006e26: 2301 movs r3, #1 8006e28: e000 b.n 8006e2c 8006e2a: 2300 movs r3, #0 8006e2c: 2b00 cmp r3, #0 8006e2e: d10b bne.n 8006e48 __asm volatile 8006e30: f04f 0350 mov.w r3, #80 @ 0x50 8006e34: f383 8811 msr BASEPRI, r3 8006e38: f3bf 8f6f isb sy 8006e3c: f3bf 8f4f dsb sy 8006e40: 627b str r3, [r7, #36] @ 0x24 } 8006e42: bf00 nop 8006e44: bf00 nop 8006e46: e7fd b.n 8006e44 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8006e48: 683b ldr r3, [r7, #0] 8006e4a: 2b02 cmp r3, #2 8006e4c: d103 bne.n 8006e56 8006e4e: 6b3b ldr r3, [r7, #48] @ 0x30 8006e50: 6bdb ldr r3, [r3, #60] @ 0x3c 8006e52: 2b01 cmp r3, #1 8006e54: d101 bne.n 8006e5a 8006e56: 2301 movs r3, #1 8006e58: e000 b.n 8006e5c 8006e5a: 2300 movs r3, #0 8006e5c: 2b00 cmp r3, #0 8006e5e: d10b bne.n 8006e78 __asm volatile 8006e60: f04f 0350 mov.w r3, #80 @ 0x50 8006e64: f383 8811 msr BASEPRI, r3 8006e68: f3bf 8f6f isb sy 8006e6c: f3bf 8f4f dsb sy 8006e70: 623b str r3, [r7, #32] } 8006e72: bf00 nop 8006e74: bf00 nop 8006e76: e7fd b.n 8006e74 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8006e78: f000 fd7e bl 8007978 8006e7c: 4603 mov r3, r0 8006e7e: 2b00 cmp r3, #0 8006e80: d102 bne.n 8006e88 8006e82: 687b ldr r3, [r7, #4] 8006e84: 2b00 cmp r3, #0 8006e86: d101 bne.n 8006e8c 8006e88: 2301 movs r3, #1 8006e8a: e000 b.n 8006e8e 8006e8c: 2300 movs r3, #0 8006e8e: 2b00 cmp r3, #0 8006e90: d10b bne.n 8006eaa __asm volatile 8006e92: f04f 0350 mov.w r3, #80 @ 0x50 8006e96: f383 8811 msr BASEPRI, r3 8006e9a: f3bf 8f6f isb sy 8006e9e: f3bf 8f4f dsb sy 8006ea2: 61fb str r3, [r7, #28] } 8006ea4: bf00 nop 8006ea6: bf00 nop 8006ea8: e7fd b.n 8006ea6 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8006eaa: f000 fe85 bl 8007bb8 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8006eae: 6b3b ldr r3, [r7, #48] @ 0x30 8006eb0: 6b9a ldr r2, [r3, #56] @ 0x38 8006eb2: 6b3b ldr r3, [r7, #48] @ 0x30 8006eb4: 6bdb ldr r3, [r3, #60] @ 0x3c 8006eb6: 429a cmp r2, r3 8006eb8: d302 bcc.n 8006ec0 8006eba: 683b ldr r3, [r7, #0] 8006ebc: 2b02 cmp r3, #2 8006ebe: d129 bne.n 8006f14 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8006ec0: 683a ldr r2, [r7, #0] 8006ec2: 68b9 ldr r1, [r7, #8] 8006ec4: 6b38 ldr r0, [r7, #48] @ 0x30 8006ec6: f000 f96b bl 80071a0 8006eca: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8006ecc: 6b3b ldr r3, [r7, #48] @ 0x30 8006ece: 6a5b ldr r3, [r3, #36] @ 0x24 8006ed0: 2b00 cmp r3, #0 8006ed2: d010 beq.n 8006ef6 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8006ed4: 6b3b ldr r3, [r7, #48] @ 0x30 8006ed6: 3324 adds r3, #36 @ 0x24 8006ed8: 4618 mov r0, r3 8006eda: f000 fc43 bl 8007764 8006ede: 4603 mov r3, r0 8006ee0: 2b00 cmp r3, #0 8006ee2: d013 beq.n 8006f0c { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8006ee4: 4b3f ldr r3, [pc, #252] @ (8006fe4 ) 8006ee6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006eea: 601a str r2, [r3, #0] 8006eec: f3bf 8f4f dsb sy 8006ef0: f3bf 8f6f isb sy 8006ef4: e00a b.n 8006f0c else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8006ef6: 6afb ldr r3, [r7, #44] @ 0x2c 8006ef8: 2b00 cmp r3, #0 8006efa: d007 beq.n 8006f0c { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8006efc: 4b39 ldr r3, [pc, #228] @ (8006fe4 ) 8006efe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006f02: 601a str r2, [r3, #0] 8006f04: f3bf 8f4f dsb sy 8006f08: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8006f0c: f000 fe86 bl 8007c1c return pdPASS; 8006f10: 2301 movs r3, #1 8006f12: e063 b.n 8006fdc } else { if( xTicksToWait == ( TickType_t ) 0 ) 8006f14: 687b ldr r3, [r7, #4] 8006f16: 2b00 cmp r3, #0 8006f18: d103 bne.n 8006f22 { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8006f1a: f000 fe7f bl 8007c1c /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8006f1e: 2300 movs r3, #0 8006f20: e05c b.n 8006fdc } else if( xEntryTimeSet == pdFALSE ) 8006f22: 6b7b ldr r3, [r7, #52] @ 0x34 8006f24: 2b00 cmp r3, #0 8006f26: d106 bne.n 8006f36 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8006f28: f107 0314 add.w r3, r7, #20 8006f2c: 4618 mov r0, r3 8006f2e: f000 fc7d bl 800782c xEntryTimeSet = pdTRUE; 8006f32: 2301 movs r3, #1 8006f34: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8006f36: f000 fe71 bl 8007c1c /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8006f3a: f000 fa05 bl 8007348 prvLockQueue( pxQueue ); 8006f3e: f000 fe3b bl 8007bb8 8006f42: 6b3b ldr r3, [r7, #48] @ 0x30 8006f44: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8006f48: b25b sxtb r3, r3 8006f4a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006f4e: d103 bne.n 8006f58 8006f50: 6b3b ldr r3, [r7, #48] @ 0x30 8006f52: 2200 movs r2, #0 8006f54: f883 2044 strb.w r2, [r3, #68] @ 0x44 8006f58: 6b3b ldr r3, [r7, #48] @ 0x30 8006f5a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8006f5e: b25b sxtb r3, r3 8006f60: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006f64: d103 bne.n 8006f6e 8006f66: 6b3b ldr r3, [r7, #48] @ 0x30 8006f68: 2200 movs r2, #0 8006f6a: f883 2045 strb.w r2, [r3, #69] @ 0x45 8006f6e: f000 fe55 bl 8007c1c /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8006f72: 1d3a adds r2, r7, #4 8006f74: f107 0314 add.w r3, r7, #20 8006f78: 4611 mov r1, r2 8006f7a: 4618 mov r0, r3 8006f7c: f000 fc6c bl 8007858 8006f80: 4603 mov r3, r0 8006f82: 2b00 cmp r3, #0 8006f84: d124 bne.n 8006fd0 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8006f86: 6b38 ldr r0, [r7, #48] @ 0x30 8006f88: f000 f9c6 bl 8007318 8006f8c: 4603 mov r3, r0 8006f8e: 2b00 cmp r3, #0 8006f90: d018 beq.n 8006fc4 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8006f92: 6b3b ldr r3, [r7, #48] @ 0x30 8006f94: 3310 adds r3, #16 8006f96: 687a ldr r2, [r7, #4] 8006f98: 4611 mov r1, r2 8006f9a: 4618 mov r0, r3 8006f9c: f000 fbbc bl 8007718 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8006fa0: 6b38 ldr r0, [r7, #48] @ 0x30 8006fa2: f000 f967 bl 8007274 /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8006fa6: f000 f9dd bl 8007364 8006faa: 4603 mov r3, r0 8006fac: 2b00 cmp r3, #0 8006fae: f47f af7c bne.w 8006eaa { portYIELD_WITHIN_API(); 8006fb2: 4b0c ldr r3, [pc, #48] @ (8006fe4 ) 8006fb4: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006fb8: 601a str r2, [r3, #0] 8006fba: f3bf 8f4f dsb sy 8006fbe: f3bf 8f6f isb sy 8006fc2: e772 b.n 8006eaa } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8006fc4: 6b38 ldr r0, [r7, #48] @ 0x30 8006fc6: f000 f955 bl 8007274 ( void ) xTaskResumeAll(); 8006fca: f000 f9cb bl 8007364 8006fce: e76c b.n 8006eaa } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8006fd0: 6b38 ldr r0, [r7, #48] @ 0x30 8006fd2: f000 f94f bl 8007274 ( void ) xTaskResumeAll(); 8006fd6: f000 f9c5 bl 8007364 traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8006fda: 2300 movs r3, #0 } } /*lint -restore */ } 8006fdc: 4618 mov r0, r3 8006fde: 3738 adds r7, #56 @ 0x38 8006fe0: 46bd mov sp, r7 8006fe2: bd80 pop {r7, pc} 8006fe4: e000ed04 .word 0xe000ed04 08006fe8 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8006fe8: b580 push {r7, lr} 8006fea: b090 sub sp, #64 @ 0x40 8006fec: af00 add r7, sp, #0 8006fee: 60f8 str r0, [r7, #12] 8006ff0: 60b9 str r1, [r7, #8] 8006ff2: 607a str r2, [r7, #4] 8006ff4: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8006ff6: 68fb ldr r3, [r7, #12] 8006ff8: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8006ffa: 6bbb ldr r3, [r7, #56] @ 0x38 8006ffc: 2b00 cmp r3, #0 8006ffe: d10b bne.n 8007018 __asm volatile 8007000: f04f 0350 mov.w r3, #80 @ 0x50 8007004: f383 8811 msr BASEPRI, r3 8007008: f3bf 8f6f isb sy 800700c: f3bf 8f4f dsb sy 8007010: 62bb str r3, [r7, #40] @ 0x28 } 8007012: bf00 nop 8007014: bf00 nop 8007016: e7fd b.n 8007014 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8007018: 68bb ldr r3, [r7, #8] 800701a: 2b00 cmp r3, #0 800701c: d103 bne.n 8007026 800701e: 6bbb ldr r3, [r7, #56] @ 0x38 8007020: 6c1b ldr r3, [r3, #64] @ 0x40 8007022: 2b00 cmp r3, #0 8007024: d101 bne.n 800702a 8007026: 2301 movs r3, #1 8007028: e000 b.n 800702c 800702a: 2300 movs r3, #0 800702c: 2b00 cmp r3, #0 800702e: d10b bne.n 8007048 __asm volatile 8007030: f04f 0350 mov.w r3, #80 @ 0x50 8007034: f383 8811 msr BASEPRI, r3 8007038: f3bf 8f6f isb sy 800703c: f3bf 8f4f dsb sy 8007040: 627b str r3, [r7, #36] @ 0x24 } 8007042: bf00 nop 8007044: bf00 nop 8007046: e7fd b.n 8007044 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8007048: 683b ldr r3, [r7, #0] 800704a: 2b02 cmp r3, #2 800704c: d103 bne.n 8007056 800704e: 6bbb ldr r3, [r7, #56] @ 0x38 8007050: 6bdb ldr r3, [r3, #60] @ 0x3c 8007052: 2b01 cmp r3, #1 8007054: d101 bne.n 800705a 8007056: 2301 movs r3, #1 8007058: e000 b.n 800705c 800705a: 2300 movs r3, #0 800705c: 2b00 cmp r3, #0 800705e: d10b bne.n 8007078 __asm volatile 8007060: f04f 0350 mov.w r3, #80 @ 0x50 8007064: f383 8811 msr BASEPRI, r3 8007068: f3bf 8f6f isb sy 800706c: f3bf 8f4f dsb sy 8007070: 623b str r3, [r7, #32] } 8007072: bf00 nop 8007074: bf00 nop 8007076: e7fd b.n 8007074 that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8007078: f000 fe50 bl 8007d1c portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 800707c: f3ef 8211 mrs r2, BASEPRI 8007080: f04f 0350 mov.w r3, #80 @ 0x50 8007084: f383 8811 msr BASEPRI, r3 8007088: f3bf 8f6f isb sy 800708c: f3bf 8f4f dsb sy 8007090: 61fa str r2, [r7, #28] 8007092: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 8007094: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 8007096: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8007098: 6bbb ldr r3, [r7, #56] @ 0x38 800709a: 6b9a ldr r2, [r3, #56] @ 0x38 800709c: 6bbb ldr r3, [r7, #56] @ 0x38 800709e: 6bdb ldr r3, [r3, #60] @ 0x3c 80070a0: 429a cmp r2, r3 80070a2: d302 bcc.n 80070aa 80070a4: 683b ldr r3, [r7, #0] 80070a6: 2b02 cmp r3, #2 80070a8: d12f bne.n 800710a { const int8_t cTxLock = pxQueue->cTxLock; 80070aa: 6bbb ldr r3, [r7, #56] @ 0x38 80070ac: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 80070b0: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 80070b4: 6bbb ldr r3, [r7, #56] @ 0x38 80070b6: 6b9b ldr r3, [r3, #56] @ 0x38 80070b8: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 80070ba: 683a ldr r2, [r7, #0] 80070bc: 68b9 ldr r1, [r7, #8] 80070be: 6bb8 ldr r0, [r7, #56] @ 0x38 80070c0: f000 f86e bl 80071a0 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 80070c4: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 80070c8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80070cc: d112 bne.n 80070f4 } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 80070ce: 6bbb ldr r3, [r7, #56] @ 0x38 80070d0: 6a5b ldr r3, [r3, #36] @ 0x24 80070d2: 2b00 cmp r3, #0 80070d4: d016 beq.n 8007104 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 80070d6: 6bbb ldr r3, [r7, #56] @ 0x38 80070d8: 3324 adds r3, #36 @ 0x24 80070da: 4618 mov r0, r3 80070dc: f000 fb42 bl 8007764 80070e0: 4603 mov r3, r0 80070e2: 2b00 cmp r3, #0 80070e4: d00e beq.n 8007104 { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 80070e6: 687b ldr r3, [r7, #4] 80070e8: 2b00 cmp r3, #0 80070ea: d00b beq.n 8007104 { *pxHigherPriorityTaskWoken = pdTRUE; 80070ec: 687b ldr r3, [r7, #4] 80070ee: 2201 movs r2, #1 80070f0: 601a str r2, [r3, #0] 80070f2: e007 b.n 8007104 } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 80070f4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 80070f8: 3301 adds r3, #1 80070fa: b2db uxtb r3, r3 80070fc: b25a sxtb r2, r3 80070fe: 6bbb ldr r3, [r7, #56] @ 0x38 8007100: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 8007104: 2301 movs r3, #1 8007106: 63fb str r3, [r7, #60] @ 0x3c { 8007108: e001 b.n 800710e } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 800710a: 2300 movs r3, #0 800710c: 63fb str r3, [r7, #60] @ 0x3c 800710e: 6b7b ldr r3, [r7, #52] @ 0x34 8007110: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 8007112: 697b ldr r3, [r7, #20] 8007114: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 8007118: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 800711a: 6bfb ldr r3, [r7, #60] @ 0x3c } 800711c: 4618 mov r0, r3 800711e: 3740 adds r7, #64 @ 0x40 8007120: 46bd mov sp, r7 8007122: bd80 pop {r7, pc} 08007124 : return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) { 8007124: b580 push {r7, lr} 8007126: b084 sub sp, #16 8007128: af00 add r7, sp, #0 800712a: 6078 str r0, [r7, #4] UBaseType_t uxReturn; configASSERT( xQueue ); 800712c: 687b ldr r3, [r7, #4] 800712e: 2b00 cmp r3, #0 8007130: d10b bne.n 800714a __asm volatile 8007132: f04f 0350 mov.w r3, #80 @ 0x50 8007136: f383 8811 msr BASEPRI, r3 800713a: f3bf 8f6f isb sy 800713e: f3bf 8f4f dsb sy 8007142: 60bb str r3, [r7, #8] } 8007144: bf00 nop 8007146: bf00 nop 8007148: e7fd b.n 8007146 taskENTER_CRITICAL(); 800714a: f000 fd35 bl 8007bb8 { uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; 800714e: 687b ldr r3, [r7, #4] 8007150: 6b9b ldr r3, [r3, #56] @ 0x38 8007152: 60fb str r3, [r7, #12] } taskEXIT_CRITICAL(); 8007154: f000 fd62 bl 8007c1c return uxReturn; 8007158: 68fb ldr r3, [r7, #12] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 800715a: 4618 mov r0, r3 800715c: 3710 adds r7, #16 800715e: 46bd mov sp, r7 8007160: bd80 pop {r7, pc} 08007162 : return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) { 8007162: b480 push {r7} 8007164: b087 sub sp, #28 8007166: af00 add r7, sp, #0 8007168: 6078 str r0, [r7, #4] UBaseType_t uxReturn; Queue_t * const pxQueue = xQueue; 800716a: 687b ldr r3, [r7, #4] 800716c: 617b str r3, [r7, #20] configASSERT( pxQueue ); 800716e: 697b ldr r3, [r7, #20] 8007170: 2b00 cmp r3, #0 8007172: d10b bne.n 800718c __asm volatile 8007174: f04f 0350 mov.w r3, #80 @ 0x50 8007178: f383 8811 msr BASEPRI, r3 800717c: f3bf 8f6f isb sy 8007180: f3bf 8f4f dsb sy 8007184: 60fb str r3, [r7, #12] } 8007186: bf00 nop 8007188: bf00 nop 800718a: e7fd b.n 8007188 uxReturn = pxQueue->uxMessagesWaiting; 800718c: 697b ldr r3, [r7, #20] 800718e: 6b9b ldr r3, [r3, #56] @ 0x38 8007190: 613b str r3, [r7, #16] return uxReturn; 8007192: 693b ldr r3, [r7, #16] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 8007194: 4618 mov r0, r3 8007196: 371c adds r7, #28 8007198: 46bd mov sp, r7 800719a: f85d 7b04 ldr.w r7, [sp], #4 800719e: 4770 bx lr 080071a0 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 80071a0: b580 push {r7, lr} 80071a2: b086 sub sp, #24 80071a4: af00 add r7, sp, #0 80071a6: 60f8 str r0, [r7, #12] 80071a8: 60b9 str r1, [r7, #8] 80071aa: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 80071ac: 2300 movs r3, #0 80071ae: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 80071b0: 68fb ldr r3, [r7, #12] 80071b2: 6b9b ldr r3, [r3, #56] @ 0x38 80071b4: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 80071b6: 68fb ldr r3, [r7, #12] 80071b8: 6c1b ldr r3, [r3, #64] @ 0x40 80071ba: 2b00 cmp r3, #0 80071bc: d10d bne.n 80071da { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 80071be: 68fb ldr r3, [r7, #12] 80071c0: 681b ldr r3, [r3, #0] 80071c2: 2b00 cmp r3, #0 80071c4: d14d bne.n 8007262 { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 80071c6: 68fb ldr r3, [r7, #12] 80071c8: 689b ldr r3, [r3, #8] 80071ca: 4618 mov r0, r3 80071cc: f000 fbf2 bl 80079b4 80071d0: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 80071d2: 68fb ldr r3, [r7, #12] 80071d4: 2200 movs r2, #0 80071d6: 609a str r2, [r3, #8] 80071d8: e043 b.n 8007262 mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 80071da: 687b ldr r3, [r7, #4] 80071dc: 2b00 cmp r3, #0 80071de: d119 bne.n 8007214 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 80071e0: 68fb ldr r3, [r7, #12] 80071e2: 6858 ldr r0, [r3, #4] 80071e4: 68fb ldr r3, [r7, #12] 80071e6: 6c1b ldr r3, [r3, #64] @ 0x40 80071e8: 461a mov r2, r3 80071ea: 68b9 ldr r1, [r7, #8] 80071ec: f000 fea4 bl 8007f38 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80071f0: 68fb ldr r3, [r7, #12] 80071f2: 685a ldr r2, [r3, #4] 80071f4: 68fb ldr r3, [r7, #12] 80071f6: 6c1b ldr r3, [r3, #64] @ 0x40 80071f8: 441a add r2, r3 80071fa: 68fb ldr r3, [r7, #12] 80071fc: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80071fe: 68fb ldr r3, [r7, #12] 8007200: 685a ldr r2, [r3, #4] 8007202: 68fb ldr r3, [r7, #12] 8007204: 689b ldr r3, [r3, #8] 8007206: 429a cmp r2, r3 8007208: d32b bcc.n 8007262 { pxQueue->pcWriteTo = pxQueue->pcHead; 800720a: 68fb ldr r3, [r7, #12] 800720c: 681a ldr r2, [r3, #0] 800720e: 68fb ldr r3, [r7, #12] 8007210: 605a str r2, [r3, #4] 8007212: e026 b.n 8007262 mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 8007214: 68fb ldr r3, [r7, #12] 8007216: 68d8 ldr r0, [r3, #12] 8007218: 68fb ldr r3, [r7, #12] 800721a: 6c1b ldr r3, [r3, #64] @ 0x40 800721c: 461a mov r2, r3 800721e: 68b9 ldr r1, [r7, #8] 8007220: f000 fe8a bl 8007f38 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 8007224: 68fb ldr r3, [r7, #12] 8007226: 68da ldr r2, [r3, #12] 8007228: 68fb ldr r3, [r7, #12] 800722a: 6c1b ldr r3, [r3, #64] @ 0x40 800722c: 425b negs r3, r3 800722e: 441a add r2, r3 8007230: 68fb ldr r3, [r7, #12] 8007232: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 8007234: 68fb ldr r3, [r7, #12] 8007236: 68da ldr r2, [r3, #12] 8007238: 68fb ldr r3, [r7, #12] 800723a: 681b ldr r3, [r3, #0] 800723c: 429a cmp r2, r3 800723e: d207 bcs.n 8007250 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 8007240: 68fb ldr r3, [r7, #12] 8007242: 689a ldr r2, [r3, #8] 8007244: 68fb ldr r3, [r7, #12] 8007246: 6c1b ldr r3, [r3, #64] @ 0x40 8007248: 425b negs r3, r3 800724a: 441a add r2, r3 800724c: 68fb ldr r3, [r7, #12] 800724e: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8007250: 687b ldr r3, [r7, #4] 8007252: 2b02 cmp r3, #2 8007254: d105 bne.n 8007262 { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 8007256: 693b ldr r3, [r7, #16] 8007258: 2b00 cmp r3, #0 800725a: d002 beq.n 8007262 { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 800725c: 693b ldr r3, [r7, #16] 800725e: 3b01 subs r3, #1 8007260: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 8007262: 693b ldr r3, [r7, #16] 8007264: 1c5a adds r2, r3, #1 8007266: 68fb ldr r3, [r7, #12] 8007268: 639a str r2, [r3, #56] @ 0x38 return xReturn; 800726a: 697b ldr r3, [r7, #20] } 800726c: 4618 mov r0, r3 800726e: 3718 adds r7, #24 8007270: 46bd mov sp, r7 8007272: bd80 pop {r7, pc} 08007274 : } } /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 8007274: b580 push {r7, lr} 8007276: b084 sub sp, #16 8007278: af00 add r7, sp, #0 800727a: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 800727c: f000 fc9c bl 8007bb8 { int8_t cTxLock = pxQueue->cTxLock; 8007280: 687b ldr r3, [r7, #4] 8007282: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8007286: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8007288: e011 b.n 80072ae } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 800728a: 687b ldr r3, [r7, #4] 800728c: 6a5b ldr r3, [r3, #36] @ 0x24 800728e: 2b00 cmp r3, #0 8007290: d012 beq.n 80072b8 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8007292: 687b ldr r3, [r7, #4] 8007294: 3324 adds r3, #36 @ 0x24 8007296: 4618 mov r0, r3 8007298: f000 fa64 bl 8007764 800729c: 4603 mov r3, r0 800729e: 2b00 cmp r3, #0 80072a0: d001 beq.n 80072a6 { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 80072a2: f000 fb3d bl 8007920 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 80072a6: 7bfb ldrb r3, [r7, #15] 80072a8: 3b01 subs r3, #1 80072aa: b2db uxtb r3, r3 80072ac: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 80072ae: f997 300f ldrsb.w r3, [r7, #15] 80072b2: 2b00 cmp r3, #0 80072b4: dce9 bgt.n 800728a 80072b6: e000 b.n 80072ba break; 80072b8: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 80072ba: 687b ldr r3, [r7, #4] 80072bc: 22ff movs r2, #255 @ 0xff 80072be: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 80072c2: f000 fcab bl 8007c1c /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 80072c6: f000 fc77 bl 8007bb8 { int8_t cRxLock = pxQueue->cRxLock; 80072ca: 687b ldr r3, [r7, #4] 80072cc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 80072d0: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80072d2: e011 b.n 80072f8 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 80072d4: 687b ldr r3, [r7, #4] 80072d6: 691b ldr r3, [r3, #16] 80072d8: 2b00 cmp r3, #0 80072da: d012 beq.n 8007302 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 80072dc: 687b ldr r3, [r7, #4] 80072de: 3310 adds r3, #16 80072e0: 4618 mov r0, r3 80072e2: f000 fa3f bl 8007764 80072e6: 4603 mov r3, r0 80072e8: 2b00 cmp r3, #0 80072ea: d001 beq.n 80072f0 { vTaskMissedYield(); 80072ec: f000 fb18 bl 8007920 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80072f0: 7bbb ldrb r3, [r7, #14] 80072f2: 3b01 subs r3, #1 80072f4: b2db uxtb r3, r3 80072f6: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80072f8: f997 300e ldrsb.w r3, [r7, #14] 80072fc: 2b00 cmp r3, #0 80072fe: dce9 bgt.n 80072d4 8007300: e000 b.n 8007304 } else { break; 8007302: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 8007304: 687b ldr r3, [r7, #4] 8007306: 22ff movs r2, #255 @ 0xff 8007308: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 800730c: f000 fc86 bl 8007c1c } 8007310: bf00 nop 8007312: 3710 adds r7, #16 8007314: 46bd mov sp, r7 8007316: bd80 pop {r7, pc} 08007318 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 8007318: b580 push {r7, lr} 800731a: b084 sub sp, #16 800731c: af00 add r7, sp, #0 800731e: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 8007320: f000 fc4a bl 8007bb8 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 8007324: 687b ldr r3, [r7, #4] 8007326: 6b9a ldr r2, [r3, #56] @ 0x38 8007328: 687b ldr r3, [r7, #4] 800732a: 6bdb ldr r3, [r3, #60] @ 0x3c 800732c: 429a cmp r2, r3 800732e: d102 bne.n 8007336 { xReturn = pdTRUE; 8007330: 2301 movs r3, #1 8007332: 60fb str r3, [r7, #12] 8007334: e001 b.n 800733a } else { xReturn = pdFALSE; 8007336: 2300 movs r3, #0 8007338: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 800733a: f000 fc6f bl 8007c1c return xReturn; 800733e: 68fb ldr r3, [r7, #12] } 8007340: 4618 mov r0, r3 8007342: 3710 adds r7, #16 8007344: 46bd mov sp, r7 8007346: bd80 pop {r7, pc} 08007348 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8007348: b480 push {r7} 800734a: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 800734c: 4b04 ldr r3, [pc, #16] @ (8007360 ) 800734e: 681b ldr r3, [r3, #0] 8007350: 3301 adds r3, #1 8007352: 4a03 ldr r2, [pc, #12] @ (8007360 ) 8007354: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 8007356: bf00 nop 8007358: 46bd mov sp, r7 800735a: f85d 7b04 ldr.w r7, [sp], #4 800735e: 4770 bx lr 8007360: 200003c8 .word 0x200003c8 08007364 : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 8007364: b580 push {r7, lr} 8007366: b084 sub sp, #16 8007368: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 800736a: 2300 movs r3, #0 800736c: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 800736e: 2300 movs r3, #0 8007370: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 8007372: 4b42 ldr r3, [pc, #264] @ (800747c ) 8007374: 681b ldr r3, [r3, #0] 8007376: 2b00 cmp r3, #0 8007378: d10b bne.n 8007392 __asm volatile 800737a: f04f 0350 mov.w r3, #80 @ 0x50 800737e: f383 8811 msr BASEPRI, r3 8007382: f3bf 8f6f isb sy 8007386: f3bf 8f4f dsb sy 800738a: 603b str r3, [r7, #0] } 800738c: bf00 nop 800738e: bf00 nop 8007390: e7fd b.n 800738e /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 8007392: f000 fc11 bl 8007bb8 { --uxSchedulerSuspended; 8007396: 4b39 ldr r3, [pc, #228] @ (800747c ) 8007398: 681b ldr r3, [r3, #0] 800739a: 3b01 subs r3, #1 800739c: 4a37 ldr r2, [pc, #220] @ (800747c ) 800739e: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80073a0: 4b36 ldr r3, [pc, #216] @ (800747c ) 80073a2: 681b ldr r3, [r3, #0] 80073a4: 2b00 cmp r3, #0 80073a6: d161 bne.n 800746c { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 80073a8: 4b35 ldr r3, [pc, #212] @ (8007480 ) 80073aa: 681b ldr r3, [r3, #0] 80073ac: 2b00 cmp r3, #0 80073ae: d05d beq.n 800746c { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80073b0: e02e b.n 8007410 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80073b2: 4b34 ldr r3, [pc, #208] @ (8007484 ) 80073b4: 68db ldr r3, [r3, #12] 80073b6: 68db ldr r3, [r3, #12] 80073b8: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 80073ba: 68fb ldr r3, [r7, #12] 80073bc: 3318 adds r3, #24 80073be: 4618 mov r0, r3 80073c0: f7ff fce5 bl 8006d8e ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 80073c4: 68fb ldr r3, [r7, #12] 80073c6: 3304 adds r3, #4 80073c8: 4618 mov r0, r3 80073ca: f7ff fce0 bl 8006d8e prvAddTaskToReadyList( pxTCB ); 80073ce: 68fb ldr r3, [r7, #12] 80073d0: 6adb ldr r3, [r3, #44] @ 0x2c 80073d2: 2201 movs r2, #1 80073d4: 409a lsls r2, r3 80073d6: 4b2c ldr r3, [pc, #176] @ (8007488 ) 80073d8: 681b ldr r3, [r3, #0] 80073da: 4313 orrs r3, r2 80073dc: 4a2a ldr r2, [pc, #168] @ (8007488 ) 80073de: 6013 str r3, [r2, #0] 80073e0: 68fb ldr r3, [r7, #12] 80073e2: 6ada ldr r2, [r3, #44] @ 0x2c 80073e4: 4613 mov r3, r2 80073e6: 009b lsls r3, r3, #2 80073e8: 4413 add r3, r2 80073ea: 009b lsls r3, r3, #2 80073ec: 4a27 ldr r2, [pc, #156] @ (800748c ) 80073ee: 441a add r2, r3 80073f0: 68fb ldr r3, [r7, #12] 80073f2: 3304 adds r3, #4 80073f4: 4619 mov r1, r3 80073f6: 4610 mov r0, r2 80073f8: f7ff fc6c bl 8006cd4 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80073fc: 68fb ldr r3, [r7, #12] 80073fe: 6ada ldr r2, [r3, #44] @ 0x2c 8007400: 4b23 ldr r3, [pc, #140] @ (8007490 ) 8007402: 681b ldr r3, [r3, #0] 8007404: 6adb ldr r3, [r3, #44] @ 0x2c 8007406: 429a cmp r2, r3 8007408: d302 bcc.n 8007410 { xYieldPending = pdTRUE; 800740a: 4b22 ldr r3, [pc, #136] @ (8007494 ) 800740c: 2201 movs r2, #1 800740e: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8007410: 4b1c ldr r3, [pc, #112] @ (8007484 ) 8007412: 681b ldr r3, [r3, #0] 8007414: 2b00 cmp r3, #0 8007416: d1cc bne.n 80073b2 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 8007418: 68fb ldr r3, [r7, #12] 800741a: 2b00 cmp r3, #0 800741c: d001 beq.n 8007422 which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 800741e: f000 fa8b bl 8007938 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 8007422: 4b1d ldr r3, [pc, #116] @ (8007498 ) 8007424: 681b ldr r3, [r3, #0] 8007426: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 8007428: 687b ldr r3, [r7, #4] 800742a: 2b00 cmp r3, #0 800742c: d010 beq.n 8007450 { do { if( xTaskIncrementTick() != pdFALSE ) 800742e: f000 f837 bl 80074a0 8007432: 4603 mov r3, r0 8007434: 2b00 cmp r3, #0 8007436: d002 beq.n 800743e { xYieldPending = pdTRUE; 8007438: 4b16 ldr r3, [pc, #88] @ (8007494 ) 800743a: 2201 movs r2, #1 800743c: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 800743e: 687b ldr r3, [r7, #4] 8007440: 3b01 subs r3, #1 8007442: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 8007444: 687b ldr r3, [r7, #4] 8007446: 2b00 cmp r3, #0 8007448: d1f1 bne.n 800742e xPendedTicks = 0; 800744a: 4b13 ldr r3, [pc, #76] @ (8007498 ) 800744c: 2200 movs r2, #0 800744e: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8007450: 4b10 ldr r3, [pc, #64] @ (8007494 ) 8007452: 681b ldr r3, [r3, #0] 8007454: 2b00 cmp r3, #0 8007456: d009 beq.n 800746c { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8007458: 2301 movs r3, #1 800745a: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 800745c: 4b0f ldr r3, [pc, #60] @ (800749c ) 800745e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8007462: 601a str r2, [r3, #0] 8007464: f3bf 8f4f dsb sy 8007468: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 800746c: f000 fbd6 bl 8007c1c return xAlreadyYielded; 8007470: 68bb ldr r3, [r7, #8] } 8007472: 4618 mov r0, r3 8007474: 3710 adds r7, #16 8007476: 46bd mov sp, r7 8007478: bd80 pop {r7, pc} 800747a: bf00 nop 800747c: 200003c8 .word 0x200003c8 8007480: 200003a8 .word 0x200003a8 8007484: 20000380 .word 0x20000380 8007488: 200003b0 .word 0x200003b0 800748c: 200002ec .word 0x200002ec 8007490: 200002e8 .word 0x200002e8 8007494: 200003bc .word 0x200003bc 8007498: 200003b8 .word 0x200003b8 800749c: e000ed04 .word 0xe000ed04 080074a0 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 80074a0: b580 push {r7, lr} 80074a2: b086 sub sp, #24 80074a4: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 80074a6: 2300 movs r3, #0 80074a8: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 80074aa: 4b4f ldr r3, [pc, #316] @ (80075e8 ) 80074ac: 681b ldr r3, [r3, #0] 80074ae: 2b00 cmp r3, #0 80074b0: f040 808f bne.w 80075d2 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 80074b4: 4b4d ldr r3, [pc, #308] @ (80075ec ) 80074b6: 681b ldr r3, [r3, #0] 80074b8: 3301 adds r3, #1 80074ba: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 80074bc: 4a4b ldr r2, [pc, #300] @ (80075ec ) 80074be: 693b ldr r3, [r7, #16] 80074c0: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 80074c2: 693b ldr r3, [r7, #16] 80074c4: 2b00 cmp r3, #0 80074c6: d121 bne.n 800750c { taskSWITCH_DELAYED_LISTS(); 80074c8: 4b49 ldr r3, [pc, #292] @ (80075f0 ) 80074ca: 681b ldr r3, [r3, #0] 80074cc: 681b ldr r3, [r3, #0] 80074ce: 2b00 cmp r3, #0 80074d0: d00b beq.n 80074ea __asm volatile 80074d2: f04f 0350 mov.w r3, #80 @ 0x50 80074d6: f383 8811 msr BASEPRI, r3 80074da: f3bf 8f6f isb sy 80074de: f3bf 8f4f dsb sy 80074e2: 603b str r3, [r7, #0] } 80074e4: bf00 nop 80074e6: bf00 nop 80074e8: e7fd b.n 80074e6 80074ea: 4b41 ldr r3, [pc, #260] @ (80075f0 ) 80074ec: 681b ldr r3, [r3, #0] 80074ee: 60fb str r3, [r7, #12] 80074f0: 4b40 ldr r3, [pc, #256] @ (80075f4 ) 80074f2: 681b ldr r3, [r3, #0] 80074f4: 4a3e ldr r2, [pc, #248] @ (80075f0 ) 80074f6: 6013 str r3, [r2, #0] 80074f8: 4a3e ldr r2, [pc, #248] @ (80075f4 ) 80074fa: 68fb ldr r3, [r7, #12] 80074fc: 6013 str r3, [r2, #0] 80074fe: 4b3e ldr r3, [pc, #248] @ (80075f8 ) 8007500: 681b ldr r3, [r3, #0] 8007502: 3301 adds r3, #1 8007504: 4a3c ldr r2, [pc, #240] @ (80075f8 ) 8007506: 6013 str r3, [r2, #0] 8007508: f000 fa16 bl 8007938 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 800750c: 4b3b ldr r3, [pc, #236] @ (80075fc ) 800750e: 681b ldr r3, [r3, #0] 8007510: 693a ldr r2, [r7, #16] 8007512: 429a cmp r2, r3 8007514: d348 bcc.n 80075a8 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 8007516: 4b36 ldr r3, [pc, #216] @ (80075f0 ) 8007518: 681b ldr r3, [r3, #0] 800751a: 681b ldr r3, [r3, #0] 800751c: 2b00 cmp r3, #0 800751e: d104 bne.n 800752a /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8007520: 4b36 ldr r3, [pc, #216] @ (80075fc ) 8007522: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007526: 601a str r2, [r3, #0] break; 8007528: e03e b.n 80075a8 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800752a: 4b31 ldr r3, [pc, #196] @ (80075f0 ) 800752c: 681b ldr r3, [r3, #0] 800752e: 68db ldr r3, [r3, #12] 8007530: 68db ldr r3, [r3, #12] 8007532: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 8007534: 68bb ldr r3, [r7, #8] 8007536: 685b ldr r3, [r3, #4] 8007538: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 800753a: 693a ldr r2, [r7, #16] 800753c: 687b ldr r3, [r7, #4] 800753e: 429a cmp r2, r3 8007540: d203 bcs.n 800754a /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 8007542: 4a2e ldr r2, [pc, #184] @ (80075fc ) 8007544: 687b ldr r3, [r7, #4] 8007546: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8007548: e02e b.n 80075a8 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800754a: 68bb ldr r3, [r7, #8] 800754c: 3304 adds r3, #4 800754e: 4618 mov r0, r3 8007550: f7ff fc1d bl 8006d8e /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 8007554: 68bb ldr r3, [r7, #8] 8007556: 6a9b ldr r3, [r3, #40] @ 0x28 8007558: 2b00 cmp r3, #0 800755a: d004 beq.n 8007566 { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 800755c: 68bb ldr r3, [r7, #8] 800755e: 3318 adds r3, #24 8007560: 4618 mov r0, r3 8007562: f7ff fc14 bl 8006d8e mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 8007566: 68bb ldr r3, [r7, #8] 8007568: 6adb ldr r3, [r3, #44] @ 0x2c 800756a: 2201 movs r2, #1 800756c: 409a lsls r2, r3 800756e: 4b24 ldr r3, [pc, #144] @ (8007600 ) 8007570: 681b ldr r3, [r3, #0] 8007572: 4313 orrs r3, r2 8007574: 4a22 ldr r2, [pc, #136] @ (8007600 ) 8007576: 6013 str r3, [r2, #0] 8007578: 68bb ldr r3, [r7, #8] 800757a: 6ada ldr r2, [r3, #44] @ 0x2c 800757c: 4613 mov r3, r2 800757e: 009b lsls r3, r3, #2 8007580: 4413 add r3, r2 8007582: 009b lsls r3, r3, #2 8007584: 4a1f ldr r2, [pc, #124] @ (8007604 ) 8007586: 441a add r2, r3 8007588: 68bb ldr r3, [r7, #8] 800758a: 3304 adds r3, #4 800758c: 4619 mov r1, r3 800758e: 4610 mov r0, r2 8007590: f7ff fba0 bl 8006cd4 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 8007594: 68bb ldr r3, [r7, #8] 8007596: 6ada ldr r2, [r3, #44] @ 0x2c 8007598: 4b1b ldr r3, [pc, #108] @ (8007608 ) 800759a: 681b ldr r3, [r3, #0] 800759c: 6adb ldr r3, [r3, #44] @ 0x2c 800759e: 429a cmp r2, r3 80075a0: d3b9 bcc.n 8007516 { xSwitchRequired = pdTRUE; 80075a2: 2301 movs r3, #1 80075a4: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80075a6: e7b6 b.n 8007516 /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 80075a8: 4b17 ldr r3, [pc, #92] @ (8007608 ) 80075aa: 681b ldr r3, [r3, #0] 80075ac: 6ada ldr r2, [r3, #44] @ 0x2c 80075ae: 4915 ldr r1, [pc, #84] @ (8007604 ) 80075b0: 4613 mov r3, r2 80075b2: 009b lsls r3, r3, #2 80075b4: 4413 add r3, r2 80075b6: 009b lsls r3, r3, #2 80075b8: 440b add r3, r1 80075ba: 681b ldr r3, [r3, #0] 80075bc: 2b01 cmp r3, #1 80075be: d901 bls.n 80075c4 { xSwitchRequired = pdTRUE; 80075c0: 2301 movs r3, #1 80075c2: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 80075c4: 4b11 ldr r3, [pc, #68] @ (800760c ) 80075c6: 681b ldr r3, [r3, #0] 80075c8: 2b00 cmp r3, #0 80075ca: d007 beq.n 80075dc { xSwitchRequired = pdTRUE; 80075cc: 2301 movs r3, #1 80075ce: 617b str r3, [r7, #20] 80075d0: e004 b.n 80075dc } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 80075d2: 4b0f ldr r3, [pc, #60] @ (8007610 ) 80075d4: 681b ldr r3, [r3, #0] 80075d6: 3301 adds r3, #1 80075d8: 4a0d ldr r2, [pc, #52] @ (8007610 ) 80075da: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 80075dc: 697b ldr r3, [r7, #20] } 80075de: 4618 mov r0, r3 80075e0: 3718 adds r7, #24 80075e2: 46bd mov sp, r7 80075e4: bd80 pop {r7, pc} 80075e6: bf00 nop 80075e8: 200003c8 .word 0x200003c8 80075ec: 200003ac .word 0x200003ac 80075f0: 20000378 .word 0x20000378 80075f4: 2000037c .word 0x2000037c 80075f8: 200003c0 .word 0x200003c0 80075fc: 200003c4 .word 0x200003c4 8007600: 200003b0 .word 0x200003b0 8007604: 200002ec .word 0x200002ec 8007608: 200002e8 .word 0x200002e8 800760c: 200003bc .word 0x200003bc 8007610: 200003b8 .word 0x200003b8 08007614 : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 8007614: b580 push {r7, lr} 8007616: b088 sub sp, #32 8007618: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 800761a: 4b3a ldr r3, [pc, #232] @ (8007704 ) 800761c: 681b ldr r3, [r3, #0] 800761e: 2b00 cmp r3, #0 8007620: d003 beq.n 800762a { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 8007622: 4b39 ldr r3, [pc, #228] @ (8007708 ) 8007624: 2201 movs r2, #1 8007626: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 8007628: e067 b.n 80076fa xYieldPending = pdFALSE; 800762a: 4b37 ldr r3, [pc, #220] @ (8007708 ) 800762c: 2200 movs r2, #0 800762e: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 8007630: 4b36 ldr r3, [pc, #216] @ (800770c ) 8007632: 681b ldr r3, [r3, #0] 8007634: 6b1b ldr r3, [r3, #48] @ 0x30 8007636: 61fb str r3, [r7, #28] 8007638: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5 800763c: 61bb str r3, [r7, #24] 800763e: 69fb ldr r3, [r7, #28] 8007640: 681b ldr r3, [r3, #0] 8007642: 69ba ldr r2, [r7, #24] 8007644: 429a cmp r2, r3 8007646: d111 bne.n 800766c 8007648: 69fb ldr r3, [r7, #28] 800764a: 3304 adds r3, #4 800764c: 681b ldr r3, [r3, #0] 800764e: 69ba ldr r2, [r7, #24] 8007650: 429a cmp r2, r3 8007652: d10b bne.n 800766c 8007654: 69fb ldr r3, [r7, #28] 8007656: 3308 adds r3, #8 8007658: 681b ldr r3, [r3, #0] 800765a: 69ba ldr r2, [r7, #24] 800765c: 429a cmp r2, r3 800765e: d105 bne.n 800766c 8007660: 69fb ldr r3, [r7, #28] 8007662: 330c adds r3, #12 8007664: 681b ldr r3, [r3, #0] 8007666: 69ba ldr r2, [r7, #24] 8007668: 429a cmp r2, r3 800766a: d008 beq.n 800767e 800766c: 4b27 ldr r3, [pc, #156] @ (800770c ) 800766e: 681a ldr r2, [r3, #0] 8007670: 4b26 ldr r3, [pc, #152] @ (800770c ) 8007672: 681b ldr r3, [r3, #0] 8007674: 3334 adds r3, #52 @ 0x34 8007676: 4619 mov r1, r3 8007678: 4610 mov r0, r2 800767a: f7f8 ffcb bl 8000614 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800767e: 4b24 ldr r3, [pc, #144] @ (8007710 ) 8007680: 681b ldr r3, [r3, #0] 8007682: 60fb str r3, [r7, #12] __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); 8007684: 68fb ldr r3, [r7, #12] 8007686: fab3 f383 clz r3, r3 800768a: 72fb strb r3, [r7, #11] return ucReturn; 800768c: 7afb ldrb r3, [r7, #11] 800768e: f1c3 031f rsb r3, r3, #31 8007692: 617b str r3, [r7, #20] 8007694: 491f ldr r1, [pc, #124] @ (8007714 ) 8007696: 697a ldr r2, [r7, #20] 8007698: 4613 mov r3, r2 800769a: 009b lsls r3, r3, #2 800769c: 4413 add r3, r2 800769e: 009b lsls r3, r3, #2 80076a0: 440b add r3, r1 80076a2: 681b ldr r3, [r3, #0] 80076a4: 2b00 cmp r3, #0 80076a6: d10b bne.n 80076c0 __asm volatile 80076a8: f04f 0350 mov.w r3, #80 @ 0x50 80076ac: f383 8811 msr BASEPRI, r3 80076b0: f3bf 8f6f isb sy 80076b4: f3bf 8f4f dsb sy 80076b8: 607b str r3, [r7, #4] } 80076ba: bf00 nop 80076bc: bf00 nop 80076be: e7fd b.n 80076bc 80076c0: 697a ldr r2, [r7, #20] 80076c2: 4613 mov r3, r2 80076c4: 009b lsls r3, r3, #2 80076c6: 4413 add r3, r2 80076c8: 009b lsls r3, r3, #2 80076ca: 4a12 ldr r2, [pc, #72] @ (8007714 ) 80076cc: 4413 add r3, r2 80076ce: 613b str r3, [r7, #16] 80076d0: 693b ldr r3, [r7, #16] 80076d2: 685b ldr r3, [r3, #4] 80076d4: 685a ldr r2, [r3, #4] 80076d6: 693b ldr r3, [r7, #16] 80076d8: 605a str r2, [r3, #4] 80076da: 693b ldr r3, [r7, #16] 80076dc: 685a ldr r2, [r3, #4] 80076de: 693b ldr r3, [r7, #16] 80076e0: 3308 adds r3, #8 80076e2: 429a cmp r2, r3 80076e4: d104 bne.n 80076f0 80076e6: 693b ldr r3, [r7, #16] 80076e8: 685b ldr r3, [r3, #4] 80076ea: 685a ldr r2, [r3, #4] 80076ec: 693b ldr r3, [r7, #16] 80076ee: 605a str r2, [r3, #4] 80076f0: 693b ldr r3, [r7, #16] 80076f2: 685b ldr r3, [r3, #4] 80076f4: 68db ldr r3, [r3, #12] 80076f6: 4a05 ldr r2, [pc, #20] @ (800770c ) 80076f8: 6013 str r3, [r2, #0] } 80076fa: bf00 nop 80076fc: 3720 adds r7, #32 80076fe: 46bd mov sp, r7 8007700: bd80 pop {r7, pc} 8007702: bf00 nop 8007704: 200003c8 .word 0x200003c8 8007708: 200003bc .word 0x200003bc 800770c: 200002e8 .word 0x200002e8 8007710: 200003b0 .word 0x200003b0 8007714: 200002ec .word 0x200002ec 08007718 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 8007718: b580 push {r7, lr} 800771a: b084 sub sp, #16 800771c: af00 add r7, sp, #0 800771e: 6078 str r0, [r7, #4] 8007720: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 8007722: 687b ldr r3, [r7, #4] 8007724: 2b00 cmp r3, #0 8007726: d10b bne.n 8007740 __asm volatile 8007728: f04f 0350 mov.w r3, #80 @ 0x50 800772c: f383 8811 msr BASEPRI, r3 8007730: f3bf 8f6f isb sy 8007734: f3bf 8f4f dsb sy 8007738: 60fb str r3, [r7, #12] } 800773a: bf00 nop 800773c: bf00 nop 800773e: e7fd b.n 800773c /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 8007740: 4b07 ldr r3, [pc, #28] @ (8007760 ) 8007742: 681b ldr r3, [r3, #0] 8007744: 3318 adds r3, #24 8007746: 4619 mov r1, r3 8007748: 6878 ldr r0, [r7, #4] 800774a: f7ff fae7 bl 8006d1c prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 800774e: 2101 movs r1, #1 8007750: 6838 ldr r0, [r7, #0] 8007752: f000 f9b7 bl 8007ac4 } 8007756: bf00 nop 8007758: 3710 adds r7, #16 800775a: 46bd mov sp, r7 800775c: bd80 pop {r7, pc} 800775e: bf00 nop 8007760: 200002e8 .word 0x200002e8 08007764 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 8007764: b580 push {r7, lr} 8007766: b086 sub sp, #24 8007768: af00 add r7, sp, #0 800776a: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800776c: 687b ldr r3, [r7, #4] 800776e: 68db ldr r3, [r3, #12] 8007770: 68db ldr r3, [r3, #12] 8007772: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 8007774: 693b ldr r3, [r7, #16] 8007776: 2b00 cmp r3, #0 8007778: d10b bne.n 8007792 __asm volatile 800777a: f04f 0350 mov.w r3, #80 @ 0x50 800777e: f383 8811 msr BASEPRI, r3 8007782: f3bf 8f6f isb sy 8007786: f3bf 8f4f dsb sy 800778a: 60fb str r3, [r7, #12] } 800778c: bf00 nop 800778e: bf00 nop 8007790: e7fd b.n 800778e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 8007792: 693b ldr r3, [r7, #16] 8007794: 3318 adds r3, #24 8007796: 4618 mov r0, r3 8007798: f7ff faf9 bl 8006d8e if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800779c: 4b1d ldr r3, [pc, #116] @ (8007814 ) 800779e: 681b ldr r3, [r3, #0] 80077a0: 2b00 cmp r3, #0 80077a2: d11c bne.n 80077de { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 80077a4: 693b ldr r3, [r7, #16] 80077a6: 3304 adds r3, #4 80077a8: 4618 mov r0, r3 80077aa: f7ff faf0 bl 8006d8e prvAddTaskToReadyList( pxUnblockedTCB ); 80077ae: 693b ldr r3, [r7, #16] 80077b0: 6adb ldr r3, [r3, #44] @ 0x2c 80077b2: 2201 movs r2, #1 80077b4: 409a lsls r2, r3 80077b6: 4b18 ldr r3, [pc, #96] @ (8007818 ) 80077b8: 681b ldr r3, [r3, #0] 80077ba: 4313 orrs r3, r2 80077bc: 4a16 ldr r2, [pc, #88] @ (8007818 ) 80077be: 6013 str r3, [r2, #0] 80077c0: 693b ldr r3, [r7, #16] 80077c2: 6ada ldr r2, [r3, #44] @ 0x2c 80077c4: 4613 mov r3, r2 80077c6: 009b lsls r3, r3, #2 80077c8: 4413 add r3, r2 80077ca: 009b lsls r3, r3, #2 80077cc: 4a13 ldr r2, [pc, #76] @ (800781c ) 80077ce: 441a add r2, r3 80077d0: 693b ldr r3, [r7, #16] 80077d2: 3304 adds r3, #4 80077d4: 4619 mov r1, r3 80077d6: 4610 mov r0, r2 80077d8: f7ff fa7c bl 8006cd4 80077dc: e005 b.n 80077ea } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 80077de: 693b ldr r3, [r7, #16] 80077e0: 3318 adds r3, #24 80077e2: 4619 mov r1, r3 80077e4: 480e ldr r0, [pc, #56] @ (8007820 ) 80077e6: f7ff fa75 bl 8006cd4 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 80077ea: 693b ldr r3, [r7, #16] 80077ec: 6ada ldr r2, [r3, #44] @ 0x2c 80077ee: 4b0d ldr r3, [pc, #52] @ (8007824 ) 80077f0: 681b ldr r3, [r3, #0] 80077f2: 6adb ldr r3, [r3, #44] @ 0x2c 80077f4: 429a cmp r2, r3 80077f6: d905 bls.n 8007804 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 80077f8: 2301 movs r3, #1 80077fa: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80077fc: 4b0a ldr r3, [pc, #40] @ (8007828 ) 80077fe: 2201 movs r2, #1 8007800: 601a str r2, [r3, #0] 8007802: e001 b.n 8007808 } else { xReturn = pdFALSE; 8007804: 2300 movs r3, #0 8007806: 617b str r3, [r7, #20] } return xReturn; 8007808: 697b ldr r3, [r7, #20] } 800780a: 4618 mov r0, r3 800780c: 3718 adds r7, #24 800780e: 46bd mov sp, r7 8007810: bd80 pop {r7, pc} 8007812: bf00 nop 8007814: 200003c8 .word 0x200003c8 8007818: 200003b0 .word 0x200003b0 800781c: 200002ec .word 0x200002ec 8007820: 20000380 .word 0x20000380 8007824: 200002e8 .word 0x200002e8 8007828: 200003bc .word 0x200003bc 0800782c : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 800782c: b480 push {r7} 800782e: b083 sub sp, #12 8007830: af00 add r7, sp, #0 8007832: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 8007834: 4b06 ldr r3, [pc, #24] @ (8007850 ) 8007836: 681a ldr r2, [r3, #0] 8007838: 687b ldr r3, [r7, #4] 800783a: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 800783c: 4b05 ldr r3, [pc, #20] @ (8007854 ) 800783e: 681a ldr r2, [r3, #0] 8007840: 687b ldr r3, [r7, #4] 8007842: 605a str r2, [r3, #4] } 8007844: bf00 nop 8007846: 370c adds r7, #12 8007848: 46bd mov sp, r7 800784a: f85d 7b04 ldr.w r7, [sp], #4 800784e: 4770 bx lr 8007850: 200003c0 .word 0x200003c0 8007854: 200003ac .word 0x200003ac 08007858 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8007858: b580 push {r7, lr} 800785a: b088 sub sp, #32 800785c: af00 add r7, sp, #0 800785e: 6078 str r0, [r7, #4] 8007860: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 8007862: 687b ldr r3, [r7, #4] 8007864: 2b00 cmp r3, #0 8007866: d10b bne.n 8007880 __asm volatile 8007868: f04f 0350 mov.w r3, #80 @ 0x50 800786c: f383 8811 msr BASEPRI, r3 8007870: f3bf 8f6f isb sy 8007874: f3bf 8f4f dsb sy 8007878: 613b str r3, [r7, #16] } 800787a: bf00 nop 800787c: bf00 nop 800787e: e7fd b.n 800787c configASSERT( pxTicksToWait ); 8007880: 683b ldr r3, [r7, #0] 8007882: 2b00 cmp r3, #0 8007884: d10b bne.n 800789e __asm volatile 8007886: f04f 0350 mov.w r3, #80 @ 0x50 800788a: f383 8811 msr BASEPRI, r3 800788e: f3bf 8f6f isb sy 8007892: f3bf 8f4f dsb sy 8007896: 60fb str r3, [r7, #12] } 8007898: bf00 nop 800789a: bf00 nop 800789c: e7fd b.n 800789a taskENTER_CRITICAL(); 800789e: f000 f98b bl 8007bb8 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 80078a2: 4b1d ldr r3, [pc, #116] @ (8007918 ) 80078a4: 681b ldr r3, [r3, #0] 80078a6: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 80078a8: 687b ldr r3, [r7, #4] 80078aa: 685b ldr r3, [r3, #4] 80078ac: 69ba ldr r2, [r7, #24] 80078ae: 1ad3 subs r3, r2, r3 80078b0: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 80078b2: 683b ldr r3, [r7, #0] 80078b4: 681b ldr r3, [r3, #0] 80078b6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 80078ba: d102 bne.n 80078c2 { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 80078bc: 2300 movs r3, #0 80078be: 61fb str r3, [r7, #28] 80078c0: e023 b.n 800790a } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 80078c2: 687b ldr r3, [r7, #4] 80078c4: 681a ldr r2, [r3, #0] 80078c6: 4b15 ldr r3, [pc, #84] @ (800791c ) 80078c8: 681b ldr r3, [r3, #0] 80078ca: 429a cmp r2, r3 80078cc: d007 beq.n 80078de 80078ce: 687b ldr r3, [r7, #4] 80078d0: 685b ldr r3, [r3, #4] 80078d2: 69ba ldr r2, [r7, #24] 80078d4: 429a cmp r2, r3 80078d6: d302 bcc.n 80078de /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 80078d8: 2301 movs r3, #1 80078da: 61fb str r3, [r7, #28] 80078dc: e015 b.n 800790a } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 80078de: 683b ldr r3, [r7, #0] 80078e0: 681b ldr r3, [r3, #0] 80078e2: 697a ldr r2, [r7, #20] 80078e4: 429a cmp r2, r3 80078e6: d20b bcs.n 8007900 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80078e8: 683b ldr r3, [r7, #0] 80078ea: 681a ldr r2, [r3, #0] 80078ec: 697b ldr r3, [r7, #20] 80078ee: 1ad2 subs r2, r2, r3 80078f0: 683b ldr r3, [r7, #0] 80078f2: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80078f4: 6878 ldr r0, [r7, #4] 80078f6: f7ff ff99 bl 800782c xReturn = pdFALSE; 80078fa: 2300 movs r3, #0 80078fc: 61fb str r3, [r7, #28] 80078fe: e004 b.n 800790a } else { *pxTicksToWait = 0; 8007900: 683b ldr r3, [r7, #0] 8007902: 2200 movs r2, #0 8007904: 601a str r2, [r3, #0] xReturn = pdTRUE; 8007906: 2301 movs r3, #1 8007908: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 800790a: f000 f987 bl 8007c1c return xReturn; 800790e: 69fb ldr r3, [r7, #28] } 8007910: 4618 mov r0, r3 8007912: 3720 adds r7, #32 8007914: 46bd mov sp, r7 8007916: bd80 pop {r7, pc} 8007918: 200003ac .word 0x200003ac 800791c: 200003c0 .word 0x200003c0 08007920 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 8007920: b480 push {r7} 8007922: af00 add r7, sp, #0 xYieldPending = pdTRUE; 8007924: 4b03 ldr r3, [pc, #12] @ (8007934 ) 8007926: 2201 movs r2, #1 8007928: 601a str r2, [r3, #0] } 800792a: bf00 nop 800792c: 46bd mov sp, r7 800792e: f85d 7b04 ldr.w r7, [sp], #4 8007932: 4770 bx lr 8007934: 200003bc .word 0x200003bc 08007938 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 8007938: b480 push {r7} 800793a: b083 sub sp, #12 800793c: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800793e: 4b0c ldr r3, [pc, #48] @ (8007970 ) 8007940: 681b ldr r3, [r3, #0] 8007942: 681b ldr r3, [r3, #0] 8007944: 2b00 cmp r3, #0 8007946: d104 bne.n 8007952 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8007948: 4b0a ldr r3, [pc, #40] @ (8007974 ) 800794a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 800794e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8007950: e008 b.n 8007964 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8007952: 4b07 ldr r3, [pc, #28] @ (8007970 ) 8007954: 681b ldr r3, [r3, #0] 8007956: 68db ldr r3, [r3, #12] 8007958: 68db ldr r3, [r3, #12] 800795a: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 800795c: 687b ldr r3, [r7, #4] 800795e: 685b ldr r3, [r3, #4] 8007960: 4a04 ldr r2, [pc, #16] @ (8007974 ) 8007962: 6013 str r3, [r2, #0] } 8007964: bf00 nop 8007966: 370c adds r7, #12 8007968: 46bd mov sp, r7 800796a: f85d 7b04 ldr.w r7, [sp], #4 800796e: 4770 bx lr 8007970: 20000378 .word 0x20000378 8007974: 200003c4 .word 0x200003c4 08007978 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8007978: b480 push {r7} 800797a: b083 sub sp, #12 800797c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 800797e: 4b0b ldr r3, [pc, #44] @ (80079ac ) 8007980: 681b ldr r3, [r3, #0] 8007982: 2b00 cmp r3, #0 8007984: d102 bne.n 800798c { xReturn = taskSCHEDULER_NOT_STARTED; 8007986: 2301 movs r3, #1 8007988: 607b str r3, [r7, #4] 800798a: e008 b.n 800799e } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 800798c: 4b08 ldr r3, [pc, #32] @ (80079b0 ) 800798e: 681b ldr r3, [r3, #0] 8007990: 2b00 cmp r3, #0 8007992: d102 bne.n 800799a { xReturn = taskSCHEDULER_RUNNING; 8007994: 2302 movs r3, #2 8007996: 607b str r3, [r7, #4] 8007998: e001 b.n 800799e } else { xReturn = taskSCHEDULER_SUSPENDED; 800799a: 2300 movs r3, #0 800799c: 607b str r3, [r7, #4] } } return xReturn; 800799e: 687b ldr r3, [r7, #4] } 80079a0: 4618 mov r0, r3 80079a2: 370c adds r7, #12 80079a4: 46bd mov sp, r7 80079a6: f85d 7b04 ldr.w r7, [sp], #4 80079aa: 4770 bx lr 80079ac: 200003b4 .word 0x200003b4 80079b0: 200003c8 .word 0x200003c8 080079b4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 80079b4: b580 push {r7, lr} 80079b6: b086 sub sp, #24 80079b8: af00 add r7, sp, #0 80079ba: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 80079bc: 687b ldr r3, [r7, #4] 80079be: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 80079c0: 2300 movs r3, #0 80079c2: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 80079c4: 687b ldr r3, [r7, #4] 80079c6: 2b00 cmp r3, #0 80079c8: d070 beq.n 8007aac { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 80079ca: 4b3b ldr r3, [pc, #236] @ (8007ab8 ) 80079cc: 681b ldr r3, [r3, #0] 80079ce: 693a ldr r2, [r7, #16] 80079d0: 429a cmp r2, r3 80079d2: d00b beq.n 80079ec __asm volatile 80079d4: f04f 0350 mov.w r3, #80 @ 0x50 80079d8: f383 8811 msr BASEPRI, r3 80079dc: f3bf 8f6f isb sy 80079e0: f3bf 8f4f dsb sy 80079e4: 60fb str r3, [r7, #12] } 80079e6: bf00 nop 80079e8: bf00 nop 80079ea: e7fd b.n 80079e8 configASSERT( pxTCB->uxMutexesHeld ); 80079ec: 693b ldr r3, [r7, #16] 80079ee: 6c9b ldr r3, [r3, #72] @ 0x48 80079f0: 2b00 cmp r3, #0 80079f2: d10b bne.n 8007a0c __asm volatile 80079f4: f04f 0350 mov.w r3, #80 @ 0x50 80079f8: f383 8811 msr BASEPRI, r3 80079fc: f3bf 8f6f isb sy 8007a00: f3bf 8f4f dsb sy 8007a04: 60bb str r3, [r7, #8] } 8007a06: bf00 nop 8007a08: bf00 nop 8007a0a: e7fd b.n 8007a08 ( pxTCB->uxMutexesHeld )--; 8007a0c: 693b ldr r3, [r7, #16] 8007a0e: 6c9b ldr r3, [r3, #72] @ 0x48 8007a10: 1e5a subs r2, r3, #1 8007a12: 693b ldr r3, [r7, #16] 8007a14: 649a str r2, [r3, #72] @ 0x48 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 8007a16: 693b ldr r3, [r7, #16] 8007a18: 6ada ldr r2, [r3, #44] @ 0x2c 8007a1a: 693b ldr r3, [r7, #16] 8007a1c: 6c5b ldr r3, [r3, #68] @ 0x44 8007a1e: 429a cmp r2, r3 8007a20: d044 beq.n 8007aac { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 8007a22: 693b ldr r3, [r7, #16] 8007a24: 6c9b ldr r3, [r3, #72] @ 0x48 8007a26: 2b00 cmp r3, #0 8007a28: d140 bne.n 8007aac /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8007a2a: 693b ldr r3, [r7, #16] 8007a2c: 3304 adds r3, #4 8007a2e: 4618 mov r0, r3 8007a30: f7ff f9ad bl 8006d8e 8007a34: 4603 mov r3, r0 8007a36: 2b00 cmp r3, #0 8007a38: d115 bne.n 8007a66 { taskRESET_READY_PRIORITY( pxTCB->uxPriority ); 8007a3a: 693b ldr r3, [r7, #16] 8007a3c: 6ada ldr r2, [r3, #44] @ 0x2c 8007a3e: 491f ldr r1, [pc, #124] @ (8007abc ) 8007a40: 4613 mov r3, r2 8007a42: 009b lsls r3, r3, #2 8007a44: 4413 add r3, r2 8007a46: 009b lsls r3, r3, #2 8007a48: 440b add r3, r1 8007a4a: 681b ldr r3, [r3, #0] 8007a4c: 2b00 cmp r3, #0 8007a4e: d10a bne.n 8007a66 8007a50: 693b ldr r3, [r7, #16] 8007a52: 6adb ldr r3, [r3, #44] @ 0x2c 8007a54: 2201 movs r2, #1 8007a56: fa02 f303 lsl.w r3, r2, r3 8007a5a: 43da mvns r2, r3 8007a5c: 4b18 ldr r3, [pc, #96] @ (8007ac0 ) 8007a5e: 681b ldr r3, [r3, #0] 8007a60: 4013 ands r3, r2 8007a62: 4a17 ldr r2, [pc, #92] @ (8007ac0 ) 8007a64: 6013 str r3, [r2, #0] } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8007a66: 693b ldr r3, [r7, #16] 8007a68: 6c5a ldr r2, [r3, #68] @ 0x44 8007a6a: 693b ldr r3, [r7, #16] 8007a6c: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8007a6e: 693b ldr r3, [r7, #16] 8007a70: 6adb ldr r3, [r3, #44] @ 0x2c 8007a72: f1c3 0207 rsb r2, r3, #7 8007a76: 693b ldr r3, [r7, #16] 8007a78: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8007a7a: 693b ldr r3, [r7, #16] 8007a7c: 6adb ldr r3, [r3, #44] @ 0x2c 8007a7e: 2201 movs r2, #1 8007a80: 409a lsls r2, r3 8007a82: 4b0f ldr r3, [pc, #60] @ (8007ac0 ) 8007a84: 681b ldr r3, [r3, #0] 8007a86: 4313 orrs r3, r2 8007a88: 4a0d ldr r2, [pc, #52] @ (8007ac0 ) 8007a8a: 6013 str r3, [r2, #0] 8007a8c: 693b ldr r3, [r7, #16] 8007a8e: 6ada ldr r2, [r3, #44] @ 0x2c 8007a90: 4613 mov r3, r2 8007a92: 009b lsls r3, r3, #2 8007a94: 4413 add r3, r2 8007a96: 009b lsls r3, r3, #2 8007a98: 4a08 ldr r2, [pc, #32] @ (8007abc ) 8007a9a: 441a add r2, r3 8007a9c: 693b ldr r3, [r7, #16] 8007a9e: 3304 adds r3, #4 8007aa0: 4619 mov r1, r3 8007aa2: 4610 mov r0, r2 8007aa4: f7ff f916 bl 8006cd4 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8007aa8: 2301 movs r3, #1 8007aaa: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8007aac: 697b ldr r3, [r7, #20] } 8007aae: 4618 mov r0, r3 8007ab0: 3718 adds r7, #24 8007ab2: 46bd mov sp, r7 8007ab4: bd80 pop {r7, pc} 8007ab6: bf00 nop 8007ab8: 200002e8 .word 0x200002e8 8007abc: 200002ec .word 0x200002ec 8007ac0: 200003b0 .word 0x200003b0 08007ac4 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8007ac4: b580 push {r7, lr} 8007ac6: b084 sub sp, #16 8007ac8: af00 add r7, sp, #0 8007aca: 6078 str r0, [r7, #4] 8007acc: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8007ace: 4b29 ldr r3, [pc, #164] @ (8007b74 ) 8007ad0: 681b ldr r3, [r3, #0] 8007ad2: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8007ad4: 4b28 ldr r3, [pc, #160] @ (8007b78 ) 8007ad6: 681b ldr r3, [r3, #0] 8007ad8: 3304 adds r3, #4 8007ada: 4618 mov r0, r3 8007adc: f7ff f957 bl 8006d8e 8007ae0: 4603 mov r3, r0 8007ae2: 2b00 cmp r3, #0 8007ae4: d10b bne.n 8007afe { /* The current task must be in a ready list, so there is no need to check, and the port reset macro can be called directly. */ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ 8007ae6: 4b24 ldr r3, [pc, #144] @ (8007b78 ) 8007ae8: 681b ldr r3, [r3, #0] 8007aea: 6adb ldr r3, [r3, #44] @ 0x2c 8007aec: 2201 movs r2, #1 8007aee: fa02 f303 lsl.w r3, r2, r3 8007af2: 43da mvns r2, r3 8007af4: 4b21 ldr r3, [pc, #132] @ (8007b7c ) 8007af6: 681b ldr r3, [r3, #0] 8007af8: 4013 ands r3, r2 8007afa: 4a20 ldr r2, [pc, #128] @ (8007b7c ) 8007afc: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8007afe: 687b ldr r3, [r7, #4] 8007b00: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8007b04: d10a bne.n 8007b1c 8007b06: 683b ldr r3, [r7, #0] 8007b08: 2b00 cmp r3, #0 8007b0a: d007 beq.n 8007b1c { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007b0c: 4b1a ldr r3, [pc, #104] @ (8007b78 ) 8007b0e: 681b ldr r3, [r3, #0] 8007b10: 3304 adds r3, #4 8007b12: 4619 mov r1, r3 8007b14: 481a ldr r0, [pc, #104] @ (8007b80 ) 8007b16: f7ff f8dd bl 8006cd4 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8007b1a: e026 b.n 8007b6a xTimeToWake = xConstTickCount + xTicksToWait; 8007b1c: 68fa ldr r2, [r7, #12] 8007b1e: 687b ldr r3, [r7, #4] 8007b20: 4413 add r3, r2 8007b22: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8007b24: 4b14 ldr r3, [pc, #80] @ (8007b78 ) 8007b26: 681b ldr r3, [r3, #0] 8007b28: 68ba ldr r2, [r7, #8] 8007b2a: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8007b2c: 68ba ldr r2, [r7, #8] 8007b2e: 68fb ldr r3, [r7, #12] 8007b30: 429a cmp r2, r3 8007b32: d209 bcs.n 8007b48 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007b34: 4b13 ldr r3, [pc, #76] @ (8007b84 ) 8007b36: 681a ldr r2, [r3, #0] 8007b38: 4b0f ldr r3, [pc, #60] @ (8007b78 ) 8007b3a: 681b ldr r3, [r3, #0] 8007b3c: 3304 adds r3, #4 8007b3e: 4619 mov r1, r3 8007b40: 4610 mov r0, r2 8007b42: f7ff f8eb bl 8006d1c } 8007b46: e010 b.n 8007b6a vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007b48: 4b0f ldr r3, [pc, #60] @ (8007b88 ) 8007b4a: 681a ldr r2, [r3, #0] 8007b4c: 4b0a ldr r3, [pc, #40] @ (8007b78 ) 8007b4e: 681b ldr r3, [r3, #0] 8007b50: 3304 adds r3, #4 8007b52: 4619 mov r1, r3 8007b54: 4610 mov r0, r2 8007b56: f7ff f8e1 bl 8006d1c if( xTimeToWake < xNextTaskUnblockTime ) 8007b5a: 4b0c ldr r3, [pc, #48] @ (8007b8c ) 8007b5c: 681b ldr r3, [r3, #0] 8007b5e: 68ba ldr r2, [r7, #8] 8007b60: 429a cmp r2, r3 8007b62: d202 bcs.n 8007b6a xNextTaskUnblockTime = xTimeToWake; 8007b64: 4a09 ldr r2, [pc, #36] @ (8007b8c ) 8007b66: 68bb ldr r3, [r7, #8] 8007b68: 6013 str r3, [r2, #0] } 8007b6a: bf00 nop 8007b6c: 3710 adds r7, #16 8007b6e: 46bd mov sp, r7 8007b70: bd80 pop {r7, pc} 8007b72: bf00 nop 8007b74: 200003ac .word 0x200003ac 8007b78: 200002e8 .word 0x200002e8 8007b7c: 200003b0 .word 0x200003b0 8007b80: 20000394 .word 0x20000394 8007b84: 2000037c .word 0x2000037c 8007b88: 20000378 .word 0x20000378 8007b8c: 200003c4 .word 0x200003c4 08007b90 : } /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8007b90: 4b07 ldr r3, [pc, #28] @ (8007bb0 ) 8007b92: 6819 ldr r1, [r3, #0] 8007b94: 6808 ldr r0, [r1, #0] 8007b96: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007b9a: f380 8809 msr PSP, r0 8007b9e: f3bf 8f6f isb sy 8007ba2: f04f 0000 mov.w r0, #0 8007ba6: f380 8811 msr BASEPRI, r0 8007baa: 4770 bx lr 8007bac: f3af 8000 nop.w 08007bb0 : 8007bb0: 200002e8 .word 0x200002e8 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8007bb4: bf00 nop 8007bb6: bf00 nop 08007bb8 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8007bb8: b480 push {r7} 8007bba: b083 sub sp, #12 8007bbc: af00 add r7, sp, #0 __asm volatile 8007bbe: f04f 0350 mov.w r3, #80 @ 0x50 8007bc2: f383 8811 msr BASEPRI, r3 8007bc6: f3bf 8f6f isb sy 8007bca: f3bf 8f4f dsb sy 8007bce: 607b str r3, [r7, #4] } 8007bd0: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8007bd2: 4b10 ldr r3, [pc, #64] @ (8007c14 ) 8007bd4: 681b ldr r3, [r3, #0] 8007bd6: 3301 adds r3, #1 8007bd8: 4a0e ldr r2, [pc, #56] @ (8007c14 ) 8007bda: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8007bdc: 4b0d ldr r3, [pc, #52] @ (8007c14 ) 8007bde: 681b ldr r3, [r3, #0] 8007be0: 2b01 cmp r3, #1 8007be2: d110 bne.n 8007c06 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8007be4: 4b0c ldr r3, [pc, #48] @ (8007c18 ) 8007be6: 681b ldr r3, [r3, #0] 8007be8: b2db uxtb r3, r3 8007bea: 2b00 cmp r3, #0 8007bec: d00b beq.n 8007c06 __asm volatile 8007bee: f04f 0350 mov.w r3, #80 @ 0x50 8007bf2: f383 8811 msr BASEPRI, r3 8007bf6: f3bf 8f6f isb sy 8007bfa: f3bf 8f4f dsb sy 8007bfe: 603b str r3, [r7, #0] } 8007c00: bf00 nop 8007c02: bf00 nop 8007c04: e7fd b.n 8007c02 } } 8007c06: bf00 nop 8007c08: 370c adds r7, #12 8007c0a: 46bd mov sp, r7 8007c0c: f85d 7b04 ldr.w r7, [sp], #4 8007c10: 4770 bx lr 8007c12: bf00 nop 8007c14: 2000000c .word 0x2000000c 8007c18: e000ed04 .word 0xe000ed04 08007c1c : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8007c1c: b480 push {r7} 8007c1e: b083 sub sp, #12 8007c20: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8007c22: 4b12 ldr r3, [pc, #72] @ (8007c6c ) 8007c24: 681b ldr r3, [r3, #0] 8007c26: 2b00 cmp r3, #0 8007c28: d10b bne.n 8007c42 __asm volatile 8007c2a: f04f 0350 mov.w r3, #80 @ 0x50 8007c2e: f383 8811 msr BASEPRI, r3 8007c32: f3bf 8f6f isb sy 8007c36: f3bf 8f4f dsb sy 8007c3a: 607b str r3, [r7, #4] } 8007c3c: bf00 nop 8007c3e: bf00 nop 8007c40: e7fd b.n 8007c3e uxCriticalNesting--; 8007c42: 4b0a ldr r3, [pc, #40] @ (8007c6c ) 8007c44: 681b ldr r3, [r3, #0] 8007c46: 3b01 subs r3, #1 8007c48: 4a08 ldr r2, [pc, #32] @ (8007c6c ) 8007c4a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8007c4c: 4b07 ldr r3, [pc, #28] @ (8007c6c ) 8007c4e: 681b ldr r3, [r3, #0] 8007c50: 2b00 cmp r3, #0 8007c52: d105 bne.n 8007c60 8007c54: 2300 movs r3, #0 8007c56: 603b str r3, [r7, #0] __asm volatile 8007c58: 683b ldr r3, [r7, #0] 8007c5a: f383 8811 msr BASEPRI, r3 } 8007c5e: bf00 nop { portENABLE_INTERRUPTS(); } } 8007c60: bf00 nop 8007c62: 370c adds r7, #12 8007c64: 46bd mov sp, r7 8007c66: f85d 7b04 ldr.w r7, [sp], #4 8007c6a: 4770 bx lr 8007c6c: 2000000c .word 0x2000000c 08007c70 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8007c70: f3ef 8009 mrs r0, PSP 8007c74: f3bf 8f6f isb sy 8007c78: 4b15 ldr r3, [pc, #84] @ (8007cd0 ) 8007c7a: 681a ldr r2, [r3, #0] 8007c7c: f01e 0f10 tst.w lr, #16 8007c80: bf08 it eq 8007c82: ed20 8a10 vstmdbeq r0!, {s16-s31} 8007c86: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007c8a: 6010 str r0, [r2, #0] 8007c8c: e92d 0009 stmdb sp!, {r0, r3} 8007c90: f04f 0050 mov.w r0, #80 @ 0x50 8007c94: f380 8811 msr BASEPRI, r0 8007c98: f3bf 8f4f dsb sy 8007c9c: f3bf 8f6f isb sy 8007ca0: f7ff fcb8 bl 8007614 8007ca4: f04f 0000 mov.w r0, #0 8007ca8: f380 8811 msr BASEPRI, r0 8007cac: bc09 pop {r0, r3} 8007cae: 6819 ldr r1, [r3, #0] 8007cb0: 6808 ldr r0, [r1, #0] 8007cb2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007cb6: f01e 0f10 tst.w lr, #16 8007cba: bf08 it eq 8007cbc: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8007cc0: f380 8809 msr PSP, r0 8007cc4: f3bf 8f6f isb sy 8007cc8: 4770 bx lr 8007cca: bf00 nop 8007ccc: f3af 8000 nop.w 08007cd0 : 8007cd0: 200002e8 .word 0x200002e8 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8007cd4: bf00 nop 8007cd6: bf00 nop 08007cd8 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8007cd8: b580 push {r7, lr} 8007cda: b082 sub sp, #8 8007cdc: af00 add r7, sp, #0 __asm volatile 8007cde: f04f 0350 mov.w r3, #80 @ 0x50 8007ce2: f383 8811 msr BASEPRI, r3 8007ce6: f3bf 8f6f isb sy 8007cea: f3bf 8f4f dsb sy 8007cee: 607b str r3, [r7, #4] } 8007cf0: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8007cf2: f7ff fbd5 bl 80074a0 8007cf6: 4603 mov r3, r0 8007cf8: 2b00 cmp r3, #0 8007cfa: d003 beq.n 8007d04 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8007cfc: 4b06 ldr r3, [pc, #24] @ (8007d18 ) 8007cfe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8007d02: 601a str r2, [r3, #0] 8007d04: 2300 movs r3, #0 8007d06: 603b str r3, [r7, #0] __asm volatile 8007d08: 683b ldr r3, [r7, #0] 8007d0a: f383 8811 msr BASEPRI, r3 } 8007d0e: bf00 nop } } portENABLE_INTERRUPTS(); } 8007d10: bf00 nop 8007d12: 3708 adds r7, #8 8007d14: 46bd mov sp, r7 8007d16: bd80 pop {r7, pc} 8007d18: e000ed04 .word 0xe000ed04 08007d1c : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8007d1c: b480 push {r7} 8007d1e: b085 sub sp, #20 8007d20: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8007d22: f3ef 8305 mrs r3, IPSR 8007d26: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8007d28: 68fb ldr r3, [r7, #12] 8007d2a: 2b0f cmp r3, #15 8007d2c: d915 bls.n 8007d5a { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8007d2e: 4a18 ldr r2, [pc, #96] @ (8007d90 ) 8007d30: 68fb ldr r3, [r7, #12] 8007d32: 4413 add r3, r2 8007d34: 781b ldrb r3, [r3, #0] 8007d36: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8007d38: 4b16 ldr r3, [pc, #88] @ (8007d94 ) 8007d3a: 781b ldrb r3, [r3, #0] 8007d3c: 7afa ldrb r2, [r7, #11] 8007d3e: 429a cmp r2, r3 8007d40: d20b bcs.n 8007d5a __asm volatile 8007d42: f04f 0350 mov.w r3, #80 @ 0x50 8007d46: f383 8811 msr BASEPRI, r3 8007d4a: f3bf 8f6f isb sy 8007d4e: f3bf 8f4f dsb sy 8007d52: 607b str r3, [r7, #4] } 8007d54: bf00 nop 8007d56: bf00 nop 8007d58: e7fd b.n 8007d56 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8007d5a: 4b0f ldr r3, [pc, #60] @ (8007d98 ) 8007d5c: 681b ldr r3, [r3, #0] 8007d5e: f403 62e0 and.w r2, r3, #1792 @ 0x700 8007d62: 4b0e ldr r3, [pc, #56] @ (8007d9c ) 8007d64: 681b ldr r3, [r3, #0] 8007d66: 429a cmp r2, r3 8007d68: d90b bls.n 8007d82 __asm volatile 8007d6a: f04f 0350 mov.w r3, #80 @ 0x50 8007d6e: f383 8811 msr BASEPRI, r3 8007d72: f3bf 8f6f isb sy 8007d76: f3bf 8f4f dsb sy 8007d7a: 603b str r3, [r7, #0] } 8007d7c: bf00 nop 8007d7e: bf00 nop 8007d80: e7fd b.n 8007d7e } 8007d82: bf00 nop 8007d84: 3714 adds r7, #20 8007d86: 46bd mov sp, r7 8007d88: f85d 7b04 ldr.w r7, [sp], #4 8007d8c: 4770 bx lr 8007d8e: bf00 nop 8007d90: e000e3f0 .word 0xe000e3f0 8007d94: 200003cc .word 0x200003cc 8007d98: e000ed0c .word 0xe000ed0c 8007d9c: 200003d0 .word 0x200003d0 08007da0 : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) { 8007da0: b580 push {r7, lr} 8007da2: b082 sub sp, #8 8007da4: af00 add r7, sp, #0 8007da6: 6078 str r0, [r7, #4] USBH_LL_IncTimer(hhcd->pData); 8007da8: 687b ldr r3, [r7, #4] 8007daa: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007dae: 4618 mov r0, r3 8007db0: f7fe fe40 bl 8006a34 } 8007db4: bf00 nop 8007db6: 3708 adds r7, #8 8007db8: 46bd mov sp, r7 8007dba: bd80 pop {r7, pc} 08007dbc : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) { 8007dbc: b580 push {r7, lr} 8007dbe: b082 sub sp, #8 8007dc0: af00 add r7, sp, #0 8007dc2: 6078 str r0, [r7, #4] USBH_LL_Connect(hhcd->pData); 8007dc4: 687b ldr r3, [r7, #4] 8007dc6: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007dca: 4618 mov r0, r3 8007dcc: f7fe fe80 bl 8006ad0 } 8007dd0: bf00 nop 8007dd2: 3708 adds r7, #8 8007dd4: 46bd mov sp, r7 8007dd6: bd80 pop {r7, pc} 08007dd8 : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) { 8007dd8: b580 push {r7, lr} 8007dda: b082 sub sp, #8 8007ddc: af00 add r7, sp, #0 8007dde: 6078 str r0, [r7, #4] USBH_LL_Disconnect(hhcd->pData); 8007de0: 687b ldr r3, [r7, #4] 8007de2: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007de6: 4618 mov r0, r3 8007de8: f7fe fe8d bl 8006b06 } 8007dec: bf00 nop 8007dee: 3708 adds r7, #8 8007df0: 46bd mov sp, r7 8007df2: bd80 pop {r7, pc} 08007df4 : * @param chnum: channel number * @param urb_state: state * @retval None */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) { 8007df4: b580 push {r7, lr} 8007df6: b082 sub sp, #8 8007df8: af00 add r7, sp, #0 8007dfa: 6078 str r0, [r7, #4] 8007dfc: 460b mov r3, r1 8007dfe: 70fb strb r3, [r7, #3] 8007e00: 4613 mov r3, r2 8007e02: 70bb strb r3, [r7, #2] /* To be used with OS to sync URB state with the global state machine */ #if (USBH_USE_OS == 1) USBH_LL_NotifyURBChange(hhcd->pData); 8007e04: 687b ldr r3, [r7, #4] 8007e06: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007e0a: 4618 mov r0, r3 8007e0c: f7fe fecc bl 8006ba8 #endif } 8007e10: bf00 nop 8007e12: 3708 adds r7, #8 8007e14: 46bd mov sp, r7 8007e16: bd80 pop {r7, pc} 08007e18 : * @brief Port Port Enabled callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) { 8007e18: b580 push {r7, lr} 8007e1a: b082 sub sp, #8 8007e1c: af00 add r7, sp, #0 8007e1e: 6078 str r0, [r7, #4] USBH_LL_PortEnabled(hhcd->pData); 8007e20: 687b ldr r3, [r7, #4] 8007e22: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007e26: 4618 mov r0, r3 8007e28: f7fe fe2e bl 8006a88 } 8007e2c: bf00 nop 8007e2e: 3708 adds r7, #8 8007e30: 46bd mov sp, r7 8007e32: bd80 pop {r7, pc} 08007e34 : * @brief Port Port Disabled callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) { 8007e34: b580 push {r7, lr} 8007e36: b082 sub sp, #8 8007e38: af00 add r7, sp, #0 8007e3a: 6078 str r0, [r7, #4] USBH_LL_PortDisabled(hhcd->pData); 8007e3c: 687b ldr r3, [r7, #4] 8007e3e: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007e42: 4618 mov r0, r3 8007e44: f7fe fe32 bl 8006aac } 8007e48: bf00 nop 8007e4a: 3708 adds r7, #8 8007e4c: 46bd mov sp, r7 8007e4e: bd80 pop {r7, pc} 08007e50 : * @brief Stop the low level portion of the host driver. * @param phost: Host handle * @retval USBH status */ USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost) { 8007e50: b580 push {r7, lr} 8007e52: b084 sub sp, #16 8007e54: af00 add r7, sp, #0 8007e56: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 8007e58: 2300 movs r3, #0 8007e5a: 73fb strb r3, [r7, #15] USBH_StatusTypeDef usb_status = USBH_OK; 8007e5c: 2300 movs r3, #0 8007e5e: 73bb strb r3, [r7, #14] hal_status = HAL_HCD_Stop(phost->pData); 8007e60: 687b ldr r3, [r7, #4] 8007e62: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0 8007e66: 4618 mov r0, r3 8007e68: f7fa fa21 bl 80022ae 8007e6c: 4603 mov r3, r0 8007e6e: 73fb strb r3, [r7, #15] usb_status = USBH_Get_USB_Status(hal_status); 8007e70: 7bfb ldrb r3, [r7, #15] 8007e72: 4618 mov r0, r3 8007e74: f000 f808 bl 8007e88 8007e78: 4603 mov r3, r0 8007e7a: 73bb strb r3, [r7, #14] return usb_status; 8007e7c: 7bbb ldrb r3, [r7, #14] } 8007e7e: 4618 mov r0, r3 8007e80: 3710 adds r7, #16 8007e82: 46bd mov sp, r7 8007e84: bd80 pop {r7, pc} ... 08007e88 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status) { 8007e88: b480 push {r7} 8007e8a: b085 sub sp, #20 8007e8c: af00 add r7, sp, #0 8007e8e: 4603 mov r3, r0 8007e90: 71fb strb r3, [r7, #7] USBH_StatusTypeDef usb_status = USBH_OK; 8007e92: 2300 movs r3, #0 8007e94: 73fb strb r3, [r7, #15] switch (hal_status) 8007e96: 79fb ldrb r3, [r7, #7] 8007e98: 2b03 cmp r3, #3 8007e9a: d817 bhi.n 8007ecc 8007e9c: a201 add r2, pc, #4 @ (adr r2, 8007ea4 ) 8007e9e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007ea2: bf00 nop 8007ea4: 08007eb5 .word 0x08007eb5 8007ea8: 08007ebb .word 0x08007ebb 8007eac: 08007ec1 .word 0x08007ec1 8007eb0: 08007ec7 .word 0x08007ec7 { case HAL_OK : usb_status = USBH_OK; 8007eb4: 2300 movs r3, #0 8007eb6: 73fb strb r3, [r7, #15] break; 8007eb8: e00b b.n 8007ed2 case HAL_ERROR : usb_status = USBH_FAIL; 8007eba: 2302 movs r3, #2 8007ebc: 73fb strb r3, [r7, #15] break; 8007ebe: e008 b.n 8007ed2 case HAL_BUSY : usb_status = USBH_BUSY; 8007ec0: 2301 movs r3, #1 8007ec2: 73fb strb r3, [r7, #15] break; 8007ec4: e005 b.n 8007ed2 case HAL_TIMEOUT : usb_status = USBH_FAIL; 8007ec6: 2302 movs r3, #2 8007ec8: 73fb strb r3, [r7, #15] break; 8007eca: e002 b.n 8007ed2 default : usb_status = USBH_FAIL; 8007ecc: 2302 movs r3, #2 8007ece: 73fb strb r3, [r7, #15] break; 8007ed0: bf00 nop } return usb_status; 8007ed2: 7bfb ldrb r3, [r7, #15] } 8007ed4: 4618 mov r0, r3 8007ed6: 3714 adds r7, #20 8007ed8: 46bd mov sp, r7 8007eda: f85d 7b04 ldr.w r7, [sp], #4 8007ede: 4770 bx lr 08007ee0 : 8007ee0: 4402 add r2, r0 8007ee2: 4603 mov r3, r0 8007ee4: 4293 cmp r3, r2 8007ee6: d100 bne.n 8007eea 8007ee8: 4770 bx lr 8007eea: f803 1b01 strb.w r1, [r3], #1 8007eee: e7f9 b.n 8007ee4 08007ef0 <__libc_init_array>: 8007ef0: b570 push {r4, r5, r6, lr} 8007ef2: 4d0d ldr r5, [pc, #52] @ (8007f28 <__libc_init_array+0x38>) 8007ef4: 4c0d ldr r4, [pc, #52] @ (8007f2c <__libc_init_array+0x3c>) 8007ef6: 1b64 subs r4, r4, r5 8007ef8: 10a4 asrs r4, r4, #2 8007efa: 2600 movs r6, #0 8007efc: 42a6 cmp r6, r4 8007efe: d109 bne.n 8007f14 <__libc_init_array+0x24> 8007f00: 4d0b ldr r5, [pc, #44] @ (8007f30 <__libc_init_array+0x40>) 8007f02: 4c0c ldr r4, [pc, #48] @ (8007f34 <__libc_init_array+0x44>) 8007f04: f000 f826 bl 8007f54 <_init> 8007f08: 1b64 subs r4, r4, r5 8007f0a: 10a4 asrs r4, r4, #2 8007f0c: 2600 movs r6, #0 8007f0e: 42a6 cmp r6, r4 8007f10: d105 bne.n 8007f1e <__libc_init_array+0x2e> 8007f12: bd70 pop {r4, r5, r6, pc} 8007f14: f855 3b04 ldr.w r3, [r5], #4 8007f18: 4798 blx r3 8007f1a: 3601 adds r6, #1 8007f1c: e7ee b.n 8007efc <__libc_init_array+0xc> 8007f1e: f855 3b04 ldr.w r3, [r5], #4 8007f22: 4798 blx r3 8007f24: 3601 adds r6, #1 8007f26: e7f2 b.n 8007f0e <__libc_init_array+0x1e> 8007f28: 08007f8c .word 0x08007f8c 8007f2c: 08007f8c .word 0x08007f8c 8007f30: 08007f8c .word 0x08007f8c 8007f34: 08007f90 .word 0x08007f90 08007f38 : 8007f38: 440a add r2, r1 8007f3a: 4291 cmp r1, r2 8007f3c: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8007f40: d100 bne.n 8007f44 8007f42: 4770 bx lr 8007f44: b510 push {r4, lr} 8007f46: f811 4b01 ldrb.w r4, [r1], #1 8007f4a: f803 4f01 strb.w r4, [r3, #1]! 8007f4e: 4291 cmp r1, r2 8007f50: d1f9 bne.n 8007f46 8007f52: bd10 pop {r4, pc} 08007f54 <_init>: 8007f54: b5f8 push {r3, r4, r5, r6, r7, lr} 8007f56: bf00 nop 8007f58: bcf8 pop {r3, r4, r5, r6, r7} 8007f5a: bc08 pop {r3} 8007f5c: 469e mov lr, r3 8007f5e: 4770 bx lr 08007f60 <_fini>: 8007f60: b5f8 push {r3, r4, r5, r6, r7, lr} 8007f62: bf00 nop 8007f64: bcf8 pop {r3, r4, r5, r6, r7} 8007f66: bc08 pop {r3} 8007f68: 469e mov lr, r3 8007f6a: 4770 bx lr