Calc2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000001ac 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007d7c 080001b0 080001b0 000011b0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000018 08007f2c 08007f2c 00008f2c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007f44 08007f44 00009010 2**0 CONTENTS, READONLY 4 .ARM 00000008 08007f44 08007f44 00008f44 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08007f4c 08007f4c 00009010 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007f4c 08007f4c 00008f4c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08007f50 08007f50 00008f50 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000010 20000000 08007f54 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .ccmram 00000000 10000000 10000000 00009010 2**0 CONTENTS 10 .bss 00000798 20000010 20000010 00009010 2**2 ALLOC 11 ._user_heap_stack 00000600 200007a8 200007a8 00009010 2**0 ALLOC 12 .ARM.attributes 00000030 00000000 00000000 00009010 2**0 CONTENTS, READONLY 13 .debug_info 00025054 00000000 00000000 00009040 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_abbrev 00004ebd 00000000 00000000 0002e094 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_aranges 00002090 00000000 00000000 00032f58 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_rnglists 00001956 00000000 00000000 00034fe8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_macro 00028e25 00000000 00000000 0003693e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_line 0002544a 00000000 00000000 0005f763 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .debug_str 000f417a 00000000 00000000 00084bad 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 20 .comment 00000043 00000000 00000000 00178d27 2**0 CONTENTS, READONLY 21 .debug_frame 00008bf0 00000000 00000000 00178d6c 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 22 .debug_line_str 00000045 00000000 00000000 0018195c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080001b0 <__do_global_dtors_aux>: 80001b0: b510 push {r4, lr} 80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>) 80001b4: 7823 ldrb r3, [r4, #0] 80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16> 80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>) 80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12> 80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>) 80001be: f3af 8000 nop.w 80001c2: 2301 movs r3, #1 80001c4: 7023 strb r3, [r4, #0] 80001c6: bd10 pop {r4, pc} 80001c8: 20000010 .word 0x20000010 80001cc: 00000000 .word 0x00000000 80001d0: 08007f14 .word 0x08007f14 080001d4 : 80001d4: b508 push {r3, lr} 80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 ) 80001d8: b11b cbz r3, 80001e2 80001da: 4903 ldr r1, [pc, #12] @ (80001e8 ) 80001dc: 4803 ldr r0, [pc, #12] @ (80001ec ) 80001de: f3af 8000 nop.w 80001e2: bd08 pop {r3, pc} 80001e4: 00000000 .word 0x00000000 80001e8: 20000014 .word 0x20000014 80001ec: 08007f14 .word 0x08007f14 080001f0 <__aeabi_uldivmod>: 80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18> 80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18> 80001f4: 2900 cmp r1, #0 80001f6: bf08 it eq 80001f8: 2800 cmpeq r0, #0 80001fa: bf1c itt ne 80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff 8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff 8000204: f000 b988 b.w 8000518 <__aeabi_idiv0> 8000208: f1ad 0c08 sub.w ip, sp, #8 800020c: e96d ce04 strd ip, lr, [sp, #-16]! 8000210: f000 f806 bl 8000220 <__udivmoddi4> 8000214: f8dd e004 ldr.w lr, [sp, #4] 8000218: e9dd 2302 ldrd r2, r3, [sp, #8] 800021c: b004 add sp, #16 800021e: 4770 bx lr 08000220 <__udivmoddi4>: 8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8000224: 9d08 ldr r5, [sp, #32] 8000226: 468e mov lr, r1 8000228: 4604 mov r4, r0 800022a: 4688 mov r8, r1 800022c: 2b00 cmp r3, #0 800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6> 8000230: 428a cmp r2, r1 8000232: 4617 mov r7, r2 8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc> 8000236: fab2 f682 clz r6, r2 800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30> 800023c: f1c6 0320 rsb r3, r6, #32 8000240: fa01 f806 lsl.w r8, r1, r6 8000244: fa20 f303 lsr.w r3, r0, r3 8000248: 40b7 lsls r7, r6 800024a: ea43 0808 orr.w r8, r3, r8 800024e: 40b4 lsls r4, r6 8000250: ea4f 4e17 mov.w lr, r7, lsr #16 8000254: fa1f fc87 uxth.w ip, r7 8000258: fbb8 f1fe udiv r1, r8, lr 800025c: 0c23 lsrs r3, r4, #16 800025e: fb0e 8811 mls r8, lr, r1, r8 8000262: ea43 4308 orr.w r3, r3, r8, lsl #16 8000266: fb01 f20c mul.w r2, r1, ip 800026a: 429a cmp r2, r3 800026c: d909 bls.n 8000282 <__udivmoddi4+0x62> 800026e: 18fb adds r3, r7, r3 8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff 8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c> 8000278: 429a cmp r2, r3 800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c> 800027e: 3902 subs r1, #2 8000280: 443b add r3, r7 8000282: 1a9a subs r2, r3, r2 8000284: b2a3 uxth r3, r4 8000286: fbb2 f0fe udiv r0, r2, lr 800028a: fb0e 2210 mls r2, lr, r0, r2 800028e: ea43 4302 orr.w r3, r3, r2, lsl #16 8000292: fb00 fc0c mul.w ip, r0, ip 8000296: 459c cmp ip, r3 8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e> 800029a: 18fb adds r3, r7, r3 800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff 80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230> 80002a4: 459c cmp ip, r3 80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230> 80002aa: 443b add r3, r7 80002ac: 3802 subs r0, #2 80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16 80002b2: eba3 030c sub.w r3, r3, ip 80002b6: 2100 movs r1, #0 80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2> 80002ba: 40f3 lsrs r3, r6 80002bc: 2200 movs r2, #0 80002be: e9c5 3200 strd r3, r2, [r5] 80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 80002c6: 428b cmp r3, r1 80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6> 80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0> 80002cc: e9c5 0100 strd r0, r1, [r5] 80002d0: 2100 movs r1, #0 80002d2: 4608 mov r0, r1 80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2> 80002d6: fab3 f183 clz r1, r3 80002da: 2900 cmp r1, #0 80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c> 80002de: 4573 cmp r3, lr 80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8> 80002e2: 4282 cmp r2, r0 80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2> 80002e8: 1a84 subs r4, r0, r2 80002ea: eb6e 0203 sbc.w r2, lr, r3 80002ee: 2001 movs r0, #1 80002f0: 4690 mov r8, r2 80002f2: 2d00 cmp r5, #0 80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2> 80002f6: e9c5 4800 strd r4, r8, [r5] 80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2> 80002fc: 2a00 cmp r2, #0 80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202> 8000302: fab2 f682 clz r6, r2 8000306: 2e00 cmp r6, #0 8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234> 800030c: 1a8a subs r2, r1, r2 800030e: 0c03 lsrs r3, r0, #16 8000310: ea4f 4e17 mov.w lr, r7, lsr #16 8000314: b280 uxth r0, r0 8000316: b2bc uxth r4, r7 8000318: 2101 movs r1, #1 800031a: fbb2 fcfe udiv ip, r2, lr 800031e: fb0e 221c mls r2, lr, ip, r2 8000322: ea43 4302 orr.w r3, r3, r2, lsl #16 8000326: fb04 f20c mul.w r2, r4, ip 800032a: 429a cmp r2, r3 800032c: d907 bls.n 800033e <__udivmoddi4+0x11e> 800032e: 18fb adds r3, r7, r3 8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff 8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c> 8000336: 429a cmp r2, r3 8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc> 800033c: 46c4 mov ip, r8 800033e: 1a9b subs r3, r3, r2 8000340: fbb3 f2fe udiv r2, r3, lr 8000344: fb0e 3312 mls r3, lr, r2, r3 8000348: ea40 4303 orr.w r3, r0, r3, lsl #16 800034c: fb02 f404 mul.w r4, r2, r4 8000350: 429c cmp r4, r3 8000352: d907 bls.n 8000364 <__udivmoddi4+0x144> 8000354: 18fb adds r3, r7, r3 8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff 800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142> 800035c: 429c cmp r4, r3 800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6> 8000362: 4602 mov r2, r0 8000364: 1b1b subs r3, r3, r4 8000366: ea42 400c orr.w r0, r2, ip, lsl #16 800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98> 800036c: f1c1 0620 rsb r6, r1, #32 8000370: 408b lsls r3, r1 8000372: fa22 f706 lsr.w r7, r2, r6 8000376: 431f orrs r7, r3 8000378: fa0e f401 lsl.w r4, lr, r1 800037c: fa20 f306 lsr.w r3, r0, r6 8000380: fa2e fe06 lsr.w lr, lr, r6 8000384: ea4f 4917 mov.w r9, r7, lsr #16 8000388: 4323 orrs r3, r4 800038a: fa00 f801 lsl.w r8, r0, r1 800038e: fa1f fc87 uxth.w ip, r7 8000392: fbbe f0f9 udiv r0, lr, r9 8000396: 0c1c lsrs r4, r3, #16 8000398: fb09 ee10 mls lr, r9, r0, lr 800039c: ea44 440e orr.w r4, r4, lr, lsl #16 80003a0: fb00 fe0c mul.w lr, r0, ip 80003a4: 45a6 cmp lr, r4 80003a6: fa02 f201 lsl.w r2, r2, r1 80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0> 80003ac: 193c adds r4, r7, r4 80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff 80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce> 80003b6: 45a6 cmp lr, r4 80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce> 80003bc: 3802 subs r0, #2 80003be: 443c add r4, r7 80003c0: eba4 040e sub.w r4, r4, lr 80003c4: fa1f fe83 uxth.w lr, r3 80003c8: fbb4 f3f9 udiv r3, r4, r9 80003cc: fb09 4413 mls r4, r9, r3, r4 80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16 80003d4: fb03 fc0c mul.w ip, r3, ip 80003d8: 45a4 cmp ip, r4 80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce> 80003dc: 193c adds r4, r7, r4 80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff 80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca> 80003e6: 45a4 cmp ip, r4 80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca> 80003ea: 3b02 subs r3, #2 80003ec: 443c add r4, r7 80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16 80003f2: eba4 040c sub.w r4, r4, ip 80003f6: fba0 ec02 umull lr, ip, r0, r2 80003fa: 4564 cmp r4, ip 80003fc: 4673 mov r3, lr 80003fe: 46e1 mov r9, ip 8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8> 8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4> 8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe> 8000406: ebb8 0203 subs.w r2, r8, r3 800040a: eb64 0409 sbc.w r4, r4, r9 800040e: fa04 f606 lsl.w r6, r4, r6 8000412: fa22 f301 lsr.w r3, r2, r1 8000416: 431e orrs r6, r3 8000418: 40cc lsrs r4, r1 800041a: e9c5 6400 strd r6, r4, [r5] 800041e: 2100 movs r1, #0 8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2> 8000422: fbb1 fcf2 udiv ip, r1, r2 8000426: 0c01 lsrs r1, r0, #16 8000428: ea41 410e orr.w r1, r1, lr, lsl #16 800042c: b280 uxth r0, r0 800042e: ea40 4201 orr.w r2, r0, r1, lsl #16 8000432: 463b mov r3, r7 8000434: 4638 mov r0, r7 8000436: 463c mov r4, r7 8000438: 46b8 mov r8, r7 800043a: 46be mov lr, r7 800043c: 2620 movs r6, #32 800043e: fbb1 f1f7 udiv r1, r1, r7 8000442: eba2 0208 sub.w r2, r2, r8 8000446: ea41 410c orr.w r1, r1, ip, lsl #16 800044a: e766 b.n 800031a <__udivmoddi4+0xfa> 800044c: 4601 mov r1, r0 800044e: e718 b.n 8000282 <__udivmoddi4+0x62> 8000450: 4610 mov r0, r2 8000452: e72c b.n 80002ae <__udivmoddi4+0x8e> 8000454: f1c6 0220 rsb r2, r6, #32 8000458: fa2e f302 lsr.w r3, lr, r2 800045c: 40b7 lsls r7, r6 800045e: 40b1 lsls r1, r6 8000460: fa20 f202 lsr.w r2, r0, r2 8000464: ea4f 4e17 mov.w lr, r7, lsr #16 8000468: 430a orrs r2, r1 800046a: fbb3 f8fe udiv r8, r3, lr 800046e: b2bc uxth r4, r7 8000470: fb0e 3318 mls r3, lr, r8, r3 8000474: 0c11 lsrs r1, r2, #16 8000476: ea41 4103 orr.w r1, r1, r3, lsl #16 800047a: fb08 f904 mul.w r9, r8, r4 800047e: 40b0 lsls r0, r6 8000480: 4589 cmp r9, r1 8000482: ea4f 4310 mov.w r3, r0, lsr #16 8000486: b280 uxth r0, r0 8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8> 800048a: 1879 adds r1, r7, r1 800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff 8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276> 8000492: 4589 cmp r9, r1 8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6> 8000496: eba1 0109 sub.w r1, r1, r9 800049a: fbb1 f9fe udiv r9, r1, lr 800049e: fb09 f804 mul.w r8, r9, r4 80004a2: fb0e 1119 mls r1, lr, r9, r1 80004a6: b292 uxth r2, r2 80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16 80004ac: 4542 cmp r2, r8 80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4> 80004b0: 18ba adds r2, r7, r2 80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff 80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222> 80004b8: 4542 cmp r2, r8 80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222> 80004bc: f1a9 0102 sub.w r1, r9, #2 80004c0: 443a add r2, r7 80004c2: e7be b.n 8000442 <__udivmoddi4+0x222> 80004c4: 45f0 cmp r8, lr 80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4> 80004c8: ebbe 0302 subs.w r3, lr, r2 80004cc: eb6c 0c07 sbc.w ip, ip, r7 80004d0: 3801 subs r0, #1 80004d2: 46e1 mov r9, ip 80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4> 80004d6: eba7 0909 sub.w r9, r7, r9 80004da: 4449 add r1, r9 80004dc: f1a8 0c02 sub.w ip, r8, #2 80004e0: fbb1 f9fe udiv r9, r1, lr 80004e4: fb09 f804 mul.w r8, r9, r4 80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282> 80004ea: 4673 mov r3, lr 80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce> 80004ee: 4650 mov r0, sl 80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0> 80004f2: 4608 mov r0, r1 80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2> 80004f6: 443b add r3, r7 80004f8: 3a02 subs r2, #2 80004fa: e733 b.n 8000364 <__udivmoddi4+0x144> 80004fc: f1ac 0c02 sub.w ip, ip, #2 8000500: 443b add r3, r7 8000502: e71c b.n 800033e <__udivmoddi4+0x11e> 8000504: 4649 mov r1, r9 8000506: e79c b.n 8000442 <__udivmoddi4+0x222> 8000508: eba1 0109 sub.w r1, r1, r9 800050c: 46c4 mov ip, r8 800050e: fbb1 f9fe udiv r9, r1, lr 8000512: fb09 f804 mul.w r8, r9, r4 8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282> 08000518 <__aeabi_idiv0>: 8000518: 4770 bx lr 800051a: bf00 nop 0800051c : #include #include "main.h" void breadboard(int DELAY_MS) { 800051c: b580 push {r7, lr} 800051e: b084 sub sp, #16 8000520: af00 add r7, sp, #0 8000522: 6078 str r0, [r7, #4] bool Purple = (HAL_GPIO_ReadPin(GPIOD, BTN_PRPL_Pin) == GPIO_PIN_SET); // PD5 8000524: 2120 movs r1, #32 8000526: 4819 ldr r0, [pc, #100] @ (800058c ) 8000528: f001 fd5c bl 8001fe4 800052c: 4603 mov r3, r0 800052e: 2b01 cmp r3, #1 8000530: bf0c ite eq 8000532: 2301 moveq r3, #1 8000534: 2300 movne r3, #0 8000536: 73fb strb r3, [r7, #15] bool Grey = (HAL_GPIO_ReadPin(GPIOD, BTN_GREY_Pin) == GPIO_PIN_SET); // PD7 8000538: 2180 movs r1, #128 @ 0x80 800053a: 4814 ldr r0, [pc, #80] @ (800058c ) 800053c: f001 fd52 bl 8001fe4 8000540: 4603 mov r3, r0 8000542: 2b01 cmp r3, #1 8000544: bf0c ite eq 8000546: 2301 moveq r3, #1 8000548: 2300 movne r3, #0 800054a: 73bb strb r3, [r7, #14] if (!Purple && !Grey) { 800054c: 7bfb ldrb r3, [r7, #15] 800054e: f083 0301 eor.w r3, r3, #1 8000552: b2db uxtb r3, r3 8000554: 2b00 cmp r3, #0 8000556: d00b beq.n 8000570 8000558: 7bbb ldrb r3, [r7, #14] 800055a: f083 0301 eor.w r3, r3, #1 800055e: b2db uxtb r3, r3 8000560: 2b00 cmp r3, #0 8000562: d005 beq.n 8000570 HAL_GPIO_WritePin(GPIOB, LED_EXT_Pin, GPIO_PIN_SET); // PB4 8000564: 2201 movs r2, #1 8000566: 2110 movs r1, #16 8000568: 4809 ldr r0, [pc, #36] @ (8000590 ) 800056a: f001 fd53 bl 8002014 800056e: e004 b.n 800057a } else { HAL_GPIO_WritePin(GPIOB, LED_EXT_Pin, GPIO_PIN_RESET); // PB4 8000570: 2200 movs r2, #0 8000572: 2110 movs r1, #16 8000574: 4806 ldr r0, [pc, #24] @ (8000590 ) 8000576: f001 fd4d bl 8002014 } HAL_Delay(DELAY_MS); // milliseconds of delay after execution 800057a: 687b ldr r3, [r7, #4] 800057c: 4618 mov r0, r3 800057e: f001 f877 bl 8001670 HAL_GPIO_WritePin(GPIOB, LED_EXT_Pin, GPIO_PIN_SET); // PB4 ON HAL_Delay(DELAY_MS); HAL_GPIO_WritePin(GPIOB, LED_EXT_Pin, GPIO_PIN_RESET); // PB4 OFF HAL_Delay(DELAY_MS); */ } 8000582: bf00 nop 8000584: 3710 adds r7, #16 8000586: 46bd mov sp, r7 8000588: bd80 pop {r7, pc} 800058a: bf00 nop 800058c: 40020c00 .word 0x40020c00 8000590: 40020400 .word 0x40020400 08000594 : } /* USER CODE END 2 */ /* USER CODE BEGIN 4 */ __weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName) { 8000594: b480 push {r7} 8000596: b083 sub sp, #12 8000598: af00 add r7, sp, #0 800059a: 6078 str r0, [r7, #4] 800059c: 6039 str r1, [r7, #0] /* Run time stack overflow checking is performed if configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is called if a stack overflow is detected. */ } 800059e: bf00 nop 80005a0: 370c adds r7, #12 80005a2: 46bd mov sp, r7 80005a4: f85d 7b04 ldr.w r7, [sp], #4 80005a8: 4770 bx lr 080005aa
: /** * @brief The application entry point. * @retval int */ int main(void) { 80005aa: b580 push {r7, lr} 80005ac: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80005ae: f001 f81d bl 80015ec /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 80005b2: f000 f817 bl 80005e4 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 80005b6: f000 fa85 bl 8000ac4 MX_CRC_Init(); 80005ba: f000 f87d bl 80006b8 MX_DMA2D_Init(); 80005be: f000 f88f bl 80006e0 MX_FMC_Init(); 80005c2: f000 fa2f bl 8000a24 MX_I2C3_Init(); 80005c6: f000 f8bd bl 8000744 MX_LTDC_Init(); 80005ca: f000 f8fb bl 80007c4 MX_SPI5_Init(); 80005ce: f000 f979 bl 80008c4 MX_TIM1_Init(); 80005d2: f000 f9ad bl 8000930 MX_USART1_UART_Init(); 80005d6: f000 f9fb bl 80009d0 // Slowly blink built-in red light (test) //HAL_GPIO_TogglePin(LD4_GPIO_Port, LD4_Pin); //HAL_Delay(2000); // userloop pleeease breadboard(200); 80005da: 20c8 movs r0, #200 @ 0xc8 80005dc: f7ff ff9e bl 800051c { 80005e0: bf00 nop 80005e2: e7fa b.n 80005da 080005e4 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 80005e4: b580 push {r7, lr} 80005e6: b094 sub sp, #80 @ 0x50 80005e8: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80005ea: f107 0320 add.w r3, r7, #32 80005ee: 2230 movs r2, #48 @ 0x30 80005f0: 2100 movs r1, #0 80005f2: 4618 mov r0, r3 80005f4: f007 fc54 bl 8007ea0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 80005f8: f107 030c add.w r3, r7, #12 80005fc: 2200 movs r2, #0 80005fe: 601a str r2, [r3, #0] 8000600: 605a str r2, [r3, #4] 8000602: 609a str r2, [r3, #8] 8000604: 60da str r2, [r3, #12] 8000606: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); 8000608: 2300 movs r3, #0 800060a: 60bb str r3, [r7, #8] 800060c: 4b28 ldr r3, [pc, #160] @ (80006b0 ) 800060e: 6c1b ldr r3, [r3, #64] @ 0x40 8000610: 4a27 ldr r2, [pc, #156] @ (80006b0 ) 8000612: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000616: 6413 str r3, [r2, #64] @ 0x40 8000618: 4b25 ldr r3, [pc, #148] @ (80006b0 ) 800061a: 6c1b ldr r3, [r3, #64] @ 0x40 800061c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000620: 60bb str r3, [r7, #8] 8000622: 68bb ldr r3, [r7, #8] __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); 8000624: 2300 movs r3, #0 8000626: 607b str r3, [r7, #4] 8000628: 4b22 ldr r3, [pc, #136] @ (80006b4 ) 800062a: 681b ldr r3, [r3, #0] 800062c: f423 4340 bic.w r3, r3, #49152 @ 0xc000 8000630: 4a20 ldr r2, [pc, #128] @ (80006b4 ) 8000632: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000636: 6013 str r3, [r2, #0] 8000638: 4b1e ldr r3, [pc, #120] @ (80006b4 ) 800063a: 681b ldr r3, [r3, #0] 800063c: f403 4340 and.w r3, r3, #49152 @ 0xc000 8000640: 607b str r3, [r7, #4] 8000642: 687b ldr r3, [r7, #4] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 8000644: 2301 movs r3, #1 8000646: 623b str r3, [r7, #32] RCC_OscInitStruct.HSEState = RCC_HSE_ON; 8000648: f44f 3380 mov.w r3, #65536 @ 0x10000 800064c: 627b str r3, [r7, #36] @ 0x24 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 800064e: 2302 movs r3, #2 8000650: 63bb str r3, [r7, #56] @ 0x38 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 8000652: f44f 0380 mov.w r3, #4194304 @ 0x400000 8000656: 63fb str r3, [r7, #60] @ 0x3c RCC_OscInitStruct.PLL.PLLM = 4; 8000658: 2304 movs r3, #4 800065a: 643b str r3, [r7, #64] @ 0x40 RCC_OscInitStruct.PLL.PLLN = 72; 800065c: 2348 movs r3, #72 @ 0x48 800065e: 647b str r3, [r7, #68] @ 0x44 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 8000660: 2302 movs r3, #2 8000662: 64bb str r3, [r7, #72] @ 0x48 RCC_OscInitStruct.PLL.PLLQ = 3; 8000664: 2303 movs r3, #3 8000666: 64fb str r3, [r7, #76] @ 0x4c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8000668: f107 0320 add.w r3, r7, #32 800066c: 4618 mov r0, r3 800066e: f003 ff61 bl 8004534 8000672: 4603 mov r3, r0 8000674: 2b00 cmp r3, #0 8000676: d001 beq.n 800067c { Error_Handler(); 8000678: f000 fb58 bl 8000d2c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 800067c: 230f movs r3, #15 800067e: 60fb str r3, [r7, #12] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 8000680: 2302 movs r3, #2 8000682: 613b str r3, [r7, #16] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8000684: 2300 movs r3, #0 8000686: 617b str r3, [r7, #20] RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 8000688: f44f 5380 mov.w r3, #4096 @ 0x1000 800068c: 61bb str r3, [r7, #24] RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 800068e: 2300 movs r3, #0 8000690: 61fb str r3, [r7, #28] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 8000692: f107 030c add.w r3, r7, #12 8000696: 2102 movs r1, #2 8000698: 4618 mov r0, r3 800069a: f004 f9c3 bl 8004a24 800069e: 4603 mov r3, r0 80006a0: 2b00 cmp r3, #0 80006a2: d001 beq.n 80006a8 { Error_Handler(); 80006a4: f000 fb42 bl 8000d2c } } 80006a8: bf00 nop 80006aa: 3750 adds r7, #80 @ 0x50 80006ac: 46bd mov sp, r7 80006ae: bd80 pop {r7, pc} 80006b0: 40023800 .word 0x40023800 80006b4: 40007000 .word 0x40007000 080006b8 : * @brief CRC Initialization Function * @param None * @retval None */ static void MX_CRC_Init(void) { 80006b8: b580 push {r7, lr} 80006ba: af00 add r7, sp, #0 /* USER CODE END CRC_Init 0 */ /* USER CODE BEGIN CRC_Init 1 */ /* USER CODE END CRC_Init 1 */ hcrc.Instance = CRC; 80006bc: 4b06 ldr r3, [pc, #24] @ (80006d8 ) 80006be: 4a07 ldr r2, [pc, #28] @ (80006dc ) 80006c0: 601a str r2, [r3, #0] if (HAL_CRC_Init(&hcrc) != HAL_OK) 80006c2: 4805 ldr r0, [pc, #20] @ (80006d8 ) 80006c4: f001 f8da bl 800187c 80006c8: 4603 mov r3, r0 80006ca: 2b00 cmp r3, #0 80006cc: d001 beq.n 80006d2 { Error_Handler(); 80006ce: f000 fb2d bl 8000d2c } /* USER CODE BEGIN CRC_Init 2 */ /* USER CODE END CRC_Init 2 */ } 80006d2: bf00 nop 80006d4: bd80 pop {r7, pc} 80006d6: bf00 nop 80006d8: 2000002c .word 0x2000002c 80006dc: 40023000 .word 0x40023000 080006e0 : * @brief DMA2D Initialization Function * @param None * @retval None */ static void MX_DMA2D_Init(void) { 80006e0: b580 push {r7, lr} 80006e2: af00 add r7, sp, #0 /* USER CODE END DMA2D_Init 0 */ /* USER CODE BEGIN DMA2D_Init 1 */ /* USER CODE END DMA2D_Init 1 */ hdma2d.Instance = DMA2D; 80006e4: 4b15 ldr r3, [pc, #84] @ (800073c ) 80006e6: 4a16 ldr r2, [pc, #88] @ (8000740 ) 80006e8: 601a str r2, [r3, #0] hdma2d.Init.Mode = DMA2D_M2M; 80006ea: 4b14 ldr r3, [pc, #80] @ (800073c ) 80006ec: 2200 movs r2, #0 80006ee: 605a str r2, [r3, #4] hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888; 80006f0: 4b12 ldr r3, [pc, #72] @ (800073c ) 80006f2: 2200 movs r2, #0 80006f4: 609a str r2, [r3, #8] hdma2d.Init.OutputOffset = 0; 80006f6: 4b11 ldr r3, [pc, #68] @ (800073c ) 80006f8: 2200 movs r2, #0 80006fa: 60da str r2, [r3, #12] hdma2d.LayerCfg[1].InputOffset = 0; 80006fc: 4b0f ldr r3, [pc, #60] @ (800073c ) 80006fe: 2200 movs r2, #0 8000700: 629a str r2, [r3, #40] @ 0x28 hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888; 8000702: 4b0e ldr r3, [pc, #56] @ (800073c ) 8000704: 2200 movs r2, #0 8000706: 62da str r2, [r3, #44] @ 0x2c hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA; 8000708: 4b0c ldr r3, [pc, #48] @ (800073c ) 800070a: 2200 movs r2, #0 800070c: 631a str r2, [r3, #48] @ 0x30 hdma2d.LayerCfg[1].InputAlpha = 0; 800070e: 4b0b ldr r3, [pc, #44] @ (800073c ) 8000710: 2200 movs r2, #0 8000712: 635a str r2, [r3, #52] @ 0x34 if (HAL_DMA2D_Init(&hdma2d) != HAL_OK) 8000714: 4809 ldr r0, [pc, #36] @ (800073c ) 8000716: f001 f8cd bl 80018b4 800071a: 4603 mov r3, r0 800071c: 2b00 cmp r3, #0 800071e: d001 beq.n 8000724 { Error_Handler(); 8000720: f000 fb04 bl 8000d2c } if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK) 8000724: 2101 movs r1, #1 8000726: 4805 ldr r0, [pc, #20] @ (800073c ) 8000728: f001 fa1e bl 8001b68 800072c: 4603 mov r3, r0 800072e: 2b00 cmp r3, #0 8000730: d001 beq.n 8000736 { Error_Handler(); 8000732: f000 fafb bl 8000d2c } /* USER CODE BEGIN DMA2D_Init 2 */ /* USER CODE END DMA2D_Init 2 */ } 8000736: bf00 nop 8000738: bd80 pop {r7, pc} 800073a: bf00 nop 800073c: 20000034 .word 0x20000034 8000740: 4002b000 .word 0x4002b000 08000744 : * @brief I2C3 Initialization Function * @param None * @retval None */ static void MX_I2C3_Init(void) { 8000744: b580 push {r7, lr} 8000746: af00 add r7, sp, #0 /* USER CODE END I2C3_Init 0 */ /* USER CODE BEGIN I2C3_Init 1 */ /* USER CODE END I2C3_Init 1 */ hi2c3.Instance = I2C3; 8000748: 4b1b ldr r3, [pc, #108] @ (80007b8 ) 800074a: 4a1c ldr r2, [pc, #112] @ (80007bc ) 800074c: 601a str r2, [r3, #0] hi2c3.Init.ClockSpeed = 100000; 800074e: 4b1a ldr r3, [pc, #104] @ (80007b8 ) 8000750: 4a1b ldr r2, [pc, #108] @ (80007c0 ) 8000752: 605a str r2, [r3, #4] hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2; 8000754: 4b18 ldr r3, [pc, #96] @ (80007b8 ) 8000756: 2200 movs r2, #0 8000758: 609a str r2, [r3, #8] hi2c3.Init.OwnAddress1 = 0; 800075a: 4b17 ldr r3, [pc, #92] @ (80007b8 ) 800075c: 2200 movs r2, #0 800075e: 60da str r2, [r3, #12] hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; 8000760: 4b15 ldr r3, [pc, #84] @ (80007b8 ) 8000762: f44f 4280 mov.w r2, #16384 @ 0x4000 8000766: 611a str r2, [r3, #16] hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; 8000768: 4b13 ldr r3, [pc, #76] @ (80007b8 ) 800076a: 2200 movs r2, #0 800076c: 615a str r2, [r3, #20] hi2c3.Init.OwnAddress2 = 0; 800076e: 4b12 ldr r3, [pc, #72] @ (80007b8 ) 8000770: 2200 movs r2, #0 8000772: 619a str r2, [r3, #24] hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; 8000774: 4b10 ldr r3, [pc, #64] @ (80007b8 ) 8000776: 2200 movs r2, #0 8000778: 61da str r2, [r3, #28] hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; 800077a: 4b0f ldr r3, [pc, #60] @ (80007b8 ) 800077c: 2200 movs r2, #0 800077e: 621a str r2, [r3, #32] if (HAL_I2C_Init(&hi2c3) != HAL_OK) 8000780: 480d ldr r0, [pc, #52] @ (80007b8 ) 8000782: f003 fa07 bl 8003b94 8000786: 4603 mov r3, r0 8000788: 2b00 cmp r3, #0 800078a: d001 beq.n 8000790 { Error_Handler(); 800078c: f000 face bl 8000d2c } /** Configure Analogue filter */ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK) 8000790: 2100 movs r1, #0 8000792: 4809 ldr r0, [pc, #36] @ (80007b8 ) 8000794: f003 fb42 bl 8003e1c 8000798: 4603 mov r3, r0 800079a: 2b00 cmp r3, #0 800079c: d001 beq.n 80007a2 { Error_Handler(); 800079e: f000 fac5 bl 8000d2c } /** Configure Digital filter */ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK) 80007a2: 2100 movs r1, #0 80007a4: 4804 ldr r0, [pc, #16] @ (80007b8 ) 80007a6: f003 fb75 bl 8003e94 80007aa: 4603 mov r3, r0 80007ac: 2b00 cmp r3, #0 80007ae: d001 beq.n 80007b4 { Error_Handler(); 80007b0: f000 fabc bl 8000d2c } /* USER CODE BEGIN I2C3_Init 2 */ /* USER CODE END I2C3_Init 2 */ } 80007b4: bf00 nop 80007b6: bd80 pop {r7, pc} 80007b8: 20000074 .word 0x20000074 80007bc: 40005c00 .word 0x40005c00 80007c0: 000186a0 .word 0x000186a0 080007c4 : * @brief LTDC Initialization Function * @param None * @retval None */ static void MX_LTDC_Init(void) { 80007c4: b580 push {r7, lr} 80007c6: b08e sub sp, #56 @ 0x38 80007c8: af00 add r7, sp, #0 /* USER CODE BEGIN LTDC_Init 0 */ /* USER CODE END LTDC_Init 0 */ LTDC_LayerCfgTypeDef pLayerCfg = {0}; 80007ca: 1d3b adds r3, r7, #4 80007cc: 2234 movs r2, #52 @ 0x34 80007ce: 2100 movs r1, #0 80007d0: 4618 mov r0, r3 80007d2: f007 fb65 bl 8007ea0 /* USER CODE BEGIN LTDC_Init 1 */ /* USER CODE END LTDC_Init 1 */ hltdc.Instance = LTDC; 80007d6: 4b39 ldr r3, [pc, #228] @ (80008bc ) 80007d8: 4a39 ldr r2, [pc, #228] @ (80008c0 ) 80007da: 601a str r2, [r3, #0] hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; 80007dc: 4b37 ldr r3, [pc, #220] @ (80008bc ) 80007de: 2200 movs r2, #0 80007e0: 605a str r2, [r3, #4] hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; 80007e2: 4b36 ldr r3, [pc, #216] @ (80008bc ) 80007e4: 2200 movs r2, #0 80007e6: 609a str r2, [r3, #8] hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; 80007e8: 4b34 ldr r3, [pc, #208] @ (80008bc ) 80007ea: 2200 movs r2, #0 80007ec: 60da str r2, [r3, #12] hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; 80007ee: 4b33 ldr r3, [pc, #204] @ (80008bc ) 80007f0: 2200 movs r2, #0 80007f2: 611a str r2, [r3, #16] hltdc.Init.HorizontalSync = 9; 80007f4: 4b31 ldr r3, [pc, #196] @ (80008bc ) 80007f6: 2209 movs r2, #9 80007f8: 615a str r2, [r3, #20] hltdc.Init.VerticalSync = 1; 80007fa: 4b30 ldr r3, [pc, #192] @ (80008bc ) 80007fc: 2201 movs r2, #1 80007fe: 619a str r2, [r3, #24] hltdc.Init.AccumulatedHBP = 29; 8000800: 4b2e ldr r3, [pc, #184] @ (80008bc ) 8000802: 221d movs r2, #29 8000804: 61da str r2, [r3, #28] hltdc.Init.AccumulatedVBP = 3; 8000806: 4b2d ldr r3, [pc, #180] @ (80008bc ) 8000808: 2203 movs r2, #3 800080a: 621a str r2, [r3, #32] hltdc.Init.AccumulatedActiveW = 269; 800080c: 4b2b ldr r3, [pc, #172] @ (80008bc ) 800080e: f240 120d movw r2, #269 @ 0x10d 8000812: 625a str r2, [r3, #36] @ 0x24 hltdc.Init.AccumulatedActiveH = 323; 8000814: 4b29 ldr r3, [pc, #164] @ (80008bc ) 8000816: f240 1243 movw r2, #323 @ 0x143 800081a: 629a str r2, [r3, #40] @ 0x28 hltdc.Init.TotalWidth = 279; 800081c: 4b27 ldr r3, [pc, #156] @ (80008bc ) 800081e: f240 1217 movw r2, #279 @ 0x117 8000822: 62da str r2, [r3, #44] @ 0x2c hltdc.Init.TotalHeigh = 327; 8000824: 4b25 ldr r3, [pc, #148] @ (80008bc ) 8000826: f240 1247 movw r2, #327 @ 0x147 800082a: 631a str r2, [r3, #48] @ 0x30 hltdc.Init.Backcolor.Blue = 0; 800082c: 4b23 ldr r3, [pc, #140] @ (80008bc ) 800082e: 2200 movs r2, #0 8000830: f883 2034 strb.w r2, [r3, #52] @ 0x34 hltdc.Init.Backcolor.Green = 0; 8000834: 4b21 ldr r3, [pc, #132] @ (80008bc ) 8000836: 2200 movs r2, #0 8000838: f883 2035 strb.w r2, [r3, #53] @ 0x35 hltdc.Init.Backcolor.Red = 0; 800083c: 4b1f ldr r3, [pc, #124] @ (80008bc ) 800083e: 2200 movs r2, #0 8000840: f883 2036 strb.w r2, [r3, #54] @ 0x36 if (HAL_LTDC_Init(&hltdc) != HAL_OK) 8000844: 481d ldr r0, [pc, #116] @ (80008bc ) 8000846: f003 fb64 bl 8003f12 800084a: 4603 mov r3, r0 800084c: 2b00 cmp r3, #0 800084e: d001 beq.n 8000854 { Error_Handler(); 8000850: f000 fa6c bl 8000d2c } pLayerCfg.WindowX0 = 0; 8000854: 2300 movs r3, #0 8000856: 607b str r3, [r7, #4] pLayerCfg.WindowX1 = 240; 8000858: 23f0 movs r3, #240 @ 0xf0 800085a: 60bb str r3, [r7, #8] pLayerCfg.WindowY0 = 0; 800085c: 2300 movs r3, #0 800085e: 60fb str r3, [r7, #12] pLayerCfg.WindowY1 = 320; 8000860: f44f 73a0 mov.w r3, #320 @ 0x140 8000864: 613b str r3, [r7, #16] pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565; 8000866: 2302 movs r3, #2 8000868: 617b str r3, [r7, #20] pLayerCfg.Alpha = 255; 800086a: 23ff movs r3, #255 @ 0xff 800086c: 61bb str r3, [r7, #24] pLayerCfg.Alpha0 = 0; 800086e: 2300 movs r3, #0 8000870: 61fb str r3, [r7, #28] pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; 8000872: f44f 63c0 mov.w r3, #1536 @ 0x600 8000876: 623b str r3, [r7, #32] pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; 8000878: 2307 movs r3, #7 800087a: 627b str r3, [r7, #36] @ 0x24 pLayerCfg.FBStartAdress = 0xD0000000; 800087c: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000 8000880: 62bb str r3, [r7, #40] @ 0x28 pLayerCfg.ImageWidth = 240; 8000882: 23f0 movs r3, #240 @ 0xf0 8000884: 62fb str r3, [r7, #44] @ 0x2c pLayerCfg.ImageHeight = 320; 8000886: f44f 73a0 mov.w r3, #320 @ 0x140 800088a: 633b str r3, [r7, #48] @ 0x30 pLayerCfg.Backcolor.Blue = 0; 800088c: 2300 movs r3, #0 800088e: f887 3034 strb.w r3, [r7, #52] @ 0x34 pLayerCfg.Backcolor.Green = 0; 8000892: 2300 movs r3, #0 8000894: f887 3035 strb.w r3, [r7, #53] @ 0x35 pLayerCfg.Backcolor.Red = 0; 8000898: 2300 movs r3, #0 800089a: f887 3036 strb.w r3, [r7, #54] @ 0x36 if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) 800089e: 1d3b adds r3, r7, #4 80008a0: 2200 movs r2, #0 80008a2: 4619 mov r1, r3 80008a4: 4805 ldr r0, [pc, #20] @ (80008bc ) 80008a6: f003 fc93 bl 80041d0 80008aa: 4603 mov r3, r0 80008ac: 2b00 cmp r3, #0 80008ae: d001 beq.n 80008b4 { Error_Handler(); 80008b0: f000 fa3c bl 8000d2c } /* USER CODE BEGIN LTDC_Init 2 */ /* USER CODE END LTDC_Init 2 */ } 80008b4: bf00 nop 80008b6: 3738 adds r7, #56 @ 0x38 80008b8: 46bd mov sp, r7 80008ba: bd80 pop {r7, pc} 80008bc: 200000c8 .word 0x200000c8 80008c0: 40016800 .word 0x40016800 080008c4 : * @brief SPI5 Initialization Function * @param None * @retval None */ static void MX_SPI5_Init(void) { 80008c4: b580 push {r7, lr} 80008c6: af00 add r7, sp, #0 /* USER CODE BEGIN SPI5_Init 1 */ /* USER CODE END SPI5_Init 1 */ /* SPI5 parameter configuration*/ hspi5.Instance = SPI5; 80008c8: 4b17 ldr r3, [pc, #92] @ (8000928 ) 80008ca: 4a18 ldr r2, [pc, #96] @ (800092c ) 80008cc: 601a str r2, [r3, #0] hspi5.Init.Mode = SPI_MODE_MASTER; 80008ce: 4b16 ldr r3, [pc, #88] @ (8000928 ) 80008d0: f44f 7282 mov.w r2, #260 @ 0x104 80008d4: 605a str r2, [r3, #4] hspi5.Init.Direction = SPI_DIRECTION_2LINES; 80008d6: 4b14 ldr r3, [pc, #80] @ (8000928 ) 80008d8: 2200 movs r2, #0 80008da: 609a str r2, [r3, #8] hspi5.Init.DataSize = SPI_DATASIZE_8BIT; 80008dc: 4b12 ldr r3, [pc, #72] @ (8000928 ) 80008de: 2200 movs r2, #0 80008e0: 60da str r2, [r3, #12] hspi5.Init.CLKPolarity = SPI_POLARITY_LOW; 80008e2: 4b11 ldr r3, [pc, #68] @ (8000928 ) 80008e4: 2200 movs r2, #0 80008e6: 611a str r2, [r3, #16] hspi5.Init.CLKPhase = SPI_PHASE_1EDGE; 80008e8: 4b0f ldr r3, [pc, #60] @ (8000928 ) 80008ea: 2200 movs r2, #0 80008ec: 615a str r2, [r3, #20] hspi5.Init.NSS = SPI_NSS_SOFT; 80008ee: 4b0e ldr r3, [pc, #56] @ (8000928 ) 80008f0: f44f 7200 mov.w r2, #512 @ 0x200 80008f4: 619a str r2, [r3, #24] hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; 80008f6: 4b0c ldr r3, [pc, #48] @ (8000928 ) 80008f8: 2218 movs r2, #24 80008fa: 61da str r2, [r3, #28] hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB; 80008fc: 4b0a ldr r3, [pc, #40] @ (8000928 ) 80008fe: 2200 movs r2, #0 8000900: 621a str r2, [r3, #32] hspi5.Init.TIMode = SPI_TIMODE_DISABLE; 8000902: 4b09 ldr r3, [pc, #36] @ (8000928 ) 8000904: 2200 movs r2, #0 8000906: 625a str r2, [r3, #36] @ 0x24 hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 8000908: 4b07 ldr r3, [pc, #28] @ (8000928 ) 800090a: 2200 movs r2, #0 800090c: 629a str r2, [r3, #40] @ 0x28 hspi5.Init.CRCPolynomial = 10; 800090e: 4b06 ldr r3, [pc, #24] @ (8000928 ) 8000910: 220a movs r2, #10 8000912: 62da str r2, [r3, #44] @ 0x2c if (HAL_SPI_Init(&hspi5) != HAL_OK) 8000914: 4804 ldr r0, [pc, #16] @ (8000928 ) 8000916: f004 fccb bl 80052b0 800091a: 4603 mov r3, r0 800091c: 2b00 cmp r3, #0 800091e: d001 beq.n 8000924 { Error_Handler(); 8000920: f000 fa04 bl 8000d2c } /* USER CODE BEGIN SPI5_Init 2 */ /* USER CODE END SPI5_Init 2 */ } 8000924: bf00 nop 8000926: bd80 pop {r7, pc} 8000928: 20000170 .word 0x20000170 800092c: 40015000 .word 0x40015000 08000930 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 8000930: b580 push {r7, lr} 8000932: b086 sub sp, #24 8000934: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 8000936: f107 0308 add.w r3, r7, #8 800093a: 2200 movs r2, #0 800093c: 601a str r2, [r3, #0] 800093e: 605a str r2, [r3, #4] 8000940: 609a str r2, [r3, #8] 8000942: 60da str r2, [r3, #12] TIM_MasterConfigTypeDef sMasterConfig = {0}; 8000944: 463b mov r3, r7 8000946: 2200 movs r2, #0 8000948: 601a str r2, [r3, #0] 800094a: 605a str r2, [r3, #4] /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 800094c: 4b1e ldr r3, [pc, #120] @ (80009c8 ) 800094e: 4a1f ldr r2, [pc, #124] @ (80009cc ) 8000950: 601a str r2, [r3, #0] htim1.Init.Prescaler = 0; 8000952: 4b1d ldr r3, [pc, #116] @ (80009c8 ) 8000954: 2200 movs r2, #0 8000956: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8000958: 4b1b ldr r3, [pc, #108] @ (80009c8 ) 800095a: 2200 movs r2, #0 800095c: 609a str r2, [r3, #8] htim1.Init.Period = 65535; 800095e: 4b1a ldr r3, [pc, #104] @ (80009c8 ) 8000960: f64f 72ff movw r2, #65535 @ 0xffff 8000964: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8000966: 4b18 ldr r3, [pc, #96] @ (80009c8 ) 8000968: 2200 movs r2, #0 800096a: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 800096c: 4b16 ldr r3, [pc, #88] @ (80009c8 ) 800096e: 2200 movs r2, #0 8000970: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8000972: 4b15 ldr r3, [pc, #84] @ (80009c8 ) 8000974: 2200 movs r2, #0 8000976: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8000978: 4813 ldr r0, [pc, #76] @ (80009c8 ) 800097a: f004 fd22 bl 80053c2 800097e: 4603 mov r3, r0 8000980: 2b00 cmp r3, #0 8000982: d001 beq.n 8000988 { Error_Handler(); 8000984: f000 f9d2 bl 8000d2c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8000988: f44f 5380 mov.w r3, #4096 @ 0x1000 800098c: 60bb str r3, [r7, #8] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 800098e: f107 0308 add.w r3, r7, #8 8000992: 4619 mov r1, r3 8000994: 480c ldr r0, [pc, #48] @ (80009c8 ) 8000996: f004 fec3 bl 8005720 800099a: 4603 mov r3, r0 800099c: 2b00 cmp r3, #0 800099e: d001 beq.n 80009a4 { Error_Handler(); 80009a0: f000 f9c4 bl 8000d2c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80009a4: 2300 movs r3, #0 80009a6: 603b str r3, [r7, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80009a8: 2300 movs r3, #0 80009aa: 607b str r3, [r7, #4] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 80009ac: 463b mov r3, r7 80009ae: 4619 mov r1, r3 80009b0: 4805 ldr r0, [pc, #20] @ (80009c8 ) 80009b2: f005 f8e5 bl 8005b80 80009b6: 4603 mov r3, r0 80009b8: 2b00 cmp r3, #0 80009ba: d001 beq.n 80009c0 { Error_Handler(); 80009bc: f000 f9b6 bl 8000d2c } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ } 80009c0: bf00 nop 80009c2: 3718 adds r7, #24 80009c4: 46bd mov sp, r7 80009c6: bd80 pop {r7, pc} 80009c8: 200001c8 .word 0x200001c8 80009cc: 40010000 .word 0x40010000 080009d0 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 80009d0: b580 push {r7, lr} 80009d2: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 80009d4: 4b11 ldr r3, [pc, #68] @ (8000a1c ) 80009d6: 4a12 ldr r2, [pc, #72] @ (8000a20 ) 80009d8: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 80009da: 4b10 ldr r3, [pc, #64] @ (8000a1c ) 80009dc: f44f 32e1 mov.w r2, #115200 @ 0x1c200 80009e0: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 80009e2: 4b0e ldr r3, [pc, #56] @ (8000a1c ) 80009e4: 2200 movs r2, #0 80009e6: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80009e8: 4b0c ldr r3, [pc, #48] @ (8000a1c ) 80009ea: 2200 movs r2, #0 80009ec: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80009ee: 4b0b ldr r3, [pc, #44] @ (8000a1c ) 80009f0: 2200 movs r2, #0 80009f2: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80009f4: 4b09 ldr r3, [pc, #36] @ (8000a1c ) 80009f6: 220c movs r2, #12 80009f8: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80009fa: 4b08 ldr r3, [pc, #32] @ (8000a1c ) 80009fc: 2200 movs r2, #0 80009fe: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 8000a00: 4b06 ldr r3, [pc, #24] @ (8000a1c ) 8000a02: 2200 movs r2, #0 8000a04: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart1) != HAL_OK) 8000a06: 4805 ldr r0, [pc, #20] @ (8000a1c ) 8000a08: f005 f94a bl 8005ca0 8000a0c: 4603 mov r3, r0 8000a0e: 2b00 cmp r3, #0 8000a10: d001 beq.n 8000a16 { Error_Handler(); 8000a12: f000 f98b bl 8000d2c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8000a16: bf00 nop 8000a18: bd80 pop {r7, pc} 8000a1a: bf00 nop 8000a1c: 20000210 .word 0x20000210 8000a20: 40011000 .word 0x40011000 08000a24 : /* FMC initialization function */ static void MX_FMC_Init(void) { 8000a24: b580 push {r7, lr} 8000a26: b088 sub sp, #32 8000a28: af00 add r7, sp, #0 /* USER CODE BEGIN FMC_Init 0 */ /* USER CODE END FMC_Init 0 */ FMC_SDRAM_TimingTypeDef SdramTiming = {0}; 8000a2a: 1d3b adds r3, r7, #4 8000a2c: 2200 movs r2, #0 8000a2e: 601a str r2, [r3, #0] 8000a30: 605a str r2, [r3, #4] 8000a32: 609a str r2, [r3, #8] 8000a34: 60da str r2, [r3, #12] 8000a36: 611a str r2, [r3, #16] 8000a38: 615a str r2, [r3, #20] 8000a3a: 619a str r2, [r3, #24] /* USER CODE END FMC_Init 1 */ /** Perform the SDRAM1 memory initialization sequence */ hsdram1.Instance = FMC_SDRAM_DEVICE; 8000a3c: 4b1f ldr r3, [pc, #124] @ (8000abc ) 8000a3e: 4a20 ldr r2, [pc, #128] @ (8000ac0 ) 8000a40: 601a str r2, [r3, #0] /* hsdram1.Init */ hsdram1.Init.SDBank = FMC_SDRAM_BANK2; 8000a42: 4b1e ldr r3, [pc, #120] @ (8000abc ) 8000a44: 2201 movs r2, #1 8000a46: 605a str r2, [r3, #4] hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; 8000a48: 4b1c ldr r3, [pc, #112] @ (8000abc ) 8000a4a: 2200 movs r2, #0 8000a4c: 609a str r2, [r3, #8] hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; 8000a4e: 4b1b ldr r3, [pc, #108] @ (8000abc ) 8000a50: 2204 movs r2, #4 8000a52: 60da str r2, [r3, #12] hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16; 8000a54: 4b19 ldr r3, [pc, #100] @ (8000abc ) 8000a56: 2210 movs r2, #16 8000a58: 611a str r2, [r3, #16] hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 8000a5a: 4b18 ldr r3, [pc, #96] @ (8000abc ) 8000a5c: 2240 movs r2, #64 @ 0x40 8000a5e: 615a str r2, [r3, #20] hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; 8000a60: 4b16 ldr r3, [pc, #88] @ (8000abc ) 8000a62: f44f 72c0 mov.w r2, #384 @ 0x180 8000a66: 619a str r2, [r3, #24] hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 8000a68: 4b14 ldr r3, [pc, #80] @ (8000abc ) 8000a6a: 2200 movs r2, #0 8000a6c: 61da str r2, [r3, #28] hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; 8000a6e: 4b13 ldr r3, [pc, #76] @ (8000abc ) 8000a70: f44f 6200 mov.w r2, #2048 @ 0x800 8000a74: 621a str r2, [r3, #32] hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; 8000a76: 4b11 ldr r3, [pc, #68] @ (8000abc ) 8000a78: 2200 movs r2, #0 8000a7a: 625a str r2, [r3, #36] @ 0x24 hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; 8000a7c: 4b0f ldr r3, [pc, #60] @ (8000abc ) 8000a7e: f44f 5200 mov.w r2, #8192 @ 0x2000 8000a82: 629a str r2, [r3, #40] @ 0x28 /* SdramTiming */ SdramTiming.LoadToActiveDelay = 2; 8000a84: 2302 movs r3, #2 8000a86: 607b str r3, [r7, #4] SdramTiming.ExitSelfRefreshDelay = 7; 8000a88: 2307 movs r3, #7 8000a8a: 60bb str r3, [r7, #8] SdramTiming.SelfRefreshTime = 4; 8000a8c: 2304 movs r3, #4 8000a8e: 60fb str r3, [r7, #12] SdramTiming.RowCycleDelay = 7; 8000a90: 2307 movs r3, #7 8000a92: 613b str r3, [r7, #16] SdramTiming.WriteRecoveryTime = 3; 8000a94: 2303 movs r3, #3 8000a96: 617b str r3, [r7, #20] SdramTiming.RPDelay = 2; 8000a98: 2302 movs r3, #2 8000a9a: 61bb str r3, [r7, #24] SdramTiming.RCDDelay = 2; 8000a9c: 2302 movs r3, #2 8000a9e: 61fb str r3, [r7, #28] if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) 8000aa0: 1d3b adds r3, r7, #4 8000aa2: 4619 mov r1, r3 8000aa4: 4805 ldr r0, [pc, #20] @ (8000abc ) 8000aa6: f004 fbcf bl 8005248 8000aaa: 4603 mov r3, r0 8000aac: 2b00 cmp r3, #0 8000aae: d001 beq.n 8000ab4 { Error_Handler( ); 8000ab0: f000 f93c bl 8000d2c } /* USER CODE BEGIN FMC_Init 2 */ /* USER CODE END FMC_Init 2 */ } 8000ab4: bf00 nop 8000ab6: 3720 adds r7, #32 8000ab8: 46bd mov sp, r7 8000aba: bd80 pop {r7, pc} 8000abc: 20000258 .word 0x20000258 8000ac0: a0000140 .word 0xa0000140 08000ac4 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8000ac4: b580 push {r7, lr} 8000ac6: b08e sub sp, #56 @ 0x38 8000ac8: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000aca: f107 0324 add.w r3, r7, #36 @ 0x24 8000ace: 2200 movs r2, #0 8000ad0: 601a str r2, [r3, #0] 8000ad2: 605a str r2, [r3, #4] 8000ad4: 609a str r2, [r3, #8] 8000ad6: 60da str r2, [r3, #12] 8000ad8: 611a str r2, [r3, #16] /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000ada: 2300 movs r3, #0 8000adc: 623b str r3, [r7, #32] 8000ade: 4b84 ldr r3, [pc, #528] @ (8000cf0 ) 8000ae0: 6b1b ldr r3, [r3, #48] @ 0x30 8000ae2: 4a83 ldr r2, [pc, #524] @ (8000cf0 ) 8000ae4: f043 0304 orr.w r3, r3, #4 8000ae8: 6313 str r3, [r2, #48] @ 0x30 8000aea: 4b81 ldr r3, [pc, #516] @ (8000cf0 ) 8000aec: 6b1b ldr r3, [r3, #48] @ 0x30 8000aee: f003 0304 and.w r3, r3, #4 8000af2: 623b str r3, [r7, #32] 8000af4: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000af6: 2300 movs r3, #0 8000af8: 61fb str r3, [r7, #28] 8000afa: 4b7d ldr r3, [pc, #500] @ (8000cf0 ) 8000afc: 6b1b ldr r3, [r3, #48] @ 0x30 8000afe: 4a7c ldr r2, [pc, #496] @ (8000cf0 ) 8000b00: f043 0320 orr.w r3, r3, #32 8000b04: 6313 str r3, [r2, #48] @ 0x30 8000b06: 4b7a ldr r3, [pc, #488] @ (8000cf0 ) 8000b08: 6b1b ldr r3, [r3, #48] @ 0x30 8000b0a: f003 0320 and.w r3, r3, #32 8000b0e: 61fb str r3, [r7, #28] 8000b10: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOH_CLK_ENABLE(); 8000b12: 2300 movs r3, #0 8000b14: 61bb str r3, [r7, #24] 8000b16: 4b76 ldr r3, [pc, #472] @ (8000cf0 ) 8000b18: 6b1b ldr r3, [r3, #48] @ 0x30 8000b1a: 4a75 ldr r2, [pc, #468] @ (8000cf0 ) 8000b1c: f043 0380 orr.w r3, r3, #128 @ 0x80 8000b20: 6313 str r3, [r2, #48] @ 0x30 8000b22: 4b73 ldr r3, [pc, #460] @ (8000cf0 ) 8000b24: 6b1b ldr r3, [r3, #48] @ 0x30 8000b26: f003 0380 and.w r3, r3, #128 @ 0x80 8000b2a: 61bb str r3, [r7, #24] 8000b2c: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000b2e: 2300 movs r3, #0 8000b30: 617b str r3, [r7, #20] 8000b32: 4b6f ldr r3, [pc, #444] @ (8000cf0 ) 8000b34: 6b1b ldr r3, [r3, #48] @ 0x30 8000b36: 4a6e ldr r2, [pc, #440] @ (8000cf0 ) 8000b38: f043 0301 orr.w r3, r3, #1 8000b3c: 6313 str r3, [r2, #48] @ 0x30 8000b3e: 4b6c ldr r3, [pc, #432] @ (8000cf0 ) 8000b40: 6b1b ldr r3, [r3, #48] @ 0x30 8000b42: f003 0301 and.w r3, r3, #1 8000b46: 617b str r3, [r7, #20] 8000b48: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000b4a: 2300 movs r3, #0 8000b4c: 613b str r3, [r7, #16] 8000b4e: 4b68 ldr r3, [pc, #416] @ (8000cf0 ) 8000b50: 6b1b ldr r3, [r3, #48] @ 0x30 8000b52: 4a67 ldr r2, [pc, #412] @ (8000cf0 ) 8000b54: f043 0302 orr.w r3, r3, #2 8000b58: 6313 str r3, [r2, #48] @ 0x30 8000b5a: 4b65 ldr r3, [pc, #404] @ (8000cf0 ) 8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30 8000b5e: f003 0302 and.w r3, r3, #2 8000b62: 613b str r3, [r7, #16] 8000b64: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000b66: 2300 movs r3, #0 8000b68: 60fb str r3, [r7, #12] 8000b6a: 4b61 ldr r3, [pc, #388] @ (8000cf0 ) 8000b6c: 6b1b ldr r3, [r3, #48] @ 0x30 8000b6e: 4a60 ldr r2, [pc, #384] @ (8000cf0 ) 8000b70: f043 0340 orr.w r3, r3, #64 @ 0x40 8000b74: 6313 str r3, [r2, #48] @ 0x30 8000b76: 4b5e ldr r3, [pc, #376] @ (8000cf0 ) 8000b78: 6b1b ldr r3, [r3, #48] @ 0x30 8000b7a: f003 0340 and.w r3, r3, #64 @ 0x40 8000b7e: 60fb str r3, [r7, #12] 8000b80: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOE_CLK_ENABLE(); 8000b82: 2300 movs r3, #0 8000b84: 60bb str r3, [r7, #8] 8000b86: 4b5a ldr r3, [pc, #360] @ (8000cf0 ) 8000b88: 6b1b ldr r3, [r3, #48] @ 0x30 8000b8a: 4a59 ldr r2, [pc, #356] @ (8000cf0 ) 8000b8c: f043 0310 orr.w r3, r3, #16 8000b90: 6313 str r3, [r2, #48] @ 0x30 8000b92: 4b57 ldr r3, [pc, #348] @ (8000cf0 ) 8000b94: 6b1b ldr r3, [r3, #48] @ 0x30 8000b96: f003 0310 and.w r3, r3, #16 8000b9a: 60bb str r3, [r7, #8] 8000b9c: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000b9e: 2300 movs r3, #0 8000ba0: 607b str r3, [r7, #4] 8000ba2: 4b53 ldr r3, [pc, #332] @ (8000cf0 ) 8000ba4: 6b1b ldr r3, [r3, #48] @ 0x30 8000ba6: 4a52 ldr r2, [pc, #328] @ (8000cf0 ) 8000ba8: f043 0308 orr.w r3, r3, #8 8000bac: 6313 str r3, [r2, #48] @ 0x30 8000bae: 4b50 ldr r3, [pc, #320] @ (8000cf0 ) 8000bb0: 6b1b ldr r3, [r3, #48] @ 0x30 8000bb2: f003 0308 and.w r3, r3, #8 8000bb6: 607b str r3, [r7, #4] 8000bb8: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET); 8000bba: 2200 movs r2, #0 8000bbc: 2116 movs r1, #22 8000bbe: 484d ldr r0, [pc, #308] @ (8000cf4 ) 8000bc0: f001 fa28 bl 8002014 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET); 8000bc4: 2200 movs r2, #0 8000bc6: 2180 movs r1, #128 @ 0x80 8000bc8: 484b ldr r0, [pc, #300] @ (8000cf8 ) 8000bca: f001 fa23 bl 8002014 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET); 8000bce: 2200 movs r2, #0 8000bd0: f44f 5140 mov.w r1, #12288 @ 0x3000 8000bd4: 4849 ldr r0, [pc, #292] @ (8000cfc ) 8000bd6: f001 fa1d bl 8002014 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET); 8000bda: 2200 movs r2, #0 8000bdc: f44f 41c0 mov.w r1, #24576 @ 0x6000 8000be0: 4847 ldr r0, [pc, #284] @ (8000d00 ) 8000be2: f001 fa17 bl 8002014 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LED_EXT_GPIO_Port, LED_EXT_Pin, GPIO_PIN_RESET); 8000be6: 2200 movs r2, #0 8000be8: 2110 movs r1, #16 8000bea: 4846 ldr r0, [pc, #280] @ (8000d04 ) 8000bec: f001 fa12 bl 8002014 /*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */ GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin; 8000bf0: 2316 movs r3, #22 8000bf2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000bf4: 2301 movs r3, #1 8000bf6: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000bf8: 2300 movs r3, #0 8000bfa: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000bfc: 2300 movs r3, #0 8000bfe: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8000c00: f107 0324 add.w r3, r7, #36 @ 0x24 8000c04: 4619 mov r1, r3 8000c06: 483b ldr r0, [pc, #236] @ (8000cf4 ) 8000c08: f001 f840 bl 8001c8c /*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */ GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin; 8000c0c: f248 0307 movw r3, #32775 @ 0x8007 8000c10: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; 8000c12: f44f 1390 mov.w r3, #1179648 @ 0x120000 8000c16: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c18: 2300 movs r3, #0 8000c1a: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8000c1c: f107 0324 add.w r3, r7, #36 @ 0x24 8000c20: 4619 mov r1, r3 8000c22: 4835 ldr r0, [pc, #212] @ (8000cf8 ) 8000c24: f001 f832 bl 8001c8c /*Configure GPIO pin : ACP_RST_Pin */ GPIO_InitStruct.Pin = ACP_RST_Pin; 8000c28: 2380 movs r3, #128 @ 0x80 8000c2a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c2c: 2301 movs r3, #1 8000c2e: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c30: 2300 movs r3, #0 8000c32: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c34: 2300 movs r3, #0 8000c36: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct); 8000c38: f107 0324 add.w r3, r7, #36 @ 0x24 8000c3c: 4619 mov r1, r3 8000c3e: 482e ldr r0, [pc, #184] @ (8000cf8 ) 8000c40: f001 f824 bl 8001c8c /*Configure GPIO pin : OTG_FS_OC_Pin */ GPIO_InitStruct.Pin = OTG_FS_OC_Pin; 8000c44: 2320 movs r3, #32 8000c46: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING; 8000c48: f44f 1390 mov.w r3, #1179648 @ 0x120000 8000c4c: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c4e: 2300 movs r3, #0 8000c50: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct); 8000c52: f107 0324 add.w r3, r7, #36 @ 0x24 8000c56: 4619 mov r1, r3 8000c58: 4826 ldr r0, [pc, #152] @ (8000cf4 ) 8000c5a: f001 f817 bl 8001c8c /*Configure GPIO pin : BOOT1_Pin */ GPIO_InitStruct.Pin = BOOT1_Pin; 8000c5e: 2304 movs r3, #4 8000c60: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000c62: 2300 movs r3, #0 8000c64: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c66: 2300 movs r3, #0 8000c68: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct); 8000c6a: f107 0324 add.w r3, r7, #36 @ 0x24 8000c6e: 4619 mov r1, r3 8000c70: 4824 ldr r0, [pc, #144] @ (8000d04 ) 8000c72: f001 f80b bl 8001c8c /*Configure GPIO pins : TE_Pin BTN_PRPL_Pin BTN_GREY_Pin */ GPIO_InitStruct.Pin = TE_Pin|BTN_PRPL_Pin|BTN_GREY_Pin; 8000c76: f44f 630a mov.w r3, #2208 @ 0x8a0 8000c7a: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 8000c7c: 2300 movs r3, #0 8000c7e: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c80: 2300 movs r3, #0 8000c82: 62fb str r3, [r7, #44] @ 0x2c HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000c84: f107 0324 add.w r3, r7, #36 @ 0x24 8000c88: 4619 mov r1, r3 8000c8a: 481c ldr r0, [pc, #112] @ (8000cfc ) 8000c8c: f000 fffe bl 8001c8c /*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */ GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin; 8000c90: f44f 5340 mov.w r3, #12288 @ 0x3000 8000c94: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000c96: 2301 movs r3, #1 8000c98: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000c9a: 2300 movs r3, #0 8000c9c: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000c9e: 2300 movs r3, #0 8000ca0: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 8000ca2: f107 0324 add.w r3, r7, #36 @ 0x24 8000ca6: 4619 mov r1, r3 8000ca8: 4814 ldr r0, [pc, #80] @ (8000cfc ) 8000caa: f000 ffef bl 8001c8c /*Configure GPIO pins : LD3_Pin LD4_Pin */ GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin; 8000cae: f44f 43c0 mov.w r3, #24576 @ 0x6000 8000cb2: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000cb4: 2301 movs r3, #1 8000cb6: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cb8: 2300 movs r3, #0 8000cba: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000cbc: 2300 movs r3, #0 8000cbe: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8000cc0: f107 0324 add.w r3, r7, #36 @ 0x24 8000cc4: 4619 mov r1, r3 8000cc6: 480e ldr r0, [pc, #56] @ (8000d00 ) 8000cc8: f000 ffe0 bl 8001c8c /*Configure GPIO pin : LED_EXT_Pin */ GPIO_InitStruct.Pin = LED_EXT_Pin; 8000ccc: 2310 movs r3, #16 8000cce: 627b str r3, [r7, #36] @ 0x24 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8000cd0: 2301 movs r3, #1 8000cd2: 62bb str r3, [r7, #40] @ 0x28 GPIO_InitStruct.Pull = GPIO_NOPULL; 8000cd4: 2300 movs r3, #0 8000cd6: 62fb str r3, [r7, #44] @ 0x2c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000cd8: 2300 movs r3, #0 8000cda: 633b str r3, [r7, #48] @ 0x30 HAL_GPIO_Init(LED_EXT_GPIO_Port, &GPIO_InitStruct); 8000cdc: f107 0324 add.w r3, r7, #36 @ 0x24 8000ce0: 4619 mov r1, r3 8000ce2: 4808 ldr r0, [pc, #32] @ (8000d04 ) 8000ce4: f000 ffd2 bl 8001c8c /* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */ } 8000ce8: bf00 nop 8000cea: 3738 adds r7, #56 @ 0x38 8000cec: 46bd mov sp, r7 8000cee: bd80 pop {r7, pc} 8000cf0: 40023800 .word 0x40023800 8000cf4: 40020800 .word 0x40020800 8000cf8: 40020000 .word 0x40020000 8000cfc: 40020c00 .word 0x40020c00 8000d00: 40021800 .word 0x40021800 8000d04: 40020400 .word 0x40020400 08000d08 : * a global variable "uwTick" used as application time base. * @param htim : TIM handle * @retval None */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 8000d08: b580 push {r7, lr} 8000d0a: b082 sub sp, #8 8000d0c: af00 add r7, sp, #0 8000d0e: 6078 str r0, [r7, #4] /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ if (htim->Instance == TIM6) 8000d10: 687b ldr r3, [r7, #4] 8000d12: 681b ldr r3, [r3, #0] 8000d14: 4a04 ldr r2, [pc, #16] @ (8000d28 ) 8000d16: 4293 cmp r3, r2 8000d18: d101 bne.n 8000d1e { HAL_IncTick(); 8000d1a: f000 fc89 bl 8001630 } /* USER CODE BEGIN Callback 1 */ /* USER CODE END Callback 1 */ } 8000d1e: bf00 nop 8000d20: 3708 adds r7, #8 8000d22: 46bd mov sp, r7 8000d24: bd80 pop {r7, pc} 8000d26: bf00 nop 8000d28: 40001000 .word 0x40001000 08000d2c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8000d2c: b480 push {r7} 8000d2e: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 8000d30: b672 cpsid i } 8000d32: bf00 nop /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8000d34: bf00 nop 8000d36: e7fd b.n 8000d34 08000d38 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8000d38: b580 push {r7, lr} 8000d3a: b082 sub sp, #8 8000d3c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000d3e: 2300 movs r3, #0 8000d40: 607b str r3, [r7, #4] 8000d42: 4b12 ldr r3, [pc, #72] @ (8000d8c ) 8000d44: 6c5b ldr r3, [r3, #68] @ 0x44 8000d46: 4a11 ldr r2, [pc, #68] @ (8000d8c ) 8000d48: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8000d4c: 6453 str r3, [r2, #68] @ 0x44 8000d4e: 4b0f ldr r3, [pc, #60] @ (8000d8c ) 8000d50: 6c5b ldr r3, [r3, #68] @ 0x44 8000d52: f403 4380 and.w r3, r3, #16384 @ 0x4000 8000d56: 607b str r3, [r7, #4] 8000d58: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8000d5a: 2300 movs r3, #0 8000d5c: 603b str r3, [r7, #0] 8000d5e: 4b0b ldr r3, [pc, #44] @ (8000d8c ) 8000d60: 6c1b ldr r3, [r3, #64] @ 0x40 8000d62: 4a0a ldr r2, [pc, #40] @ (8000d8c ) 8000d64: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8000d68: 6413 str r3, [r2, #64] @ 0x40 8000d6a: 4b08 ldr r3, [pc, #32] @ (8000d8c ) 8000d6c: 6c1b ldr r3, [r3, #64] @ 0x40 8000d6e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 8000d72: 603b str r3, [r7, #0] 8000d74: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); 8000d76: 2200 movs r2, #0 8000d78: 210f movs r1, #15 8000d7a: f06f 0001 mvn.w r0, #1 8000d7e: f000 fd53 bl 8001828 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8000d82: bf00 nop 8000d84: 3708 adds r7, #8 8000d86: 46bd mov sp, r7 8000d88: bd80 pop {r7, pc} 8000d8a: bf00 nop 8000d8c: 40023800 .word 0x40023800 08000d90 : * This function configures the hardware resources used in this example * @param hcrc: CRC handle pointer * @retval None */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { 8000d90: b480 push {r7} 8000d92: b085 sub sp, #20 8000d94: af00 add r7, sp, #0 8000d96: 6078 str r0, [r7, #4] if(hcrc->Instance==CRC) 8000d98: 687b ldr r3, [r7, #4] 8000d9a: 681b ldr r3, [r3, #0] 8000d9c: 4a0b ldr r2, [pc, #44] @ (8000dcc ) 8000d9e: 4293 cmp r3, r2 8000da0: d10d bne.n 8000dbe { /* USER CODE BEGIN CRC_MspInit 0 */ /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); 8000da2: 2300 movs r3, #0 8000da4: 60fb str r3, [r7, #12] 8000da6: 4b0a ldr r3, [pc, #40] @ (8000dd0 ) 8000da8: 6b1b ldr r3, [r3, #48] @ 0x30 8000daa: 4a09 ldr r2, [pc, #36] @ (8000dd0 ) 8000dac: f443 5380 orr.w r3, r3, #4096 @ 0x1000 8000db0: 6313 str r3, [r2, #48] @ 0x30 8000db2: 4b07 ldr r3, [pc, #28] @ (8000dd0 ) 8000db4: 6b1b ldr r3, [r3, #48] @ 0x30 8000db6: f403 5380 and.w r3, r3, #4096 @ 0x1000 8000dba: 60fb str r3, [r7, #12] 8000dbc: 68fb ldr r3, [r7, #12] /* USER CODE END CRC_MspInit 1 */ } } 8000dbe: bf00 nop 8000dc0: 3714 adds r7, #20 8000dc2: 46bd mov sp, r7 8000dc4: f85d 7b04 ldr.w r7, [sp], #4 8000dc8: 4770 bx lr 8000dca: bf00 nop 8000dcc: 40023000 .word 0x40023000 8000dd0: 40023800 .word 0x40023800 08000dd4 : * This function configures the hardware resources used in this example * @param hdma2d: DMA2D handle pointer * @retval None */ void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) { 8000dd4: b580 push {r7, lr} 8000dd6: b084 sub sp, #16 8000dd8: af00 add r7, sp, #0 8000dda: 6078 str r0, [r7, #4] if(hdma2d->Instance==DMA2D) 8000ddc: 687b ldr r3, [r7, #4] 8000dde: 681b ldr r3, [r3, #0] 8000de0: 4a0e ldr r2, [pc, #56] @ (8000e1c ) 8000de2: 4293 cmp r3, r2 8000de4: d115 bne.n 8000e12 { /* USER CODE BEGIN DMA2D_MspInit 0 */ /* USER CODE END DMA2D_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DMA2D_CLK_ENABLE(); 8000de6: 2300 movs r3, #0 8000de8: 60fb str r3, [r7, #12] 8000dea: 4b0d ldr r3, [pc, #52] @ (8000e20 ) 8000dec: 6b1b ldr r3, [r3, #48] @ 0x30 8000dee: 4a0c ldr r2, [pc, #48] @ (8000e20 ) 8000df0: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8000df4: 6313 str r3, [r2, #48] @ 0x30 8000df6: 4b0a ldr r3, [pc, #40] @ (8000e20 ) 8000df8: 6b1b ldr r3, [r3, #48] @ 0x30 8000dfa: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8000dfe: 60fb str r3, [r7, #12] 8000e00: 68fb ldr r3, [r7, #12] /* DMA2D interrupt Init */ HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0); 8000e02: 2200 movs r2, #0 8000e04: 2105 movs r1, #5 8000e06: 205a movs r0, #90 @ 0x5a 8000e08: f000 fd0e bl 8001828 HAL_NVIC_EnableIRQ(DMA2D_IRQn); 8000e0c: 205a movs r0, #90 @ 0x5a 8000e0e: f000 fd27 bl 8001860 /* USER CODE END DMA2D_MspInit 1 */ } } 8000e12: bf00 nop 8000e14: 3710 adds r7, #16 8000e16: 46bd mov sp, r7 8000e18: bd80 pop {r7, pc} 8000e1a: bf00 nop 8000e1c: 4002b000 .word 0x4002b000 8000e20: 40023800 .word 0x40023800 08000e24 : * This function configures the hardware resources used in this example * @param hi2c: I2C handle pointer * @retval None */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { 8000e24: b580 push {r7, lr} 8000e26: b08a sub sp, #40 @ 0x28 8000e28: af00 add r7, sp, #0 8000e2a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000e2c: f107 0314 add.w r3, r7, #20 8000e30: 2200 movs r2, #0 8000e32: 601a str r2, [r3, #0] 8000e34: 605a str r2, [r3, #4] 8000e36: 609a str r2, [r3, #8] 8000e38: 60da str r2, [r3, #12] 8000e3a: 611a str r2, [r3, #16] if(hi2c->Instance==I2C3) 8000e3c: 687b ldr r3, [r7, #4] 8000e3e: 681b ldr r3, [r3, #0] 8000e40: 4a29 ldr r2, [pc, #164] @ (8000ee8 ) 8000e42: 4293 cmp r3, r2 8000e44: d14b bne.n 8000ede { /* USER CODE BEGIN I2C3_MspInit 0 */ /* USER CODE END I2C3_MspInit 0 */ __HAL_RCC_GPIOC_CLK_ENABLE(); 8000e46: 2300 movs r3, #0 8000e48: 613b str r3, [r7, #16] 8000e4a: 4b28 ldr r3, [pc, #160] @ (8000eec ) 8000e4c: 6b1b ldr r3, [r3, #48] @ 0x30 8000e4e: 4a27 ldr r2, [pc, #156] @ (8000eec ) 8000e50: f043 0304 orr.w r3, r3, #4 8000e54: 6313 str r3, [r2, #48] @ 0x30 8000e56: 4b25 ldr r3, [pc, #148] @ (8000eec ) 8000e58: 6b1b ldr r3, [r3, #48] @ 0x30 8000e5a: f003 0304 and.w r3, r3, #4 8000e5e: 613b str r3, [r7, #16] 8000e60: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000e62: 2300 movs r3, #0 8000e64: 60fb str r3, [r7, #12] 8000e66: 4b21 ldr r3, [pc, #132] @ (8000eec ) 8000e68: 6b1b ldr r3, [r3, #48] @ 0x30 8000e6a: 4a20 ldr r2, [pc, #128] @ (8000eec ) 8000e6c: f043 0301 orr.w r3, r3, #1 8000e70: 6313 str r3, [r2, #48] @ 0x30 8000e72: 4b1e ldr r3, [pc, #120] @ (8000eec ) 8000e74: 6b1b ldr r3, [r3, #48] @ 0x30 8000e76: f003 0301 and.w r3, r3, #1 8000e7a: 60fb str r3, [r7, #12] 8000e7c: 68fb ldr r3, [r7, #12] /**I2C3 GPIO Configuration PC9 ------> I2C3_SDA PA8 ------> I2C3_SCL */ GPIO_InitStruct.Pin = I2C3_SDA_Pin; 8000e7e: f44f 7300 mov.w r3, #512 @ 0x200 8000e82: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000e84: 2312 movs r3, #18 8000e86: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000e88: 2301 movs r3, #1 8000e8a: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000e8c: 2300 movs r3, #0 8000e8e: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; 8000e90: 2304 movs r3, #4 8000e92: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct); 8000e94: f107 0314 add.w r3, r7, #20 8000e98: 4619 mov r1, r3 8000e9a: 4815 ldr r0, [pc, #84] @ (8000ef0 ) 8000e9c: f000 fef6 bl 8001c8c GPIO_InitStruct.Pin = I2C3_SCL_Pin; 8000ea0: f44f 7380 mov.w r3, #256 @ 0x100 8000ea4: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; 8000ea6: 2312 movs r3, #18 8000ea8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_PULLUP; 8000eaa: 2301 movs r3, #1 8000eac: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8000eae: 2300 movs r3, #0 8000eb0: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF4_I2C3; 8000eb2: 2304 movs r3, #4 8000eb4: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct); 8000eb6: f107 0314 add.w r3, r7, #20 8000eba: 4619 mov r1, r3 8000ebc: 480d ldr r0, [pc, #52] @ (8000ef4 ) 8000ebe: f000 fee5 bl 8001c8c /* Peripheral clock enable */ __HAL_RCC_I2C3_CLK_ENABLE(); 8000ec2: 2300 movs r3, #0 8000ec4: 60bb str r3, [r7, #8] 8000ec6: 4b09 ldr r3, [pc, #36] @ (8000eec ) 8000ec8: 6c1b ldr r3, [r3, #64] @ 0x40 8000eca: 4a08 ldr r2, [pc, #32] @ (8000eec ) 8000ecc: f443 0300 orr.w r3, r3, #8388608 @ 0x800000 8000ed0: 6413 str r3, [r2, #64] @ 0x40 8000ed2: 4b06 ldr r3, [pc, #24] @ (8000eec ) 8000ed4: 6c1b ldr r3, [r3, #64] @ 0x40 8000ed6: f403 0300 and.w r3, r3, #8388608 @ 0x800000 8000eda: 60bb str r3, [r7, #8] 8000edc: 68bb ldr r3, [r7, #8] /* USER CODE END I2C3_MspInit 1 */ } } 8000ede: bf00 nop 8000ee0: 3728 adds r7, #40 @ 0x28 8000ee2: 46bd mov sp, r7 8000ee4: bd80 pop {r7, pc} 8000ee6: bf00 nop 8000ee8: 40005c00 .word 0x40005c00 8000eec: 40023800 .word 0x40023800 8000ef0: 40020800 .word 0x40020800 8000ef4: 40020000 .word 0x40020000 08000ef8 : * This function configures the hardware resources used in this example * @param hltdc: LTDC handle pointer * @retval None */ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) { 8000ef8: b580 push {r7, lr} 8000efa: b09a sub sp, #104 @ 0x68 8000efc: af00 add r7, sp, #0 8000efe: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8000f00: f107 0354 add.w r3, r7, #84 @ 0x54 8000f04: 2200 movs r2, #0 8000f06: 601a str r2, [r3, #0] 8000f08: 605a str r2, [r3, #4] 8000f0a: 609a str r2, [r3, #8] 8000f0c: 60da str r2, [r3, #12] 8000f0e: 611a str r2, [r3, #16] RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 8000f10: f107 0324 add.w r3, r7, #36 @ 0x24 8000f14: 2230 movs r2, #48 @ 0x30 8000f16: 2100 movs r1, #0 8000f18: 4618 mov r0, r3 8000f1a: f006 ffc1 bl 8007ea0 if(hltdc->Instance==LTDC) 8000f1e: 687b ldr r3, [r7, #4] 8000f20: 681b ldr r3, [r3, #0] 8000f22: 4a85 ldr r2, [pc, #532] @ (8001138 ) 8000f24: 4293 cmp r3, r2 8000f26: f040 8102 bne.w 800112e /* USER CODE END LTDC_MspInit 0 */ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; 8000f2a: 2308 movs r3, #8 8000f2c: 627b str r3, [r7, #36] @ 0x24 PeriphClkInitStruct.PLLSAI.PLLSAIN = 50; 8000f2e: 2332 movs r3, #50 @ 0x32 8000f30: 637b str r3, [r7, #52] @ 0x34 PeriphClkInitStruct.PLLSAI.PLLSAIR = 2; 8000f32: 2302 movs r3, #2 8000f34: 63fb str r3, [r7, #60] @ 0x3c PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2; 8000f36: 2300 movs r3, #0 8000f38: 64bb str r3, [r7, #72] @ 0x48 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 8000f3a: f107 0324 add.w r3, r7, #36 @ 0x24 8000f3e: 4618 mov r0, r3 8000f40: f003 ffc2 bl 8004ec8 8000f44: 4603 mov r3, r0 8000f46: 2b00 cmp r3, #0 8000f48: d001 beq.n 8000f4e { Error_Handler(); 8000f4a: f7ff feef bl 8000d2c } /* Peripheral clock enable */ __HAL_RCC_LTDC_CLK_ENABLE(); 8000f4e: 2300 movs r3, #0 8000f50: 623b str r3, [r7, #32] 8000f52: 4b7a ldr r3, [pc, #488] @ (800113c ) 8000f54: 6c5b ldr r3, [r3, #68] @ 0x44 8000f56: 4a79 ldr r2, [pc, #484] @ (800113c ) 8000f58: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000 8000f5c: 6453 str r3, [r2, #68] @ 0x44 8000f5e: 4b77 ldr r3, [pc, #476] @ (800113c ) 8000f60: 6c5b ldr r3, [r3, #68] @ 0x44 8000f62: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 8000f66: 623b str r3, [r7, #32] 8000f68: 6a3b ldr r3, [r7, #32] __HAL_RCC_GPIOF_CLK_ENABLE(); 8000f6a: 2300 movs r3, #0 8000f6c: 61fb str r3, [r7, #28] 8000f6e: 4b73 ldr r3, [pc, #460] @ (800113c ) 8000f70: 6b1b ldr r3, [r3, #48] @ 0x30 8000f72: 4a72 ldr r2, [pc, #456] @ (800113c ) 8000f74: f043 0320 orr.w r3, r3, #32 8000f78: 6313 str r3, [r2, #48] @ 0x30 8000f7a: 4b70 ldr r3, [pc, #448] @ (800113c ) 8000f7c: 6b1b ldr r3, [r3, #48] @ 0x30 8000f7e: f003 0320 and.w r3, r3, #32 8000f82: 61fb str r3, [r7, #28] 8000f84: 69fb ldr r3, [r7, #28] __HAL_RCC_GPIOA_CLK_ENABLE(); 8000f86: 2300 movs r3, #0 8000f88: 61bb str r3, [r7, #24] 8000f8a: 4b6c ldr r3, [pc, #432] @ (800113c ) 8000f8c: 6b1b ldr r3, [r3, #48] @ 0x30 8000f8e: 4a6b ldr r2, [pc, #428] @ (800113c ) 8000f90: f043 0301 orr.w r3, r3, #1 8000f94: 6313 str r3, [r2, #48] @ 0x30 8000f96: 4b69 ldr r3, [pc, #420] @ (800113c ) 8000f98: 6b1b ldr r3, [r3, #48] @ 0x30 8000f9a: f003 0301 and.w r3, r3, #1 8000f9e: 61bb str r3, [r7, #24] 8000fa0: 69bb ldr r3, [r7, #24] __HAL_RCC_GPIOB_CLK_ENABLE(); 8000fa2: 2300 movs r3, #0 8000fa4: 617b str r3, [r7, #20] 8000fa6: 4b65 ldr r3, [pc, #404] @ (800113c ) 8000fa8: 6b1b ldr r3, [r3, #48] @ 0x30 8000faa: 4a64 ldr r2, [pc, #400] @ (800113c ) 8000fac: f043 0302 orr.w r3, r3, #2 8000fb0: 6313 str r3, [r2, #48] @ 0x30 8000fb2: 4b62 ldr r3, [pc, #392] @ (800113c ) 8000fb4: 6b1b ldr r3, [r3, #48] @ 0x30 8000fb6: f003 0302 and.w r3, r3, #2 8000fba: 617b str r3, [r7, #20] 8000fbc: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOG_CLK_ENABLE(); 8000fbe: 2300 movs r3, #0 8000fc0: 613b str r3, [r7, #16] 8000fc2: 4b5e ldr r3, [pc, #376] @ (800113c ) 8000fc4: 6b1b ldr r3, [r3, #48] @ 0x30 8000fc6: 4a5d ldr r2, [pc, #372] @ (800113c ) 8000fc8: f043 0340 orr.w r3, r3, #64 @ 0x40 8000fcc: 6313 str r3, [r2, #48] @ 0x30 8000fce: 4b5b ldr r3, [pc, #364] @ (800113c ) 8000fd0: 6b1b ldr r3, [r3, #48] @ 0x30 8000fd2: f003 0340 and.w r3, r3, #64 @ 0x40 8000fd6: 613b str r3, [r7, #16] 8000fd8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8000fda: 2300 movs r3, #0 8000fdc: 60fb str r3, [r7, #12] 8000fde: 4b57 ldr r3, [pc, #348] @ (800113c ) 8000fe0: 6b1b ldr r3, [r3, #48] @ 0x30 8000fe2: 4a56 ldr r2, [pc, #344] @ (800113c ) 8000fe4: f043 0304 orr.w r3, r3, #4 8000fe8: 6313 str r3, [r2, #48] @ 0x30 8000fea: 4b54 ldr r3, [pc, #336] @ (800113c ) 8000fec: 6b1b ldr r3, [r3, #48] @ 0x30 8000fee: f003 0304 and.w r3, r3, #4 8000ff2: 60fb str r3, [r7, #12] 8000ff4: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOD_CLK_ENABLE(); 8000ff6: 2300 movs r3, #0 8000ff8: 60bb str r3, [r7, #8] 8000ffa: 4b50 ldr r3, [pc, #320] @ (800113c ) 8000ffc: 6b1b ldr r3, [r3, #48] @ 0x30 8000ffe: 4a4f ldr r2, [pc, #316] @ (800113c ) 8001000: f043 0308 orr.w r3, r3, #8 8001004: 6313 str r3, [r2, #48] @ 0x30 8001006: 4b4d ldr r3, [pc, #308] @ (800113c ) 8001008: 6b1b ldr r3, [r3, #48] @ 0x30 800100a: f003 0308 and.w r3, r3, #8 800100e: 60bb str r3, [r7, #8] 8001010: 68bb ldr r3, [r7, #8] PG11 ------> LTDC_B3 PG12 ------> LTDC_B4 PB8 ------> LTDC_B6 PB9 ------> LTDC_B7 */ GPIO_InitStruct.Pin = ENABLE_Pin; 8001012: f44f 6380 mov.w r3, #1024 @ 0x400 8001016: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001018: 2302 movs r3, #2 800101a: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800101c: 2300 movs r3, #0 800101e: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001020: 2300 movs r3, #0 8001022: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001024: 230e movs r3, #14 8001026: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct); 8001028: f107 0354 add.w r3, r7, #84 @ 0x54 800102c: 4619 mov r1, r3 800102e: 4844 ldr r0, [pc, #272] @ (8001140 ) 8001030: f000 fe2c bl 8001c8c GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin 8001034: f641 0358 movw r3, #6232 @ 0x1858 8001038: 657b str r3, [r7, #84] @ 0x54 |R5_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800103a: 2302 movs r3, #2 800103c: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800103e: 2300 movs r3, #0 8001040: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001042: 2300 movs r3, #0 8001044: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001046: 230e movs r3, #14 8001048: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800104a: f107 0354 add.w r3, r7, #84 @ 0x54 800104e: 4619 mov r1, r3 8001050: 483c ldr r0, [pc, #240] @ (8001144 ) 8001052: f000 fe1b bl 8001c8c GPIO_InitStruct.Pin = R3_Pin|R6_Pin; 8001056: 2303 movs r3, #3 8001058: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800105a: 2302 movs r3, #2 800105c: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 800105e: 2300 movs r3, #0 8001060: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001062: 2300 movs r3, #0 8001064: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 8001066: 2309 movs r3, #9 8001068: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800106a: f107 0354 add.w r3, r7, #84 @ 0x54 800106e: 4619 mov r1, r3 8001070: 4835 ldr r0, [pc, #212] @ (8001148 ) 8001072: f000 fe0b bl 8001c8c GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin; 8001076: f44f 6370 mov.w r3, #3840 @ 0xf00 800107a: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800107c: 2302 movs r3, #2 800107e: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001080: 2300 movs r3, #0 8001082: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001084: 2300 movs r3, #0 8001086: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 8001088: 230e movs r3, #14 800108a: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 800108c: f107 0354 add.w r3, r7, #84 @ 0x54 8001090: 4619 mov r1, r3 8001092: 482d ldr r0, [pc, #180] @ (8001148 ) 8001094: f000 fdfa bl 8001c8c GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin; 8001098: f44f 630c mov.w r3, #2240 @ 0x8c0 800109c: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800109e: 2302 movs r3, #2 80010a0: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010a2: 2300 movs r3, #0 80010a4: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010a6: 2300 movs r3, #0 80010a8: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 80010aa: 230e movs r3, #14 80010ac: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 80010ae: f107 0354 add.w r3, r7, #84 @ 0x54 80010b2: 4619 mov r1, r3 80010b4: 4825 ldr r0, [pc, #148] @ (800114c ) 80010b6: f000 fde9 bl 8001c8c GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin; 80010ba: f44f 6398 mov.w r3, #1216 @ 0x4c0 80010be: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010c0: 2302 movs r3, #2 80010c2: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010c4: 2300 movs r3, #0 80010c6: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010c8: 2300 movs r3, #0 80010ca: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 80010cc: 230e movs r3, #14 80010ce: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 80010d0: f107 0354 add.w r3, r7, #84 @ 0x54 80010d4: 4619 mov r1, r3 80010d6: 481e ldr r0, [pc, #120] @ (8001150 ) 80010d8: f000 fdd8 bl 8001c8c GPIO_InitStruct.Pin = G7_Pin|B2_Pin; 80010dc: 2348 movs r3, #72 @ 0x48 80010de: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80010e0: 2302 movs r3, #2 80010e2: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 80010e4: 2300 movs r3, #0 80010e6: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80010e8: 2300 movs r3, #0 80010ea: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; 80010ec: 230e movs r3, #14 80010ee: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 80010f0: f107 0354 add.w r3, r7, #84 @ 0x54 80010f4: 4619 mov r1, r3 80010f6: 4817 ldr r0, [pc, #92] @ (8001154 ) 80010f8: f000 fdc8 bl 8001c8c GPIO_InitStruct.Pin = G3_Pin|B4_Pin; 80010fc: f44f 53a0 mov.w r3, #5120 @ 0x1400 8001100: 657b str r3, [r7, #84] @ 0x54 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001102: 2302 movs r3, #2 8001104: 65bb str r3, [r7, #88] @ 0x58 GPIO_InitStruct.Pull = GPIO_NOPULL; 8001106: 2300 movs r3, #0 8001108: 65fb str r3, [r7, #92] @ 0x5c GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 800110a: 2300 movs r3, #0 800110c: 663b str r3, [r7, #96] @ 0x60 GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; 800110e: 2309 movs r3, #9 8001110: 667b str r3, [r7, #100] @ 0x64 HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 8001112: f107 0354 add.w r3, r7, #84 @ 0x54 8001116: 4619 mov r1, r3 8001118: 480c ldr r0, [pc, #48] @ (800114c ) 800111a: f000 fdb7 bl 8001c8c /* LTDC interrupt Init */ HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0); 800111e: 2200 movs r2, #0 8001120: 2105 movs r1, #5 8001122: 2058 movs r0, #88 @ 0x58 8001124: f000 fb80 bl 8001828 HAL_NVIC_EnableIRQ(LTDC_IRQn); 8001128: 2058 movs r0, #88 @ 0x58 800112a: f000 fb99 bl 8001860 /* USER CODE END LTDC_MspInit 1 */ } } 800112e: bf00 nop 8001130: 3768 adds r7, #104 @ 0x68 8001132: 46bd mov sp, r7 8001134: bd80 pop {r7, pc} 8001136: bf00 nop 8001138: 40016800 .word 0x40016800 800113c: 40023800 .word 0x40023800 8001140: 40021400 .word 0x40021400 8001144: 40020000 .word 0x40020000 8001148: 40020400 .word 0x40020400 800114c: 40021800 .word 0x40021800 8001150: 40020800 .word 0x40020800 8001154: 40020c00 .word 0x40020c00 08001158 : * This function configures the hardware resources used in this example * @param hspi: SPI handle pointer * @retval None */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { 8001158: b580 push {r7, lr} 800115a: b08a sub sp, #40 @ 0x28 800115c: af00 add r7, sp, #0 800115e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001160: f107 0314 add.w r3, r7, #20 8001164: 2200 movs r2, #0 8001166: 601a str r2, [r3, #0] 8001168: 605a str r2, [r3, #4] 800116a: 609a str r2, [r3, #8] 800116c: 60da str r2, [r3, #12] 800116e: 611a str r2, [r3, #16] if(hspi->Instance==SPI5) 8001170: 687b ldr r3, [r7, #4] 8001172: 681b ldr r3, [r3, #0] 8001174: 4a19 ldr r2, [pc, #100] @ (80011dc ) 8001176: 4293 cmp r3, r2 8001178: d12c bne.n 80011d4 { /* USER CODE BEGIN SPI5_MspInit 0 */ /* USER CODE END SPI5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_SPI5_CLK_ENABLE(); 800117a: 2300 movs r3, #0 800117c: 613b str r3, [r7, #16] 800117e: 4b18 ldr r3, [pc, #96] @ (80011e0 ) 8001180: 6c5b ldr r3, [r3, #68] @ 0x44 8001182: 4a17 ldr r2, [pc, #92] @ (80011e0 ) 8001184: f443 1380 orr.w r3, r3, #1048576 @ 0x100000 8001188: 6453 str r3, [r2, #68] @ 0x44 800118a: 4b15 ldr r3, [pc, #84] @ (80011e0 ) 800118c: 6c5b ldr r3, [r3, #68] @ 0x44 800118e: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001192: 613b str r3, [r7, #16] 8001194: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOF_CLK_ENABLE(); 8001196: 2300 movs r3, #0 8001198: 60fb str r3, [r7, #12] 800119a: 4b11 ldr r3, [pc, #68] @ (80011e0 ) 800119c: 6b1b ldr r3, [r3, #48] @ 0x30 800119e: 4a10 ldr r2, [pc, #64] @ (80011e0 ) 80011a0: f043 0320 orr.w r3, r3, #32 80011a4: 6313 str r3, [r2, #48] @ 0x30 80011a6: 4b0e ldr r3, [pc, #56] @ (80011e0 ) 80011a8: 6b1b ldr r3, [r3, #48] @ 0x30 80011aa: f003 0320 and.w r3, r3, #32 80011ae: 60fb str r3, [r7, #12] 80011b0: 68fb ldr r3, [r7, #12] /**SPI5 GPIO Configuration PF7 ------> SPI5_SCK PF8 ------> SPI5_MISO PF9 ------> SPI5_MOSI */ GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin; 80011b2: f44f 7360 mov.w r3, #896 @ 0x380 80011b6: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 80011b8: 2302 movs r3, #2 80011ba: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 80011bc: 2300 movs r3, #0 80011be: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80011c0: 2300 movs r3, #0 80011c2: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF5_SPI5; 80011c4: 2305 movs r3, #5 80011c6: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 80011c8: f107 0314 add.w r3, r7, #20 80011cc: 4619 mov r1, r3 80011ce: 4805 ldr r0, [pc, #20] @ (80011e4 ) 80011d0: f000 fd5c bl 8001c8c /* USER CODE END SPI5_MspInit 1 */ } } 80011d4: bf00 nop 80011d6: 3728 adds r7, #40 @ 0x28 80011d8: 46bd mov sp, r7 80011da: bd80 pop {r7, pc} 80011dc: 40015000 .word 0x40015000 80011e0: 40023800 .word 0x40023800 80011e4: 40021400 .word 0x40021400 080011e8 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 80011e8: b480 push {r7} 80011ea: b085 sub sp, #20 80011ec: af00 add r7, sp, #0 80011ee: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 80011f0: 687b ldr r3, [r7, #4] 80011f2: 681b ldr r3, [r3, #0] 80011f4: 4a0b ldr r2, [pc, #44] @ (8001224 ) 80011f6: 4293 cmp r3, r2 80011f8: d10d bne.n 8001216 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 80011fa: 2300 movs r3, #0 80011fc: 60fb str r3, [r7, #12] 80011fe: 4b0a ldr r3, [pc, #40] @ (8001228 ) 8001200: 6c5b ldr r3, [r3, #68] @ 0x44 8001202: 4a09 ldr r2, [pc, #36] @ (8001228 ) 8001204: f043 0301 orr.w r3, r3, #1 8001208: 6453 str r3, [r2, #68] @ 0x44 800120a: 4b07 ldr r3, [pc, #28] @ (8001228 ) 800120c: 6c5b ldr r3, [r3, #68] @ 0x44 800120e: f003 0301 and.w r3, r3, #1 8001212: 60fb str r3, [r7, #12] 8001214: 68fb ldr r3, [r7, #12] /* USER CODE END TIM1_MspInit 1 */ } } 8001216: bf00 nop 8001218: 3714 adds r7, #20 800121a: 46bd mov sp, r7 800121c: f85d 7b04 ldr.w r7, [sp], #4 8001220: 4770 bx lr 8001222: bf00 nop 8001224: 40010000 .word 0x40010000 8001228: 40023800 .word 0x40023800 0800122c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 800122c: b580 push {r7, lr} 800122e: b08a sub sp, #40 @ 0x28 8001230: af00 add r7, sp, #0 8001232: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8001234: f107 0314 add.w r3, r7, #20 8001238: 2200 movs r2, #0 800123a: 601a str r2, [r3, #0] 800123c: 605a str r2, [r3, #4] 800123e: 609a str r2, [r3, #8] 8001240: 60da str r2, [r3, #12] 8001242: 611a str r2, [r3, #16] if(huart->Instance==USART1) 8001244: 687b ldr r3, [r7, #4] 8001246: 681b ldr r3, [r3, #0] 8001248: 4a19 ldr r2, [pc, #100] @ (80012b0 ) 800124a: 4293 cmp r3, r2 800124c: d12c bne.n 80012a8 { /* USER CODE BEGIN USART1_MspInit 0 */ /* USER CODE END USART1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 800124e: 2300 movs r3, #0 8001250: 613b str r3, [r7, #16] 8001252: 4b18 ldr r3, [pc, #96] @ (80012b4 ) 8001254: 6c5b ldr r3, [r3, #68] @ 0x44 8001256: 4a17 ldr r2, [pc, #92] @ (80012b4 ) 8001258: f043 0310 orr.w r3, r3, #16 800125c: 6453 str r3, [r2, #68] @ 0x44 800125e: 4b15 ldr r3, [pc, #84] @ (80012b4 ) 8001260: 6c5b ldr r3, [r3, #68] @ 0x44 8001262: f003 0310 and.w r3, r3, #16 8001266: 613b str r3, [r7, #16] 8001268: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 800126a: 2300 movs r3, #0 800126c: 60fb str r3, [r7, #12] 800126e: 4b11 ldr r3, [pc, #68] @ (80012b4 ) 8001270: 6b1b ldr r3, [r3, #48] @ 0x30 8001272: 4a10 ldr r2, [pc, #64] @ (80012b4 ) 8001274: f043 0301 orr.w r3, r3, #1 8001278: 6313 str r3, [r2, #48] @ 0x30 800127a: 4b0e ldr r3, [pc, #56] @ (80012b4 ) 800127c: 6b1b ldr r3, [r3, #48] @ 0x30 800127e: f003 0301 and.w r3, r3, #1 8001282: 60fb str r3, [r7, #12] 8001284: 68fb ldr r3, [r7, #12] /**USART1 GPIO Configuration PA9 ------> USART1_TX PA10 ------> USART1_RX */ GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; 8001286: f44f 63c0 mov.w r3, #1536 @ 0x600 800128a: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800128c: 2302 movs r3, #2 800128e: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001290: 2300 movs r3, #0 8001292: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001294: 2303 movs r3, #3 8001296: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART1; 8001298: 2307 movs r3, #7 800129a: 627b str r3, [r7, #36] @ 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 800129c: f107 0314 add.w r3, r7, #20 80012a0: 4619 mov r1, r3 80012a2: 4805 ldr r0, [pc, #20] @ (80012b8 ) 80012a4: f000 fcf2 bl 8001c8c /* USER CODE END USART1_MspInit 1 */ } } 80012a8: bf00 nop 80012aa: 3728 adds r7, #40 @ 0x28 80012ac: 46bd mov sp, r7 80012ae: bd80 pop {r7, pc} 80012b0: 40011000 .word 0x40011000 80012b4: 40023800 .word 0x40023800 80012b8: 40020000 .word 0x40020000 080012bc : } static uint32_t FMC_Initialized = 0; static void HAL_FMC_MspInit(void){ 80012bc: b580 push {r7, lr} 80012be: b086 sub sp, #24 80012c0: af00 add r7, sp, #0 /* USER CODE BEGIN FMC_MspInit 0 */ /* USER CODE END FMC_MspInit 0 */ GPIO_InitTypeDef GPIO_InitStruct ={0}; 80012c2: 1d3b adds r3, r7, #4 80012c4: 2200 movs r2, #0 80012c6: 601a str r2, [r3, #0] 80012c8: 605a str r2, [r3, #4] 80012ca: 609a str r2, [r3, #8] 80012cc: 60da str r2, [r3, #12] 80012ce: 611a str r2, [r3, #16] if (FMC_Initialized) { 80012d0: 4b3b ldr r3, [pc, #236] @ (80013c0 ) 80012d2: 681b ldr r3, [r3, #0] 80012d4: 2b00 cmp r3, #0 80012d6: d16f bne.n 80013b8 return; } FMC_Initialized = 1; 80012d8: 4b39 ldr r3, [pc, #228] @ (80013c0 ) 80012da: 2201 movs r2, #1 80012dc: 601a str r2, [r3, #0] /* Peripheral clock enable */ __HAL_RCC_FMC_CLK_ENABLE(); 80012de: 2300 movs r3, #0 80012e0: 603b str r3, [r7, #0] 80012e2: 4b38 ldr r3, [pc, #224] @ (80013c4 ) 80012e4: 6b9b ldr r3, [r3, #56] @ 0x38 80012e6: 4a37 ldr r2, [pc, #220] @ (80013c4 ) 80012e8: f043 0301 orr.w r3, r3, #1 80012ec: 6393 str r3, [r2, #56] @ 0x38 80012ee: 4b35 ldr r3, [pc, #212] @ (80013c4 ) 80012f0: 6b9b ldr r3, [r3, #56] @ 0x38 80012f2: f003 0301 and.w r3, r3, #1 80012f6: 603b str r3, [r7, #0] 80012f8: 683b ldr r3, [r7, #0] PB5 ------> FMC_SDCKE1 PB6 ------> FMC_SDNE1 PE0 ------> FMC_NBL0 PE1 ------> FMC_NBL1 */ GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin 80012fa: f64f 033f movw r3, #63551 @ 0xf83f 80012fe: 607b str r3, [r7, #4] |A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin |A7_Pin|A8_Pin|A9_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8001300: 2302 movs r3, #2 8001302: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001304: 2300 movs r3, #0 8001306: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001308: 2303 movs r3, #3 800130a: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 800130c: 230c movs r3, #12 800130e: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); 8001310: 1d3b adds r3, r7, #4 8001312: 4619 mov r1, r3 8001314: 482c ldr r0, [pc, #176] @ (80013c8 ) 8001316: f000 fcb9 bl 8001c8c GPIO_InitStruct.Pin = SDNWE_Pin; 800131a: 2301 movs r3, #1 800131c: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800131e: 2302 movs r3, #2 8001320: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001322: 2300 movs r3, #0 8001324: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001326: 2303 movs r3, #3 8001328: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 800132a: 230c movs r3, #12 800132c: 617b str r3, [r7, #20] HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct); 800132e: 1d3b adds r3, r7, #4 8001330: 4619 mov r1, r3 8001332: 4826 ldr r0, [pc, #152] @ (80013cc ) 8001334: f000 fcaa bl 8001c8c GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin 8001338: f248 1333 movw r3, #33075 @ 0x8133 800133c: 607b str r3, [r7, #4] |SDCLK_Pin|SDNCAS_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800133e: 2302 movs r3, #2 8001340: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001342: 2300 movs r3, #0 8001344: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001346: 2303 movs r3, #3 8001348: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 800134a: 230c movs r3, #12 800134c: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 800134e: 1d3b adds r3, r7, #4 8001350: 4619 mov r1, r3 8001352: 481f ldr r0, [pc, #124] @ (80013d0 ) 8001354: f000 fc9a bl 8001c8c GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin 8001358: f64f 7383 movw r3, #65411 @ 0xff83 800135c: 607b str r3, [r7, #4] |D8_Pin|D9_Pin|D10_Pin|D11_Pin |D12_Pin|NBL0_Pin|NBL1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800135e: 2302 movs r3, #2 8001360: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001362: 2300 movs r3, #0 8001364: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001366: 2303 movs r3, #3 8001368: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 800136a: 230c movs r3, #12 800136c: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); 800136e: 1d3b adds r3, r7, #4 8001370: 4619 mov r1, r3 8001372: 4818 ldr r0, [pc, #96] @ (80013d4 ) 8001374: f000 fc8a bl 8001c8c GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin 8001378: f24c 7303 movw r3, #50947 @ 0xc703 800137c: 607b str r3, [r7, #4] |D1_Pin|D2_Pin|D3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800137e: 2302 movs r3, #2 8001380: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001382: 2300 movs r3, #0 8001384: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 8001386: 2303 movs r3, #3 8001388: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 800138a: 230c movs r3, #12 800138c: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); 800138e: 1d3b adds r3, r7, #4 8001390: 4619 mov r1, r3 8001392: 4811 ldr r0, [pc, #68] @ (80013d8 ) 8001394: f000 fc7a bl 8001c8c GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin; 8001398: 2360 movs r3, #96 @ 0x60 800139a: 607b str r3, [r7, #4] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 800139c: 2302 movs r3, #2 800139e: 60bb str r3, [r7, #8] GPIO_InitStruct.Pull = GPIO_NOPULL; 80013a0: 2300 movs r3, #0 80013a2: 60fb str r3, [r7, #12] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; 80013a4: 2303 movs r3, #3 80013a6: 613b str r3, [r7, #16] GPIO_InitStruct.Alternate = GPIO_AF12_FMC; 80013a8: 230c movs r3, #12 80013aa: 617b str r3, [r7, #20] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80013ac: 1d3b adds r3, r7, #4 80013ae: 4619 mov r1, r3 80013b0: 480a ldr r0, [pc, #40] @ (80013dc ) 80013b2: f000 fc6b bl 8001c8c 80013b6: e000 b.n 80013ba return; 80013b8: bf00 nop /* USER CODE BEGIN FMC_MspInit 1 */ /* USER CODE END FMC_MspInit 1 */ } 80013ba: 3718 adds r7, #24 80013bc: 46bd mov sp, r7 80013be: bd80 pop {r7, pc} 80013c0: 2000028c .word 0x2000028c 80013c4: 40023800 .word 0x40023800 80013c8: 40021400 .word 0x40021400 80013cc: 40020800 .word 0x40020800 80013d0: 40021800 .word 0x40021800 80013d4: 40021000 .word 0x40021000 80013d8: 40020c00 .word 0x40020c00 80013dc: 40020400 .word 0x40020400 080013e0 : void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){ 80013e0: b580 push {r7, lr} 80013e2: b082 sub sp, #8 80013e4: af00 add r7, sp, #0 80013e6: 6078 str r0, [r7, #4] /* USER CODE BEGIN SDRAM_MspInit 0 */ /* USER CODE END SDRAM_MspInit 0 */ HAL_FMC_MspInit(); 80013e8: f7ff ff68 bl 80012bc /* USER CODE BEGIN SDRAM_MspInit 1 */ /* USER CODE END SDRAM_MspInit 1 */ } 80013ec: bf00 nop 80013ee: 3708 adds r7, #8 80013f0: 46bd mov sp, r7 80013f2: bd80 pop {r7, pc} 080013f4 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80013f4: b580 push {r7, lr} 80013f6: b08e sub sp, #56 @ 0x38 80013f8: af00 add r7, sp, #0 80013fa: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock, uwAPB1Prescaler = 0U; 80013fc: 2300 movs r3, #0 80013fe: 62fb str r3, [r7, #44] @ 0x2c uint32_t uwPrescalerValue = 0U; 8001400: 2300 movs r3, #0 8001402: 62bb str r3, [r7, #40] @ 0x28 uint32_t pFLatency; HAL_StatusTypeDef status; /* Enable TIM6 clock */ __HAL_RCC_TIM6_CLK_ENABLE(); 8001404: 2300 movs r3, #0 8001406: 60fb str r3, [r7, #12] 8001408: 4b33 ldr r3, [pc, #204] @ (80014d8 ) 800140a: 6c1b ldr r3, [r3, #64] @ 0x40 800140c: 4a32 ldr r2, [pc, #200] @ (80014d8 ) 800140e: f043 0310 orr.w r3, r3, #16 8001412: 6413 str r3, [r2, #64] @ 0x40 8001414: 4b30 ldr r3, [pc, #192] @ (80014d8 ) 8001416: 6c1b ldr r3, [r3, #64] @ 0x40 8001418: f003 0310 and.w r3, r3, #16 800141c: 60fb str r3, [r7, #12] 800141e: 68fb ldr r3, [r7, #12] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); 8001420: f107 0210 add.w r2, r7, #16 8001424: f107 0314 add.w r3, r7, #20 8001428: 4611 mov r1, r2 800142a: 4618 mov r0, r3 800142c: f003 fd1a bl 8004e64 /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; 8001430: 6a3b ldr r3, [r7, #32] 8001432: 62fb str r3, [r7, #44] @ 0x2c /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) 8001434: 6afb ldr r3, [r7, #44] @ 0x2c 8001436: 2b00 cmp r3, #0 8001438: d103 bne.n 8001442 { uwTimclock = HAL_RCC_GetPCLK1Freq(); 800143a: f003 fceb bl 8004e14 800143e: 6378 str r0, [r7, #52] @ 0x34 8001440: e004 b.n 800144c } else { uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); 8001442: f003 fce7 bl 8004e14 8001446: 4603 mov r3, r0 8001448: 005b lsls r3, r3, #1 800144a: 637b str r3, [r7, #52] @ 0x34 } /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); 800144c: 6b7b ldr r3, [r7, #52] @ 0x34 800144e: 4a23 ldr r2, [pc, #140] @ (80014dc ) 8001450: fba2 2303 umull r2, r3, r2, r3 8001454: 0c9b lsrs r3, r3, #18 8001456: 3b01 subs r3, #1 8001458: 62bb str r3, [r7, #40] @ 0x28 /* Initialize TIM6 */ htim6.Instance = TIM6; 800145a: 4b21 ldr r3, [pc, #132] @ (80014e0 ) 800145c: 4a21 ldr r2, [pc, #132] @ (80014e4 ) 800145e: 601a str r2, [r3, #0] * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. * ClockDivision = 0 * Counter direction = Up */ htim6.Init.Period = (1000000U / 1000U) - 1U; 8001460: 4b1f ldr r3, [pc, #124] @ (80014e0 ) 8001462: f240 32e7 movw r2, #999 @ 0x3e7 8001466: 60da str r2, [r3, #12] htim6.Init.Prescaler = uwPrescalerValue; 8001468: 4a1d ldr r2, [pc, #116] @ (80014e0 ) 800146a: 6abb ldr r3, [r7, #40] @ 0x28 800146c: 6053 str r3, [r2, #4] htim6.Init.ClockDivision = 0; 800146e: 4b1c ldr r3, [pc, #112] @ (80014e0 ) 8001470: 2200 movs r2, #0 8001472: 611a str r2, [r3, #16] htim6.Init.CounterMode = TIM_COUNTERMODE_UP; 8001474: 4b1a ldr r3, [pc, #104] @ (80014e0 ) 8001476: 2200 movs r2, #0 8001478: 609a str r2, [r3, #8] htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800147a: 4b19 ldr r3, [pc, #100] @ (80014e0 ) 800147c: 2200 movs r2, #0 800147e: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim6); 8001480: 4817 ldr r0, [pc, #92] @ (80014e0 ) 8001482: f003 ff9e bl 80053c2 8001486: 4603 mov r3, r0 8001488: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 800148c: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 8001490: 2b00 cmp r3, #0 8001492: d11b bne.n 80014cc { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim6); 8001494: 4812 ldr r0, [pc, #72] @ (80014e0 ) 8001496: f003 ffe3 bl 8005460 800149a: 4603 mov r3, r0 800149c: f887 3033 strb.w r3, [r7, #51] @ 0x33 if (status == HAL_OK) 80014a0: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 80014a4: 2b00 cmp r3, #0 80014a6: d111 bne.n 80014cc { /* Enable the TIM6 global Interrupt */ HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); 80014a8: 2036 movs r0, #54 @ 0x36 80014aa: f000 f9d9 bl 8001860 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 80014ae: 687b ldr r3, [r7, #4] 80014b0: 2b0f cmp r3, #15 80014b2: d808 bhi.n 80014c6 { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); 80014b4: 2200 movs r2, #0 80014b6: 6879 ldr r1, [r7, #4] 80014b8: 2036 movs r0, #54 @ 0x36 80014ba: f000 f9b5 bl 8001828 uwTickPrio = TickPriority; 80014be: 4a0a ldr r2, [pc, #40] @ (80014e8 ) 80014c0: 687b ldr r3, [r7, #4] 80014c2: 6013 str r3, [r2, #0] 80014c4: e002 b.n 80014cc } else { status = HAL_ERROR; 80014c6: 2301 movs r3, #1 80014c8: f887 3033 strb.w r3, [r7, #51] @ 0x33 } } } /* Return function status */ return status; 80014cc: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 } 80014d0: 4618 mov r0, r3 80014d2: 3738 adds r7, #56 @ 0x38 80014d4: 46bd mov sp, r7 80014d6: bd80 pop {r7, pc} 80014d8: 40023800 .word 0x40023800 80014dc: 431bde83 .word 0x431bde83 80014e0: 20000290 .word 0x20000290 80014e4: 40001000 .word 0x40001000 80014e8: 20000004 .word 0x20000004 080014ec : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 80014ec: b480 push {r7} 80014ee: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 80014f0: bf00 nop 80014f2: e7fd b.n 80014f0 080014f4 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 80014f4: b480 push {r7} 80014f6: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 80014f8: bf00 nop 80014fa: e7fd b.n 80014f8 080014fc : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 80014fc: b480 push {r7} 80014fe: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) 8001500: bf00 nop 8001502: e7fd b.n 8001500 08001504 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { 8001504: b480 push {r7} 8001506: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) 8001508: bf00 nop 800150a: e7fd b.n 8001508 0800150c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 800150c: b480 push {r7} 800150e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) 8001510: bf00 nop 8001512: e7fd b.n 8001510 08001514 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001514: b480 push {r7} 8001516: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001518: bf00 nop 800151a: 46bd mov sp, r7 800151c: f85d 7b04 ldr.w r7, [sp], #4 8001520: 4770 bx lr ... 08001524 : /** * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. */ void TIM6_DAC_IRQHandler(void) { 8001524: b580 push {r7, lr} 8001526: af00 add r7, sp, #0 /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ /* USER CODE END TIM6_DAC_IRQn 0 */ HAL_TIM_IRQHandler(&htim6); 8001528: 4802 ldr r0, [pc, #8] @ (8001534 ) 800152a: f004 f809 bl 8005540 /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ /* USER CODE END TIM6_DAC_IRQn 1 */ } 800152e: bf00 nop 8001530: bd80 pop {r7, pc} 8001532: bf00 nop 8001534: 20000290 .word 0x20000290 08001538 : /** * @brief This function handles USB On The Go HS global interrupt. */ void OTG_HS_IRQHandler(void) { 8001538: b580 push {r7, lr} 800153a: af00 add r7, sp, #0 /* USER CODE BEGIN OTG_HS_IRQn 0 */ /* USER CODE END OTG_HS_IRQn 0 */ HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS); 800153c: 4802 ldr r0, [pc, #8] @ (8001548 ) 800153e: f000 fd82 bl 8002046 /* USER CODE BEGIN OTG_HS_IRQn 1 */ /* USER CODE END OTG_HS_IRQn 1 */ } 8001542: bf00 nop 8001544: bd80 pop {r7, pc} 8001546: bf00 nop 8001548: 200003c8 .word 0x200003c8 0800154c : /** * @brief This function handles LTDC global interrupt. */ void LTDC_IRQHandler(void) { 800154c: b580 push {r7, lr} 800154e: af00 add r7, sp, #0 /* USER CODE BEGIN LTDC_IRQn 0 */ /* USER CODE END LTDC_IRQn 0 */ HAL_LTDC_IRQHandler(&hltdc); 8001550: 4802 ldr r0, [pc, #8] @ (800155c ) 8001552: f002 fd7b bl 800404c /* USER CODE BEGIN LTDC_IRQn 1 */ /* USER CODE END LTDC_IRQn 1 */ } 8001556: bf00 nop 8001558: bd80 pop {r7, pc} 800155a: bf00 nop 800155c: 200000c8 .word 0x200000c8 08001560 : /** * @brief This function handles DMA2D global interrupt. */ void DMA2D_IRQHandler(void) { 8001560: b580 push {r7, lr} 8001562: af00 add r7, sp, #0 /* USER CODE BEGIN DMA2D_IRQn 0 */ /* USER CODE END DMA2D_IRQn 0 */ HAL_DMA2D_IRQHandler(&hdma2d); 8001564: 4802 ldr r0, [pc, #8] @ (8001570 ) 8001566: f000 f9ee bl 8001946 /* USER CODE BEGIN DMA2D_IRQn 1 */ /* USER CODE END DMA2D_IRQn 1 */ } 800156a: bf00 nop 800156c: bd80 pop {r7, pc} 800156e: bf00 nop 8001570: 20000034 .word 0x20000034 08001574 : * configuration. * @param None * @retval None */ void SystemInit(void) { 8001574: b480 push {r7} 8001576: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001578: 4b06 ldr r3, [pc, #24] @ (8001594 ) 800157a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800157e: 4a05 ldr r2, [pc, #20] @ (8001594 ) 8001580: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000 8001584: f8c2 3088 str.w r3, [r2, #136] @ 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } 8001588: bf00 nop 800158a: 46bd mov sp, r7 800158c: f85d 7b04 ldr.w r7, [sp], #4 8001590: 4770 bx lr 8001592: bf00 nop 8001594: e000ed00 .word 0xe000ed00 08001598 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ 8001598: f8df d034 ldr.w sp, [pc, #52] @ 80015d0 /* Call the clock system initialization function.*/ bl SystemInit 800159c: f7ff ffea bl 8001574 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata 80015a0: 480c ldr r0, [pc, #48] @ (80015d4 ) ldr r1, =_edata 80015a2: 490d ldr r1, [pc, #52] @ (80015d8 ) ldr r2, =_sidata 80015a4: 4a0d ldr r2, [pc, #52] @ (80015dc ) movs r3, #0 80015a6: 2300 movs r3, #0 b LoopCopyDataInit 80015a8: e002 b.n 80015b0 080015aa : CopyDataInit: ldr r4, [r2, r3] 80015aa: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] 80015ac: 50c4 str r4, [r0, r3] adds r3, r3, #4 80015ae: 3304 adds r3, #4 080015b0 : LoopCopyDataInit: adds r4, r0, r3 80015b0: 18c4 adds r4, r0, r3 cmp r4, r1 80015b2: 428c cmp r4, r1 bcc CopyDataInit 80015b4: d3f9 bcc.n 80015aa /* Zero fill the bss segment. */ ldr r2, =_sbss 80015b6: 4a0a ldr r2, [pc, #40] @ (80015e0 ) ldr r4, =_ebss 80015b8: 4c0a ldr r4, [pc, #40] @ (80015e4 ) movs r3, #0 80015ba: 2300 movs r3, #0 b LoopFillZerobss 80015bc: e001 b.n 80015c2 080015be : FillZerobss: str r3, [r2] 80015be: 6013 str r3, [r2, #0] adds r2, r2, #4 80015c0: 3204 adds r2, #4 080015c2 : LoopFillZerobss: cmp r2, r4 80015c2: 42a2 cmp r2, r4 bcc FillZerobss 80015c4: d3fb bcc.n 80015be /* Call static constructors */ bl __libc_init_array 80015c6: f006 fc73 bl 8007eb0 <__libc_init_array> /* Call the application's entry point.*/ bl main 80015ca: f7fe ffee bl 80005aa
bx lr 80015ce: 4770 bx lr ldr sp, =_estack /* set stack pointer */ 80015d0: 20030000 .word 0x20030000 ldr r0, =_sdata 80015d4: 20000000 .word 0x20000000 ldr r1, =_edata 80015d8: 20000010 .word 0x20000010 ldr r2, =_sidata 80015dc: 08007f54 .word 0x08007f54 ldr r2, =_sbss 80015e0: 20000010 .word 0x20000010 ldr r4, =_ebss 80015e4: 200007a8 .word 0x200007a8 080015e8 : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 80015e8: e7fe b.n 80015e8 ... 080015ec : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 80015ec: b580 push {r7, lr} 80015ee: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 80015f0: 4b0e ldr r3, [pc, #56] @ (800162c ) 80015f2: 681b ldr r3, [r3, #0] 80015f4: 4a0d ldr r2, [pc, #52] @ (800162c ) 80015f6: f443 7300 orr.w r3, r3, #512 @ 0x200 80015fa: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); 80015fc: 4b0b ldr r3, [pc, #44] @ (800162c ) 80015fe: 681b ldr r3, [r3, #0] 8001600: 4a0a ldr r2, [pc, #40] @ (800162c ) 8001602: f443 6380 orr.w r3, r3, #1024 @ 0x400 8001606: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); 8001608: 4b08 ldr r3, [pc, #32] @ (800162c ) 800160a: 681b ldr r3, [r3, #0] 800160c: 4a07 ldr r2, [pc, #28] @ (800162c ) 800160e: f443 7380 orr.w r3, r3, #256 @ 0x100 8001612: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001614: 2003 movs r0, #3 8001616: f000 f8fc bl 8001812 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); 800161a: 2000 movs r0, #0 800161c: f7ff feea bl 80013f4 /* Init the low level hardware */ HAL_MspInit(); 8001620: f7ff fb8a bl 8000d38 /* Return function status */ return HAL_OK; 8001624: 2300 movs r3, #0 } 8001626: 4618 mov r0, r3 8001628: bd80 pop {r7, pc} 800162a: bf00 nop 800162c: 40023c00 .word 0x40023c00 08001630 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 8001630: b480 push {r7} 8001632: af00 add r7, sp, #0 uwTick += uwTickFreq; 8001634: 4b06 ldr r3, [pc, #24] @ (8001650 ) 8001636: 781b ldrb r3, [r3, #0] 8001638: 461a mov r2, r3 800163a: 4b06 ldr r3, [pc, #24] @ (8001654 ) 800163c: 681b ldr r3, [r3, #0] 800163e: 4413 add r3, r2 8001640: 4a04 ldr r2, [pc, #16] @ (8001654 ) 8001642: 6013 str r3, [r2, #0] } 8001644: bf00 nop 8001646: 46bd mov sp, r7 8001648: f85d 7b04 ldr.w r7, [sp], #4 800164c: 4770 bx lr 800164e: bf00 nop 8001650: 20000008 .word 0x20000008 8001654: 200002d8 .word 0x200002d8 08001658 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 8001658: b480 push {r7} 800165a: af00 add r7, sp, #0 return uwTick; 800165c: 4b03 ldr r3, [pc, #12] @ (800166c ) 800165e: 681b ldr r3, [r3, #0] } 8001660: 4618 mov r0, r3 8001662: 46bd mov sp, r7 8001664: f85d 7b04 ldr.w r7, [sp], #4 8001668: 4770 bx lr 800166a: bf00 nop 800166c: 200002d8 .word 0x200002d8 08001670 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 8001670: b580 push {r7, lr} 8001672: b084 sub sp, #16 8001674: af00 add r7, sp, #0 8001676: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 8001678: f7ff ffee bl 8001658 800167c: 60b8 str r0, [r7, #8] uint32_t wait = Delay; 800167e: 687b ldr r3, [r7, #4] 8001680: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8001682: 68fb ldr r3, [r7, #12] 8001684: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8001688: d005 beq.n 8001696 { wait += (uint32_t)(uwTickFreq); 800168a: 4b0a ldr r3, [pc, #40] @ (80016b4 ) 800168c: 781b ldrb r3, [r3, #0] 800168e: 461a mov r2, r3 8001690: 68fb ldr r3, [r7, #12] 8001692: 4413 add r3, r2 8001694: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) 8001696: bf00 nop 8001698: f7ff ffde bl 8001658 800169c: 4602 mov r2, r0 800169e: 68bb ldr r3, [r7, #8] 80016a0: 1ad3 subs r3, r2, r3 80016a2: 68fa ldr r2, [r7, #12] 80016a4: 429a cmp r2, r3 80016a6: d8f7 bhi.n 8001698 { } } 80016a8: bf00 nop 80016aa: bf00 nop 80016ac: 3710 adds r7, #16 80016ae: 46bd mov sp, r7 80016b0: bd80 pop {r7, pc} 80016b2: bf00 nop 80016b4: 20000008 .word 0x20000008 080016b8 <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 80016b8: b480 push {r7} 80016ba: b085 sub sp, #20 80016bc: af00 add r7, sp, #0 80016be: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80016c0: 687b ldr r3, [r7, #4] 80016c2: f003 0307 and.w r3, r3, #7 80016c6: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 80016c8: 4b0c ldr r3, [pc, #48] @ (80016fc <__NVIC_SetPriorityGrouping+0x44>) 80016ca: 68db ldr r3, [r3, #12] 80016cc: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 80016ce: 68ba ldr r2, [r7, #8] 80016d0: f64f 03ff movw r3, #63743 @ 0xf8ff 80016d4: 4013 ands r3, r2 80016d6: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ 80016d8: 68fb ldr r3, [r7, #12] 80016da: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 80016dc: 68bb ldr r3, [r7, #8] 80016de: 4313 orrs r3, r2 reg_value = (reg_value | 80016e0: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000 80016e4: f443 3300 orr.w r3, r3, #131072 @ 0x20000 80016e8: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; 80016ea: 4a04 ldr r2, [pc, #16] @ (80016fc <__NVIC_SetPriorityGrouping+0x44>) 80016ec: 68bb ldr r3, [r7, #8] 80016ee: 60d3 str r3, [r2, #12] } 80016f0: bf00 nop 80016f2: 3714 adds r7, #20 80016f4: 46bd mov sp, r7 80016f6: f85d 7b04 ldr.w r7, [sp], #4 80016fa: 4770 bx lr 80016fc: e000ed00 .word 0xe000ed00 08001700 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { 8001700: b480 push {r7} 8001702: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 8001704: 4b04 ldr r3, [pc, #16] @ (8001718 <__NVIC_GetPriorityGrouping+0x18>) 8001706: 68db ldr r3, [r3, #12] 8001708: 0a1b lsrs r3, r3, #8 800170a: f003 0307 and.w r3, r3, #7 } 800170e: 4618 mov r0, r3 8001710: 46bd mov sp, r7 8001712: f85d 7b04 ldr.w r7, [sp], #4 8001716: 4770 bx lr 8001718: e000ed00 .word 0xe000ed00 0800171c <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { 800171c: b480 push {r7} 800171e: b083 sub sp, #12 8001720: af00 add r7, sp, #0 8001722: 4603 mov r3, r0 8001724: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001726: f997 3007 ldrsb.w r3, [r7, #7] 800172a: 2b00 cmp r3, #0 800172c: db0b blt.n 8001746 <__NVIC_EnableIRQ+0x2a> { __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 800172e: 79fb ldrb r3, [r7, #7] 8001730: f003 021f and.w r2, r3, #31 8001734: 4907 ldr r1, [pc, #28] @ (8001754 <__NVIC_EnableIRQ+0x38>) 8001736: f997 3007 ldrsb.w r3, [r7, #7] 800173a: 095b lsrs r3, r3, #5 800173c: 2001 movs r0, #1 800173e: fa00 f202 lsl.w r2, r0, r2 8001742: f841 2023 str.w r2, [r1, r3, lsl #2] __COMPILER_BARRIER(); } } 8001746: bf00 nop 8001748: 370c adds r7, #12 800174a: 46bd mov sp, r7 800174c: f85d 7b04 ldr.w r7, [sp], #4 8001750: 4770 bx lr 8001752: bf00 nop 8001754: e000e100 .word 0xe000e100 08001758 <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8001758: b480 push {r7} 800175a: b083 sub sp, #12 800175c: af00 add r7, sp, #0 800175e: 4603 mov r3, r0 8001760: 6039 str r1, [r7, #0] 8001762: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) 8001764: f997 3007 ldrsb.w r3, [r7, #7] 8001768: 2b00 cmp r3, #0 800176a: db0a blt.n 8001782 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 800176c: 683b ldr r3, [r7, #0] 800176e: b2da uxtb r2, r3 8001770: 490c ldr r1, [pc, #48] @ (80017a4 <__NVIC_SetPriority+0x4c>) 8001772: f997 3007 ldrsb.w r3, [r7, #7] 8001776: 0112 lsls r2, r2, #4 8001778: b2d2 uxtb r2, r2 800177a: 440b add r3, r1 800177c: f883 2300 strb.w r2, [r3, #768] @ 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } 8001780: e00a b.n 8001798 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8001782: 683b ldr r3, [r7, #0] 8001784: b2da uxtb r2, r3 8001786: 4908 ldr r1, [pc, #32] @ (80017a8 <__NVIC_SetPriority+0x50>) 8001788: 79fb ldrb r3, [r7, #7] 800178a: f003 030f and.w r3, r3, #15 800178e: 3b04 subs r3, #4 8001790: 0112 lsls r2, r2, #4 8001792: b2d2 uxtb r2, r2 8001794: 440b add r3, r1 8001796: 761a strb r2, [r3, #24] } 8001798: bf00 nop 800179a: 370c adds r7, #12 800179c: 46bd mov sp, r7 800179e: f85d 7b04 ldr.w r7, [sp], #4 80017a2: 4770 bx lr 80017a4: e000e100 .word 0xe000e100 80017a8: e000ed00 .word 0xe000ed00 080017ac : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80017ac: b480 push {r7} 80017ae: b089 sub sp, #36 @ 0x24 80017b0: af00 add r7, sp, #0 80017b2: 60f8 str r0, [r7, #12] 80017b4: 60b9 str r1, [r7, #8] 80017b6: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80017b8: 68fb ldr r3, [r7, #12] 80017ba: f003 0307 and.w r3, r3, #7 80017be: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80017c0: 69fb ldr r3, [r7, #28] 80017c2: f1c3 0307 rsb r3, r3, #7 80017c6: 2b04 cmp r3, #4 80017c8: bf28 it cs 80017ca: 2304 movcs r3, #4 80017cc: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80017ce: 69fb ldr r3, [r7, #28] 80017d0: 3304 adds r3, #4 80017d2: 2b06 cmp r3, #6 80017d4: d902 bls.n 80017dc 80017d6: 69fb ldr r3, [r7, #28] 80017d8: 3b03 subs r3, #3 80017da: e000 b.n 80017de 80017dc: 2300 movs r3, #0 80017de: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80017e0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80017e4: 69bb ldr r3, [r7, #24] 80017e6: fa02 f303 lsl.w r3, r2, r3 80017ea: 43da mvns r2, r3 80017ec: 68bb ldr r3, [r7, #8] 80017ee: 401a ands r2, r3 80017f0: 697b ldr r3, [r7, #20] 80017f2: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 80017f4: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff 80017f8: 697b ldr r3, [r7, #20] 80017fa: fa01 f303 lsl.w r3, r1, r3 80017fe: 43d9 mvns r1, r3 8001800: 687b ldr r3, [r7, #4] 8001802: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 8001804: 4313 orrs r3, r2 ); } 8001806: 4618 mov r0, r3 8001808: 3724 adds r7, #36 @ 0x24 800180a: 46bd mov sp, r7 800180c: f85d 7b04 ldr.w r7, [sp], #4 8001810: 4770 bx lr 08001812 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8001812: b580 push {r7, lr} 8001814: b082 sub sp, #8 8001816: af00 add r7, sp, #0 8001818: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 800181a: 6878 ldr r0, [r7, #4] 800181c: f7ff ff4c bl 80016b8 <__NVIC_SetPriorityGrouping> } 8001820: bf00 nop 8001822: 3708 adds r7, #8 8001824: 46bd mov sp, r7 8001826: bd80 pop {r7, pc} 08001828 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8001828: b580 push {r7, lr} 800182a: b086 sub sp, #24 800182c: af00 add r7, sp, #0 800182e: 4603 mov r3, r0 8001830: 60b9 str r1, [r7, #8] 8001832: 607a str r2, [r7, #4] 8001834: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; 8001836: 2300 movs r3, #0 8001838: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 800183a: f7ff ff61 bl 8001700 <__NVIC_GetPriorityGrouping> 800183e: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 8001840: 687a ldr r2, [r7, #4] 8001842: 68b9 ldr r1, [r7, #8] 8001844: 6978 ldr r0, [r7, #20] 8001846: f7ff ffb1 bl 80017ac 800184a: 4602 mov r2, r0 800184c: f997 300f ldrsb.w r3, [r7, #15] 8001850: 4611 mov r1, r2 8001852: 4618 mov r0, r3 8001854: f7ff ff80 bl 8001758 <__NVIC_SetPriority> } 8001858: bf00 nop 800185a: 3718 adds r7, #24 800185c: 46bd mov sp, r7 800185e: bd80 pop {r7, pc} 08001860 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 8001860: b580 push {r7, lr} 8001862: b082 sub sp, #8 8001864: af00 add r7, sp, #0 8001866: 4603 mov r3, r0 8001868: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 800186a: f997 3007 ldrsb.w r3, [r7, #7] 800186e: 4618 mov r0, r3 8001870: f7ff ff54 bl 800171c <__NVIC_EnableIRQ> } 8001874: bf00 nop 8001876: 3708 adds r7, #8 8001878: 46bd mov sp, r7 800187a: bd80 pop {r7, pc} 0800187c : * parameters in the CRC_InitTypeDef and create the associated handle. * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { 800187c: b580 push {r7, lr} 800187e: b082 sub sp, #8 8001880: af00 add r7, sp, #0 8001882: 6078 str r0, [r7, #4] /* Check the CRC handle allocation */ if (hcrc == NULL) 8001884: 687b ldr r3, [r7, #4] 8001886: 2b00 cmp r3, #0 8001888: d101 bne.n 800188e { return HAL_ERROR; 800188a: 2301 movs r3, #1 800188c: e00e b.n 80018ac } /* Check the parameters */ assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if (hcrc->State == HAL_CRC_STATE_RESET) 800188e: 687b ldr r3, [r7, #4] 8001890: 795b ldrb r3, [r3, #5] 8001892: b2db uxtb r3, r3 8001894: 2b00 cmp r3, #0 8001896: d105 bne.n 80018a4 { /* Allocate lock resource and initialize it */ hcrc->Lock = HAL_UNLOCKED; 8001898: 687b ldr r3, [r7, #4] 800189a: 2200 movs r2, #0 800189c: 711a strb r2, [r3, #4] /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); 800189e: 6878 ldr r0, [r7, #4] 80018a0: f7ff fa76 bl 8000d90 } /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_READY; 80018a4: 687b ldr r3, [r7, #4] 80018a6: 2201 movs r2, #1 80018a8: 715a strb r2, [r3, #5] /* Return function status */ return HAL_OK; 80018aa: 2300 movs r3, #0 } 80018ac: 4618 mov r0, r3 80018ae: 3708 adds r7, #8 80018b0: 46bd mov sp, r7 80018b2: bd80 pop {r7, pc} 080018b4 : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) { 80018b4: b580 push {r7, lr} 80018b6: b082 sub sp, #8 80018b8: af00 add r7, sp, #0 80018ba: 6078 str r0, [r7, #4] /* Check the DMA2D peripheral state */ if (hdma2d == NULL) 80018bc: 687b ldr r3, [r7, #4] 80018be: 2b00 cmp r3, #0 80018c0: d101 bne.n 80018c6 { return HAL_ERROR; 80018c2: 2301 movs r3, #1 80018c4: e03b b.n 800193e /* Init the low level hardware */ hdma2d->MspInitCallback(hdma2d); } #else if (hdma2d->State == HAL_DMA2D_STATE_RESET) 80018c6: 687b ldr r3, [r7, #4] 80018c8: f893 3039 ldrb.w r3, [r3, #57] @ 0x39 80018cc: b2db uxtb r3, r3 80018ce: 2b00 cmp r3, #0 80018d0: d106 bne.n 80018e0 { /* Allocate lock resource and initialize it */ hdma2d->Lock = HAL_UNLOCKED; 80018d2: 687b ldr r3, [r7, #4] 80018d4: 2200 movs r2, #0 80018d6: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Init the low level hardware */ HAL_DMA2D_MspInit(hdma2d); 80018da: 6878 ldr r0, [r7, #4] 80018dc: f7ff fa7a bl 8000dd4 } #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; 80018e0: 687b ldr r3, [r7, #4] 80018e2: 2202 movs r2, #2 80018e4: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* DMA2D CR register configuration -------------------------------------------*/ MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); 80018e8: 687b ldr r3, [r7, #4] 80018ea: 681b ldr r3, [r3, #0] 80018ec: 681b ldr r3, [r3, #0] 80018ee: f423 3140 bic.w r1, r3, #196608 @ 0x30000 80018f2: 687b ldr r3, [r7, #4] 80018f4: 685a ldr r2, [r3, #4] 80018f6: 687b ldr r3, [r7, #4] 80018f8: 681b ldr r3, [r3, #0] 80018fa: 430a orrs r2, r1 80018fc: 601a str r2, [r3, #0] /* DMA2D OPFCCR register configuration ---------------------------------------*/ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); 80018fe: 687b ldr r3, [r7, #4] 8001900: 681b ldr r3, [r3, #0] 8001902: 6b5b ldr r3, [r3, #52] @ 0x34 8001904: f023 0107 bic.w r1, r3, #7 8001908: 687b ldr r3, [r7, #4] 800190a: 689a ldr r2, [r3, #8] 800190c: 687b ldr r3, [r7, #4] 800190e: 681b ldr r3, [r3, #0] 8001910: 430a orrs r2, r1 8001912: 635a str r2, [r3, #52] @ 0x34 /* DMA2D OOR register configuration ------------------------------------------*/ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); 8001914: 687b ldr r3, [r7, #4] 8001916: 681b ldr r3, [r3, #0] 8001918: 6c1b ldr r3, [r3, #64] @ 0x40 800191a: f423 537f bic.w r3, r3, #16320 @ 0x3fc0 800191e: f023 033f bic.w r3, r3, #63 @ 0x3f 8001922: 687a ldr r2, [r7, #4] 8001924: 68d1 ldr r1, [r2, #12] 8001926: 687a ldr r2, [r7, #4] 8001928: 6812 ldr r2, [r2, #0] 800192a: 430b orrs r3, r1 800192c: 6413 str r3, [r2, #64] @ 0x40 /* Update error code */ hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; 800192e: 687b ldr r3, [r7, #4] 8001930: 2200 movs r2, #0 8001932: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; 8001934: 687b ldr r3, [r7, #4] 8001936: 2201 movs r2, #1 8001938: f883 2039 strb.w r2, [r3, #57] @ 0x39 return HAL_OK; 800193c: 2300 movs r3, #0 } 800193e: 4618 mov r0, r3 8001940: 3708 adds r7, #8 8001942: 46bd mov sp, r7 8001944: bd80 pop {r7, pc} 08001946 : * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval HAL status */ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) { 8001946: b580 push {r7, lr} 8001948: b084 sub sp, #16 800194a: af00 add r7, sp, #0 800194c: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); 800194e: 687b ldr r3, [r7, #4] 8001950: 681b ldr r3, [r3, #0] 8001952: 685b ldr r3, [r3, #4] 8001954: 60fb str r3, [r7, #12] uint32_t crflags = READ_REG(hdma2d->Instance->CR); 8001956: 687b ldr r3, [r7, #4] 8001958: 681b ldr r3, [r3, #0] 800195a: 681b ldr r3, [r3, #0] 800195c: 60bb str r3, [r7, #8] /* Transfer Error Interrupt management ***************************************/ if ((isrflags & DMA2D_FLAG_TE) != 0U) 800195e: 68fb ldr r3, [r7, #12] 8001960: f003 0301 and.w r3, r3, #1 8001964: 2b00 cmp r3, #0 8001966: d026 beq.n 80019b6 { if ((crflags & DMA2D_IT_TE) != 0U) 8001968: 68bb ldr r3, [r7, #8] 800196a: f403 7380 and.w r3, r3, #256 @ 0x100 800196e: 2b00 cmp r3, #0 8001970: d021 beq.n 80019b6 { /* Disable the transfer Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); 8001972: 687b ldr r3, [r7, #4] 8001974: 681b ldr r3, [r3, #0] 8001976: 681a ldr r2, [r3, #0] 8001978: 687b ldr r3, [r7, #4] 800197a: 681b ldr r3, [r3, #0] 800197c: f422 7280 bic.w r2, r2, #256 @ 0x100 8001980: 601a str r2, [r3, #0] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; 8001982: 687b ldr r3, [r7, #4] 8001984: 6bdb ldr r3, [r3, #60] @ 0x3c 8001986: f043 0201 orr.w r2, r3, #1 800198a: 687b ldr r3, [r7, #4] 800198c: 63da str r2, [r3, #60] @ 0x3c /* Clear the transfer error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); 800198e: 687b ldr r3, [r7, #4] 8001990: 681b ldr r3, [r3, #0] 8001992: 2201 movs r2, #1 8001994: 609a str r2, [r3, #8] /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 8001996: 687b ldr r3, [r7, #4] 8001998: 2204 movs r2, #4 800199a: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 800199e: 687b ldr r3, [r7, #4] 80019a0: 2200 movs r2, #0 80019a2: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 80019a6: 687b ldr r3, [r7, #4] 80019a8: 695b ldr r3, [r3, #20] 80019aa: 2b00 cmp r3, #0 80019ac: d003 beq.n 80019b6 { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 80019ae: 687b ldr r3, [r7, #4] 80019b0: 695b ldr r3, [r3, #20] 80019b2: 6878 ldr r0, [r7, #4] 80019b4: 4798 blx r3 } } } /* Configuration Error Interrupt management **********************************/ if ((isrflags & DMA2D_FLAG_CE) != 0U) 80019b6: 68fb ldr r3, [r7, #12] 80019b8: f003 0320 and.w r3, r3, #32 80019bc: 2b00 cmp r3, #0 80019be: d026 beq.n 8001a0e { if ((crflags & DMA2D_IT_CE) != 0U) 80019c0: 68bb ldr r3, [r7, #8] 80019c2: f403 5300 and.w r3, r3, #8192 @ 0x2000 80019c6: 2b00 cmp r3, #0 80019c8: d021 beq.n 8001a0e { /* Disable the Configuration Error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); 80019ca: 687b ldr r3, [r7, #4] 80019cc: 681b ldr r3, [r3, #0] 80019ce: 681a ldr r2, [r3, #0] 80019d0: 687b ldr r3, [r7, #4] 80019d2: 681b ldr r3, [r3, #0] 80019d4: f422 5200 bic.w r2, r2, #8192 @ 0x2000 80019d8: 601a str r2, [r3, #0] /* Clear the Configuration error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); 80019da: 687b ldr r3, [r7, #4] 80019dc: 681b ldr r3, [r3, #0] 80019de: 2220 movs r2, #32 80019e0: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; 80019e2: 687b ldr r3, [r7, #4] 80019e4: 6bdb ldr r3, [r3, #60] @ 0x3c 80019e6: f043 0202 orr.w r2, r3, #2 80019ea: 687b ldr r3, [r7, #4] 80019ec: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 80019ee: 687b ldr r3, [r7, #4] 80019f0: 2204 movs r2, #4 80019f2: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 80019f6: 687b ldr r3, [r7, #4] 80019f8: 2200 movs r2, #0 80019fa: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 80019fe: 687b ldr r3, [r7, #4] 8001a00: 695b ldr r3, [r3, #20] 8001a02: 2b00 cmp r3, #0 8001a04: d003 beq.n 8001a0e { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 8001a06: 687b ldr r3, [r7, #4] 8001a08: 695b ldr r3, [r3, #20] 8001a0a: 6878 ldr r0, [r7, #4] 8001a0c: 4798 blx r3 } } } /* CLUT access Error Interrupt management ***********************************/ if ((isrflags & DMA2D_FLAG_CAE) != 0U) 8001a0e: 68fb ldr r3, [r7, #12] 8001a10: f003 0308 and.w r3, r3, #8 8001a14: 2b00 cmp r3, #0 8001a16: d026 beq.n 8001a66 { if ((crflags & DMA2D_IT_CAE) != 0U) 8001a18: 68bb ldr r3, [r7, #8] 8001a1a: f403 6300 and.w r3, r3, #2048 @ 0x800 8001a1e: 2b00 cmp r3, #0 8001a20: d021 beq.n 8001a66 { /* Disable the CLUT access error interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); 8001a22: 687b ldr r3, [r7, #4] 8001a24: 681b ldr r3, [r3, #0] 8001a26: 681a ldr r2, [r3, #0] 8001a28: 687b ldr r3, [r7, #4] 8001a2a: 681b ldr r3, [r3, #0] 8001a2c: f422 6200 bic.w r2, r2, #2048 @ 0x800 8001a30: 601a str r2, [r3, #0] /* Clear the CLUT access error flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); 8001a32: 687b ldr r3, [r7, #4] 8001a34: 681b ldr r3, [r3, #0] 8001a36: 2208 movs r2, #8 8001a38: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; 8001a3a: 687b ldr r3, [r7, #4] 8001a3c: 6bdb ldr r3, [r3, #60] @ 0x3c 8001a3e: f043 0204 orr.w r2, r3, #4 8001a42: 687b ldr r3, [r7, #4] 8001a44: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_ERROR; 8001a46: 687b ldr r3, [r7, #4] 8001a48: 2204 movs r2, #4 8001a4a: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001a4e: 687b ldr r3, [r7, #4] 8001a50: 2200 movs r2, #0 8001a52: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferErrorCallback != NULL) 8001a56: 687b ldr r3, [r7, #4] 8001a58: 695b ldr r3, [r3, #20] 8001a5a: 2b00 cmp r3, #0 8001a5c: d003 beq.n 8001a66 { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); 8001a5e: 687b ldr r3, [r7, #4] 8001a60: 695b ldr r3, [r3, #20] 8001a62: 6878 ldr r0, [r7, #4] 8001a64: 4798 blx r3 } } } /* Transfer watermark Interrupt management **********************************/ if ((isrflags & DMA2D_FLAG_TW) != 0U) 8001a66: 68fb ldr r3, [r7, #12] 8001a68: f003 0304 and.w r3, r3, #4 8001a6c: 2b00 cmp r3, #0 8001a6e: d013 beq.n 8001a98 { if ((crflags & DMA2D_IT_TW) != 0U) 8001a70: 68bb ldr r3, [r7, #8] 8001a72: f403 6380 and.w r3, r3, #1024 @ 0x400 8001a76: 2b00 cmp r3, #0 8001a78: d00e beq.n 8001a98 { /* Disable the transfer watermark interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); 8001a7a: 687b ldr r3, [r7, #4] 8001a7c: 681b ldr r3, [r3, #0] 8001a7e: 681a ldr r2, [r3, #0] 8001a80: 687b ldr r3, [r7, #4] 8001a82: 681b ldr r3, [r3, #0] 8001a84: f422 6280 bic.w r2, r2, #1024 @ 0x400 8001a88: 601a str r2, [r3, #0] /* Clear the transfer watermark flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); 8001a8a: 687b ldr r3, [r7, #4] 8001a8c: 681b ldr r3, [r3, #0] 8001a8e: 2204 movs r2, #4 8001a90: 609a str r2, [r3, #8] /* Transfer watermark Callback */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) hdma2d->LineEventCallback(hdma2d); #else HAL_DMA2D_LineEventCallback(hdma2d); 8001a92: 6878 ldr r0, [r7, #4] 8001a94: f000 f853 bl 8001b3e #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } } /* Transfer Complete Interrupt management ************************************/ if ((isrflags & DMA2D_FLAG_TC) != 0U) 8001a98: 68fb ldr r3, [r7, #12] 8001a9a: f003 0302 and.w r3, r3, #2 8001a9e: 2b00 cmp r3, #0 8001aa0: d024 beq.n 8001aec { if ((crflags & DMA2D_IT_TC) != 0U) 8001aa2: 68bb ldr r3, [r7, #8] 8001aa4: f403 7300 and.w r3, r3, #512 @ 0x200 8001aa8: 2b00 cmp r3, #0 8001aaa: d01f beq.n 8001aec { /* Disable the transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); 8001aac: 687b ldr r3, [r7, #4] 8001aae: 681b ldr r3, [r3, #0] 8001ab0: 681a ldr r2, [r3, #0] 8001ab2: 687b ldr r3, [r7, #4] 8001ab4: 681b ldr r3, [r3, #0] 8001ab6: f422 7200 bic.w r2, r2, #512 @ 0x200 8001aba: 601a str r2, [r3, #0] /* Clear the transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); 8001abc: 687b ldr r3, [r7, #4] 8001abe: 681b ldr r3, [r3, #0] 8001ac0: 2202 movs r2, #2 8001ac2: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; 8001ac4: 687b ldr r3, [r7, #4] 8001ac6: 6bda ldr r2, [r3, #60] @ 0x3c 8001ac8: 687b ldr r3, [r7, #4] 8001aca: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; 8001acc: 687b ldr r3, [r7, #4] 8001ace: 2201 movs r2, #1 8001ad0: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001ad4: 687b ldr r3, [r7, #4] 8001ad6: 2200 movs r2, #0 8001ad8: f883 2038 strb.w r2, [r3, #56] @ 0x38 if (hdma2d->XferCpltCallback != NULL) 8001adc: 687b ldr r3, [r7, #4] 8001ade: 691b ldr r3, [r3, #16] 8001ae0: 2b00 cmp r3, #0 8001ae2: d003 beq.n 8001aec { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); 8001ae4: 687b ldr r3, [r7, #4] 8001ae6: 691b ldr r3, [r3, #16] 8001ae8: 6878 ldr r0, [r7, #4] 8001aea: 4798 blx r3 } } } /* CLUT Transfer Complete Interrupt management ******************************/ if ((isrflags & DMA2D_FLAG_CTC) != 0U) 8001aec: 68fb ldr r3, [r7, #12] 8001aee: f003 0310 and.w r3, r3, #16 8001af2: 2b00 cmp r3, #0 8001af4: d01f beq.n 8001b36 { if ((crflags & DMA2D_IT_CTC) != 0U) 8001af6: 68bb ldr r3, [r7, #8] 8001af8: f403 5380 and.w r3, r3, #4096 @ 0x1000 8001afc: 2b00 cmp r3, #0 8001afe: d01a beq.n 8001b36 { /* Disable the CLUT transfer complete interrupt */ __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); 8001b00: 687b ldr r3, [r7, #4] 8001b02: 681b ldr r3, [r3, #0] 8001b04: 681a ldr r2, [r3, #0] 8001b06: 687b ldr r3, [r7, #4] 8001b08: 681b ldr r3, [r3, #0] 8001b0a: f422 5280 bic.w r2, r2, #4096 @ 0x1000 8001b0e: 601a str r2, [r3, #0] /* Clear the CLUT transfer complete flag */ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); 8001b10: 687b ldr r3, [r7, #4] 8001b12: 681b ldr r3, [r3, #0] 8001b14: 2210 movs r2, #16 8001b16: 609a str r2, [r3, #8] /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; 8001b18: 687b ldr r3, [r7, #4] 8001b1a: 6bda ldr r2, [r3, #60] @ 0x3c 8001b1c: 687b ldr r3, [r7, #4] 8001b1e: 63da str r2, [r3, #60] @ 0x3c /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; 8001b20: 687b ldr r3, [r7, #4] 8001b22: 2201 movs r2, #1 8001b24: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process Unlocked */ __HAL_UNLOCK(hdma2d); 8001b28: 687b ldr r3, [r7, #4] 8001b2a: 2200 movs r2, #0 8001b2c: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* CLUT Transfer complete Callback */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) hdma2d->CLUTLoadingCpltCallback(hdma2d); #else HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); 8001b30: 6878 ldr r0, [r7, #4] 8001b32: f000 f80e bl 8001b52 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ } } } 8001b36: bf00 nop 8001b38: 3710 adds r7, #16 8001b3a: 46bd mov sp, r7 8001b3c: bd80 pop {r7, pc} 08001b3e : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) { 8001b3e: b480 push {r7} 8001b40: b083 sub sp, #12 8001b42: af00 add r7, sp, #0 8001b44: 6078 str r0, [r7, #4] UNUSED(hdma2d); /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_LineEventCallback can be implemented in the user file. */ } 8001b46: bf00 nop 8001b48: 370c adds r7, #12 8001b4a: 46bd mov sp, r7 8001b4c: f85d 7b04 ldr.w r7, [sp], #4 8001b50: 4770 bx lr 08001b52 : * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains * the configuration information for the DMA2D. * @retval None */ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) { 8001b52: b480 push {r7} 8001b54: b083 sub sp, #12 8001b56: af00 add r7, sp, #0 8001b58: 6078 str r0, [r7, #4] UNUSED(hdma2d); /* NOTE : This function should not be modified; when the callback is needed, the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. */ } 8001b5a: bf00 nop 8001b5c: 370c adds r7, #12 8001b5e: 46bd mov sp, r7 8001b60: f85d 7b04 ldr.w r7, [sp], #4 8001b64: 4770 bx lr ... 08001b68 : * This parameter can be one of the following values: * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { 8001b68: b480 push {r7} 8001b6a: b087 sub sp, #28 8001b6c: af00 add r7, sp, #0 8001b6e: 6078 str r0, [r7, #4] 8001b70: 6039 str r1, [r7, #0] uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); if (hdma2d->Init.Mode != DMA2D_R2M) 8001b72: 687b ldr r3, [r7, #4] 8001b74: 685b ldr r3, [r3, #4] 8001b76: f5b3 3f40 cmp.w r3, #196608 @ 0x30000 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } } /* Process locked */ __HAL_LOCK(hdma2d); 8001b7a: 687b ldr r3, [r7, #4] 8001b7c: f893 3038 ldrb.w r3, [r3, #56] @ 0x38 8001b80: 2b01 cmp r3, #1 8001b82: d101 bne.n 8001b88 8001b84: 2302 movs r3, #2 8001b86: e079 b.n 8001c7c 8001b88: 687b ldr r3, [r7, #4] 8001b8a: 2201 movs r2, #1 8001b8c: f883 2038 strb.w r2, [r3, #56] @ 0x38 /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; 8001b90: 687b ldr r3, [r7, #4] 8001b92: 2202 movs r2, #2 8001b94: f883 2039 strb.w r2, [r3, #57] @ 0x39 pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; 8001b98: 683b ldr r3, [r7, #0] 8001b9a: 011b lsls r3, r3, #4 8001b9c: 3318 adds r3, #24 8001b9e: 687a ldr r2, [r7, #4] 8001ba0: 4413 add r3, r2 8001ba2: 613b str r3, [r7, #16] /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); 8001ba4: 693b ldr r3, [r7, #16] 8001ba6: 685a ldr r2, [r3, #4] 8001ba8: 693b ldr r3, [r7, #16] 8001baa: 689b ldr r3, [r3, #8] 8001bac: 041b lsls r3, r3, #16 8001bae: 4313 orrs r3, r2 8001bb0: 617b str r3, [r7, #20] regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; 8001bb2: 4b35 ldr r3, [pc, #212] @ (8001c88 ) 8001bb4: 60fb str r3, [r7, #12] if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001bb6: 693b ldr r3, [r7, #16] 8001bb8: 685b ldr r3, [r3, #4] 8001bba: 2b0a cmp r3, #10 8001bbc: d003 beq.n 8001bc6 8001bbe: 693b ldr r3, [r7, #16] 8001bc0: 685b ldr r3, [r3, #4] 8001bc2: 2b09 cmp r3, #9 8001bc4: d107 bne.n 8001bd6 { regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); 8001bc6: 693b ldr r3, [r7, #16] 8001bc8: 68db ldr r3, [r3, #12] 8001bca: f003 437f and.w r3, r3, #4278190080 @ 0xff000000 8001bce: 697a ldr r2, [r7, #20] 8001bd0: 4313 orrs r3, r2 8001bd2: 617b str r3, [r7, #20] 8001bd4: e005 b.n 8001be2 } else { regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); 8001bd6: 693b ldr r3, [r7, #16] 8001bd8: 68db ldr r3, [r3, #12] 8001bda: 061b lsls r3, r3, #24 8001bdc: 697a ldr r2, [r7, #20] 8001bde: 4313 orrs r3, r2 8001be0: 617b str r3, [r7, #20] } /* Configure the background DMA2D layer */ if (LayerIdx == DMA2D_BACKGROUND_LAYER) 8001be2: 683b ldr r3, [r7, #0] 8001be4: 2b00 cmp r3, #0 8001be6: d120 bne.n 8001c2a { /* Write DMA2D BGPFCCR register */ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); 8001be8: 687b ldr r3, [r7, #4] 8001bea: 681b ldr r3, [r3, #0] 8001bec: 6a5a ldr r2, [r3, #36] @ 0x24 8001bee: 68fb ldr r3, [r7, #12] 8001bf0: 43db mvns r3, r3 8001bf2: ea02 0103 and.w r1, r2, r3 8001bf6: 687b ldr r3, [r7, #4] 8001bf8: 681b ldr r3, [r3, #0] 8001bfa: 697a ldr r2, [r7, #20] 8001bfc: 430a orrs r2, r1 8001bfe: 625a str r2, [r3, #36] @ 0x24 /* DMA2D BGOR register configuration -------------------------------------*/ WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); 8001c00: 687b ldr r3, [r7, #4] 8001c02: 681b ldr r3, [r3, #0] 8001c04: 693a ldr r2, [r7, #16] 8001c06: 6812 ldr r2, [r2, #0] 8001c08: 619a str r2, [r3, #24] /* DMA2D BGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001c0a: 693b ldr r3, [r7, #16] 8001c0c: 685b ldr r3, [r3, #4] 8001c0e: 2b0a cmp r3, #10 8001c10: d003 beq.n 8001c1a 8001c12: 693b ldr r3, [r7, #16] 8001c14: 685b ldr r3, [r3, #4] 8001c16: 2b09 cmp r3, #9 8001c18: d127 bne.n 8001c6a { WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ 8001c1a: 693b ldr r3, [r7, #16] 8001c1c: 68da ldr r2, [r3, #12] 8001c1e: 687b ldr r3, [r7, #4] 8001c20: 681b ldr r3, [r3, #0] 8001c22: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000 8001c26: 629a str r2, [r3, #40] @ 0x28 8001c28: e01f b.n 8001c6a else { /* Write DMA2D FGPFCCR register */ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); 8001c2a: 687b ldr r3, [r7, #4] 8001c2c: 681b ldr r3, [r3, #0] 8001c2e: 69da ldr r2, [r3, #28] 8001c30: 68fb ldr r3, [r7, #12] 8001c32: 43db mvns r3, r3 8001c34: ea02 0103 and.w r1, r2, r3 8001c38: 687b ldr r3, [r7, #4] 8001c3a: 681b ldr r3, [r3, #0] 8001c3c: 697a ldr r2, [r7, #20] 8001c3e: 430a orrs r2, r1 8001c40: 61da str r2, [r3, #28] /* DMA2D FGOR register configuration -------------------------------------*/ WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); 8001c42: 687b ldr r3, [r7, #4] 8001c44: 681b ldr r3, [r3, #0] 8001c46: 693a ldr r2, [r7, #16] 8001c48: 6812 ldr r2, [r2, #0] 8001c4a: 611a str r2, [r3, #16] /* DMA2D FGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) 8001c4c: 693b ldr r3, [r7, #16] 8001c4e: 685b ldr r3, [r3, #4] 8001c50: 2b0a cmp r3, #10 8001c52: d003 beq.n 8001c5c 8001c54: 693b ldr r3, [r7, #16] 8001c56: 685b ldr r3, [r3, #4] 8001c58: 2b09 cmp r3, #9 8001c5a: d106 bne.n 8001c6a { WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ 8001c5c: 693b ldr r3, [r7, #16] 8001c5e: 68da ldr r2, [r3, #12] 8001c60: 687b ldr r3, [r7, #4] 8001c62: 681b ldr r3, [r3, #0] 8001c64: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000 8001c68: 621a str r2, [r3, #32] DMA2D_FGCOLR_RED)); } } /* Initialize the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; 8001c6a: 687b ldr r3, [r7, #4] 8001c6c: 2201 movs r2, #1 8001c6e: f883 2039 strb.w r2, [r3, #57] @ 0x39 /* Process unlocked */ __HAL_UNLOCK(hdma2d); 8001c72: 687b ldr r3, [r7, #4] 8001c74: 2200 movs r2, #0 8001c76: f883 2038 strb.w r2, [r3, #56] @ 0x38 return HAL_OK; 8001c7a: 2300 movs r3, #0 } 8001c7c: 4618 mov r0, r3 8001c7e: 371c adds r7, #28 8001c80: 46bd mov sp, r7 8001c82: f85d 7b04 ldr.w r7, [sp], #4 8001c86: 4770 bx lr 8001c88: ff03000f .word 0xff03000f 08001c8c : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8001c8c: b480 push {r7} 8001c8e: b089 sub sp, #36 @ 0x24 8001c90: af00 add r7, sp, #0 8001c92: 6078 str r0, [r7, #4] 8001c94: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; 8001c96: 2300 movs r3, #0 8001c98: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; 8001c9a: 2300 movs r3, #0 8001c9c: 613b str r3, [r7, #16] uint32_t temp = 0x00U; 8001c9e: 2300 movs r3, #0 8001ca0: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) 8001ca2: 2300 movs r3, #0 8001ca4: 61fb str r3, [r7, #28] 8001ca6: e177 b.n 8001f98 { /* Get the IO position */ ioposition = 0x01U << position; 8001ca8: 2201 movs r2, #1 8001caa: 69fb ldr r3, [r7, #28] 8001cac: fa02 f303 lsl.w r3, r2, r3 8001cb0: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; 8001cb2: 683b ldr r3, [r7, #0] 8001cb4: 681b ldr r3, [r3, #0] 8001cb6: 697a ldr r2, [r7, #20] 8001cb8: 4013 ands r3, r2 8001cba: 613b str r3, [r7, #16] if(iocurrent == ioposition) 8001cbc: 693a ldr r2, [r7, #16] 8001cbe: 697b ldr r3, [r7, #20] 8001cc0: 429a cmp r2, r3 8001cc2: f040 8166 bne.w 8001f92 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001cc6: 683b ldr r3, [r7, #0] 8001cc8: 685b ldr r3, [r3, #4] 8001cca: f003 0303 and.w r3, r3, #3 8001cce: 2b01 cmp r3, #1 8001cd0: d005 beq.n 8001cde (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001cd2: 683b ldr r3, [r7, #0] 8001cd4: 685b ldr r3, [r3, #4] 8001cd6: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ 8001cda: 2b02 cmp r3, #2 8001cdc: d130 bne.n 8001d40 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 8001cde: 687b ldr r3, [r7, #4] 8001ce0: 689b ldr r3, [r3, #8] 8001ce2: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); 8001ce4: 69fb ldr r3, [r7, #28] 8001ce6: 005b lsls r3, r3, #1 8001ce8: 2203 movs r2, #3 8001cea: fa02 f303 lsl.w r3, r2, r3 8001cee: 43db mvns r3, r3 8001cf0: 69ba ldr r2, [r7, #24] 8001cf2: 4013 ands r3, r2 8001cf4: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); 8001cf6: 683b ldr r3, [r7, #0] 8001cf8: 68da ldr r2, [r3, #12] 8001cfa: 69fb ldr r3, [r7, #28] 8001cfc: 005b lsls r3, r3, #1 8001cfe: fa02 f303 lsl.w r3, r2, r3 8001d02: 69ba ldr r2, [r7, #24] 8001d04: 4313 orrs r3, r2 8001d06: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; 8001d08: 687b ldr r3, [r7, #4] 8001d0a: 69ba ldr r2, [r7, #24] 8001d0c: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 8001d0e: 687b ldr r3, [r7, #4] 8001d10: 685b ldr r3, [r3, #4] 8001d12: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; 8001d14: 2201 movs r2, #1 8001d16: 69fb ldr r3, [r7, #28] 8001d18: fa02 f303 lsl.w r3, r2, r3 8001d1c: 43db mvns r3, r3 8001d1e: 69ba ldr r2, [r7, #24] 8001d20: 4013 ands r3, r2 8001d22: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); 8001d24: 683b ldr r3, [r7, #0] 8001d26: 685b ldr r3, [r3, #4] 8001d28: 091b lsrs r3, r3, #4 8001d2a: f003 0201 and.w r2, r3, #1 8001d2e: 69fb ldr r3, [r7, #28] 8001d30: fa02 f303 lsl.w r3, r2, r3 8001d34: 69ba ldr r2, [r7, #24] 8001d36: 4313 orrs r3, r2 8001d38: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; 8001d3a: 687b ldr r3, [r7, #4] 8001d3c: 69ba ldr r2, [r7, #24] 8001d3e: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) 8001d40: 683b ldr r3, [r7, #0] 8001d42: 685b ldr r3, [r3, #4] 8001d44: f003 0303 and.w r3, r3, #3 8001d48: 2b03 cmp r3, #3 8001d4a: d017 beq.n 8001d7c { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 8001d4c: 687b ldr r3, [r7, #4] 8001d4e: 68db ldr r3, [r3, #12] 8001d50: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); 8001d52: 69fb ldr r3, [r7, #28] 8001d54: 005b lsls r3, r3, #1 8001d56: 2203 movs r2, #3 8001d58: fa02 f303 lsl.w r3, r2, r3 8001d5c: 43db mvns r3, r3 8001d5e: 69ba ldr r2, [r7, #24] 8001d60: 4013 ands r3, r2 8001d62: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); 8001d64: 683b ldr r3, [r7, #0] 8001d66: 689a ldr r2, [r3, #8] 8001d68: 69fb ldr r3, [r7, #28] 8001d6a: 005b lsls r3, r3, #1 8001d6c: fa02 f303 lsl.w r3, r2, r3 8001d70: 69ba ldr r2, [r7, #24] 8001d72: 4313 orrs r3, r2 8001d74: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; 8001d76: 687b ldr r3, [r7, #4] 8001d78: 69ba ldr r2, [r7, #24] 8001d7a: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) 8001d7c: 683b ldr r3, [r7, #0] 8001d7e: 685b ldr r3, [r3, #4] 8001d80: f003 0303 and.w r3, r3, #3 8001d84: 2b02 cmp r3, #2 8001d86: d123 bne.n 8001dd0 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; 8001d88: 69fb ldr r3, [r7, #28] 8001d8a: 08da lsrs r2, r3, #3 8001d8c: 687b ldr r3, [r7, #4] 8001d8e: 3208 adds r2, #8 8001d90: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8001d94: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; 8001d96: 69fb ldr r3, [r7, #28] 8001d98: f003 0307 and.w r3, r3, #7 8001d9c: 009b lsls r3, r3, #2 8001d9e: 220f movs r2, #15 8001da0: fa02 f303 lsl.w r3, r2, r3 8001da4: 43db mvns r3, r3 8001da6: 69ba ldr r2, [r7, #24] 8001da8: 4013 ands r3, r2 8001daa: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); 8001dac: 683b ldr r3, [r7, #0] 8001dae: 691a ldr r2, [r3, #16] 8001db0: 69fb ldr r3, [r7, #28] 8001db2: f003 0307 and.w r3, r3, #7 8001db6: 009b lsls r3, r3, #2 8001db8: fa02 f303 lsl.w r3, r2, r3 8001dbc: 69ba ldr r2, [r7, #24] 8001dbe: 4313 orrs r3, r2 8001dc0: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; 8001dc2: 69fb ldr r3, [r7, #28] 8001dc4: 08da lsrs r2, r3, #3 8001dc6: 687b ldr r3, [r7, #4] 8001dc8: 3208 adds r2, #8 8001dca: 69b9 ldr r1, [r7, #24] 8001dcc: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 8001dd0: 687b ldr r3, [r7, #4] 8001dd2: 681b ldr r3, [r3, #0] 8001dd4: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); 8001dd6: 69fb ldr r3, [r7, #28] 8001dd8: 005b lsls r3, r3, #1 8001dda: 2203 movs r2, #3 8001ddc: fa02 f303 lsl.w r3, r2, r3 8001de0: 43db mvns r3, r3 8001de2: 69ba ldr r2, [r7, #24] 8001de4: 4013 ands r3, r2 8001de6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); 8001de8: 683b ldr r3, [r7, #0] 8001dea: 685b ldr r3, [r3, #4] 8001dec: f003 0203 and.w r2, r3, #3 8001df0: 69fb ldr r3, [r7, #28] 8001df2: 005b lsls r3, r3, #1 8001df4: fa02 f303 lsl.w r3, r2, r3 8001df8: 69ba ldr r2, [r7, #24] 8001dfa: 4313 orrs r3, r2 8001dfc: 61bb str r3, [r7, #24] GPIOx->MODER = temp; 8001dfe: 687b ldr r3, [r7, #4] 8001e00: 69ba ldr r2, [r7, #24] 8001e02: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) 8001e04: 683b ldr r3, [r7, #0] 8001e06: 685b ldr r3, [r3, #4] 8001e08: f403 3340 and.w r3, r3, #196608 @ 0x30000 8001e0c: 2b00 cmp r3, #0 8001e0e: f000 80c0 beq.w 8001f92 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001e12: 2300 movs r3, #0 8001e14: 60fb str r3, [r7, #12] 8001e16: 4b66 ldr r3, [pc, #408] @ (8001fb0 ) 8001e18: 6c5b ldr r3, [r3, #68] @ 0x44 8001e1a: 4a65 ldr r2, [pc, #404] @ (8001fb0 ) 8001e1c: f443 4380 orr.w r3, r3, #16384 @ 0x4000 8001e20: 6453 str r3, [r2, #68] @ 0x44 8001e22: 4b63 ldr r3, [pc, #396] @ (8001fb0 ) 8001e24: 6c5b ldr r3, [r3, #68] @ 0x44 8001e26: f403 4380 and.w r3, r3, #16384 @ 0x4000 8001e2a: 60fb str r3, [r7, #12] 8001e2c: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; 8001e2e: 4a61 ldr r2, [pc, #388] @ (8001fb4 ) 8001e30: 69fb ldr r3, [r7, #28] 8001e32: 089b lsrs r3, r3, #2 8001e34: 3302 adds r3, #2 8001e36: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001e3a: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); 8001e3c: 69fb ldr r3, [r7, #28] 8001e3e: f003 0303 and.w r3, r3, #3 8001e42: 009b lsls r3, r3, #2 8001e44: 220f movs r2, #15 8001e46: fa02 f303 lsl.w r3, r2, r3 8001e4a: 43db mvns r3, r3 8001e4c: 69ba ldr r2, [r7, #24] 8001e4e: 4013 ands r3, r2 8001e50: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); 8001e52: 687b ldr r3, [r7, #4] 8001e54: 4a58 ldr r2, [pc, #352] @ (8001fb8 ) 8001e56: 4293 cmp r3, r2 8001e58: d037 beq.n 8001eca 8001e5a: 687b ldr r3, [r7, #4] 8001e5c: 4a57 ldr r2, [pc, #348] @ (8001fbc ) 8001e5e: 4293 cmp r3, r2 8001e60: d031 beq.n 8001ec6 8001e62: 687b ldr r3, [r7, #4] 8001e64: 4a56 ldr r2, [pc, #344] @ (8001fc0 ) 8001e66: 4293 cmp r3, r2 8001e68: d02b beq.n 8001ec2 8001e6a: 687b ldr r3, [r7, #4] 8001e6c: 4a55 ldr r2, [pc, #340] @ (8001fc4 ) 8001e6e: 4293 cmp r3, r2 8001e70: d025 beq.n 8001ebe 8001e72: 687b ldr r3, [r7, #4] 8001e74: 4a54 ldr r2, [pc, #336] @ (8001fc8 ) 8001e76: 4293 cmp r3, r2 8001e78: d01f beq.n 8001eba 8001e7a: 687b ldr r3, [r7, #4] 8001e7c: 4a53 ldr r2, [pc, #332] @ (8001fcc ) 8001e7e: 4293 cmp r3, r2 8001e80: d019 beq.n 8001eb6 8001e82: 687b ldr r3, [r7, #4] 8001e84: 4a52 ldr r2, [pc, #328] @ (8001fd0 ) 8001e86: 4293 cmp r3, r2 8001e88: d013 beq.n 8001eb2 8001e8a: 687b ldr r3, [r7, #4] 8001e8c: 4a51 ldr r2, [pc, #324] @ (8001fd4 ) 8001e8e: 4293 cmp r3, r2 8001e90: d00d beq.n 8001eae 8001e92: 687b ldr r3, [r7, #4] 8001e94: 4a50 ldr r2, [pc, #320] @ (8001fd8 ) 8001e96: 4293 cmp r3, r2 8001e98: d007 beq.n 8001eaa 8001e9a: 687b ldr r3, [r7, #4] 8001e9c: 4a4f ldr r2, [pc, #316] @ (8001fdc ) 8001e9e: 4293 cmp r3, r2 8001ea0: d101 bne.n 8001ea6 8001ea2: 2309 movs r3, #9 8001ea4: e012 b.n 8001ecc 8001ea6: 230a movs r3, #10 8001ea8: e010 b.n 8001ecc 8001eaa: 2308 movs r3, #8 8001eac: e00e b.n 8001ecc 8001eae: 2307 movs r3, #7 8001eb0: e00c b.n 8001ecc 8001eb2: 2306 movs r3, #6 8001eb4: e00a b.n 8001ecc 8001eb6: 2305 movs r3, #5 8001eb8: e008 b.n 8001ecc 8001eba: 2304 movs r3, #4 8001ebc: e006 b.n 8001ecc 8001ebe: 2303 movs r3, #3 8001ec0: e004 b.n 8001ecc 8001ec2: 2302 movs r3, #2 8001ec4: e002 b.n 8001ecc 8001ec6: 2301 movs r3, #1 8001ec8: e000 b.n 8001ecc 8001eca: 2300 movs r3, #0 8001ecc: 69fa ldr r2, [r7, #28] 8001ece: f002 0203 and.w r2, r2, #3 8001ed2: 0092 lsls r2, r2, #2 8001ed4: 4093 lsls r3, r2 8001ed6: 69ba ldr r2, [r7, #24] 8001ed8: 4313 orrs r3, r2 8001eda: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; 8001edc: 4935 ldr r1, [pc, #212] @ (8001fb4 ) 8001ede: 69fb ldr r3, [r7, #28] 8001ee0: 089b lsrs r3, r3, #2 8001ee2: 3302 adds r3, #2 8001ee4: 69ba ldr r2, [r7, #24] 8001ee6: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; 8001eea: 4b3d ldr r3, [pc, #244] @ (8001fe0 ) 8001eec: 689b ldr r3, [r3, #8] 8001eee: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001ef0: 693b ldr r3, [r7, #16] 8001ef2: 43db mvns r3, r3 8001ef4: 69ba ldr r2, [r7, #24] 8001ef6: 4013 ands r3, r2 8001ef8: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) 8001efa: 683b ldr r3, [r7, #0] 8001efc: 685b ldr r3, [r3, #4] 8001efe: f403 1380 and.w r3, r3, #1048576 @ 0x100000 8001f02: 2b00 cmp r3, #0 8001f04: d003 beq.n 8001f0e { temp |= iocurrent; 8001f06: 69ba ldr r2, [r7, #24] 8001f08: 693b ldr r3, [r7, #16] 8001f0a: 4313 orrs r3, r2 8001f0c: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; 8001f0e: 4a34 ldr r2, [pc, #208] @ (8001fe0 ) 8001f10: 69bb ldr r3, [r7, #24] 8001f12: 6093 str r3, [r2, #8] temp = EXTI->FTSR; 8001f14: 4b32 ldr r3, [pc, #200] @ (8001fe0 ) 8001f16: 68db ldr r3, [r3, #12] 8001f18: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f1a: 693b ldr r3, [r7, #16] 8001f1c: 43db mvns r3, r3 8001f1e: 69ba ldr r2, [r7, #24] 8001f20: 4013 ands r3, r2 8001f22: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) 8001f24: 683b ldr r3, [r7, #0] 8001f26: 685b ldr r3, [r3, #4] 8001f28: f403 1300 and.w r3, r3, #2097152 @ 0x200000 8001f2c: 2b00 cmp r3, #0 8001f2e: d003 beq.n 8001f38 { temp |= iocurrent; 8001f30: 69ba ldr r2, [r7, #24] 8001f32: 693b ldr r3, [r7, #16] 8001f34: 4313 orrs r3, r2 8001f36: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; 8001f38: 4a29 ldr r2, [pc, #164] @ (8001fe0 ) 8001f3a: 69bb ldr r3, [r7, #24] 8001f3c: 60d3 str r3, [r2, #12] temp = EXTI->EMR; 8001f3e: 4b28 ldr r3, [pc, #160] @ (8001fe0 ) 8001f40: 685b ldr r3, [r3, #4] 8001f42: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f44: 693b ldr r3, [r7, #16] 8001f46: 43db mvns r3, r3 8001f48: 69ba ldr r2, [r7, #24] 8001f4a: 4013 ands r3, r2 8001f4c: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) 8001f4e: 683b ldr r3, [r7, #0] 8001f50: 685b ldr r3, [r3, #4] 8001f52: f403 3300 and.w r3, r3, #131072 @ 0x20000 8001f56: 2b00 cmp r3, #0 8001f58: d003 beq.n 8001f62 { temp |= iocurrent; 8001f5a: 69ba ldr r2, [r7, #24] 8001f5c: 693b ldr r3, [r7, #16] 8001f5e: 4313 orrs r3, r2 8001f60: 61bb str r3, [r7, #24] } EXTI->EMR = temp; 8001f62: 4a1f ldr r2, [pc, #124] @ (8001fe0 ) 8001f64: 69bb ldr r3, [r7, #24] 8001f66: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; 8001f68: 4b1d ldr r3, [pc, #116] @ (8001fe0 ) 8001f6a: 681b ldr r3, [r3, #0] 8001f6c: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); 8001f6e: 693b ldr r3, [r7, #16] 8001f70: 43db mvns r3, r3 8001f72: 69ba ldr r2, [r7, #24] 8001f74: 4013 ands r3, r2 8001f76: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) 8001f78: 683b ldr r3, [r7, #0] 8001f7a: 685b ldr r3, [r3, #4] 8001f7c: f403 3380 and.w r3, r3, #65536 @ 0x10000 8001f80: 2b00 cmp r3, #0 8001f82: d003 beq.n 8001f8c { temp |= iocurrent; 8001f84: 69ba ldr r2, [r7, #24] 8001f86: 693b ldr r3, [r7, #16] 8001f88: 4313 orrs r3, r2 8001f8a: 61bb str r3, [r7, #24] } EXTI->IMR = temp; 8001f8c: 4a14 ldr r2, [pc, #80] @ (8001fe0 ) 8001f8e: 69bb ldr r3, [r7, #24] 8001f90: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) 8001f92: 69fb ldr r3, [r7, #28] 8001f94: 3301 adds r3, #1 8001f96: 61fb str r3, [r7, #28] 8001f98: 69fb ldr r3, [r7, #28] 8001f9a: 2b0f cmp r3, #15 8001f9c: f67f ae84 bls.w 8001ca8 } } } } 8001fa0: bf00 nop 8001fa2: bf00 nop 8001fa4: 3724 adds r7, #36 @ 0x24 8001fa6: 46bd mov sp, r7 8001fa8: f85d 7b04 ldr.w r7, [sp], #4 8001fac: 4770 bx lr 8001fae: bf00 nop 8001fb0: 40023800 .word 0x40023800 8001fb4: 40013800 .word 0x40013800 8001fb8: 40020000 .word 0x40020000 8001fbc: 40020400 .word 0x40020400 8001fc0: 40020800 .word 0x40020800 8001fc4: 40020c00 .word 0x40020c00 8001fc8: 40021000 .word 0x40021000 8001fcc: 40021400 .word 0x40021400 8001fd0: 40021800 .word 0x40021800 8001fd4: 40021c00 .word 0x40021c00 8001fd8: 40022000 .word 0x40022000 8001fdc: 40022400 .word 0x40022400 8001fe0: 40013c00 .word 0x40013c00 08001fe4 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { 8001fe4: b480 push {r7} 8001fe6: b085 sub sp, #20 8001fe8: af00 add r7, sp, #0 8001fea: 6078 str r0, [r7, #4] 8001fec: 460b mov r3, r1 8001fee: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) 8001ff0: 687b ldr r3, [r7, #4] 8001ff2: 691a ldr r2, [r3, #16] 8001ff4: 887b ldrh r3, [r7, #2] 8001ff6: 4013 ands r3, r2 8001ff8: 2b00 cmp r3, #0 8001ffa: d002 beq.n 8002002 { bitstatus = GPIO_PIN_SET; 8001ffc: 2301 movs r3, #1 8001ffe: 73fb strb r3, [r7, #15] 8002000: e001 b.n 8002006 } else { bitstatus = GPIO_PIN_RESET; 8002002: 2300 movs r3, #0 8002004: 73fb strb r3, [r7, #15] } return bitstatus; 8002006: 7bfb ldrb r3, [r7, #15] } 8002008: 4618 mov r0, r3 800200a: 3714 adds r7, #20 800200c: 46bd mov sp, r7 800200e: f85d 7b04 ldr.w r7, [sp], #4 8002012: 4770 bx lr 08002014 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8002014: b480 push {r7} 8002016: b083 sub sp, #12 8002018: af00 add r7, sp, #0 800201a: 6078 str r0, [r7, #4] 800201c: 460b mov r3, r1 800201e: 807b strh r3, [r7, #2] 8002020: 4613 mov r3, r2 8002022: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8002024: 787b ldrb r3, [r7, #1] 8002026: 2b00 cmp r3, #0 8002028: d003 beq.n 8002032 { GPIOx->BSRR = GPIO_Pin; 800202a: 887a ldrh r2, [r7, #2] 800202c: 687b ldr r3, [r7, #4] 800202e: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } 8002030: e003 b.n 800203a GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; 8002032: 887b ldrh r3, [r7, #2] 8002034: 041a lsls r2, r3, #16 8002036: 687b ldr r3, [r7, #4] 8002038: 619a str r2, [r3, #24] } 800203a: bf00 nop 800203c: 370c adds r7, #12 800203e: 46bd mov sp, r7 8002040: f85d 7b04 ldr.w r7, [sp], #4 8002044: 4770 bx lr 08002046 : * @brief Handle HCD interrupt request. * @param hhcd HCD handle * @retval None */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { 8002046: b580 push {r7, lr} 8002048: b086 sub sp, #24 800204a: af00 add r7, sp, #0 800204c: 6078 str r0, [r7, #4] USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 800204e: 687b ldr r3, [r7, #4] 8002050: 681b ldr r3, [r3, #0] 8002052: 613b str r3, [r7, #16] uint32_t USBx_BASE = (uint32_t)USBx; 8002054: 693b ldr r3, [r7, #16] 8002056: 60fb str r3, [r7, #12] uint32_t i; uint32_t interrupt; /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) 8002058: 687b ldr r3, [r7, #4] 800205a: 681b ldr r3, [r3, #0] 800205c: 4618 mov r0, r3 800205e: f004 fab7 bl 80065d0 8002062: 4603 mov r3, r0 8002064: 2b01 cmp r3, #1 8002066: f040 80fb bne.w 8002260 { /* Avoid spurious interrupt */ if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) 800206a: 687b ldr r3, [r7, #4] 800206c: 681b ldr r3, [r3, #0] 800206e: 4618 mov r0, r3 8002070: f004 fa7a bl 8006568 8002074: 4603 mov r3, r0 8002076: 2b00 cmp r3, #0 8002078: f000 80f1 beq.w 800225e { return; } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) 800207c: 687b ldr r3, [r7, #4] 800207e: 681b ldr r3, [r3, #0] 8002080: 4618 mov r0, r3 8002082: f004 fa71 bl 8006568 8002086: 4603 mov r3, r0 8002088: f403 1300 and.w r3, r3, #2097152 @ 0x200000 800208c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000 8002090: d104 bne.n 800209c { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); 8002092: 687b ldr r3, [r7, #4] 8002094: 681b ldr r3, [r3, #0] 8002096: f44f 1200 mov.w r2, #2097152 @ 0x200000 800209a: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) 800209c: 687b ldr r3, [r7, #4] 800209e: 681b ldr r3, [r3, #0] 80020a0: 4618 mov r0, r3 80020a2: f004 fa61 bl 8006568 80020a6: 4603 mov r3, r0 80020a8: f403 1380 and.w r3, r3, #1048576 @ 0x100000 80020ac: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000 80020b0: d104 bne.n 80020bc { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); 80020b2: 687b ldr r3, [r7, #4] 80020b4: 681b ldr r3, [r3, #0] 80020b6: f44f 1280 mov.w r2, #1048576 @ 0x100000 80020ba: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) 80020bc: 687b ldr r3, [r7, #4] 80020be: 681b ldr r3, [r3, #0] 80020c0: 4618 mov r0, r3 80020c2: f004 fa51 bl 8006568 80020c6: 4603 mov r3, r0 80020c8: f003 6380 and.w r3, r3, #67108864 @ 0x4000000 80020cc: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000 80020d0: d104 bne.n 80020dc { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); 80020d2: 687b ldr r3, [r7, #4] 80020d4: 681b ldr r3, [r3, #0] 80020d6: f04f 6280 mov.w r2, #67108864 @ 0x4000000 80020da: 615a str r2, [r3, #20] } if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) 80020dc: 687b ldr r3, [r7, #4] 80020de: 681b ldr r3, [r3, #0] 80020e0: 4618 mov r0, r3 80020e2: f004 fa41 bl 8006568 80020e6: 4603 mov r3, r0 80020e8: f003 0302 and.w r3, r3, #2 80020ec: 2b02 cmp r3, #2 80020ee: d103 bne.n 80020f8 { /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); 80020f0: 687b ldr r3, [r7, #4] 80020f2: 681b ldr r3, [r3, #0] 80020f4: 2202 movs r2, #2 80020f6: 615a str r2, [r3, #20] } /* Handle Host Disconnect Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) 80020f8: 687b ldr r3, [r7, #4] 80020fa: 681b ldr r3, [r3, #0] 80020fc: 4618 mov r0, r3 80020fe: f004 fa33 bl 8006568 8002102: 4603 mov r3, r0 8002104: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8002108: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800210c: d120 bne.n 8002150 { __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); 800210e: 687b ldr r3, [r7, #4] 8002110: 681b ldr r3, [r3, #0] 8002112: f04f 5200 mov.w r2, #536870912 @ 0x20000000 8002116: 615a str r2, [r3, #20] if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) 8002118: 68fb ldr r3, [r7, #12] 800211a: f503 6388 add.w r3, r3, #1088 @ 0x440 800211e: 681b ldr r3, [r3, #0] 8002120: f003 0301 and.w r3, r3, #1 8002124: 2b00 cmp r3, #0 8002126: d113 bne.n 8002150 { /* Flush USB Fifo */ (void)USB_FlushTxFifo(USBx, 0x10U); 8002128: 2110 movs r1, #16 800212a: 6938 ldr r0, [r7, #16] 800212c: f004 f964 bl 80063f8 (void)USB_FlushRxFifo(USBx); 8002130: 6938 ldr r0, [r7, #16] 8002132: f004 f993 bl 800645c if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) 8002136: 687b ldr r3, [r7, #4] 8002138: 7a5b ldrb r3, [r3, #9] 800213a: 2b02 cmp r3, #2 800213c: d105 bne.n 800214a { /* Restore FS Clock */ (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); 800213e: 687b ldr r3, [r7, #4] 8002140: 681b ldr r3, [r3, #0] 8002142: 2101 movs r1, #1 8002144: 4618 mov r0, r3 8002146: f004 fa51 bl 80065ec /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->DisconnectCallback(hhcd); #else HAL_HCD_Disconnect_Callback(hhcd); 800214a: 6878 ldr r0, [r7, #4] 800214c: f005 fe24 bl 8007d98 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Handle Host Port Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) 8002150: 687b ldr r3, [r7, #4] 8002152: 681b ldr r3, [r3, #0] 8002154: 4618 mov r0, r3 8002156: f004 fa07 bl 8006568 800215a: 4603 mov r3, r0 800215c: f003 7380 and.w r3, r3, #16777216 @ 0x1000000 8002160: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000 8002164: d102 bne.n 800216c { HCD_Port_IRQHandler(hhcd); 8002166: 6878 ldr r0, [r7, #4] 8002168: f001 fca1 bl 8003aae } /* Handle Host SOF Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) 800216c: 687b ldr r3, [r7, #4] 800216e: 681b ldr r3, [r3, #0] 8002170: 4618 mov r0, r3 8002172: f004 f9f9 bl 8006568 8002176: 4603 mov r3, r0 8002178: f003 0308 and.w r3, r3, #8 800217c: 2b08 cmp r3, #8 800217e: d106 bne.n 800218e { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->SOFCallback(hhcd); #else HAL_HCD_SOF_Callback(hhcd); 8002180: 6878 ldr r0, [r7, #4] 8002182: f005 fded bl 8007d60 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); 8002186: 687b ldr r3, [r7, #4] 8002188: 681b ldr r3, [r3, #0] 800218a: 2208 movs r2, #8 800218c: 615a str r2, [r3, #20] } /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) 800218e: 687b ldr r3, [r7, #4] 8002190: 681b ldr r3, [r3, #0] 8002192: 4618 mov r0, r3 8002194: f004 f9e8 bl 8006568 8002198: 4603 mov r3, r0 800219a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800219e: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000 80021a2: d139 bne.n 8002218 { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); 80021a4: 687b ldr r3, [r7, #4] 80021a6: 681b ldr r3, [r3, #0] 80021a8: 4618 mov r0, r3 80021aa: f004 fa5c bl 8006666 80021ae: 60b8 str r0, [r7, #8] for (i = 0U; i < hhcd->Init.Host_channels; i++) 80021b0: 2300 movs r3, #0 80021b2: 617b str r3, [r7, #20] 80021b4: e025 b.n 8002202 { if ((interrupt & (1UL << (i & 0xFU))) != 0U) 80021b6: 697b ldr r3, [r7, #20] 80021b8: f003 030f and.w r3, r3, #15 80021bc: 68ba ldr r2, [r7, #8] 80021be: fa22 f303 lsr.w r3, r2, r3 80021c2: f003 0301 and.w r3, r3, #1 80021c6: 2b00 cmp r3, #0 80021c8: d018 beq.n 80021fc { if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) 80021ca: 697b ldr r3, [r7, #20] 80021cc: 015a lsls r2, r3, #5 80021ce: 68fb ldr r3, [r7, #12] 80021d0: 4413 add r3, r2 80021d2: f503 63a0 add.w r3, r3, #1280 @ 0x500 80021d6: 681b ldr r3, [r3, #0] 80021d8: f403 4300 and.w r3, r3, #32768 @ 0x8000 80021dc: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 80021e0: d106 bne.n 80021f0 { HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); 80021e2: 697b ldr r3, [r7, #20] 80021e4: b2db uxtb r3, r3 80021e6: 4619 mov r1, r3 80021e8: 6878 ldr r0, [r7, #4] 80021ea: f000 f859 bl 80022a0 80021ee: e005 b.n 80021fc } else { HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); 80021f0: 697b ldr r3, [r7, #20] 80021f2: b2db uxtb r3, r3 80021f4: 4619 mov r1, r3 80021f6: 6878 ldr r0, [r7, #4] 80021f8: f000 febb bl 8002f72 for (i = 0U; i < hhcd->Init.Host_channels; i++) 80021fc: 697b ldr r3, [r7, #20] 80021fe: 3301 adds r3, #1 8002200: 617b str r3, [r7, #20] 8002202: 687b ldr r3, [r7, #4] 8002204: 795b ldrb r3, [r3, #5] 8002206: 461a mov r2, r3 8002208: 697b ldr r3, [r7, #20] 800220a: 4293 cmp r3, r2 800220c: d3d3 bcc.n 80021b6 } } } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); 800220e: 687b ldr r3, [r7, #4] 8002210: 681b ldr r3, [r3, #0] 8002212: f04f 7200 mov.w r2, #33554432 @ 0x2000000 8002216: 615a str r2, [r3, #20] } /* Handle Rx Queue Level Interrupts */ if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) 8002218: 687b ldr r3, [r7, #4] 800221a: 681b ldr r3, [r3, #0] 800221c: 4618 mov r0, r3 800221e: f004 f9a3 bl 8006568 8002222: 4603 mov r3, r0 8002224: f003 0310 and.w r3, r3, #16 8002228: 2b10 cmp r3, #16 800222a: d101 bne.n 8002230 800222c: 2301 movs r3, #1 800222e: e000 b.n 8002232 8002230: 2300 movs r3, #0 8002232: 2b00 cmp r3, #0 8002234: d014 beq.n 8002260 { USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); 8002236: 687b ldr r3, [r7, #4] 8002238: 681b ldr r3, [r3, #0] 800223a: 699a ldr r2, [r3, #24] 800223c: 687b ldr r3, [r7, #4] 800223e: 681b ldr r3, [r3, #0] 8002240: f022 0210 bic.w r2, r2, #16 8002244: 619a str r2, [r3, #24] HCD_RXQLVL_IRQHandler(hhcd); 8002246: 6878 ldr r0, [r7, #4] 8002248: f001 fb52 bl 80038f0 USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); 800224c: 687b ldr r3, [r7, #4] 800224e: 681b ldr r3, [r3, #0] 8002250: 699a ldr r2, [r3, #24] 8002252: 687b ldr r3, [r7, #4] 8002254: 681b ldr r3, [r3, #0] 8002256: f042 0210 orr.w r2, r2, #16 800225a: 619a str r2, [r3, #24] 800225c: e000 b.n 8002260 return; 800225e: bf00 nop } } } 8002260: 3718 adds r7, #24 8002262: 46bd mov sp, r7 8002264: bd80 pop {r7, pc} 08002266 : * @param hhcd HCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) { 8002266: b580 push {r7, lr} 8002268: b082 sub sp, #8 800226a: af00 add r7, sp, #0 800226c: 6078 str r0, [r7, #4] __HAL_LOCK(hhcd); 800226e: 687b ldr r3, [r7, #4] 8002270: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4 8002274: 2b01 cmp r3, #1 8002276: d101 bne.n 800227c 8002278: 2302 movs r3, #2 800227a: e00d b.n 8002298 800227c: 687b ldr r3, [r7, #4] 800227e: 2201 movs r2, #1 8002280: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4 (void)USB_StopHost(hhcd->Instance); 8002284: 687b ldr r3, [r7, #4] 8002286: 681b ldr r3, [r3, #0] 8002288: 4618 mov r0, r3 800228a: f004 fb1d bl 80068c8 __HAL_UNLOCK(hhcd); 800228e: 687b ldr r3, [r7, #4] 8002290: 2200 movs r2, #0 8002292: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4 return HAL_OK; 8002296: 2300 movs r3, #0 } 8002298: 4618 mov r0, r3 800229a: 3708 adds r7, #8 800229c: 46bd mov sp, r7 800229e: bd80 pop {r7, pc} 080022a0 : * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { 80022a0: b580 push {r7, lr} 80022a2: b086 sub sp, #24 80022a4: af00 add r7, sp, #0 80022a6: 6078 str r0, [r7, #4] 80022a8: 460b mov r3, r1 80022aa: 70fb strb r3, [r7, #3] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 80022ac: 687b ldr r3, [r7, #4] 80022ae: 681b ldr r3, [r3, #0] 80022b0: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 80022b2: 697b ldr r3, [r7, #20] 80022b4: 613b str r3, [r7, #16] uint32_t tmpreg; if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) 80022b6: 687b ldr r3, [r7, #4] 80022b8: 681b ldr r3, [r3, #0] 80022ba: 78fa ldrb r2, [r7, #3] 80022bc: 4611 mov r1, r2 80022be: 4618 mov r0, r3 80022c0: f004 f965 bl 800658e 80022c4: 4603 mov r3, r0 80022c6: f003 0304 and.w r3, r3, #4 80022ca: 2b04 cmp r3, #4 80022cc: d11a bne.n 8002304 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); 80022ce: 78fb ldrb r3, [r7, #3] 80022d0: 015a lsls r2, r3, #5 80022d2: 693b ldr r3, [r7, #16] 80022d4: 4413 add r3, r2 80022d6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80022da: 461a mov r2, r3 80022dc: 2304 movs r3, #4 80022de: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 80022e0: 78fa ldrb r2, [r7, #3] 80022e2: 6879 ldr r1, [r7, #4] 80022e4: 4613 mov r3, r2 80022e6: 011b lsls r3, r3, #4 80022e8: 1a9b subs r3, r3, r2 80022ea: 009b lsls r3, r3, #2 80022ec: 440b add r3, r1 80022ee: 334d adds r3, #77 @ 0x4d 80022f0: 2207 movs r2, #7 80022f2: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80022f4: 687b ldr r3, [r7, #4] 80022f6: 681b ldr r3, [r3, #0] 80022f8: 78fa ldrb r2, [r7, #3] 80022fa: 4611 mov r1, r2 80022fc: 4618 mov r0, r3 80022fe: f004 f9c3 bl 8006688 8002302: e09e b.n 8002442 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) 8002304: 687b ldr r3, [r7, #4] 8002306: 681b ldr r3, [r3, #0] 8002308: 78fa ldrb r2, [r7, #3] 800230a: 4611 mov r1, r2 800230c: 4618 mov r0, r3 800230e: f004 f93e bl 800658e 8002312: 4603 mov r3, r0 8002314: f403 7380 and.w r3, r3, #256 @ 0x100 8002318: f5b3 7f80 cmp.w r3, #256 @ 0x100 800231c: d11b bne.n 8002356 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); 800231e: 78fb ldrb r3, [r7, #3] 8002320: 015a lsls r2, r3, #5 8002322: 693b ldr r3, [r7, #16] 8002324: 4413 add r3, r2 8002326: f503 63a0 add.w r3, r3, #1280 @ 0x500 800232a: 461a mov r2, r3 800232c: f44f 7380 mov.w r3, #256 @ 0x100 8002330: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_BBLERR; 8002332: 78fa ldrb r2, [r7, #3] 8002334: 6879 ldr r1, [r7, #4] 8002336: 4613 mov r3, r2 8002338: 011b lsls r3, r3, #4 800233a: 1a9b subs r3, r3, r2 800233c: 009b lsls r3, r3, #2 800233e: 440b add r3, r1 8002340: 334d adds r3, #77 @ 0x4d 8002342: 2208 movs r2, #8 8002344: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002346: 687b ldr r3, [r7, #4] 8002348: 681b ldr r3, [r3, #0] 800234a: 78fa ldrb r2, [r7, #3] 800234c: 4611 mov r1, r2 800234e: 4618 mov r0, r3 8002350: f004 f99a bl 8006688 8002354: e075 b.n 8002442 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) 8002356: 687b ldr r3, [r7, #4] 8002358: 681b ldr r3, [r3, #0] 800235a: 78fa ldrb r2, [r7, #3] 800235c: 4611 mov r1, r2 800235e: 4618 mov r0, r3 8002360: f004 f915 bl 800658e 8002364: 4603 mov r3, r0 8002366: f003 0308 and.w r3, r3, #8 800236a: 2b08 cmp r3, #8 800236c: d11a bne.n 80023a4 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); 800236e: 78fb ldrb r3, [r7, #3] 8002370: 015a lsls r2, r3, #5 8002372: 693b ldr r3, [r7, #16] 8002374: 4413 add r3, r2 8002376: f503 63a0 add.w r3, r3, #1280 @ 0x500 800237a: 461a mov r2, r3 800237c: 2308 movs r3, #8 800237e: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_STALL; 8002380: 78fa ldrb r2, [r7, #3] 8002382: 6879 ldr r1, [r7, #4] 8002384: 4613 mov r3, r2 8002386: 011b lsls r3, r3, #4 8002388: 1a9b subs r3, r3, r2 800238a: 009b lsls r3, r3, #2 800238c: 440b add r3, r1 800238e: 334d adds r3, #77 @ 0x4d 8002390: 2206 movs r2, #6 8002392: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002394: 687b ldr r3, [r7, #4] 8002396: 681b ldr r3, [r3, #0] 8002398: 78fa ldrb r2, [r7, #3] 800239a: 4611 mov r1, r2 800239c: 4618 mov r0, r3 800239e: f004 f973 bl 8006688 80023a2: e04e b.n 8002442 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) 80023a4: 687b ldr r3, [r7, #4] 80023a6: 681b ldr r3, [r3, #0] 80023a8: 78fa ldrb r2, [r7, #3] 80023aa: 4611 mov r1, r2 80023ac: 4618 mov r0, r3 80023ae: f004 f8ee bl 800658e 80023b2: 4603 mov r3, r0 80023b4: f403 6380 and.w r3, r3, #1024 @ 0x400 80023b8: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80023bc: d11b bne.n 80023f6 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); 80023be: 78fb ldrb r3, [r7, #3] 80023c0: 015a lsls r2, r3, #5 80023c2: 693b ldr r3, [r7, #16] 80023c4: 4413 add r3, r2 80023c6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80023ca: 461a mov r2, r3 80023cc: f44f 6380 mov.w r3, #1024 @ 0x400 80023d0: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_DATATGLERR; 80023d2: 78fa ldrb r2, [r7, #3] 80023d4: 6879 ldr r1, [r7, #4] 80023d6: 4613 mov r3, r2 80023d8: 011b lsls r3, r3, #4 80023da: 1a9b subs r3, r3, r2 80023dc: 009b lsls r3, r3, #2 80023de: 440b add r3, r1 80023e0: 334d adds r3, #77 @ 0x4d 80023e2: 2209 movs r2, #9 80023e4: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80023e6: 687b ldr r3, [r7, #4] 80023e8: 681b ldr r3, [r3, #0] 80023ea: 78fa ldrb r2, [r7, #3] 80023ec: 4611 mov r1, r2 80023ee: 4618 mov r0, r3 80023f0: f004 f94a bl 8006688 80023f4: e025 b.n 8002442 } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) 80023f6: 687b ldr r3, [r7, #4] 80023f8: 681b ldr r3, [r3, #0] 80023fa: 78fa ldrb r2, [r7, #3] 80023fc: 4611 mov r1, r2 80023fe: 4618 mov r0, r3 8002400: f004 f8c5 bl 800658e 8002404: 4603 mov r3, r0 8002406: f003 0380 and.w r3, r3, #128 @ 0x80 800240a: 2b80 cmp r3, #128 @ 0x80 800240c: d119 bne.n 8002442 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); 800240e: 78fb ldrb r3, [r7, #3] 8002410: 015a lsls r2, r3, #5 8002412: 693b ldr r3, [r7, #16] 8002414: 4413 add r3, r2 8002416: f503 63a0 add.w r3, r3, #1280 @ 0x500 800241a: 461a mov r2, r3 800241c: 2380 movs r3, #128 @ 0x80 800241e: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 8002420: 78fa ldrb r2, [r7, #3] 8002422: 6879 ldr r1, [r7, #4] 8002424: 4613 mov r3, r2 8002426: 011b lsls r3, r3, #4 8002428: 1a9b subs r3, r3, r2 800242a: 009b lsls r3, r3, #2 800242c: 440b add r3, r1 800242e: 334d adds r3, #77 @ 0x4d 8002430: 2207 movs r2, #7 8002432: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002434: 687b ldr r3, [r7, #4] 8002436: 681b ldr r3, [r3, #0] 8002438: 78fa ldrb r2, [r7, #3] 800243a: 4611 mov r1, r2 800243c: 4618 mov r0, r3 800243e: f004 f923 bl 8006688 else { /* ... */ } if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) 8002442: 687b ldr r3, [r7, #4] 8002444: 681b ldr r3, [r3, #0] 8002446: 78fa ldrb r2, [r7, #3] 8002448: 4611 mov r1, r2 800244a: 4618 mov r0, r3 800244c: f004 f89f bl 800658e 8002450: 4603 mov r3, r0 8002452: f403 7300 and.w r3, r3, #512 @ 0x200 8002456: f5b3 7f00 cmp.w r3, #512 @ 0x200 800245a: d112 bne.n 8002482 { (void)USB_HC_Halt(hhcd->Instance, chnum); 800245c: 687b ldr r3, [r7, #4] 800245e: 681b ldr r3, [r3, #0] 8002460: 78fa ldrb r2, [r7, #3] 8002462: 4611 mov r1, r2 8002464: 4618 mov r0, r3 8002466: f004 f90f bl 8006688 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); 800246a: 78fb ldrb r3, [r7, #3] 800246c: 015a lsls r2, r3, #5 800246e: 693b ldr r3, [r7, #16] 8002470: 4413 add r3, r2 8002472: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002476: 461a mov r2, r3 8002478: f44f 7300 mov.w r3, #512 @ 0x200 800247c: 6093 str r3, [r2, #8] 800247e: f000 bd75 b.w 8002f6c } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) 8002482: 687b ldr r3, [r7, #4] 8002484: 681b ldr r3, [r3, #0] 8002486: 78fa ldrb r2, [r7, #3] 8002488: 4611 mov r1, r2 800248a: 4618 mov r0, r3 800248c: f004 f87f bl 800658e 8002490: 4603 mov r3, r0 8002492: f003 0301 and.w r3, r3, #1 8002496: 2b01 cmp r3, #1 8002498: f040 8128 bne.w 80026ec { /* Clear any pending ACK IT */ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 800249c: 78fb ldrb r3, [r7, #3] 800249e: 015a lsls r2, r3, #5 80024a0: 693b ldr r3, [r7, #16] 80024a2: 4413 add r3, r2 80024a4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80024a8: 461a mov r2, r3 80024aa: 2320 movs r3, #32 80024ac: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_csplit == 1U) 80024ae: 78fa ldrb r2, [r7, #3] 80024b0: 6879 ldr r1, [r7, #4] 80024b2: 4613 mov r3, r2 80024b4: 011b lsls r3, r3, #4 80024b6: 1a9b subs r3, r3, r2 80024b8: 009b lsls r3, r3, #2 80024ba: 440b add r3, r1 80024bc: 331b adds r3, #27 80024be: 781b ldrb r3, [r3, #0] 80024c0: 2b01 cmp r3, #1 80024c2: d119 bne.n 80024f8 { hhcd->hc[chnum].do_csplit = 0U; 80024c4: 78fa ldrb r2, [r7, #3] 80024c6: 6879 ldr r1, [r7, #4] 80024c8: 4613 mov r3, r2 80024ca: 011b lsls r3, r3, #4 80024cc: 1a9b subs r3, r3, r2 80024ce: 009b lsls r3, r3, #2 80024d0: 440b add r3, r1 80024d2: 331b adds r3, #27 80024d4: 2200 movs r2, #0 80024d6: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 80024d8: 78fb ldrb r3, [r7, #3] 80024da: 015a lsls r2, r3, #5 80024dc: 693b ldr r3, [r7, #16] 80024de: 4413 add r3, r2 80024e0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80024e4: 685b ldr r3, [r3, #4] 80024e6: 78fa ldrb r2, [r7, #3] 80024e8: 0151 lsls r1, r2, #5 80024ea: 693a ldr r2, [r7, #16] 80024ec: 440a add r2, r1 80024ee: f502 62a0 add.w r2, r2, #1280 @ 0x500 80024f2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80024f6: 6053 str r3, [r2, #4] } if (hhcd->Init.dma_enable != 0U) 80024f8: 687b ldr r3, [r7, #4] 80024fa: 799b ldrb r3, [r3, #6] 80024fc: 2b00 cmp r3, #0 80024fe: d01b beq.n 8002538 { hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); 8002500: 78fa ldrb r2, [r7, #3] 8002502: 6879 ldr r1, [r7, #4] 8002504: 4613 mov r3, r2 8002506: 011b lsls r3, r3, #4 8002508: 1a9b subs r3, r3, r2 800250a: 009b lsls r3, r3, #2 800250c: 440b add r3, r1 800250e: 3330 adds r3, #48 @ 0x30 8002510: 6819 ldr r1, [r3, #0] 8002512: 78fb ldrb r3, [r7, #3] 8002514: 015a lsls r2, r3, #5 8002516: 693b ldr r3, [r7, #16] 8002518: 4413 add r3, r2 800251a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800251e: 691b ldr r3, [r3, #16] 8002520: f3c3 0312 ubfx r3, r3, #0, #19 8002524: 78fa ldrb r2, [r7, #3] 8002526: 1ac9 subs r1, r1, r3 8002528: 6878 ldr r0, [r7, #4] 800252a: 4613 mov r3, r2 800252c: 011b lsls r3, r3, #4 800252e: 1a9b subs r3, r3, r2 8002530: 009b lsls r3, r3, #2 8002532: 4403 add r3, r0 8002534: 3338 adds r3, #56 @ 0x38 8002536: 6019 str r1, [r3, #0] } hhcd->hc[chnum].state = HC_XFRC; 8002538: 78fa ldrb r2, [r7, #3] 800253a: 6879 ldr r1, [r7, #4] 800253c: 4613 mov r3, r2 800253e: 011b lsls r3, r3, #4 8002540: 1a9b subs r3, r3, r2 8002542: 009b lsls r3, r3, #2 8002544: 440b add r3, r1 8002546: 334d adds r3, #77 @ 0x4d 8002548: 2201 movs r2, #1 800254a: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt = 0U; 800254c: 78fa ldrb r2, [r7, #3] 800254e: 6879 ldr r1, [r7, #4] 8002550: 4613 mov r3, r2 8002552: 011b lsls r3, r3, #4 8002554: 1a9b subs r3, r3, r2 8002556: 009b lsls r3, r3, #2 8002558: 440b add r3, r1 800255a: 3344 adds r3, #68 @ 0x44 800255c: 2200 movs r2, #0 800255e: 601a str r2, [r3, #0] __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); 8002560: 78fb ldrb r3, [r7, #3] 8002562: 015a lsls r2, r3, #5 8002564: 693b ldr r3, [r7, #16] 8002566: 4413 add r3, r2 8002568: f503 63a0 add.w r3, r3, #1280 @ 0x500 800256c: 461a mov r2, r3 800256e: 2301 movs r3, #1 8002570: 6093 str r3, [r2, #8] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002572: 78fa ldrb r2, [r7, #3] 8002574: 6879 ldr r1, [r7, #4] 8002576: 4613 mov r3, r2 8002578: 011b lsls r3, r3, #4 800257a: 1a9b subs r3, r3, r2 800257c: 009b lsls r3, r3, #2 800257e: 440b add r3, r1 8002580: 3326 adds r3, #38 @ 0x26 8002582: 781b ldrb r3, [r3, #0] 8002584: 2b00 cmp r3, #0 8002586: d00a beq.n 800259e (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002588: 78fa ldrb r2, [r7, #3] 800258a: 6879 ldr r1, [r7, #4] 800258c: 4613 mov r3, r2 800258e: 011b lsls r3, r3, #4 8002590: 1a9b subs r3, r3, r2 8002592: 009b lsls r3, r3, #2 8002594: 440b add r3, r1 8002596: 3326 adds r3, #38 @ 0x26 8002598: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 800259a: 2b02 cmp r3, #2 800259c: d110 bne.n 80025c0 { (void)USB_HC_Halt(hhcd->Instance, chnum); 800259e: 687b ldr r3, [r7, #4] 80025a0: 681b ldr r3, [r3, #0] 80025a2: 78fa ldrb r2, [r7, #3] 80025a4: 4611 mov r1, r2 80025a6: 4618 mov r0, r3 80025a8: f004 f86e bl 8006688 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 80025ac: 78fb ldrb r3, [r7, #3] 80025ae: 015a lsls r2, r3, #5 80025b0: 693b ldr r3, [r7, #16] 80025b2: 4413 add r3, r2 80025b4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80025b8: 461a mov r2, r3 80025ba: 2310 movs r3, #16 80025bc: 6093 str r3, [r2, #8] 80025be: e03d b.n 800263c } else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || 80025c0: 78fa ldrb r2, [r7, #3] 80025c2: 6879 ldr r1, [r7, #4] 80025c4: 4613 mov r3, r2 80025c6: 011b lsls r3, r3, #4 80025c8: 1a9b subs r3, r3, r2 80025ca: 009b lsls r3, r3, #2 80025cc: 440b add r3, r1 80025ce: 3326 adds r3, #38 @ 0x26 80025d0: 781b ldrb r3, [r3, #0] 80025d2: 2b03 cmp r3, #3 80025d4: d00a beq.n 80025ec (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) 80025d6: 78fa ldrb r2, [r7, #3] 80025d8: 6879 ldr r1, [r7, #4] 80025da: 4613 mov r3, r2 80025dc: 011b lsls r3, r3, #4 80025de: 1a9b subs r3, r3, r2 80025e0: 009b lsls r3, r3, #2 80025e2: 440b add r3, r1 80025e4: 3326 adds r3, #38 @ 0x26 80025e6: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || 80025e8: 2b01 cmp r3, #1 80025ea: d127 bne.n 800263c { USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; 80025ec: 78fb ldrb r3, [r7, #3] 80025ee: 015a lsls r2, r3, #5 80025f0: 693b ldr r3, [r7, #16] 80025f2: 4413 add r3, r2 80025f4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80025f8: 681b ldr r3, [r3, #0] 80025fa: 78fa ldrb r2, [r7, #3] 80025fc: 0151 lsls r1, r2, #5 80025fe: 693a ldr r2, [r7, #16] 8002600: 440a add r2, r1 8002602: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002606: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000 800260a: 6013 str r3, [r2, #0] hhcd->hc[chnum].urb_state = URB_DONE; 800260c: 78fa ldrb r2, [r7, #3] 800260e: 6879 ldr r1, [r7, #4] 8002610: 4613 mov r3, r2 8002612: 011b lsls r3, r3, #4 8002614: 1a9b subs r3, r3, r2 8002616: 009b lsls r3, r3, #2 8002618: 440b add r3, r1 800261a: 334c adds r3, #76 @ 0x4c 800261c: 2201 movs r2, #1 800261e: 701a strb r2, [r3, #0] #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 8002620: 78fa ldrb r2, [r7, #3] 8002622: 6879 ldr r1, [r7, #4] 8002624: 4613 mov r3, r2 8002626: 011b lsls r3, r3, #4 8002628: 1a9b subs r3, r3, r2 800262a: 009b lsls r3, r3, #2 800262c: 440b add r3, r1 800262e: 334c adds r3, #76 @ 0x4c 8002630: 781a ldrb r2, [r3, #0] 8002632: 78fb ldrb r3, [r7, #3] 8002634: 4619 mov r1, r3 8002636: 6878 ldr r0, [r7, #4] 8002638: f005 fbbc bl 8007db4 else { /* ... */ } if (hhcd->Init.dma_enable == 1U) 800263c: 687b ldr r3, [r7, #4] 800263e: 799b ldrb r3, [r3, #6] 8002640: 2b01 cmp r3, #1 8002642: d13b bne.n 80026bc { if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) 8002644: 78fa ldrb r2, [r7, #3] 8002646: 6879 ldr r1, [r7, #4] 8002648: 4613 mov r3, r2 800264a: 011b lsls r3, r3, #4 800264c: 1a9b subs r3, r3, r2 800264e: 009b lsls r3, r3, #2 8002650: 440b add r3, r1 8002652: 3338 adds r3, #56 @ 0x38 8002654: 6819 ldr r1, [r3, #0] 8002656: 78fa ldrb r2, [r7, #3] 8002658: 6878 ldr r0, [r7, #4] 800265a: 4613 mov r3, r2 800265c: 011b lsls r3, r3, #4 800265e: 1a9b subs r3, r3, r2 8002660: 009b lsls r3, r3, #2 8002662: 4403 add r3, r0 8002664: 3328 adds r3, #40 @ 0x28 8002666: 881b ldrh r3, [r3, #0] 8002668: 440b add r3, r1 800266a: 1e59 subs r1, r3, #1 800266c: 78fa ldrb r2, [r7, #3] 800266e: 6878 ldr r0, [r7, #4] 8002670: 4613 mov r3, r2 8002672: 011b lsls r3, r3, #4 8002674: 1a9b subs r3, r3, r2 8002676: 009b lsls r3, r3, #2 8002678: 4403 add r3, r0 800267a: 3328 adds r3, #40 @ 0x28 800267c: 881b ldrh r3, [r3, #0] 800267e: fbb1 f3f3 udiv r3, r1, r3 8002682: f003 0301 and.w r3, r3, #1 8002686: 2b00 cmp r3, #0 8002688: f000 8470 beq.w 8002f6c { hhcd->hc[chnum].toggle_in ^= 1U; 800268c: 78fa ldrb r2, [r7, #3] 800268e: 6879 ldr r1, [r7, #4] 8002690: 4613 mov r3, r2 8002692: 011b lsls r3, r3, #4 8002694: 1a9b subs r3, r3, r2 8002696: 009b lsls r3, r3, #2 8002698: 440b add r3, r1 800269a: 333c adds r3, #60 @ 0x3c 800269c: 781b ldrb r3, [r3, #0] 800269e: 78fa ldrb r2, [r7, #3] 80026a0: f083 0301 eor.w r3, r3, #1 80026a4: b2d8 uxtb r0, r3 80026a6: 6879 ldr r1, [r7, #4] 80026a8: 4613 mov r3, r2 80026aa: 011b lsls r3, r3, #4 80026ac: 1a9b subs r3, r3, r2 80026ae: 009b lsls r3, r3, #2 80026b0: 440b add r3, r1 80026b2: 333c adds r3, #60 @ 0x3c 80026b4: 4602 mov r2, r0 80026b6: 701a strb r2, [r3, #0] 80026b8: f000 bc58 b.w 8002f6c } } else { hhcd->hc[chnum].toggle_in ^= 1U; 80026bc: 78fa ldrb r2, [r7, #3] 80026be: 6879 ldr r1, [r7, #4] 80026c0: 4613 mov r3, r2 80026c2: 011b lsls r3, r3, #4 80026c4: 1a9b subs r3, r3, r2 80026c6: 009b lsls r3, r3, #2 80026c8: 440b add r3, r1 80026ca: 333c adds r3, #60 @ 0x3c 80026cc: 781b ldrb r3, [r3, #0] 80026ce: 78fa ldrb r2, [r7, #3] 80026d0: f083 0301 eor.w r3, r3, #1 80026d4: b2d8 uxtb r0, r3 80026d6: 6879 ldr r1, [r7, #4] 80026d8: 4613 mov r3, r2 80026da: 011b lsls r3, r3, #4 80026dc: 1a9b subs r3, r3, r2 80026de: 009b lsls r3, r3, #2 80026e0: 440b add r3, r1 80026e2: 333c adds r3, #60 @ 0x3c 80026e4: 4602 mov r2, r0 80026e6: 701a strb r2, [r3, #0] 80026e8: f000 bc40 b.w 8002f6c } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) 80026ec: 687b ldr r3, [r7, #4] 80026ee: 681b ldr r3, [r3, #0] 80026f0: 78fa ldrb r2, [r7, #3] 80026f2: 4611 mov r1, r2 80026f4: 4618 mov r0, r3 80026f6: f003 ff4a bl 800658e 80026fa: 4603 mov r3, r0 80026fc: f003 0320 and.w r3, r3, #32 8002700: 2b20 cmp r3, #32 8002702: d131 bne.n 8002768 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 8002704: 78fb ldrb r3, [r7, #3] 8002706: 015a lsls r2, r3, #5 8002708: 693b ldr r3, [r7, #16] 800270a: 4413 add r3, r2 800270c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002710: 461a mov r2, r3 8002712: 2320 movs r3, #32 8002714: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_ssplit == 1U) 8002716: 78fa ldrb r2, [r7, #3] 8002718: 6879 ldr r1, [r7, #4] 800271a: 4613 mov r3, r2 800271c: 011b lsls r3, r3, #4 800271e: 1a9b subs r3, r3, r2 8002720: 009b lsls r3, r3, #2 8002722: 440b add r3, r1 8002724: 331a adds r3, #26 8002726: 781b ldrb r3, [r3, #0] 8002728: 2b01 cmp r3, #1 800272a: f040 841f bne.w 8002f6c { hhcd->hc[chnum].do_csplit = 1U; 800272e: 78fa ldrb r2, [r7, #3] 8002730: 6879 ldr r1, [r7, #4] 8002732: 4613 mov r3, r2 8002734: 011b lsls r3, r3, #4 8002736: 1a9b subs r3, r3, r2 8002738: 009b lsls r3, r3, #2 800273a: 440b add r3, r1 800273c: 331b adds r3, #27 800273e: 2201 movs r2, #1 8002740: 701a strb r2, [r3, #0] hhcd->hc[chnum].state = HC_ACK; 8002742: 78fa ldrb r2, [r7, #3] 8002744: 6879 ldr r1, [r7, #4] 8002746: 4613 mov r3, r2 8002748: 011b lsls r3, r3, #4 800274a: 1a9b subs r3, r3, r2 800274c: 009b lsls r3, r3, #2 800274e: 440b add r3, r1 8002750: 334d adds r3, #77 @ 0x4d 8002752: 2203 movs r2, #3 8002754: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002756: 687b ldr r3, [r7, #4] 8002758: 681b ldr r3, [r3, #0] 800275a: 78fa ldrb r2, [r7, #3] 800275c: 4611 mov r1, r2 800275e: 4618 mov r0, r3 8002760: f003 ff92 bl 8006688 8002764: f000 bc02 b.w 8002f6c } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) 8002768: 687b ldr r3, [r7, #4] 800276a: 681b ldr r3, [r3, #0] 800276c: 78fa ldrb r2, [r7, #3] 800276e: 4611 mov r1, r2 8002770: 4618 mov r0, r3 8002772: f003 ff0c bl 800658e 8002776: 4603 mov r3, r0 8002778: f003 0302 and.w r3, r3, #2 800277c: 2b02 cmp r3, #2 800277e: f040 8305 bne.w 8002d8c { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); 8002782: 78fb ldrb r3, [r7, #3] 8002784: 015a lsls r2, r3, #5 8002786: 693b ldr r3, [r7, #16] 8002788: 4413 add r3, r2 800278a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800278e: 461a mov r2, r3 8002790: 2302 movs r3, #2 8002792: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].state == HC_XFRC) 8002794: 78fa ldrb r2, [r7, #3] 8002796: 6879 ldr r1, [r7, #4] 8002798: 4613 mov r3, r2 800279a: 011b lsls r3, r3, #4 800279c: 1a9b subs r3, r3, r2 800279e: 009b lsls r3, r3, #2 80027a0: 440b add r3, r1 80027a2: 334d adds r3, #77 @ 0x4d 80027a4: 781b ldrb r3, [r3, #0] 80027a6: 2b01 cmp r3, #1 80027a8: d114 bne.n 80027d4 { hhcd->hc[chnum].state = HC_HALTED; 80027aa: 78fa ldrb r2, [r7, #3] 80027ac: 6879 ldr r1, [r7, #4] 80027ae: 4613 mov r3, r2 80027b0: 011b lsls r3, r3, #4 80027b2: 1a9b subs r3, r3, r2 80027b4: 009b lsls r3, r3, #2 80027b6: 440b add r3, r1 80027b8: 334d adds r3, #77 @ 0x4d 80027ba: 2202 movs r2, #2 80027bc: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_DONE; 80027be: 78fa ldrb r2, [r7, #3] 80027c0: 6879 ldr r1, [r7, #4] 80027c2: 4613 mov r3, r2 80027c4: 011b lsls r3, r3, #4 80027c6: 1a9b subs r3, r3, r2 80027c8: 009b lsls r3, r3, #2 80027ca: 440b add r3, r1 80027cc: 334c adds r3, #76 @ 0x4c 80027ce: 2201 movs r2, #1 80027d0: 701a strb r2, [r3, #0] 80027d2: e2cc b.n 8002d6e } else if (hhcd->hc[chnum].state == HC_STALL) 80027d4: 78fa ldrb r2, [r7, #3] 80027d6: 6879 ldr r1, [r7, #4] 80027d8: 4613 mov r3, r2 80027da: 011b lsls r3, r3, #4 80027dc: 1a9b subs r3, r3, r2 80027de: 009b lsls r3, r3, #2 80027e0: 440b add r3, r1 80027e2: 334d adds r3, #77 @ 0x4d 80027e4: 781b ldrb r3, [r3, #0] 80027e6: 2b06 cmp r3, #6 80027e8: d114 bne.n 8002814 { hhcd->hc[chnum].state = HC_HALTED; 80027ea: 78fa ldrb r2, [r7, #3] 80027ec: 6879 ldr r1, [r7, #4] 80027ee: 4613 mov r3, r2 80027f0: 011b lsls r3, r3, #4 80027f2: 1a9b subs r3, r3, r2 80027f4: 009b lsls r3, r3, #2 80027f6: 440b add r3, r1 80027f8: 334d adds r3, #77 @ 0x4d 80027fa: 2202 movs r2, #2 80027fc: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_STALL; 80027fe: 78fa ldrb r2, [r7, #3] 8002800: 6879 ldr r1, [r7, #4] 8002802: 4613 mov r3, r2 8002804: 011b lsls r3, r3, #4 8002806: 1a9b subs r3, r3, r2 8002808: 009b lsls r3, r3, #2 800280a: 440b add r3, r1 800280c: 334c adds r3, #76 @ 0x4c 800280e: 2205 movs r2, #5 8002810: 701a strb r2, [r3, #0] 8002812: e2ac b.n 8002d6e } else if ((hhcd->hc[chnum].state == HC_XACTERR) || 8002814: 78fa ldrb r2, [r7, #3] 8002816: 6879 ldr r1, [r7, #4] 8002818: 4613 mov r3, r2 800281a: 011b lsls r3, r3, #4 800281c: 1a9b subs r3, r3, r2 800281e: 009b lsls r3, r3, #2 8002820: 440b add r3, r1 8002822: 334d adds r3, #77 @ 0x4d 8002824: 781b ldrb r3, [r3, #0] 8002826: 2b07 cmp r3, #7 8002828: d00b beq.n 8002842 (hhcd->hc[chnum].state == HC_DATATGLERR)) 800282a: 78fa ldrb r2, [r7, #3] 800282c: 6879 ldr r1, [r7, #4] 800282e: 4613 mov r3, r2 8002830: 011b lsls r3, r3, #4 8002832: 1a9b subs r3, r3, r2 8002834: 009b lsls r3, r3, #2 8002836: 440b add r3, r1 8002838: 334d adds r3, #77 @ 0x4d 800283a: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].state == HC_XACTERR) || 800283c: 2b09 cmp r3, #9 800283e: f040 80a6 bne.w 800298e { hhcd->hc[chnum].state = HC_HALTED; 8002842: 78fa ldrb r2, [r7, #3] 8002844: 6879 ldr r1, [r7, #4] 8002846: 4613 mov r3, r2 8002848: 011b lsls r3, r3, #4 800284a: 1a9b subs r3, r3, r2 800284c: 009b lsls r3, r3, #2 800284e: 440b add r3, r1 8002850: 334d adds r3, #77 @ 0x4d 8002852: 2202 movs r2, #2 8002854: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 8002856: 78fa ldrb r2, [r7, #3] 8002858: 6879 ldr r1, [r7, #4] 800285a: 4613 mov r3, r2 800285c: 011b lsls r3, r3, #4 800285e: 1a9b subs r3, r3, r2 8002860: 009b lsls r3, r3, #2 8002862: 440b add r3, r1 8002864: 3344 adds r3, #68 @ 0x44 8002866: 681b ldr r3, [r3, #0] 8002868: 1c59 adds r1, r3, #1 800286a: 6878 ldr r0, [r7, #4] 800286c: 4613 mov r3, r2 800286e: 011b lsls r3, r3, #4 8002870: 1a9b subs r3, r3, r2 8002872: 009b lsls r3, r3, #2 8002874: 4403 add r3, r0 8002876: 3344 adds r3, #68 @ 0x44 8002878: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800287a: 78fa ldrb r2, [r7, #3] 800287c: 6879 ldr r1, [r7, #4] 800287e: 4613 mov r3, r2 8002880: 011b lsls r3, r3, #4 8002882: 1a9b subs r3, r3, r2 8002884: 009b lsls r3, r3, #2 8002886: 440b add r3, r1 8002888: 3344 adds r3, #68 @ 0x44 800288a: 681b ldr r3, [r3, #0] 800288c: 2b02 cmp r3, #2 800288e: d943 bls.n 8002918 { hhcd->hc[chnum].ErrCnt = 0U; 8002890: 78fa ldrb r2, [r7, #3] 8002892: 6879 ldr r1, [r7, #4] 8002894: 4613 mov r3, r2 8002896: 011b lsls r3, r3, #4 8002898: 1a9b subs r3, r3, r2 800289a: 009b lsls r3, r3, #2 800289c: 440b add r3, r1 800289e: 3344 adds r3, #68 @ 0x44 80028a0: 2200 movs r2, #0 80028a2: 601a str r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 1U) 80028a4: 78fa ldrb r2, [r7, #3] 80028a6: 6879 ldr r1, [r7, #4] 80028a8: 4613 mov r3, r2 80028aa: 011b lsls r3, r3, #4 80028ac: 1a9b subs r3, r3, r2 80028ae: 009b lsls r3, r3, #2 80028b0: 440b add r3, r1 80028b2: 331a adds r3, #26 80028b4: 781b ldrb r3, [r3, #0] 80028b6: 2b01 cmp r3, #1 80028b8: d123 bne.n 8002902 { hhcd->hc[chnum].do_csplit = 0U; 80028ba: 78fa ldrb r2, [r7, #3] 80028bc: 6879 ldr r1, [r7, #4] 80028be: 4613 mov r3, r2 80028c0: 011b lsls r3, r3, #4 80028c2: 1a9b subs r3, r3, r2 80028c4: 009b lsls r3, r3, #2 80028c6: 440b add r3, r1 80028c8: 331b adds r3, #27 80028ca: 2200 movs r2, #0 80028cc: 701a strb r2, [r3, #0] hhcd->hc[chnum].ep_ss_schedule = 0U; 80028ce: 78fa ldrb r2, [r7, #3] 80028d0: 6879 ldr r1, [r7, #4] 80028d2: 4613 mov r3, r2 80028d4: 011b lsls r3, r3, #4 80028d6: 1a9b subs r3, r3, r2 80028d8: 009b lsls r3, r3, #2 80028da: 440b add r3, r1 80028dc: 331c adds r3, #28 80028de: 2200 movs r2, #0 80028e0: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 80028e2: 78fb ldrb r3, [r7, #3] 80028e4: 015a lsls r2, r3, #5 80028e6: 693b ldr r3, [r7, #16] 80028e8: 4413 add r3, r2 80028ea: f503 63a0 add.w r3, r3, #1280 @ 0x500 80028ee: 685b ldr r3, [r3, #4] 80028f0: 78fa ldrb r2, [r7, #3] 80028f2: 0151 lsls r1, r2, #5 80028f4: 693a ldr r2, [r7, #16] 80028f6: 440a add r2, r1 80028f8: f502 62a0 add.w r2, r2, #1280 @ 0x500 80028fc: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002900: 6053 str r3, [r2, #4] } hhcd->hc[chnum].urb_state = URB_ERROR; 8002902: 78fa ldrb r2, [r7, #3] 8002904: 6879 ldr r1, [r7, #4] 8002906: 4613 mov r3, r2 8002908: 011b lsls r3, r3, #4 800290a: 1a9b subs r3, r3, r2 800290c: 009b lsls r3, r3, #2 800290e: 440b add r3, r1 8002910: 334c adds r3, #76 @ 0x4c 8002912: 2204 movs r2, #4 8002914: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 8002916: e229 b.n 8002d6c } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002918: 78fa ldrb r2, [r7, #3] 800291a: 6879 ldr r1, [r7, #4] 800291c: 4613 mov r3, r2 800291e: 011b lsls r3, r3, #4 8002920: 1a9b subs r3, r3, r2 8002922: 009b lsls r3, r3, #2 8002924: 440b add r3, r1 8002926: 334c adds r3, #76 @ 0x4c 8002928: 2202 movs r2, #2 800292a: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 800292c: 78fa ldrb r2, [r7, #3] 800292e: 6879 ldr r1, [r7, #4] 8002930: 4613 mov r3, r2 8002932: 011b lsls r3, r3, #4 8002934: 1a9b subs r3, r3, r2 8002936: 009b lsls r3, r3, #2 8002938: 440b add r3, r1 800293a: 3326 adds r3, #38 @ 0x26 800293c: 781b ldrb r3, [r3, #0] 800293e: 2b00 cmp r3, #0 8002940: d00b beq.n 800295a (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002942: 78fa ldrb r2, [r7, #3] 8002944: 6879 ldr r1, [r7, #4] 8002946: 4613 mov r3, r2 8002948: 011b lsls r3, r3, #4 800294a: 1a9b subs r3, r3, r2 800294c: 009b lsls r3, r3, #2 800294e: 440b add r3, r1 8002950: 3326 adds r3, #38 @ 0x26 8002952: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002954: 2b02 cmp r3, #2 8002956: f040 8209 bne.w 8002d6c { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 800295a: 78fb ldrb r3, [r7, #3] 800295c: 015a lsls r2, r3, #5 800295e: 693b ldr r3, [r7, #16] 8002960: 4413 add r3, r2 8002962: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002966: 681b ldr r3, [r3, #0] 8002968: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 800296a: 68fb ldr r3, [r7, #12] 800296c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002970: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002972: 68fb ldr r3, [r7, #12] 8002974: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002978: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 800297a: 78fb ldrb r3, [r7, #3] 800297c: 015a lsls r2, r3, #5 800297e: 693b ldr r3, [r7, #16] 8002980: 4413 add r3, r2 8002982: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002986: 461a mov r2, r3 8002988: 68fb ldr r3, [r7, #12] 800298a: 6013 str r3, [r2, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800298c: e1ee b.n 8002d6c } } } else if (hhcd->hc[chnum].state == HC_NYET) 800298e: 78fa ldrb r2, [r7, #3] 8002990: 6879 ldr r1, [r7, #4] 8002992: 4613 mov r3, r2 8002994: 011b lsls r3, r3, #4 8002996: 1a9b subs r3, r3, r2 8002998: 009b lsls r3, r3, #2 800299a: 440b add r3, r1 800299c: 334d adds r3, #77 @ 0x4d 800299e: 781b ldrb r3, [r3, #0] 80029a0: 2b05 cmp r3, #5 80029a2: f040 80c8 bne.w 8002b36 { hhcd->hc[chnum].state = HC_HALTED; 80029a6: 78fa ldrb r2, [r7, #3] 80029a8: 6879 ldr r1, [r7, #4] 80029aa: 4613 mov r3, r2 80029ac: 011b lsls r3, r3, #4 80029ae: 1a9b subs r3, r3, r2 80029b0: 009b lsls r3, r3, #2 80029b2: 440b add r3, r1 80029b4: 334d adds r3, #77 @ 0x4d 80029b6: 2202 movs r2, #2 80029b8: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 80029ba: 78fa ldrb r2, [r7, #3] 80029bc: 6879 ldr r1, [r7, #4] 80029be: 4613 mov r3, r2 80029c0: 011b lsls r3, r3, #4 80029c2: 1a9b subs r3, r3, r2 80029c4: 009b lsls r3, r3, #2 80029c6: 440b add r3, r1 80029c8: 331b adds r3, #27 80029ca: 781b ldrb r3, [r3, #0] 80029cc: 2b01 cmp r3, #1 80029ce: f040 81ce bne.w 8002d6e { if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) 80029d2: 78fa ldrb r2, [r7, #3] 80029d4: 6879 ldr r1, [r7, #4] 80029d6: 4613 mov r3, r2 80029d8: 011b lsls r3, r3, #4 80029da: 1a9b subs r3, r3, r2 80029dc: 009b lsls r3, r3, #2 80029de: 440b add r3, r1 80029e0: 3326 adds r3, #38 @ 0x26 80029e2: 781b ldrb r3, [r3, #0] 80029e4: 2b03 cmp r3, #3 80029e6: d16b bne.n 8002ac0 { hhcd->hc[chnum].NyetErrCnt++; 80029e8: 78fa ldrb r2, [r7, #3] 80029ea: 6879 ldr r1, [r7, #4] 80029ec: 4613 mov r3, r2 80029ee: 011b lsls r3, r3, #4 80029f0: 1a9b subs r3, r3, r2 80029f2: 009b lsls r3, r3, #2 80029f4: 440b add r3, r1 80029f6: 3348 adds r3, #72 @ 0x48 80029f8: 681b ldr r3, [r3, #0] 80029fa: 1c59 adds r1, r3, #1 80029fc: 6878 ldr r0, [r7, #4] 80029fe: 4613 mov r3, r2 8002a00: 011b lsls r3, r3, #4 8002a02: 1a9b subs r3, r3, r2 8002a04: 009b lsls r3, r3, #2 8002a06: 4403 add r3, r0 8002a08: 3348 adds r3, #72 @ 0x48 8002a0a: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].NyetErrCnt > 2U) 8002a0c: 78fa ldrb r2, [r7, #3] 8002a0e: 6879 ldr r1, [r7, #4] 8002a10: 4613 mov r3, r2 8002a12: 011b lsls r3, r3, #4 8002a14: 1a9b subs r3, r3, r2 8002a16: 009b lsls r3, r3, #2 8002a18: 440b add r3, r1 8002a1a: 3348 adds r3, #72 @ 0x48 8002a1c: 681b ldr r3, [r3, #0] 8002a1e: 2b02 cmp r3, #2 8002a20: d943 bls.n 8002aaa { hhcd->hc[chnum].NyetErrCnt = 0U; 8002a22: 78fa ldrb r2, [r7, #3] 8002a24: 6879 ldr r1, [r7, #4] 8002a26: 4613 mov r3, r2 8002a28: 011b lsls r3, r3, #4 8002a2a: 1a9b subs r3, r3, r2 8002a2c: 009b lsls r3, r3, #2 8002a2e: 440b add r3, r1 8002a30: 3348 adds r3, #72 @ 0x48 8002a32: 2200 movs r2, #0 8002a34: 601a str r2, [r3, #0] hhcd->hc[chnum].do_csplit = 0U; 8002a36: 78fa ldrb r2, [r7, #3] 8002a38: 6879 ldr r1, [r7, #4] 8002a3a: 4613 mov r3, r2 8002a3c: 011b lsls r3, r3, #4 8002a3e: 1a9b subs r3, r3, r2 8002a40: 009b lsls r3, r3, #2 8002a42: 440b add r3, r1 8002a44: 331b adds r3, #27 8002a46: 2200 movs r2, #0 8002a48: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt < 3U) 8002a4a: 78fa ldrb r2, [r7, #3] 8002a4c: 6879 ldr r1, [r7, #4] 8002a4e: 4613 mov r3, r2 8002a50: 011b lsls r3, r3, #4 8002a52: 1a9b subs r3, r3, r2 8002a54: 009b lsls r3, r3, #2 8002a56: 440b add r3, r1 8002a58: 3344 adds r3, #68 @ 0x44 8002a5a: 681b ldr r3, [r3, #0] 8002a5c: 2b02 cmp r3, #2 8002a5e: d809 bhi.n 8002a74 { hhcd->hc[chnum].ep_ss_schedule = 1U; 8002a60: 78fa ldrb r2, [r7, #3] 8002a62: 6879 ldr r1, [r7, #4] 8002a64: 4613 mov r3, r2 8002a66: 011b lsls r3, r3, #4 8002a68: 1a9b subs r3, r3, r2 8002a6a: 009b lsls r3, r3, #2 8002a6c: 440b add r3, r1 8002a6e: 331c adds r3, #28 8002a70: 2201 movs r2, #1 8002a72: 701a strb r2, [r3, #0] } __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8002a74: 78fb ldrb r3, [r7, #3] 8002a76: 015a lsls r2, r3, #5 8002a78: 693b ldr r3, [r7, #16] 8002a7a: 4413 add r3, r2 8002a7c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002a80: 685b ldr r3, [r3, #4] 8002a82: 78fa ldrb r2, [r7, #3] 8002a84: 0151 lsls r1, r2, #5 8002a86: 693a ldr r2, [r7, #16] 8002a88: 440a add r2, r1 8002a8a: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002a8e: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002a92: 6053 str r3, [r2, #4] hhcd->hc[chnum].urb_state = URB_ERROR; 8002a94: 78fa ldrb r2, [r7, #3] 8002a96: 6879 ldr r1, [r7, #4] 8002a98: 4613 mov r3, r2 8002a9a: 011b lsls r3, r3, #4 8002a9c: 1a9b subs r3, r3, r2 8002a9e: 009b lsls r3, r3, #2 8002aa0: 440b add r3, r1 8002aa2: 334c adds r3, #76 @ 0x4c 8002aa4: 2204 movs r2, #4 8002aa6: 701a strb r2, [r3, #0] 8002aa8: e014 b.n 8002ad4 } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002aaa: 78fa ldrb r2, [r7, #3] 8002aac: 6879 ldr r1, [r7, #4] 8002aae: 4613 mov r3, r2 8002ab0: 011b lsls r3, r3, #4 8002ab2: 1a9b subs r3, r3, r2 8002ab4: 009b lsls r3, r3, #2 8002ab6: 440b add r3, r1 8002ab8: 334c adds r3, #76 @ 0x4c 8002aba: 2202 movs r2, #2 8002abc: 701a strb r2, [r3, #0] 8002abe: e009 b.n 8002ad4 } } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002ac0: 78fa ldrb r2, [r7, #3] 8002ac2: 6879 ldr r1, [r7, #4] 8002ac4: 4613 mov r3, r2 8002ac6: 011b lsls r3, r3, #4 8002ac8: 1a9b subs r3, r3, r2 8002aca: 009b lsls r3, r3, #2 8002acc: 440b add r3, r1 8002ace: 334c adds r3, #76 @ 0x4c 8002ad0: 2202 movs r2, #2 8002ad2: 701a strb r2, [r3, #0] } if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002ad4: 78fa ldrb r2, [r7, #3] 8002ad6: 6879 ldr r1, [r7, #4] 8002ad8: 4613 mov r3, r2 8002ada: 011b lsls r3, r3, #4 8002adc: 1a9b subs r3, r3, r2 8002ade: 009b lsls r3, r3, #2 8002ae0: 440b add r3, r1 8002ae2: 3326 adds r3, #38 @ 0x26 8002ae4: 781b ldrb r3, [r3, #0] 8002ae6: 2b00 cmp r3, #0 8002ae8: d00b beq.n 8002b02 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002aea: 78fa ldrb r2, [r7, #3] 8002aec: 6879 ldr r1, [r7, #4] 8002aee: 4613 mov r3, r2 8002af0: 011b lsls r3, r3, #4 8002af2: 1a9b subs r3, r3, r2 8002af4: 009b lsls r3, r3, #2 8002af6: 440b add r3, r1 8002af8: 3326 adds r3, #38 @ 0x26 8002afa: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002afc: 2b02 cmp r3, #2 8002afe: f040 8136 bne.w 8002d6e { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002b02: 78fb ldrb r3, [r7, #3] 8002b04: 015a lsls r2, r3, #5 8002b06: 693b ldr r3, [r7, #16] 8002b08: 4413 add r3, r2 8002b0a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002b0e: 681b ldr r3, [r3, #0] 8002b10: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002b12: 68fb ldr r3, [r7, #12] 8002b14: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002b18: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002b1a: 68fb ldr r3, [r7, #12] 8002b1c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002b20: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002b22: 78fb ldrb r3, [r7, #3] 8002b24: 015a lsls r2, r3, #5 8002b26: 693b ldr r3, [r7, #16] 8002b28: 4413 add r3, r2 8002b2a: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002b2e: 461a mov r2, r3 8002b30: 68fb ldr r3, [r7, #12] 8002b32: 6013 str r3, [r2, #0] 8002b34: e11b b.n 8002d6e } } } else if (hhcd->hc[chnum].state == HC_ACK) 8002b36: 78fa ldrb r2, [r7, #3] 8002b38: 6879 ldr r1, [r7, #4] 8002b3a: 4613 mov r3, r2 8002b3c: 011b lsls r3, r3, #4 8002b3e: 1a9b subs r3, r3, r2 8002b40: 009b lsls r3, r3, #2 8002b42: 440b add r3, r1 8002b44: 334d adds r3, #77 @ 0x4d 8002b46: 781b ldrb r3, [r3, #0] 8002b48: 2b03 cmp r3, #3 8002b4a: f040 8081 bne.w 8002c50 { hhcd->hc[chnum].state = HC_HALTED; 8002b4e: 78fa ldrb r2, [r7, #3] 8002b50: 6879 ldr r1, [r7, #4] 8002b52: 4613 mov r3, r2 8002b54: 011b lsls r3, r3, #4 8002b56: 1a9b subs r3, r3, r2 8002b58: 009b lsls r3, r3, #2 8002b5a: 440b add r3, r1 8002b5c: 334d adds r3, #77 @ 0x4d 8002b5e: 2202 movs r2, #2 8002b60: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 8002b62: 78fa ldrb r2, [r7, #3] 8002b64: 6879 ldr r1, [r7, #4] 8002b66: 4613 mov r3, r2 8002b68: 011b lsls r3, r3, #4 8002b6a: 1a9b subs r3, r3, r2 8002b6c: 009b lsls r3, r3, #2 8002b6e: 440b add r3, r1 8002b70: 331b adds r3, #27 8002b72: 781b ldrb r3, [r3, #0] 8002b74: 2b01 cmp r3, #1 8002b76: f040 80fa bne.w 8002d6e { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002b7a: 78fa ldrb r2, [r7, #3] 8002b7c: 6879 ldr r1, [r7, #4] 8002b7e: 4613 mov r3, r2 8002b80: 011b lsls r3, r3, #4 8002b82: 1a9b subs r3, r3, r2 8002b84: 009b lsls r3, r3, #2 8002b86: 440b add r3, r1 8002b88: 334c adds r3, #76 @ 0x4c 8002b8a: 2202 movs r2, #2 8002b8c: 701a strb r2, [r3, #0] /* Set Complete split and re-activate the channel */ USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; 8002b8e: 78fb ldrb r3, [r7, #3] 8002b90: 015a lsls r2, r3, #5 8002b92: 693b ldr r3, [r7, #16] 8002b94: 4413 add r3, r2 8002b96: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002b9a: 685b ldr r3, [r3, #4] 8002b9c: 78fa ldrb r2, [r7, #3] 8002b9e: 0151 lsls r1, r2, #5 8002ba0: 693a ldr r2, [r7, #16] 8002ba2: 440a add r2, r1 8002ba4: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002ba8: f443 3380 orr.w r3, r3, #65536 @ 0x10000 8002bac: 6053 str r3, [r2, #4] USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; 8002bae: 78fb ldrb r3, [r7, #3] 8002bb0: 015a lsls r2, r3, #5 8002bb2: 693b ldr r3, [r7, #16] 8002bb4: 4413 add r3, r2 8002bb6: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002bba: 68db ldr r3, [r3, #12] 8002bbc: 78fa ldrb r2, [r7, #3] 8002bbe: 0151 lsls r1, r2, #5 8002bc0: 693a ldr r2, [r7, #16] 8002bc2: 440a add r2, r1 8002bc4: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002bc8: f043 0340 orr.w r3, r3, #64 @ 0x40 8002bcc: 60d3 str r3, [r2, #12] USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; 8002bce: 78fb ldrb r3, [r7, #3] 8002bd0: 015a lsls r2, r3, #5 8002bd2: 693b ldr r3, [r7, #16] 8002bd4: 4413 add r3, r2 8002bd6: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002bda: 68db ldr r3, [r3, #12] 8002bdc: 78fa ldrb r2, [r7, #3] 8002bde: 0151 lsls r1, r2, #5 8002be0: 693a ldr r2, [r7, #16] 8002be2: 440a add r2, r1 8002be4: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002be8: f023 0320 bic.w r3, r3, #32 8002bec: 60d3 str r3, [r2, #12] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002bee: 78fa ldrb r2, [r7, #3] 8002bf0: 6879 ldr r1, [r7, #4] 8002bf2: 4613 mov r3, r2 8002bf4: 011b lsls r3, r3, #4 8002bf6: 1a9b subs r3, r3, r2 8002bf8: 009b lsls r3, r3, #2 8002bfa: 440b add r3, r1 8002bfc: 3326 adds r3, #38 @ 0x26 8002bfe: 781b ldrb r3, [r3, #0] 8002c00: 2b00 cmp r3, #0 8002c02: d00b beq.n 8002c1c (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002c04: 78fa ldrb r2, [r7, #3] 8002c06: 6879 ldr r1, [r7, #4] 8002c08: 4613 mov r3, r2 8002c0a: 011b lsls r3, r3, #4 8002c0c: 1a9b subs r3, r3, r2 8002c0e: 009b lsls r3, r3, #2 8002c10: 440b add r3, r1 8002c12: 3326 adds r3, #38 @ 0x26 8002c14: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002c16: 2b02 cmp r3, #2 8002c18: f040 80a9 bne.w 8002d6e { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002c1c: 78fb ldrb r3, [r7, #3] 8002c1e: 015a lsls r2, r3, #5 8002c20: 693b ldr r3, [r7, #16] 8002c22: 4413 add r3, r2 8002c24: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c28: 681b ldr r3, [r3, #0] 8002c2a: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002c2c: 68fb ldr r3, [r7, #12] 8002c2e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002c32: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002c34: 68fb ldr r3, [r7, #12] 8002c36: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002c3a: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002c3c: 78fb ldrb r3, [r7, #3] 8002c3e: 015a lsls r2, r3, #5 8002c40: 693b ldr r3, [r7, #16] 8002c42: 4413 add r3, r2 8002c44: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002c48: 461a mov r2, r3 8002c4a: 68fb ldr r3, [r7, #12] 8002c4c: 6013 str r3, [r2, #0] 8002c4e: e08e b.n 8002d6e } } } else if (hhcd->hc[chnum].state == HC_NAK) 8002c50: 78fa ldrb r2, [r7, #3] 8002c52: 6879 ldr r1, [r7, #4] 8002c54: 4613 mov r3, r2 8002c56: 011b lsls r3, r3, #4 8002c58: 1a9b subs r3, r3, r2 8002c5a: 009b lsls r3, r3, #2 8002c5c: 440b add r3, r1 8002c5e: 334d adds r3, #77 @ 0x4d 8002c60: 781b ldrb r3, [r3, #0] 8002c62: 2b04 cmp r3, #4 8002c64: d143 bne.n 8002cee { hhcd->hc[chnum].state = HC_HALTED; 8002c66: 78fa ldrb r2, [r7, #3] 8002c68: 6879 ldr r1, [r7, #4] 8002c6a: 4613 mov r3, r2 8002c6c: 011b lsls r3, r3, #4 8002c6e: 1a9b subs r3, r3, r2 8002c70: 009b lsls r3, r3, #2 8002c72: 440b add r3, r1 8002c74: 334d adds r3, #77 @ 0x4d 8002c76: 2202 movs r2, #2 8002c78: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 8002c7a: 78fa ldrb r2, [r7, #3] 8002c7c: 6879 ldr r1, [r7, #4] 8002c7e: 4613 mov r3, r2 8002c80: 011b lsls r3, r3, #4 8002c82: 1a9b subs r3, r3, r2 8002c84: 009b lsls r3, r3, #2 8002c86: 440b add r3, r1 8002c88: 334c adds r3, #76 @ 0x4c 8002c8a: 2202 movs r2, #2 8002c8c: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002c8e: 78fa ldrb r2, [r7, #3] 8002c90: 6879 ldr r1, [r7, #4] 8002c92: 4613 mov r3, r2 8002c94: 011b lsls r3, r3, #4 8002c96: 1a9b subs r3, r3, r2 8002c98: 009b lsls r3, r3, #2 8002c9a: 440b add r3, r1 8002c9c: 3326 adds r3, #38 @ 0x26 8002c9e: 781b ldrb r3, [r3, #0] 8002ca0: 2b00 cmp r3, #0 8002ca2: d00a beq.n 8002cba (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002ca4: 78fa ldrb r2, [r7, #3] 8002ca6: 6879 ldr r1, [r7, #4] 8002ca8: 4613 mov r3, r2 8002caa: 011b lsls r3, r3, #4 8002cac: 1a9b subs r3, r3, r2 8002cae: 009b lsls r3, r3, #2 8002cb0: 440b add r3, r1 8002cb2: 3326 adds r3, #38 @ 0x26 8002cb4: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002cb6: 2b02 cmp r3, #2 8002cb8: d159 bne.n 8002d6e { /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8002cba: 78fb ldrb r3, [r7, #3] 8002cbc: 015a lsls r2, r3, #5 8002cbe: 693b ldr r3, [r7, #16] 8002cc0: 4413 add r3, r2 8002cc2: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002cc6: 681b ldr r3, [r3, #0] 8002cc8: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8002cca: 68fb ldr r3, [r7, #12] 8002ccc: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8002cd0: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 8002cd2: 68fb ldr r3, [r7, #12] 8002cd4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8002cd8: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8002cda: 78fb ldrb r3, [r7, #3] 8002cdc: 015a lsls r2, r3, #5 8002cde: 693b ldr r3, [r7, #16] 8002ce0: 4413 add r3, r2 8002ce2: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002ce6: 461a mov r2, r3 8002ce8: 68fb ldr r3, [r7, #12] 8002cea: 6013 str r3, [r2, #0] 8002cec: e03f b.n 8002d6e } } else if (hhcd->hc[chnum].state == HC_BBLERR) 8002cee: 78fa ldrb r2, [r7, #3] 8002cf0: 6879 ldr r1, [r7, #4] 8002cf2: 4613 mov r3, r2 8002cf4: 011b lsls r3, r3, #4 8002cf6: 1a9b subs r3, r3, r2 8002cf8: 009b lsls r3, r3, #2 8002cfa: 440b add r3, r1 8002cfc: 334d adds r3, #77 @ 0x4d 8002cfe: 781b ldrb r3, [r3, #0] 8002d00: 2b08 cmp r3, #8 8002d02: d126 bne.n 8002d52 { hhcd->hc[chnum].state = HC_HALTED; 8002d04: 78fa ldrb r2, [r7, #3] 8002d06: 6879 ldr r1, [r7, #4] 8002d08: 4613 mov r3, r2 8002d0a: 011b lsls r3, r3, #4 8002d0c: 1a9b subs r3, r3, r2 8002d0e: 009b lsls r3, r3, #2 8002d10: 440b add r3, r1 8002d12: 334d adds r3, #77 @ 0x4d 8002d14: 2202 movs r2, #2 8002d16: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 8002d18: 78fa ldrb r2, [r7, #3] 8002d1a: 6879 ldr r1, [r7, #4] 8002d1c: 4613 mov r3, r2 8002d1e: 011b lsls r3, r3, #4 8002d20: 1a9b subs r3, r3, r2 8002d22: 009b lsls r3, r3, #2 8002d24: 440b add r3, r1 8002d26: 3344 adds r3, #68 @ 0x44 8002d28: 681b ldr r3, [r3, #0] 8002d2a: 1c59 adds r1, r3, #1 8002d2c: 6878 ldr r0, [r7, #4] 8002d2e: 4613 mov r3, r2 8002d30: 011b lsls r3, r3, #4 8002d32: 1a9b subs r3, r3, r2 8002d34: 009b lsls r3, r3, #2 8002d36: 4403 add r3, r0 8002d38: 3344 adds r3, #68 @ 0x44 8002d3a: 6019 str r1, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 8002d3c: 78fa ldrb r2, [r7, #3] 8002d3e: 6879 ldr r1, [r7, #4] 8002d40: 4613 mov r3, r2 8002d42: 011b lsls r3, r3, #4 8002d44: 1a9b subs r3, r3, r2 8002d46: 009b lsls r3, r3, #2 8002d48: 440b add r3, r1 8002d4a: 334c adds r3, #76 @ 0x4c 8002d4c: 2204 movs r2, #4 8002d4e: 701a strb r2, [r3, #0] 8002d50: e00d b.n 8002d6e } else { if (hhcd->hc[chnum].state == HC_HALTED) 8002d52: 78fa ldrb r2, [r7, #3] 8002d54: 6879 ldr r1, [r7, #4] 8002d56: 4613 mov r3, r2 8002d58: 011b lsls r3, r3, #4 8002d5a: 1a9b subs r3, r3, r2 8002d5c: 009b lsls r3, r3, #2 8002d5e: 440b add r3, r1 8002d60: 334d adds r3, #77 @ 0x4d 8002d62: 781b ldrb r3, [r3, #0] 8002d64: 2b02 cmp r3, #2 8002d66: f000 8100 beq.w 8002f6a 8002d6a: e000 b.n 8002d6e if (hhcd->hc[chnum].ErrCnt > 2U) 8002d6c: bf00 nop } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 8002d6e: 78fa ldrb r2, [r7, #3] 8002d70: 6879 ldr r1, [r7, #4] 8002d72: 4613 mov r3, r2 8002d74: 011b lsls r3, r3, #4 8002d76: 1a9b subs r3, r3, r2 8002d78: 009b lsls r3, r3, #2 8002d7a: 440b add r3, r1 8002d7c: 334c adds r3, #76 @ 0x4c 8002d7e: 781a ldrb r2, [r3, #0] 8002d80: 78fb ldrb r3, [r7, #3] 8002d82: 4619 mov r1, r3 8002d84: 6878 ldr r0, [r7, #4] 8002d86: f005 f815 bl 8007db4 8002d8a: e0ef b.n 8002f6c #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 8002d8c: 687b ldr r3, [r7, #4] 8002d8e: 681b ldr r3, [r3, #0] 8002d90: 78fa ldrb r2, [r7, #3] 8002d92: 4611 mov r1, r2 8002d94: 4618 mov r0, r3 8002d96: f003 fbfa bl 800658e 8002d9a: 4603 mov r3, r0 8002d9c: f003 0340 and.w r3, r3, #64 @ 0x40 8002da0: 2b40 cmp r3, #64 @ 0x40 8002da2: d12f bne.n 8002e04 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 8002da4: 78fb ldrb r3, [r7, #3] 8002da6: 015a lsls r2, r3, #5 8002da8: 693b ldr r3, [r7, #16] 8002daa: 4413 add r3, r2 8002dac: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002db0: 461a mov r2, r3 8002db2: 2340 movs r3, #64 @ 0x40 8002db4: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_NYET; 8002db6: 78fa ldrb r2, [r7, #3] 8002db8: 6879 ldr r1, [r7, #4] 8002dba: 4613 mov r3, r2 8002dbc: 011b lsls r3, r3, #4 8002dbe: 1a9b subs r3, r3, r2 8002dc0: 009b lsls r3, r3, #2 8002dc2: 440b add r3, r1 8002dc4: 334d adds r3, #77 @ 0x4d 8002dc6: 2205 movs r2, #5 8002dc8: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 0U) 8002dca: 78fa ldrb r2, [r7, #3] 8002dcc: 6879 ldr r1, [r7, #4] 8002dce: 4613 mov r3, r2 8002dd0: 011b lsls r3, r3, #4 8002dd2: 1a9b subs r3, r3, r2 8002dd4: 009b lsls r3, r3, #2 8002dd6: 440b add r3, r1 8002dd8: 331a adds r3, #26 8002dda: 781b ldrb r3, [r3, #0] 8002ddc: 2b00 cmp r3, #0 8002dde: d109 bne.n 8002df4 { hhcd->hc[chnum].ErrCnt = 0U; 8002de0: 78fa ldrb r2, [r7, #3] 8002de2: 6879 ldr r1, [r7, #4] 8002de4: 4613 mov r3, r2 8002de6: 011b lsls r3, r3, #4 8002de8: 1a9b subs r3, r3, r2 8002dea: 009b lsls r3, r3, #2 8002dec: 440b add r3, r1 8002dee: 3344 adds r3, #68 @ 0x44 8002df0: 2200 movs r2, #0 8002df2: 601a str r2, [r3, #0] } (void)USB_HC_Halt(hhcd->Instance, chnum); 8002df4: 687b ldr r3, [r7, #4] 8002df6: 681b ldr r3, [r3, #0] 8002df8: 78fa ldrb r2, [r7, #3] 8002dfa: 4611 mov r1, r2 8002dfc: 4618 mov r0, r3 8002dfe: f003 fc43 bl 8006688 8002e02: e0b3 b.n 8002f6c } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) 8002e04: 687b ldr r3, [r7, #4] 8002e06: 681b ldr r3, [r3, #0] 8002e08: 78fa ldrb r2, [r7, #3] 8002e0a: 4611 mov r1, r2 8002e0c: 4618 mov r0, r3 8002e0e: f003 fbbe bl 800658e 8002e12: 4603 mov r3, r0 8002e14: f003 0310 and.w r3, r3, #16 8002e18: 2b10 cmp r3, #16 8002e1a: f040 80a7 bne.w 8002f6c { if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) 8002e1e: 78fa ldrb r2, [r7, #3] 8002e20: 6879 ldr r1, [r7, #4] 8002e22: 4613 mov r3, r2 8002e24: 011b lsls r3, r3, #4 8002e26: 1a9b subs r3, r3, r2 8002e28: 009b lsls r3, r3, #2 8002e2a: 440b add r3, r1 8002e2c: 3326 adds r3, #38 @ 0x26 8002e2e: 781b ldrb r3, [r3, #0] 8002e30: 2b03 cmp r3, #3 8002e32: d11b bne.n 8002e6c { hhcd->hc[chnum].ErrCnt = 0U; 8002e34: 78fa ldrb r2, [r7, #3] 8002e36: 6879 ldr r1, [r7, #4] 8002e38: 4613 mov r3, r2 8002e3a: 011b lsls r3, r3, #4 8002e3c: 1a9b subs r3, r3, r2 8002e3e: 009b lsls r3, r3, #2 8002e40: 440b add r3, r1 8002e42: 3344 adds r3, #68 @ 0x44 8002e44: 2200 movs r2, #0 8002e46: 601a str r2, [r3, #0] hhcd->hc[chnum].state = HC_NAK; 8002e48: 78fa ldrb r2, [r7, #3] 8002e4a: 6879 ldr r1, [r7, #4] 8002e4c: 4613 mov r3, r2 8002e4e: 011b lsls r3, r3, #4 8002e50: 1a9b subs r3, r3, r2 8002e52: 009b lsls r3, r3, #2 8002e54: 440b add r3, r1 8002e56: 334d adds r3, #77 @ 0x4d 8002e58: 2204 movs r2, #4 8002e5a: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002e5c: 687b ldr r3, [r7, #4] 8002e5e: 681b ldr r3, [r3, #0] 8002e60: 78fa ldrb r2, [r7, #3] 8002e62: 4611 mov r1, r2 8002e64: 4618 mov r0, r3 8002e66: f003 fc0f bl 8006688 8002e6a: e03f b.n 8002eec } else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002e6c: 78fa ldrb r2, [r7, #3] 8002e6e: 6879 ldr r1, [r7, #4] 8002e70: 4613 mov r3, r2 8002e72: 011b lsls r3, r3, #4 8002e74: 1a9b subs r3, r3, r2 8002e76: 009b lsls r3, r3, #2 8002e78: 440b add r3, r1 8002e7a: 3326 adds r3, #38 @ 0x26 8002e7c: 781b ldrb r3, [r3, #0] 8002e7e: 2b00 cmp r3, #0 8002e80: d00a beq.n 8002e98 (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) 8002e82: 78fa ldrb r2, [r7, #3] 8002e84: 6879 ldr r1, [r7, #4] 8002e86: 4613 mov r3, r2 8002e88: 011b lsls r3, r3, #4 8002e8a: 1a9b subs r3, r3, r2 8002e8c: 009b lsls r3, r3, #2 8002e8e: 440b add r3, r1 8002e90: 3326 adds r3, #38 @ 0x26 8002e92: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || 8002e94: 2b02 cmp r3, #2 8002e96: d129 bne.n 8002eec { hhcd->hc[chnum].ErrCnt = 0U; 8002e98: 78fa ldrb r2, [r7, #3] 8002e9a: 6879 ldr r1, [r7, #4] 8002e9c: 4613 mov r3, r2 8002e9e: 011b lsls r3, r3, #4 8002ea0: 1a9b subs r3, r3, r2 8002ea2: 009b lsls r3, r3, #2 8002ea4: 440b add r3, r1 8002ea6: 3344 adds r3, #68 @ 0x44 8002ea8: 2200 movs r2, #0 8002eaa: 601a str r2, [r3, #0] if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) 8002eac: 687b ldr r3, [r7, #4] 8002eae: 799b ldrb r3, [r3, #6] 8002eb0: 2b00 cmp r3, #0 8002eb2: d00a beq.n 8002eca 8002eb4: 78fa ldrb r2, [r7, #3] 8002eb6: 6879 ldr r1, [r7, #4] 8002eb8: 4613 mov r3, r2 8002eba: 011b lsls r3, r3, #4 8002ebc: 1a9b subs r3, r3, r2 8002ebe: 009b lsls r3, r3, #2 8002ec0: 440b add r3, r1 8002ec2: 331b adds r3, #27 8002ec4: 781b ldrb r3, [r3, #0] 8002ec6: 2b01 cmp r3, #1 8002ec8: d110 bne.n 8002eec { hhcd->hc[chnum].state = HC_NAK; 8002eca: 78fa ldrb r2, [r7, #3] 8002ecc: 6879 ldr r1, [r7, #4] 8002ece: 4613 mov r3, r2 8002ed0: 011b lsls r3, r3, #4 8002ed2: 1a9b subs r3, r3, r2 8002ed4: 009b lsls r3, r3, #2 8002ed6: 440b add r3, r1 8002ed8: 334d adds r3, #77 @ 0x4d 8002eda: 2204 movs r2, #4 8002edc: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002ede: 687b ldr r3, [r7, #4] 8002ee0: 681b ldr r3, [r3, #0] 8002ee2: 78fa ldrb r2, [r7, #3] 8002ee4: 4611 mov r1, r2 8002ee6: 4618 mov r0, r3 8002ee8: f003 fbce bl 8006688 else { /* ... */ } if (hhcd->hc[chnum].do_csplit == 1U) 8002eec: 78fa ldrb r2, [r7, #3] 8002eee: 6879 ldr r1, [r7, #4] 8002ef0: 4613 mov r3, r2 8002ef2: 011b lsls r3, r3, #4 8002ef4: 1a9b subs r3, r3, r2 8002ef6: 009b lsls r3, r3, #2 8002ef8: 440b add r3, r1 8002efa: 331b adds r3, #27 8002efc: 781b ldrb r3, [r3, #0] 8002efe: 2b01 cmp r3, #1 8002f00: d129 bne.n 8002f56 { hhcd->hc[chnum].do_csplit = 0U; 8002f02: 78fa ldrb r2, [r7, #3] 8002f04: 6879 ldr r1, [r7, #4] 8002f06: 4613 mov r3, r2 8002f08: 011b lsls r3, r3, #4 8002f0a: 1a9b subs r3, r3, r2 8002f0c: 009b lsls r3, r3, #2 8002f0e: 440b add r3, r1 8002f10: 331b adds r3, #27 8002f12: 2200 movs r2, #0 8002f14: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8002f16: 78fb ldrb r3, [r7, #3] 8002f18: 015a lsls r2, r3, #5 8002f1a: 693b ldr r3, [r7, #16] 8002f1c: 4413 add r3, r2 8002f1e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002f22: 685b ldr r3, [r3, #4] 8002f24: 78fa ldrb r2, [r7, #3] 8002f26: 0151 lsls r1, r2, #5 8002f28: 693a ldr r2, [r7, #16] 8002f2a: 440a add r2, r1 8002f2c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002f30: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8002f34: 6053 str r3, [r2, #4] __HAL_HCD_UNMASK_ACK_HC_INT(chnum); 8002f36: 78fb ldrb r3, [r7, #3] 8002f38: 015a lsls r2, r3, #5 8002f3a: 693b ldr r3, [r7, #16] 8002f3c: 4413 add r3, r2 8002f3e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002f42: 68db ldr r3, [r3, #12] 8002f44: 78fa ldrb r2, [r7, #3] 8002f46: 0151 lsls r1, r2, #5 8002f48: 693a ldr r2, [r7, #16] 8002f4a: 440a add r2, r1 8002f4c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8002f50: f043 0320 orr.w r3, r3, #32 8002f54: 60d3 str r3, [r2, #12] } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 8002f56: 78fb ldrb r3, [r7, #3] 8002f58: 015a lsls r2, r3, #5 8002f5a: 693b ldr r3, [r7, #16] 8002f5c: 4413 add r3, r2 8002f5e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002f62: 461a mov r2, r3 8002f64: 2310 movs r3, #16 8002f66: 6093 str r3, [r2, #8] 8002f68: e000 b.n 8002f6c return; 8002f6a: bf00 nop } else { /* ... */ } } 8002f6c: 3718 adds r7, #24 8002f6e: 46bd mov sp, r7 8002f70: bd80 pop {r7, pc} 08002f72 : * @param chnum Channel number. * This parameter can be a value from 1 to 15 * @retval none */ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { 8002f72: b580 push {r7, lr} 8002f74: b086 sub sp, #24 8002f76: af00 add r7, sp, #0 8002f78: 6078 str r0, [r7, #4] 8002f7a: 460b mov r3, r1 8002f7c: 70fb strb r3, [r7, #3] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8002f7e: 687b ldr r3, [r7, #4] 8002f80: 681b ldr r3, [r3, #0] 8002f82: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8002f84: 697b ldr r3, [r7, #20] 8002f86: 613b str r3, [r7, #16] uint32_t tmpreg; uint32_t num_packets; if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) 8002f88: 687b ldr r3, [r7, #4] 8002f8a: 681b ldr r3, [r3, #0] 8002f8c: 78fa ldrb r2, [r7, #3] 8002f8e: 4611 mov r1, r2 8002f90: 4618 mov r0, r3 8002f92: f003 fafc bl 800658e 8002f96: 4603 mov r3, r0 8002f98: f003 0304 and.w r3, r3, #4 8002f9c: 2b04 cmp r3, #4 8002f9e: d11b bne.n 8002fd8 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); 8002fa0: 78fb ldrb r3, [r7, #3] 8002fa2: 015a lsls r2, r3, #5 8002fa4: 693b ldr r3, [r7, #16] 8002fa6: 4413 add r3, r2 8002fa8: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002fac: 461a mov r2, r3 8002fae: 2304 movs r3, #4 8002fb0: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XACTERR; 8002fb2: 78fa ldrb r2, [r7, #3] 8002fb4: 6879 ldr r1, [r7, #4] 8002fb6: 4613 mov r3, r2 8002fb8: 011b lsls r3, r3, #4 8002fba: 1a9b subs r3, r3, r2 8002fbc: 009b lsls r3, r3, #2 8002fbe: 440b add r3, r1 8002fc0: 334d adds r3, #77 @ 0x4d 8002fc2: 2207 movs r2, #7 8002fc4: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8002fc6: 687b ldr r3, [r7, #4] 8002fc8: 681b ldr r3, [r3, #0] 8002fca: 78fa ldrb r2, [r7, #3] 8002fcc: 4611 mov r1, r2 8002fce: 4618 mov r0, r3 8002fd0: f003 fb5a bl 8006688 8002fd4: f000 bc89 b.w 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) 8002fd8: 687b ldr r3, [r7, #4] 8002fda: 681b ldr r3, [r3, #0] 8002fdc: 78fa ldrb r2, [r7, #3] 8002fde: 4611 mov r1, r2 8002fe0: 4618 mov r0, r3 8002fe2: f003 fad4 bl 800658e 8002fe6: 4603 mov r3, r0 8002fe8: f003 0320 and.w r3, r3, #32 8002fec: 2b20 cmp r3, #32 8002fee: f040 8082 bne.w 80030f6 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); 8002ff2: 78fb ldrb r3, [r7, #3] 8002ff4: 015a lsls r2, r3, #5 8002ff6: 693b ldr r3, [r7, #16] 8002ff8: 4413 add r3, r2 8002ffa: f503 63a0 add.w r3, r3, #1280 @ 0x500 8002ffe: 461a mov r2, r3 8003000: 2320 movs r3, #32 8003002: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].do_ping == 1U) 8003004: 78fa ldrb r2, [r7, #3] 8003006: 6879 ldr r1, [r7, #4] 8003008: 4613 mov r3, r2 800300a: 011b lsls r3, r3, #4 800300c: 1a9b subs r3, r3, r2 800300e: 009b lsls r3, r3, #2 8003010: 440b add r3, r1 8003012: 3319 adds r3, #25 8003014: 781b ldrb r3, [r3, #0] 8003016: 2b01 cmp r3, #1 8003018: d124 bne.n 8003064 { hhcd->hc[chnum].do_ping = 0U; 800301a: 78fa ldrb r2, [r7, #3] 800301c: 6879 ldr r1, [r7, #4] 800301e: 4613 mov r3, r2 8003020: 011b lsls r3, r3, #4 8003022: 1a9b subs r3, r3, r2 8003024: 009b lsls r3, r3, #2 8003026: 440b add r3, r1 8003028: 3319 adds r3, #25 800302a: 2200 movs r2, #0 800302c: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 800302e: 78fa ldrb r2, [r7, #3] 8003030: 6879 ldr r1, [r7, #4] 8003032: 4613 mov r3, r2 8003034: 011b lsls r3, r3, #4 8003036: 1a9b subs r3, r3, r2 8003038: 009b lsls r3, r3, #2 800303a: 440b add r3, r1 800303c: 334c adds r3, #76 @ 0x4c 800303e: 2202 movs r2, #2 8003040: 701a strb r2, [r3, #0] hhcd->hc[chnum].state = HC_ACK; 8003042: 78fa ldrb r2, [r7, #3] 8003044: 6879 ldr r1, [r7, #4] 8003046: 4613 mov r3, r2 8003048: 011b lsls r3, r3, #4 800304a: 1a9b subs r3, r3, r2 800304c: 009b lsls r3, r3, #2 800304e: 440b add r3, r1 8003050: 334d adds r3, #77 @ 0x4d 8003052: 2203 movs r2, #3 8003054: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003056: 687b ldr r3, [r7, #4] 8003058: 681b ldr r3, [r3, #0] 800305a: 78fa ldrb r2, [r7, #3] 800305c: 4611 mov r1, r2 800305e: 4618 mov r0, r3 8003060: f003 fb12 bl 8006688 } if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) 8003064: 78fa ldrb r2, [r7, #3] 8003066: 6879 ldr r1, [r7, #4] 8003068: 4613 mov r3, r2 800306a: 011b lsls r3, r3, #4 800306c: 1a9b subs r3, r3, r2 800306e: 009b lsls r3, r3, #2 8003070: 440b add r3, r1 8003072: 331a adds r3, #26 8003074: 781b ldrb r3, [r3, #0] 8003076: 2b01 cmp r3, #1 8003078: f040 8437 bne.w 80038ea 800307c: 78fa ldrb r2, [r7, #3] 800307e: 6879 ldr r1, [r7, #4] 8003080: 4613 mov r3, r2 8003082: 011b lsls r3, r3, #4 8003084: 1a9b subs r3, r3, r2 8003086: 009b lsls r3, r3, #2 8003088: 440b add r3, r1 800308a: 331b adds r3, #27 800308c: 781b ldrb r3, [r3, #0] 800308e: 2b00 cmp r3, #0 8003090: f040 842b bne.w 80038ea { if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) 8003094: 78fa ldrb r2, [r7, #3] 8003096: 6879 ldr r1, [r7, #4] 8003098: 4613 mov r3, r2 800309a: 011b lsls r3, r3, #4 800309c: 1a9b subs r3, r3, r2 800309e: 009b lsls r3, r3, #2 80030a0: 440b add r3, r1 80030a2: 3326 adds r3, #38 @ 0x26 80030a4: 781b ldrb r3, [r3, #0] 80030a6: 2b01 cmp r3, #1 80030a8: d009 beq.n 80030be { hhcd->hc[chnum].do_csplit = 1U; 80030aa: 78fa ldrb r2, [r7, #3] 80030ac: 6879 ldr r1, [r7, #4] 80030ae: 4613 mov r3, r2 80030b0: 011b lsls r3, r3, #4 80030b2: 1a9b subs r3, r3, r2 80030b4: 009b lsls r3, r3, #2 80030b6: 440b add r3, r1 80030b8: 331b adds r3, #27 80030ba: 2201 movs r2, #1 80030bc: 701a strb r2, [r3, #0] } hhcd->hc[chnum].state = HC_ACK; 80030be: 78fa ldrb r2, [r7, #3] 80030c0: 6879 ldr r1, [r7, #4] 80030c2: 4613 mov r3, r2 80030c4: 011b lsls r3, r3, #4 80030c6: 1a9b subs r3, r3, r2 80030c8: 009b lsls r3, r3, #2 80030ca: 440b add r3, r1 80030cc: 334d adds r3, #77 @ 0x4d 80030ce: 2203 movs r2, #3 80030d0: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80030d2: 687b ldr r3, [r7, #4] 80030d4: 681b ldr r3, [r3, #0] 80030d6: 78fa ldrb r2, [r7, #3] 80030d8: 4611 mov r1, r2 80030da: 4618 mov r0, r3 80030dc: f003 fad4 bl 8006688 /* reset error_count */ hhcd->hc[chnum].ErrCnt = 0U; 80030e0: 78fa ldrb r2, [r7, #3] 80030e2: 6879 ldr r1, [r7, #4] 80030e4: 4613 mov r3, r2 80030e6: 011b lsls r3, r3, #4 80030e8: 1a9b subs r3, r3, r2 80030ea: 009b lsls r3, r3, #2 80030ec: 440b add r3, r1 80030ee: 3344 adds r3, #68 @ 0x44 80030f0: 2200 movs r2, #0 80030f2: 601a str r2, [r3, #0] 80030f4: e3f9 b.n 80038ea } } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) 80030f6: 687b ldr r3, [r7, #4] 80030f8: 681b ldr r3, [r3, #0] 80030fa: 78fa ldrb r2, [r7, #3] 80030fc: 4611 mov r1, r2 80030fe: 4618 mov r0, r3 8003100: f003 fa45 bl 800658e 8003104: 4603 mov r3, r0 8003106: f403 7300 and.w r3, r3, #512 @ 0x200 800310a: f5b3 7f00 cmp.w r3, #512 @ 0x200 800310e: d111 bne.n 8003134 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); 8003110: 78fb ldrb r3, [r7, #3] 8003112: 015a lsls r2, r3, #5 8003114: 693b ldr r3, [r7, #16] 8003116: 4413 add r3, r2 8003118: f503 63a0 add.w r3, r3, #1280 @ 0x500 800311c: 461a mov r2, r3 800311e: f44f 7300 mov.w r3, #512 @ 0x200 8003122: 6093 str r3, [r2, #8] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003124: 687b ldr r3, [r7, #4] 8003126: 681b ldr r3, [r3, #0] 8003128: 78fa ldrb r2, [r7, #3] 800312a: 4611 mov r1, r2 800312c: 4618 mov r0, r3 800312e: f003 faab bl 8006688 8003132: e3da b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) 8003134: 687b ldr r3, [r7, #4] 8003136: 681b ldr r3, [r3, #0] 8003138: 78fa ldrb r2, [r7, #3] 800313a: 4611 mov r1, r2 800313c: 4618 mov r0, r3 800313e: f003 fa26 bl 800658e 8003142: 4603 mov r3, r0 8003144: f003 0301 and.w r3, r3, #1 8003148: 2b01 cmp r3, #1 800314a: d168 bne.n 800321e { hhcd->hc[chnum].ErrCnt = 0U; 800314c: 78fa ldrb r2, [r7, #3] 800314e: 6879 ldr r1, [r7, #4] 8003150: 4613 mov r3, r2 8003152: 011b lsls r3, r3, #4 8003154: 1a9b subs r3, r3, r2 8003156: 009b lsls r3, r3, #2 8003158: 440b add r3, r1 800315a: 3344 adds r3, #68 @ 0x44 800315c: 2200 movs r2, #0 800315e: 601a str r2, [r3, #0] /* transaction completed with NYET state, update do ping state */ if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 8003160: 687b ldr r3, [r7, #4] 8003162: 681b ldr r3, [r3, #0] 8003164: 78fa ldrb r2, [r7, #3] 8003166: 4611 mov r1, r2 8003168: 4618 mov r0, r3 800316a: f003 fa10 bl 800658e 800316e: 4603 mov r3, r0 8003170: f003 0340 and.w r3, r3, #64 @ 0x40 8003174: 2b40 cmp r3, #64 @ 0x40 8003176: d112 bne.n 800319e { hhcd->hc[chnum].do_ping = 1U; 8003178: 78fa ldrb r2, [r7, #3] 800317a: 6879 ldr r1, [r7, #4] 800317c: 4613 mov r3, r2 800317e: 011b lsls r3, r3, #4 8003180: 1a9b subs r3, r3, r2 8003182: 009b lsls r3, r3, #2 8003184: 440b add r3, r1 8003186: 3319 adds r3, #25 8003188: 2201 movs r2, #1 800318a: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 800318c: 78fb ldrb r3, [r7, #3] 800318e: 015a lsls r2, r3, #5 8003190: 693b ldr r3, [r7, #16] 8003192: 4413 add r3, r2 8003194: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003198: 461a mov r2, r3 800319a: 2340 movs r3, #64 @ 0x40 800319c: 6093 str r3, [r2, #8] } if (hhcd->hc[chnum].do_csplit != 0U) 800319e: 78fa ldrb r2, [r7, #3] 80031a0: 6879 ldr r1, [r7, #4] 80031a2: 4613 mov r3, r2 80031a4: 011b lsls r3, r3, #4 80031a6: 1a9b subs r3, r3, r2 80031a8: 009b lsls r3, r3, #2 80031aa: 440b add r3, r1 80031ac: 331b adds r3, #27 80031ae: 781b ldrb r3, [r3, #0] 80031b0: 2b00 cmp r3, #0 80031b2: d019 beq.n 80031e8 { hhcd->hc[chnum].do_csplit = 0U; 80031b4: 78fa ldrb r2, [r7, #3] 80031b6: 6879 ldr r1, [r7, #4] 80031b8: 4613 mov r3, r2 80031ba: 011b lsls r3, r3, #4 80031bc: 1a9b subs r3, r3, r2 80031be: 009b lsls r3, r3, #2 80031c0: 440b add r3, r1 80031c2: 331b adds r3, #27 80031c4: 2200 movs r2, #0 80031c6: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 80031c8: 78fb ldrb r3, [r7, #3] 80031ca: 015a lsls r2, r3, #5 80031cc: 693b ldr r3, [r7, #16] 80031ce: 4413 add r3, r2 80031d0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80031d4: 685b ldr r3, [r3, #4] 80031d6: 78fa ldrb r2, [r7, #3] 80031d8: 0151 lsls r1, r2, #5 80031da: 693a ldr r2, [r7, #16] 80031dc: 440a add r2, r1 80031de: f502 62a0 add.w r2, r2, #1280 @ 0x500 80031e2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80031e6: 6053 str r3, [r2, #4] } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); 80031e8: 78fb ldrb r3, [r7, #3] 80031ea: 015a lsls r2, r3, #5 80031ec: 693b ldr r3, [r7, #16] 80031ee: 4413 add r3, r2 80031f0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80031f4: 461a mov r2, r3 80031f6: 2301 movs r3, #1 80031f8: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_XFRC; 80031fa: 78fa ldrb r2, [r7, #3] 80031fc: 6879 ldr r1, [r7, #4] 80031fe: 4613 mov r3, r2 8003200: 011b lsls r3, r3, #4 8003202: 1a9b subs r3, r3, r2 8003204: 009b lsls r3, r3, #2 8003206: 440b add r3, r1 8003208: 334d adds r3, #77 @ 0x4d 800320a: 2201 movs r2, #1 800320c: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 800320e: 687b ldr r3, [r7, #4] 8003210: 681b ldr r3, [r3, #0] 8003212: 78fa ldrb r2, [r7, #3] 8003214: 4611 mov r1, r2 8003216: 4618 mov r0, r3 8003218: f003 fa36 bl 8006688 800321c: e365 b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) 800321e: 687b ldr r3, [r7, #4] 8003220: 681b ldr r3, [r3, #0] 8003222: 78fa ldrb r2, [r7, #3] 8003224: 4611 mov r1, r2 8003226: 4618 mov r0, r3 8003228: f003 f9b1 bl 800658e 800322c: 4603 mov r3, r0 800322e: f003 0340 and.w r3, r3, #64 @ 0x40 8003232: 2b40 cmp r3, #64 @ 0x40 8003234: d139 bne.n 80032aa { hhcd->hc[chnum].state = HC_NYET; 8003236: 78fa ldrb r2, [r7, #3] 8003238: 6879 ldr r1, [r7, #4] 800323a: 4613 mov r3, r2 800323c: 011b lsls r3, r3, #4 800323e: 1a9b subs r3, r3, r2 8003240: 009b lsls r3, r3, #2 8003242: 440b add r3, r1 8003244: 334d adds r3, #77 @ 0x4d 8003246: 2205 movs r2, #5 8003248: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ssplit == 0U) 800324a: 78fa ldrb r2, [r7, #3] 800324c: 6879 ldr r1, [r7, #4] 800324e: 4613 mov r3, r2 8003250: 011b lsls r3, r3, #4 8003252: 1a9b subs r3, r3, r2 8003254: 009b lsls r3, r3, #2 8003256: 440b add r3, r1 8003258: 331a adds r3, #26 800325a: 781b ldrb r3, [r3, #0] 800325c: 2b00 cmp r3, #0 800325e: d109 bne.n 8003274 { hhcd->hc[chnum].do_ping = 1U; 8003260: 78fa ldrb r2, [r7, #3] 8003262: 6879 ldr r1, [r7, #4] 8003264: 4613 mov r3, r2 8003266: 011b lsls r3, r3, #4 8003268: 1a9b subs r3, r3, r2 800326a: 009b lsls r3, r3, #2 800326c: 440b add r3, r1 800326e: 3319 adds r3, #25 8003270: 2201 movs r2, #1 8003272: 701a strb r2, [r3, #0] } hhcd->hc[chnum].ErrCnt = 0U; 8003274: 78fa ldrb r2, [r7, #3] 8003276: 6879 ldr r1, [r7, #4] 8003278: 4613 mov r3, r2 800327a: 011b lsls r3, r3, #4 800327c: 1a9b subs r3, r3, r2 800327e: 009b lsls r3, r3, #2 8003280: 440b add r3, r1 8003282: 3344 adds r3, #68 @ 0x44 8003284: 2200 movs r2, #0 8003286: 601a str r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 8003288: 687b ldr r3, [r7, #4] 800328a: 681b ldr r3, [r3, #0] 800328c: 78fa ldrb r2, [r7, #3] 800328e: 4611 mov r1, r2 8003290: 4618 mov r0, r3 8003292: f003 f9f9 bl 8006688 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); 8003296: 78fb ldrb r3, [r7, #3] 8003298: 015a lsls r2, r3, #5 800329a: 693b ldr r3, [r7, #16] 800329c: 4413 add r3, r2 800329e: f503 63a0 add.w r3, r3, #1280 @ 0x500 80032a2: 461a mov r2, r3 80032a4: 2340 movs r3, #64 @ 0x40 80032a6: 6093 str r3, [r2, #8] 80032a8: e31f b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) 80032aa: 687b ldr r3, [r7, #4] 80032ac: 681b ldr r3, [r3, #0] 80032ae: 78fa ldrb r2, [r7, #3] 80032b0: 4611 mov r1, r2 80032b2: 4618 mov r0, r3 80032b4: f003 f96b bl 800658e 80032b8: 4603 mov r3, r0 80032ba: f003 0308 and.w r3, r3, #8 80032be: 2b08 cmp r3, #8 80032c0: d11a bne.n 80032f8 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); 80032c2: 78fb ldrb r3, [r7, #3] 80032c4: 015a lsls r2, r3, #5 80032c6: 693b ldr r3, [r7, #16] 80032c8: 4413 add r3, r2 80032ca: f503 63a0 add.w r3, r3, #1280 @ 0x500 80032ce: 461a mov r2, r3 80032d0: 2308 movs r3, #8 80032d2: 6093 str r3, [r2, #8] hhcd->hc[chnum].state = HC_STALL; 80032d4: 78fa ldrb r2, [r7, #3] 80032d6: 6879 ldr r1, [r7, #4] 80032d8: 4613 mov r3, r2 80032da: 011b lsls r3, r3, #4 80032dc: 1a9b subs r3, r3, r2 80032de: 009b lsls r3, r3, #2 80032e0: 440b add r3, r1 80032e2: 334d adds r3, #77 @ 0x4d 80032e4: 2206 movs r2, #6 80032e6: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80032e8: 687b ldr r3, [r7, #4] 80032ea: 681b ldr r3, [r3, #0] 80032ec: 78fa ldrb r2, [r7, #3] 80032ee: 4611 mov r1, r2 80032f0: 4618 mov r0, r3 80032f2: f003 f9c9 bl 8006688 80032f6: e2f8 b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) 80032f8: 687b ldr r3, [r7, #4] 80032fa: 681b ldr r3, [r3, #0] 80032fc: 78fa ldrb r2, [r7, #3] 80032fe: 4611 mov r1, r2 8003300: 4618 mov r0, r3 8003302: f003 f944 bl 800658e 8003306: 4603 mov r3, r0 8003308: f003 0310 and.w r3, r3, #16 800330c: 2b10 cmp r3, #16 800330e: d144 bne.n 800339a { hhcd->hc[chnum].ErrCnt = 0U; 8003310: 78fa ldrb r2, [r7, #3] 8003312: 6879 ldr r1, [r7, #4] 8003314: 4613 mov r3, r2 8003316: 011b lsls r3, r3, #4 8003318: 1a9b subs r3, r3, r2 800331a: 009b lsls r3, r3, #2 800331c: 440b add r3, r1 800331e: 3344 adds r3, #68 @ 0x44 8003320: 2200 movs r2, #0 8003322: 601a str r2, [r3, #0] hhcd->hc[chnum].state = HC_NAK; 8003324: 78fa ldrb r2, [r7, #3] 8003326: 6879 ldr r1, [r7, #4] 8003328: 4613 mov r3, r2 800332a: 011b lsls r3, r3, #4 800332c: 1a9b subs r3, r3, r2 800332e: 009b lsls r3, r3, #2 8003330: 440b add r3, r1 8003332: 334d adds r3, #77 @ 0x4d 8003334: 2204 movs r2, #4 8003336: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_ping == 0U) 8003338: 78fa ldrb r2, [r7, #3] 800333a: 6879 ldr r1, [r7, #4] 800333c: 4613 mov r3, r2 800333e: 011b lsls r3, r3, #4 8003340: 1a9b subs r3, r3, r2 8003342: 009b lsls r3, r3, #2 8003344: 440b add r3, r1 8003346: 3319 adds r3, #25 8003348: 781b ldrb r3, [r3, #0] 800334a: 2b00 cmp r3, #0 800334c: d114 bne.n 8003378 { if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) 800334e: 78fa ldrb r2, [r7, #3] 8003350: 6879 ldr r1, [r7, #4] 8003352: 4613 mov r3, r2 8003354: 011b lsls r3, r3, #4 8003356: 1a9b subs r3, r3, r2 8003358: 009b lsls r3, r3, #2 800335a: 440b add r3, r1 800335c: 3318 adds r3, #24 800335e: 781b ldrb r3, [r3, #0] 8003360: 2b00 cmp r3, #0 8003362: d109 bne.n 8003378 { hhcd->hc[chnum].do_ping = 1U; 8003364: 78fa ldrb r2, [r7, #3] 8003366: 6879 ldr r1, [r7, #4] 8003368: 4613 mov r3, r2 800336a: 011b lsls r3, r3, #4 800336c: 1a9b subs r3, r3, r2 800336e: 009b lsls r3, r3, #2 8003370: 440b add r3, r1 8003372: 3319 adds r3, #25 8003374: 2201 movs r2, #1 8003376: 701a strb r2, [r3, #0] } } (void)USB_HC_Halt(hhcd->Instance, chnum); 8003378: 687b ldr r3, [r7, #4] 800337a: 681b ldr r3, [r3, #0] 800337c: 78fa ldrb r2, [r7, #3] 800337e: 4611 mov r1, r2 8003380: 4618 mov r0, r3 8003382: f003 f981 bl 8006688 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); 8003386: 78fb ldrb r3, [r7, #3] 8003388: 015a lsls r2, r3, #5 800338a: 693b ldr r3, [r7, #16] 800338c: 4413 add r3, r2 800338e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003392: 461a mov r2, r3 8003394: 2310 movs r3, #16 8003396: 6093 str r3, [r2, #8] 8003398: e2a7 b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) 800339a: 687b ldr r3, [r7, #4] 800339c: 681b ldr r3, [r3, #0] 800339e: 78fa ldrb r2, [r7, #3] 80033a0: 4611 mov r1, r2 80033a2: 4618 mov r0, r3 80033a4: f003 f8f3 bl 800658e 80033a8: 4603 mov r3, r0 80033aa: f003 0380 and.w r3, r3, #128 @ 0x80 80033ae: 2b80 cmp r3, #128 @ 0x80 80033b0: f040 8083 bne.w 80034ba { if (hhcd->Init.dma_enable == 0U) 80033b4: 687b ldr r3, [r7, #4] 80033b6: 799b ldrb r3, [r3, #6] 80033b8: 2b00 cmp r3, #0 80033ba: d111 bne.n 80033e0 { hhcd->hc[chnum].state = HC_XACTERR; 80033bc: 78fa ldrb r2, [r7, #3] 80033be: 6879 ldr r1, [r7, #4] 80033c0: 4613 mov r3, r2 80033c2: 011b lsls r3, r3, #4 80033c4: 1a9b subs r3, r3, r2 80033c6: 009b lsls r3, r3, #2 80033c8: 440b add r3, r1 80033ca: 334d adds r3, #77 @ 0x4d 80033cc: 2207 movs r2, #7 80033ce: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80033d0: 687b ldr r3, [r7, #4] 80033d2: 681b ldr r3, [r3, #0] 80033d4: 78fa ldrb r2, [r7, #3] 80033d6: 4611 mov r1, r2 80033d8: 4618 mov r0, r3 80033da: f003 f955 bl 8006688 80033de: e062 b.n 80034a6 } else { hhcd->hc[chnum].ErrCnt++; 80033e0: 78fa ldrb r2, [r7, #3] 80033e2: 6879 ldr r1, [r7, #4] 80033e4: 4613 mov r3, r2 80033e6: 011b lsls r3, r3, #4 80033e8: 1a9b subs r3, r3, r2 80033ea: 009b lsls r3, r3, #2 80033ec: 440b add r3, r1 80033ee: 3344 adds r3, #68 @ 0x44 80033f0: 681b ldr r3, [r3, #0] 80033f2: 1c59 adds r1, r3, #1 80033f4: 6878 ldr r0, [r7, #4] 80033f6: 4613 mov r3, r2 80033f8: 011b lsls r3, r3, #4 80033fa: 1a9b subs r3, r3, r2 80033fc: 009b lsls r3, r3, #2 80033fe: 4403 add r3, r0 8003400: 3344 adds r3, #68 @ 0x44 8003402: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 8003404: 78fa ldrb r2, [r7, #3] 8003406: 6879 ldr r1, [r7, #4] 8003408: 4613 mov r3, r2 800340a: 011b lsls r3, r3, #4 800340c: 1a9b subs r3, r3, r2 800340e: 009b lsls r3, r3, #2 8003410: 440b add r3, r1 8003412: 3344 adds r3, #68 @ 0x44 8003414: 681b ldr r3, [r3, #0] 8003416: 2b02 cmp r3, #2 8003418: d922 bls.n 8003460 { hhcd->hc[chnum].ErrCnt = 0U; 800341a: 78fa ldrb r2, [r7, #3] 800341c: 6879 ldr r1, [r7, #4] 800341e: 4613 mov r3, r2 8003420: 011b lsls r3, r3, #4 8003422: 1a9b subs r3, r3, r2 8003424: 009b lsls r3, r3, #2 8003426: 440b add r3, r1 8003428: 3344 adds r3, #68 @ 0x44 800342a: 2200 movs r2, #0 800342c: 601a str r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 800342e: 78fa ldrb r2, [r7, #3] 8003430: 6879 ldr r1, [r7, #4] 8003432: 4613 mov r3, r2 8003434: 011b lsls r3, r3, #4 8003436: 1a9b subs r3, r3, r2 8003438: 009b lsls r3, r3, #2 800343a: 440b add r3, r1 800343c: 334c adds r3, #76 @ 0x4c 800343e: 2204 movs r2, #4 8003440: 701a strb r2, [r3, #0] #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 8003442: 78fa ldrb r2, [r7, #3] 8003444: 6879 ldr r1, [r7, #4] 8003446: 4613 mov r3, r2 8003448: 011b lsls r3, r3, #4 800344a: 1a9b subs r3, r3, r2 800344c: 009b lsls r3, r3, #2 800344e: 440b add r3, r1 8003450: 334c adds r3, #76 @ 0x4c 8003452: 781a ldrb r2, [r3, #0] 8003454: 78fb ldrb r3, [r7, #3] 8003456: 4619 mov r1, r3 8003458: 6878 ldr r0, [r7, #4] 800345a: f004 fcab bl 8007db4 800345e: e022 b.n 80034a6 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 8003460: 78fa ldrb r2, [r7, #3] 8003462: 6879 ldr r1, [r7, #4] 8003464: 4613 mov r3, r2 8003466: 011b lsls r3, r3, #4 8003468: 1a9b subs r3, r3, r2 800346a: 009b lsls r3, r3, #2 800346c: 440b add r3, r1 800346e: 334c adds r3, #76 @ 0x4c 8003470: 2202 movs r2, #2 8003472: 701a strb r2, [r3, #0] /* Re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8003474: 78fb ldrb r3, [r7, #3] 8003476: 015a lsls r2, r3, #5 8003478: 693b ldr r3, [r7, #16] 800347a: 4413 add r3, r2 800347c: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003480: 681b ldr r3, [r3, #0] 8003482: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8003484: 68fb ldr r3, [r7, #12] 8003486: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 800348a: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 800348c: 68fb ldr r3, [r7, #12] 800348e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8003492: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 8003494: 78fb ldrb r3, [r7, #3] 8003496: 015a lsls r2, r3, #5 8003498: 693b ldr r3, [r7, #16] 800349a: 4413 add r3, r2 800349c: f503 63a0 add.w r3, r3, #1280 @ 0x500 80034a0: 461a mov r2, r3 80034a2: 68fb ldr r3, [r7, #12] 80034a4: 6013 str r3, [r2, #0] } } __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); 80034a6: 78fb ldrb r3, [r7, #3] 80034a8: 015a lsls r2, r3, #5 80034aa: 693b ldr r3, [r7, #16] 80034ac: 4413 add r3, r2 80034ae: f503 63a0 add.w r3, r3, #1280 @ 0x500 80034b2: 461a mov r2, r3 80034b4: 2380 movs r3, #128 @ 0x80 80034b6: 6093 str r3, [r2, #8] 80034b8: e217 b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) 80034ba: 687b ldr r3, [r7, #4] 80034bc: 681b ldr r3, [r3, #0] 80034be: 78fa ldrb r2, [r7, #3] 80034c0: 4611 mov r1, r2 80034c2: 4618 mov r0, r3 80034c4: f003 f863 bl 800658e 80034c8: 4603 mov r3, r0 80034ca: f403 6380 and.w r3, r3, #1024 @ 0x400 80034ce: f5b3 6f80 cmp.w r3, #1024 @ 0x400 80034d2: d11b bne.n 800350c { hhcd->hc[chnum].state = HC_DATATGLERR; 80034d4: 78fa ldrb r2, [r7, #3] 80034d6: 6879 ldr r1, [r7, #4] 80034d8: 4613 mov r3, r2 80034da: 011b lsls r3, r3, #4 80034dc: 1a9b subs r3, r3, r2 80034de: 009b lsls r3, r3, #2 80034e0: 440b add r3, r1 80034e2: 334d adds r3, #77 @ 0x4d 80034e4: 2209 movs r2, #9 80034e6: 701a strb r2, [r3, #0] (void)USB_HC_Halt(hhcd->Instance, chnum); 80034e8: 687b ldr r3, [r7, #4] 80034ea: 681b ldr r3, [r3, #0] 80034ec: 78fa ldrb r2, [r7, #3] 80034ee: 4611 mov r1, r2 80034f0: 4618 mov r0, r3 80034f2: f003 f8c9 bl 8006688 __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); 80034f6: 78fb ldrb r3, [r7, #3] 80034f8: 015a lsls r2, r3, #5 80034fa: 693b ldr r3, [r7, #16] 80034fc: 4413 add r3, r2 80034fe: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003502: 461a mov r2, r3 8003504: f44f 6380 mov.w r3, #1024 @ 0x400 8003508: 6093 str r3, [r2, #8] 800350a: e1ee b.n 80038ea } else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) 800350c: 687b ldr r3, [r7, #4] 800350e: 681b ldr r3, [r3, #0] 8003510: 78fa ldrb r2, [r7, #3] 8003512: 4611 mov r1, r2 8003514: 4618 mov r0, r3 8003516: f003 f83a bl 800658e 800351a: 4603 mov r3, r0 800351c: f003 0302 and.w r3, r3, #2 8003520: 2b02 cmp r3, #2 8003522: f040 81df bne.w 80038e4 { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); 8003526: 78fb ldrb r3, [r7, #3] 8003528: 015a lsls r2, r3, #5 800352a: 693b ldr r3, [r7, #16] 800352c: 4413 add r3, r2 800352e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003532: 461a mov r2, r3 8003534: 2302 movs r3, #2 8003536: 6093 str r3, [r2, #8] if (hhcd->hc[chnum].state == HC_XFRC) 8003538: 78fa ldrb r2, [r7, #3] 800353a: 6879 ldr r1, [r7, #4] 800353c: 4613 mov r3, r2 800353e: 011b lsls r3, r3, #4 8003540: 1a9b subs r3, r3, r2 8003542: 009b lsls r3, r3, #2 8003544: 440b add r3, r1 8003546: 334d adds r3, #77 @ 0x4d 8003548: 781b ldrb r3, [r3, #0] 800354a: 2b01 cmp r3, #1 800354c: f040 8093 bne.w 8003676 { hhcd->hc[chnum].state = HC_HALTED; 8003550: 78fa ldrb r2, [r7, #3] 8003552: 6879 ldr r1, [r7, #4] 8003554: 4613 mov r3, r2 8003556: 011b lsls r3, r3, #4 8003558: 1a9b subs r3, r3, r2 800355a: 009b lsls r3, r3, #2 800355c: 440b add r3, r1 800355e: 334d adds r3, #77 @ 0x4d 8003560: 2202 movs r2, #2 8003562: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_DONE; 8003564: 78fa ldrb r2, [r7, #3] 8003566: 6879 ldr r1, [r7, #4] 8003568: 4613 mov r3, r2 800356a: 011b lsls r3, r3, #4 800356c: 1a9b subs r3, r3, r2 800356e: 009b lsls r3, r3, #2 8003570: 440b add r3, r1 8003572: 334c adds r3, #76 @ 0x4c 8003574: 2201 movs r2, #1 8003576: 701a strb r2, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || 8003578: 78fa ldrb r2, [r7, #3] 800357a: 6879 ldr r1, [r7, #4] 800357c: 4613 mov r3, r2 800357e: 011b lsls r3, r3, #4 8003580: 1a9b subs r3, r3, r2 8003582: 009b lsls r3, r3, #2 8003584: 440b add r3, r1 8003586: 3326 adds r3, #38 @ 0x26 8003588: 781b ldrb r3, [r3, #0] 800358a: 2b02 cmp r3, #2 800358c: d00b beq.n 80035a6 (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) 800358e: 78fa ldrb r2, [r7, #3] 8003590: 6879 ldr r1, [r7, #4] 8003592: 4613 mov r3, r2 8003594: 011b lsls r3, r3, #4 8003596: 1a9b subs r3, r3, r2 8003598: 009b lsls r3, r3, #2 800359a: 440b add r3, r1 800359c: 3326 adds r3, #38 @ 0x26 800359e: 781b ldrb r3, [r3, #0] if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || 80035a0: 2b03 cmp r3, #3 80035a2: f040 8190 bne.w 80038c6 { if (hhcd->Init.dma_enable == 0U) 80035a6: 687b ldr r3, [r7, #4] 80035a8: 799b ldrb r3, [r3, #6] 80035aa: 2b00 cmp r3, #0 80035ac: d115 bne.n 80035da { hhcd->hc[chnum].toggle_out ^= 1U; 80035ae: 78fa ldrb r2, [r7, #3] 80035b0: 6879 ldr r1, [r7, #4] 80035b2: 4613 mov r3, r2 80035b4: 011b lsls r3, r3, #4 80035b6: 1a9b subs r3, r3, r2 80035b8: 009b lsls r3, r3, #2 80035ba: 440b add r3, r1 80035bc: 333d adds r3, #61 @ 0x3d 80035be: 781b ldrb r3, [r3, #0] 80035c0: 78fa ldrb r2, [r7, #3] 80035c2: f083 0301 eor.w r3, r3, #1 80035c6: b2d8 uxtb r0, r3 80035c8: 6879 ldr r1, [r7, #4] 80035ca: 4613 mov r3, r2 80035cc: 011b lsls r3, r3, #4 80035ce: 1a9b subs r3, r3, r2 80035d0: 009b lsls r3, r3, #2 80035d2: 440b add r3, r1 80035d4: 333d adds r3, #61 @ 0x3d 80035d6: 4602 mov r2, r0 80035d8: 701a strb r2, [r3, #0] } if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) 80035da: 687b ldr r3, [r7, #4] 80035dc: 799b ldrb r3, [r3, #6] 80035de: 2b01 cmp r3, #1 80035e0: f040 8171 bne.w 80038c6 80035e4: 78fa ldrb r2, [r7, #3] 80035e6: 6879 ldr r1, [r7, #4] 80035e8: 4613 mov r3, r2 80035ea: 011b lsls r3, r3, #4 80035ec: 1a9b subs r3, r3, r2 80035ee: 009b lsls r3, r3, #2 80035f0: 440b add r3, r1 80035f2: 3334 adds r3, #52 @ 0x34 80035f4: 681b ldr r3, [r3, #0] 80035f6: 2b00 cmp r3, #0 80035f8: f000 8165 beq.w 80038c6 { num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; 80035fc: 78fa ldrb r2, [r7, #3] 80035fe: 6879 ldr r1, [r7, #4] 8003600: 4613 mov r3, r2 8003602: 011b lsls r3, r3, #4 8003604: 1a9b subs r3, r3, r2 8003606: 009b lsls r3, r3, #2 8003608: 440b add r3, r1 800360a: 3334 adds r3, #52 @ 0x34 800360c: 6819 ldr r1, [r3, #0] 800360e: 78fa ldrb r2, [r7, #3] 8003610: 6878 ldr r0, [r7, #4] 8003612: 4613 mov r3, r2 8003614: 011b lsls r3, r3, #4 8003616: 1a9b subs r3, r3, r2 8003618: 009b lsls r3, r3, #2 800361a: 4403 add r3, r0 800361c: 3328 adds r3, #40 @ 0x28 800361e: 881b ldrh r3, [r3, #0] 8003620: 440b add r3, r1 8003622: 1e59 subs r1, r3, #1 8003624: 78fa ldrb r2, [r7, #3] 8003626: 6878 ldr r0, [r7, #4] 8003628: 4613 mov r3, r2 800362a: 011b lsls r3, r3, #4 800362c: 1a9b subs r3, r3, r2 800362e: 009b lsls r3, r3, #2 8003630: 4403 add r3, r0 8003632: 3328 adds r3, #40 @ 0x28 8003634: 881b ldrh r3, [r3, #0] 8003636: fbb1 f3f3 udiv r3, r1, r3 800363a: 60bb str r3, [r7, #8] if ((num_packets & 1U) != 0U) 800363c: 68bb ldr r3, [r7, #8] 800363e: f003 0301 and.w r3, r3, #1 8003642: 2b00 cmp r3, #0 8003644: f000 813f beq.w 80038c6 { hhcd->hc[chnum].toggle_out ^= 1U; 8003648: 78fa ldrb r2, [r7, #3] 800364a: 6879 ldr r1, [r7, #4] 800364c: 4613 mov r3, r2 800364e: 011b lsls r3, r3, #4 8003650: 1a9b subs r3, r3, r2 8003652: 009b lsls r3, r3, #2 8003654: 440b add r3, r1 8003656: 333d adds r3, #61 @ 0x3d 8003658: 781b ldrb r3, [r3, #0] 800365a: 78fa ldrb r2, [r7, #3] 800365c: f083 0301 eor.w r3, r3, #1 8003660: b2d8 uxtb r0, r3 8003662: 6879 ldr r1, [r7, #4] 8003664: 4613 mov r3, r2 8003666: 011b lsls r3, r3, #4 8003668: 1a9b subs r3, r3, r2 800366a: 009b lsls r3, r3, #2 800366c: 440b add r3, r1 800366e: 333d adds r3, #61 @ 0x3d 8003670: 4602 mov r2, r0 8003672: 701a strb r2, [r3, #0] 8003674: e127 b.n 80038c6 } } } } else if (hhcd->hc[chnum].state == HC_ACK) 8003676: 78fa ldrb r2, [r7, #3] 8003678: 6879 ldr r1, [r7, #4] 800367a: 4613 mov r3, r2 800367c: 011b lsls r3, r3, #4 800367e: 1a9b subs r3, r3, r2 8003680: 009b lsls r3, r3, #2 8003682: 440b add r3, r1 8003684: 334d adds r3, #77 @ 0x4d 8003686: 781b ldrb r3, [r3, #0] 8003688: 2b03 cmp r3, #3 800368a: d120 bne.n 80036ce { hhcd->hc[chnum].state = HC_HALTED; 800368c: 78fa ldrb r2, [r7, #3] 800368e: 6879 ldr r1, [r7, #4] 8003690: 4613 mov r3, r2 8003692: 011b lsls r3, r3, #4 8003694: 1a9b subs r3, r3, r2 8003696: 009b lsls r3, r3, #2 8003698: 440b add r3, r1 800369a: 334d adds r3, #77 @ 0x4d 800369c: 2202 movs r2, #2 800369e: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 80036a0: 78fa ldrb r2, [r7, #3] 80036a2: 6879 ldr r1, [r7, #4] 80036a4: 4613 mov r3, r2 80036a6: 011b lsls r3, r3, #4 80036a8: 1a9b subs r3, r3, r2 80036aa: 009b lsls r3, r3, #2 80036ac: 440b add r3, r1 80036ae: 331b adds r3, #27 80036b0: 781b ldrb r3, [r3, #0] 80036b2: 2b01 cmp r3, #1 80036b4: f040 8107 bne.w 80038c6 { hhcd->hc[chnum].urb_state = URB_NOTREADY; 80036b8: 78fa ldrb r2, [r7, #3] 80036ba: 6879 ldr r1, [r7, #4] 80036bc: 4613 mov r3, r2 80036be: 011b lsls r3, r3, #4 80036c0: 1a9b subs r3, r3, r2 80036c2: 009b lsls r3, r3, #2 80036c4: 440b add r3, r1 80036c6: 334c adds r3, #76 @ 0x4c 80036c8: 2202 movs r2, #2 80036ca: 701a strb r2, [r3, #0] 80036cc: e0fb b.n 80038c6 } } else if (hhcd->hc[chnum].state == HC_NAK) 80036ce: 78fa ldrb r2, [r7, #3] 80036d0: 6879 ldr r1, [r7, #4] 80036d2: 4613 mov r3, r2 80036d4: 011b lsls r3, r3, #4 80036d6: 1a9b subs r3, r3, r2 80036d8: 009b lsls r3, r3, #2 80036da: 440b add r3, r1 80036dc: 334d adds r3, #77 @ 0x4d 80036de: 781b ldrb r3, [r3, #0] 80036e0: 2b04 cmp r3, #4 80036e2: d13a bne.n 800375a { hhcd->hc[chnum].state = HC_HALTED; 80036e4: 78fa ldrb r2, [r7, #3] 80036e6: 6879 ldr r1, [r7, #4] 80036e8: 4613 mov r3, r2 80036ea: 011b lsls r3, r3, #4 80036ec: 1a9b subs r3, r3, r2 80036ee: 009b lsls r3, r3, #2 80036f0: 440b add r3, r1 80036f2: 334d adds r3, #77 @ 0x4d 80036f4: 2202 movs r2, #2 80036f6: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 80036f8: 78fa ldrb r2, [r7, #3] 80036fa: 6879 ldr r1, [r7, #4] 80036fc: 4613 mov r3, r2 80036fe: 011b lsls r3, r3, #4 8003700: 1a9b subs r3, r3, r2 8003702: 009b lsls r3, r3, #2 8003704: 440b add r3, r1 8003706: 334c adds r3, #76 @ 0x4c 8003708: 2202 movs r2, #2 800370a: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].do_csplit == 1U) 800370c: 78fa ldrb r2, [r7, #3] 800370e: 6879 ldr r1, [r7, #4] 8003710: 4613 mov r3, r2 8003712: 011b lsls r3, r3, #4 8003714: 1a9b subs r3, r3, r2 8003716: 009b lsls r3, r3, #2 8003718: 440b add r3, r1 800371a: 331b adds r3, #27 800371c: 781b ldrb r3, [r3, #0] 800371e: 2b01 cmp r3, #1 8003720: f040 80d1 bne.w 80038c6 { hhcd->hc[chnum].do_csplit = 0U; 8003724: 78fa ldrb r2, [r7, #3] 8003726: 6879 ldr r1, [r7, #4] 8003728: 4613 mov r3, r2 800372a: 011b lsls r3, r3, #4 800372c: 1a9b subs r3, r3, r2 800372e: 009b lsls r3, r3, #2 8003730: 440b add r3, r1 8003732: 331b adds r3, #27 8003734: 2200 movs r2, #0 8003736: 701a strb r2, [r3, #0] __HAL_HCD_CLEAR_HC_CSPLT(chnum); 8003738: 78fb ldrb r3, [r7, #3] 800373a: 015a lsls r2, r3, #5 800373c: 693b ldr r3, [r7, #16] 800373e: 4413 add r3, r2 8003740: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003744: 685b ldr r3, [r3, #4] 8003746: 78fa ldrb r2, [r7, #3] 8003748: 0151 lsls r1, r2, #5 800374a: 693a ldr r2, [r7, #16] 800374c: 440a add r2, r1 800374e: f502 62a0 add.w r2, r2, #1280 @ 0x500 8003752: f423 3380 bic.w r3, r3, #65536 @ 0x10000 8003756: 6053 str r3, [r2, #4] 8003758: e0b5 b.n 80038c6 } } else if (hhcd->hc[chnum].state == HC_NYET) 800375a: 78fa ldrb r2, [r7, #3] 800375c: 6879 ldr r1, [r7, #4] 800375e: 4613 mov r3, r2 8003760: 011b lsls r3, r3, #4 8003762: 1a9b subs r3, r3, r2 8003764: 009b lsls r3, r3, #2 8003766: 440b add r3, r1 8003768: 334d adds r3, #77 @ 0x4d 800376a: 781b ldrb r3, [r3, #0] 800376c: 2b05 cmp r3, #5 800376e: d114 bne.n 800379a { hhcd->hc[chnum].state = HC_HALTED; 8003770: 78fa ldrb r2, [r7, #3] 8003772: 6879 ldr r1, [r7, #4] 8003774: 4613 mov r3, r2 8003776: 011b lsls r3, r3, #4 8003778: 1a9b subs r3, r3, r2 800377a: 009b lsls r3, r3, #2 800377c: 440b add r3, r1 800377e: 334d adds r3, #77 @ 0x4d 8003780: 2202 movs r2, #2 8003782: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_NOTREADY; 8003784: 78fa ldrb r2, [r7, #3] 8003786: 6879 ldr r1, [r7, #4] 8003788: 4613 mov r3, r2 800378a: 011b lsls r3, r3, #4 800378c: 1a9b subs r3, r3, r2 800378e: 009b lsls r3, r3, #2 8003790: 440b add r3, r1 8003792: 334c adds r3, #76 @ 0x4c 8003794: 2202 movs r2, #2 8003796: 701a strb r2, [r3, #0] 8003798: e095 b.n 80038c6 } else if (hhcd->hc[chnum].state == HC_STALL) 800379a: 78fa ldrb r2, [r7, #3] 800379c: 6879 ldr r1, [r7, #4] 800379e: 4613 mov r3, r2 80037a0: 011b lsls r3, r3, #4 80037a2: 1a9b subs r3, r3, r2 80037a4: 009b lsls r3, r3, #2 80037a6: 440b add r3, r1 80037a8: 334d adds r3, #77 @ 0x4d 80037aa: 781b ldrb r3, [r3, #0] 80037ac: 2b06 cmp r3, #6 80037ae: d114 bne.n 80037da { hhcd->hc[chnum].state = HC_HALTED; 80037b0: 78fa ldrb r2, [r7, #3] 80037b2: 6879 ldr r1, [r7, #4] 80037b4: 4613 mov r3, r2 80037b6: 011b lsls r3, r3, #4 80037b8: 1a9b subs r3, r3, r2 80037ba: 009b lsls r3, r3, #2 80037bc: 440b add r3, r1 80037be: 334d adds r3, #77 @ 0x4d 80037c0: 2202 movs r2, #2 80037c2: 701a strb r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_STALL; 80037c4: 78fa ldrb r2, [r7, #3] 80037c6: 6879 ldr r1, [r7, #4] 80037c8: 4613 mov r3, r2 80037ca: 011b lsls r3, r3, #4 80037cc: 1a9b subs r3, r3, r2 80037ce: 009b lsls r3, r3, #2 80037d0: 440b add r3, r1 80037d2: 334c adds r3, #76 @ 0x4c 80037d4: 2205 movs r2, #5 80037d6: 701a strb r2, [r3, #0] 80037d8: e075 b.n 80038c6 } else if ((hhcd->hc[chnum].state == HC_XACTERR) || 80037da: 78fa ldrb r2, [r7, #3] 80037dc: 6879 ldr r1, [r7, #4] 80037de: 4613 mov r3, r2 80037e0: 011b lsls r3, r3, #4 80037e2: 1a9b subs r3, r3, r2 80037e4: 009b lsls r3, r3, #2 80037e6: 440b add r3, r1 80037e8: 334d adds r3, #77 @ 0x4d 80037ea: 781b ldrb r3, [r3, #0] 80037ec: 2b07 cmp r3, #7 80037ee: d00a beq.n 8003806 (hhcd->hc[chnum].state == HC_DATATGLERR)) 80037f0: 78fa ldrb r2, [r7, #3] 80037f2: 6879 ldr r1, [r7, #4] 80037f4: 4613 mov r3, r2 80037f6: 011b lsls r3, r3, #4 80037f8: 1a9b subs r3, r3, r2 80037fa: 009b lsls r3, r3, #2 80037fc: 440b add r3, r1 80037fe: 334d adds r3, #77 @ 0x4d 8003800: 781b ldrb r3, [r3, #0] else if ((hhcd->hc[chnum].state == HC_XACTERR) || 8003802: 2b09 cmp r3, #9 8003804: d170 bne.n 80038e8 { hhcd->hc[chnum].state = HC_HALTED; 8003806: 78fa ldrb r2, [r7, #3] 8003808: 6879 ldr r1, [r7, #4] 800380a: 4613 mov r3, r2 800380c: 011b lsls r3, r3, #4 800380e: 1a9b subs r3, r3, r2 8003810: 009b lsls r3, r3, #2 8003812: 440b add r3, r1 8003814: 334d adds r3, #77 @ 0x4d 8003816: 2202 movs r2, #2 8003818: 701a strb r2, [r3, #0] hhcd->hc[chnum].ErrCnt++; 800381a: 78fa ldrb r2, [r7, #3] 800381c: 6879 ldr r1, [r7, #4] 800381e: 4613 mov r3, r2 8003820: 011b lsls r3, r3, #4 8003822: 1a9b subs r3, r3, r2 8003824: 009b lsls r3, r3, #2 8003826: 440b add r3, r1 8003828: 3344 adds r3, #68 @ 0x44 800382a: 681b ldr r3, [r3, #0] 800382c: 1c59 adds r1, r3, #1 800382e: 6878 ldr r0, [r7, #4] 8003830: 4613 mov r3, r2 8003832: 011b lsls r3, r3, #4 8003834: 1a9b subs r3, r3, r2 8003836: 009b lsls r3, r3, #2 8003838: 4403 add r3, r0 800383a: 3344 adds r3, #68 @ 0x44 800383c: 6019 str r1, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800383e: 78fa ldrb r2, [r7, #3] 8003840: 6879 ldr r1, [r7, #4] 8003842: 4613 mov r3, r2 8003844: 011b lsls r3, r3, #4 8003846: 1a9b subs r3, r3, r2 8003848: 009b lsls r3, r3, #2 800384a: 440b add r3, r1 800384c: 3344 adds r3, #68 @ 0x44 800384e: 681b ldr r3, [r3, #0] 8003850: 2b02 cmp r3, #2 8003852: d914 bls.n 800387e { hhcd->hc[chnum].ErrCnt = 0U; 8003854: 78fa ldrb r2, [r7, #3] 8003856: 6879 ldr r1, [r7, #4] 8003858: 4613 mov r3, r2 800385a: 011b lsls r3, r3, #4 800385c: 1a9b subs r3, r3, r2 800385e: 009b lsls r3, r3, #2 8003860: 440b add r3, r1 8003862: 3344 adds r3, #68 @ 0x44 8003864: 2200 movs r2, #0 8003866: 601a str r2, [r3, #0] hhcd->hc[chnum].urb_state = URB_ERROR; 8003868: 78fa ldrb r2, [r7, #3] 800386a: 6879 ldr r1, [r7, #4] 800386c: 4613 mov r3, r2 800386e: 011b lsls r3, r3, #4 8003870: 1a9b subs r3, r3, r2 8003872: 009b lsls r3, r3, #2 8003874: 440b add r3, r1 8003876: 334c adds r3, #76 @ 0x4c 8003878: 2204 movs r2, #4 800387a: 701a strb r2, [r3, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 800387c: e022 b.n 80038c4 } else { hhcd->hc[chnum].urb_state = URB_NOTREADY; 800387e: 78fa ldrb r2, [r7, #3] 8003880: 6879 ldr r1, [r7, #4] 8003882: 4613 mov r3, r2 8003884: 011b lsls r3, r3, #4 8003886: 1a9b subs r3, r3, r2 8003888: 009b lsls r3, r3, #2 800388a: 440b add r3, r1 800388c: 334c adds r3, #76 @ 0x4c 800388e: 2202 movs r2, #2 8003890: 701a strb r2, [r3, #0] /* re-activate the channel */ tmpreg = USBx_HC(chnum)->HCCHAR; 8003892: 78fb ldrb r3, [r7, #3] 8003894: 015a lsls r2, r3, #5 8003896: 693b ldr r3, [r7, #16] 8003898: 4413 add r3, r2 800389a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800389e: 681b ldr r3, [r3, #0] 80038a0: 60fb str r3, [r7, #12] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 80038a2: 68fb ldr r3, [r7, #12] 80038a4: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 80038a8: 60fb str r3, [r7, #12] tmpreg |= USB_OTG_HCCHAR_CHENA; 80038aa: 68fb ldr r3, [r7, #12] 80038ac: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80038b0: 60fb str r3, [r7, #12] USBx_HC(chnum)->HCCHAR = tmpreg; 80038b2: 78fb ldrb r3, [r7, #3] 80038b4: 015a lsls r2, r3, #5 80038b6: 693b ldr r3, [r7, #16] 80038b8: 4413 add r3, r2 80038ba: f503 63a0 add.w r3, r3, #1280 @ 0x500 80038be: 461a mov r2, r3 80038c0: 68fb ldr r3, [r7, #12] 80038c2: 6013 str r3, [r2, #0] if (hhcd->hc[chnum].ErrCnt > 2U) 80038c4: bf00 nop } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); 80038c6: 78fa ldrb r2, [r7, #3] 80038c8: 6879 ldr r1, [r7, #4] 80038ca: 4613 mov r3, r2 80038cc: 011b lsls r3, r3, #4 80038ce: 1a9b subs r3, r3, r2 80038d0: 009b lsls r3, r3, #2 80038d2: 440b add r3, r1 80038d4: 334c adds r3, #76 @ 0x4c 80038d6: 781a ldrb r2, [r3, #0] 80038d8: 78fb ldrb r3, [r7, #3] 80038da: 4619 mov r1, r3 80038dc: 6878 ldr r0, [r7, #4] 80038de: f004 fa69 bl 8007db4 80038e2: e002 b.n 80038ea #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { return; 80038e4: bf00 nop 80038e6: e000 b.n 80038ea return; 80038e8: bf00 nop } } 80038ea: 3718 adds r7, #24 80038ec: 46bd mov sp, r7 80038ee: bd80 pop {r7, pc} 080038f0 : * @brief Handle Rx Queue Level interrupt requests. * @param hhcd HCD handle * @retval none */ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { 80038f0: b580 push {r7, lr} 80038f2: b08a sub sp, #40 @ 0x28 80038f4: af00 add r7, sp, #0 80038f6: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 80038f8: 687b ldr r3, [r7, #4] 80038fa: 681b ldr r3, [r3, #0] 80038fc: 627b str r3, [r7, #36] @ 0x24 uint32_t USBx_BASE = (uint32_t)USBx; 80038fe: 6a7b ldr r3, [r7, #36] @ 0x24 8003900: 623b str r3, [r7, #32] uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; 8003902: 687b ldr r3, [r7, #4] 8003904: 681b ldr r3, [r3, #0] 8003906: 6a1b ldr r3, [r3, #32] 8003908: 61fb str r3, [r7, #28] chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; 800390a: 69fb ldr r3, [r7, #28] 800390c: f003 030f and.w r3, r3, #15 8003910: 61bb str r3, [r7, #24] pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; 8003912: 69fb ldr r3, [r7, #28] 8003914: 0c5b lsrs r3, r3, #17 8003916: f003 030f and.w r3, r3, #15 800391a: 617b str r3, [r7, #20] pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; 800391c: 69fb ldr r3, [r7, #28] 800391e: 091b lsrs r3, r3, #4 8003920: f3c3 030a ubfx r3, r3, #0, #11 8003924: 613b str r3, [r7, #16] switch (pktsts) 8003926: 697b ldr r3, [r7, #20] 8003928: 2b02 cmp r3, #2 800392a: d004 beq.n 8003936 800392c: 697b ldr r3, [r7, #20] 800392e: 2b05 cmp r3, #5 8003930: f000 80b6 beq.w 8003aa0 break; case GRXSTS_PKTSTS_IN_XFER_COMP: case GRXSTS_PKTSTS_CH_HALTED: default: break; 8003934: e0b7 b.n 8003aa6 if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) 8003936: 693b ldr r3, [r7, #16] 8003938: 2b00 cmp r3, #0 800393a: f000 80b3 beq.w 8003aa4 800393e: 6879 ldr r1, [r7, #4] 8003940: 69ba ldr r2, [r7, #24] 8003942: 4613 mov r3, r2 8003944: 011b lsls r3, r3, #4 8003946: 1a9b subs r3, r3, r2 8003948: 009b lsls r3, r3, #2 800394a: 440b add r3, r1 800394c: 332c adds r3, #44 @ 0x2c 800394e: 681b ldr r3, [r3, #0] 8003950: 2b00 cmp r3, #0 8003952: f000 80a7 beq.w 8003aa4 if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) 8003956: 6879 ldr r1, [r7, #4] 8003958: 69ba ldr r2, [r7, #24] 800395a: 4613 mov r3, r2 800395c: 011b lsls r3, r3, #4 800395e: 1a9b subs r3, r3, r2 8003960: 009b lsls r3, r3, #2 8003962: 440b add r3, r1 8003964: 3338 adds r3, #56 @ 0x38 8003966: 681a ldr r2, [r3, #0] 8003968: 693b ldr r3, [r7, #16] 800396a: 18d1 adds r1, r2, r3 800396c: 6878 ldr r0, [r7, #4] 800396e: 69ba ldr r2, [r7, #24] 8003970: 4613 mov r3, r2 8003972: 011b lsls r3, r3, #4 8003974: 1a9b subs r3, r3, r2 8003976: 009b lsls r3, r3, #2 8003978: 4403 add r3, r0 800397a: 3334 adds r3, #52 @ 0x34 800397c: 681b ldr r3, [r3, #0] 800397e: 4299 cmp r1, r3 8003980: f200 8083 bhi.w 8003a8a (void)USB_ReadPacket(hhcd->Instance, 8003984: 687b ldr r3, [r7, #4] 8003986: 6818 ldr r0, [r3, #0] 8003988: 6879 ldr r1, [r7, #4] 800398a: 69ba ldr r2, [r7, #24] 800398c: 4613 mov r3, r2 800398e: 011b lsls r3, r3, #4 8003990: 1a9b subs r3, r3, r2 8003992: 009b lsls r3, r3, #2 8003994: 440b add r3, r1 8003996: 332c adds r3, #44 @ 0x2c 8003998: 681b ldr r3, [r3, #0] 800399a: 693a ldr r2, [r7, #16] 800399c: b292 uxth r2, r2 800399e: 4619 mov r1, r3 80039a0: f002 fd8a bl 80064b8 hhcd->hc[chnum].xfer_buff += pktcnt; 80039a4: 6879 ldr r1, [r7, #4] 80039a6: 69ba ldr r2, [r7, #24] 80039a8: 4613 mov r3, r2 80039aa: 011b lsls r3, r3, #4 80039ac: 1a9b subs r3, r3, r2 80039ae: 009b lsls r3, r3, #2 80039b0: 440b add r3, r1 80039b2: 332c adds r3, #44 @ 0x2c 80039b4: 681a ldr r2, [r3, #0] 80039b6: 693b ldr r3, [r7, #16] 80039b8: 18d1 adds r1, r2, r3 80039ba: 6878 ldr r0, [r7, #4] 80039bc: 69ba ldr r2, [r7, #24] 80039be: 4613 mov r3, r2 80039c0: 011b lsls r3, r3, #4 80039c2: 1a9b subs r3, r3, r2 80039c4: 009b lsls r3, r3, #2 80039c6: 4403 add r3, r0 80039c8: 332c adds r3, #44 @ 0x2c 80039ca: 6019 str r1, [r3, #0] hhcd->hc[chnum].xfer_count += pktcnt; 80039cc: 6879 ldr r1, [r7, #4] 80039ce: 69ba ldr r2, [r7, #24] 80039d0: 4613 mov r3, r2 80039d2: 011b lsls r3, r3, #4 80039d4: 1a9b subs r3, r3, r2 80039d6: 009b lsls r3, r3, #2 80039d8: 440b add r3, r1 80039da: 3338 adds r3, #56 @ 0x38 80039dc: 681a ldr r2, [r3, #0] 80039de: 693b ldr r3, [r7, #16] 80039e0: 18d1 adds r1, r2, r3 80039e2: 6878 ldr r0, [r7, #4] 80039e4: 69ba ldr r2, [r7, #24] 80039e6: 4613 mov r3, r2 80039e8: 011b lsls r3, r3, #4 80039ea: 1a9b subs r3, r3, r2 80039ec: 009b lsls r3, r3, #2 80039ee: 4403 add r3, r0 80039f0: 3338 adds r3, #56 @ 0x38 80039f2: 6019 str r1, [r3, #0] xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; 80039f4: 69bb ldr r3, [r7, #24] 80039f6: 015a lsls r2, r3, #5 80039f8: 6a3b ldr r3, [r7, #32] 80039fa: 4413 add r3, r2 80039fc: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a00: 691b ldr r3, [r3, #16] 8003a02: 0cdb lsrs r3, r3, #19 8003a04: f3c3 0309 ubfx r3, r3, #0, #10 8003a08: 60fb str r3, [r7, #12] if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) 8003a0a: 6879 ldr r1, [r7, #4] 8003a0c: 69ba ldr r2, [r7, #24] 8003a0e: 4613 mov r3, r2 8003a10: 011b lsls r3, r3, #4 8003a12: 1a9b subs r3, r3, r2 8003a14: 009b lsls r3, r3, #2 8003a16: 440b add r3, r1 8003a18: 3328 adds r3, #40 @ 0x28 8003a1a: 881b ldrh r3, [r3, #0] 8003a1c: 461a mov r2, r3 8003a1e: 693b ldr r3, [r7, #16] 8003a20: 4293 cmp r3, r2 8003a22: d13f bne.n 8003aa4 8003a24: 68fb ldr r3, [r7, #12] 8003a26: 2b00 cmp r3, #0 8003a28: d03c beq.n 8003aa4 tmpreg = USBx_HC(chnum)->HCCHAR; 8003a2a: 69bb ldr r3, [r7, #24] 8003a2c: 015a lsls r2, r3, #5 8003a2e: 6a3b ldr r3, [r7, #32] 8003a30: 4413 add r3, r2 8003a32: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a36: 681b ldr r3, [r3, #0] 8003a38: 60bb str r3, [r7, #8] tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 8003a3a: 68bb ldr r3, [r7, #8] 8003a3c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000 8003a40: 60bb str r3, [r7, #8] tmpreg |= USB_OTG_HCCHAR_CHENA; 8003a42: 68bb ldr r3, [r7, #8] 8003a44: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8003a48: 60bb str r3, [r7, #8] USBx_HC(chnum)->HCCHAR = tmpreg; 8003a4a: 69bb ldr r3, [r7, #24] 8003a4c: 015a lsls r2, r3, #5 8003a4e: 6a3b ldr r3, [r7, #32] 8003a50: 4413 add r3, r2 8003a52: f503 63a0 add.w r3, r3, #1280 @ 0x500 8003a56: 461a mov r2, r3 8003a58: 68bb ldr r3, [r7, #8] 8003a5a: 6013 str r3, [r2, #0] hhcd->hc[chnum].toggle_in ^= 1U; 8003a5c: 6879 ldr r1, [r7, #4] 8003a5e: 69ba ldr r2, [r7, #24] 8003a60: 4613 mov r3, r2 8003a62: 011b lsls r3, r3, #4 8003a64: 1a9b subs r3, r3, r2 8003a66: 009b lsls r3, r3, #2 8003a68: 440b add r3, r1 8003a6a: 333c adds r3, #60 @ 0x3c 8003a6c: 781b ldrb r3, [r3, #0] 8003a6e: f083 0301 eor.w r3, r3, #1 8003a72: b2d8 uxtb r0, r3 8003a74: 6879 ldr r1, [r7, #4] 8003a76: 69ba ldr r2, [r7, #24] 8003a78: 4613 mov r3, r2 8003a7a: 011b lsls r3, r3, #4 8003a7c: 1a9b subs r3, r3, r2 8003a7e: 009b lsls r3, r3, #2 8003a80: 440b add r3, r1 8003a82: 333c adds r3, #60 @ 0x3c 8003a84: 4602 mov r2, r0 8003a86: 701a strb r2, [r3, #0] break; 8003a88: e00c b.n 8003aa4 hhcd->hc[chnum].urb_state = URB_ERROR; 8003a8a: 6879 ldr r1, [r7, #4] 8003a8c: 69ba ldr r2, [r7, #24] 8003a8e: 4613 mov r3, r2 8003a90: 011b lsls r3, r3, #4 8003a92: 1a9b subs r3, r3, r2 8003a94: 009b lsls r3, r3, #2 8003a96: 440b add r3, r1 8003a98: 334c adds r3, #76 @ 0x4c 8003a9a: 2204 movs r2, #4 8003a9c: 701a strb r2, [r3, #0] break; 8003a9e: e001 b.n 8003aa4 break; 8003aa0: bf00 nop 8003aa2: e000 b.n 8003aa6 break; 8003aa4: bf00 nop } } 8003aa6: bf00 nop 8003aa8: 3728 adds r7, #40 @ 0x28 8003aaa: 46bd mov sp, r7 8003aac: bd80 pop {r7, pc} 08003aae : * @brief Handle Host Port interrupt requests. * @param hhcd HCD handle * @retval None */ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { 8003aae: b580 push {r7, lr} 8003ab0: b086 sub sp, #24 8003ab2: af00 add r7, sp, #0 8003ab4: 6078 str r0, [r7, #4] const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; 8003ab6: 687b ldr r3, [r7, #4] 8003ab8: 681b ldr r3, [r3, #0] 8003aba: 617b str r3, [r7, #20] uint32_t USBx_BASE = (uint32_t)USBx; 8003abc: 697b ldr r3, [r7, #20] 8003abe: 613b str r3, [r7, #16] __IO uint32_t hprt0; __IO uint32_t hprt0_dup; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; 8003ac0: 693b ldr r3, [r7, #16] 8003ac2: f503 6388 add.w r3, r3, #1088 @ 0x440 8003ac6: 681b ldr r3, [r3, #0] 8003ac8: 60fb str r3, [r7, #12] hprt0_dup = USBx_HPRT0; 8003aca: 693b ldr r3, [r7, #16] 8003acc: f503 6388 add.w r3, r3, #1088 @ 0x440 8003ad0: 681b ldr r3, [r3, #0] 8003ad2: 60bb str r3, [r7, #8] hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ 8003ad4: 68bb ldr r3, [r7, #8] 8003ad6: f023 032e bic.w r3, r3, #46 @ 0x2e 8003ada: 60bb str r3, [r7, #8] USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); /* Check whether Port Connect detected */ if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) 8003adc: 68fb ldr r3, [r7, #12] 8003ade: f003 0302 and.w r3, r3, #2 8003ae2: 2b02 cmp r3, #2 8003ae4: d10b bne.n 8003afe { if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) 8003ae6: 68fb ldr r3, [r7, #12] 8003ae8: f003 0301 and.w r3, r3, #1 8003aec: 2b01 cmp r3, #1 8003aee: d102 bne.n 8003af6 { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->ConnectCallback(hhcd); #else HAL_HCD_Connect_Callback(hhcd); 8003af0: 6878 ldr r0, [r7, #4] 8003af2: f004 f943 bl 8007d7c #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } hprt0_dup |= USB_OTG_HPRT_PCDET; 8003af6: 68bb ldr r3, [r7, #8] 8003af8: f043 0302 orr.w r3, r3, #2 8003afc: 60bb str r3, [r7, #8] } /* Check whether Port Enable Changed */ if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) 8003afe: 68fb ldr r3, [r7, #12] 8003b00: f003 0308 and.w r3, r3, #8 8003b04: 2b08 cmp r3, #8 8003b06: d132 bne.n 8003b6e { hprt0_dup |= USB_OTG_HPRT_PENCHNG; 8003b08: 68bb ldr r3, [r7, #8] 8003b0a: f043 0308 orr.w r3, r3, #8 8003b0e: 60bb str r3, [r7, #8] if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) 8003b10: 68fb ldr r3, [r7, #12] 8003b12: f003 0304 and.w r3, r3, #4 8003b16: 2b04 cmp r3, #4 8003b18: d126 bne.n 8003b68 { if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) 8003b1a: 687b ldr r3, [r7, #4] 8003b1c: 7a5b ldrb r3, [r3, #9] 8003b1e: 2b02 cmp r3, #2 8003b20: d113 bne.n 8003b4a { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) 8003b22: 68fb ldr r3, [r7, #12] 8003b24: f403 23c0 and.w r3, r3, #393216 @ 0x60000 8003b28: f5b3 2f80 cmp.w r3, #262144 @ 0x40000 8003b2c: d106 bne.n 8003b3c { (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); 8003b2e: 687b ldr r3, [r7, #4] 8003b30: 681b ldr r3, [r3, #0] 8003b32: 2102 movs r1, #2 8003b34: 4618 mov r0, r3 8003b36: f002 fd59 bl 80065ec 8003b3a: e011 b.n 8003b60 } else { (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); 8003b3c: 687b ldr r3, [r7, #4] 8003b3e: 681b ldr r3, [r3, #0] 8003b40: 2101 movs r1, #1 8003b42: 4618 mov r0, r3 8003b44: f002 fd52 bl 80065ec 8003b48: e00a b.n 8003b60 } } else { if (hhcd->Init.speed == HCD_SPEED_FULL) 8003b4a: 687b ldr r3, [r7, #4] 8003b4c: 79db ldrb r3, [r3, #7] 8003b4e: 2b01 cmp r3, #1 8003b50: d106 bne.n 8003b60 { USBx_HOST->HFIR = HFIR_60_MHZ; 8003b52: 693b ldr r3, [r7, #16] 8003b54: f503 6380 add.w r3, r3, #1024 @ 0x400 8003b58: 461a mov r2, r3 8003b5a: f64e 2360 movw r3, #60000 @ 0xea60 8003b5e: 6053 str r3, [r2, #4] } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortEnabledCallback(hhcd); #else HAL_HCD_PortEnabled_Callback(hhcd); 8003b60: 6878 ldr r0, [r7, #4] 8003b62: f004 f939 bl 8007dd8 8003b66: e002 b.n 8003b6e else { #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortDisabledCallback(hhcd); #else HAL_HCD_PortDisabled_Callback(hhcd); 8003b68: 6878 ldr r0, [r7, #4] 8003b6a: f004 f943 bl 8007df4 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } } /* Check for an overcurrent */ if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) 8003b6e: 68fb ldr r3, [r7, #12] 8003b70: f003 0320 and.w r3, r3, #32 8003b74: 2b20 cmp r3, #32 8003b76: d103 bne.n 8003b80 { hprt0_dup |= USB_OTG_HPRT_POCCHNG; 8003b78: 68bb ldr r3, [r7, #8] 8003b7a: f043 0320 orr.w r3, r3, #32 8003b7e: 60bb str r3, [r7, #8] } /* Clear Port Interrupts */ USBx_HPRT0 = hprt0_dup; 8003b80: 693b ldr r3, [r7, #16] 8003b82: f503 6388 add.w r3, r3, #1088 @ 0x440 8003b86: 461a mov r2, r3 8003b88: 68bb ldr r3, [r7, #8] 8003b8a: 6013 str r3, [r2, #0] } 8003b8c: bf00 nop 8003b8e: 3718 adds r7, #24 8003b90: 46bd mov sp, r7 8003b92: bd80 pop {r7, pc} 08003b94 : * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { 8003b94: b580 push {r7, lr} 8003b96: b084 sub sp, #16 8003b98: af00 add r7, sp, #0 8003b9a: 6078 str r0, [r7, #4] uint32_t freqrange; uint32_t pclk1; /* Check the I2C handle allocation */ if (hi2c == NULL) 8003b9c: 687b ldr r3, [r7, #4] 8003b9e: 2b00 cmp r3, #0 8003ba0: d101 bne.n 8003ba6 { return HAL_ERROR; 8003ba2: 2301 movs r3, #1 8003ba4: e12b b.n 8003dfe assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); if (hi2c->State == HAL_I2C_STATE_RESET) 8003ba6: 687b ldr r3, [r7, #4] 8003ba8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003bac: b2db uxtb r3, r3 8003bae: 2b00 cmp r3, #0 8003bb0: d106 bne.n 8003bc0 { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; 8003bb2: 687b ldr r3, [r7, #4] 8003bb4: 2200 movs r2, #0 8003bb6: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Init the low level hardware : GPIO, CLOCK, NVIC */ hi2c->MspInitCallback(hi2c); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); 8003bba: 6878 ldr r0, [r7, #4] 8003bbc: f7fd f932 bl 8000e24 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ } hi2c->State = HAL_I2C_STATE_BUSY; 8003bc0: 687b ldr r3, [r7, #4] 8003bc2: 2224 movs r2, #36 @ 0x24 8003bc4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003bc8: 687b ldr r3, [r7, #4] 8003bca: 681b ldr r3, [r3, #0] 8003bcc: 681a ldr r2, [r3, #0] 8003bce: 687b ldr r3, [r7, #4] 8003bd0: 681b ldr r3, [r3, #0] 8003bd2: f022 0201 bic.w r2, r2, #1 8003bd6: 601a str r2, [r3, #0] /*Reset I2C*/ hi2c->Instance->CR1 |= I2C_CR1_SWRST; 8003bd8: 687b ldr r3, [r7, #4] 8003bda: 681b ldr r3, [r3, #0] 8003bdc: 681a ldr r2, [r3, #0] 8003bde: 687b ldr r3, [r7, #4] 8003be0: 681b ldr r3, [r3, #0] 8003be2: f442 4200 orr.w r2, r2, #32768 @ 0x8000 8003be6: 601a str r2, [r3, #0] hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 8003be8: 687b ldr r3, [r7, #4] 8003bea: 681b ldr r3, [r3, #0] 8003bec: 681a ldr r2, [r3, #0] 8003bee: 687b ldr r3, [r7, #4] 8003bf0: 681b ldr r3, [r3, #0] 8003bf2: f422 4200 bic.w r2, r2, #32768 @ 0x8000 8003bf6: 601a str r2, [r3, #0] /* Get PCLK1 frequency */ pclk1 = HAL_RCC_GetPCLK1Freq(); 8003bf8: f001 f90c bl 8004e14 8003bfc: 60f8 str r0, [r7, #12] /* Check the minimum allowed PCLK1 frequency */ if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 8003bfe: 687b ldr r3, [r7, #4] 8003c00: 685b ldr r3, [r3, #4] 8003c02: 4a81 ldr r2, [pc, #516] @ (8003e08 ) 8003c04: 4293 cmp r3, r2 8003c06: d807 bhi.n 8003c18 8003c08: 68fb ldr r3, [r7, #12] 8003c0a: 4a80 ldr r2, [pc, #512] @ (8003e0c ) 8003c0c: 4293 cmp r3, r2 8003c0e: bf94 ite ls 8003c10: 2301 movls r3, #1 8003c12: 2300 movhi r3, #0 8003c14: b2db uxtb r3, r3 8003c16: e006 b.n 8003c26 8003c18: 68fb ldr r3, [r7, #12] 8003c1a: 4a7d ldr r2, [pc, #500] @ (8003e10 ) 8003c1c: 4293 cmp r3, r2 8003c1e: bf94 ite ls 8003c20: 2301 movls r3, #1 8003c22: 2300 movhi r3, #0 8003c24: b2db uxtb r3, r3 8003c26: 2b00 cmp r3, #0 8003c28: d001 beq.n 8003c2e { return HAL_ERROR; 8003c2a: 2301 movs r3, #1 8003c2c: e0e7 b.n 8003dfe } /* Calculate frequency range */ freqrange = I2C_FREQRANGE(pclk1); 8003c2e: 68fb ldr r3, [r7, #12] 8003c30: 4a78 ldr r2, [pc, #480] @ (8003e14 ) 8003c32: fba2 2303 umull r2, r3, r2, r3 8003c36: 0c9b lsrs r3, r3, #18 8003c38: 60bb str r3, [r7, #8] /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 8003c3a: 687b ldr r3, [r7, #4] 8003c3c: 681b ldr r3, [r3, #0] 8003c3e: 685b ldr r3, [r3, #4] 8003c40: f023 013f bic.w r1, r3, #63 @ 0x3f 8003c44: 687b ldr r3, [r7, #4] 8003c46: 681b ldr r3, [r3, #0] 8003c48: 68ba ldr r2, [r7, #8] 8003c4a: 430a orrs r2, r1 8003c4c: 605a str r2, [r3, #4] /*---------------------------- I2Cx TRISE Configuration --------------------*/ /* Configure I2Cx: Rise Time */ MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 8003c4e: 687b ldr r3, [r7, #4] 8003c50: 681b ldr r3, [r3, #0] 8003c52: 6a1b ldr r3, [r3, #32] 8003c54: f023 013f bic.w r1, r3, #63 @ 0x3f 8003c58: 687b ldr r3, [r7, #4] 8003c5a: 685b ldr r3, [r3, #4] 8003c5c: 4a6a ldr r2, [pc, #424] @ (8003e08 ) 8003c5e: 4293 cmp r3, r2 8003c60: d802 bhi.n 8003c68 8003c62: 68bb ldr r3, [r7, #8] 8003c64: 3301 adds r3, #1 8003c66: e009 b.n 8003c7c 8003c68: 68bb ldr r3, [r7, #8] 8003c6a: f44f 7296 mov.w r2, #300 @ 0x12c 8003c6e: fb02 f303 mul.w r3, r2, r3 8003c72: 4a69 ldr r2, [pc, #420] @ (8003e18 ) 8003c74: fba2 2303 umull r2, r3, r2, r3 8003c78: 099b lsrs r3, r3, #6 8003c7a: 3301 adds r3, #1 8003c7c: 687a ldr r2, [r7, #4] 8003c7e: 6812 ldr r2, [r2, #0] 8003c80: 430b orrs r3, r1 8003c82: 6213 str r3, [r2, #32] /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 8003c84: 687b ldr r3, [r7, #4] 8003c86: 681b ldr r3, [r3, #0] 8003c88: 69db ldr r3, [r3, #28] 8003c8a: f423 424f bic.w r2, r3, #52992 @ 0xcf00 8003c8e: f022 02ff bic.w r2, r2, #255 @ 0xff 8003c92: 687b ldr r3, [r7, #4] 8003c94: 685b ldr r3, [r3, #4] 8003c96: 495c ldr r1, [pc, #368] @ (8003e08 ) 8003c98: 428b cmp r3, r1 8003c9a: d819 bhi.n 8003cd0 8003c9c: 68fb ldr r3, [r7, #12] 8003c9e: 1e59 subs r1, r3, #1 8003ca0: 687b ldr r3, [r7, #4] 8003ca2: 685b ldr r3, [r3, #4] 8003ca4: 005b lsls r3, r3, #1 8003ca6: fbb1 f3f3 udiv r3, r1, r3 8003caa: 1c59 adds r1, r3, #1 8003cac: f640 73fc movw r3, #4092 @ 0xffc 8003cb0: 400b ands r3, r1 8003cb2: 2b00 cmp r3, #0 8003cb4: d00a beq.n 8003ccc 8003cb6: 68fb ldr r3, [r7, #12] 8003cb8: 1e59 subs r1, r3, #1 8003cba: 687b ldr r3, [r7, #4] 8003cbc: 685b ldr r3, [r3, #4] 8003cbe: 005b lsls r3, r3, #1 8003cc0: fbb1 f3f3 udiv r3, r1, r3 8003cc4: 3301 adds r3, #1 8003cc6: f3c3 030b ubfx r3, r3, #0, #12 8003cca: e051 b.n 8003d70 8003ccc: 2304 movs r3, #4 8003cce: e04f b.n 8003d70 8003cd0: 687b ldr r3, [r7, #4] 8003cd2: 689b ldr r3, [r3, #8] 8003cd4: 2b00 cmp r3, #0 8003cd6: d111 bne.n 8003cfc 8003cd8: 68fb ldr r3, [r7, #12] 8003cda: 1e58 subs r0, r3, #1 8003cdc: 687b ldr r3, [r7, #4] 8003cde: 6859 ldr r1, [r3, #4] 8003ce0: 460b mov r3, r1 8003ce2: 005b lsls r3, r3, #1 8003ce4: 440b add r3, r1 8003ce6: fbb0 f3f3 udiv r3, r0, r3 8003cea: 3301 adds r3, #1 8003cec: f3c3 030b ubfx r3, r3, #0, #12 8003cf0: 2b00 cmp r3, #0 8003cf2: bf0c ite eq 8003cf4: 2301 moveq r3, #1 8003cf6: 2300 movne r3, #0 8003cf8: b2db uxtb r3, r3 8003cfa: e012 b.n 8003d22 8003cfc: 68fb ldr r3, [r7, #12] 8003cfe: 1e58 subs r0, r3, #1 8003d00: 687b ldr r3, [r7, #4] 8003d02: 6859 ldr r1, [r3, #4] 8003d04: 460b mov r3, r1 8003d06: 009b lsls r3, r3, #2 8003d08: 440b add r3, r1 8003d0a: 0099 lsls r1, r3, #2 8003d0c: 440b add r3, r1 8003d0e: fbb0 f3f3 udiv r3, r0, r3 8003d12: 3301 adds r3, #1 8003d14: f3c3 030b ubfx r3, r3, #0, #12 8003d18: 2b00 cmp r3, #0 8003d1a: bf0c ite eq 8003d1c: 2301 moveq r3, #1 8003d1e: 2300 movne r3, #0 8003d20: b2db uxtb r3, r3 8003d22: 2b00 cmp r3, #0 8003d24: d001 beq.n 8003d2a 8003d26: 2301 movs r3, #1 8003d28: e022 b.n 8003d70 8003d2a: 687b ldr r3, [r7, #4] 8003d2c: 689b ldr r3, [r3, #8] 8003d2e: 2b00 cmp r3, #0 8003d30: d10e bne.n 8003d50 8003d32: 68fb ldr r3, [r7, #12] 8003d34: 1e58 subs r0, r3, #1 8003d36: 687b ldr r3, [r7, #4] 8003d38: 6859 ldr r1, [r3, #4] 8003d3a: 460b mov r3, r1 8003d3c: 005b lsls r3, r3, #1 8003d3e: 440b add r3, r1 8003d40: fbb0 f3f3 udiv r3, r0, r3 8003d44: 3301 adds r3, #1 8003d46: f3c3 030b ubfx r3, r3, #0, #12 8003d4a: f443 4300 orr.w r3, r3, #32768 @ 0x8000 8003d4e: e00f b.n 8003d70 8003d50: 68fb ldr r3, [r7, #12] 8003d52: 1e58 subs r0, r3, #1 8003d54: 687b ldr r3, [r7, #4] 8003d56: 6859 ldr r1, [r3, #4] 8003d58: 460b mov r3, r1 8003d5a: 009b lsls r3, r3, #2 8003d5c: 440b add r3, r1 8003d5e: 0099 lsls r1, r3, #2 8003d60: 440b add r3, r1 8003d62: fbb0 f3f3 udiv r3, r0, r3 8003d66: 3301 adds r3, #1 8003d68: f3c3 030b ubfx r3, r3, #0, #12 8003d6c: f443 4340 orr.w r3, r3, #49152 @ 0xc000 8003d70: 6879 ldr r1, [r7, #4] 8003d72: 6809 ldr r1, [r1, #0] 8003d74: 4313 orrs r3, r2 8003d76: 61cb str r3, [r1, #28] /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 8003d78: 687b ldr r3, [r7, #4] 8003d7a: 681b ldr r3, [r3, #0] 8003d7c: 681b ldr r3, [r3, #0] 8003d7e: f023 01c0 bic.w r1, r3, #192 @ 0xc0 8003d82: 687b ldr r3, [r7, #4] 8003d84: 69da ldr r2, [r3, #28] 8003d86: 687b ldr r3, [r7, #4] 8003d88: 6a1b ldr r3, [r3, #32] 8003d8a: 431a orrs r2, r3 8003d8c: 687b ldr r3, [r7, #4] 8003d8e: 681b ldr r3, [r3, #0] 8003d90: 430a orrs r2, r1 8003d92: 601a str r2, [r3, #0] /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ /* Configure I2Cx: Own Address1 and addressing mode */ MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 8003d94: 687b ldr r3, [r7, #4] 8003d96: 681b ldr r3, [r3, #0] 8003d98: 689b ldr r3, [r3, #8] 8003d9a: f423 4303 bic.w r3, r3, #33536 @ 0x8300 8003d9e: f023 03ff bic.w r3, r3, #255 @ 0xff 8003da2: 687a ldr r2, [r7, #4] 8003da4: 6911 ldr r1, [r2, #16] 8003da6: 687a ldr r2, [r7, #4] 8003da8: 68d2 ldr r2, [r2, #12] 8003daa: 4311 orrs r1, r2 8003dac: 687a ldr r2, [r7, #4] 8003dae: 6812 ldr r2, [r2, #0] 8003db0: 430b orrs r3, r1 8003db2: 6093 str r3, [r2, #8] /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ /* Configure I2Cx: Dual mode and Own Address2 */ MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 8003db4: 687b ldr r3, [r7, #4] 8003db6: 681b ldr r3, [r3, #0] 8003db8: 68db ldr r3, [r3, #12] 8003dba: f023 01ff bic.w r1, r3, #255 @ 0xff 8003dbe: 687b ldr r3, [r7, #4] 8003dc0: 695a ldr r2, [r3, #20] 8003dc2: 687b ldr r3, [r7, #4] 8003dc4: 699b ldr r3, [r3, #24] 8003dc6: 431a orrs r2, r3 8003dc8: 687b ldr r3, [r7, #4] 8003dca: 681b ldr r3, [r3, #0] 8003dcc: 430a orrs r2, r1 8003dce: 60da str r2, [r3, #12] /* Enable the selected I2C peripheral */ __HAL_I2C_ENABLE(hi2c); 8003dd0: 687b ldr r3, [r7, #4] 8003dd2: 681b ldr r3, [r3, #0] 8003dd4: 681a ldr r2, [r3, #0] 8003dd6: 687b ldr r3, [r7, #4] 8003dd8: 681b ldr r3, [r3, #0] 8003dda: f042 0201 orr.w r2, r2, #1 8003dde: 601a str r2, [r3, #0] hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 8003de0: 687b ldr r3, [r7, #4] 8003de2: 2200 movs r2, #0 8003de4: 641a str r2, [r3, #64] @ 0x40 hi2c->State = HAL_I2C_STATE_READY; 8003de6: 687b ldr r3, [r7, #4] 8003de8: 2220 movs r2, #32 8003dea: f883 203d strb.w r2, [r3, #61] @ 0x3d hi2c->PreviousState = I2C_STATE_NONE; 8003dee: 687b ldr r3, [r7, #4] 8003df0: 2200 movs r2, #0 8003df2: 631a str r2, [r3, #48] @ 0x30 hi2c->Mode = HAL_I2C_MODE_NONE; 8003df4: 687b ldr r3, [r7, #4] 8003df6: 2200 movs r2, #0 8003df8: f883 203e strb.w r2, [r3, #62] @ 0x3e return HAL_OK; 8003dfc: 2300 movs r3, #0 } 8003dfe: 4618 mov r0, r3 8003e00: 3710 adds r7, #16 8003e02: 46bd mov sp, r7 8003e04: bd80 pop {r7, pc} 8003e06: bf00 nop 8003e08: 000186a0 .word 0x000186a0 8003e0c: 001e847f .word 0x001e847f 8003e10: 003d08ff .word 0x003d08ff 8003e14: 431bde83 .word 0x431bde83 8003e18: 10624dd3 .word 0x10624dd3 08003e1c : * the configuration information for the specified I2Cx peripheral. * @param AnalogFilter new state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { 8003e1c: b480 push {r7} 8003e1e: b083 sub sp, #12 8003e20: af00 add r7, sp, #0 8003e22: 6078 str r0, [r7, #4] 8003e24: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8003e26: 687b ldr r3, [r7, #4] 8003e28: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003e2c: b2db uxtb r3, r3 8003e2e: 2b20 cmp r3, #32 8003e30: d129 bne.n 8003e86 { hi2c->State = HAL_I2C_STATE_BUSY; 8003e32: 687b ldr r3, [r7, #4] 8003e34: 2224 movs r2, #36 @ 0x24 8003e36: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003e3a: 687b ldr r3, [r7, #4] 8003e3c: 681b ldr r3, [r3, #0] 8003e3e: 681a ldr r2, [r3, #0] 8003e40: 687b ldr r3, [r7, #4] 8003e42: 681b ldr r3, [r3, #0] 8003e44: f022 0201 bic.w r2, r2, #1 8003e48: 601a str r2, [r3, #0] /* Reset I2Cx ANOFF bit */ hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF); 8003e4a: 687b ldr r3, [r7, #4] 8003e4c: 681b ldr r3, [r3, #0] 8003e4e: 6a5a ldr r2, [r3, #36] @ 0x24 8003e50: 687b ldr r3, [r7, #4] 8003e52: 681b ldr r3, [r3, #0] 8003e54: f022 0210 bic.w r2, r2, #16 8003e58: 625a str r2, [r3, #36] @ 0x24 /* Disable the analog filter */ hi2c->Instance->FLTR |= AnalogFilter; 8003e5a: 687b ldr r3, [r7, #4] 8003e5c: 681b ldr r3, [r3, #0] 8003e5e: 6a59 ldr r1, [r3, #36] @ 0x24 8003e60: 687b ldr r3, [r7, #4] 8003e62: 681b ldr r3, [r3, #0] 8003e64: 683a ldr r2, [r7, #0] 8003e66: 430a orrs r2, r1 8003e68: 625a str r2, [r3, #36] @ 0x24 __HAL_I2C_ENABLE(hi2c); 8003e6a: 687b ldr r3, [r7, #4] 8003e6c: 681b ldr r3, [r3, #0] 8003e6e: 681a ldr r2, [r3, #0] 8003e70: 687b ldr r3, [r7, #4] 8003e72: 681b ldr r3, [r3, #0] 8003e74: f042 0201 orr.w r2, r2, #1 8003e78: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003e7a: 687b ldr r3, [r7, #4] 8003e7c: 2220 movs r2, #32 8003e7e: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8003e82: 2300 movs r3, #0 8003e84: e000 b.n 8003e88 } else { return HAL_BUSY; 8003e86: 2302 movs r3, #2 } } 8003e88: 4618 mov r0, r3 8003e8a: 370c adds r7, #12 8003e8c: 46bd mov sp, r7 8003e8e: f85d 7b04 ldr.w r7, [sp], #4 8003e92: 4770 bx lr 08003e94 : * the configuration information for the specified I2Cx peripheral. * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { 8003e94: b480 push {r7} 8003e96: b085 sub sp, #20 8003e98: af00 add r7, sp, #0 8003e9a: 6078 str r0, [r7, #4] 8003e9c: 6039 str r1, [r7, #0] uint16_t tmpreg = 0; 8003e9e: 2300 movs r3, #0 8003ea0: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); if (hi2c->State == HAL_I2C_STATE_READY) 8003ea2: 687b ldr r3, [r7, #4] 8003ea4: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 8003ea8: b2db uxtb r3, r3 8003eaa: 2b20 cmp r3, #32 8003eac: d12a bne.n 8003f04 { hi2c->State = HAL_I2C_STATE_BUSY; 8003eae: 687b ldr r3, [r7, #4] 8003eb0: 2224 movs r2, #36 @ 0x24 8003eb2: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Disable the selected I2C peripheral */ __HAL_I2C_DISABLE(hi2c); 8003eb6: 687b ldr r3, [r7, #4] 8003eb8: 681b ldr r3, [r3, #0] 8003eba: 681a ldr r2, [r3, #0] 8003ebc: 687b ldr r3, [r7, #4] 8003ebe: 681b ldr r3, [r3, #0] 8003ec0: f022 0201 bic.w r2, r2, #1 8003ec4: 601a str r2, [r3, #0] /* Get the old register value */ tmpreg = hi2c->Instance->FLTR; 8003ec6: 687b ldr r3, [r7, #4] 8003ec8: 681b ldr r3, [r3, #0] 8003eca: 6a5b ldr r3, [r3, #36] @ 0x24 8003ecc: 81fb strh r3, [r7, #14] /* Reset I2Cx DNF bit [3:0] */ tmpreg &= ~(I2C_FLTR_DNF); 8003ece: 89fb ldrh r3, [r7, #14] 8003ed0: f023 030f bic.w r3, r3, #15 8003ed4: 81fb strh r3, [r7, #14] /* Set I2Cx DNF coefficient */ tmpreg |= DigitalFilter; 8003ed6: 683b ldr r3, [r7, #0] 8003ed8: b29a uxth r2, r3 8003eda: 89fb ldrh r3, [r7, #14] 8003edc: 4313 orrs r3, r2 8003ede: 81fb strh r3, [r7, #14] /* Store the new register value */ hi2c->Instance->FLTR = tmpreg; 8003ee0: 687b ldr r3, [r7, #4] 8003ee2: 681b ldr r3, [r3, #0] 8003ee4: 89fa ldrh r2, [r7, #14] 8003ee6: 625a str r2, [r3, #36] @ 0x24 __HAL_I2C_ENABLE(hi2c); 8003ee8: 687b ldr r3, [r7, #4] 8003eea: 681b ldr r3, [r3, #0] 8003eec: 681a ldr r2, [r3, #0] 8003eee: 687b ldr r3, [r7, #4] 8003ef0: 681b ldr r3, [r3, #0] 8003ef2: f042 0201 orr.w r2, r2, #1 8003ef6: 601a str r2, [r3, #0] hi2c->State = HAL_I2C_STATE_READY; 8003ef8: 687b ldr r3, [r7, #4] 8003efa: 2220 movs r2, #32 8003efc: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8003f00: 2300 movs r3, #0 8003f02: e000 b.n 8003f06 } else { return HAL_BUSY; 8003f04: 2302 movs r3, #2 } } 8003f06: 4618 mov r0, r3 8003f08: 3714 adds r7, #20 8003f0a: 46bd mov sp, r7 8003f0c: f85d 7b04 ldr.w r7, [sp], #4 8003f10: 4770 bx lr 08003f12 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { 8003f12: b580 push {r7, lr} 8003f14: b084 sub sp, #16 8003f16: af00 add r7, sp, #0 8003f18: 6078 str r0, [r7, #4] uint32_t tmp; uint32_t tmp1; /* Check the LTDC peripheral state */ if (hltdc == NULL) 8003f1a: 687b ldr r3, [r7, #4] 8003f1c: 2b00 cmp r3, #0 8003f1e: d101 bne.n 8003f24 { return HAL_ERROR; 8003f20: 2301 movs r3, #1 8003f22: e08f b.n 8004044 } /* Init the low level hardware */ hltdc->MspInitCallback(hltdc); } #else if (hltdc->State == HAL_LTDC_STATE_RESET) 8003f24: 687b ldr r3, [r7, #4] 8003f26: f893 30a1 ldrb.w r3, [r3, #161] @ 0xa1 8003f2a: b2db uxtb r3, r3 8003f2c: 2b00 cmp r3, #0 8003f2e: d106 bne.n 8003f3e { /* Allocate lock resource and initialize it */ hltdc->Lock = HAL_UNLOCKED; 8003f30: 687b ldr r3, [r7, #4] 8003f32: 2200 movs r2, #0 8003f34: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 /* Init the low level hardware */ HAL_LTDC_MspInit(hltdc); 8003f38: 6878 ldr r0, [r7, #4] 8003f3a: f7fc ffdd bl 8000ef8 } #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; 8003f3e: 687b ldr r3, [r7, #4] 8003f40: 2202 movs r2, #2 8003f42: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Configure the HS, VS, DE and PC polarity */ hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); 8003f46: 687b ldr r3, [r7, #4] 8003f48: 681b ldr r3, [r3, #0] 8003f4a: 699a ldr r2, [r3, #24] 8003f4c: 687b ldr r3, [r7, #4] 8003f4e: 681b ldr r3, [r3, #0] 8003f50: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000 8003f54: 619a str r2, [r3, #24] hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003f56: 687b ldr r3, [r7, #4] 8003f58: 681b ldr r3, [r3, #0] 8003f5a: 6999 ldr r1, [r3, #24] 8003f5c: 687b ldr r3, [r7, #4] 8003f5e: 685a ldr r2, [r3, #4] 8003f60: 687b ldr r3, [r7, #4] 8003f62: 689b ldr r3, [r3, #8] 8003f64: 431a orrs r2, r3 hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); 8003f66: 687b ldr r3, [r7, #4] 8003f68: 68db ldr r3, [r3, #12] hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003f6a: 431a orrs r2, r3 hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); 8003f6c: 687b ldr r3, [r7, #4] 8003f6e: 691b ldr r3, [r3, #16] 8003f70: 431a orrs r2, r3 hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ 8003f72: 687b ldr r3, [r7, #4] 8003f74: 681b ldr r3, [r3, #0] 8003f76: 430a orrs r2, r1 8003f78: 619a str r2, [r3, #24] /* Set Synchronization size */ tmp = (hltdc->Init.HorizontalSync << 16U); 8003f7a: 687b ldr r3, [r7, #4] 8003f7c: 695b ldr r3, [r3, #20] 8003f7e: 041b lsls r3, r3, #16 8003f80: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync)); 8003f82: 687b ldr r3, [r7, #4] 8003f84: 6999 ldr r1, [r3, #24] 8003f86: 687b ldr r3, [r7, #4] 8003f88: 681b ldr r3, [r3, #0] 8003f8a: 68fa ldr r2, [r7, #12] 8003f8c: 430a orrs r2, r1 8003f8e: 609a str r2, [r3, #8] /* Set Accumulated Back porch */ tmp = (hltdc->Init.AccumulatedHBP << 16U); 8003f90: 687b ldr r3, [r7, #4] 8003f92: 69db ldr r3, [r3, #28] 8003f94: 041b lsls r3, r3, #16 8003f96: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP)); 8003f98: 687b ldr r3, [r7, #4] 8003f9a: 6a19 ldr r1, [r3, #32] 8003f9c: 687b ldr r3, [r7, #4] 8003f9e: 681b ldr r3, [r3, #0] 8003fa0: 68fa ldr r2, [r7, #12] 8003fa2: 430a orrs r2, r1 8003fa4: 60da str r2, [r3, #12] /* Set Accumulated Active Width */ tmp = (hltdc->Init.AccumulatedActiveW << 16U); 8003fa6: 687b ldr r3, [r7, #4] 8003fa8: 6a5b ldr r3, [r3, #36] @ 0x24 8003faa: 041b lsls r3, r3, #16 8003fac: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH)); 8003fae: 687b ldr r3, [r7, #4] 8003fb0: 6a99 ldr r1, [r3, #40] @ 0x28 8003fb2: 687b ldr r3, [r7, #4] 8003fb4: 681b ldr r3, [r3, #0] 8003fb6: 68fa ldr r2, [r7, #12] 8003fb8: 430a orrs r2, r1 8003fba: 611a str r2, [r3, #16] /* Set Total Width */ tmp = (hltdc->Init.TotalWidth << 16U); 8003fbc: 687b ldr r3, [r7, #4] 8003fbe: 6adb ldr r3, [r3, #44] @ 0x2c 8003fc0: 041b lsls r3, r3, #16 8003fc2: 60fb str r3, [r7, #12] WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh)); 8003fc4: 687b ldr r3, [r7, #4] 8003fc6: 6b19 ldr r1, [r3, #48] @ 0x30 8003fc8: 687b ldr r3, [r7, #4] 8003fca: 681b ldr r3, [r3, #0] 8003fcc: 68fa ldr r2, [r7, #12] 8003fce: 430a orrs r2, r1 8003fd0: 615a str r2, [r3, #20] /* Set the background color value */ tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); 8003fd2: 687b ldr r3, [r7, #4] 8003fd4: f893 3035 ldrb.w r3, [r3, #53] @ 0x35 8003fd8: 021b lsls r3, r3, #8 8003fda: 60fb str r3, [r7, #12] tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); 8003fdc: 687b ldr r3, [r7, #4] 8003fde: f893 3036 ldrb.w r3, [r3, #54] @ 0x36 8003fe2: 041b lsls r3, r3, #16 8003fe4: 60bb str r3, [r7, #8] hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); 8003fe6: 687b ldr r3, [r7, #4] 8003fe8: 681b ldr r3, [r3, #0] 8003fea: 6ada ldr r2, [r3, #44] @ 0x2c 8003fec: 687b ldr r3, [r7, #4] 8003fee: 681b ldr r3, [r3, #0] 8003ff0: f002 427f and.w r2, r2, #4278190080 @ 0xff000000 8003ff4: 62da str r2, [r3, #44] @ 0x2c hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); 8003ff6: 687b ldr r3, [r7, #4] 8003ff8: 681b ldr r3, [r3, #0] 8003ffa: 6ad9 ldr r1, [r3, #44] @ 0x2c 8003ffc: 68ba ldr r2, [r7, #8] 8003ffe: 68fb ldr r3, [r7, #12] 8004000: 4313 orrs r3, r2 8004002: 687a ldr r2, [r7, #4] 8004004: f892 2034 ldrb.w r2, [r2, #52] @ 0x34 8004008: 431a orrs r2, r3 800400a: 687b ldr r3, [r7, #4] 800400c: 681b ldr r3, [r3, #0] 800400e: 430a orrs r2, r1 8004010: 62da str r2, [r3, #44] @ 0x2c /* Enable the Transfer Error and FIFO underrun interrupts */ __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); 8004012: 687b ldr r3, [r7, #4] 8004014: 681b ldr r3, [r3, #0] 8004016: 6b5a ldr r2, [r3, #52] @ 0x34 8004018: 687b ldr r3, [r7, #4] 800401a: 681b ldr r3, [r3, #0] 800401c: f042 0206 orr.w r2, r2, #6 8004020: 635a str r2, [r3, #52] @ 0x34 /* Enable LTDC by setting LTDCEN bit */ __HAL_LTDC_ENABLE(hltdc); 8004022: 687b ldr r3, [r7, #4] 8004024: 681b ldr r3, [r3, #0] 8004026: 699a ldr r2, [r3, #24] 8004028: 687b ldr r3, [r7, #4] 800402a: 681b ldr r3, [r3, #0] 800402c: f042 0201 orr.w r2, r2, #1 8004030: 619a str r2, [r3, #24] /* Initialize the error code */ hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; 8004032: 687b ldr r3, [r7, #4] 8004034: 2200 movs r2, #0 8004036: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; 800403a: 687b ldr r3, [r7, #4] 800403c: 2201 movs r2, #1 800403e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 return HAL_OK; 8004042: 2300 movs r3, #0 } 8004044: 4618 mov r0, r3 8004046: 3710 adds r7, #16 8004048: 46bd mov sp, r7 800404a: bd80 pop {r7, pc} 0800404c : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval HAL status */ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) { 800404c: b580 push {r7, lr} 800404e: b084 sub sp, #16 8004050: af00 add r7, sp, #0 8004052: 6078 str r0, [r7, #4] uint32_t isrflags = READ_REG(hltdc->Instance->ISR); 8004054: 687b ldr r3, [r7, #4] 8004056: 681b ldr r3, [r3, #0] 8004058: 6b9b ldr r3, [r3, #56] @ 0x38 800405a: 60fb str r3, [r7, #12] uint32_t itsources = READ_REG(hltdc->Instance->IER); 800405c: 687b ldr r3, [r7, #4] 800405e: 681b ldr r3, [r3, #0] 8004060: 6b5b ldr r3, [r3, #52] @ 0x34 8004062: 60bb str r3, [r7, #8] /* Transfer Error Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) 8004064: 68fb ldr r3, [r7, #12] 8004066: f003 0304 and.w r3, r3, #4 800406a: 2b00 cmp r3, #0 800406c: d023 beq.n 80040b6 800406e: 68bb ldr r3, [r7, #8] 8004070: f003 0304 and.w r3, r3, #4 8004074: 2b00 cmp r3, #0 8004076: d01e beq.n 80040b6 { /* Disable the transfer Error interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); 8004078: 687b ldr r3, [r7, #4] 800407a: 681b ldr r3, [r3, #0] 800407c: 6b5a ldr r2, [r3, #52] @ 0x34 800407e: 687b ldr r3, [r7, #4] 8004080: 681b ldr r3, [r3, #0] 8004082: f022 0204 bic.w r2, r2, #4 8004086: 635a str r2, [r3, #52] @ 0x34 /* Clear the transfer error flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); 8004088: 687b ldr r3, [r7, #4] 800408a: 681b ldr r3, [r3, #0] 800408c: 2204 movs r2, #4 800408e: 63da str r2, [r3, #60] @ 0x3c /* Update error code */ hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; 8004090: 687b ldr r3, [r7, #4] 8004092: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 8004096: f043 0201 orr.w r2, r3, #1 800409a: 687b ldr r3, [r7, #4] 800409c: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_ERROR; 80040a0: 687b ldr r3, [r7, #4] 80040a2: 2204 movs r2, #4 80040a4: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 80040a8: 687b ldr r3, [r7, #4] 80040aa: 2200 movs r2, #0 80040ac: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ hltdc->ErrorCallback(hltdc); #else /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); 80040b0: 6878 ldr r0, [r7, #4] 80040b2: f000 f86f bl 8004194 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* FIFO underrun Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) 80040b6: 68fb ldr r3, [r7, #12] 80040b8: f003 0302 and.w r3, r3, #2 80040bc: 2b00 cmp r3, #0 80040be: d023 beq.n 8004108 80040c0: 68bb ldr r3, [r7, #8] 80040c2: f003 0302 and.w r3, r3, #2 80040c6: 2b00 cmp r3, #0 80040c8: d01e beq.n 8004108 { /* Disable the FIFO underrun interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); 80040ca: 687b ldr r3, [r7, #4] 80040cc: 681b ldr r3, [r3, #0] 80040ce: 6b5a ldr r2, [r3, #52] @ 0x34 80040d0: 687b ldr r3, [r7, #4] 80040d2: 681b ldr r3, [r3, #0] 80040d4: f022 0202 bic.w r2, r2, #2 80040d8: 635a str r2, [r3, #52] @ 0x34 /* Clear the FIFO underrun flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); 80040da: 687b ldr r3, [r7, #4] 80040dc: 681b ldr r3, [r3, #0] 80040de: 2202 movs r2, #2 80040e0: 63da str r2, [r3, #60] @ 0x3c /* Update error code */ hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; 80040e2: 687b ldr r3, [r7, #4] 80040e4: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4 80040e8: f043 0202 orr.w r2, r3, #2 80040ec: 687b ldr r3, [r7, #4] 80040ee: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4 /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_ERROR; 80040f2: 687b ldr r3, [r7, #4] 80040f4: 2204 movs r2, #4 80040f6: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 80040fa: 687b ldr r3, [r7, #4] 80040fc: 2200 movs r2, #0 80040fe: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ hltdc->ErrorCallback(hltdc); #else /* Call legacy error callback*/ HAL_LTDC_ErrorCallback(hltdc); 8004102: 6878 ldr r0, [r7, #4] 8004104: f000 f846 bl 8004194 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Line Interrupt management ************************************************/ if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) 8004108: 68fb ldr r3, [r7, #12] 800410a: f003 0301 and.w r3, r3, #1 800410e: 2b00 cmp r3, #0 8004110: d01b beq.n 800414a 8004112: 68bb ldr r3, [r7, #8] 8004114: f003 0301 and.w r3, r3, #1 8004118: 2b00 cmp r3, #0 800411a: d016 beq.n 800414a { /* Disable the Line interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); 800411c: 687b ldr r3, [r7, #4] 800411e: 681b ldr r3, [r3, #0] 8004120: 6b5a ldr r2, [r3, #52] @ 0x34 8004122: 687b ldr r3, [r7, #4] 8004124: 681b ldr r3, [r3, #0] 8004126: f022 0201 bic.w r2, r2, #1 800412a: 635a str r2, [r3, #52] @ 0x34 /* Clear the Line interrupt flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); 800412c: 687b ldr r3, [r7, #4] 800412e: 681b ldr r3, [r3, #0] 8004130: 2201 movs r2, #1 8004132: 63da str r2, [r3, #60] @ 0x3c /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; 8004134: 687b ldr r3, [r7, #4] 8004136: 2201 movs r2, #1 8004138: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 800413c: 687b ldr r3, [r7, #4] 800413e: 2200 movs r2, #0 8004140: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered Line Event callback */ hltdc->LineEventCallback(hltdc); #else /*Call Legacy Line Event callback */ HAL_LTDC_LineEventCallback(hltdc); 8004144: 6878 ldr r0, [r7, #4] 8004146: f000 f82f bl 80041a8 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } /* Register reload Interrupt management ***************************************/ if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) 800414a: 68fb ldr r3, [r7, #12] 800414c: f003 0308 and.w r3, r3, #8 8004150: 2b00 cmp r3, #0 8004152: d01b beq.n 800418c 8004154: 68bb ldr r3, [r7, #8] 8004156: f003 0308 and.w r3, r3, #8 800415a: 2b00 cmp r3, #0 800415c: d016 beq.n 800418c { /* Disable the register reload interrupt */ __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); 800415e: 687b ldr r3, [r7, #4] 8004160: 681b ldr r3, [r3, #0] 8004162: 6b5a ldr r2, [r3, #52] @ 0x34 8004164: 687b ldr r3, [r7, #4] 8004166: 681b ldr r3, [r3, #0] 8004168: f022 0208 bic.w r2, r2, #8 800416c: 635a str r2, [r3, #52] @ 0x34 /* Clear the register reload flag */ __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); 800416e: 687b ldr r3, [r7, #4] 8004170: 681b ldr r3, [r3, #0] 8004172: 2208 movs r2, #8 8004174: 63da str r2, [r3, #60] @ 0x3c /* Change LTDC state */ hltdc->State = HAL_LTDC_STATE_READY; 8004176: 687b ldr r3, [r7, #4] 8004178: 2201 movs r2, #1 800417a: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 800417e: 687b ldr r3, [r7, #4] 8004180: 2200 movs r2, #0 8004182: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) /*Call registered reload Event callback */ hltdc->ReloadEventCallback(hltdc); #else /*Call Legacy Reload Event callback */ HAL_LTDC_ReloadEventCallback(hltdc); 8004186: 6878 ldr r0, [r7, #4] 8004188: f000 f818 bl 80041bc #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ } } 800418c: bf00 nop 800418e: 3710 adds r7, #16 8004190: 46bd mov sp, r7 8004192: bd80 pop {r7, pc} 08004194 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) { 8004194: b480 push {r7} 8004196: b083 sub sp, #12 8004198: af00 add r7, sp, #0 800419a: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ErrorCallback could be implemented in the user file */ } 800419c: bf00 nop 800419e: 370c adds r7, #12 80041a0: 46bd mov sp, r7 80041a2: f85d 7b04 ldr.w r7, [sp], #4 80041a6: 4770 bx lr 080041a8 : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) { 80041a8: b480 push {r7} 80041aa: b083 sub sp, #12 80041ac: af00 add r7, sp, #0 80041ae: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_LineEventCallback could be implemented in the user file */ } 80041b0: bf00 nop 80041b2: 370c adds r7, #12 80041b4: 46bd mov sp, r7 80041b6: f85d 7b04 ldr.w r7, [sp], #4 80041ba: 4770 bx lr 080041bc : * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @retval None */ __weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) { 80041bc: b480 push {r7} 80041be: b083 sub sp, #12 80041c0: af00 add r7, sp, #0 80041c2: 6078 str r0, [r7, #4] UNUSED(hltdc); /* NOTE : This function should not be modified, when the callback is needed, the HAL_LTDC_ReloadEvenCallback could be implemented in the user file */ } 80041c4: bf00 nop 80041c6: 370c adds r7, #12 80041c8: 46bd mov sp, r7 80041ca: f85d 7b04 ldr.w r7, [sp], #4 80041ce: 4770 bx lr 080041d0 : * This parameter can be one of the following values: * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { 80041d0: b5b0 push {r4, r5, r7, lr} 80041d2: b084 sub sp, #16 80041d4: af00 add r7, sp, #0 80041d6: 60f8 str r0, [r7, #12] 80041d8: 60b9 str r1, [r7, #8] 80041da: 607a str r2, [r7, #4] assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); /* Process locked */ __HAL_LOCK(hltdc); 80041dc: 68fb ldr r3, [r7, #12] 80041de: f893 30a0 ldrb.w r3, [r3, #160] @ 0xa0 80041e2: 2b01 cmp r3, #1 80041e4: d101 bne.n 80041ea 80041e6: 2302 movs r3, #2 80041e8: e02c b.n 8004244 80041ea: 68fb ldr r3, [r7, #12] 80041ec: 2201 movs r2, #1 80041ee: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 /* Change LTDC peripheral state */ hltdc->State = HAL_LTDC_STATE_BUSY; 80041f2: 68fb ldr r3, [r7, #12] 80041f4: 2202 movs r2, #2 80041f6: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Copy new layer configuration into handle structure */ hltdc->LayerCfg[LayerIdx] = *pLayerCfg; 80041fa: 68fa ldr r2, [r7, #12] 80041fc: 687b ldr r3, [r7, #4] 80041fe: 2134 movs r1, #52 @ 0x34 8004200: fb01 f303 mul.w r3, r1, r3 8004204: 4413 add r3, r2 8004206: f103 0238 add.w r2, r3, #56 @ 0x38 800420a: 68bb ldr r3, [r7, #8] 800420c: 4614 mov r4, r2 800420e: 461d mov r5, r3 8004210: cd0f ldmia r5!, {r0, r1, r2, r3} 8004212: c40f stmia r4!, {r0, r1, r2, r3} 8004214: cd0f ldmia r5!, {r0, r1, r2, r3} 8004216: c40f stmia r4!, {r0, r1, r2, r3} 8004218: cd0f ldmia r5!, {r0, r1, r2, r3} 800421a: c40f stmia r4!, {r0, r1, r2, r3} 800421c: 682b ldr r3, [r5, #0] 800421e: 6023 str r3, [r4, #0] /* Configure the LTDC Layer */ LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); 8004220: 687a ldr r2, [r7, #4] 8004222: 68b9 ldr r1, [r7, #8] 8004224: 68f8 ldr r0, [r7, #12] 8004226: f000 f811 bl 800424c /* Set the Immediate Reload type */ hltdc->Instance->SRCR = LTDC_SRCR_IMR; 800422a: 68fb ldr r3, [r7, #12] 800422c: 681b ldr r3, [r3, #0] 800422e: 2201 movs r2, #1 8004230: 625a str r2, [r3, #36] @ 0x24 /* Initialize the LTDC state*/ hltdc->State = HAL_LTDC_STATE_READY; 8004232: 68fb ldr r3, [r7, #12] 8004234: 2201 movs r2, #1 8004236: f883 20a1 strb.w r2, [r3, #161] @ 0xa1 /* Process unlocked */ __HAL_UNLOCK(hltdc); 800423a: 68fb ldr r3, [r7, #12] 800423c: 2200 movs r2, #0 800423e: f883 20a0 strb.w r2, [r3, #160] @ 0xa0 return HAL_OK; 8004242: 2300 movs r3, #0 } 8004244: 4618 mov r0, r3 8004246: 3710 adds r7, #16 8004248: 46bd mov sp, r7 800424a: bdb0 pop {r4, r5, r7, pc} 0800424c : * @param LayerIdx LTDC Layer index. * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval None */ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) { 800424c: b480 push {r7} 800424e: b089 sub sp, #36 @ 0x24 8004250: af00 add r7, sp, #0 8004252: 60f8 str r0, [r7, #12] 8004254: 60b9 str r1, [r7, #8] 8004256: 607a str r2, [r7, #4] uint32_t tmp; uint32_t tmp1; uint32_t tmp2; /* Configure the horizontal start and stop position */ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); 8004258: 68bb ldr r3, [r7, #8] 800425a: 685a ldr r2, [r3, #4] 800425c: 68fb ldr r3, [r7, #12] 800425e: 681b ldr r3, [r3, #0] 8004260: 68db ldr r3, [r3, #12] 8004262: 0c1b lsrs r3, r3, #16 8004264: f3c3 030b ubfx r3, r3, #0, #12 8004268: 4413 add r3, r2 800426a: 041b lsls r3, r3, #16 800426c: 61fb str r3, [r7, #28] LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); 800426e: 68fb ldr r3, [r7, #12] 8004270: 681b ldr r3, [r3, #0] 8004272: 461a mov r2, r3 8004274: 687b ldr r3, [r7, #4] 8004276: 01db lsls r3, r3, #7 8004278: 4413 add r3, r2 800427a: 3384 adds r3, #132 @ 0x84 800427c: 685b ldr r3, [r3, #4] 800427e: 68fa ldr r2, [r7, #12] 8004280: 6812 ldr r2, [r2, #0] 8004282: 4611 mov r1, r2 8004284: 687a ldr r2, [r7, #4] 8004286: 01d2 lsls r2, r2, #7 8004288: 440a add r2, r1 800428a: 3284 adds r2, #132 @ 0x84 800428c: f403 4370 and.w r3, r3, #61440 @ 0xf000 8004290: 6053 str r3, [r2, #4] LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 8004292: 68bb ldr r3, [r7, #8] 8004294: 681a ldr r2, [r3, #0] ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 8004296: 68fb ldr r3, [r7, #12] 8004298: 681b ldr r3, [r3, #0] 800429a: 68db ldr r3, [r3, #12] 800429c: 0c1b lsrs r3, r3, #16 800429e: f3c3 030b ubfx r3, r3, #0, #12 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042a2: 4413 add r3, r2 ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 80042a4: 1c5a adds r2, r3, #1 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042a6: 68fb ldr r3, [r7, #12] 80042a8: 681b ldr r3, [r3, #0] 80042aa: 4619 mov r1, r3 80042ac: 687b ldr r3, [r7, #4] 80042ae: 01db lsls r3, r3, #7 80042b0: 440b add r3, r1 80042b2: 3384 adds r3, #132 @ 0x84 80042b4: 4619 mov r1, r3 ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); 80042b6: 69fb ldr r3, [r7, #28] 80042b8: 4313 orrs r3, r2 LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ 80042ba: 604b str r3, [r1, #4] /* Configure the vertical start and stop position */ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); 80042bc: 68bb ldr r3, [r7, #8] 80042be: 68da ldr r2, [r3, #12] 80042c0: 68fb ldr r3, [r7, #12] 80042c2: 681b ldr r3, [r3, #0] 80042c4: 68db ldr r3, [r3, #12] 80042c6: f3c3 030a ubfx r3, r3, #0, #11 80042ca: 4413 add r3, r2 80042cc: 041b lsls r3, r3, #16 80042ce: 61fb str r3, [r7, #28] LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); 80042d0: 68fb ldr r3, [r7, #12] 80042d2: 681b ldr r3, [r3, #0] 80042d4: 461a mov r2, r3 80042d6: 687b ldr r3, [r7, #4] 80042d8: 01db lsls r3, r3, #7 80042da: 4413 add r3, r2 80042dc: 3384 adds r3, #132 @ 0x84 80042de: 689b ldr r3, [r3, #8] 80042e0: 68fa ldr r2, [r7, #12] 80042e2: 6812 ldr r2, [r2, #0] 80042e4: 4611 mov r1, r2 80042e6: 687a ldr r2, [r7, #4] 80042e8: 01d2 lsls r2, r2, #7 80042ea: 440a add r2, r1 80042ec: 3284 adds r2, #132 @ 0x84 80042ee: f403 4370 and.w r3, r3, #61440 @ 0xf000 80042f2: 6093 str r3, [r2, #8] LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); 80042f4: 68bb ldr r3, [r7, #8] 80042f6: 689a ldr r2, [r3, #8] 80042f8: 68fb ldr r3, [r7, #12] 80042fa: 681b ldr r3, [r3, #0] 80042fc: 68db ldr r3, [r3, #12] 80042fe: f3c3 030a ubfx r3, r3, #0, #11 8004302: 4413 add r3, r2 8004304: 1c5a adds r2, r3, #1 8004306: 68fb ldr r3, [r7, #12] 8004308: 681b ldr r3, [r3, #0] 800430a: 4619 mov r1, r3 800430c: 687b ldr r3, [r7, #4] 800430e: 01db lsls r3, r3, #7 8004310: 440b add r3, r1 8004312: 3384 adds r3, #132 @ 0x84 8004314: 4619 mov r1, r3 8004316: 69fb ldr r3, [r7, #28] 8004318: 4313 orrs r3, r2 800431a: 608b str r3, [r1, #8] /* Specifies the pixel format */ LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); 800431c: 68fb ldr r3, [r7, #12] 800431e: 681b ldr r3, [r3, #0] 8004320: 461a mov r2, r3 8004322: 687b ldr r3, [r7, #4] 8004324: 01db lsls r3, r3, #7 8004326: 4413 add r3, r2 8004328: 3384 adds r3, #132 @ 0x84 800432a: 691b ldr r3, [r3, #16] 800432c: 68fa ldr r2, [r7, #12] 800432e: 6812 ldr r2, [r2, #0] 8004330: 4611 mov r1, r2 8004332: 687a ldr r2, [r7, #4] 8004334: 01d2 lsls r2, r2, #7 8004336: 440a add r2, r1 8004338: 3284 adds r2, #132 @ 0x84 800433a: f023 0307 bic.w r3, r3, #7 800433e: 6113 str r3, [r2, #16] LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); 8004340: 68fb ldr r3, [r7, #12] 8004342: 681b ldr r3, [r3, #0] 8004344: 461a mov r2, r3 8004346: 687b ldr r3, [r7, #4] 8004348: 01db lsls r3, r3, #7 800434a: 4413 add r3, r2 800434c: 3384 adds r3, #132 @ 0x84 800434e: 461a mov r2, r3 8004350: 68bb ldr r3, [r7, #8] 8004352: 691b ldr r3, [r3, #16] 8004354: 6113 str r3, [r2, #16] /* Configure the default color values */ tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); 8004356: 68bb ldr r3, [r7, #8] 8004358: f893 3031 ldrb.w r3, [r3, #49] @ 0x31 800435c: 021b lsls r3, r3, #8 800435e: 61fb str r3, [r7, #28] tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); 8004360: 68bb ldr r3, [r7, #8] 8004362: f893 3032 ldrb.w r3, [r3, #50] @ 0x32 8004366: 041b lsls r3, r3, #16 8004368: 61bb str r3, [r7, #24] tmp2 = (pLayerCfg->Alpha0 << 24U); 800436a: 68bb ldr r3, [r7, #8] 800436c: 699b ldr r3, [r3, #24] 800436e: 061b lsls r3, r3, #24 8004370: 617b str r3, [r7, #20] WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2)); 8004372: 68bb ldr r3, [r7, #8] 8004374: f893 3030 ldrb.w r3, [r3, #48] @ 0x30 8004378: 461a mov r2, r3 800437a: 69fb ldr r3, [r7, #28] 800437c: 431a orrs r2, r3 800437e: 69bb ldr r3, [r7, #24] 8004380: 431a orrs r2, r3 8004382: 68fb ldr r3, [r7, #12] 8004384: 681b ldr r3, [r3, #0] 8004386: 4619 mov r1, r3 8004388: 687b ldr r3, [r7, #4] 800438a: 01db lsls r3, r3, #7 800438c: 440b add r3, r1 800438e: 3384 adds r3, #132 @ 0x84 8004390: 4619 mov r1, r3 8004392: 697b ldr r3, [r7, #20] 8004394: 4313 orrs r3, r2 8004396: 618b str r3, [r1, #24] /* Specifies the constant alpha value */ LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); 8004398: 68fb ldr r3, [r7, #12] 800439a: 681b ldr r3, [r3, #0] 800439c: 461a mov r2, r3 800439e: 687b ldr r3, [r7, #4] 80043a0: 01db lsls r3, r3, #7 80043a2: 4413 add r3, r2 80043a4: 3384 adds r3, #132 @ 0x84 80043a6: 695b ldr r3, [r3, #20] 80043a8: 68fa ldr r2, [r7, #12] 80043aa: 6812 ldr r2, [r2, #0] 80043ac: 4611 mov r1, r2 80043ae: 687a ldr r2, [r7, #4] 80043b0: 01d2 lsls r2, r2, #7 80043b2: 440a add r2, r1 80043b4: 3284 adds r2, #132 @ 0x84 80043b6: f023 03ff bic.w r3, r3, #255 @ 0xff 80043ba: 6153 str r3, [r2, #20] LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); 80043bc: 68fb ldr r3, [r7, #12] 80043be: 681b ldr r3, [r3, #0] 80043c0: 461a mov r2, r3 80043c2: 687b ldr r3, [r7, #4] 80043c4: 01db lsls r3, r3, #7 80043c6: 4413 add r3, r2 80043c8: 3384 adds r3, #132 @ 0x84 80043ca: 461a mov r2, r3 80043cc: 68bb ldr r3, [r7, #8] 80043ce: 695b ldr r3, [r3, #20] 80043d0: 6153 str r3, [r2, #20] /* Specifies the blending factors */ LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); 80043d2: 68fb ldr r3, [r7, #12] 80043d4: 681b ldr r3, [r3, #0] 80043d6: 461a mov r2, r3 80043d8: 687b ldr r3, [r7, #4] 80043da: 01db lsls r3, r3, #7 80043dc: 4413 add r3, r2 80043de: 3384 adds r3, #132 @ 0x84 80043e0: 69db ldr r3, [r3, #28] 80043e2: 68fa ldr r2, [r7, #12] 80043e4: 6812 ldr r2, [r2, #0] 80043e6: 4611 mov r1, r2 80043e8: 687a ldr r2, [r7, #4] 80043ea: 01d2 lsls r2, r2, #7 80043ec: 440a add r2, r1 80043ee: 3284 adds r2, #132 @ 0x84 80043f0: f423 63e0 bic.w r3, r3, #1792 @ 0x700 80043f4: f023 0307 bic.w r3, r3, #7 80043f8: 61d3 str r3, [r2, #28] LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); 80043fa: 68bb ldr r3, [r7, #8] 80043fc: 69da ldr r2, [r3, #28] 80043fe: 68bb ldr r3, [r7, #8] 8004400: 6a1b ldr r3, [r3, #32] 8004402: 68f9 ldr r1, [r7, #12] 8004404: 6809 ldr r1, [r1, #0] 8004406: 4608 mov r0, r1 8004408: 6879 ldr r1, [r7, #4] 800440a: 01c9 lsls r1, r1, #7 800440c: 4401 add r1, r0 800440e: 3184 adds r1, #132 @ 0x84 8004410: 4313 orrs r3, r2 8004412: 61cb str r3, [r1, #28] /* Configure the color frame buffer start address */ WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress); 8004414: 68fb ldr r3, [r7, #12] 8004416: 681b ldr r3, [r3, #0] 8004418: 461a mov r2, r3 800441a: 687b ldr r3, [r7, #4] 800441c: 01db lsls r3, r3, #7 800441e: 4413 add r3, r2 8004420: 3384 adds r3, #132 @ 0x84 8004422: 461a mov r2, r3 8004424: 68bb ldr r3, [r7, #8] 8004426: 6a5b ldr r3, [r3, #36] @ 0x24 8004428: 6293 str r3, [r2, #40] @ 0x28 if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) 800442a: 68bb ldr r3, [r7, #8] 800442c: 691b ldr r3, [r3, #16] 800442e: 2b00 cmp r3, #0 8004430: d102 bne.n 8004438 { tmp = 4U; 8004432: 2304 movs r3, #4 8004434: 61fb str r3, [r7, #28] 8004436: e01b b.n 8004470 } else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) 8004438: 68bb ldr r3, [r7, #8] 800443a: 691b ldr r3, [r3, #16] 800443c: 2b01 cmp r3, #1 800443e: d102 bne.n 8004446 { tmp = 3U; 8004440: 2303 movs r3, #3 8004442: 61fb str r3, [r7, #28] 8004444: e014 b.n 8004470 } else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ 8004446: 68bb ldr r3, [r7, #8] 8004448: 691b ldr r3, [r3, #16] 800444a: 2b04 cmp r3, #4 800444c: d00b beq.n 8004466 (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ 800444e: 68bb ldr r3, [r7, #8] 8004450: 691b ldr r3, [r3, #16] else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ 8004452: 2b02 cmp r3, #2 8004454: d007 beq.n 8004466 (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ 8004456: 68bb ldr r3, [r7, #8] 8004458: 691b ldr r3, [r3, #16] (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ 800445a: 2b03 cmp r3, #3 800445c: d003 beq.n 8004466 (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) 800445e: 68bb ldr r3, [r7, #8] 8004460: 691b ldr r3, [r3, #16] (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ 8004462: 2b07 cmp r3, #7 8004464: d102 bne.n 800446c { tmp = 2U; 8004466: 2302 movs r3, #2 8004468: 61fb str r3, [r7, #28] 800446a: e001 b.n 8004470 } else { tmp = 1U; 800446c: 2301 movs r3, #1 800446e: 61fb str r3, [r7, #28] } /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); 8004470: 68fb ldr r3, [r7, #12] 8004472: 681b ldr r3, [r3, #0] 8004474: 461a mov r2, r3 8004476: 687b ldr r3, [r7, #4] 8004478: 01db lsls r3, r3, #7 800447a: 4413 add r3, r2 800447c: 3384 adds r3, #132 @ 0x84 800447e: 6adb ldr r3, [r3, #44] @ 0x2c 8004480: 68fa ldr r2, [r7, #12] 8004482: 6812 ldr r2, [r2, #0] 8004484: 4611 mov r1, r2 8004486: 687a ldr r2, [r7, #4] 8004488: 01d2 lsls r2, r2, #7 800448a: 440a add r2, r1 800448c: 3284 adds r2, #132 @ 0x84 800448e: f003 23e0 and.w r3, r3, #3758153728 @ 0xe000e000 8004492: 62d3 str r3, [r2, #44] @ 0x2c LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ 8004494: 68bb ldr r3, [r7, #8] 8004496: 6a9b ldr r3, [r3, #40] @ 0x28 8004498: 69fa ldr r2, [r7, #28] 800449a: fb02 f303 mul.w r3, r2, r3 800449e: 041a lsls r2, r3, #16 (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); 80044a0: 68bb ldr r3, [r7, #8] 80044a2: 6859 ldr r1, [r3, #4] 80044a4: 68bb ldr r3, [r7, #8] 80044a6: 681b ldr r3, [r3, #0] 80044a8: 1acb subs r3, r1, r3 80044aa: 69f9 ldr r1, [r7, #28] 80044ac: fb01 f303 mul.w r3, r1, r3 80044b0: 3303 adds r3, #3 LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ 80044b2: 68f9 ldr r1, [r7, #12] 80044b4: 6809 ldr r1, [r1, #0] 80044b6: 4608 mov r0, r1 80044b8: 6879 ldr r1, [r7, #4] 80044ba: 01c9 lsls r1, r1, #7 80044bc: 4401 add r1, r0 80044be: 3184 adds r1, #132 @ 0x84 80044c0: 4313 orrs r3, r2 80044c2: 62cb str r3, [r1, #44] @ 0x2c /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); 80044c4: 68fb ldr r3, [r7, #12] 80044c6: 681b ldr r3, [r3, #0] 80044c8: 461a mov r2, r3 80044ca: 687b ldr r3, [r7, #4] 80044cc: 01db lsls r3, r3, #7 80044ce: 4413 add r3, r2 80044d0: 3384 adds r3, #132 @ 0x84 80044d2: 6b1b ldr r3, [r3, #48] @ 0x30 80044d4: 68fa ldr r2, [r7, #12] 80044d6: 6812 ldr r2, [r2, #0] 80044d8: 4611 mov r1, r2 80044da: 687a ldr r2, [r7, #4] 80044dc: 01d2 lsls r2, r2, #7 80044de: 440a add r2, r1 80044e0: 3284 adds r2, #132 @ 0x84 80044e2: f423 63ff bic.w r3, r3, #2040 @ 0x7f8 80044e6: f023 0307 bic.w r3, r3, #7 80044ea: 6313 str r3, [r2, #48] @ 0x30 LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); 80044ec: 68fb ldr r3, [r7, #12] 80044ee: 681b ldr r3, [r3, #0] 80044f0: 461a mov r2, r3 80044f2: 687b ldr r3, [r7, #4] 80044f4: 01db lsls r3, r3, #7 80044f6: 4413 add r3, r2 80044f8: 3384 adds r3, #132 @ 0x84 80044fa: 461a mov r2, r3 80044fc: 68bb ldr r3, [r7, #8] 80044fe: 6adb ldr r3, [r3, #44] @ 0x2c 8004500: 6313 str r3, [r2, #48] @ 0x30 /* Enable LTDC_Layer by setting LEN bit */ LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; 8004502: 68fb ldr r3, [r7, #12] 8004504: 681b ldr r3, [r3, #0] 8004506: 461a mov r2, r3 8004508: 687b ldr r3, [r7, #4] 800450a: 01db lsls r3, r3, #7 800450c: 4413 add r3, r2 800450e: 3384 adds r3, #132 @ 0x84 8004510: 681b ldr r3, [r3, #0] 8004512: 68fa ldr r2, [r7, #12] 8004514: 6812 ldr r2, [r2, #0] 8004516: 4611 mov r1, r2 8004518: 687a ldr r2, [r7, #4] 800451a: 01d2 lsls r2, r2, #7 800451c: 440a add r2, r1 800451e: 3284 adds r2, #132 @ 0x84 8004520: f043 0301 orr.w r3, r3, #1 8004524: 6013 str r3, [r2, #0] } 8004526: bf00 nop 8004528: 3724 adds r7, #36 @ 0x24 800452a: 46bd mov sp, r7 800452c: f85d 7b04 ldr.w r7, [sp], #4 8004530: 4770 bx lr ... 08004534 : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004534: b580 push {r7, lr} 8004536: b086 sub sp, #24 8004538: af00 add r7, sp, #0 800453a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t pll_config; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 800453c: 687b ldr r3, [r7, #4] 800453e: 2b00 cmp r3, #0 8004540: d101 bne.n 8004546 { return HAL_ERROR; 8004542: 2301 movs r3, #1 8004544: e267 b.n 8004a16 } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004546: 687b ldr r3, [r7, #4] 8004548: 681b ldr r3, [r3, #0] 800454a: f003 0301 and.w r3, r3, #1 800454e: 2b00 cmp r3, #0 8004550: d075 beq.n 800463e { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 8004552: 4b88 ldr r3, [pc, #544] @ (8004774 ) 8004554: 689b ldr r3, [r3, #8] 8004556: f003 030c and.w r3, r3, #12 800455a: 2b04 cmp r3, #4 800455c: d00c beq.n 8004578 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800455e: 4b85 ldr r3, [pc, #532] @ (8004774 ) 8004560: 689b ldr r3, [r3, #8] 8004562: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \ 8004566: 2b08 cmp r3, #8 8004568: d112 bne.n 8004590 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) 800456a: 4b82 ldr r3, [pc, #520] @ (8004774 ) 800456c: 685b ldr r3, [r3, #4] 800456e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004572: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000 8004576: d10b bne.n 8004590 { if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8004578: 4b7e ldr r3, [pc, #504] @ (8004774 ) 800457a: 681b ldr r3, [r3, #0] 800457c: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004580: 2b00 cmp r3, #0 8004582: d05b beq.n 800463c 8004584: 687b ldr r3, [r7, #4] 8004586: 685b ldr r3, [r3, #4] 8004588: 2b00 cmp r3, #0 800458a: d157 bne.n 800463c { return HAL_ERROR; 800458c: 2301 movs r3, #1 800458e: e242 b.n 8004a16 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004590: 687b ldr r3, [r7, #4] 8004592: 685b ldr r3, [r3, #4] 8004594: f5b3 3f80 cmp.w r3, #65536 @ 0x10000 8004598: d106 bne.n 80045a8 800459a: 4b76 ldr r3, [pc, #472] @ (8004774 ) 800459c: 681b ldr r3, [r3, #0] 800459e: 4a75 ldr r2, [pc, #468] @ (8004774 ) 80045a0: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80045a4: 6013 str r3, [r2, #0] 80045a6: e01d b.n 80045e4 80045a8: 687b ldr r3, [r7, #4] 80045aa: 685b ldr r3, [r3, #4] 80045ac: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000 80045b0: d10c bne.n 80045cc 80045b2: 4b70 ldr r3, [pc, #448] @ (8004774 ) 80045b4: 681b ldr r3, [r3, #0] 80045b6: 4a6f ldr r2, [pc, #444] @ (8004774 ) 80045b8: f443 2380 orr.w r3, r3, #262144 @ 0x40000 80045bc: 6013 str r3, [r2, #0] 80045be: 4b6d ldr r3, [pc, #436] @ (8004774 ) 80045c0: 681b ldr r3, [r3, #0] 80045c2: 4a6c ldr r2, [pc, #432] @ (8004774 ) 80045c4: f443 3380 orr.w r3, r3, #65536 @ 0x10000 80045c8: 6013 str r3, [r2, #0] 80045ca: e00b b.n 80045e4 80045cc: 4b69 ldr r3, [pc, #420] @ (8004774 ) 80045ce: 681b ldr r3, [r3, #0] 80045d0: 4a68 ldr r2, [pc, #416] @ (8004774 ) 80045d2: f423 3380 bic.w r3, r3, #65536 @ 0x10000 80045d6: 6013 str r3, [r2, #0] 80045d8: 4b66 ldr r3, [pc, #408] @ (8004774 ) 80045da: 681b ldr r3, [r3, #0] 80045dc: 4a65 ldr r2, [pc, #404] @ (8004774 ) 80045de: f423 2380 bic.w r3, r3, #262144 @ 0x40000 80045e2: 6013 str r3, [r2, #0] /* Check the HSE State */ if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) 80045e4: 687b ldr r3, [r7, #4] 80045e6: 685b ldr r3, [r3, #4] 80045e8: 2b00 cmp r3, #0 80045ea: d013 beq.n 8004614 { /* Get Start Tick */ tickstart = HAL_GetTick(); 80045ec: f7fd f834 bl 8001658 80045f0: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 80045f2: e008 b.n 8004606 { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 80045f4: f7fd f830 bl 8001658 80045f8: 4602 mov r2, r0 80045fa: 693b ldr r3, [r7, #16] 80045fc: 1ad3 subs r3, r2, r3 80045fe: 2b64 cmp r3, #100 @ 0x64 8004600: d901 bls.n 8004606 { return HAL_TIMEOUT; 8004602: 2303 movs r3, #3 8004604: e207 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004606: 4b5b ldr r3, [pc, #364] @ (8004774 ) 8004608: 681b ldr r3, [r3, #0] 800460a: f403 3300 and.w r3, r3, #131072 @ 0x20000 800460e: 2b00 cmp r3, #0 8004610: d0f0 beq.n 80045f4 8004612: e014 b.n 800463e } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 8004614: f7fd f820 bl 8001658 8004618: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800461a: e008 b.n 800462e { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 800461c: f7fd f81c bl 8001658 8004620: 4602 mov r2, r0 8004622: 693b ldr r3, [r7, #16] 8004624: 1ad3 subs r3, r2, r3 8004626: 2b64 cmp r3, #100 @ 0x64 8004628: d901 bls.n 800462e { return HAL_TIMEOUT; 800462a: 2303 movs r3, #3 800462c: e1f3 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) 800462e: 4b51 ldr r3, [pc, #324] @ (8004774 ) 8004630: 681b ldr r3, [r3, #0] 8004632: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004636: 2b00 cmp r3, #0 8004638: d1f0 bne.n 800461c 800463a: e000 b.n 800463e if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 800463c: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 800463e: 687b ldr r3, [r7, #4] 8004640: 681b ldr r3, [r3, #0] 8004642: f003 0302 and.w r3, r3, #2 8004646: 2b00 cmp r3, #0 8004648: d063 beq.n 8004712 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 800464a: 4b4a ldr r3, [pc, #296] @ (8004774 ) 800464c: 689b ldr r3, [r3, #8] 800464e: f003 030c and.w r3, r3, #12 8004652: 2b00 cmp r3, #0 8004654: d00b beq.n 800466e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004656: 4b47 ldr r3, [pc, #284] @ (8004774 ) 8004658: 689b ldr r3, [r3, #8] 800465a: f003 030c and.w r3, r3, #12 if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \ 800465e: 2b08 cmp r3, #8 8004660: d11c bne.n 800469c ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) 8004662: 4b44 ldr r3, [pc, #272] @ (8004774 ) 8004664: 685b ldr r3, [r3, #4] 8004666: f403 0380 and.w r3, r3, #4194304 @ 0x400000 800466a: 2b00 cmp r3, #0 800466c: d116 bne.n 800469c { /* When HSI is used as system clock it will not disabled */ if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800466e: 4b41 ldr r3, [pc, #260] @ (8004774 ) 8004670: 681b ldr r3, [r3, #0] 8004672: f003 0302 and.w r3, r3, #2 8004676: 2b00 cmp r3, #0 8004678: d005 beq.n 8004686 800467a: 687b ldr r3, [r7, #4] 800467c: 68db ldr r3, [r3, #12] 800467e: 2b01 cmp r3, #1 8004680: d001 beq.n 8004686 { return HAL_ERROR; 8004682: 2301 movs r3, #1 8004684: e1c7 b.n 8004a16 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004686: 4b3b ldr r3, [pc, #236] @ (8004774 ) 8004688: 681b ldr r3, [r3, #0] 800468a: f023 02f8 bic.w r2, r3, #248 @ 0xf8 800468e: 687b ldr r3, [r7, #4] 8004690: 691b ldr r3, [r3, #16] 8004692: 00db lsls r3, r3, #3 8004694: 4937 ldr r1, [pc, #220] @ (8004774 ) 8004696: 4313 orrs r3, r2 8004698: 600b str r3, [r1, #0] if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) 800469a: e03a b.n 8004712 } } else { /* Check the HSI State */ if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) 800469c: 687b ldr r3, [r7, #4] 800469e: 68db ldr r3, [r3, #12] 80046a0: 2b00 cmp r3, #0 80046a2: d020 beq.n 80046e6 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 80046a4: 4b34 ldr r3, [pc, #208] @ (8004778 ) 80046a6: 2201 movs r2, #1 80046a8: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80046aa: f7fc ffd5 bl 8001658 80046ae: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80046b0: e008 b.n 80046c4 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80046b2: f7fc ffd1 bl 8001658 80046b6: 4602 mov r2, r0 80046b8: 693b ldr r3, [r7, #16] 80046ba: 1ad3 subs r3, r2, r3 80046bc: 2b02 cmp r3, #2 80046be: d901 bls.n 80046c4 { return HAL_TIMEOUT; 80046c0: 2303 movs r3, #3 80046c2: e1a8 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 80046c4: 4b2b ldr r3, [pc, #172] @ (8004774 ) 80046c6: 681b ldr r3, [r3, #0] 80046c8: f003 0302 and.w r3, r3, #2 80046cc: 2b00 cmp r3, #0 80046ce: d0f0 beq.n 80046b2 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 80046d0: 4b28 ldr r3, [pc, #160] @ (8004774 ) 80046d2: 681b ldr r3, [r3, #0] 80046d4: f023 02f8 bic.w r2, r3, #248 @ 0xf8 80046d8: 687b ldr r3, [r7, #4] 80046da: 691b ldr r3, [r3, #16] 80046dc: 00db lsls r3, r3, #3 80046de: 4925 ldr r1, [pc, #148] @ (8004774 ) 80046e0: 4313 orrs r3, r2 80046e2: 600b str r3, [r1, #0] 80046e4: e015 b.n 8004712 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 80046e6: 4b24 ldr r3, [pc, #144] @ (8004778 ) 80046e8: 2200 movs r2, #0 80046ea: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 80046ec: f7fc ffb4 bl 8001658 80046f0: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 80046f2: e008 b.n 8004706 { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 80046f4: f7fc ffb0 bl 8001658 80046f8: 4602 mov r2, r0 80046fa: 693b ldr r3, [r7, #16] 80046fc: 1ad3 subs r3, r2, r3 80046fe: 2b02 cmp r3, #2 8004700: d901 bls.n 8004706 { return HAL_TIMEOUT; 8004702: 2303 movs r3, #3 8004704: e187 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) 8004706: 4b1b ldr r3, [pc, #108] @ (8004774 ) 8004708: 681b ldr r3, [r3, #0] 800470a: f003 0302 and.w r3, r3, #2 800470e: 2b00 cmp r3, #0 8004710: d1f0 bne.n 80046f4 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004712: 687b ldr r3, [r7, #4] 8004714: 681b ldr r3, [r3, #0] 8004716: f003 0308 and.w r3, r3, #8 800471a: 2b00 cmp r3, #0 800471c: d036 beq.n 800478c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) 800471e: 687b ldr r3, [r7, #4] 8004720: 695b ldr r3, [r3, #20] 8004722: 2b00 cmp r3, #0 8004724: d016 beq.n 8004754 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004726: 4b15 ldr r3, [pc, #84] @ (800477c ) 8004728: 2201 movs r2, #1 800472a: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800472c: f7fc ff94 bl 8001658 8004730: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004732: e008 b.n 8004746 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004734: f7fc ff90 bl 8001658 8004738: 4602 mov r2, r0 800473a: 693b ldr r3, [r7, #16] 800473c: 1ad3 subs r3, r2, r3 800473e: 2b02 cmp r3, #2 8004740: d901 bls.n 8004746 { return HAL_TIMEOUT; 8004742: 2303 movs r3, #3 8004744: e167 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) 8004746: 4b0b ldr r3, [pc, #44] @ (8004774 ) 8004748: 6f5b ldr r3, [r3, #116] @ 0x74 800474a: f003 0302 and.w r3, r3, #2 800474e: 2b00 cmp r3, #0 8004750: d0f0 beq.n 8004734 8004752: e01b b.n 800478c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004754: 4b09 ldr r3, [pc, #36] @ (800477c ) 8004756: 2200 movs r2, #0 8004758: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 800475a: f7fc ff7d bl 8001658 800475e: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004760: e00e b.n 8004780 { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8004762: f7fc ff79 bl 8001658 8004766: 4602 mov r2, r0 8004768: 693b ldr r3, [r7, #16] 800476a: 1ad3 subs r3, r2, r3 800476c: 2b02 cmp r3, #2 800476e: d907 bls.n 8004780 { return HAL_TIMEOUT; 8004770: 2303 movs r3, #3 8004772: e150 b.n 8004a16 8004774: 40023800 .word 0x40023800 8004778: 42470000 .word 0x42470000 800477c: 42470e80 .word 0x42470e80 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) 8004780: 4b88 ldr r3, [pc, #544] @ (80049a4 ) 8004782: 6f5b ldr r3, [r3, #116] @ 0x74 8004784: f003 0302 and.w r3, r3, #2 8004788: 2b00 cmp r3, #0 800478a: d1ea bne.n 8004762 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 800478c: 687b ldr r3, [r7, #4] 800478e: 681b ldr r3, [r3, #0] 8004790: f003 0304 and.w r3, r3, #4 8004794: 2b00 cmp r3, #0 8004796: f000 8097 beq.w 80048c8 { FlagStatus pwrclkchanged = RESET; 800479a: 2300 movs r3, #0 800479c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 800479e: 4b81 ldr r3, [pc, #516] @ (80049a4 ) 80047a0: 6c1b ldr r3, [r3, #64] @ 0x40 80047a2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80047a6: 2b00 cmp r3, #0 80047a8: d10f bne.n 80047ca { __HAL_RCC_PWR_CLK_ENABLE(); 80047aa: 2300 movs r3, #0 80047ac: 60bb str r3, [r7, #8] 80047ae: 4b7d ldr r3, [pc, #500] @ (80049a4 ) 80047b0: 6c1b ldr r3, [r3, #64] @ 0x40 80047b2: 4a7c ldr r2, [pc, #496] @ (80049a4 ) 80047b4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 80047b8: 6413 str r3, [r2, #64] @ 0x40 80047ba: 4b7a ldr r3, [pc, #488] @ (80049a4 ) 80047bc: 6c1b ldr r3, [r3, #64] @ 0x40 80047be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 80047c2: 60bb str r3, [r7, #8] 80047c4: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80047c6: 2301 movs r3, #1 80047c8: 75fb strb r3, [r7, #23] } if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80047ca: 4b77 ldr r3, [pc, #476] @ (80049a8 ) 80047cc: 681b ldr r3, [r3, #0] 80047ce: f403 7380 and.w r3, r3, #256 @ 0x100 80047d2: 2b00 cmp r3, #0 80047d4: d118 bne.n 8004808 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); 80047d6: 4b74 ldr r3, [pc, #464] @ (80049a8 ) 80047d8: 681b ldr r3, [r3, #0] 80047da: 4a73 ldr r2, [pc, #460] @ (80049a8 ) 80047dc: f443 7380 orr.w r3, r3, #256 @ 0x100 80047e0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 80047e2: f7fc ff39 bl 8001658 80047e6: 6138 str r0, [r7, #16] while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80047e8: e008 b.n 80047fc { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 80047ea: f7fc ff35 bl 8001658 80047ee: 4602 mov r2, r0 80047f0: 693b ldr r3, [r7, #16] 80047f2: 1ad3 subs r3, r2, r3 80047f4: 2b02 cmp r3, #2 80047f6: d901 bls.n 80047fc { return HAL_TIMEOUT; 80047f8: 2303 movs r3, #3 80047fa: e10c b.n 8004a16 while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) 80047fc: 4b6a ldr r3, [pc, #424] @ (80049a8 ) 80047fe: 681b ldr r3, [r3, #0] 8004800: f403 7380 and.w r3, r3, #256 @ 0x100 8004804: 2b00 cmp r3, #0 8004806: d0f0 beq.n 80047ea } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004808: 687b ldr r3, [r7, #4] 800480a: 689b ldr r3, [r3, #8] 800480c: 2b01 cmp r3, #1 800480e: d106 bne.n 800481e 8004810: 4b64 ldr r3, [pc, #400] @ (80049a4 ) 8004812: 6f1b ldr r3, [r3, #112] @ 0x70 8004814: 4a63 ldr r2, [pc, #396] @ (80049a4 ) 8004816: f043 0301 orr.w r3, r3, #1 800481a: 6713 str r3, [r2, #112] @ 0x70 800481c: e01c b.n 8004858 800481e: 687b ldr r3, [r7, #4] 8004820: 689b ldr r3, [r3, #8] 8004822: 2b05 cmp r3, #5 8004824: d10c bne.n 8004840 8004826: 4b5f ldr r3, [pc, #380] @ (80049a4 ) 8004828: 6f1b ldr r3, [r3, #112] @ 0x70 800482a: 4a5e ldr r2, [pc, #376] @ (80049a4 ) 800482c: f043 0304 orr.w r3, r3, #4 8004830: 6713 str r3, [r2, #112] @ 0x70 8004832: 4b5c ldr r3, [pc, #368] @ (80049a4 ) 8004834: 6f1b ldr r3, [r3, #112] @ 0x70 8004836: 4a5b ldr r2, [pc, #364] @ (80049a4 ) 8004838: f043 0301 orr.w r3, r3, #1 800483c: 6713 str r3, [r2, #112] @ 0x70 800483e: e00b b.n 8004858 8004840: 4b58 ldr r3, [pc, #352] @ (80049a4 ) 8004842: 6f1b ldr r3, [r3, #112] @ 0x70 8004844: 4a57 ldr r2, [pc, #348] @ (80049a4 ) 8004846: f023 0301 bic.w r3, r3, #1 800484a: 6713 str r3, [r2, #112] @ 0x70 800484c: 4b55 ldr r3, [pc, #340] @ (80049a4 ) 800484e: 6f1b ldr r3, [r3, #112] @ 0x70 8004850: 4a54 ldr r2, [pc, #336] @ (80049a4 ) 8004852: f023 0304 bic.w r3, r3, #4 8004856: 6713 str r3, [r2, #112] @ 0x70 /* Check the LSE State */ if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) 8004858: 687b ldr r3, [r7, #4] 800485a: 689b ldr r3, [r3, #8] 800485c: 2b00 cmp r3, #0 800485e: d015 beq.n 800488c { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004860: f7fc fefa bl 8001658 8004864: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 8004866: e00a b.n 800487e { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004868: f7fc fef6 bl 8001658 800486c: 4602 mov r2, r0 800486e: 693b ldr r3, [r7, #16] 8004870: 1ad3 subs r3, r2, r3 8004872: f241 3288 movw r2, #5000 @ 0x1388 8004876: 4293 cmp r3, r2 8004878: d901 bls.n 800487e { return HAL_TIMEOUT; 800487a: 2303 movs r3, #3 800487c: e0cb b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 800487e: 4b49 ldr r3, [pc, #292] @ (80049a4 ) 8004880: 6f1b ldr r3, [r3, #112] @ 0x70 8004882: f003 0302 and.w r3, r3, #2 8004886: 2b00 cmp r3, #0 8004888: d0ee beq.n 8004868 800488a: e014 b.n 80048b6 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); 800488c: f7fc fee4 bl 8001658 8004890: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 8004892: e00a b.n 80048aa { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004894: f7fc fee0 bl 8001658 8004898: 4602 mov r2, r0 800489a: 693b ldr r3, [r7, #16] 800489c: 1ad3 subs r3, r2, r3 800489e: f241 3288 movw r2, #5000 @ 0x1388 80048a2: 4293 cmp r3, r2 80048a4: d901 bls.n 80048aa { return HAL_TIMEOUT; 80048a6: 2303 movs r3, #3 80048a8: e0b5 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) 80048aa: 4b3e ldr r3, [pc, #248] @ (80049a4 ) 80048ac: 6f1b ldr r3, [r3, #112] @ 0x70 80048ae: f003 0302 and.w r3, r3, #2 80048b2: 2b00 cmp r3, #0 80048b4: d1ee bne.n 8004894 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 80048b6: 7dfb ldrb r3, [r7, #23] 80048b8: 2b01 cmp r3, #1 80048ba: d105 bne.n 80048c8 { __HAL_RCC_PWR_CLK_DISABLE(); 80048bc: 4b39 ldr r3, [pc, #228] @ (80049a4 ) 80048be: 6c1b ldr r3, [r3, #64] @ 0x40 80048c0: 4a38 ldr r2, [pc, #224] @ (80049a4 ) 80048c2: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000 80048c6: 6413 str r3, [r2, #64] @ 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) 80048c8: 687b ldr r3, [r7, #4] 80048ca: 699b ldr r3, [r3, #24] 80048cc: 2b00 cmp r3, #0 80048ce: f000 80a1 beq.w 8004a14 { /* Check if the PLL is used as system clock or not */ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 80048d2: 4b34 ldr r3, [pc, #208] @ (80049a4 ) 80048d4: 689b ldr r3, [r3, #8] 80048d6: f003 030c and.w r3, r3, #12 80048da: 2b08 cmp r3, #8 80048dc: d05c beq.n 8004998 { if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) 80048de: 687b ldr r3, [r7, #4] 80048e0: 699b ldr r3, [r3, #24] 80048e2: 2b02 cmp r3, #2 80048e4: d141 bne.n 800496a assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 80048e6: 4b31 ldr r3, [pc, #196] @ (80049ac ) 80048e8: 2200 movs r2, #0 80048ea: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 80048ec: f7fc feb4 bl 8001658 80048f0: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 80048f2: e008 b.n 8004906 { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 80048f4: f7fc feb0 bl 8001658 80048f8: 4602 mov r2, r0 80048fa: 693b ldr r3, [r7, #16] 80048fc: 1ad3 subs r3, r2, r3 80048fe: 2b02 cmp r3, #2 8004900: d901 bls.n 8004906 { return HAL_TIMEOUT; 8004902: 2303 movs r3, #3 8004904: e087 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004906: 4b27 ldr r3, [pc, #156] @ (80049a4 ) 8004908: 681b ldr r3, [r3, #0] 800490a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 800490e: 2b00 cmp r3, #0 8004910: d1f0 bne.n 80048f4 } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ 8004912: 687b ldr r3, [r7, #4] 8004914: 69da ldr r2, [r3, #28] 8004916: 687b ldr r3, [r7, #4] 8004918: 6a1b ldr r3, [r3, #32] 800491a: 431a orrs r2, r3 800491c: 687b ldr r3, [r7, #4] 800491e: 6a5b ldr r3, [r3, #36] @ 0x24 8004920: 019b lsls r3, r3, #6 8004922: 431a orrs r2, r3 8004924: 687b ldr r3, [r7, #4] 8004926: 6a9b ldr r3, [r3, #40] @ 0x28 8004928: 085b lsrs r3, r3, #1 800492a: 3b01 subs r3, #1 800492c: 041b lsls r3, r3, #16 800492e: 431a orrs r2, r3 8004930: 687b ldr r3, [r7, #4] 8004932: 6adb ldr r3, [r3, #44] @ 0x2c 8004934: 061b lsls r3, r3, #24 8004936: 491b ldr r1, [pc, #108] @ (80049a4 ) 8004938: 4313 orrs r3, r2 800493a: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 800493c: 4b1b ldr r3, [pc, #108] @ (80049ac ) 800493e: 2201 movs r2, #1 8004940: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004942: f7fc fe89 bl 8001658 8004946: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004948: e008 b.n 800495c { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800494a: f7fc fe85 bl 8001658 800494e: 4602 mov r2, r0 8004950: 693b ldr r3, [r7, #16] 8004952: 1ad3 subs r3, r2, r3 8004954: 2b02 cmp r3, #2 8004956: d901 bls.n 800495c { return HAL_TIMEOUT; 8004958: 2303 movs r3, #3 800495a: e05c b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 800495c: 4b11 ldr r3, [pc, #68] @ (80049a4 ) 800495e: 681b ldr r3, [r3, #0] 8004960: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004964: 2b00 cmp r3, #0 8004966: d0f0 beq.n 800494a 8004968: e054 b.n 8004a14 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 800496a: 4b10 ldr r3, [pc, #64] @ (80049ac ) 800496c: 2200 movs r2, #0 800496e: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004970: f7fc fe72 bl 8001658 8004974: 6138 str r0, [r7, #16] /* Wait till PLL is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 8004976: e008 b.n 800498a { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8004978: f7fc fe6e bl 8001658 800497c: 4602 mov r2, r0 800497e: 693b ldr r3, [r7, #16] 8004980: 1ad3 subs r3, r2, r3 8004982: 2b02 cmp r3, #2 8004984: d901 bls.n 800498a { return HAL_TIMEOUT; 8004986: 2303 movs r3, #3 8004988: e045 b.n 8004a16 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 800498a: 4b06 ldr r3, [pc, #24] @ (80049a4 ) 800498c: 681b ldr r3, [r3, #0] 800498e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004992: 2b00 cmp r3, #0 8004994: d1f0 bne.n 8004978 8004996: e03d b.n 8004a14 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) 8004998: 687b ldr r3, [r7, #4] 800499a: 699b ldr r3, [r3, #24] 800499c: 2b01 cmp r3, #1 800499e: d107 bne.n 80049b0 { return HAL_ERROR; 80049a0: 2301 movs r3, #1 80049a2: e038 b.n 8004a16 80049a4: 40023800 .word 0x40023800 80049a8: 40007000 .word 0x40007000 80049ac: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; 80049b0: 4b1b ldr r3, [pc, #108] @ (8004a20 ) 80049b2: 685b ldr r3, [r3, #4] 80049b4: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80049b6: 687b ldr r3, [r7, #4] 80049b8: 699b ldr r3, [r3, #24] 80049ba: 2b01 cmp r3, #1 80049bc: d028 beq.n 8004a10 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80049be: 68fb ldr r3, [r7, #12] 80049c0: f403 0280 and.w r2, r3, #4194304 @ 0x400000 80049c4: 687b ldr r3, [r7, #4] 80049c6: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || 80049c8: 429a cmp r2, r3 80049ca: d121 bne.n 8004a10 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80049cc: 68fb ldr r3, [r7, #12] 80049ce: f003 023f and.w r2, r3, #63 @ 0x3f 80049d2: 687b ldr r3, [r7, #4] 80049d4: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || 80049d6: 429a cmp r2, r3 80049d8: d11a bne.n 8004a10 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80049da: 68fa ldr r2, [r7, #12] 80049dc: f647 73c0 movw r3, #32704 @ 0x7fc0 80049e0: 4013 ands r3, r2 80049e2: 687a ldr r2, [r7, #4] 80049e4: 6a52 ldr r2, [r2, #36] @ 0x24 80049e6: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || 80049e8: 4293 cmp r3, r2 80049ea: d111 bne.n 8004a10 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 80049ec: 68fb ldr r3, [r7, #12] 80049ee: f403 3240 and.w r2, r3, #196608 @ 0x30000 80049f2: 687b ldr r3, [r7, #4] 80049f4: 6a9b ldr r3, [r3, #40] @ 0x28 80049f6: 085b lsrs r3, r3, #1 80049f8: 3b01 subs r3, #1 80049fa: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || 80049fc: 429a cmp r2, r3 80049fe: d107 bne.n 8004a10 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) 8004a00: 68fb ldr r3, [r7, #12] 8004a02: f003 6270 and.w r2, r3, #251658240 @ 0xf000000 8004a06: 687b ldr r3, [r7, #4] 8004a08: 6adb ldr r3, [r3, #44] @ 0x2c 8004a0a: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || 8004a0c: 429a cmp r2, r3 8004a0e: d001 beq.n 8004a14 #endif /* RCC_PLLCFGR_PLLR */ { return HAL_ERROR; 8004a10: 2301 movs r3, #1 8004a12: e000 b.n 8004a16 } } } } return HAL_OK; 8004a14: 2300 movs r3, #0 } 8004a16: 4618 mov r0, r3 8004a18: 3718 adds r7, #24 8004a1a: 46bd mov sp, r7 8004a1c: bd80 pop {r7, pc} 8004a1e: bf00 nop 8004a20: 40023800 .word 0x40023800 08004a24 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004a24: b580 push {r7, lr} 8004a26: b084 sub sp, #16 8004a28: af00 add r7, sp, #0 8004a2a: 6078 str r0, [r7, #4] 8004a2c: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8004a2e: 687b ldr r3, [r7, #4] 8004a30: 2b00 cmp r3, #0 8004a32: d101 bne.n 8004a38 { return HAL_ERROR; 8004a34: 2301 movs r3, #1 8004a36: e0cc b.n 8004bd2 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004a38: 4b68 ldr r3, [pc, #416] @ (8004bdc ) 8004a3a: 681b ldr r3, [r3, #0] 8004a3c: f003 030f and.w r3, r3, #15 8004a40: 683a ldr r2, [r7, #0] 8004a42: 429a cmp r2, r3 8004a44: d90c bls.n 8004a60 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004a46: 4b65 ldr r3, [pc, #404] @ (8004bdc ) 8004a48: 683a ldr r2, [r7, #0] 8004a4a: b2d2 uxtb r2, r2 8004a4c: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004a4e: 4b63 ldr r3, [pc, #396] @ (8004bdc ) 8004a50: 681b ldr r3, [r3, #0] 8004a52: f003 030f and.w r3, r3, #15 8004a56: 683a ldr r2, [r7, #0] 8004a58: 429a cmp r2, r3 8004a5a: d001 beq.n 8004a60 { return HAL_ERROR; 8004a5c: 2301 movs r3, #1 8004a5e: e0b8 b.n 8004bd2 } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004a60: 687b ldr r3, [r7, #4] 8004a62: 681b ldr r3, [r3, #0] 8004a64: f003 0302 and.w r3, r3, #2 8004a68: 2b00 cmp r3, #0 8004a6a: d020 beq.n 8004aae { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004a6c: 687b ldr r3, [r7, #4] 8004a6e: 681b ldr r3, [r3, #0] 8004a70: f003 0304 and.w r3, r3, #4 8004a74: 2b00 cmp r3, #0 8004a76: d005 beq.n 8004a84 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); 8004a78: 4b59 ldr r3, [pc, #356] @ (8004be0 ) 8004a7a: 689b ldr r3, [r3, #8] 8004a7c: 4a58 ldr r2, [pc, #352] @ (8004be0 ) 8004a7e: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00 8004a82: 6093 str r3, [r2, #8] } if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004a84: 687b ldr r3, [r7, #4] 8004a86: 681b ldr r3, [r3, #0] 8004a88: f003 0308 and.w r3, r3, #8 8004a8c: 2b00 cmp r3, #0 8004a8e: d005 beq.n 8004a9c { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); 8004a90: 4b53 ldr r3, [pc, #332] @ (8004be0 ) 8004a92: 689b ldr r3, [r3, #8] 8004a94: 4a52 ldr r2, [pc, #328] @ (8004be0 ) 8004a96: f443 4360 orr.w r3, r3, #57344 @ 0xe000 8004a9a: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004a9c: 4b50 ldr r3, [pc, #320] @ (8004be0 ) 8004a9e: 689b ldr r3, [r3, #8] 8004aa0: f023 02f0 bic.w r2, r3, #240 @ 0xf0 8004aa4: 687b ldr r3, [r7, #4] 8004aa6: 689b ldr r3, [r3, #8] 8004aa8: 494d ldr r1, [pc, #308] @ (8004be0 ) 8004aaa: 4313 orrs r3, r2 8004aac: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004aae: 687b ldr r3, [r7, #4] 8004ab0: 681b ldr r3, [r3, #0] 8004ab2: f003 0301 and.w r3, r3, #1 8004ab6: 2b00 cmp r3, #0 8004ab8: d044 beq.n 8004b44 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8004aba: 687b ldr r3, [r7, #4] 8004abc: 685b ldr r3, [r3, #4] 8004abe: 2b01 cmp r3, #1 8004ac0: d107 bne.n 8004ad2 { /* Check the HSE ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) 8004ac2: 4b47 ldr r3, [pc, #284] @ (8004be0 ) 8004ac4: 681b ldr r3, [r3, #0] 8004ac6: f403 3300 and.w r3, r3, #131072 @ 0x20000 8004aca: 2b00 cmp r3, #0 8004acc: d119 bne.n 8004b02 { return HAL_ERROR; 8004ace: 2301 movs r3, #1 8004ad0: e07f b.n 8004bd2 } } /* PLL is selected as System Clock Source */ else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004ad2: 687b ldr r3, [r7, #4] 8004ad4: 685b ldr r3, [r3, #4] 8004ad6: 2b02 cmp r3, #2 8004ad8: d003 beq.n 8004ae2 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) 8004ada: 687b ldr r3, [r7, #4] 8004adc: 685b ldr r3, [r3, #4] else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || 8004ade: 2b03 cmp r3, #3 8004ae0: d107 bne.n 8004af2 { /* Check the PLL ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 8004ae2: 4b3f ldr r3, [pc, #252] @ (8004be0 ) 8004ae4: 681b ldr r3, [r3, #0] 8004ae6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000 8004aea: 2b00 cmp r3, #0 8004aec: d109 bne.n 8004b02 { return HAL_ERROR; 8004aee: 2301 movs r3, #1 8004af0: e06f b.n 8004bd2 } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) 8004af2: 4b3b ldr r3, [pc, #236] @ (8004be0 ) 8004af4: 681b ldr r3, [r3, #0] 8004af6: f003 0302 and.w r3, r3, #2 8004afa: 2b00 cmp r3, #0 8004afc: d101 bne.n 8004b02 { return HAL_ERROR; 8004afe: 2301 movs r3, #1 8004b00: e067 b.n 8004bd2 } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); 8004b02: 4b37 ldr r3, [pc, #220] @ (8004be0 ) 8004b04: 689b ldr r3, [r3, #8] 8004b06: f023 0203 bic.w r2, r3, #3 8004b0a: 687b ldr r3, [r7, #4] 8004b0c: 685b ldr r3, [r3, #4] 8004b0e: 4934 ldr r1, [pc, #208] @ (8004be0 ) 8004b10: 4313 orrs r3, r2 8004b12: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); 8004b14: f7fc fda0 bl 8001658 8004b18: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004b1a: e00a b.n 8004b32 { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8004b1c: f7fc fd9c bl 8001658 8004b20: 4602 mov r2, r0 8004b22: 68fb ldr r3, [r7, #12] 8004b24: 1ad3 subs r3, r2, r3 8004b26: f241 3288 movw r2, #5000 @ 0x1388 8004b2a: 4293 cmp r3, r2 8004b2c: d901 bls.n 8004b32 { return HAL_TIMEOUT; 8004b2e: 2303 movs r3, #3 8004b30: e04f b.n 8004bd2 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8004b32: 4b2b ldr r3, [pc, #172] @ (8004be0 ) 8004b34: 689b ldr r3, [r3, #8] 8004b36: f003 020c and.w r2, r3, #12 8004b3a: 687b ldr r3, [r7, #4] 8004b3c: 685b ldr r3, [r3, #4] 8004b3e: 009b lsls r3, r3, #2 8004b40: 429a cmp r2, r3 8004b42: d1eb bne.n 8004b1c } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 8004b44: 4b25 ldr r3, [pc, #148] @ (8004bdc ) 8004b46: 681b ldr r3, [r3, #0] 8004b48: f003 030f and.w r3, r3, #15 8004b4c: 683a ldr r2, [r7, #0] 8004b4e: 429a cmp r2, r3 8004b50: d20c bcs.n 8004b6c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004b52: 4b22 ldr r3, [pc, #136] @ (8004bdc ) 8004b54: 683a ldr r2, [r7, #0] 8004b56: b2d2 uxtb r2, r2 8004b58: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (__HAL_FLASH_GET_LATENCY() != FLatency) 8004b5a: 4b20 ldr r3, [pc, #128] @ (8004bdc ) 8004b5c: 681b ldr r3, [r3, #0] 8004b5e: f003 030f and.w r3, r3, #15 8004b62: 683a ldr r2, [r7, #0] 8004b64: 429a cmp r2, r3 8004b66: d001 beq.n 8004b6c { return HAL_ERROR; 8004b68: 2301 movs r3, #1 8004b6a: e032 b.n 8004bd2 } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004b6c: 687b ldr r3, [r7, #4] 8004b6e: 681b ldr r3, [r3, #0] 8004b70: f003 0304 and.w r3, r3, #4 8004b74: 2b00 cmp r3, #0 8004b76: d008 beq.n 8004b8a { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8004b78: 4b19 ldr r3, [pc, #100] @ (8004be0 ) 8004b7a: 689b ldr r3, [r3, #8] 8004b7c: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00 8004b80: 687b ldr r3, [r7, #4] 8004b82: 68db ldr r3, [r3, #12] 8004b84: 4916 ldr r1, [pc, #88] @ (8004be0 ) 8004b86: 4313 orrs r3, r2 8004b88: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8004b8a: 687b ldr r3, [r7, #4] 8004b8c: 681b ldr r3, [r3, #0] 8004b8e: f003 0308 and.w r3, r3, #8 8004b92: 2b00 cmp r3, #0 8004b94: d009 beq.n 8004baa { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 8004b96: 4b12 ldr r3, [pc, #72] @ (8004be0 ) 8004b98: 689b ldr r3, [r3, #8] 8004b9a: f423 4260 bic.w r2, r3, #57344 @ 0xe000 8004b9e: 687b ldr r3, [r7, #4] 8004ba0: 691b ldr r3, [r3, #16] 8004ba2: 00db lsls r3, r3, #3 8004ba4: 490e ldr r1, [pc, #56] @ (8004be0 ) 8004ba6: 4313 orrs r3, r2 8004ba8: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; 8004baa: f000 f821 bl 8004bf0 8004bae: 4602 mov r2, r0 8004bb0: 4b0b ldr r3, [pc, #44] @ (8004be0 ) 8004bb2: 689b ldr r3, [r3, #8] 8004bb4: 091b lsrs r3, r3, #4 8004bb6: f003 030f and.w r3, r3, #15 8004bba: 490a ldr r1, [pc, #40] @ (8004be4 ) 8004bbc: 5ccb ldrb r3, [r1, r3] 8004bbe: fa22 f303 lsr.w r3, r2, r3 8004bc2: 4a09 ldr r2, [pc, #36] @ (8004be8 ) 8004bc4: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick(uwTickPrio); 8004bc6: 4b09 ldr r3, [pc, #36] @ (8004bec ) 8004bc8: 681b ldr r3, [r3, #0] 8004bca: 4618 mov r0, r3 8004bcc: f7fc fc12 bl 80013f4 return HAL_OK; 8004bd0: 2300 movs r3, #0 } 8004bd2: 4618 mov r0, r3 8004bd4: 3710 adds r7, #16 8004bd6: 46bd mov sp, r7 8004bd8: bd80 pop {r7, pc} 8004bda: bf00 nop 8004bdc: 40023c00 .word 0x40023c00 8004be0: 40023800 .word 0x40023800 8004be4: 08007f2c .word 0x08007f2c 8004be8: 20000000 .word 0x20000000 8004bec: 20000004 .word 0x20000004 08004bf0 : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { 8004bf0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8004bf4: b094 sub sp, #80 @ 0x50 8004bf6: af00 add r7, sp, #0 uint32_t pllm = 0U; 8004bf8: 2300 movs r3, #0 8004bfa: 647b str r3, [r7, #68] @ 0x44 uint32_t pllvco = 0U; 8004bfc: 2300 movs r3, #0 8004bfe: 64fb str r3, [r7, #76] @ 0x4c uint32_t pllp = 0U; 8004c00: 2300 movs r3, #0 8004c02: 643b str r3, [r7, #64] @ 0x40 uint32_t sysclockfreq = 0U; 8004c04: 2300 movs r3, #0 8004c06: 64bb str r3, [r7, #72] @ 0x48 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) 8004c08: 4b79 ldr r3, [pc, #484] @ (8004df0 ) 8004c0a: 689b ldr r3, [r3, #8] 8004c0c: f003 030c and.w r3, r3, #12 8004c10: 2b08 cmp r3, #8 8004c12: d00d beq.n 8004c30 8004c14: 2b08 cmp r3, #8 8004c16: f200 80e1 bhi.w 8004ddc 8004c1a: 2b00 cmp r3, #0 8004c1c: d002 beq.n 8004c24 8004c1e: 2b04 cmp r3, #4 8004c20: d003 beq.n 8004c2a 8004c22: e0db b.n 8004ddc { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; 8004c24: 4b73 ldr r3, [pc, #460] @ (8004df4 ) 8004c26: 64bb str r3, [r7, #72] @ 0x48 break; 8004c28: e0db b.n 8004de2 } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; 8004c2a: 4b73 ldr r3, [pc, #460] @ (8004df8 ) 8004c2c: 64bb str r3, [r7, #72] @ 0x48 break; 8004c2e: e0d8 b.n 8004de2 } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 8004c30: 4b6f ldr r3, [pc, #444] @ (8004df0 ) 8004c32: 685b ldr r3, [r3, #4] 8004c34: f003 033f and.w r3, r3, #63 @ 0x3f 8004c38: 647b str r3, [r7, #68] @ 0x44 if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) 8004c3a: 4b6d ldr r3, [pc, #436] @ (8004df0 ) 8004c3c: 685b ldr r3, [r3, #4] 8004c3e: f403 0380 and.w r3, r3, #4194304 @ 0x400000 8004c42: 2b00 cmp r3, #0 8004c44: d063 beq.n 8004d0e { /* HSE used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004c46: 4b6a ldr r3, [pc, #424] @ (8004df0 ) 8004c48: 685b ldr r3, [r3, #4] 8004c4a: 099b lsrs r3, r3, #6 8004c4c: 2200 movs r2, #0 8004c4e: 63bb str r3, [r7, #56] @ 0x38 8004c50: 63fa str r2, [r7, #60] @ 0x3c 8004c52: 6bbb ldr r3, [r7, #56] @ 0x38 8004c54: f3c3 0308 ubfx r3, r3, #0, #9 8004c58: 633b str r3, [r7, #48] @ 0x30 8004c5a: 2300 movs r3, #0 8004c5c: 637b str r3, [r7, #52] @ 0x34 8004c5e: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30 8004c62: 4622 mov r2, r4 8004c64: 462b mov r3, r5 8004c66: f04f 0000 mov.w r0, #0 8004c6a: f04f 0100 mov.w r1, #0 8004c6e: 0159 lsls r1, r3, #5 8004c70: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004c74: 0150 lsls r0, r2, #5 8004c76: 4602 mov r2, r0 8004c78: 460b mov r3, r1 8004c7a: 4621 mov r1, r4 8004c7c: 1a51 subs r1, r2, r1 8004c7e: 6139 str r1, [r7, #16] 8004c80: 4629 mov r1, r5 8004c82: eb63 0301 sbc.w r3, r3, r1 8004c86: 617b str r3, [r7, #20] 8004c88: f04f 0200 mov.w r2, #0 8004c8c: f04f 0300 mov.w r3, #0 8004c90: e9d7 ab04 ldrd sl, fp, [r7, #16] 8004c94: 4659 mov r1, fp 8004c96: 018b lsls r3, r1, #6 8004c98: 4651 mov r1, sl 8004c9a: ea43 6391 orr.w r3, r3, r1, lsr #26 8004c9e: 4651 mov r1, sl 8004ca0: 018a lsls r2, r1, #6 8004ca2: 4651 mov r1, sl 8004ca4: ebb2 0801 subs.w r8, r2, r1 8004ca8: 4659 mov r1, fp 8004caa: eb63 0901 sbc.w r9, r3, r1 8004cae: f04f 0200 mov.w r2, #0 8004cb2: f04f 0300 mov.w r3, #0 8004cb6: ea4f 03c9 mov.w r3, r9, lsl #3 8004cba: ea43 7358 orr.w r3, r3, r8, lsr #29 8004cbe: ea4f 02c8 mov.w r2, r8, lsl #3 8004cc2: 4690 mov r8, r2 8004cc4: 4699 mov r9, r3 8004cc6: 4623 mov r3, r4 8004cc8: eb18 0303 adds.w r3, r8, r3 8004ccc: 60bb str r3, [r7, #8] 8004cce: 462b mov r3, r5 8004cd0: eb49 0303 adc.w r3, r9, r3 8004cd4: 60fb str r3, [r7, #12] 8004cd6: f04f 0200 mov.w r2, #0 8004cda: f04f 0300 mov.w r3, #0 8004cde: e9d7 4502 ldrd r4, r5, [r7, #8] 8004ce2: 4629 mov r1, r5 8004ce4: 024b lsls r3, r1, #9 8004ce6: 4621 mov r1, r4 8004ce8: ea43 53d1 orr.w r3, r3, r1, lsr #23 8004cec: 4621 mov r1, r4 8004cee: 024a lsls r2, r1, #9 8004cf0: 4610 mov r0, r2 8004cf2: 4619 mov r1, r3 8004cf4: 6c7b ldr r3, [r7, #68] @ 0x44 8004cf6: 2200 movs r2, #0 8004cf8: 62bb str r3, [r7, #40] @ 0x28 8004cfa: 62fa str r2, [r7, #44] @ 0x2c 8004cfc: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8004d00: f7fb fa76 bl 80001f0 <__aeabi_uldivmod> 8004d04: 4602 mov r2, r0 8004d06: 460b mov r3, r1 8004d08: 4613 mov r3, r2 8004d0a: 64fb str r3, [r7, #76] @ 0x4c 8004d0c: e058 b.n 8004dc0 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); 8004d0e: 4b38 ldr r3, [pc, #224] @ (8004df0 ) 8004d10: 685b ldr r3, [r3, #4] 8004d12: 099b lsrs r3, r3, #6 8004d14: 2200 movs r2, #0 8004d16: 4618 mov r0, r3 8004d18: 4611 mov r1, r2 8004d1a: f3c0 0308 ubfx r3, r0, #0, #9 8004d1e: 623b str r3, [r7, #32] 8004d20: 2300 movs r3, #0 8004d22: 627b str r3, [r7, #36] @ 0x24 8004d24: e9d7 8908 ldrd r8, r9, [r7, #32] 8004d28: 4642 mov r2, r8 8004d2a: 464b mov r3, r9 8004d2c: f04f 0000 mov.w r0, #0 8004d30: f04f 0100 mov.w r1, #0 8004d34: 0159 lsls r1, r3, #5 8004d36: ea41 61d2 orr.w r1, r1, r2, lsr #27 8004d3a: 0150 lsls r0, r2, #5 8004d3c: 4602 mov r2, r0 8004d3e: 460b mov r3, r1 8004d40: 4641 mov r1, r8 8004d42: ebb2 0a01 subs.w sl, r2, r1 8004d46: 4649 mov r1, r9 8004d48: eb63 0b01 sbc.w fp, r3, r1 8004d4c: f04f 0200 mov.w r2, #0 8004d50: f04f 0300 mov.w r3, #0 8004d54: ea4f 138b mov.w r3, fp, lsl #6 8004d58: ea43 639a orr.w r3, r3, sl, lsr #26 8004d5c: ea4f 128a mov.w r2, sl, lsl #6 8004d60: ebb2 040a subs.w r4, r2, sl 8004d64: eb63 050b sbc.w r5, r3, fp 8004d68: f04f 0200 mov.w r2, #0 8004d6c: f04f 0300 mov.w r3, #0 8004d70: 00eb lsls r3, r5, #3 8004d72: ea43 7354 orr.w r3, r3, r4, lsr #29 8004d76: 00e2 lsls r2, r4, #3 8004d78: 4614 mov r4, r2 8004d7a: 461d mov r5, r3 8004d7c: 4643 mov r3, r8 8004d7e: 18e3 adds r3, r4, r3 8004d80: 603b str r3, [r7, #0] 8004d82: 464b mov r3, r9 8004d84: eb45 0303 adc.w r3, r5, r3 8004d88: 607b str r3, [r7, #4] 8004d8a: f04f 0200 mov.w r2, #0 8004d8e: f04f 0300 mov.w r3, #0 8004d92: e9d7 4500 ldrd r4, r5, [r7] 8004d96: 4629 mov r1, r5 8004d98: 028b lsls r3, r1, #10 8004d9a: 4621 mov r1, r4 8004d9c: ea43 5391 orr.w r3, r3, r1, lsr #22 8004da0: 4621 mov r1, r4 8004da2: 028a lsls r2, r1, #10 8004da4: 4610 mov r0, r2 8004da6: 4619 mov r1, r3 8004da8: 6c7b ldr r3, [r7, #68] @ 0x44 8004daa: 2200 movs r2, #0 8004dac: 61bb str r3, [r7, #24] 8004dae: 61fa str r2, [r7, #28] 8004db0: e9d7 2306 ldrd r2, r3, [r7, #24] 8004db4: f7fb fa1c bl 80001f0 <__aeabi_uldivmod> 8004db8: 4602 mov r2, r0 8004dba: 460b mov r3, r1 8004dbc: 4613 mov r3, r2 8004dbe: 64fb str r3, [r7, #76] @ 0x4c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U); 8004dc0: 4b0b ldr r3, [pc, #44] @ (8004df0 ) 8004dc2: 685b ldr r3, [r3, #4] 8004dc4: 0c1b lsrs r3, r3, #16 8004dc6: f003 0303 and.w r3, r3, #3 8004dca: 3301 adds r3, #1 8004dcc: 005b lsls r3, r3, #1 8004dce: 643b str r3, [r7, #64] @ 0x40 sysclockfreq = pllvco / pllp; 8004dd0: 6cfa ldr r2, [r7, #76] @ 0x4c 8004dd2: 6c3b ldr r3, [r7, #64] @ 0x40 8004dd4: fbb2 f3f3 udiv r3, r2, r3 8004dd8: 64bb str r3, [r7, #72] @ 0x48 break; 8004dda: e002 b.n 8004de2 } default: { sysclockfreq = HSI_VALUE; 8004ddc: 4b05 ldr r3, [pc, #20] @ (8004df4 ) 8004dde: 64bb str r3, [r7, #72] @ 0x48 break; 8004de0: bf00 nop } } return sysclockfreq; 8004de2: 6cbb ldr r3, [r7, #72] @ 0x48 } 8004de4: 4618 mov r0, r3 8004de6: 3750 adds r7, #80 @ 0x50 8004de8: 46bd mov sp, r7 8004dea: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8004dee: bf00 nop 8004df0: 40023800 .word 0x40023800 8004df4: 00f42400 .word 0x00f42400 8004df8: 007a1200 .word 0x007a1200 08004dfc : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8004dfc: b480 push {r7} 8004dfe: af00 add r7, sp, #0 return SystemCoreClock; 8004e00: 4b03 ldr r3, [pc, #12] @ (8004e10 ) 8004e02: 681b ldr r3, [r3, #0] } 8004e04: 4618 mov r0, r3 8004e06: 46bd mov sp, r7 8004e08: f85d 7b04 ldr.w r7, [sp], #4 8004e0c: 4770 bx lr 8004e0e: bf00 nop 8004e10: 20000000 .word 0x20000000 08004e14 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 8004e14: b580 push {r7, lr} 8004e16: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); 8004e18: f7ff fff0 bl 8004dfc 8004e1c: 4602 mov r2, r0 8004e1e: 4b05 ldr r3, [pc, #20] @ (8004e34 ) 8004e20: 689b ldr r3, [r3, #8] 8004e22: 0a9b lsrs r3, r3, #10 8004e24: f003 0307 and.w r3, r3, #7 8004e28: 4903 ldr r1, [pc, #12] @ (8004e38 ) 8004e2a: 5ccb ldrb r3, [r1, r3] 8004e2c: fa22 f303 lsr.w r3, r2, r3 } 8004e30: 4618 mov r0, r3 8004e32: bd80 pop {r7, pc} 8004e34: 40023800 .word 0x40023800 8004e38: 08007f3c .word 0x08007f3c 08004e3c : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { 8004e3c: b580 push {r7, lr} 8004e3e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); 8004e40: f7ff ffdc bl 8004dfc 8004e44: 4602 mov r2, r0 8004e46: 4b05 ldr r3, [pc, #20] @ (8004e5c ) 8004e48: 689b ldr r3, [r3, #8] 8004e4a: 0b5b lsrs r3, r3, #13 8004e4c: f003 0307 and.w r3, r3, #7 8004e50: 4903 ldr r1, [pc, #12] @ (8004e60 ) 8004e52: 5ccb ldrb r3, [r1, r3] 8004e54: fa22 f303 lsr.w r3, r2, r3 } 8004e58: 4618 mov r0, r3 8004e5a: bd80 pop {r7, pc} 8004e5c: 40023800 .word 0x40023800 8004e60: 08007f3c .word 0x08007f3c 08004e64 : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { 8004e64: b480 push {r7} 8004e66: b083 sub sp, #12 8004e68: af00 add r7, sp, #0 8004e6a: 6078 str r0, [r7, #4] 8004e6c: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; 8004e6e: 687b ldr r3, [r7, #4] 8004e70: 220f movs r2, #15 8004e72: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); 8004e74: 4b12 ldr r3, [pc, #72] @ (8004ec0 ) 8004e76: 689b ldr r3, [r3, #8] 8004e78: f003 0203 and.w r2, r3, #3 8004e7c: 687b ldr r3, [r7, #4] 8004e7e: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 8004e80: 4b0f ldr r3, [pc, #60] @ (8004ec0 ) 8004e82: 689b ldr r3, [r3, #8] 8004e84: f003 02f0 and.w r2, r3, #240 @ 0xf0 8004e88: 687b ldr r3, [r7, #4] 8004e8a: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); 8004e8c: 4b0c ldr r3, [pc, #48] @ (8004ec0 ) 8004e8e: 689b ldr r3, [r3, #8] 8004e90: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8004e94: 687b ldr r3, [r7, #4] 8004e96: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); 8004e98: 4b09 ldr r3, [pc, #36] @ (8004ec0 ) 8004e9a: 689b ldr r3, [r3, #8] 8004e9c: 08db lsrs r3, r3, #3 8004e9e: f403 52e0 and.w r2, r3, #7168 @ 0x1c00 8004ea2: 687b ldr r3, [r7, #4] 8004ea4: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 8004ea6: 4b07 ldr r3, [pc, #28] @ (8004ec4 ) 8004ea8: 681b ldr r3, [r3, #0] 8004eaa: f003 020f and.w r2, r3, #15 8004eae: 683b ldr r3, [r7, #0] 8004eb0: 601a str r2, [r3, #0] } 8004eb2: bf00 nop 8004eb4: 370c adds r7, #12 8004eb6: 46bd mov sp, r7 8004eb8: f85d 7b04 ldr.w r7, [sp], #4 8004ebc: 4770 bx lr 8004ebe: bf00 nop 8004ec0: 40023800 .word 0x40023800 8004ec4: 40023c00 .word 0x40023c00 08004ec8 : * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8004ec8: b580 push {r7, lr} 8004eca: b086 sub sp, #24 8004ecc: af00 add r7, sp, #0 8004ece: 6078 str r0, [r7, #4] uint32_t tickstart = 0U; 8004ed0: 2300 movs r3, #0 8004ed2: 617b str r3, [r7, #20] uint32_t tmpreg1 = 0U; 8004ed4: 2300 movs r3, #0 8004ed6: 613b str r3, [r7, #16] /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*----------------------- Common configuration SAI/I2S ---------------------*/ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division factor is common parameters for both peripherals */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 8004ed8: 687b ldr r3, [r7, #4] 8004eda: 681b ldr r3, [r3, #0] 8004edc: f003 0301 and.w r3, r3, #1 8004ee0: 2b00 cmp r3, #0 8004ee2: d10b bne.n 8004efc (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || 8004ee4: 687b ldr r3, [r7, #4] 8004ee6: 681b ldr r3, [r3, #0] 8004ee8: f003 0302 and.w r3, r3, #2 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || 8004eec: 2b00 cmp r3, #0 8004eee: d105 bne.n 8004efc (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) 8004ef0: 687b ldr r3, [r7, #4] 8004ef2: 681b ldr r3, [r3, #0] 8004ef4: f003 0340 and.w r3, r3, #64 @ 0x40 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || 8004ef8: 2b00 cmp r3, #0 8004efa: d075 beq.n 8004fe8 { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); 8004efc: 4b91 ldr r3, [pc, #580] @ (8005144 ) 8004efe: 2200 movs r2, #0 8004f00: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004f02: f7fc fba9 bl 8001658 8004f06: 6178 str r0, [r7, #20] /* Wait till PLLI2S is disabled */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004f08: e008 b.n 8004f1c { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004f0a: f7fc fba5 bl 8001658 8004f0e: 4602 mov r2, r0 8004f10: 697b ldr r3, [r7, #20] 8004f12: 1ad3 subs r3, r2, r3 8004f14: 2b02 cmp r3, #2 8004f16: d901 bls.n 8004f1c { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004f18: 2303 movs r3, #3 8004f1a: e189 b.n 8005230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) 8004f1c: 4b8a ldr r3, [pc, #552] @ (8005148 ) 8004f1e: 681b ldr r3, [r3, #0] 8004f20: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004f24: 2b00 cmp r3, #0 8004f26: d1f0 bne.n 8004f0a } /*---------------------------- I2S configuration -------------------------*/ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added only for I2S configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) 8004f28: 687b ldr r3, [r7, #4] 8004f2a: 681b ldr r3, [r3, #0] 8004f2c: f003 0301 and.w r3, r3, #1 8004f30: 2b00 cmp r3, #0 8004f32: d009 beq.n 8004f48 /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); 8004f34: 687b ldr r3, [r7, #4] 8004f36: 685b ldr r3, [r3, #4] 8004f38: 019a lsls r2, r3, #6 8004f3a: 687b ldr r3, [r7, #4] 8004f3c: 689b ldr r3, [r3, #8] 8004f3e: 071b lsls r3, r3, #28 8004f40: 4981 ldr r1, [pc, #516] @ (8005148 ) 8004f42: 4313 orrs r3, r2 8004f44: f8c1 3084 str.w r3, [r1, #132] @ 0x84 } /*---------------------------- SAI configuration -------------------------*/ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must be added only for SAI configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) 8004f48: 687b ldr r3, [r7, #4] 8004f4a: 681b ldr r3, [r3, #0] 8004f4c: f003 0302 and.w r3, r3, #2 8004f50: 2b00 cmp r3, #0 8004f52: d01f beq.n 8004f94 /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); 8004f54: 4b7c ldr r3, [pc, #496] @ (8005148 ) 8004f56: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84 8004f5a: 0f1b lsrs r3, r3, #28 8004f5c: f003 0307 and.w r3, r3, #7 8004f60: 613b str r3, [r7, #16] /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); 8004f62: 687b ldr r3, [r7, #4] 8004f64: 685b ldr r3, [r3, #4] 8004f66: 019a lsls r2, r3, #6 8004f68: 687b ldr r3, [r7, #4] 8004f6a: 68db ldr r3, [r3, #12] 8004f6c: 061b lsls r3, r3, #24 8004f6e: 431a orrs r2, r3 8004f70: 693b ldr r3, [r7, #16] 8004f72: 071b lsls r3, r3, #28 8004f74: 4974 ldr r1, [pc, #464] @ (8005148 ) 8004f76: 4313 orrs r3, r2 8004f78: f8c1 3084 str.w r3, [r1, #132] @ 0x84 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); 8004f7c: 4b72 ldr r3, [pc, #456] @ (8005148 ) 8004f7e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8004f82: f023 021f bic.w r2, r3, #31 8004f86: 687b ldr r3, [r7, #4] 8004f88: 69db ldr r3, [r3, #28] 8004f8a: 3b01 subs r3, #1 8004f8c: 496e ldr r1, [pc, #440] @ (8005148 ) 8004f8e: 4313 orrs r3, r2 8004f90: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*----------------- In Case of PLLI2S is just selected -----------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) 8004f94: 687b ldr r3, [r7, #4] 8004f96: 681b ldr r3, [r3, #0] 8004f98: f003 0340 and.w r3, r3, #64 @ 0x40 8004f9c: 2b00 cmp r3, #0 8004f9e: d00d beq.n 8004fbc /* Check for Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Configure the PLLI2S multiplication and division factors */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, 8004fa0: 687b ldr r3, [r7, #4] 8004fa2: 685b ldr r3, [r3, #4] 8004fa4: 019a lsls r2, r3, #6 8004fa6: 687b ldr r3, [r7, #4] 8004fa8: 68db ldr r3, [r3, #12] 8004faa: 061b lsls r3, r3, #24 8004fac: 431a orrs r2, r3 8004fae: 687b ldr r3, [r7, #4] 8004fb0: 689b ldr r3, [r3, #8] 8004fb2: 071b lsls r3, r3, #28 8004fb4: 4964 ldr r1, [pc, #400] @ (8005148 ) 8004fb6: 4313 orrs r3, r2 8004fb8: f8c1 3084 str.w r3, [r1, #132] @ 0x84 PeriphClkInit->PLLI2S.PLLI2SR); } /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); 8004fbc: 4b61 ldr r3, [pc, #388] @ (8005144 ) 8004fbe: 2201 movs r2, #1 8004fc0: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8004fc2: f7fc fb49 bl 8001658 8004fc6: 6178 str r0, [r7, #20] /* Wait till PLLI2S is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004fc8: e008 b.n 8004fdc { if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) 8004fca: f7fc fb45 bl 8001658 8004fce: 4602 mov r2, r0 8004fd0: 697b ldr r3, [r7, #20] 8004fd2: 1ad3 subs r3, r2, r3 8004fd4: 2b02 cmp r3, #2 8004fd6: d901 bls.n 8004fdc { /* return in case of Timeout detected */ return HAL_TIMEOUT; 8004fd8: 2303 movs r3, #3 8004fda: e129 b.n 8005230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) 8004fdc: 4b5a ldr r3, [pc, #360] @ (8005148 ) 8004fde: 681b ldr r3, [r3, #0] 8004fe0: f003 6300 and.w r3, r3, #134217728 @ 0x8000000 8004fe4: 2b00 cmp r3, #0 8004fe6: d0f0 beq.n 8004fca /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division factor is common parameters for both peripherals */ if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 8004fe8: 687b ldr r3, [r7, #4] 8004fea: 681b ldr r3, [r3, #0] 8004fec: f003 0304 and.w r3, r3, #4 8004ff0: 2b00 cmp r3, #0 8004ff2: d105 bne.n 8005000 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) 8004ff4: 687b ldr r3, [r7, #4] 8004ff6: 681b ldr r3, [r3, #0] 8004ff8: f003 0308 and.w r3, r3, #8 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || 8004ffc: 2b00 cmp r3, #0 8004ffe: d079 beq.n 80050f4 { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); /* Disable PLLSAI Clock */ __HAL_RCC_PLLSAI_DISABLE(); 8005000: 4b52 ldr r3, [pc, #328] @ (800514c ) 8005002: 2200 movs r2, #0 8005004: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 8005006: f7fc fb27 bl 8001658 800500a: 6178 str r0, [r7, #20] /* Wait till PLLSAI is disabled */ while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 800500c: e008 b.n 8005020 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 800500e: f7fc fb23 bl 8001658 8005012: 4602 mov r2, r0 8005014: 697b ldr r3, [r7, #20] 8005016: 1ad3 subs r3, r2, r3 8005018: 2b02 cmp r3, #2 800501a: d901 bls.n 8005020 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 800501c: 2303 movs r3, #3 800501e: e107 b.n 8005230 while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET) 8005020: 4b49 ldr r3, [pc, #292] @ (8005148 ) 8005022: 681b ldr r3, [r3, #0] 8005024: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 8005028: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 800502c: d0ef beq.n 800500e } /*---------------------------- SAI configuration -------------------------*/ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must be added only for SAI configuration */ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) 800502e: 687b ldr r3, [r7, #4] 8005030: 681b ldr r3, [r3, #0] 8005032: f003 0304 and.w r3, r3, #4 8005036: 2b00 cmp r3, #0 8005038: d020 beq.n 800507c { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); 800503a: 4b43 ldr r3, [pc, #268] @ (8005148 ) 800503c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 8005040: 0f1b lsrs r3, r3, #28 8005042: f003 0307 and.w r3, r3, #7 8005046: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); 8005048: 687b ldr r3, [r7, #4] 800504a: 691b ldr r3, [r3, #16] 800504c: 019a lsls r2, r3, #6 800504e: 687b ldr r3, [r7, #4] 8005050: 695b ldr r3, [r3, #20] 8005052: 061b lsls r3, r3, #24 8005054: 431a orrs r2, r3 8005056: 693b ldr r3, [r7, #16] 8005058: 071b lsls r3, r3, #28 800505a: 493b ldr r1, [pc, #236] @ (8005148 ) 800505c: 4313 orrs r3, r2 800505e: f8c1 3088 str.w r3, [r1, #136] @ 0x88 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); 8005062: 4b39 ldr r3, [pc, #228] @ (8005148 ) 8005064: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 8005068: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00 800506c: 687b ldr r3, [r7, #4] 800506e: 6a1b ldr r3, [r3, #32] 8005070: 3b01 subs r3, #1 8005072: 021b lsls r3, r3, #8 8005074: 4934 ldr r1, [pc, #208] @ (8005148 ) 8005076: 4313 orrs r3, r2 8005078: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /*---------------------------- LTDC configuration ------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) 800507c: 687b ldr r3, [r7, #4] 800507e: 681b ldr r3, [r3, #0] 8005080: f003 0308 and.w r3, r3, #8 8005084: 2b00 cmp r3, #0 8005086: d01e beq.n 80050c6 { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); 8005088: 4b2f ldr r3, [pc, #188] @ (8005148 ) 800508a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88 800508e: 0e1b lsrs r3, r3, #24 8005090: f003 030f and.w r3, r3, #15 8005094: 613b str r3, [r7, #16] /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); 8005096: 687b ldr r3, [r7, #4] 8005098: 691b ldr r3, [r3, #16] 800509a: 019a lsls r2, r3, #6 800509c: 693b ldr r3, [r7, #16] 800509e: 061b lsls r3, r3, #24 80050a0: 431a orrs r2, r3 80050a2: 687b ldr r3, [r7, #4] 80050a4: 699b ldr r3, [r3, #24] 80050a6: 071b lsls r3, r3, #28 80050a8: 4927 ldr r1, [pc, #156] @ (8005148 ) 80050aa: 4313 orrs r3, r2 80050ac: f8c1 3088 str.w r3, [r1, #136] @ 0x88 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); 80050b0: 4b25 ldr r3, [pc, #148] @ (8005148 ) 80050b2: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c 80050b6: f423 3240 bic.w r2, r3, #196608 @ 0x30000 80050ba: 687b ldr r3, [r7, #4] 80050bc: 6a5b ldr r3, [r3, #36] @ 0x24 80050be: 4922 ldr r1, [pc, #136] @ (8005148 ) 80050c0: 4313 orrs r3, r2 80050c2: f8c1 308c str.w r3, [r1, #140] @ 0x8c } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); 80050c6: 4b21 ldr r3, [pc, #132] @ (800514c ) 80050c8: 2201 movs r2, #1 80050ca: 601a str r2, [r3, #0] /* Get tick */ tickstart = HAL_GetTick(); 80050cc: f7fc fac4 bl 8001658 80050d0: 6178 str r0, [r7, #20] /* Wait till PLLSAI is ready */ while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 80050d2: e008 b.n 80050e6 { if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) 80050d4: f7fc fac0 bl 8001658 80050d8: 4602 mov r2, r0 80050da: 697b ldr r3, [r7, #20] 80050dc: 1ad3 subs r3, r2, r3 80050de: 2b02 cmp r3, #2 80050e0: d901 bls.n 80050e6 { /* return in case of Timeout detected */ return HAL_TIMEOUT; 80050e2: 2303 movs r3, #3 80050e4: e0a4 b.n 8005230 while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET) 80050e6: 4b18 ldr r3, [pc, #96] @ (8005148 ) 80050e8: 681b ldr r3, [r3, #0] 80050ea: f003 5300 and.w r3, r3, #536870912 @ 0x20000000 80050ee: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000 80050f2: d1ef bne.n 80050d4 } } /*--------------------------------------------------------------------------*/ /*---------------------------- RTC configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) 80050f4: 687b ldr r3, [r7, #4] 80050f6: 681b ldr r3, [r3, #0] 80050f8: f003 0320 and.w r3, r3, #32 80050fc: 2b00 cmp r3, #0 80050fe: f000 808b beq.w 8005218 { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); 8005102: 2300 movs r3, #0 8005104: 60fb str r3, [r7, #12] 8005106: 4b10 ldr r3, [pc, #64] @ (8005148 ) 8005108: 6c1b ldr r3, [r3, #64] @ 0x40 800510a: 4a0f ldr r2, [pc, #60] @ (8005148 ) 800510c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000 8005110: 6413 str r3, [r2, #64] @ 0x40 8005112: 4b0d ldr r3, [pc, #52] @ (8005148 ) 8005114: 6c1b ldr r3, [r3, #64] @ 0x40 8005116: f003 5380 and.w r3, r3, #268435456 @ 0x10000000 800511a: 60fb str r3, [r7, #12] 800511c: 68fb ldr r3, [r7, #12] /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; 800511e: 4b0c ldr r3, [pc, #48] @ (8005150 ) 8005120: 681b ldr r3, [r3, #0] 8005122: 4a0b ldr r2, [pc, #44] @ (8005150 ) 8005124: f443 7380 orr.w r3, r3, #256 @ 0x100 8005128: 6013 str r3, [r2, #0] /* Get tick */ tickstart = HAL_GetTick(); 800512a: f7fc fa95 bl 8001658 800512e: 6178 str r0, [r7, #20] while ((PWR->CR & PWR_CR_DBP) == RESET) 8005130: e010 b.n 8005154 { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8005132: f7fc fa91 bl 8001658 8005136: 4602 mov r2, r0 8005138: 697b ldr r3, [r7, #20] 800513a: 1ad3 subs r3, r2, r3 800513c: 2b02 cmp r3, #2 800513e: d909 bls.n 8005154 { return HAL_TIMEOUT; 8005140: 2303 movs r3, #3 8005142: e075 b.n 8005230 8005144: 42470068 .word 0x42470068 8005148: 40023800 .word 0x40023800 800514c: 42470070 .word 0x42470070 8005150: 40007000 .word 0x40007000 while ((PWR->CR & PWR_CR_DBP) == RESET) 8005154: 4b38 ldr r3, [pc, #224] @ (8005238 ) 8005156: 681b ldr r3, [r3, #0] 8005158: f403 7380 and.w r3, r3, #256 @ 0x100 800515c: 2b00 cmp r3, #0 800515e: d0e8 beq.n 8005132 } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); 8005160: 4b36 ldr r3, [pc, #216] @ (800523c ) 8005162: 6f1b ldr r3, [r3, #112] @ 0x70 8005164: f403 7340 and.w r3, r3, #768 @ 0x300 8005168: 613b str r3, [r7, #16] if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) 800516a: 693b ldr r3, [r7, #16] 800516c: 2b00 cmp r3, #0 800516e: d02f beq.n 80051d0 8005170: 687b ldr r3, [r7, #4] 8005172: 6a9b ldr r3, [r3, #40] @ 0x28 8005174: f403 7340 and.w r3, r3, #768 @ 0x300 8005178: 693a ldr r2, [r7, #16] 800517a: 429a cmp r2, r3 800517c: d028 beq.n 80051d0 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); 800517e: 4b2f ldr r3, [pc, #188] @ (800523c ) 8005180: 6f1b ldr r3, [r3, #112] @ 0x70 8005182: f423 7340 bic.w r3, r3, #768 @ 0x300 8005186: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 8005188: 4b2d ldr r3, [pc, #180] @ (8005240 ) 800518a: 2201 movs r2, #1 800518c: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); 800518e: 4b2c ldr r3, [pc, #176] @ (8005240 ) 8005190: 2200 movs r2, #0 8005192: 601a str r2, [r3, #0] /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; 8005194: 4a29 ldr r2, [pc, #164] @ (800523c ) 8005196: 693b ldr r3, [r7, #16] 8005198: 6713 str r3, [r2, #112] @ 0x70 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) 800519a: 4b28 ldr r3, [pc, #160] @ (800523c ) 800519c: 6f1b ldr r3, [r3, #112] @ 0x70 800519e: f003 0301 and.w r3, r3, #1 80051a2: 2b01 cmp r3, #1 80051a4: d114 bne.n 80051d0 { /* Get tick */ tickstart = HAL_GetTick(); 80051a6: f7fc fa57 bl 8001658 80051aa: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80051ac: e00a b.n 80051c4 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80051ae: f7fc fa53 bl 8001658 80051b2: 4602 mov r2, r0 80051b4: 697b ldr r3, [r7, #20] 80051b6: 1ad3 subs r3, r2, r3 80051b8: f241 3288 movw r2, #5000 @ 0x1388 80051bc: 4293 cmp r3, r2 80051be: d901 bls.n 80051c4 { return HAL_TIMEOUT; 80051c0: 2303 movs r3, #3 80051c2: e035 b.n 8005230 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) 80051c4: 4b1d ldr r3, [pc, #116] @ (800523c ) 80051c6: 6f1b ldr r3, [r3, #112] @ 0x70 80051c8: f003 0302 and.w r3, r3, #2 80051cc: 2b00 cmp r3, #0 80051ce: d0ee beq.n 80051ae } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 80051d0: 687b ldr r3, [r7, #4] 80051d2: 6a9b ldr r3, [r3, #40] @ 0x28 80051d4: f403 7340 and.w r3, r3, #768 @ 0x300 80051d8: f5b3 7f40 cmp.w r3, #768 @ 0x300 80051dc: d10d bne.n 80051fa 80051de: 4b17 ldr r3, [pc, #92] @ (800523c ) 80051e0: 689b ldr r3, [r3, #8] 80051e2: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000 80051e6: 687b ldr r3, [r7, #4] 80051e8: 6a9b ldr r3, [r3, #40] @ 0x28 80051ea: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000 80051ee: f423 7340 bic.w r3, r3, #768 @ 0x300 80051f2: 4912 ldr r1, [pc, #72] @ (800523c ) 80051f4: 4313 orrs r3, r2 80051f6: 608b str r3, [r1, #8] 80051f8: e005 b.n 8005206 80051fa: 4b10 ldr r3, [pc, #64] @ (800523c ) 80051fc: 689b ldr r3, [r3, #8] 80051fe: 4a0f ldr r2, [pc, #60] @ (800523c ) 8005200: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000 8005204: 6093 str r3, [r2, #8] 8005206: 4b0d ldr r3, [pc, #52] @ (800523c ) 8005208: 6f1a ldr r2, [r3, #112] @ 0x70 800520a: 687b ldr r3, [r7, #4] 800520c: 6a9b ldr r3, [r3, #40] @ 0x28 800520e: f3c3 030b ubfx r3, r3, #0, #12 8005212: 490a ldr r1, [pc, #40] @ (800523c ) 8005214: 4313 orrs r3, r2 8005216: 670b str r3, [r1, #112] @ 0x70 } /*--------------------------------------------------------------------------*/ /*---------------------------- TIM configuration ---------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) 8005218: 687b ldr r3, [r7, #4] 800521a: 681b ldr r3, [r3, #0] 800521c: f003 0310 and.w r3, r3, #16 8005220: 2b00 cmp r3, #0 8005222: d004 beq.n 800522e { __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); 8005224: 687b ldr r3, [r7, #4] 8005226: f893 202c ldrb.w r2, [r3, #44] @ 0x2c 800522a: 4b06 ldr r3, [pc, #24] @ (8005244 ) 800522c: 601a str r2, [r3, #0] } return HAL_OK; 800522e: 2300 movs r3, #0 } 8005230: 4618 mov r0, r3 8005232: 3718 adds r7, #24 8005234: 46bd mov sp, r7 8005236: bd80 pop {r7, pc} 8005238: 40007000 .word 0x40007000 800523c: 40023800 .word 0x40023800 8005240: 42470e40 .word 0x42470e40 8005244: 424711e0 .word 0x424711e0 08005248 : * the configuration information for SDRAM module. * @param Timing Pointer to SDRAM control timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) { 8005248: b580 push {r7, lr} 800524a: b082 sub sp, #8 800524c: af00 add r7, sp, #0 800524e: 6078 str r0, [r7, #4] 8005250: 6039 str r1, [r7, #0] /* Check the SDRAM handle parameter */ if (hsdram == NULL) 8005252: 687b ldr r3, [r7, #4] 8005254: 2b00 cmp r3, #0 8005256: d101 bne.n 800525c { return HAL_ERROR; 8005258: 2301 movs r3, #1 800525a: e025 b.n 80052a8 } if (hsdram->State == HAL_SDRAM_STATE_RESET) 800525c: 687b ldr r3, [r7, #4] 800525e: f893 302c ldrb.w r3, [r3, #44] @ 0x2c 8005262: b2db uxtb r3, r3 8005264: 2b00 cmp r3, #0 8005266: d106 bne.n 8005276 { /* Allocate lock resource and initialize it */ hsdram->Lock = HAL_UNLOCKED; 8005268: 687b ldr r3, [r7, #4] 800526a: 2200 movs r2, #0 800526c: f883 202d strb.w r2, [r3, #45] @ 0x2d /* Init the low level hardware */ hsdram->MspInitCallback(hsdram); #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); 8005270: 6878 ldr r0, [r7, #4] 8005272: f7fc f8b5 bl 80013e0 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /* Initialize the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_BUSY; 8005276: 687b ldr r3, [r7, #4] 8005278: 2202 movs r2, #2 800527a: f883 202c strb.w r2, [r3, #44] @ 0x2c /* Initialize SDRAM control Interface */ (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); 800527e: 687b ldr r3, [r7, #4] 8005280: 681a ldr r2, [r3, #0] 8005282: 687b ldr r3, [r7, #4] 8005284: 3304 adds r3, #4 8005286: 4619 mov r1, r3 8005288: 4610 mov r0, r2 800528a: f000 ffcd bl 8006228 /* Initialize SDRAM timing Interface */ (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 800528e: 687b ldr r3, [r7, #4] 8005290: 6818 ldr r0, [r3, #0] 8005292: 687b ldr r3, [r7, #4] 8005294: 685b ldr r3, [r3, #4] 8005296: 461a mov r2, r3 8005298: 6839 ldr r1, [r7, #0] 800529a: f001 f822 bl 80062e2 /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; 800529e: 687b ldr r3, [r7, #4] 80052a0: 2201 movs r2, #1 80052a2: f883 202c strb.w r2, [r3, #44] @ 0x2c return HAL_OK; 80052a6: 2300 movs r3, #0 } 80052a8: 4618 mov r0, r3 80052aa: 3708 adds r7, #8 80052ac: 46bd mov sp, r7 80052ae: bd80 pop {r7, pc} 080052b0 : * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { 80052b0: b580 push {r7, lr} 80052b2: b082 sub sp, #8 80052b4: af00 add r7, sp, #0 80052b6: 6078 str r0, [r7, #4] /* Check the SPI handle allocation */ if (hspi == NULL) 80052b8: 687b ldr r3, [r7, #4] 80052ba: 2b00 cmp r3, #0 80052bc: d101 bne.n 80052c2 { return HAL_ERROR; 80052be: 2301 movs r3, #1 80052c0: e07b b.n 80053ba assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) 80052c2: 687b ldr r3, [r7, #4] 80052c4: 6a5b ldr r3, [r3, #36] @ 0x24 80052c6: 2b00 cmp r3, #0 80052c8: d108 bne.n 80052dc { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); if (hspi->Init.Mode == SPI_MODE_MASTER) 80052ca: 687b ldr r3, [r7, #4] 80052cc: 685b ldr r3, [r3, #4] 80052ce: f5b3 7f82 cmp.w r3, #260 @ 0x104 80052d2: d009 beq.n 80052e8 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); } else { /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 80052d4: 687b ldr r3, [r7, #4] 80052d6: 2200 movs r2, #0 80052d8: 61da str r2, [r3, #28] 80052da: e005 b.n 80052e8 else { assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); /* Force polarity and phase to TI protocaol requirements */ hspi->Init.CLKPolarity = SPI_POLARITY_LOW; 80052dc: 687b ldr r3, [r7, #4] 80052de: 2200 movs r2, #0 80052e0: 611a str r2, [r3, #16] hspi->Init.CLKPhase = SPI_PHASE_1EDGE; 80052e2: 687b ldr r3, [r7, #4] 80052e4: 2200 movs r2, #0 80052e6: 615a str r2, [r3, #20] if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); } #else hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 80052e8: 687b ldr r3, [r7, #4] 80052ea: 2200 movs r2, #0 80052ec: 629a str r2, [r3, #40] @ 0x28 #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) 80052ee: 687b ldr r3, [r7, #4] 80052f0: f893 3051 ldrb.w r3, [r3, #81] @ 0x51 80052f4: b2db uxtb r3, r3 80052f6: 2b00 cmp r3, #0 80052f8: d106 bne.n 8005308 { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; 80052fa: 687b ldr r3, [r7, #4] 80052fc: 2200 movs r2, #0 80052fe: f883 2050 strb.w r2, [r3, #80] @ 0x50 /* Init the low level hardware : GPIO, CLOCK, NVIC... */ hspi->MspInitCallback(hspi); #else /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); 8005302: 6878 ldr r0, [r7, #4] 8005304: f7fb ff28 bl 8001158 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ } hspi->State = HAL_SPI_STATE_BUSY; 8005308: 687b ldr r3, [r7, #4] 800530a: 2202 movs r2, #2 800530c: f883 2051 strb.w r2, [r3, #81] @ 0x51 /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); 8005310: 687b ldr r3, [r7, #4] 8005312: 681b ldr r3, [r3, #0] 8005314: 681a ldr r2, [r3, #0] 8005316: 687b ldr r3, [r7, #4] 8005318: 681b ldr r3, [r3, #0] 800531a: f022 0240 bic.w r2, r2, #64 @ 0x40 800531e: 601a str r2, [r3, #0] /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | 8005320: 687b ldr r3, [r7, #4] 8005322: 685b ldr r3, [r3, #4] 8005324: f403 7282 and.w r2, r3, #260 @ 0x104 8005328: 687b ldr r3, [r7, #4] 800532a: 689b ldr r3, [r3, #8] 800532c: f403 4304 and.w r3, r3, #33792 @ 0x8400 8005330: 431a orrs r2, r3 8005332: 687b ldr r3, [r7, #4] 8005334: 68db ldr r3, [r3, #12] 8005336: f403 6300 and.w r3, r3, #2048 @ 0x800 800533a: 431a orrs r2, r3 800533c: 687b ldr r3, [r7, #4] 800533e: 691b ldr r3, [r3, #16] 8005340: f003 0302 and.w r3, r3, #2 8005344: 431a orrs r2, r3 8005346: 687b ldr r3, [r7, #4] 8005348: 695b ldr r3, [r3, #20] 800534a: f003 0301 and.w r3, r3, #1 800534e: 431a orrs r2, r3 8005350: 687b ldr r3, [r7, #4] 8005352: 699b ldr r3, [r3, #24] 8005354: f403 7300 and.w r3, r3, #512 @ 0x200 8005358: 431a orrs r2, r3 800535a: 687b ldr r3, [r7, #4] 800535c: 69db ldr r3, [r3, #28] 800535e: f003 0338 and.w r3, r3, #56 @ 0x38 8005362: 431a orrs r2, r3 8005364: 687b ldr r3, [r7, #4] 8005366: 6a1b ldr r3, [r3, #32] 8005368: f003 0380 and.w r3, r3, #128 @ 0x80 800536c: ea42 0103 orr.w r1, r2, r3 8005370: 687b ldr r3, [r7, #4] 8005372: 6a9b ldr r3, [r3, #40] @ 0x28 8005374: f403 5200 and.w r2, r3, #8192 @ 0x2000 8005378: 687b ldr r3, [r7, #4] 800537a: 681b ldr r3, [r3, #0] 800537c: 430a orrs r2, r1 800537e: 601a str r2, [r3, #0] (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); /* Configure : NSS management, TI Mode */ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF))); 8005380: 687b ldr r3, [r7, #4] 8005382: 699b ldr r3, [r3, #24] 8005384: 0c1b lsrs r3, r3, #16 8005386: f003 0104 and.w r1, r3, #4 800538a: 687b ldr r3, [r7, #4] 800538c: 6a5b ldr r3, [r3, #36] @ 0x24 800538e: f003 0210 and.w r2, r3, #16 8005392: 687b ldr r3, [r7, #4] 8005394: 681b ldr r3, [r3, #0] 8005396: 430a orrs r2, r1 8005398: 605a str r2, [r3, #4] } #endif /* USE_SPI_CRC */ #if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); 800539a: 687b ldr r3, [r7, #4] 800539c: 681b ldr r3, [r3, #0] 800539e: 69da ldr r2, [r3, #28] 80053a0: 687b ldr r3, [r7, #4] 80053a2: 681b ldr r3, [r3, #0] 80053a4: f422 6200 bic.w r2, r2, #2048 @ 0x800 80053a8: 61da str r2, [r3, #28] #endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; 80053aa: 687b ldr r3, [r7, #4] 80053ac: 2200 movs r2, #0 80053ae: 655a str r2, [r3, #84] @ 0x54 hspi->State = HAL_SPI_STATE_READY; 80053b0: 687b ldr r3, [r7, #4] 80053b2: 2201 movs r2, #1 80053b4: f883 2051 strb.w r2, [r3, #81] @ 0x51 return HAL_OK; 80053b8: 2300 movs r3, #0 } 80053ba: 4618 mov r0, r3 80053bc: 3708 adds r7, #8 80053be: 46bd mov sp, r7 80053c0: bd80 pop {r7, pc} 080053c2 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 80053c2: b580 push {r7, lr} 80053c4: b082 sub sp, #8 80053c6: af00 add r7, sp, #0 80053c8: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 80053ca: 687b ldr r3, [r7, #4] 80053cc: 2b00 cmp r3, #0 80053ce: d101 bne.n 80053d4 { return HAL_ERROR; 80053d0: 2301 movs r3, #1 80053d2: e041 b.n 8005458 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 80053d4: 687b ldr r3, [r7, #4] 80053d6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 80053da: b2db uxtb r3, r3 80053dc: 2b00 cmp r3, #0 80053de: d106 bne.n 80053ee { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 80053e0: 687b ldr r3, [r7, #4] 80053e2: 2200 movs r2, #0 80053e4: f883 203c strb.w r2, [r3, #60] @ 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 80053e8: 6878 ldr r0, [r7, #4] 80053ea: f7fb fefd bl 80011e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80053ee: 687b ldr r3, [r7, #4] 80053f0: 2202 movs r2, #2 80053f2: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80053f6: 687b ldr r3, [r7, #4] 80053f8: 681a ldr r2, [r3, #0] 80053fa: 687b ldr r3, [r7, #4] 80053fc: 3304 adds r3, #4 80053fe: 4619 mov r1, r3 8005400: 4610 mov r0, r2 8005402: f000 fa7d bl 8005900 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005406: 687b ldr r3, [r7, #4] 8005408: 2201 movs r2, #1 800540a: f883 2046 strb.w r2, [r3, #70] @ 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800540e: 687b ldr r3, [r7, #4] 8005410: 2201 movs r2, #1 8005412: f883 203e strb.w r2, [r3, #62] @ 0x3e 8005416: 687b ldr r3, [r7, #4] 8005418: 2201 movs r2, #1 800541a: f883 203f strb.w r2, [r3, #63] @ 0x3f 800541e: 687b ldr r3, [r7, #4] 8005420: 2201 movs r2, #1 8005422: f883 2040 strb.w r2, [r3, #64] @ 0x40 8005426: 687b ldr r3, [r7, #4] 8005428: 2201 movs r2, #1 800542a: f883 2041 strb.w r2, [r3, #65] @ 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 800542e: 687b ldr r3, [r7, #4] 8005430: 2201 movs r2, #1 8005432: f883 2042 strb.w r2, [r3, #66] @ 0x42 8005436: 687b ldr r3, [r7, #4] 8005438: 2201 movs r2, #1 800543a: f883 2043 strb.w r2, [r3, #67] @ 0x43 800543e: 687b ldr r3, [r7, #4] 8005440: 2201 movs r2, #1 8005442: f883 2044 strb.w r2, [r3, #68] @ 0x44 8005446: 687b ldr r3, [r7, #4] 8005448: 2201 movs r2, #1 800544a: f883 2045 strb.w r2, [r3, #69] @ 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 800544e: 687b ldr r3, [r7, #4] 8005450: 2201 movs r2, #1 8005452: f883 203d strb.w r2, [r3, #61] @ 0x3d return HAL_OK; 8005456: 2300 movs r3, #0 } 8005458: 4618 mov r0, r3 800545a: 3708 adds r7, #8 800545c: 46bd mov sp, r7 800545e: bd80 pop {r7, pc} 08005460 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8005460: b480 push {r7} 8005462: b085 sub sp, #20 8005464: af00 add r7, sp, #0 8005466: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8005468: 687b ldr r3, [r7, #4] 800546a: f893 303d ldrb.w r3, [r3, #61] @ 0x3d 800546e: b2db uxtb r3, r3 8005470: 2b01 cmp r3, #1 8005472: d001 beq.n 8005478 { return HAL_ERROR; 8005474: 2301 movs r3, #1 8005476: e04e b.n 8005516 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005478: 687b ldr r3, [r7, #4] 800547a: 2202 movs r2, #2 800547c: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8005480: 687b ldr r3, [r7, #4] 8005482: 681b ldr r3, [r3, #0] 8005484: 68da ldr r2, [r3, #12] 8005486: 687b ldr r3, [r7, #4] 8005488: 681b ldr r3, [r3, #0] 800548a: f042 0201 orr.w r2, r2, #1 800548e: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005490: 687b ldr r3, [r7, #4] 8005492: 681b ldr r3, [r3, #0] 8005494: 4a23 ldr r2, [pc, #140] @ (8005524 ) 8005496: 4293 cmp r3, r2 8005498: d022 beq.n 80054e0 800549a: 687b ldr r3, [r7, #4] 800549c: 681b ldr r3, [r3, #0] 800549e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 80054a2: d01d beq.n 80054e0 80054a4: 687b ldr r3, [r7, #4] 80054a6: 681b ldr r3, [r3, #0] 80054a8: 4a1f ldr r2, [pc, #124] @ (8005528 ) 80054aa: 4293 cmp r3, r2 80054ac: d018 beq.n 80054e0 80054ae: 687b ldr r3, [r7, #4] 80054b0: 681b ldr r3, [r3, #0] 80054b2: 4a1e ldr r2, [pc, #120] @ (800552c ) 80054b4: 4293 cmp r3, r2 80054b6: d013 beq.n 80054e0 80054b8: 687b ldr r3, [r7, #4] 80054ba: 681b ldr r3, [r3, #0] 80054bc: 4a1c ldr r2, [pc, #112] @ (8005530 ) 80054be: 4293 cmp r3, r2 80054c0: d00e beq.n 80054e0 80054c2: 687b ldr r3, [r7, #4] 80054c4: 681b ldr r3, [r3, #0] 80054c6: 4a1b ldr r2, [pc, #108] @ (8005534 ) 80054c8: 4293 cmp r3, r2 80054ca: d009 beq.n 80054e0 80054cc: 687b ldr r3, [r7, #4] 80054ce: 681b ldr r3, [r3, #0] 80054d0: 4a19 ldr r2, [pc, #100] @ (8005538 ) 80054d2: 4293 cmp r3, r2 80054d4: d004 beq.n 80054e0 80054d6: 687b ldr r3, [r7, #4] 80054d8: 681b ldr r3, [r3, #0] 80054da: 4a18 ldr r2, [pc, #96] @ (800553c ) 80054dc: 4293 cmp r3, r2 80054de: d111 bne.n 8005504 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80054e0: 687b ldr r3, [r7, #4] 80054e2: 681b ldr r3, [r3, #0] 80054e4: 689b ldr r3, [r3, #8] 80054e6: f003 0307 and.w r3, r3, #7 80054ea: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80054ec: 68fb ldr r3, [r7, #12] 80054ee: 2b06 cmp r3, #6 80054f0: d010 beq.n 8005514 { __HAL_TIM_ENABLE(htim); 80054f2: 687b ldr r3, [r7, #4] 80054f4: 681b ldr r3, [r3, #0] 80054f6: 681a ldr r2, [r3, #0] 80054f8: 687b ldr r3, [r7, #4] 80054fa: 681b ldr r3, [r3, #0] 80054fc: f042 0201 orr.w r2, r2, #1 8005500: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005502: e007 b.n 8005514 } } else { __HAL_TIM_ENABLE(htim); 8005504: 687b ldr r3, [r7, #4] 8005506: 681b ldr r3, [r3, #0] 8005508: 681a ldr r2, [r3, #0] 800550a: 687b ldr r3, [r7, #4] 800550c: 681b ldr r3, [r3, #0] 800550e: f042 0201 orr.w r2, r2, #1 8005512: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; 8005514: 2300 movs r3, #0 } 8005516: 4618 mov r0, r3 8005518: 3714 adds r7, #20 800551a: 46bd mov sp, r7 800551c: f85d 7b04 ldr.w r7, [sp], #4 8005520: 4770 bx lr 8005522: bf00 nop 8005524: 40010000 .word 0x40010000 8005528: 40000400 .word 0x40000400 800552c: 40000800 .word 0x40000800 8005530: 40000c00 .word 0x40000c00 8005534: 40010400 .word 0x40010400 8005538: 40014000 .word 0x40014000 800553c: 40001800 .word 0x40001800 08005540 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005540: b580 push {r7, lr} 8005542: b084 sub sp, #16 8005544: af00 add r7, sp, #0 8005546: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8005548: 687b ldr r3, [r7, #4] 800554a: 681b ldr r3, [r3, #0] 800554c: 68db ldr r3, [r3, #12] 800554e: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8005550: 687b ldr r3, [r7, #4] 8005552: 681b ldr r3, [r3, #0] 8005554: 691b ldr r3, [r3, #16] 8005556: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8005558: 68bb ldr r3, [r7, #8] 800555a: f003 0302 and.w r3, r3, #2 800555e: 2b00 cmp r3, #0 8005560: d020 beq.n 80055a4 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8005562: 68fb ldr r3, [r7, #12] 8005564: f003 0302 and.w r3, r3, #2 8005568: 2b00 cmp r3, #0 800556a: d01b beq.n 80055a4 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 800556c: 687b ldr r3, [r7, #4] 800556e: 681b ldr r3, [r3, #0] 8005570: f06f 0202 mvn.w r2, #2 8005574: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8005576: 687b ldr r3, [r7, #4] 8005578: 2201 movs r2, #1 800557a: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 800557c: 687b ldr r3, [r7, #4] 800557e: 681b ldr r3, [r3, #0] 8005580: 699b ldr r3, [r3, #24] 8005582: f003 0303 and.w r3, r3, #3 8005586: 2b00 cmp r3, #0 8005588: d003 beq.n 8005592 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800558a: 6878 ldr r0, [r7, #4] 800558c: f000 f999 bl 80058c2 8005590: e005 b.n 800559e { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005592: 6878 ldr r0, [r7, #4] 8005594: f000 f98b bl 80058ae HAL_TIM_PWM_PulseFinishedCallback(htim); 8005598: 6878 ldr r0, [r7, #4] 800559a: f000 f99c bl 80058d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 800559e: 687b ldr r3, [r7, #4] 80055a0: 2200 movs r2, #0 80055a2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 80055a4: 68bb ldr r3, [r7, #8] 80055a6: f003 0304 and.w r3, r3, #4 80055aa: 2b00 cmp r3, #0 80055ac: d020 beq.n 80055f0 { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 80055ae: 68fb ldr r3, [r7, #12] 80055b0: f003 0304 and.w r3, r3, #4 80055b4: 2b00 cmp r3, #0 80055b6: d01b beq.n 80055f0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 80055b8: 687b ldr r3, [r7, #4] 80055ba: 681b ldr r3, [r3, #0] 80055bc: f06f 0204 mvn.w r2, #4 80055c0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 80055c2: 687b ldr r3, [r7, #4] 80055c4: 2202 movs r2, #2 80055c6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 80055c8: 687b ldr r3, [r7, #4] 80055ca: 681b ldr r3, [r3, #0] 80055cc: 699b ldr r3, [r3, #24] 80055ce: f403 7340 and.w r3, r3, #768 @ 0x300 80055d2: 2b00 cmp r3, #0 80055d4: d003 beq.n 80055de { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 80055d6: 6878 ldr r0, [r7, #4] 80055d8: f000 f973 bl 80058c2 80055dc: e005 b.n 80055ea { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 80055de: 6878 ldr r0, [r7, #4] 80055e0: f000 f965 bl 80058ae HAL_TIM_PWM_PulseFinishedCallback(htim); 80055e4: 6878 ldr r0, [r7, #4] 80055e6: f000 f976 bl 80058d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 80055ea: 687b ldr r3, [r7, #4] 80055ec: 2200 movs r2, #0 80055ee: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 80055f0: 68bb ldr r3, [r7, #8] 80055f2: f003 0308 and.w r3, r3, #8 80055f6: 2b00 cmp r3, #0 80055f8: d020 beq.n 800563c { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 80055fa: 68fb ldr r3, [r7, #12] 80055fc: f003 0308 and.w r3, r3, #8 8005600: 2b00 cmp r3, #0 8005602: d01b beq.n 800563c { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8005604: 687b ldr r3, [r7, #4] 8005606: 681b ldr r3, [r3, #0] 8005608: f06f 0208 mvn.w r2, #8 800560c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 800560e: 687b ldr r3, [r7, #4] 8005610: 2204 movs r2, #4 8005612: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8005614: 687b ldr r3, [r7, #4] 8005616: 681b ldr r3, [r3, #0] 8005618: 69db ldr r3, [r3, #28] 800561a: f003 0303 and.w r3, r3, #3 800561e: 2b00 cmp r3, #0 8005620: d003 beq.n 800562a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005622: 6878 ldr r0, [r7, #4] 8005624: f000 f94d bl 80058c2 8005628: e005 b.n 8005636 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 800562a: 6878 ldr r0, [r7, #4] 800562c: f000 f93f bl 80058ae HAL_TIM_PWM_PulseFinishedCallback(htim); 8005630: 6878 ldr r0, [r7, #4] 8005632: f000 f950 bl 80058d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005636: 687b ldr r3, [r7, #4] 8005638: 2200 movs r2, #0 800563a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 800563c: 68bb ldr r3, [r7, #8] 800563e: f003 0310 and.w r3, r3, #16 8005642: 2b00 cmp r3, #0 8005644: d020 beq.n 8005688 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8005646: 68fb ldr r3, [r7, #12] 8005648: f003 0310 and.w r3, r3, #16 800564c: 2b00 cmp r3, #0 800564e: d01b beq.n 8005688 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8005650: 687b ldr r3, [r7, #4] 8005652: 681b ldr r3, [r3, #0] 8005654: f06f 0210 mvn.w r2, #16 8005658: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 800565a: 687b ldr r3, [r7, #4] 800565c: 2208 movs r2, #8 800565e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005660: 687b ldr r3, [r7, #4] 8005662: 681b ldr r3, [r3, #0] 8005664: 69db ldr r3, [r3, #28] 8005666: f403 7340 and.w r3, r3, #768 @ 0x300 800566a: 2b00 cmp r3, #0 800566c: d003 beq.n 8005676 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 800566e: 6878 ldr r0, [r7, #4] 8005670: f000 f927 bl 80058c2 8005674: e005 b.n 8005682 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005676: 6878 ldr r0, [r7, #4] 8005678: f000 f919 bl 80058ae HAL_TIM_PWM_PulseFinishedCallback(htim); 800567c: 6878 ldr r0, [r7, #4] 800567e: f000 f92a bl 80058d6 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005682: 687b ldr r3, [r7, #4] 8005684: 2200 movs r2, #0 8005686: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8005688: 68bb ldr r3, [r7, #8] 800568a: f003 0301 and.w r3, r3, #1 800568e: 2b00 cmp r3, #0 8005690: d00c beq.n 80056ac { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8005692: 68fb ldr r3, [r7, #12] 8005694: f003 0301 and.w r3, r3, #1 8005698: 2b00 cmp r3, #0 800569a: d007 beq.n 80056ac { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 800569c: 687b ldr r3, [r7, #4] 800569e: 681b ldr r3, [r3, #0] 80056a0: f06f 0201 mvn.w r2, #1 80056a4: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 80056a6: 6878 ldr r0, [r7, #4] 80056a8: f7fb fb2e bl 8000d08 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) 80056ac: 68bb ldr r3, [r7, #8] 80056ae: f003 0380 and.w r3, r3, #128 @ 0x80 80056b2: 2b00 cmp r3, #0 80056b4: d00c beq.n 80056d0 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 80056b6: 68fb ldr r3, [r7, #12] 80056b8: f003 0380 and.w r3, r3, #128 @ 0x80 80056bc: 2b00 cmp r3, #0 80056be: d007 beq.n 80056d0 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK); 80056c0: 687b ldr r3, [r7, #4] 80056c2: 681b ldr r3, [r3, #0] 80056c4: f06f 0280 mvn.w r2, #128 @ 0x80 80056c8: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 80056ca: 6878 ldr r0, [r7, #4] 80056cc: f000 fade bl 8005c8c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 80056d0: 68bb ldr r3, [r7, #8] 80056d2: f003 0340 and.w r3, r3, #64 @ 0x40 80056d6: 2b00 cmp r3, #0 80056d8: d00c beq.n 80056f4 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 80056da: 68fb ldr r3, [r7, #12] 80056dc: f003 0340 and.w r3, r3, #64 @ 0x40 80056e0: 2b00 cmp r3, #0 80056e2: d007 beq.n 80056f4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 80056e4: 687b ldr r3, [r7, #4] 80056e6: 681b ldr r3, [r3, #0] 80056e8: f06f 0240 mvn.w r2, #64 @ 0x40 80056ec: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 80056ee: 6878 ldr r0, [r7, #4] 80056f0: f000 f8fb bl 80058ea #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 80056f4: 68bb ldr r3, [r7, #8] 80056f6: f003 0320 and.w r3, r3, #32 80056fa: 2b00 cmp r3, #0 80056fc: d00c beq.n 8005718 { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 80056fe: 68fb ldr r3, [r7, #12] 8005700: f003 0320 and.w r3, r3, #32 8005704: 2b00 cmp r3, #0 8005706: d007 beq.n 8005718 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8005708: 687b ldr r3, [r7, #4] 800570a: 681b ldr r3, [r3, #0] 800570c: f06f 0220 mvn.w r2, #32 8005710: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8005712: 6878 ldr r0, [r7, #4] 8005714: f000 fab0 bl 8005c78 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8005718: bf00 nop 800571a: 3710 adds r7, #16 800571c: 46bd mov sp, r7 800571e: bd80 pop {r7, pc} 08005720 : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8005720: b580 push {r7, lr} 8005722: b084 sub sp, #16 8005724: af00 add r7, sp, #0 8005726: 6078 str r0, [r7, #4] 8005728: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800572a: 2300 movs r3, #0 800572c: 73fb strb r3, [r7, #15] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 800572e: 687b ldr r3, [r7, #4] 8005730: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005734: 2b01 cmp r3, #1 8005736: d101 bne.n 800573c 8005738: 2302 movs r3, #2 800573a: e0b4 b.n 80058a6 800573c: 687b ldr r3, [r7, #4] 800573e: 2201 movs r2, #1 8005740: f883 203c strb.w r2, [r3, #60] @ 0x3c htim->State = HAL_TIM_STATE_BUSY; 8005744: 687b ldr r3, [r7, #4] 8005746: 2202 movs r2, #2 8005748: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 800574c: 687b ldr r3, [r7, #4] 800574e: 681b ldr r3, [r3, #0] 8005750: 689b ldr r3, [r3, #8] 8005752: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8005754: 68bb ldr r3, [r7, #8] 8005756: f023 0377 bic.w r3, r3, #119 @ 0x77 800575a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 800575c: 68bb ldr r3, [r7, #8] 800575e: f423 437f bic.w r3, r3, #65280 @ 0xff00 8005762: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8005764: 687b ldr r3, [r7, #4] 8005766: 681b ldr r3, [r3, #0] 8005768: 68ba ldr r2, [r7, #8] 800576a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 800576c: 683b ldr r3, [r7, #0] 800576e: 681b ldr r3, [r3, #0] 8005770: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 8005774: d03e beq.n 80057f4 8005776: f5b3 5f00 cmp.w r3, #8192 @ 0x2000 800577a: f200 8087 bhi.w 800588c 800577e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 8005782: f000 8086 beq.w 8005892 8005786: f5b3 5f80 cmp.w r3, #4096 @ 0x1000 800578a: d87f bhi.n 800588c 800578c: 2b70 cmp r3, #112 @ 0x70 800578e: d01a beq.n 80057c6 8005790: 2b70 cmp r3, #112 @ 0x70 8005792: d87b bhi.n 800588c 8005794: 2b60 cmp r3, #96 @ 0x60 8005796: d050 beq.n 800583a 8005798: 2b60 cmp r3, #96 @ 0x60 800579a: d877 bhi.n 800588c 800579c: 2b50 cmp r3, #80 @ 0x50 800579e: d03c beq.n 800581a 80057a0: 2b50 cmp r3, #80 @ 0x50 80057a2: d873 bhi.n 800588c 80057a4: 2b40 cmp r3, #64 @ 0x40 80057a6: d058 beq.n 800585a 80057a8: 2b40 cmp r3, #64 @ 0x40 80057aa: d86f bhi.n 800588c 80057ac: 2b30 cmp r3, #48 @ 0x30 80057ae: d064 beq.n 800587a 80057b0: 2b30 cmp r3, #48 @ 0x30 80057b2: d86b bhi.n 800588c 80057b4: 2b20 cmp r3, #32 80057b6: d060 beq.n 800587a 80057b8: 2b20 cmp r3, #32 80057ba: d867 bhi.n 800588c 80057bc: 2b00 cmp r3, #0 80057be: d05c beq.n 800587a 80057c0: 2b10 cmp r3, #16 80057c2: d05a beq.n 800587a 80057c4: e062 b.n 800588c assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80057c6: 687b ldr r3, [r7, #4] 80057c8: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80057ca: 683b ldr r3, [r7, #0] 80057cc: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80057ce: 683b ldr r3, [r7, #0] 80057d0: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 80057d2: 683b ldr r3, [r7, #0] 80057d4: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 80057d6: f000 f9b3 bl 8005b40 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 80057da: 687b ldr r3, [r7, #4] 80057dc: 681b ldr r3, [r3, #0] 80057de: 689b ldr r3, [r3, #8] 80057e0: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 80057e2: 68bb ldr r3, [r7, #8] 80057e4: f043 0377 orr.w r3, r3, #119 @ 0x77 80057e8: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 80057ea: 687b ldr r3, [r7, #4] 80057ec: 681b ldr r3, [r3, #0] 80057ee: 68ba ldr r2, [r7, #8] 80057f0: 609a str r2, [r3, #8] break; 80057f2: e04f b.n 8005894 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 80057f4: 687b ldr r3, [r7, #4] 80057f6: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 80057f8: 683b ldr r3, [r7, #0] 80057fa: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 80057fc: 683b ldr r3, [r7, #0] 80057fe: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8005800: 683b ldr r3, [r7, #0] 8005802: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8005804: f000 f99c bl 8005b40 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 8005808: 687b ldr r3, [r7, #4] 800580a: 681b ldr r3, [r3, #0] 800580c: 689a ldr r2, [r3, #8] 800580e: 687b ldr r3, [r7, #4] 8005810: 681b ldr r3, [r3, #0] 8005812: f442 4280 orr.w r2, r2, #16384 @ 0x4000 8005816: 609a str r2, [r3, #8] break; 8005818: e03c b.n 8005894 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800581a: 687b ldr r3, [r7, #4] 800581c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800581e: 683b ldr r3, [r7, #0] 8005820: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8005822: 683b ldr r3, [r7, #0] 8005824: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8005826: 461a mov r2, r3 8005828: f000 f910 bl 8005a4c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 800582c: 687b ldr r3, [r7, #4] 800582e: 681b ldr r3, [r3, #0] 8005830: 2150 movs r1, #80 @ 0x50 8005832: 4618 mov r0, r3 8005834: f000 f969 bl 8005b0a break; 8005838: e02c b.n 8005894 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 800583a: 687b ldr r3, [r7, #4] 800583c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800583e: 683b ldr r3, [r7, #0] 8005840: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8005842: 683b ldr r3, [r7, #0] 8005844: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 8005846: 461a mov r2, r3 8005848: f000 f92f bl 8005aaa TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 800584c: 687b ldr r3, [r7, #4] 800584e: 681b ldr r3, [r3, #0] 8005850: 2160 movs r1, #96 @ 0x60 8005852: 4618 mov r0, r3 8005854: f000 f959 bl 8005b0a break; 8005858: e01c b.n 8005894 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 800585a: 687b ldr r3, [r7, #4] 800585c: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 800585e: 683b ldr r3, [r7, #0] 8005860: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 8005862: 683b ldr r3, [r7, #0] 8005864: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 8005866: 461a mov r2, r3 8005868: f000 f8f0 bl 8005a4c TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 800586c: 687b ldr r3, [r7, #4] 800586e: 681b ldr r3, [r3, #0] 8005870: 2140 movs r1, #64 @ 0x40 8005872: 4618 mov r0, r3 8005874: f000 f949 bl 8005b0a break; 8005878: e00c b.n 8005894 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 800587a: 687b ldr r3, [r7, #4] 800587c: 681a ldr r2, [r3, #0] 800587e: 683b ldr r3, [r7, #0] 8005880: 681b ldr r3, [r3, #0] 8005882: 4619 mov r1, r3 8005884: 4610 mov r0, r2 8005886: f000 f940 bl 8005b0a break; 800588a: e003 b.n 8005894 } default: status = HAL_ERROR; 800588c: 2301 movs r3, #1 800588e: 73fb strb r3, [r7, #15] break; 8005890: e000 b.n 8005894 break; 8005892: bf00 nop } htim->State = HAL_TIM_STATE_READY; 8005894: 687b ldr r3, [r7, #4] 8005896: 2201 movs r2, #1 8005898: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 800589c: 687b ldr r3, [r7, #4] 800589e: 2200 movs r2, #0 80058a0: f883 203c strb.w r2, [r3, #60] @ 0x3c return status; 80058a4: 7bfb ldrb r3, [r7, #15] } 80058a6: 4618 mov r0, r3 80058a8: 3710 adds r7, #16 80058aa: 46bd mov sp, r7 80058ac: bd80 pop {r7, pc} 080058ae : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80058ae: b480 push {r7} 80058b0: b083 sub sp, #12 80058b2: af00 add r7, sp, #0 80058b4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80058b6: bf00 nop 80058b8: 370c adds r7, #12 80058ba: 46bd mov sp, r7 80058bc: f85d 7b04 ldr.w r7, [sp], #4 80058c0: 4770 bx lr 080058c2 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80058c2: b480 push {r7} 80058c4: b083 sub sp, #12 80058c6: af00 add r7, sp, #0 80058c8: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80058ca: bf00 nop 80058cc: 370c adds r7, #12 80058ce: 46bd mov sp, r7 80058d0: f85d 7b04 ldr.w r7, [sp], #4 80058d4: 4770 bx lr 080058d6 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80058d6: b480 push {r7} 80058d8: b083 sub sp, #12 80058da: af00 add r7, sp, #0 80058dc: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80058de: bf00 nop 80058e0: 370c adds r7, #12 80058e2: 46bd mov sp, r7 80058e4: f85d 7b04 ldr.w r7, [sp], #4 80058e8: 4770 bx lr 080058ea : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80058ea: b480 push {r7} 80058ec: b083 sub sp, #12 80058ee: af00 add r7, sp, #0 80058f0: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 80058f2: bf00 nop 80058f4: 370c adds r7, #12 80058f6: 46bd mov sp, r7 80058f8: f85d 7b04 ldr.w r7, [sp], #4 80058fc: 4770 bx lr ... 08005900 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8005900: b480 push {r7} 8005902: b085 sub sp, #20 8005904: af00 add r7, sp, #0 8005906: 6078 str r0, [r7, #4] 8005908: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 800590a: 687b ldr r3, [r7, #4] 800590c: 681b ldr r3, [r3, #0] 800590e: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8005910: 687b ldr r3, [r7, #4] 8005912: 4a43 ldr r2, [pc, #268] @ (8005a20 ) 8005914: 4293 cmp r3, r2 8005916: d013 beq.n 8005940 8005918: 687b ldr r3, [r7, #4] 800591a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 800591e: d00f beq.n 8005940 8005920: 687b ldr r3, [r7, #4] 8005922: 4a40 ldr r2, [pc, #256] @ (8005a24 ) 8005924: 4293 cmp r3, r2 8005926: d00b beq.n 8005940 8005928: 687b ldr r3, [r7, #4] 800592a: 4a3f ldr r2, [pc, #252] @ (8005a28 ) 800592c: 4293 cmp r3, r2 800592e: d007 beq.n 8005940 8005930: 687b ldr r3, [r7, #4] 8005932: 4a3e ldr r2, [pc, #248] @ (8005a2c ) 8005934: 4293 cmp r3, r2 8005936: d003 beq.n 8005940 8005938: 687b ldr r3, [r7, #4] 800593a: 4a3d ldr r2, [pc, #244] @ (8005a30 ) 800593c: 4293 cmp r3, r2 800593e: d108 bne.n 8005952 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8005940: 68fb ldr r3, [r7, #12] 8005942: f023 0370 bic.w r3, r3, #112 @ 0x70 8005946: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 8005948: 683b ldr r3, [r7, #0] 800594a: 685b ldr r3, [r3, #4] 800594c: 68fa ldr r2, [r7, #12] 800594e: 4313 orrs r3, r2 8005950: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8005952: 687b ldr r3, [r7, #4] 8005954: 4a32 ldr r2, [pc, #200] @ (8005a20 ) 8005956: 4293 cmp r3, r2 8005958: d02b beq.n 80059b2 800595a: 687b ldr r3, [r7, #4] 800595c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005960: d027 beq.n 80059b2 8005962: 687b ldr r3, [r7, #4] 8005964: 4a2f ldr r2, [pc, #188] @ (8005a24 ) 8005966: 4293 cmp r3, r2 8005968: d023 beq.n 80059b2 800596a: 687b ldr r3, [r7, #4] 800596c: 4a2e ldr r2, [pc, #184] @ (8005a28 ) 800596e: 4293 cmp r3, r2 8005970: d01f beq.n 80059b2 8005972: 687b ldr r3, [r7, #4] 8005974: 4a2d ldr r2, [pc, #180] @ (8005a2c ) 8005976: 4293 cmp r3, r2 8005978: d01b beq.n 80059b2 800597a: 687b ldr r3, [r7, #4] 800597c: 4a2c ldr r2, [pc, #176] @ (8005a30 ) 800597e: 4293 cmp r3, r2 8005980: d017 beq.n 80059b2 8005982: 687b ldr r3, [r7, #4] 8005984: 4a2b ldr r2, [pc, #172] @ (8005a34 ) 8005986: 4293 cmp r3, r2 8005988: d013 beq.n 80059b2 800598a: 687b ldr r3, [r7, #4] 800598c: 4a2a ldr r2, [pc, #168] @ (8005a38 ) 800598e: 4293 cmp r3, r2 8005990: d00f beq.n 80059b2 8005992: 687b ldr r3, [r7, #4] 8005994: 4a29 ldr r2, [pc, #164] @ (8005a3c ) 8005996: 4293 cmp r3, r2 8005998: d00b beq.n 80059b2 800599a: 687b ldr r3, [r7, #4] 800599c: 4a28 ldr r2, [pc, #160] @ (8005a40 ) 800599e: 4293 cmp r3, r2 80059a0: d007 beq.n 80059b2 80059a2: 687b ldr r3, [r7, #4] 80059a4: 4a27 ldr r2, [pc, #156] @ (8005a44 ) 80059a6: 4293 cmp r3, r2 80059a8: d003 beq.n 80059b2 80059aa: 687b ldr r3, [r7, #4] 80059ac: 4a26 ldr r2, [pc, #152] @ (8005a48 ) 80059ae: 4293 cmp r3, r2 80059b0: d108 bne.n 80059c4 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 80059b2: 68fb ldr r3, [r7, #12] 80059b4: f423 7340 bic.w r3, r3, #768 @ 0x300 80059b8: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 80059ba: 683b ldr r3, [r7, #0] 80059bc: 68db ldr r3, [r3, #12] 80059be: 68fa ldr r2, [r7, #12] 80059c0: 4313 orrs r3, r2 80059c2: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 80059c4: 68fb ldr r3, [r7, #12] 80059c6: f023 0280 bic.w r2, r3, #128 @ 0x80 80059ca: 683b ldr r3, [r7, #0] 80059cc: 695b ldr r3, [r3, #20] 80059ce: 4313 orrs r3, r2 80059d0: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 80059d2: 683b ldr r3, [r7, #0] 80059d4: 689a ldr r2, [r3, #8] 80059d6: 687b ldr r3, [r7, #4] 80059d8: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80059da: 683b ldr r3, [r7, #0] 80059dc: 681a ldr r2, [r3, #0] 80059de: 687b ldr r3, [r7, #4] 80059e0: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80059e2: 687b ldr r3, [r7, #4] 80059e4: 4a0e ldr r2, [pc, #56] @ (8005a20 ) 80059e6: 4293 cmp r3, r2 80059e8: d003 beq.n 80059f2 80059ea: 687b ldr r3, [r7, #4] 80059ec: 4a10 ldr r2, [pc, #64] @ (8005a30 ) 80059ee: 4293 cmp r3, r2 80059f0: d103 bne.n 80059fa { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80059f2: 683b ldr r3, [r7, #0] 80059f4: 691a ldr r2, [r3, #16] 80059f6: 687b ldr r3, [r7, #4] 80059f8: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 80059fa: 687b ldr r3, [r7, #4] 80059fc: 681b ldr r3, [r3, #0] 80059fe: f043 0204 orr.w r2, r3, #4 8005a02: 687b ldr r3, [r7, #4] 8005a04: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 8005a06: 687b ldr r3, [r7, #4] 8005a08: 2201 movs r2, #1 8005a0a: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 8005a0c: 687b ldr r3, [r7, #4] 8005a0e: 68fa ldr r2, [r7, #12] 8005a10: 601a str r2, [r3, #0] } 8005a12: bf00 nop 8005a14: 3714 adds r7, #20 8005a16: 46bd mov sp, r7 8005a18: f85d 7b04 ldr.w r7, [sp], #4 8005a1c: 4770 bx lr 8005a1e: bf00 nop 8005a20: 40010000 .word 0x40010000 8005a24: 40000400 .word 0x40000400 8005a28: 40000800 .word 0x40000800 8005a2c: 40000c00 .word 0x40000c00 8005a30: 40010400 .word 0x40010400 8005a34: 40014000 .word 0x40014000 8005a38: 40014400 .word 0x40014400 8005a3c: 40014800 .word 0x40014800 8005a40: 40001800 .word 0x40001800 8005a44: 40001c00 .word 0x40001c00 8005a48: 40002000 .word 0x40002000 08005a4c : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005a4c: b480 push {r7} 8005a4e: b087 sub sp, #28 8005a50: af00 add r7, sp, #0 8005a52: 60f8 str r0, [r7, #12] 8005a54: 60b9 str r1, [r7, #8] 8005a56: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8005a58: 68fb ldr r3, [r7, #12] 8005a5a: 6a1b ldr r3, [r3, #32] 8005a5c: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 8005a5e: 68fb ldr r3, [r7, #12] 8005a60: 6a1b ldr r3, [r3, #32] 8005a62: f023 0201 bic.w r2, r3, #1 8005a66: 68fb ldr r3, [r7, #12] 8005a68: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005a6a: 68fb ldr r3, [r7, #12] 8005a6c: 699b ldr r3, [r3, #24] 8005a6e: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 8005a70: 693b ldr r3, [r7, #16] 8005a72: f023 03f0 bic.w r3, r3, #240 @ 0xf0 8005a76: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8005a78: 687b ldr r3, [r7, #4] 8005a7a: 011b lsls r3, r3, #4 8005a7c: 693a ldr r2, [r7, #16] 8005a7e: 4313 orrs r3, r2 8005a80: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8005a82: 697b ldr r3, [r7, #20] 8005a84: f023 030a bic.w r3, r3, #10 8005a88: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8005a8a: 697a ldr r2, [r7, #20] 8005a8c: 68bb ldr r3, [r7, #8] 8005a8e: 4313 orrs r3, r2 8005a90: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8005a92: 68fb ldr r3, [r7, #12] 8005a94: 693a ldr r2, [r7, #16] 8005a96: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005a98: 68fb ldr r3, [r7, #12] 8005a9a: 697a ldr r2, [r7, #20] 8005a9c: 621a str r2, [r3, #32] } 8005a9e: bf00 nop 8005aa0: 371c adds r7, #28 8005aa2: 46bd mov sp, r7 8005aa4: f85d 7b04 ldr.w r7, [sp], #4 8005aa8: 4770 bx lr 08005aaa : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8005aaa: b480 push {r7} 8005aac: b087 sub sp, #28 8005aae: af00 add r7, sp, #0 8005ab0: 60f8 str r0, [r7, #12] 8005ab2: 60b9 str r1, [r7, #8] 8005ab4: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 8005ab6: 68fb ldr r3, [r7, #12] 8005ab8: 6a1b ldr r3, [r3, #32] 8005aba: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 8005abc: 68fb ldr r3, [r7, #12] 8005abe: 6a1b ldr r3, [r3, #32] 8005ac0: f023 0210 bic.w r2, r3, #16 8005ac4: 68fb ldr r3, [r7, #12] 8005ac6: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8005ac8: 68fb ldr r3, [r7, #12] 8005aca: 699b ldr r3, [r3, #24] 8005acc: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 8005ace: 693b ldr r3, [r7, #16] 8005ad0: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8005ad4: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 8005ad6: 687b ldr r3, [r7, #4] 8005ad8: 031b lsls r3, r3, #12 8005ada: 693a ldr r2, [r7, #16] 8005adc: 4313 orrs r3, r2 8005ade: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 8005ae0: 697b ldr r3, [r7, #20] 8005ae2: f023 03a0 bic.w r3, r3, #160 @ 0xa0 8005ae6: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 8005ae8: 68bb ldr r3, [r7, #8] 8005aea: 011b lsls r3, r3, #4 8005aec: 697a ldr r2, [r7, #20] 8005aee: 4313 orrs r3, r2 8005af0: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 8005af2: 68fb ldr r3, [r7, #12] 8005af4: 693a ldr r2, [r7, #16] 8005af6: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8005af8: 68fb ldr r3, [r7, #12] 8005afa: 697a ldr r2, [r7, #20] 8005afc: 621a str r2, [r3, #32] } 8005afe: bf00 nop 8005b00: 371c adds r7, #28 8005b02: 46bd mov sp, r7 8005b04: f85d 7b04 ldr.w r7, [sp], #4 8005b08: 4770 bx lr 08005b0a : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 8005b0a: b480 push {r7} 8005b0c: b085 sub sp, #20 8005b0e: af00 add r7, sp, #0 8005b10: 6078 str r0, [r7, #4] 8005b12: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8005b14: 687b ldr r3, [r7, #4] 8005b16: 689b ldr r3, [r3, #8] 8005b18: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8005b1a: 68fb ldr r3, [r7, #12] 8005b1c: f023 0370 bic.w r3, r3, #112 @ 0x70 8005b20: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8005b22: 683a ldr r2, [r7, #0] 8005b24: 68fb ldr r3, [r7, #12] 8005b26: 4313 orrs r3, r2 8005b28: f043 0307 orr.w r3, r3, #7 8005b2c: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005b2e: 687b ldr r3, [r7, #4] 8005b30: 68fa ldr r2, [r7, #12] 8005b32: 609a str r2, [r3, #8] } 8005b34: bf00 nop 8005b36: 3714 adds r7, #20 8005b38: 46bd mov sp, r7 8005b3a: f85d 7b04 ldr.w r7, [sp], #4 8005b3e: 4770 bx lr 08005b40 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8005b40: b480 push {r7} 8005b42: b087 sub sp, #28 8005b44: af00 add r7, sp, #0 8005b46: 60f8 str r0, [r7, #12] 8005b48: 60b9 str r1, [r7, #8] 8005b4a: 607a str r2, [r7, #4] 8005b4c: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 8005b4e: 68fb ldr r3, [r7, #12] 8005b50: 689b ldr r3, [r3, #8] 8005b52: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005b54: 697b ldr r3, [r7, #20] 8005b56: f423 437f bic.w r3, r3, #65280 @ 0xff00 8005b5a: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 8005b5c: 683b ldr r3, [r7, #0] 8005b5e: 021a lsls r2, r3, #8 8005b60: 687b ldr r3, [r7, #4] 8005b62: 431a orrs r2, r3 8005b64: 68bb ldr r3, [r7, #8] 8005b66: 4313 orrs r3, r2 8005b68: 697a ldr r2, [r7, #20] 8005b6a: 4313 orrs r3, r2 8005b6c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 8005b6e: 68fb ldr r3, [r7, #12] 8005b70: 697a ldr r2, [r7, #20] 8005b72: 609a str r2, [r3, #8] } 8005b74: bf00 nop 8005b76: 371c adds r7, #28 8005b78: 46bd mov sp, r7 8005b7a: f85d 7b04 ldr.w r7, [sp], #4 8005b7e: 4770 bx lr 08005b80 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 8005b80: b480 push {r7} 8005b82: b085 sub sp, #20 8005b84: af00 add r7, sp, #0 8005b86: 6078 str r0, [r7, #4] 8005b88: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 8005b8a: 687b ldr r3, [r7, #4] 8005b8c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c 8005b90: 2b01 cmp r3, #1 8005b92: d101 bne.n 8005b98 8005b94: 2302 movs r3, #2 8005b96: e05a b.n 8005c4e 8005b98: 687b ldr r3, [r7, #4] 8005b9a: 2201 movs r2, #1 8005b9c: f883 203c strb.w r2, [r3, #60] @ 0x3c /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 8005ba0: 687b ldr r3, [r7, #4] 8005ba2: 2202 movs r2, #2 8005ba4: f883 203d strb.w r2, [r3, #61] @ 0x3d /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 681b ldr r3, [r3, #0] 8005bac: 685b ldr r3, [r3, #4] 8005bae: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 681b ldr r3, [r3, #0] 8005bb4: 689b ldr r3, [r3, #8] 8005bb6: 60bb str r3, [r7, #8] /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 8005bb8: 68fb ldr r3, [r7, #12] 8005bba: f023 0370 bic.w r3, r3, #112 @ 0x70 8005bbe: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8005bc0: 683b ldr r3, [r7, #0] 8005bc2: 681b ldr r3, [r3, #0] 8005bc4: 68fa ldr r2, [r7, #12] 8005bc6: 4313 orrs r3, r2 8005bc8: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 8005bca: 687b ldr r3, [r7, #4] 8005bcc: 681b ldr r3, [r3, #0] 8005bce: 68fa ldr r2, [r7, #12] 8005bd0: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005bd2: 687b ldr r3, [r7, #4] 8005bd4: 681b ldr r3, [r3, #0] 8005bd6: 4a21 ldr r2, [pc, #132] @ (8005c5c ) 8005bd8: 4293 cmp r3, r2 8005bda: d022 beq.n 8005c22 8005bdc: 687b ldr r3, [r7, #4] 8005bde: 681b ldr r3, [r3, #0] 8005be0: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000 8005be4: d01d beq.n 8005c22 8005be6: 687b ldr r3, [r7, #4] 8005be8: 681b ldr r3, [r3, #0] 8005bea: 4a1d ldr r2, [pc, #116] @ (8005c60 ) 8005bec: 4293 cmp r3, r2 8005bee: d018 beq.n 8005c22 8005bf0: 687b ldr r3, [r7, #4] 8005bf2: 681b ldr r3, [r3, #0] 8005bf4: 4a1b ldr r2, [pc, #108] @ (8005c64 ) 8005bf6: 4293 cmp r3, r2 8005bf8: d013 beq.n 8005c22 8005bfa: 687b ldr r3, [r7, #4] 8005bfc: 681b ldr r3, [r3, #0] 8005bfe: 4a1a ldr r2, [pc, #104] @ (8005c68 ) 8005c00: 4293 cmp r3, r2 8005c02: d00e beq.n 8005c22 8005c04: 687b ldr r3, [r7, #4] 8005c06: 681b ldr r3, [r3, #0] 8005c08: 4a18 ldr r2, [pc, #96] @ (8005c6c ) 8005c0a: 4293 cmp r3, r2 8005c0c: d009 beq.n 8005c22 8005c0e: 687b ldr r3, [r7, #4] 8005c10: 681b ldr r3, [r3, #0] 8005c12: 4a17 ldr r2, [pc, #92] @ (8005c70 ) 8005c14: 4293 cmp r3, r2 8005c16: d004 beq.n 8005c22 8005c18: 687b ldr r3, [r7, #4] 8005c1a: 681b ldr r3, [r3, #0] 8005c1c: 4a15 ldr r2, [pc, #84] @ (8005c74 ) 8005c1e: 4293 cmp r3, r2 8005c20: d10c bne.n 8005c3c { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8005c22: 68bb ldr r3, [r7, #8] 8005c24: f023 0380 bic.w r3, r3, #128 @ 0x80 8005c28: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 8005c2a: 683b ldr r3, [r7, #0] 8005c2c: 685b ldr r3, [r3, #4] 8005c2e: 68ba ldr r2, [r7, #8] 8005c30: 4313 orrs r3, r2 8005c32: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005c34: 687b ldr r3, [r7, #4] 8005c36: 681b ldr r3, [r3, #0] 8005c38: 68ba ldr r2, [r7, #8] 8005c3a: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8005c3c: 687b ldr r3, [r7, #4] 8005c3e: 2201 movs r2, #1 8005c40: f883 203d strb.w r2, [r3, #61] @ 0x3d __HAL_UNLOCK(htim); 8005c44: 687b ldr r3, [r7, #4] 8005c46: 2200 movs r2, #0 8005c48: f883 203c strb.w r2, [r3, #60] @ 0x3c return HAL_OK; 8005c4c: 2300 movs r3, #0 } 8005c4e: 4618 mov r0, r3 8005c50: 3714 adds r7, #20 8005c52: 46bd mov sp, r7 8005c54: f85d 7b04 ldr.w r7, [sp], #4 8005c58: 4770 bx lr 8005c5a: bf00 nop 8005c5c: 40010000 .word 0x40010000 8005c60: 40000400 .word 0x40000400 8005c64: 40000800 .word 0x40000800 8005c68: 40000c00 .word 0x40000c00 8005c6c: 40010400 .word 0x40010400 8005c70: 40014000 .word 0x40014000 8005c74: 40001800 .word 0x40001800 08005c78 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8005c78: b480 push {r7} 8005c7a: b083 sub sp, #12 8005c7c: af00 add r7, sp, #0 8005c7e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8005c80: bf00 nop 8005c82: 370c adds r7, #12 8005c84: 46bd mov sp, r7 8005c86: f85d 7b04 ldr.w r7, [sp], #4 8005c8a: 4770 bx lr 08005c8c : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8005c8c: b480 push {r7} 8005c8e: b083 sub sp, #12 8005c90: af00 add r7, sp, #0 8005c92: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8005c94: bf00 nop 8005c96: 370c adds r7, #12 8005c98: 46bd mov sp, r7 8005c9a: f85d 7b04 ldr.w r7, [sp], #4 8005c9e: 4770 bx lr 08005ca0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8005ca0: b580 push {r7, lr} 8005ca2: b082 sub sp, #8 8005ca4: af00 add r7, sp, #0 8005ca6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8005ca8: 687b ldr r3, [r7, #4] 8005caa: 2b00 cmp r3, #0 8005cac: d101 bne.n 8005cb2 { return HAL_ERROR; 8005cae: 2301 movs r3, #1 8005cb0: e042 b.n 8005d38 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) 8005cb2: 687b ldr r3, [r7, #4] 8005cb4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41 8005cb8: b2db uxtb r3, r3 8005cba: 2b00 cmp r3, #0 8005cbc: d106 bne.n 8005ccc { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8005cbe: 687b ldr r3, [r7, #4] 8005cc0: 2200 movs r2, #0 8005cc2: f883 2040 strb.w r2, [r3, #64] @ 0x40 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8005cc6: 6878 ldr r0, [r7, #4] 8005cc8: f7fb fab0 bl 800122c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8005ccc: 687b ldr r3, [r7, #4] 8005cce: 2224 movs r2, #36 @ 0x24 8005cd0: f883 2041 strb.w r2, [r3, #65] @ 0x41 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); 8005cd4: 687b ldr r3, [r7, #4] 8005cd6: 681b ldr r3, [r3, #0] 8005cd8: 68da ldr r2, [r3, #12] 8005cda: 687b ldr r3, [r7, #4] 8005cdc: 681b ldr r3, [r3, #0] 8005cde: f422 5200 bic.w r2, r2, #8192 @ 0x2000 8005ce2: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); 8005ce4: 6878 ldr r0, [r7, #4] 8005ce6: f000 f82b bl 8005d40 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8005cea: 687b ldr r3, [r7, #4] 8005cec: 681b ldr r3, [r3, #0] 8005cee: 691a ldr r2, [r3, #16] 8005cf0: 687b ldr r3, [r7, #4] 8005cf2: 681b ldr r3, [r3, #0] 8005cf4: f422 4290 bic.w r2, r2, #18432 @ 0x4800 8005cf8: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8005cfa: 687b ldr r3, [r7, #4] 8005cfc: 681b ldr r3, [r3, #0] 8005cfe: 695a ldr r2, [r3, #20] 8005d00: 687b ldr r3, [r7, #4] 8005d02: 681b ldr r3, [r3, #0] 8005d04: f022 022a bic.w r2, r2, #42 @ 0x2a 8005d08: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); 8005d0a: 687b ldr r3, [r7, #4] 8005d0c: 681b ldr r3, [r3, #0] 8005d0e: 68da ldr r2, [r3, #12] 8005d10: 687b ldr r3, [r7, #4] 8005d12: 681b ldr r3, [r3, #0] 8005d14: f442 5200 orr.w r2, r2, #8192 @ 0x2000 8005d18: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8005d1a: 687b ldr r3, [r7, #4] 8005d1c: 2200 movs r2, #0 8005d1e: 645a str r2, [r3, #68] @ 0x44 huart->gState = HAL_UART_STATE_READY; 8005d20: 687b ldr r3, [r7, #4] 8005d22: 2220 movs r2, #32 8005d24: f883 2041 strb.w r2, [r3, #65] @ 0x41 huart->RxState = HAL_UART_STATE_READY; 8005d28: 687b ldr r3, [r7, #4] 8005d2a: 2220 movs r2, #32 8005d2c: f883 2042 strb.w r2, [r3, #66] @ 0x42 huart->RxEventType = HAL_UART_RXEVENT_TC; 8005d30: 687b ldr r3, [r7, #4] 8005d32: 2200 movs r2, #0 8005d34: 635a str r2, [r3, #52] @ 0x34 return HAL_OK; 8005d36: 2300 movs r3, #0 } 8005d38: 4618 mov r0, r3 8005d3a: 3708 adds r7, #8 8005d3c: 46bd mov sp, r7 8005d3e: bd80 pop {r7, pc} 08005d40 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { 8005d40: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8005d44: b0c0 sub sp, #256 @ 0x100 8005d46: af00 add r7, sp, #0 8005d48: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8005d4c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d50: 681b ldr r3, [r3, #0] 8005d52: 691b ldr r3, [r3, #16] 8005d54: f423 5040 bic.w r0, r3, #12288 @ 0x3000 8005d58: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d5c: 68d9 ldr r1, [r3, #12] 8005d5e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d62: 681a ldr r2, [r3, #0] 8005d64: ea40 0301 orr.w r3, r0, r1 8005d68: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; 8005d6a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d6e: 689a ldr r2, [r3, #8] 8005d70: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d74: 691b ldr r3, [r3, #16] 8005d76: 431a orrs r2, r3 8005d78: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d7c: 695b ldr r3, [r3, #20] 8005d7e: 431a orrs r2, r3 8005d80: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d84: 69db ldr r3, [r3, #28] 8005d86: 4313 orrs r3, r2 8005d88: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8 MODIFY_REG(huart->Instance->CR1, 8005d8c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005d90: 681b ldr r3, [r3, #0] 8005d92: 68db ldr r3, [r3, #12] 8005d94: f423 4116 bic.w r1, r3, #38400 @ 0x9600 8005d98: f021 010c bic.w r1, r1, #12 8005d9c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005da0: 681a ldr r2, [r3, #0] 8005da2: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8 8005da6: 430b orrs r3, r1 8005da8: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); 8005daa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dae: 681b ldr r3, [r3, #0] 8005db0: 695b ldr r3, [r3, #20] 8005db2: f423 7040 bic.w r0, r3, #768 @ 0x300 8005db6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dba: 6999 ldr r1, [r3, #24] 8005dbc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dc0: 681a ldr r2, [r3, #0] 8005dc2: ea40 0301 orr.w r3, r0, r1 8005dc6: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) 8005dc8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dcc: 681a ldr r2, [r3, #0] 8005dce: 4b8f ldr r3, [pc, #572] @ (800600c ) 8005dd0: 429a cmp r2, r3 8005dd2: d005 beq.n 8005de0 8005dd4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005dd8: 681a ldr r2, [r3, #0] 8005dda: 4b8d ldr r3, [pc, #564] @ (8006010 ) 8005ddc: 429a cmp r2, r3 8005dde: d104 bne.n 8005dea { pclk = HAL_RCC_GetPCLK2Freq(); 8005de0: f7ff f82c bl 8004e3c 8005de4: f8c7 00fc str.w r0, [r7, #252] @ 0xfc 8005de8: e003 b.n 8005df2 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); 8005dea: f7ff f813 bl 8004e14 8005dee: f8c7 00fc str.w r0, [r7, #252] @ 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8005df2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005df6: 69db ldr r3, [r3, #28] 8005df8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000 8005dfc: f040 810c bne.w 8006018 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); 8005e00: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005e04: 2200 movs r2, #0 8005e06: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8 8005e0a: f8c7 20ec str.w r2, [r7, #236] @ 0xec 8005e0e: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8 8005e12: 4622 mov r2, r4 8005e14: 462b mov r3, r5 8005e16: 1891 adds r1, r2, r2 8005e18: 65b9 str r1, [r7, #88] @ 0x58 8005e1a: 415b adcs r3, r3 8005e1c: 65fb str r3, [r7, #92] @ 0x5c 8005e1e: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58 8005e22: 4621 mov r1, r4 8005e24: eb12 0801 adds.w r8, r2, r1 8005e28: 4629 mov r1, r5 8005e2a: eb43 0901 adc.w r9, r3, r1 8005e2e: f04f 0200 mov.w r2, #0 8005e32: f04f 0300 mov.w r3, #0 8005e36: ea4f 03c9 mov.w r3, r9, lsl #3 8005e3a: ea43 7358 orr.w r3, r3, r8, lsr #29 8005e3e: ea4f 02c8 mov.w r2, r8, lsl #3 8005e42: 4690 mov r8, r2 8005e44: 4699 mov r9, r3 8005e46: 4623 mov r3, r4 8005e48: eb18 0303 adds.w r3, r8, r3 8005e4c: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0 8005e50: 462b mov r3, r5 8005e52: eb49 0303 adc.w r3, r9, r3 8005e56: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4 8005e5a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005e5e: 685b ldr r3, [r3, #4] 8005e60: 2200 movs r2, #0 8005e62: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8 8005e66: f8c7 20dc str.w r2, [r7, #220] @ 0xdc 8005e6a: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8 8005e6e: 460b mov r3, r1 8005e70: 18db adds r3, r3, r3 8005e72: 653b str r3, [r7, #80] @ 0x50 8005e74: 4613 mov r3, r2 8005e76: eb42 0303 adc.w r3, r2, r3 8005e7a: 657b str r3, [r7, #84] @ 0x54 8005e7c: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50 8005e80: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0 8005e84: f7fa f9b4 bl 80001f0 <__aeabi_uldivmod> 8005e88: 4602 mov r2, r0 8005e8a: 460b mov r3, r1 8005e8c: 4b61 ldr r3, [pc, #388] @ (8006014 ) 8005e8e: fba3 2302 umull r2, r3, r3, r2 8005e92: 095b lsrs r3, r3, #5 8005e94: 011c lsls r4, r3, #4 8005e96: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005e9a: 2200 movs r2, #0 8005e9c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0 8005ea0: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4 8005ea4: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0 8005ea8: 4642 mov r2, r8 8005eaa: 464b mov r3, r9 8005eac: 1891 adds r1, r2, r2 8005eae: 64b9 str r1, [r7, #72] @ 0x48 8005eb0: 415b adcs r3, r3 8005eb2: 64fb str r3, [r7, #76] @ 0x4c 8005eb4: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48 8005eb8: 4641 mov r1, r8 8005eba: eb12 0a01 adds.w sl, r2, r1 8005ebe: 4649 mov r1, r9 8005ec0: eb43 0b01 adc.w fp, r3, r1 8005ec4: f04f 0200 mov.w r2, #0 8005ec8: f04f 0300 mov.w r3, #0 8005ecc: ea4f 03cb mov.w r3, fp, lsl #3 8005ed0: ea43 735a orr.w r3, r3, sl, lsr #29 8005ed4: ea4f 02ca mov.w r2, sl, lsl #3 8005ed8: 4692 mov sl, r2 8005eda: 469b mov fp, r3 8005edc: 4643 mov r3, r8 8005ede: eb1a 0303 adds.w r3, sl, r3 8005ee2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8 8005ee6: 464b mov r3, r9 8005ee8: eb4b 0303 adc.w r3, fp, r3 8005eec: f8c7 30cc str.w r3, [r7, #204] @ 0xcc 8005ef0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005ef4: 685b ldr r3, [r3, #4] 8005ef6: 2200 movs r2, #0 8005ef8: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0 8005efc: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4 8005f00: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0 8005f04: 460b mov r3, r1 8005f06: 18db adds r3, r3, r3 8005f08: 643b str r3, [r7, #64] @ 0x40 8005f0a: 4613 mov r3, r2 8005f0c: eb42 0303 adc.w r3, r2, r3 8005f10: 647b str r3, [r7, #68] @ 0x44 8005f12: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40 8005f16: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8 8005f1a: f7fa f969 bl 80001f0 <__aeabi_uldivmod> 8005f1e: 4602 mov r2, r0 8005f20: 460b mov r3, r1 8005f22: 4611 mov r1, r2 8005f24: 4b3b ldr r3, [pc, #236] @ (8006014 ) 8005f26: fba3 2301 umull r2, r3, r3, r1 8005f2a: 095b lsrs r3, r3, #5 8005f2c: 2264 movs r2, #100 @ 0x64 8005f2e: fb02 f303 mul.w r3, r2, r3 8005f32: 1acb subs r3, r1, r3 8005f34: 00db lsls r3, r3, #3 8005f36: f103 0232 add.w r2, r3, #50 @ 0x32 8005f3a: 4b36 ldr r3, [pc, #216] @ (8006014 ) 8005f3c: fba3 2302 umull r2, r3, r3, r2 8005f40: 095b lsrs r3, r3, #5 8005f42: 005b lsls r3, r3, #1 8005f44: f403 73f8 and.w r3, r3, #496 @ 0x1f0 8005f48: 441c add r4, r3 8005f4a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8005f4e: 2200 movs r2, #0 8005f50: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8 8005f54: f8c7 20bc str.w r2, [r7, #188] @ 0xbc 8005f58: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8 8005f5c: 4642 mov r2, r8 8005f5e: 464b mov r3, r9 8005f60: 1891 adds r1, r2, r2 8005f62: 63b9 str r1, [r7, #56] @ 0x38 8005f64: 415b adcs r3, r3 8005f66: 63fb str r3, [r7, #60] @ 0x3c 8005f68: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38 8005f6c: 4641 mov r1, r8 8005f6e: 1851 adds r1, r2, r1 8005f70: 6339 str r1, [r7, #48] @ 0x30 8005f72: 4649 mov r1, r9 8005f74: 414b adcs r3, r1 8005f76: 637b str r3, [r7, #52] @ 0x34 8005f78: f04f 0200 mov.w r2, #0 8005f7c: f04f 0300 mov.w r3, #0 8005f80: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30 8005f84: 4659 mov r1, fp 8005f86: 00cb lsls r3, r1, #3 8005f88: 4651 mov r1, sl 8005f8a: ea43 7351 orr.w r3, r3, r1, lsr #29 8005f8e: 4651 mov r1, sl 8005f90: 00ca lsls r2, r1, #3 8005f92: 4610 mov r0, r2 8005f94: 4619 mov r1, r3 8005f96: 4603 mov r3, r0 8005f98: 4642 mov r2, r8 8005f9a: 189b adds r3, r3, r2 8005f9c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0 8005fa0: 464b mov r3, r9 8005fa2: 460a mov r2, r1 8005fa4: eb42 0303 adc.w r3, r2, r3 8005fa8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4 8005fac: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8005fb0: 685b ldr r3, [r3, #4] 8005fb2: 2200 movs r2, #0 8005fb4: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8 8005fb8: f8c7 20ac str.w r2, [r7, #172] @ 0xac 8005fbc: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8 8005fc0: 460b mov r3, r1 8005fc2: 18db adds r3, r3, r3 8005fc4: 62bb str r3, [r7, #40] @ 0x28 8005fc6: 4613 mov r3, r2 8005fc8: eb42 0303 adc.w r3, r2, r3 8005fcc: 62fb str r3, [r7, #44] @ 0x2c 8005fce: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28 8005fd2: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0 8005fd6: f7fa f90b bl 80001f0 <__aeabi_uldivmod> 8005fda: 4602 mov r2, r0 8005fdc: 460b mov r3, r1 8005fde: 4b0d ldr r3, [pc, #52] @ (8006014 ) 8005fe0: fba3 1302 umull r1, r3, r3, r2 8005fe4: 095b lsrs r3, r3, #5 8005fe6: 2164 movs r1, #100 @ 0x64 8005fe8: fb01 f303 mul.w r3, r1, r3 8005fec: 1ad3 subs r3, r2, r3 8005fee: 00db lsls r3, r3, #3 8005ff0: 3332 adds r3, #50 @ 0x32 8005ff2: 4a08 ldr r2, [pc, #32] @ (8006014 ) 8005ff4: fba2 2303 umull r2, r3, r2, r3 8005ff8: 095b lsrs r3, r3, #5 8005ffa: f003 0207 and.w r2, r3, #7 8005ffe: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006002: 681b ldr r3, [r3, #0] 8006004: 4422 add r2, r4 8006006: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } 8006008: e106 b.n 8006218 800600a: bf00 nop 800600c: 40011000 .word 0x40011000 8006010: 40011400 .word 0x40011400 8006014: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); 8006018: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 800601c: 2200 movs r2, #0 800601e: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0 8006022: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4 8006026: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0 800602a: 4642 mov r2, r8 800602c: 464b mov r3, r9 800602e: 1891 adds r1, r2, r2 8006030: 6239 str r1, [r7, #32] 8006032: 415b adcs r3, r3 8006034: 627b str r3, [r7, #36] @ 0x24 8006036: e9d7 2308 ldrd r2, r3, [r7, #32] 800603a: 4641 mov r1, r8 800603c: 1854 adds r4, r2, r1 800603e: 4649 mov r1, r9 8006040: eb43 0501 adc.w r5, r3, r1 8006044: f04f 0200 mov.w r2, #0 8006048: f04f 0300 mov.w r3, #0 800604c: 00eb lsls r3, r5, #3 800604e: ea43 7354 orr.w r3, r3, r4, lsr #29 8006052: 00e2 lsls r2, r4, #3 8006054: 4614 mov r4, r2 8006056: 461d mov r5, r3 8006058: 4643 mov r3, r8 800605a: 18e3 adds r3, r4, r3 800605c: f8c7 3098 str.w r3, [r7, #152] @ 0x98 8006060: 464b mov r3, r9 8006062: eb45 0303 adc.w r3, r5, r3 8006066: f8c7 309c str.w r3, [r7, #156] @ 0x9c 800606a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 800606e: 685b ldr r3, [r3, #4] 8006070: 2200 movs r2, #0 8006072: f8c7 3090 str.w r3, [r7, #144] @ 0x90 8006076: f8c7 2094 str.w r2, [r7, #148] @ 0x94 800607a: f04f 0200 mov.w r2, #0 800607e: f04f 0300 mov.w r3, #0 8006082: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90 8006086: 4629 mov r1, r5 8006088: 008b lsls r3, r1, #2 800608a: 4621 mov r1, r4 800608c: ea43 7391 orr.w r3, r3, r1, lsr #30 8006090: 4621 mov r1, r4 8006092: 008a lsls r2, r1, #2 8006094: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98 8006098: f7fa f8aa bl 80001f0 <__aeabi_uldivmod> 800609c: 4602 mov r2, r0 800609e: 460b mov r3, r1 80060a0: 4b60 ldr r3, [pc, #384] @ (8006224 ) 80060a2: fba3 2302 umull r2, r3, r3, r2 80060a6: 095b lsrs r3, r3, #5 80060a8: 011c lsls r4, r3, #4 80060aa: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 80060ae: 2200 movs r2, #0 80060b0: f8c7 3088 str.w r3, [r7, #136] @ 0x88 80060b4: f8c7 208c str.w r2, [r7, #140] @ 0x8c 80060b8: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88 80060bc: 4642 mov r2, r8 80060be: 464b mov r3, r9 80060c0: 1891 adds r1, r2, r2 80060c2: 61b9 str r1, [r7, #24] 80060c4: 415b adcs r3, r3 80060c6: 61fb str r3, [r7, #28] 80060c8: e9d7 2306 ldrd r2, r3, [r7, #24] 80060cc: 4641 mov r1, r8 80060ce: 1851 adds r1, r2, r1 80060d0: 6139 str r1, [r7, #16] 80060d2: 4649 mov r1, r9 80060d4: 414b adcs r3, r1 80060d6: 617b str r3, [r7, #20] 80060d8: f04f 0200 mov.w r2, #0 80060dc: f04f 0300 mov.w r3, #0 80060e0: e9d7 ab04 ldrd sl, fp, [r7, #16] 80060e4: 4659 mov r1, fp 80060e6: 00cb lsls r3, r1, #3 80060e8: 4651 mov r1, sl 80060ea: ea43 7351 orr.w r3, r3, r1, lsr #29 80060ee: 4651 mov r1, sl 80060f0: 00ca lsls r2, r1, #3 80060f2: 4610 mov r0, r2 80060f4: 4619 mov r1, r3 80060f6: 4603 mov r3, r0 80060f8: 4642 mov r2, r8 80060fa: 189b adds r3, r3, r2 80060fc: f8c7 3080 str.w r3, [r7, #128] @ 0x80 8006100: 464b mov r3, r9 8006102: 460a mov r2, r1 8006104: eb42 0303 adc.w r3, r2, r3 8006108: f8c7 3084 str.w r3, [r7, #132] @ 0x84 800610c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006110: 685b ldr r3, [r3, #4] 8006112: 2200 movs r2, #0 8006114: 67bb str r3, [r7, #120] @ 0x78 8006116: 67fa str r2, [r7, #124] @ 0x7c 8006118: f04f 0200 mov.w r2, #0 800611c: f04f 0300 mov.w r3, #0 8006120: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78 8006124: 4649 mov r1, r9 8006126: 008b lsls r3, r1, #2 8006128: 4641 mov r1, r8 800612a: ea43 7391 orr.w r3, r3, r1, lsr #30 800612e: 4641 mov r1, r8 8006130: 008a lsls r2, r1, #2 8006132: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80 8006136: f7fa f85b bl 80001f0 <__aeabi_uldivmod> 800613a: 4602 mov r2, r0 800613c: 460b mov r3, r1 800613e: 4611 mov r1, r2 8006140: 4b38 ldr r3, [pc, #224] @ (8006224 ) 8006142: fba3 2301 umull r2, r3, r3, r1 8006146: 095b lsrs r3, r3, #5 8006148: 2264 movs r2, #100 @ 0x64 800614a: fb02 f303 mul.w r3, r2, r3 800614e: 1acb subs r3, r1, r3 8006150: 011b lsls r3, r3, #4 8006152: 3332 adds r3, #50 @ 0x32 8006154: 4a33 ldr r2, [pc, #204] @ (8006224 ) 8006156: fba2 2303 umull r2, r3, r2, r3 800615a: 095b lsrs r3, r3, #5 800615c: f003 03f0 and.w r3, r3, #240 @ 0xf0 8006160: 441c add r4, r3 8006162: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc 8006166: 2200 movs r2, #0 8006168: 673b str r3, [r7, #112] @ 0x70 800616a: 677a str r2, [r7, #116] @ 0x74 800616c: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70 8006170: 4642 mov r2, r8 8006172: 464b mov r3, r9 8006174: 1891 adds r1, r2, r2 8006176: 60b9 str r1, [r7, #8] 8006178: 415b adcs r3, r3 800617a: 60fb str r3, [r7, #12] 800617c: e9d7 2302 ldrd r2, r3, [r7, #8] 8006180: 4641 mov r1, r8 8006182: 1851 adds r1, r2, r1 8006184: 6039 str r1, [r7, #0] 8006186: 4649 mov r1, r9 8006188: 414b adcs r3, r1 800618a: 607b str r3, [r7, #4] 800618c: f04f 0200 mov.w r2, #0 8006190: f04f 0300 mov.w r3, #0 8006194: e9d7 ab00 ldrd sl, fp, [r7] 8006198: 4659 mov r1, fp 800619a: 00cb lsls r3, r1, #3 800619c: 4651 mov r1, sl 800619e: ea43 7351 orr.w r3, r3, r1, lsr #29 80061a2: 4651 mov r1, sl 80061a4: 00ca lsls r2, r1, #3 80061a6: 4610 mov r0, r2 80061a8: 4619 mov r1, r3 80061aa: 4603 mov r3, r0 80061ac: 4642 mov r2, r8 80061ae: 189b adds r3, r3, r2 80061b0: 66bb str r3, [r7, #104] @ 0x68 80061b2: 464b mov r3, r9 80061b4: 460a mov r2, r1 80061b6: eb42 0303 adc.w r3, r2, r3 80061ba: 66fb str r3, [r7, #108] @ 0x6c 80061bc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 80061c0: 685b ldr r3, [r3, #4] 80061c2: 2200 movs r2, #0 80061c4: 663b str r3, [r7, #96] @ 0x60 80061c6: 667a str r2, [r7, #100] @ 0x64 80061c8: f04f 0200 mov.w r2, #0 80061cc: f04f 0300 mov.w r3, #0 80061d0: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60 80061d4: 4649 mov r1, r9 80061d6: 008b lsls r3, r1, #2 80061d8: 4641 mov r1, r8 80061da: ea43 7391 orr.w r3, r3, r1, lsr #30 80061de: 4641 mov r1, r8 80061e0: 008a lsls r2, r1, #2 80061e2: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68 80061e6: f7fa f803 bl 80001f0 <__aeabi_uldivmod> 80061ea: 4602 mov r2, r0 80061ec: 460b mov r3, r1 80061ee: 4b0d ldr r3, [pc, #52] @ (8006224 ) 80061f0: fba3 1302 umull r1, r3, r3, r2 80061f4: 095b lsrs r3, r3, #5 80061f6: 2164 movs r1, #100 @ 0x64 80061f8: fb01 f303 mul.w r3, r1, r3 80061fc: 1ad3 subs r3, r2, r3 80061fe: 011b lsls r3, r3, #4 8006200: 3332 adds r3, #50 @ 0x32 8006202: 4a08 ldr r2, [pc, #32] @ (8006224 ) 8006204: fba2 2303 umull r2, r3, r2, r3 8006208: 095b lsrs r3, r3, #5 800620a: f003 020f and.w r2, r3, #15 800620e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4 8006212: 681b ldr r3, [r3, #0] 8006214: 4422 add r2, r4 8006216: 609a str r2, [r3, #8] } 8006218: bf00 nop 800621a: f507 7780 add.w r7, r7, #256 @ 0x100 800621e: 46bd mov sp, r7 8006220: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 8006224: 51eb851f .word 0x51eb851f 08006228 : * @param Device Pointer to SDRAM device instance * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) { 8006228: b480 push {r7} 800622a: b083 sub sp, #12 800622c: af00 add r7, sp, #0 800622e: 6078 str r0, [r7, #4] 8006230: 6039 str r1, [r7, #0] assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); /* Set SDRAM bank configuration parameters */ if (Init->SDBank == FMC_SDRAM_BANK1) 8006232: 683b ldr r3, [r7, #0] 8006234: 681b ldr r3, [r3, #0] 8006236: 2b00 cmp r3, #0 8006238: d123 bne.n 8006282 { MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], 800623a: 687b ldr r3, [r7, #4] 800623c: 681b ldr r3, [r3, #0] 800623e: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 8006242: f023 037f bic.w r3, r3, #127 @ 0x7f 8006246: 683a ldr r2, [r7, #0] 8006248: 6851 ldr r1, [r2, #4] 800624a: 683a ldr r2, [r7, #0] 800624c: 6892 ldr r2, [r2, #8] 800624e: 4311 orrs r1, r2 8006250: 683a ldr r2, [r7, #0] 8006252: 68d2 ldr r2, [r2, #12] 8006254: 4311 orrs r1, r2 8006256: 683a ldr r2, [r7, #0] 8006258: 6912 ldr r2, [r2, #16] 800625a: 4311 orrs r1, r2 800625c: 683a ldr r2, [r7, #0] 800625e: 6952 ldr r2, [r2, #20] 8006260: 4311 orrs r1, r2 8006262: 683a ldr r2, [r7, #0] 8006264: 6992 ldr r2, [r2, #24] 8006266: 4311 orrs r1, r2 8006268: 683a ldr r2, [r7, #0] 800626a: 69d2 ldr r2, [r2, #28] 800626c: 4311 orrs r1, r2 800626e: 683a ldr r2, [r7, #0] 8006270: 6a12 ldr r2, [r2, #32] 8006272: 4311 orrs r1, r2 8006274: 683a ldr r2, [r7, #0] 8006276: 6a52 ldr r2, [r2, #36] @ 0x24 8006278: 430a orrs r2, r1 800627a: 431a orrs r2, r3 800627c: 687b ldr r3, [r7, #4] 800627e: 601a str r2, [r3, #0] 8006280: e028 b.n 80062d4 Init->ReadBurst | Init->ReadPipeDelay)); } else /* FMC_Bank2_SDRAM */ { MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], 8006282: 687b ldr r3, [r7, #4] 8006284: 681b ldr r3, [r3, #0] 8006286: f423 42f8 bic.w r2, r3, #31744 @ 0x7c00 800628a: 683b ldr r3, [r7, #0] 800628c: 69d9 ldr r1, [r3, #28] 800628e: 683b ldr r3, [r7, #0] 8006290: 6a1b ldr r3, [r3, #32] 8006292: 4319 orrs r1, r3 8006294: 683b ldr r3, [r7, #0] 8006296: 6a5b ldr r3, [r3, #36] @ 0x24 8006298: 430b orrs r3, r1 800629a: 431a orrs r2, r3 800629c: 687b ldr r3, [r7, #4] 800629e: 601a str r2, [r3, #0] FMC_SDCR1_RPIPE, (Init->SDClockPeriod | Init->ReadBurst | Init->ReadPipeDelay)); MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], 80062a0: 687b ldr r3, [r7, #4] 80062a2: 685b ldr r3, [r3, #4] 80062a4: f423 43ff bic.w r3, r3, #32640 @ 0x7f80 80062a8: f023 037f bic.w r3, r3, #127 @ 0x7f 80062ac: 683a ldr r2, [r7, #0] 80062ae: 6851 ldr r1, [r2, #4] 80062b0: 683a ldr r2, [r7, #0] 80062b2: 6892 ldr r2, [r2, #8] 80062b4: 4311 orrs r1, r2 80062b6: 683a ldr r2, [r7, #0] 80062b8: 68d2 ldr r2, [r2, #12] 80062ba: 4311 orrs r1, r2 80062bc: 683a ldr r2, [r7, #0] 80062be: 6912 ldr r2, [r2, #16] 80062c0: 4311 orrs r1, r2 80062c2: 683a ldr r2, [r7, #0] 80062c4: 6952 ldr r2, [r2, #20] 80062c6: 4311 orrs r1, r2 80062c8: 683a ldr r2, [r7, #0] 80062ca: 6992 ldr r2, [r2, #24] 80062cc: 430a orrs r2, r1 80062ce: 431a orrs r2, r3 80062d0: 687b ldr r3, [r7, #4] 80062d2: 605a str r2, [r3, #4] Init->InternalBankNumber | Init->CASLatency | Init->WriteProtection)); } return HAL_OK; 80062d4: 2300 movs r3, #0 } 80062d6: 4618 mov r0, r3 80062d8: 370c adds r7, #12 80062da: 46bd mov sp, r7 80062dc: f85d 7b04 ldr.w r7, [sp], #4 80062e0: 4770 bx lr 080062e2 : * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { 80062e2: b480 push {r7} 80062e4: b085 sub sp, #20 80062e6: af00 add r7, sp, #0 80062e8: 60f8 str r0, [r7, #12] 80062ea: 60b9 str r1, [r7, #8] 80062ec: 607a str r2, [r7, #4] assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Set SDRAM device timing parameters */ if (Bank == FMC_SDRAM_BANK1) 80062ee: 687b ldr r3, [r7, #4] 80062f0: 2b00 cmp r3, #0 80062f2: d128 bne.n 8006346 { MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], 80062f4: 68fb ldr r3, [r7, #12] 80062f6: 689b ldr r3, [r3, #8] 80062f8: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000 80062fc: 68bb ldr r3, [r7, #8] 80062fe: 681b ldr r3, [r3, #0] 8006300: 1e59 subs r1, r3, #1 8006302: 68bb ldr r3, [r7, #8] 8006304: 685b ldr r3, [r3, #4] 8006306: 3b01 subs r3, #1 8006308: 011b lsls r3, r3, #4 800630a: 4319 orrs r1, r3 800630c: 68bb ldr r3, [r7, #8] 800630e: 689b ldr r3, [r3, #8] 8006310: 3b01 subs r3, #1 8006312: 021b lsls r3, r3, #8 8006314: 4319 orrs r1, r3 8006316: 68bb ldr r3, [r7, #8] 8006318: 68db ldr r3, [r3, #12] 800631a: 3b01 subs r3, #1 800631c: 031b lsls r3, r3, #12 800631e: 4319 orrs r1, r3 8006320: 68bb ldr r3, [r7, #8] 8006322: 691b ldr r3, [r3, #16] 8006324: 3b01 subs r3, #1 8006326: 041b lsls r3, r3, #16 8006328: 4319 orrs r1, r3 800632a: 68bb ldr r3, [r7, #8] 800632c: 695b ldr r3, [r3, #20] 800632e: 3b01 subs r3, #1 8006330: 051b lsls r3, r3, #20 8006332: 4319 orrs r1, r3 8006334: 68bb ldr r3, [r7, #8] 8006336: 699b ldr r3, [r3, #24] 8006338: 3b01 subs r3, #1 800633a: 061b lsls r3, r3, #24 800633c: 430b orrs r3, r1 800633e: 431a orrs r2, r3 8006340: 68fb ldr r3, [r7, #12] 8006342: 609a str r2, [r3, #8] 8006344: e02f b.n 80063a6 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } else /* FMC_Bank2_SDRAM */ { MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], 8006346: 68fb ldr r3, [r7, #12] 8006348: 689b ldr r3, [r3, #8] 800634a: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000 800634e: f423 4370 bic.w r3, r3, #61440 @ 0xf000 8006352: 68ba ldr r2, [r7, #8] 8006354: 68d2 ldr r2, [r2, #12] 8006356: 3a01 subs r2, #1 8006358: 0311 lsls r1, r2, #12 800635a: 68ba ldr r2, [r7, #8] 800635c: 6952 ldr r2, [r2, #20] 800635e: 3a01 subs r2, #1 8006360: 0512 lsls r2, r2, #20 8006362: 430a orrs r2, r1 8006364: 431a orrs r2, r3 8006366: 68fb ldr r3, [r7, #12] 8006368: 609a str r2, [r3, #8] FMC_SDTR1_TRC | FMC_SDTR1_TRP, (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], 800636a: 68fb ldr r3, [r7, #12] 800636c: 68db ldr r3, [r3, #12] 800636e: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000 8006372: 68bb ldr r3, [r7, #8] 8006374: 681b ldr r3, [r3, #0] 8006376: 1e59 subs r1, r3, #1 8006378: 68bb ldr r3, [r7, #8] 800637a: 685b ldr r3, [r3, #4] 800637c: 3b01 subs r3, #1 800637e: 011b lsls r3, r3, #4 8006380: 4319 orrs r1, r3 8006382: 68bb ldr r3, [r7, #8] 8006384: 689b ldr r3, [r3, #8] 8006386: 3b01 subs r3, #1 8006388: 021b lsls r3, r3, #8 800638a: 4319 orrs r1, r3 800638c: 68bb ldr r3, [r7, #8] 800638e: 691b ldr r3, [r3, #16] 8006390: 3b01 subs r3, #1 8006392: 041b lsls r3, r3, #16 8006394: 4319 orrs r1, r3 8006396: 68bb ldr r3, [r7, #8] 8006398: 699b ldr r3, [r3, #24] 800639a: 3b01 subs r3, #1 800639c: 061b lsls r3, r3, #24 800639e: 430b orrs r3, r1 80063a0: 431a orrs r2, r3 80063a2: 68fb ldr r3, [r7, #12] 80063a4: 60da str r2, [r3, #12] (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } return HAL_OK; 80063a6: 2300 movs r3, #0 } 80063a8: 4618 mov r0, r3 80063aa: 3714 adds r7, #20 80063ac: 46bd mov sp, r7 80063ae: f85d 7b04 ldr.w r7, [sp], #4 80063b2: 4770 bx lr 080063b4 : * Enables the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80063b4: b480 push {r7} 80063b6: b083 sub sp, #12 80063b8: af00 add r7, sp, #0 80063ba: 6078 str r0, [r7, #4] USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 80063bc: 687b ldr r3, [r7, #4] 80063be: 689b ldr r3, [r3, #8] 80063c0: f043 0201 orr.w r2, r3, #1 80063c4: 687b ldr r3, [r7, #4] 80063c6: 609a str r2, [r3, #8] return HAL_OK; 80063c8: 2300 movs r3, #0 } 80063ca: 4618 mov r0, r3 80063cc: 370c adds r7, #12 80063ce: 46bd mov sp, r7 80063d0: f85d 7b04 ldr.w r7, [sp], #4 80063d4: 4770 bx lr 080063d6 : * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { 80063d6: b480 push {r7} 80063d8: b083 sub sp, #12 80063da: af00 add r7, sp, #0 80063dc: 6078 str r0, [r7, #4] USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 80063de: 687b ldr r3, [r7, #4] 80063e0: 689b ldr r3, [r3, #8] 80063e2: f023 0201 bic.w r2, r3, #1 80063e6: 687b ldr r3, [r7, #4] 80063e8: 609a str r2, [r3, #8] return HAL_OK; 80063ea: 2300 movs r3, #0 } 80063ec: 4618 mov r0, r3 80063ee: 370c adds r7, #12 80063f0: 46bd mov sp, r7 80063f2: f85d 7b04 ldr.w r7, [sp], #4 80063f6: 4770 bx lr 080063f8 : * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { 80063f8: b480 push {r7} 80063fa: b085 sub sp, #20 80063fc: af00 add r7, sp, #0 80063fe: 6078 str r0, [r7, #4] 8006400: 6039 str r1, [r7, #0] __IO uint32_t count = 0U; 8006402: 2300 movs r3, #0 8006404: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8006406: 68fb ldr r3, [r7, #12] 8006408: 3301 adds r3, #1 800640a: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800640c: 68fb ldr r3, [r7, #12] 800640e: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006412: d901 bls.n 8006418 { return HAL_TIMEOUT; 8006414: 2303 movs r3, #3 8006416: e01b b.n 8006450 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 8006418: 687b ldr r3, [r7, #4] 800641a: 691b ldr r3, [r3, #16] 800641c: 2b00 cmp r3, #0 800641e: daf2 bge.n 8006406 /* Flush TX Fifo */ count = 0U; 8006420: 2300 movs r3, #0 8006422: 60fb str r3, [r7, #12] USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); 8006424: 683b ldr r3, [r7, #0] 8006426: 019b lsls r3, r3, #6 8006428: f043 0220 orr.w r2, r3, #32 800642c: 687b ldr r3, [r7, #4] 800642e: 611a str r2, [r3, #16] do { count++; 8006430: 68fb ldr r3, [r7, #12] 8006432: 3301 adds r3, #1 8006434: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006436: 68fb ldr r3, [r7, #12] 8006438: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 800643c: d901 bls.n 8006442 { return HAL_TIMEOUT; 800643e: 2303 movs r3, #3 8006440: e006 b.n 8006450 } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 8006442: 687b ldr r3, [r7, #4] 8006444: 691b ldr r3, [r3, #16] 8006446: f003 0320 and.w r3, r3, #32 800644a: 2b20 cmp r3, #32 800644c: d0f0 beq.n 8006430 return HAL_OK; 800644e: 2300 movs r3, #0 } 8006450: 4618 mov r0, r3 8006452: 3714 adds r7, #20 8006454: 46bd mov sp, r7 8006456: f85d 7b04 ldr.w r7, [sp], #4 800645a: 4770 bx lr 0800645c : * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { 800645c: b480 push {r7} 800645e: b085 sub sp, #20 8006460: af00 add r7, sp, #0 8006462: 6078 str r0, [r7, #4] __IO uint32_t count = 0U; 8006464: 2300 movs r3, #0 8006466: 60fb str r3, [r7, #12] /* Wait for AHB master IDLE state. */ do { count++; 8006468: 68fb ldr r3, [r7, #12] 800646a: 3301 adds r3, #1 800646c: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 800646e: 68fb ldr r3, [r7, #12] 8006470: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006474: d901 bls.n 800647a { return HAL_TIMEOUT; 8006476: 2303 movs r3, #3 8006478: e018 b.n 80064ac } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); 800647a: 687b ldr r3, [r7, #4] 800647c: 691b ldr r3, [r3, #16] 800647e: 2b00 cmp r3, #0 8006480: daf2 bge.n 8006468 /* Flush RX Fifo */ count = 0U; 8006482: 2300 movs r3, #0 8006484: 60fb str r3, [r7, #12] USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 8006486: 687b ldr r3, [r7, #4] 8006488: 2210 movs r2, #16 800648a: 611a str r2, [r3, #16] do { count++; 800648c: 68fb ldr r3, [r7, #12] 800648e: 3301 adds r3, #1 8006490: 60fb str r3, [r7, #12] if (count > HAL_USB_TIMEOUT) 8006492: 68fb ldr r3, [r7, #12] 8006494: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000 8006498: d901 bls.n 800649e { return HAL_TIMEOUT; 800649a: 2303 movs r3, #3 800649c: e006 b.n 80064ac } } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 800649e: 687b ldr r3, [r7, #4] 80064a0: 691b ldr r3, [r3, #16] 80064a2: f003 0310 and.w r3, r3, #16 80064a6: 2b10 cmp r3, #16 80064a8: d0f0 beq.n 800648c return HAL_OK; 80064aa: 2300 movs r3, #0 } 80064ac: 4618 mov r0, r3 80064ae: 3714 adds r7, #20 80064b0: 46bd mov sp, r7 80064b2: f85d 7b04 ldr.w r7, [sp], #4 80064b6: 4770 bx lr 080064b8 : * @param dest source pointer * @param len Number of bytes to read * @retval pointer to destination buffer */ void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { 80064b8: b480 push {r7} 80064ba: b08b sub sp, #44 @ 0x2c 80064bc: af00 add r7, sp, #0 80064be: 60f8 str r0, [r7, #12] 80064c0: 60b9 str r1, [r7, #8] 80064c2: 4613 mov r3, r2 80064c4: 80fb strh r3, [r7, #6] uint32_t USBx_BASE = (uint32_t)USBx; 80064c6: 68fb ldr r3, [r7, #12] 80064c8: 61bb str r3, [r7, #24] uint8_t *pDest = dest; 80064ca: 68bb ldr r3, [r7, #8] 80064cc: 627b str r3, [r7, #36] @ 0x24 uint32_t pData; uint32_t i; uint32_t count32b = (uint32_t)len >> 2U; 80064ce: 88fb ldrh r3, [r7, #6] 80064d0: 089b lsrs r3, r3, #2 80064d2: b29b uxth r3, r3 80064d4: 617b str r3, [r7, #20] uint16_t remaining_bytes = len % 4U; 80064d6: 88fb ldrh r3, [r7, #6] 80064d8: f003 0303 and.w r3, r3, #3 80064dc: 83fb strh r3, [r7, #30] for (i = 0U; i < count32b; i++) 80064de: 2300 movs r3, #0 80064e0: 623b str r3, [r7, #32] 80064e2: e014 b.n 800650e { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); 80064e4: 69bb ldr r3, [r7, #24] 80064e6: f503 5380 add.w r3, r3, #4096 @ 0x1000 80064ea: 681a ldr r2, [r3, #0] 80064ec: 6a7b ldr r3, [r7, #36] @ 0x24 80064ee: 601a str r2, [r3, #0] pDest++; 80064f0: 6a7b ldr r3, [r7, #36] @ 0x24 80064f2: 3301 adds r3, #1 80064f4: 627b str r3, [r7, #36] @ 0x24 pDest++; 80064f6: 6a7b ldr r3, [r7, #36] @ 0x24 80064f8: 3301 adds r3, #1 80064fa: 627b str r3, [r7, #36] @ 0x24 pDest++; 80064fc: 6a7b ldr r3, [r7, #36] @ 0x24 80064fe: 3301 adds r3, #1 8006500: 627b str r3, [r7, #36] @ 0x24 pDest++; 8006502: 6a7b ldr r3, [r7, #36] @ 0x24 8006504: 3301 adds r3, #1 8006506: 627b str r3, [r7, #36] @ 0x24 for (i = 0U; i < count32b; i++) 8006508: 6a3b ldr r3, [r7, #32] 800650a: 3301 adds r3, #1 800650c: 623b str r3, [r7, #32] 800650e: 6a3a ldr r2, [r7, #32] 8006510: 697b ldr r3, [r7, #20] 8006512: 429a cmp r2, r3 8006514: d3e6 bcc.n 80064e4 } /* When Number of data is not word aligned, read the remaining byte */ if (remaining_bytes != 0U) 8006516: 8bfb ldrh r3, [r7, #30] 8006518: 2b00 cmp r3, #0 800651a: d01e beq.n 800655a { i = 0U; 800651c: 2300 movs r3, #0 800651e: 623b str r3, [r7, #32] __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); 8006520: 69bb ldr r3, [r7, #24] 8006522: f503 5380 add.w r3, r3, #4096 @ 0x1000 8006526: 461a mov r2, r3 8006528: f107 0310 add.w r3, r7, #16 800652c: 6812 ldr r2, [r2, #0] 800652e: 601a str r2, [r3, #0] do { *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); 8006530: 693a ldr r2, [r7, #16] 8006532: 6a3b ldr r3, [r7, #32] 8006534: b2db uxtb r3, r3 8006536: 00db lsls r3, r3, #3 8006538: fa22 f303 lsr.w r3, r2, r3 800653c: b2da uxtb r2, r3 800653e: 6a7b ldr r3, [r7, #36] @ 0x24 8006540: 701a strb r2, [r3, #0] i++; 8006542: 6a3b ldr r3, [r7, #32] 8006544: 3301 adds r3, #1 8006546: 623b str r3, [r7, #32] pDest++; 8006548: 6a7b ldr r3, [r7, #36] @ 0x24 800654a: 3301 adds r3, #1 800654c: 627b str r3, [r7, #36] @ 0x24 remaining_bytes--; 800654e: 8bfb ldrh r3, [r7, #30] 8006550: 3b01 subs r3, #1 8006552: 83fb strh r3, [r7, #30] } while (remaining_bytes != 0U); 8006554: 8bfb ldrh r3, [r7, #30] 8006556: 2b00 cmp r3, #0 8006558: d1ea bne.n 8006530 } return ((void *)pDest); 800655a: 6a7b ldr r3, [r7, #36] @ 0x24 } 800655c: 4618 mov r0, r3 800655e: 372c adds r7, #44 @ 0x2c 8006560: 46bd mov sp, r7 8006562: f85d 7b04 ldr.w r7, [sp], #4 8006566: 4770 bx lr 08006568 : * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device * @retval USB Global Interrupt status */ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) { 8006568: b480 push {r7} 800656a: b085 sub sp, #20 800656c: af00 add r7, sp, #0 800656e: 6078 str r0, [r7, #4] uint32_t tmpreg; tmpreg = USBx->GINTSTS; 8006570: 687b ldr r3, [r7, #4] 8006572: 695b ldr r3, [r3, #20] 8006574: 60fb str r3, [r7, #12] tmpreg &= USBx->GINTMSK; 8006576: 687b ldr r3, [r7, #4] 8006578: 699b ldr r3, [r3, #24] 800657a: 68fa ldr r2, [r7, #12] 800657c: 4013 ands r3, r2 800657e: 60fb str r3, [r7, #12] return tmpreg; 8006580: 68fb ldr r3, [r7, #12] } 8006582: 4618 mov r0, r3 8006584: 3714 adds r7, #20 8006586: 46bd mov sp, r7 8006588: f85d 7b04 ldr.w r7, [sp], #4 800658c: 4770 bx lr 0800658e : * @param USBx Selected device * @param chnum Channel number * @retval USB Channel Interrupt status */ uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) { 800658e: b480 push {r7} 8006590: b085 sub sp, #20 8006592: af00 add r7, sp, #0 8006594: 6078 str r0, [r7, #4] 8006596: 460b mov r3, r1 8006598: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 800659a: 687b ldr r3, [r7, #4] 800659c: 60fb str r3, [r7, #12] uint32_t tmpreg; tmpreg = USBx_HC(chnum)->HCINT; 800659e: 78fb ldrb r3, [r7, #3] 80065a0: 015a lsls r2, r3, #5 80065a2: 68fb ldr r3, [r7, #12] 80065a4: 4413 add r3, r2 80065a6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80065aa: 689b ldr r3, [r3, #8] 80065ac: 60bb str r3, [r7, #8] tmpreg &= USBx_HC(chnum)->HCINTMSK; 80065ae: 78fb ldrb r3, [r7, #3] 80065b0: 015a lsls r2, r3, #5 80065b2: 68fb ldr r3, [r7, #12] 80065b4: 4413 add r3, r2 80065b6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80065ba: 68db ldr r3, [r3, #12] 80065bc: 68ba ldr r2, [r7, #8] 80065be: 4013 ands r3, r2 80065c0: 60bb str r3, [r7, #8] return tmpreg; 80065c2: 68bb ldr r3, [r7, #8] } 80065c4: 4618 mov r0, r3 80065c6: 3714 adds r7, #20 80065c8: 46bd mov sp, r7 80065ca: f85d 7b04 ldr.w r7, [sp], #4 80065ce: 4770 bx lr 080065d0 : * This parameter can be one of these values: * 1 : Host * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { 80065d0: b480 push {r7} 80065d2: b083 sub sp, #12 80065d4: af00 add r7, sp, #0 80065d6: 6078 str r0, [r7, #4] return ((USBx->GINTSTS) & 0x1U); 80065d8: 687b ldr r3, [r7, #4] 80065da: 695b ldr r3, [r3, #20] 80065dc: f003 0301 and.w r3, r3, #1 } 80065e0: 4618 mov r0, r3 80065e2: 370c adds r7, #12 80065e4: 46bd mov sp, r7 80065e6: f85d 7b04 ldr.w r7, [sp], #4 80065ea: 4770 bx lr 080065ec : * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock * @retval HAL status */ HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) { 80065ec: b480 push {r7} 80065ee: b085 sub sp, #20 80065f0: af00 add r7, sp, #0 80065f2: 6078 str r0, [r7, #4] 80065f4: 460b mov r3, r1 80065f6: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 80065f8: 687b ldr r3, [r7, #4] 80065fa: 60fb str r3, [r7, #12] USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); 80065fc: 68fb ldr r3, [r7, #12] 80065fe: f503 6380 add.w r3, r3, #1024 @ 0x400 8006602: 681b ldr r3, [r3, #0] 8006604: 68fa ldr r2, [r7, #12] 8006606: f502 6280 add.w r2, r2, #1024 @ 0x400 800660a: f023 0303 bic.w r3, r3, #3 800660e: 6013 str r3, [r2, #0] USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; 8006610: 68fb ldr r3, [r7, #12] 8006612: f503 6380 add.w r3, r3, #1024 @ 0x400 8006616: 681a ldr r2, [r3, #0] 8006618: 78fb ldrb r3, [r7, #3] 800661a: f003 0303 and.w r3, r3, #3 800661e: 68f9 ldr r1, [r7, #12] 8006620: f501 6180 add.w r1, r1, #1024 @ 0x400 8006624: 4313 orrs r3, r2 8006626: 600b str r3, [r1, #0] if (freq == HCFG_48_MHZ) 8006628: 78fb ldrb r3, [r7, #3] 800662a: 2b01 cmp r3, #1 800662c: d107 bne.n 800663e { USBx_HOST->HFIR = HFIR_48_MHZ; 800662e: 68fb ldr r3, [r7, #12] 8006630: f503 6380 add.w r3, r3, #1024 @ 0x400 8006634: 461a mov r2, r3 8006636: f64b 3380 movw r3, #48000 @ 0xbb80 800663a: 6053 str r3, [r2, #4] 800663c: e00c b.n 8006658 } else if (freq == HCFG_6_MHZ) 800663e: 78fb ldrb r3, [r7, #3] 8006640: 2b02 cmp r3, #2 8006642: d107 bne.n 8006654 { USBx_HOST->HFIR = HFIR_6_MHZ; 8006644: 68fb ldr r3, [r7, #12] 8006646: f503 6380 add.w r3, r3, #1024 @ 0x400 800664a: 461a mov r2, r3 800664c: f241 7370 movw r3, #6000 @ 0x1770 8006650: 6053 str r3, [r2, #4] 8006652: e001 b.n 8006658 } else { return HAL_ERROR; 8006654: 2301 movs r3, #1 8006656: e000 b.n 800665a } return HAL_OK; 8006658: 2300 movs r3, #0 } 800665a: 4618 mov r0, r3 800665c: 3714 adds r7, #20 800665e: 46bd mov sp, r7 8006660: f85d 7b04 ldr.w r7, [sp], #4 8006664: 4770 bx lr 08006666 : * @brief Read all host channel interrupts status * @param USBx Selected device * @retval HAL state */ uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) { 8006666: b480 push {r7} 8006668: b085 sub sp, #20 800666a: af00 add r7, sp, #0 800666c: 6078 str r0, [r7, #4] uint32_t USBx_BASE = (uint32_t)USBx; 800666e: 687b ldr r3, [r7, #4] 8006670: 60fb str r3, [r7, #12] return ((USBx_HOST->HAINT) & 0xFFFFU); 8006672: 68fb ldr r3, [r7, #12] 8006674: f503 6380 add.w r3, r3, #1024 @ 0x400 8006678: 695b ldr r3, [r3, #20] 800667a: b29b uxth r3, r3 } 800667c: 4618 mov r0, r3 800667e: 3714 adds r7, #20 8006680: 46bd mov sp, r7 8006682: f85d 7b04 ldr.w r7, [sp], #4 8006686: 4770 bx lr 08006688 : * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { 8006688: b480 push {r7} 800668a: b089 sub sp, #36 @ 0x24 800668c: af00 add r7, sp, #0 800668e: 6078 str r0, [r7, #4] 8006690: 460b mov r3, r1 8006692: 70fb strb r3, [r7, #3] uint32_t USBx_BASE = (uint32_t)USBx; 8006694: 687b ldr r3, [r7, #4] 8006696: 61fb str r3, [r7, #28] uint32_t hcnum = (uint32_t)hc_num; 8006698: 78fb ldrb r3, [r7, #3] 800669a: 61bb str r3, [r7, #24] __IO uint32_t count = 0U; 800669c: 2300 movs r3, #0 800669e: 60bb str r3, [r7, #8] uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; 80066a0: 69bb ldr r3, [r7, #24] 80066a2: 015a lsls r2, r3, #5 80066a4: 69fb ldr r3, [r7, #28] 80066a6: 4413 add r3, r2 80066a8: f503 63a0 add.w r3, r3, #1280 @ 0x500 80066ac: 681b ldr r3, [r3, #0] 80066ae: 0c9b lsrs r3, r3, #18 80066b0: f003 0303 and.w r3, r3, #3 80066b4: 617b str r3, [r7, #20] uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; 80066b6: 69bb ldr r3, [r7, #24] 80066b8: 015a lsls r2, r3, #5 80066ba: 69fb ldr r3, [r7, #28] 80066bc: 4413 add r3, r2 80066be: f503 63a0 add.w r3, r3, #1280 @ 0x500 80066c2: 681b ldr r3, [r3, #0] 80066c4: 0fdb lsrs r3, r3, #31 80066c6: f003 0301 and.w r3, r3, #1 80066ca: 613b str r3, [r7, #16] uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; 80066cc: 69bb ldr r3, [r7, #24] 80066ce: 015a lsls r2, r3, #5 80066d0: 69fb ldr r3, [r7, #28] 80066d2: 4413 add r3, r2 80066d4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80066d8: 685b ldr r3, [r3, #4] 80066da: 0fdb lsrs r3, r3, #31 80066dc: f003 0301 and.w r3, r3, #1 80066e0: 60fb str r3, [r7, #12] /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. At the end of the next uframe/frame (in the worst case), the core generates a channel halted and disables the channel automatically. */ if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && 80066e2: 687b ldr r3, [r7, #4] 80066e4: 689b ldr r3, [r3, #8] 80066e6: f003 0320 and.w r3, r3, #32 80066ea: 2b20 cmp r3, #32 80066ec: d10d bne.n 800670a 80066ee: 68fb ldr r3, [r7, #12] 80066f0: 2b00 cmp r3, #0 80066f2: d10a bne.n 800670a 80066f4: 693b ldr r3, [r7, #16] 80066f6: 2b00 cmp r3, #0 80066f8: d005 beq.n 8006706 ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) 80066fa: 697b ldr r3, [r7, #20] 80066fc: 2b01 cmp r3, #1 80066fe: d002 beq.n 8006706 8006700: 697b ldr r3, [r7, #20] 8006702: 2b03 cmp r3, #3 8006704: d101 bne.n 800670a { return HAL_OK; 8006706: 2300 movs r3, #0 8006708: e0d8 b.n 80068bc } /* Check for space in the request queue to issue the halt. */ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) 800670a: 697b ldr r3, [r7, #20] 800670c: 2b00 cmp r3, #0 800670e: d002 beq.n 8006716 8006710: 697b ldr r3, [r7, #20] 8006712: 2b02 cmp r3, #2 8006714: d173 bne.n 80067fe { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 8006716: 69bb ldr r3, [r7, #24] 8006718: 015a lsls r2, r3, #5 800671a: 69fb ldr r3, [r7, #28] 800671c: 4413 add r3, r2 800671e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006722: 681b ldr r3, [r3, #0] 8006724: 69ba ldr r2, [r7, #24] 8006726: 0151 lsls r1, r2, #5 8006728: 69fa ldr r2, [r7, #28] 800672a: 440a add r2, r1 800672c: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006730: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8006734: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 8006736: 687b ldr r3, [r7, #4] 8006738: 689b ldr r3, [r3, #8] 800673a: f003 0320 and.w r3, r3, #32 800673e: 2b00 cmp r3, #0 8006740: d14a bne.n 80067d8 { if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) 8006742: 687b ldr r3, [r7, #4] 8006744: 6adb ldr r3, [r3, #44] @ 0x2c 8006746: f403 037f and.w r3, r3, #16711680 @ 0xff0000 800674a: 2b00 cmp r3, #0 800674c: d133 bne.n 80067b6 { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 800674e: 69bb ldr r3, [r7, #24] 8006750: 015a lsls r2, r3, #5 8006752: 69fb ldr r3, [r7, #28] 8006754: 4413 add r3, r2 8006756: f503 63a0 add.w r3, r3, #1280 @ 0x500 800675a: 681b ldr r3, [r3, #0] 800675c: 69ba ldr r2, [r7, #24] 800675e: 0151 lsls r1, r2, #5 8006760: 69fa ldr r2, [r7, #28] 8006762: 440a add r2, r1 8006764: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006768: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 800676c: 6013 str r3, [r2, #0] USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 800676e: 69bb ldr r3, [r7, #24] 8006770: 015a lsls r2, r3, #5 8006772: 69fb ldr r3, [r7, #28] 8006774: 4413 add r3, r2 8006776: f503 63a0 add.w r3, r3, #1280 @ 0x500 800677a: 681b ldr r3, [r3, #0] 800677c: 69ba ldr r2, [r7, #24] 800677e: 0151 lsls r1, r2, #5 8006780: 69fa ldr r2, [r7, #28] 8006782: 440a add r2, r1 8006784: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006788: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800678c: 6013 str r3, [r2, #0] do { count++; 800678e: 68bb ldr r3, [r7, #8] 8006790: 3301 adds r3, #1 8006792: 60bb str r3, [r7, #8] if (count > 1000U) 8006794: 68bb ldr r3, [r7, #8] 8006796: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800679a: d82e bhi.n 80067fa { break; } } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 800679c: 69bb ldr r3, [r7, #24] 800679e: 015a lsls r2, r3, #5 80067a0: 69fb ldr r3, [r7, #28] 80067a2: 4413 add r3, r2 80067a4: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067a8: 681b ldr r3, [r3, #0] 80067aa: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80067ae: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80067b2: d0ec beq.n 800678e if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 80067b4: e081 b.n 80068ba } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 80067b6: 69bb ldr r3, [r7, #24] 80067b8: 015a lsls r2, r3, #5 80067ba: 69fb ldr r3, [r7, #28] 80067bc: 4413 add r3, r2 80067be: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067c2: 681b ldr r3, [r3, #0] 80067c4: 69ba ldr r2, [r7, #24] 80067c6: 0151 lsls r1, r2, #5 80067c8: 69fa ldr r2, [r7, #28] 80067ca: 440a add r2, r1 80067cc: f502 62a0 add.w r2, r2, #1280 @ 0x500 80067d0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80067d4: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 80067d6: e070 b.n 80068ba } } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 80067d8: 69bb ldr r3, [r7, #24] 80067da: 015a lsls r2, r3, #5 80067dc: 69fb ldr r3, [r7, #28] 80067de: 4413 add r3, r2 80067e0: f503 63a0 add.w r3, r3, #1280 @ 0x500 80067e4: 681b ldr r3, [r3, #0] 80067e6: 69ba ldr r2, [r7, #24] 80067e8: 0151 lsls r1, r2, #5 80067ea: 69fa ldr r2, [r7, #28] 80067ec: 440a add r2, r1 80067ee: f502 62a0 add.w r2, r2, #1280 @ 0x500 80067f2: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80067f6: 6013 str r3, [r2, #0] if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 80067f8: e05f b.n 80068ba break; 80067fa: bf00 nop if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) 80067fc: e05d b.n 80068ba } } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 80067fe: 69bb ldr r3, [r7, #24] 8006800: 015a lsls r2, r3, #5 8006802: 69fb ldr r3, [r7, #28] 8006804: 4413 add r3, r2 8006806: f503 63a0 add.w r3, r3, #1280 @ 0x500 800680a: 681b ldr r3, [r3, #0] 800680c: 69ba ldr r2, [r7, #24] 800680e: 0151 lsls r1, r2, #5 8006810: 69fa ldr r2, [r7, #28] 8006812: 440a add r2, r1 8006814: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006818: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800681c: 6013 str r3, [r2, #0] if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) 800681e: 69fb ldr r3, [r7, #28] 8006820: f503 6380 add.w r3, r3, #1024 @ 0x400 8006824: 691b ldr r3, [r3, #16] 8006826: f403 037f and.w r3, r3, #16711680 @ 0xff0000 800682a: 2b00 cmp r3, #0 800682c: d133 bne.n 8006896 { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 800682e: 69bb ldr r3, [r7, #24] 8006830: 015a lsls r2, r3, #5 8006832: 69fb ldr r3, [r7, #28] 8006834: 4413 add r3, r2 8006836: f503 63a0 add.w r3, r3, #1280 @ 0x500 800683a: 681b ldr r3, [r3, #0] 800683c: 69ba ldr r2, [r7, #24] 800683e: 0151 lsls r1, r2, #5 8006840: 69fa ldr r2, [r7, #28] 8006842: 440a add r2, r1 8006844: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006848: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 800684c: 6013 str r3, [r2, #0] USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 800684e: 69bb ldr r3, [r7, #24] 8006850: 015a lsls r2, r3, #5 8006852: 69fb ldr r3, [r7, #28] 8006854: 4413 add r3, r2 8006856: f503 63a0 add.w r3, r3, #1280 @ 0x500 800685a: 681b ldr r3, [r3, #0] 800685c: 69ba ldr r2, [r7, #24] 800685e: 0151 lsls r1, r2, #5 8006860: 69fa ldr r2, [r7, #28] 8006862: 440a add r2, r1 8006864: f502 62a0 add.w r2, r2, #1280 @ 0x500 8006868: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 800686c: 6013 str r3, [r2, #0] do { count++; 800686e: 68bb ldr r3, [r7, #8] 8006870: 3301 adds r3, #1 8006872: 60bb str r3, [r7, #8] if (count > 1000U) 8006874: 68bb ldr r3, [r7, #8] 8006876: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800687a: d81d bhi.n 80068b8 { break; } } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 800687c: 69bb ldr r3, [r7, #24] 800687e: 015a lsls r2, r3, #5 8006880: 69fb ldr r3, [r7, #28] 8006882: 4413 add r3, r2 8006884: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006888: 681b ldr r3, [r3, #0] 800688a: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 800688e: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 8006892: d0ec beq.n 800686e 8006894: e011 b.n 80068ba } else { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 8006896: 69bb ldr r3, [r7, #24] 8006898: 015a lsls r2, r3, #5 800689a: 69fb ldr r3, [r7, #28] 800689c: 4413 add r3, r2 800689e: f503 63a0 add.w r3, r3, #1280 @ 0x500 80068a2: 681b ldr r3, [r3, #0] 80068a4: 69ba ldr r2, [r7, #24] 80068a6: 0151 lsls r1, r2, #5 80068a8: 69fa ldr r2, [r7, #28] 80068aa: 440a add r2, r1 80068ac: f502 62a0 add.w r2, r2, #1280 @ 0x500 80068b0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 80068b4: 6013 str r3, [r2, #0] 80068b6: e000 b.n 80068ba break; 80068b8: bf00 nop } } return HAL_OK; 80068ba: 2300 movs r3, #0 } 80068bc: 4618 mov r0, r3 80068be: 3724 adds r7, #36 @ 0x24 80068c0: 46bd mov sp, r7 80068c2: f85d 7b04 ldr.w r7, [sp], #4 80068c6: 4770 bx lr 080068c8 : * @brief Stop Host Core * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { 80068c8: b580 push {r7, lr} 80068ca: b088 sub sp, #32 80068cc: af00 add r7, sp, #0 80068ce: 6078 str r0, [r7, #4] HAL_StatusTypeDef ret = HAL_OK; 80068d0: 2300 movs r3, #0 80068d2: 77fb strb r3, [r7, #31] uint32_t USBx_BASE = (uint32_t)USBx; 80068d4: 687b ldr r3, [r7, #4] 80068d6: 617b str r3, [r7, #20] __IO uint32_t count = 0U; 80068d8: 2300 movs r3, #0 80068da: 60fb str r3, [r7, #12] uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); 80068dc: 6878 ldr r0, [r7, #4] 80068de: f7ff fd7a bl 80063d6 /* Flush USB FIFO */ if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ 80068e2: 2110 movs r1, #16 80068e4: 6878 ldr r0, [r7, #4] 80068e6: f7ff fd87 bl 80063f8 80068ea: 4603 mov r3, r0 80068ec: 2b00 cmp r3, #0 80068ee: d001 beq.n 80068f4 { ret = HAL_ERROR; 80068f0: 2301 movs r3, #1 80068f2: 77fb strb r3, [r7, #31] } if (USB_FlushRxFifo(USBx) != HAL_OK) 80068f4: 6878 ldr r0, [r7, #4] 80068f6: f7ff fdb1 bl 800645c 80068fa: 4603 mov r3, r0 80068fc: 2b00 cmp r3, #0 80068fe: d001 beq.n 8006904 { ret = HAL_ERROR; 8006900: 2301 movs r3, #1 8006902: 77fb strb r3, [r7, #31] } /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) 8006904: 2300 movs r3, #0 8006906: 61bb str r3, [r7, #24] 8006908: e01f b.n 800694a { value = USBx_HC(i)->HCCHAR; 800690a: 69bb ldr r3, [r7, #24] 800690c: 015a lsls r2, r3, #5 800690e: 697b ldr r3, [r7, #20] 8006910: 4413 add r3, r2 8006912: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006916: 681b ldr r3, [r3, #0] 8006918: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHDIS; 800691a: 693b ldr r3, [r7, #16] 800691c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 8006920: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_CHENA; 8006922: 693b ldr r3, [r7, #16] 8006924: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000 8006928: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_EPDIR; 800692a: 693b ldr r3, [r7, #16] 800692c: f423 4300 bic.w r3, r3, #32768 @ 0x8000 8006930: 613b str r3, [r7, #16] USBx_HC(i)->HCCHAR = value; 8006932: 69bb ldr r3, [r7, #24] 8006934: 015a lsls r2, r3, #5 8006936: 697b ldr r3, [r7, #20] 8006938: 4413 add r3, r2 800693a: f503 63a0 add.w r3, r3, #1280 @ 0x500 800693e: 461a mov r2, r3 8006940: 693b ldr r3, [r7, #16] 8006942: 6013 str r3, [r2, #0] for (i = 0U; i <= 15U; i++) 8006944: 69bb ldr r3, [r7, #24] 8006946: 3301 adds r3, #1 8006948: 61bb str r3, [r7, #24] 800694a: 69bb ldr r3, [r7, #24] 800694c: 2b0f cmp r3, #15 800694e: d9dc bls.n 800690a } /* Halt all channels to put them into a known state. */ for (i = 0U; i <= 15U; i++) 8006950: 2300 movs r3, #0 8006952: 61bb str r3, [r7, #24] 8006954: e034 b.n 80069c0 { value = USBx_HC(i)->HCCHAR; 8006956: 69bb ldr r3, [r7, #24] 8006958: 015a lsls r2, r3, #5 800695a: 697b ldr r3, [r7, #20] 800695c: 4413 add r3, r2 800695e: f503 63a0 add.w r3, r3, #1280 @ 0x500 8006962: 681b ldr r3, [r3, #0] 8006964: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHDIS; 8006966: 693b ldr r3, [r7, #16] 8006968: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000 800696c: 613b str r3, [r7, #16] value |= USB_OTG_HCCHAR_CHENA; 800696e: 693b ldr r3, [r7, #16] 8006970: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000 8006974: 613b str r3, [r7, #16] value &= ~USB_OTG_HCCHAR_EPDIR; 8006976: 693b ldr r3, [r7, #16] 8006978: f423 4300 bic.w r3, r3, #32768 @ 0x8000 800697c: 613b str r3, [r7, #16] USBx_HC(i)->HCCHAR = value; 800697e: 69bb ldr r3, [r7, #24] 8006980: 015a lsls r2, r3, #5 8006982: 697b ldr r3, [r7, #20] 8006984: 4413 add r3, r2 8006986: f503 63a0 add.w r3, r3, #1280 @ 0x500 800698a: 461a mov r2, r3 800698c: 693b ldr r3, [r7, #16] 800698e: 6013 str r3, [r2, #0] do { count++; 8006990: 68fb ldr r3, [r7, #12] 8006992: 3301 adds r3, #1 8006994: 60fb str r3, [r7, #12] if (count > 1000U) 8006996: 68fb ldr r3, [r7, #12] 8006998: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8 800699c: d80c bhi.n 80069b8 { break; } } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 800699e: 69bb ldr r3, [r7, #24] 80069a0: 015a lsls r2, r3, #5 80069a2: 697b ldr r3, [r7, #20] 80069a4: 4413 add r3, r2 80069a6: f503 63a0 add.w r3, r3, #1280 @ 0x500 80069aa: 681b ldr r3, [r3, #0] 80069ac: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000 80069b0: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000 80069b4: d0ec beq.n 8006990 80069b6: e000 b.n 80069ba break; 80069b8: bf00 nop for (i = 0U; i <= 15U; i++) 80069ba: 69bb ldr r3, [r7, #24] 80069bc: 3301 adds r3, #1 80069be: 61bb str r3, [r7, #24] 80069c0: 69bb ldr r3, [r7, #24] 80069c2: 2b0f cmp r3, #15 80069c4: d9c7 bls.n 8006956 } /* Clear any pending Host interrupts */ USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; 80069c6: 697b ldr r3, [r7, #20] 80069c8: f503 6380 add.w r3, r3, #1024 @ 0x400 80069cc: 461a mov r2, r3 80069ce: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff 80069d2: 6153 str r3, [r2, #20] USBx->GINTSTS = CLEAR_INTERRUPT_MASK; 80069d4: 687b ldr r3, [r7, #4] 80069d6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80069da: 615a str r2, [r3, #20] (void)USB_EnableGlobalInt(USBx); 80069dc: 6878 ldr r0, [r7, #4] 80069de: f7ff fce9 bl 80063b4 return ret; 80069e2: 7ffb ldrb r3, [r7, #31] } 80069e4: 4618 mov r0, r3 80069e6: 3720 adds r7, #32 80069e8: 46bd mov sp, r7 80069ea: bd80 pop {r7, pc} 080069ec : * Increment Host Timer tick * @param phost: Host Handle * @retval None */ void USBH_LL_IncTimer(USBH_HandleTypeDef *phost) { 80069ec: b580 push {r7, lr} 80069ee: b082 sub sp, #8 80069f0: af00 add r7, sp, #0 80069f2: 6078 str r0, [r7, #4] phost->Timer++; 80069f4: 687b ldr r3, [r7, #4] 80069f6: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4 80069fa: 1c5a adds r2, r3, #1 80069fc: 687b ldr r3, [r7, #4] 80069fe: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4 USBH_HandleSof(phost); 8006a02: 6878 ldr r0, [r7, #4] 8006a04: f000 f804 bl 8006a10 } 8006a08: bf00 nop 8006a0a: 3708 adds r7, #8 8006a0c: 46bd mov sp, r7 8006a0e: bd80 pop {r7, pc} 08006a10 : * Call SOF process * @param phost: Host Handle * @retval None */ static void USBH_HandleSof(USBH_HandleTypeDef *phost) { 8006a10: b580 push {r7, lr} 8006a12: b082 sub sp, #8 8006a14: af00 add r7, sp, #0 8006a16: 6078 str r0, [r7, #4] if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL)) 8006a18: 687b ldr r3, [r7, #4] 8006a1a: 781b ldrb r3, [r3, #0] 8006a1c: b2db uxtb r3, r3 8006a1e: 2b0b cmp r3, #11 8006a20: d10a bne.n 8006a38 8006a22: 687b ldr r3, [r7, #4] 8006a24: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c 8006a28: 2b00 cmp r3, #0 8006a2a: d005 beq.n 8006a38 { phost->pActiveClass->SOFProcess(phost); 8006a2c: 687b ldr r3, [r7, #4] 8006a2e: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c 8006a32: 699b ldr r3, [r3, #24] 8006a34: 6878 ldr r0, [r7, #4] 8006a36: 4798 blx r3 } } 8006a38: bf00 nop 8006a3a: 3708 adds r7, #8 8006a3c: 46bd mov sp, r7 8006a3e: bd80 pop {r7, pc} 08006a40 : * Port Enabled * @param phost: Host Handle * @retval None */ void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost) { 8006a40: b580 push {r7, lr} 8006a42: b082 sub sp, #8 8006a44: af00 add r7, sp, #0 8006a46: 6078 str r0, [r7, #4] phost->device.PortEnabled = 1U; 8006a48: 687b ldr r3, [r7, #4] 8006a4a: 2201 movs r2, #1 8006a4c: f883 2323 strb.w r2, [r3, #803] @ 0x323 #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006a50: 2300 movs r3, #0 8006a52: 2200 movs r2, #0 8006a54: 2101 movs r1, #1 8006a56: 6878 ldr r0, [r7, #4] 8006a58: f000 f85b bl 8006b12 #endif /* (USBH_USE_OS == 1U) */ return; 8006a5c: bf00 nop } 8006a5e: 3708 adds r7, #8 8006a60: 46bd mov sp, r7 8006a62: bd80 pop {r7, pc} 08006a64 : * Port Disabled * @param phost: Host Handle * @retval None */ void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost) { 8006a64: b480 push {r7} 8006a66: b083 sub sp, #12 8006a68: af00 add r7, sp, #0 8006a6a: 6078 str r0, [r7, #4] phost->device.PortEnabled = 0U; 8006a6c: 687b ldr r3, [r7, #4] 8006a6e: 2200 movs r2, #0 8006a70: f883 2323 strb.w r2, [r3, #803] @ 0x323 phost->device.is_disconnected = 1U; 8006a74: 687b ldr r3, [r7, #4] 8006a76: 2201 movs r2, #1 8006a78: f883 2321 strb.w r2, [r3, #801] @ 0x321 return; 8006a7c: bf00 nop } 8006a7e: 370c adds r7, #12 8006a80: 46bd mov sp, r7 8006a82: f85d 7b04 ldr.w r7, [sp], #4 8006a86: 4770 bx lr 08006a88 : * Handle USB Host connection event * @param phost: Host Handle * @retval USBH_Status */ USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost) { 8006a88: b580 push {r7, lr} 8006a8a: b082 sub sp, #8 8006a8c: af00 add r7, sp, #0 8006a8e: 6078 str r0, [r7, #4] phost->device.is_connected = 1U; 8006a90: 687b ldr r3, [r7, #4] 8006a92: 2201 movs r2, #1 8006a94: f883 2320 strb.w r2, [r3, #800] @ 0x320 phost->device.is_disconnected = 0U; 8006a98: 687b ldr r3, [r7, #4] 8006a9a: 2200 movs r2, #0 8006a9c: f883 2321 strb.w r2, [r3, #801] @ 0x321 phost->device.is_ReEnumerated = 0U; 8006aa0: 687b ldr r3, [r7, #4] 8006aa2: 2200 movs r2, #0 8006aa4: f883 2322 strb.w r2, [r3, #802] @ 0x322 #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006aa8: 2300 movs r3, #0 8006aaa: 2200 movs r2, #0 8006aac: 2101 movs r1, #1 8006aae: 6878 ldr r0, [r7, #4] 8006ab0: f000 f82f bl 8006b12 #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006ab4: 2300 movs r3, #0 } 8006ab6: 4618 mov r0, r3 8006ab8: 3708 adds r7, #8 8006aba: 46bd mov sp, r7 8006abc: bd80 pop {r7, pc} 08006abe : * Handle USB Host disconnection event * @param phost: Host Handle * @retval USBH_Status */ USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost) { 8006abe: b580 push {r7, lr} 8006ac0: b082 sub sp, #8 8006ac2: af00 add r7, sp, #0 8006ac4: 6078 str r0, [r7, #4] /* update device connection states */ phost->device.is_disconnected = 1U; 8006ac6: 687b ldr r3, [r7, #4] 8006ac8: 2201 movs r2, #1 8006aca: f883 2321 strb.w r2, [r3, #801] @ 0x321 phost->device.is_connected = 0U; 8006ace: 687b ldr r3, [r7, #4] 8006ad0: 2200 movs r2, #0 8006ad2: f883 2320 strb.w r2, [r3, #800] @ 0x320 phost->device.PortEnabled = 0U; 8006ad6: 687b ldr r3, [r7, #4] 8006ad8: 2200 movs r2, #0 8006ada: f883 2323 strb.w r2, [r3, #803] @ 0x323 /* Stop Host */ (void)USBH_LL_Stop(phost); 8006ade: 6878 ldr r0, [r7, #4] 8006ae0: f001 f996 bl 8007e10 /* FRee Control Pipes */ (void)USBH_FreePipe(phost, phost->Control.pipe_in); 8006ae4: 687b ldr r3, [r7, #4] 8006ae6: 791b ldrb r3, [r3, #4] 8006ae8: 4619 mov r1, r3 8006aea: 6878 ldr r0, [r7, #4] 8006aec: f000 f847 bl 8006b7e (void)USBH_FreePipe(phost, phost->Control.pipe_out); 8006af0: 687b ldr r3, [r7, #4] 8006af2: 795b ldrb r3, [r3, #5] 8006af4: 4619 mov r1, r3 8006af6: 6878 ldr r0, [r7, #4] 8006af8: f000 f841 bl 8006b7e #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006afc: 2300 movs r3, #0 8006afe: 2200 movs r2, #0 8006b00: 2101 movs r1, #1 8006b02: 6878 ldr r0, [r7, #4] 8006b04: f000 f805 bl 8006b12 #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006b08: 2300 movs r3, #0 } 8006b0a: 4618 mov r0, r3 8006b0c: 3708 adds r7, #8 8006b0e: 46bd mov sp, r7 8006b10: bd80 pop {r7, pc} 08006b12 : * @param timeout message event timeout * @param priority message event priority * @retval None */ void USBH_OS_PutMessage(USBH_HandleTypeDef *phost, USBH_OSEventTypeDef message, uint32_t timeout, uint32_t priority) { 8006b12: b580 push {r7, lr} 8006b14: b086 sub sp, #24 8006b16: af00 add r7, sp, #0 8006b18: 60f8 str r0, [r7, #12] 8006b1a: 607a str r2, [r7, #4] 8006b1c: 603b str r3, [r7, #0] 8006b1e: 460b mov r3, r1 8006b20: 72fb strb r3, [r7, #11] phost->os_msg = (uint32_t)message; 8006b22: 7afa ldrb r2, [r7, #11] 8006b24: 68fb ldr r3, [r7, #12] 8006b26: f8c3 23e0 str.w r2, [r3, #992] @ 0x3e0 #if (osCMSIS < 0x20000U) UNUSED(priority); /* Calculate the number of available spaces */ uint32_t available_spaces = MSGQUEUE_OBJECTS - osMessageWaiting(phost->os_event); 8006b2a: 68fb ldr r3, [r7, #12] 8006b2c: f8d3 33d8 ldr.w r3, [r3, #984] @ 0x3d8 8006b30: 4618 mov r0, r3 8006b32: f000 f895 bl 8006c60 8006b36: 4603 mov r3, r0 8006b38: f1c3 0310 rsb r3, r3, #16 8006b3c: 617b str r3, [r7, #20] if (available_spaces != 0U) 8006b3e: 697b ldr r3, [r7, #20] 8006b40: 2b00 cmp r3, #0 8006b42: d009 beq.n 8006b58 { (void)osMessagePut(phost->os_event, phost->os_msg, timeout); 8006b44: 68fb ldr r3, [r7, #12] 8006b46: f8d3 03d8 ldr.w r0, [r3, #984] @ 0x3d8 8006b4a: 68fb ldr r3, [r7, #12] 8006b4c: f8d3 33e0 ldr.w r3, [r3, #992] @ 0x3e0 8006b50: 687a ldr r2, [r7, #4] 8006b52: 4619 mov r1, r3 8006b54: f000 f844 bl 8006be0 if (osMessageQueueGetSpace(phost->os_event) != 0U) { (void)osMessageQueuePut(phost->os_event, &phost->os_msg, priority, timeout); } #endif /* (osCMSIS < 0x20000U) */ } 8006b58: bf00 nop 8006b5a: 3718 adds r7, #24 8006b5c: 46bd mov sp, r7 8006b5e: bd80 pop {r7, pc} 08006b60 : * Notify URB state Change * @param phost: Host handle * @retval USBH Status */ USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost) { 8006b60: b580 push {r7, lr} 8006b62: b082 sub sp, #8 8006b64: af00 add r7, sp, #0 8006b66: 6078 str r0, [r7, #4] #if (USBH_USE_OS == 1U) USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U); 8006b68: 2300 movs r3, #0 8006b6a: 2200 movs r2, #0 8006b6c: 2101 movs r1, #1 8006b6e: 6878 ldr r0, [r7, #4] 8006b70: f7ff ffcf bl 8006b12 #endif /* (USBH_USE_OS == 1U) */ return USBH_OK; 8006b74: 2300 movs r3, #0 } 8006b76: 4618 mov r0, r3 8006b78: 3708 adds r7, #8 8006b7a: 46bd mov sp, r7 8006b7c: bd80 pop {r7, pc} 08006b7e : * @param phost: Host Handle * @param idx: Pipe number to be freed * @retval USBH Status */ USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx) { 8006b7e: b480 push {r7} 8006b80: b083 sub sp, #12 8006b82: af00 add r7, sp, #0 8006b84: 6078 str r0, [r7, #4] 8006b86: 460b mov r3, r1 8006b88: 70fb strb r3, [r7, #3] if (idx < USBH_MAX_PIPES_NBR) 8006b8a: 78fb ldrb r3, [r7, #3] 8006b8c: 2b0f cmp r3, #15 8006b8e: d80d bhi.n 8006bac { phost->Pipes[idx] &= 0x7FFFU; 8006b90: 78fb ldrb r3, [r7, #3] 8006b92: 687a ldr r2, [r7, #4] 8006b94: 33e0 adds r3, #224 @ 0xe0 8006b96: 009b lsls r3, r3, #2 8006b98: 4413 add r3, r2 8006b9a: 685a ldr r2, [r3, #4] 8006b9c: 78fb ldrb r3, [r7, #3] 8006b9e: f3c2 020e ubfx r2, r2, #0, #15 8006ba2: 6879 ldr r1, [r7, #4] 8006ba4: 33e0 adds r3, #224 @ 0xe0 8006ba6: 009b lsls r3, r3, #2 8006ba8: 440b add r3, r1 8006baa: 605a str r2, [r3, #4] } return USBH_OK; 8006bac: 2300 movs r3, #0 } 8006bae: 4618 mov r0, r3 8006bb0: 370c adds r7, #12 8006bb2: 46bd mov sp, r7 8006bb4: f85d 7b04 ldr.w r7, [sp], #4 8006bb8: 4770 bx lr 08006bba : #endif /* Determine whether we are in thread mode or handler mode. */ static int inHandlerMode (void) { 8006bba: b480 push {r7} 8006bbc: b083 sub sp, #12 8006bbe: af00 add r7, sp, #0 */ __STATIC_FORCEINLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 8006bc0: f3ef 8305 mrs r3, IPSR 8006bc4: 607b str r3, [r7, #4] return(result); 8006bc6: 687b ldr r3, [r7, #4] return __get_IPSR() != 0; 8006bc8: 2b00 cmp r3, #0 8006bca: bf14 ite ne 8006bcc: 2301 movne r3, #1 8006bce: 2300 moveq r3, #0 8006bd0: b2db uxtb r3, r3 } 8006bd2: 4618 mov r0, r3 8006bd4: 370c adds r7, #12 8006bd6: 46bd mov sp, r7 8006bd8: f85d 7b04 ldr.w r7, [sp], #4 8006bdc: 4770 bx lr ... 08006be0 : * @param millisec timeout value or 0 in case of no time-out. * @retval status code that indicates the execution status of the function. * @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. */ osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { 8006be0: b580 push {r7, lr} 8006be2: b086 sub sp, #24 8006be4: af00 add r7, sp, #0 8006be6: 60f8 str r0, [r7, #12] 8006be8: 60b9 str r1, [r7, #8] 8006bea: 607a str r2, [r7, #4] portBASE_TYPE taskWoken = pdFALSE; 8006bec: 2300 movs r3, #0 8006bee: 613b str r3, [r7, #16] TickType_t ticks; ticks = millisec / portTICK_PERIOD_MS; 8006bf0: 687b ldr r3, [r7, #4] 8006bf2: 617b str r3, [r7, #20] if (ticks == 0) { 8006bf4: 697b ldr r3, [r7, #20] 8006bf6: 2b00 cmp r3, #0 8006bf8: d101 bne.n 8006bfe ticks = 1; 8006bfa: 2301 movs r3, #1 8006bfc: 617b str r3, [r7, #20] } if (inHandlerMode()) { 8006bfe: f7ff ffdc bl 8006bba 8006c02: 4603 mov r3, r0 8006c04: 2b00 cmp r3, #0 8006c06: d018 beq.n 8006c3a if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) { 8006c08: f107 0210 add.w r2, r7, #16 8006c0c: f107 0108 add.w r1, r7, #8 8006c10: 2300 movs r3, #0 8006c12: 68f8 ldr r0, [r7, #12] 8006c14: f000 f9c4 bl 8006fa0 8006c18: 4603 mov r3, r0 8006c1a: 2b01 cmp r3, #1 8006c1c: d001 beq.n 8006c22 return osErrorOS; 8006c1e: 23ff movs r3, #255 @ 0xff 8006c20: e018 b.n 8006c54 } portEND_SWITCHING_ISR(taskWoken); 8006c22: 693b ldr r3, [r7, #16] 8006c24: 2b00 cmp r3, #0 8006c26: d014 beq.n 8006c52 8006c28: 4b0c ldr r3, [pc, #48] @ (8006c5c ) 8006c2a: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006c2e: 601a str r2, [r3, #0] 8006c30: f3bf 8f4f dsb sy 8006c34: f3bf 8f6f isb sy 8006c38: e00b b.n 8006c52 } else { if (xQueueSend(queue_id, &info, ticks) != pdTRUE) { 8006c3a: f107 0108 add.w r1, r7, #8 8006c3e: 2300 movs r3, #0 8006c40: 697a ldr r2, [r7, #20] 8006c42: 68f8 ldr r0, [r7, #12] 8006c44: f000 f8aa bl 8006d9c 8006c48: 4603 mov r3, r0 8006c4a: 2b01 cmp r3, #1 8006c4c: d001 beq.n 8006c52 return osErrorOS; 8006c4e: 23ff movs r3, #255 @ 0xff 8006c50: e000 b.n 8006c54 } } return osOK; 8006c52: 2300 movs r3, #0 } 8006c54: 4618 mov r0, r3 8006c56: 3718 adds r7, #24 8006c58: 46bd mov sp, r7 8006c5a: bd80 pop {r7, pc} 8006c5c: e000ed04 .word 0xe000ed04 08006c60 : * @brief Get the number of messaged stored in a queue. * @param queue_id message queue ID obtained with \ref osMessageCreate. * @retval number of messages stored in a queue. */ uint32_t osMessageWaiting(osMessageQId queue_id) { 8006c60: b580 push {r7, lr} 8006c62: b082 sub sp, #8 8006c64: af00 add r7, sp, #0 8006c66: 6078 str r0, [r7, #4] if (inHandlerMode()) { 8006c68: f7ff ffa7 bl 8006bba 8006c6c: 4603 mov r3, r0 8006c6e: 2b00 cmp r3, #0 8006c70: d004 beq.n 8006c7c return uxQueueMessagesWaitingFromISR(queue_id); 8006c72: 6878 ldr r0, [r7, #4] 8006c74: f000 fa51 bl 800711a 8006c78: 4603 mov r3, r0 8006c7a: e003 b.n 8006c84 } else { return uxQueueMessagesWaiting(queue_id); 8006c7c: 6878 ldr r0, [r7, #4] 8006c7e: f000 fa2d bl 80070dc 8006c82: 4603 mov r3, r0 } } 8006c84: 4618 mov r0, r3 8006c86: 3708 adds r7, #8 8006c88: 46bd mov sp, r7 8006c8a: bd80 pop {r7, pc} 08006c8c : listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8006c8c: b480 push {r7} 8006c8e: b085 sub sp, #20 8006c90: af00 add r7, sp, #0 8006c92: 6078 str r0, [r7, #4] 8006c94: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; 8006c96: 687b ldr r3, [r7, #4] 8006c98: 685b ldr r3, [r3, #4] 8006c9a: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; 8006c9c: 683b ldr r3, [r7, #0] 8006c9e: 68fa ldr r2, [r7, #12] 8006ca0: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; 8006ca2: 68fb ldr r3, [r7, #12] 8006ca4: 689a ldr r2, [r3, #8] 8006ca6: 683b ldr r3, [r7, #0] 8006ca8: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; 8006caa: 68fb ldr r3, [r7, #12] 8006cac: 689b ldr r3, [r3, #8] 8006cae: 683a ldr r2, [r7, #0] 8006cb0: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; 8006cb2: 68fb ldr r3, [r7, #12] 8006cb4: 683a ldr r2, [r7, #0] 8006cb6: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; 8006cb8: 683b ldr r3, [r7, #0] 8006cba: 687a ldr r2, [r7, #4] 8006cbc: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8006cbe: 687b ldr r3, [r7, #4] 8006cc0: 681b ldr r3, [r3, #0] 8006cc2: 1c5a adds r2, r3, #1 8006cc4: 687b ldr r3, [r7, #4] 8006cc6: 601a str r2, [r3, #0] } 8006cc8: bf00 nop 8006cca: 3714 adds r7, #20 8006ccc: 46bd mov sp, r7 8006cce: f85d 7b04 ldr.w r7, [sp], #4 8006cd2: 4770 bx lr 08006cd4 : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { 8006cd4: b480 push {r7} 8006cd6: b085 sub sp, #20 8006cd8: af00 add r7, sp, #0 8006cda: 6078 str r0, [r7, #4] 8006cdc: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; 8006cde: 683b ldr r3, [r7, #0] 8006ce0: 681b ldr r3, [r3, #0] 8006ce2: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) 8006ce4: 68bb ldr r3, [r7, #8] 8006ce6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006cea: d103 bne.n 8006cf4 { pxIterator = pxList->xListEnd.pxPrevious; 8006cec: 687b ldr r3, [r7, #4] 8006cee: 691b ldr r3, [r3, #16] 8006cf0: 60fb str r3, [r7, #12] 8006cf2: e00c b.n 8006d0e 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ 8006cf4: 687b ldr r3, [r7, #4] 8006cf6: 3308 adds r3, #8 8006cf8: 60fb str r3, [r7, #12] 8006cfa: e002 b.n 8006d02 8006cfc: 68fb ldr r3, [r7, #12] 8006cfe: 685b ldr r3, [r3, #4] 8006d00: 60fb str r3, [r7, #12] 8006d02: 68fb ldr r3, [r7, #12] 8006d04: 685b ldr r3, [r3, #4] 8006d06: 681b ldr r3, [r3, #0] 8006d08: 68ba ldr r2, [r7, #8] 8006d0a: 429a cmp r2, r3 8006d0c: d2f6 bcs.n 8006cfc /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; 8006d0e: 68fb ldr r3, [r7, #12] 8006d10: 685a ldr r2, [r3, #4] 8006d12: 683b ldr r3, [r7, #0] 8006d14: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; 8006d16: 683b ldr r3, [r7, #0] 8006d18: 685b ldr r3, [r3, #4] 8006d1a: 683a ldr r2, [r7, #0] 8006d1c: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; 8006d1e: 683b ldr r3, [r7, #0] 8006d20: 68fa ldr r2, [r7, #12] 8006d22: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; 8006d24: 68fb ldr r3, [r7, #12] 8006d26: 683a ldr r2, [r7, #0] 8006d28: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; 8006d2a: 683b ldr r3, [r7, #0] 8006d2c: 687a ldr r2, [r7, #4] 8006d2e: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; 8006d30: 687b ldr r3, [r7, #4] 8006d32: 681b ldr r3, [r3, #0] 8006d34: 1c5a adds r2, r3, #1 8006d36: 687b ldr r3, [r7, #4] 8006d38: 601a str r2, [r3, #0] } 8006d3a: bf00 nop 8006d3c: 3714 adds r7, #20 8006d3e: 46bd mov sp, r7 8006d40: f85d 7b04 ldr.w r7, [sp], #4 8006d44: 4770 bx lr 08006d46 : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { 8006d46: b480 push {r7} 8006d48: b085 sub sp, #20 8006d4a: af00 add r7, sp, #0 8006d4c: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; 8006d4e: 687b ldr r3, [r7, #4] 8006d50: 691b ldr r3, [r3, #16] 8006d52: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; 8006d54: 687b ldr r3, [r7, #4] 8006d56: 685b ldr r3, [r3, #4] 8006d58: 687a ldr r2, [r7, #4] 8006d5a: 6892 ldr r2, [r2, #8] 8006d5c: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; 8006d5e: 687b ldr r3, [r7, #4] 8006d60: 689b ldr r3, [r3, #8] 8006d62: 687a ldr r2, [r7, #4] 8006d64: 6852 ldr r2, [r2, #4] 8006d66: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) 8006d68: 68fb ldr r3, [r7, #12] 8006d6a: 685b ldr r3, [r3, #4] 8006d6c: 687a ldr r2, [r7, #4] 8006d6e: 429a cmp r2, r3 8006d70: d103 bne.n 8006d7a { pxList->pxIndex = pxItemToRemove->pxPrevious; 8006d72: 687b ldr r3, [r7, #4] 8006d74: 689a ldr r2, [r3, #8] 8006d76: 68fb ldr r3, [r7, #12] 8006d78: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; 8006d7a: 687b ldr r3, [r7, #4] 8006d7c: 2200 movs r2, #0 8006d7e: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; 8006d80: 68fb ldr r3, [r7, #12] 8006d82: 681b ldr r3, [r3, #0] 8006d84: 1e5a subs r2, r3, #1 8006d86: 68fb ldr r3, [r7, #12] 8006d88: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; 8006d8a: 68fb ldr r3, [r7, #12] 8006d8c: 681b ldr r3, [r3, #0] } 8006d8e: 4618 mov r0, r3 8006d90: 3714 adds r7, #20 8006d92: 46bd mov sp, r7 8006d94: f85d 7b04 ldr.w r7, [sp], #4 8006d98: 4770 bx lr ... 08006d9c : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { 8006d9c: b580 push {r7, lr} 8006d9e: b08e sub sp, #56 @ 0x38 8006da0: af00 add r7, sp, #0 8006da2: 60f8 str r0, [r7, #12] 8006da4: 60b9 str r1, [r7, #8] 8006da6: 607a str r2, [r7, #4] 8006da8: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; 8006daa: 2300 movs r3, #0 8006dac: 637b str r3, [r7, #52] @ 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; 8006dae: 68fb ldr r3, [r7, #12] 8006db0: 633b str r3, [r7, #48] @ 0x30 configASSERT( pxQueue ); 8006db2: 6b3b ldr r3, [r7, #48] @ 0x30 8006db4: 2b00 cmp r3, #0 8006db6: d10b bne.n 8006dd0 portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile 8006db8: f04f 0350 mov.w r3, #80 @ 0x50 8006dbc: f383 8811 msr BASEPRI, r3 8006dc0: f3bf 8f6f isb sy 8006dc4: f3bf 8f4f dsb sy 8006dc8: 62bb str r3, [r7, #40] @ 0x28 " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } 8006dca: bf00 nop 8006dcc: bf00 nop 8006dce: e7fd b.n 8006dcc configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8006dd0: 68bb ldr r3, [r7, #8] 8006dd2: 2b00 cmp r3, #0 8006dd4: d103 bne.n 8006dde 8006dd6: 6b3b ldr r3, [r7, #48] @ 0x30 8006dd8: 6c1b ldr r3, [r3, #64] @ 0x40 8006dda: 2b00 cmp r3, #0 8006ddc: d101 bne.n 8006de2 8006dde: 2301 movs r3, #1 8006de0: e000 b.n 8006de4 8006de2: 2300 movs r3, #0 8006de4: 2b00 cmp r3, #0 8006de6: d10b bne.n 8006e00 __asm volatile 8006de8: f04f 0350 mov.w r3, #80 @ 0x50 8006dec: f383 8811 msr BASEPRI, r3 8006df0: f3bf 8f6f isb sy 8006df4: f3bf 8f4f dsb sy 8006df8: 627b str r3, [r7, #36] @ 0x24 } 8006dfa: bf00 nop 8006dfc: bf00 nop 8006dfe: e7fd b.n 8006dfc configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8006e00: 683b ldr r3, [r7, #0] 8006e02: 2b02 cmp r3, #2 8006e04: d103 bne.n 8006e0e 8006e06: 6b3b ldr r3, [r7, #48] @ 0x30 8006e08: 6bdb ldr r3, [r3, #60] @ 0x3c 8006e0a: 2b01 cmp r3, #1 8006e0c: d101 bne.n 8006e12 8006e0e: 2301 movs r3, #1 8006e10: e000 b.n 8006e14 8006e12: 2300 movs r3, #0 8006e14: 2b00 cmp r3, #0 8006e16: d10b bne.n 8006e30 __asm volatile 8006e18: f04f 0350 mov.w r3, #80 @ 0x50 8006e1c: f383 8811 msr BASEPRI, r3 8006e20: f3bf 8f6f isb sy 8006e24: f3bf 8f4f dsb sy 8006e28: 623b str r3, [r7, #32] } 8006e2a: bf00 nop 8006e2c: bf00 nop 8006e2e: e7fd b.n 8006e2c #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); 8006e30: f000 fd7e bl 8007930 8006e34: 4603 mov r3, r0 8006e36: 2b00 cmp r3, #0 8006e38: d102 bne.n 8006e40 8006e3a: 687b ldr r3, [r7, #4] 8006e3c: 2b00 cmp r3, #0 8006e3e: d101 bne.n 8006e44 8006e40: 2301 movs r3, #1 8006e42: e000 b.n 8006e46 8006e44: 2300 movs r3, #0 8006e46: 2b00 cmp r3, #0 8006e48: d10b bne.n 8006e62 __asm volatile 8006e4a: f04f 0350 mov.w r3, #80 @ 0x50 8006e4e: f383 8811 msr BASEPRI, r3 8006e52: f3bf 8f6f isb sy 8006e56: f3bf 8f4f dsb sy 8006e5a: 61fb str r3, [r7, #28] } 8006e5c: bf00 nop 8006e5e: bf00 nop 8006e60: e7fd b.n 8006e5e /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); 8006e62: f000 fe89 bl 8007b78 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8006e66: 6b3b ldr r3, [r7, #48] @ 0x30 8006e68: 6b9a ldr r2, [r3, #56] @ 0x38 8006e6a: 6b3b ldr r3, [r7, #48] @ 0x30 8006e6c: 6bdb ldr r3, [r3, #60] @ 0x3c 8006e6e: 429a cmp r2, r3 8006e70: d302 bcc.n 8006e78 8006e72: 683b ldr r3, [r7, #0] 8006e74: 2b02 cmp r3, #2 8006e76: d129 bne.n 8006ecc } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8006e78: 683a ldr r2, [r7, #0] 8006e7a: 68b9 ldr r1, [r7, #8] 8006e7c: 6b38 ldr r0, [r7, #48] @ 0x30 8006e7e: f000 f96b bl 8007158 8006e82: 62f8 str r0, [r7, #44] @ 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8006e84: 6b3b ldr r3, [r7, #48] @ 0x30 8006e86: 6a5b ldr r3, [r3, #36] @ 0x24 8006e88: 2b00 cmp r3, #0 8006e8a: d010 beq.n 8006eae { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 8006e8c: 6b3b ldr r3, [r7, #48] @ 0x30 8006e8e: 3324 adds r3, #36 @ 0x24 8006e90: 4618 mov r0, r3 8006e92: f000 fc43 bl 800771c 8006e96: 4603 mov r3, r0 8006e98: 2b00 cmp r3, #0 8006e9a: d013 beq.n 8006ec4 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); 8006e9c: 4b3f ldr r3, [pc, #252] @ (8006f9c ) 8006e9e: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006ea2: 601a str r2, [r3, #0] 8006ea4: f3bf 8f4f dsb sy 8006ea8: f3bf 8f6f isb sy 8006eac: e00a b.n 8006ec4 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) 8006eae: 6afb ldr r3, [r7, #44] @ 0x2c 8006eb0: 2b00 cmp r3, #0 8006eb2: d007 beq.n 8006ec4 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); 8006eb4: 4b39 ldr r3, [pc, #228] @ (8006f9c ) 8006eb6: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006eba: 601a str r2, [r3, #0] 8006ebc: f3bf 8f4f dsb sy 8006ec0: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); 8006ec4: f000 fe8a bl 8007bdc return pdPASS; 8006ec8: 2301 movs r3, #1 8006eca: e063 b.n 8006f94 } else { if( xTicksToWait == ( TickType_t ) 0 ) 8006ecc: 687b ldr r3, [r7, #4] 8006ece: 2b00 cmp r3, #0 8006ed0: d103 bne.n 8006eda { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); 8006ed2: f000 fe83 bl 8007bdc /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8006ed6: 2300 movs r3, #0 8006ed8: e05c b.n 8006f94 } else if( xEntryTimeSet == pdFALSE ) 8006eda: 6b7b ldr r3, [r7, #52] @ 0x34 8006edc: 2b00 cmp r3, #0 8006ede: d106 bne.n 8006eee { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); 8006ee0: f107 0314 add.w r3, r7, #20 8006ee4: 4618 mov r0, r3 8006ee6: f000 fc7d bl 80077e4 xEntryTimeSet = pdTRUE; 8006eea: 2301 movs r3, #1 8006eec: 637b str r3, [r7, #52] @ 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); 8006eee: f000 fe75 bl 8007bdc /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); 8006ef2: f000 fa05 bl 8007300 prvLockQueue( pxQueue ); 8006ef6: f000 fe3f bl 8007b78 8006efa: 6b3b ldr r3, [r7, #48] @ 0x30 8006efc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8006f00: b25b sxtb r3, r3 8006f02: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006f06: d103 bne.n 8006f10 8006f08: 6b3b ldr r3, [r7, #48] @ 0x30 8006f0a: 2200 movs r2, #0 8006f0c: f883 2044 strb.w r2, [r3, #68] @ 0x44 8006f10: 6b3b ldr r3, [r7, #48] @ 0x30 8006f12: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8006f16: b25b sxtb r3, r3 8006f18: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8006f1c: d103 bne.n 8006f26 8006f1e: 6b3b ldr r3, [r7, #48] @ 0x30 8006f20: 2200 movs r2, #0 8006f22: f883 2045 strb.w r2, [r3, #69] @ 0x45 8006f26: f000 fe59 bl 8007bdc /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) 8006f2a: 1d3a adds r2, r7, #4 8006f2c: f107 0314 add.w r3, r7, #20 8006f30: 4611 mov r1, r2 8006f32: 4618 mov r0, r3 8006f34: f000 fc6c bl 8007810 8006f38: 4603 mov r3, r0 8006f3a: 2b00 cmp r3, #0 8006f3c: d124 bne.n 8006f88 { if( prvIsQueueFull( pxQueue ) != pdFALSE ) 8006f3e: 6b38 ldr r0, [r7, #48] @ 0x30 8006f40: f000 f9c6 bl 80072d0 8006f44: 4603 mov r3, r0 8006f46: 2b00 cmp r3, #0 8006f48: d018 beq.n 8006f7c { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); 8006f4a: 6b3b ldr r3, [r7, #48] @ 0x30 8006f4c: 3310 adds r3, #16 8006f4e: 687a ldr r2, [r7, #4] 8006f50: 4611 mov r1, r2 8006f52: 4618 mov r0, r3 8006f54: f000 fbbc bl 80076d0 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); 8006f58: 6b38 ldr r0, [r7, #48] @ 0x30 8006f5a: f000 f967 bl 800722c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) 8006f5e: f000 f9dd bl 800731c 8006f62: 4603 mov r3, r0 8006f64: 2b00 cmp r3, #0 8006f66: f47f af7c bne.w 8006e62 { portYIELD_WITHIN_API(); 8006f6a: 4b0c ldr r3, [pc, #48] @ (8006f9c ) 8006f6c: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8006f70: 601a str r2, [r3, #0] 8006f72: f3bf 8f4f dsb sy 8006f76: f3bf 8f6f isb sy 8006f7a: e772 b.n 8006e62 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); 8006f7c: 6b38 ldr r0, [r7, #48] @ 0x30 8006f7e: f000 f955 bl 800722c ( void ) xTaskResumeAll(); 8006f82: f000 f9cb bl 800731c 8006f86: e76c b.n 8006e62 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); 8006f88: 6b38 ldr r0, [r7, #48] @ 0x30 8006f8a: f000 f94f bl 800722c ( void ) xTaskResumeAll(); 8006f8e: f000 f9c5 bl 800731c traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; 8006f92: 2300 movs r3, #0 } } /*lint -restore */ } 8006f94: 4618 mov r0, r3 8006f96: 3738 adds r7, #56 @ 0x38 8006f98: 46bd mov sp, r7 8006f9a: bd80 pop {r7, pc} 8006f9c: e000ed04 .word 0xe000ed04 08006fa0 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { 8006fa0: b580 push {r7, lr} 8006fa2: b090 sub sp, #64 @ 0x40 8006fa4: af00 add r7, sp, #0 8006fa6: 60f8 str r0, [r7, #12] 8006fa8: 60b9 str r1, [r7, #8] 8006faa: 607a str r2, [r7, #4] 8006fac: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; 8006fae: 68fb ldr r3, [r7, #12] 8006fb0: 63bb str r3, [r7, #56] @ 0x38 configASSERT( pxQueue ); 8006fb2: 6bbb ldr r3, [r7, #56] @ 0x38 8006fb4: 2b00 cmp r3, #0 8006fb6: d10b bne.n 8006fd0 __asm volatile 8006fb8: f04f 0350 mov.w r3, #80 @ 0x50 8006fbc: f383 8811 msr BASEPRI, r3 8006fc0: f3bf 8f6f isb sy 8006fc4: f3bf 8f4f dsb sy 8006fc8: 62bb str r3, [r7, #40] @ 0x28 } 8006fca: bf00 nop 8006fcc: bf00 nop 8006fce: e7fd b.n 8006fcc configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); 8006fd0: 68bb ldr r3, [r7, #8] 8006fd2: 2b00 cmp r3, #0 8006fd4: d103 bne.n 8006fde 8006fd6: 6bbb ldr r3, [r7, #56] @ 0x38 8006fd8: 6c1b ldr r3, [r3, #64] @ 0x40 8006fda: 2b00 cmp r3, #0 8006fdc: d101 bne.n 8006fe2 8006fde: 2301 movs r3, #1 8006fe0: e000 b.n 8006fe4 8006fe2: 2300 movs r3, #0 8006fe4: 2b00 cmp r3, #0 8006fe6: d10b bne.n 8007000 __asm volatile 8006fe8: f04f 0350 mov.w r3, #80 @ 0x50 8006fec: f383 8811 msr BASEPRI, r3 8006ff0: f3bf 8f6f isb sy 8006ff4: f3bf 8f4f dsb sy 8006ff8: 627b str r3, [r7, #36] @ 0x24 } 8006ffa: bf00 nop 8006ffc: bf00 nop 8006ffe: e7fd b.n 8006ffc configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); 8007000: 683b ldr r3, [r7, #0] 8007002: 2b02 cmp r3, #2 8007004: d103 bne.n 800700e 8007006: 6bbb ldr r3, [r7, #56] @ 0x38 8007008: 6bdb ldr r3, [r3, #60] @ 0x3c 800700a: 2b01 cmp r3, #1 800700c: d101 bne.n 8007012 800700e: 2301 movs r3, #1 8007010: e000 b.n 8007014 8007012: 2300 movs r3, #0 8007014: 2b00 cmp r3, #0 8007016: d10b bne.n 8007030 __asm volatile 8007018: f04f 0350 mov.w r3, #80 @ 0x50 800701c: f383 8811 msr BASEPRI, r3 8007020: f3bf 8f6f isb sy 8007024: f3bf 8f4f dsb sy 8007028: 623b str r3, [r7, #32] } 800702a: bf00 nop 800702c: bf00 nop 800702e: e7fd b.n 800702c that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); 8007030: f000 fe54 bl 8007cdc portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile 8007034: f3ef 8211 mrs r2, BASEPRI 8007038: f04f 0350 mov.w r3, #80 @ 0x50 800703c: f383 8811 msr BASEPRI, r3 8007040: f3bf 8f6f isb sy 8007044: f3bf 8f4f dsb sy 8007048: 61fa str r2, [r7, #28] 800704a: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; 800704c: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); 800704e: 637b str r3, [r7, #52] @ 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) 8007050: 6bbb ldr r3, [r7, #56] @ 0x38 8007052: 6b9a ldr r2, [r3, #56] @ 0x38 8007054: 6bbb ldr r3, [r7, #56] @ 0x38 8007056: 6bdb ldr r3, [r3, #60] @ 0x3c 8007058: 429a cmp r2, r3 800705a: d302 bcc.n 8007062 800705c: 683b ldr r3, [r7, #0] 800705e: 2b02 cmp r3, #2 8007060: d12f bne.n 80070c2 { const int8_t cTxLock = pxQueue->cTxLock; 8007062: 6bbb ldr r3, [r7, #56] @ 0x38 8007064: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 8007068: f887 3033 strb.w r3, [r7, #51] @ 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; 800706c: 6bbb ldr r3, [r7, #56] @ 0x38 800706e: 6b9b ldr r3, [r3, #56] @ 0x38 8007070: 62fb str r3, [r7, #44] @ 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); 8007072: 683a ldr r2, [r7, #0] 8007074: 68b9 ldr r1, [r7, #8] 8007076: 6bb8 ldr r0, [r7, #56] @ 0x38 8007078: f000 f86e bl 8007158 /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) 800707c: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33 8007080: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8007084: d112 bne.n 80070ac } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8007086: 6bbb ldr r3, [r7, #56] @ 0x38 8007088: 6a5b ldr r3, [r3, #36] @ 0x24 800708a: 2b00 cmp r3, #0 800708c: d016 beq.n 80070bc { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800708e: 6bbb ldr r3, [r7, #56] @ 0x38 8007090: 3324 adds r3, #36 @ 0x24 8007092: 4618 mov r0, r3 8007094: f000 fb42 bl 800771c 8007098: 4603 mov r3, r0 800709a: 2b00 cmp r3, #0 800709c: d00e beq.n 80070bc { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) 800709e: 687b ldr r3, [r7, #4] 80070a0: 2b00 cmp r3, #0 80070a2: d00b beq.n 80070bc { *pxHigherPriorityTaskWoken = pdTRUE; 80070a4: 687b ldr r3, [r7, #4] 80070a6: 2201 movs r2, #1 80070a8: 601a str r2, [r3, #0] 80070aa: e007 b.n 80070bc } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); 80070ac: f897 3033 ldrb.w r3, [r7, #51] @ 0x33 80070b0: 3301 adds r3, #1 80070b2: b2db uxtb r3, r3 80070b4: b25a sxtb r2, r3 80070b6: 6bbb ldr r3, [r7, #56] @ 0x38 80070b8: f883 2045 strb.w r2, [r3, #69] @ 0x45 } xReturn = pdPASS; 80070bc: 2301 movs r3, #1 80070be: 63fb str r3, [r7, #60] @ 0x3c { 80070c0: e001 b.n 80070c6 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; 80070c2: 2300 movs r3, #0 80070c4: 63fb str r3, [r7, #60] @ 0x3c 80070c6: 6b7b ldr r3, [r7, #52] @ 0x34 80070c8: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile 80070ca: 697b ldr r3, [r7, #20] 80070cc: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } 80070d0: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; 80070d2: 6bfb ldr r3, [r7, #60] @ 0x3c } 80070d4: 4618 mov r0, r3 80070d6: 3740 adds r7, #64 @ 0x40 80070d8: 46bd mov sp, r7 80070da: bd80 pop {r7, pc} 080070dc : return xReturn; } /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) { 80070dc: b580 push {r7, lr} 80070de: b084 sub sp, #16 80070e0: af00 add r7, sp, #0 80070e2: 6078 str r0, [r7, #4] UBaseType_t uxReturn; configASSERT( xQueue ); 80070e4: 687b ldr r3, [r7, #4] 80070e6: 2b00 cmp r3, #0 80070e8: d10b bne.n 8007102 __asm volatile 80070ea: f04f 0350 mov.w r3, #80 @ 0x50 80070ee: f383 8811 msr BASEPRI, r3 80070f2: f3bf 8f6f isb sy 80070f6: f3bf 8f4f dsb sy 80070fa: 60bb str r3, [r7, #8] } 80070fc: bf00 nop 80070fe: bf00 nop 8007100: e7fd b.n 80070fe taskENTER_CRITICAL(); 8007102: f000 fd39 bl 8007b78 { uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; 8007106: 687b ldr r3, [r7, #4] 8007108: 6b9b ldr r3, [r3, #56] @ 0x38 800710a: 60fb str r3, [r7, #12] } taskEXIT_CRITICAL(); 800710c: f000 fd66 bl 8007bdc return uxReturn; 8007110: 68fb ldr r3, [r7, #12] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 8007112: 4618 mov r0, r3 8007114: 3710 adds r7, #16 8007116: 46bd mov sp, r7 8007118: bd80 pop {r7, pc} 0800711a : return uxReturn; } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ /*-----------------------------------------------------------*/ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) { 800711a: b480 push {r7} 800711c: b087 sub sp, #28 800711e: af00 add r7, sp, #0 8007120: 6078 str r0, [r7, #4] UBaseType_t uxReturn; Queue_t * const pxQueue = xQueue; 8007122: 687b ldr r3, [r7, #4] 8007124: 617b str r3, [r7, #20] configASSERT( pxQueue ); 8007126: 697b ldr r3, [r7, #20] 8007128: 2b00 cmp r3, #0 800712a: d10b bne.n 8007144 __asm volatile 800712c: f04f 0350 mov.w r3, #80 @ 0x50 8007130: f383 8811 msr BASEPRI, r3 8007134: f3bf 8f6f isb sy 8007138: f3bf 8f4f dsb sy 800713c: 60fb str r3, [r7, #12] } 800713e: bf00 nop 8007140: bf00 nop 8007142: e7fd b.n 8007140 uxReturn = pxQueue->uxMessagesWaiting; 8007144: 697b ldr r3, [r7, #20] 8007146: 6b9b ldr r3, [r3, #56] @ 0x38 8007148: 613b str r3, [r7, #16] return uxReturn; 800714a: 693b ldr r3, [r7, #16] } /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ 800714c: 4618 mov r0, r3 800714e: 371c adds r7, #28 8007150: 46bd mov sp, r7 8007152: f85d 7b04 ldr.w r7, [sp], #4 8007156: 4770 bx lr 08007158 : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { 8007158: b580 push {r7, lr} 800715a: b086 sub sp, #24 800715c: af00 add r7, sp, #0 800715e: 60f8 str r0, [r7, #12] 8007160: 60b9 str r1, [r7, #8] 8007162: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; 8007164: 2300 movs r3, #0 8007166: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; 8007168: 68fb ldr r3, [r7, #12] 800716a: 6b9b ldr r3, [r3, #56] @ 0x38 800716c: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) 800716e: 68fb ldr r3, [r7, #12] 8007170: 6c1b ldr r3, [r3, #64] @ 0x40 8007172: 2b00 cmp r3, #0 8007174: d10d bne.n 8007192 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) 8007176: 68fb ldr r3, [r7, #12] 8007178: 681b ldr r3, [r3, #0] 800717a: 2b00 cmp r3, #0 800717c: d14d bne.n 800721a { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); 800717e: 68fb ldr r3, [r7, #12] 8007180: 689b ldr r3, [r3, #8] 8007182: 4618 mov r0, r3 8007184: f000 fbf2 bl 800796c 8007188: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; 800718a: 68fb ldr r3, [r7, #12] 800718c: 2200 movs r2, #0 800718e: 609a str r2, [r3, #8] 8007190: e043 b.n 800721a mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) 8007192: 687b ldr r3, [r7, #4] 8007194: 2b00 cmp r3, #0 8007196: d119 bne.n 80071cc { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ 8007198: 68fb ldr r3, [r7, #12] 800719a: 6858 ldr r0, [r3, #4] 800719c: 68fb ldr r3, [r7, #12] 800719e: 6c1b ldr r3, [r3, #64] @ 0x40 80071a0: 461a mov r2, r3 80071a2: 68b9 ldr r1, [r7, #8] 80071a4: f000 fea8 bl 8007ef8 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ 80071a8: 68fb ldr r3, [r7, #12] 80071aa: 685a ldr r2, [r3, #4] 80071ac: 68fb ldr r3, [r7, #12] 80071ae: 6c1b ldr r3, [r3, #64] @ 0x40 80071b0: 441a add r2, r3 80071b2: 68fb ldr r3, [r7, #12] 80071b4: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80071b6: 68fb ldr r3, [r7, #12] 80071b8: 685a ldr r2, [r3, #4] 80071ba: 68fb ldr r3, [r7, #12] 80071bc: 689b ldr r3, [r3, #8] 80071be: 429a cmp r2, r3 80071c0: d32b bcc.n 800721a { pxQueue->pcWriteTo = pxQueue->pcHead; 80071c2: 68fb ldr r3, [r7, #12] 80071c4: 681a ldr r2, [r3, #0] 80071c6: 68fb ldr r3, [r7, #12] 80071c8: 605a str r2, [r3, #4] 80071ca: e026 b.n 800721a mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ 80071cc: 68fb ldr r3, [r7, #12] 80071ce: 68d8 ldr r0, [r3, #12] 80071d0: 68fb ldr r3, [r7, #12] 80071d2: 6c1b ldr r3, [r3, #64] @ 0x40 80071d4: 461a mov r2, r3 80071d6: 68b9 ldr r1, [r7, #8] 80071d8: f000 fe8e bl 8007ef8 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; 80071dc: 68fb ldr r3, [r7, #12] 80071de: 68da ldr r2, [r3, #12] 80071e0: 68fb ldr r3, [r7, #12] 80071e2: 6c1b ldr r3, [r3, #64] @ 0x40 80071e4: 425b negs r3, r3 80071e6: 441a add r2, r3 80071e8: 68fb ldr r3, [r7, #12] 80071ea: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ 80071ec: 68fb ldr r3, [r7, #12] 80071ee: 68da ldr r2, [r3, #12] 80071f0: 68fb ldr r3, [r7, #12] 80071f2: 681b ldr r3, [r3, #0] 80071f4: 429a cmp r2, r3 80071f6: d207 bcs.n 8007208 { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); 80071f8: 68fb ldr r3, [r7, #12] 80071fa: 689a ldr r2, [r3, #8] 80071fc: 68fb ldr r3, [r7, #12] 80071fe: 6c1b ldr r3, [r3, #64] @ 0x40 8007200: 425b negs r3, r3 8007202: 441a add r2, r3 8007204: 68fb ldr r3, [r7, #12] 8007206: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) 8007208: 687b ldr r3, [r7, #4] 800720a: 2b02 cmp r3, #2 800720c: d105 bne.n 800721a { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) 800720e: 693b ldr r3, [r7, #16] 8007210: 2b00 cmp r3, #0 8007212: d002 beq.n 800721a { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; 8007214: 693b ldr r3, [r7, #16] 8007216: 3b01 subs r3, #1 8007218: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; 800721a: 693b ldr r3, [r7, #16] 800721c: 1c5a adds r2, r3, #1 800721e: 68fb ldr r3, [r7, #12] 8007220: 639a str r2, [r3, #56] @ 0x38 return xReturn; 8007222: 697b ldr r3, [r7, #20] } 8007224: 4618 mov r0, r3 8007226: 3718 adds r7, #24 8007228: 46bd mov sp, r7 800722a: bd80 pop {r7, pc} 0800722c : } } /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { 800722c: b580 push {r7, lr} 800722e: b084 sub sp, #16 8007230: af00 add r7, sp, #0 8007232: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); 8007234: f000 fca0 bl 8007b78 { int8_t cTxLock = pxQueue->cTxLock; 8007238: 687b ldr r3, [r7, #4] 800723a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45 800723e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) 8007240: e011 b.n 8007266 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) 8007242: 687b ldr r3, [r7, #4] 8007244: 6a5b ldr r3, [r3, #36] @ 0x24 8007246: 2b00 cmp r3, #0 8007248: d012 beq.n 8007270 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) 800724a: 687b ldr r3, [r7, #4] 800724c: 3324 adds r3, #36 @ 0x24 800724e: 4618 mov r0, r3 8007250: f000 fa64 bl 800771c 8007254: 4603 mov r3, r0 8007256: 2b00 cmp r3, #0 8007258: d001 beq.n 800725e { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); 800725a: f000 fb3d bl 80078d8 break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; 800725e: 7bfb ldrb r3, [r7, #15] 8007260: 3b01 subs r3, #1 8007262: b2db uxtb r3, r3 8007264: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) 8007266: f997 300f ldrsb.w r3, [r7, #15] 800726a: 2b00 cmp r3, #0 800726c: dce9 bgt.n 8007242 800726e: e000 b.n 8007272 break; 8007270: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; 8007272: 687b ldr r3, [r7, #4] 8007274: 22ff movs r2, #255 @ 0xff 8007276: f883 2045 strb.w r2, [r3, #69] @ 0x45 } taskEXIT_CRITICAL(); 800727a: f000 fcaf bl 8007bdc /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); 800727e: f000 fc7b bl 8007b78 { int8_t cRxLock = pxQueue->cRxLock; 8007282: 687b ldr r3, [r7, #4] 8007284: f893 3044 ldrb.w r3, [r3, #68] @ 0x44 8007288: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 800728a: e011 b.n 80072b0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) 800728c: 687b ldr r3, [r7, #4] 800728e: 691b ldr r3, [r3, #16] 8007290: 2b00 cmp r3, #0 8007292: d012 beq.n 80072ba { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) 8007294: 687b ldr r3, [r7, #4] 8007296: 3310 adds r3, #16 8007298: 4618 mov r0, r3 800729a: f000 fa3f bl 800771c 800729e: 4603 mov r3, r0 80072a0: 2b00 cmp r3, #0 80072a2: d001 beq.n 80072a8 { vTaskMissedYield(); 80072a4: f000 fb18 bl 80078d8 else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; 80072a8: 7bbb ldrb r3, [r7, #14] 80072aa: 3b01 subs r3, #1 80072ac: b2db uxtb r3, r3 80072ae: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) 80072b0: f997 300e ldrsb.w r3, [r7, #14] 80072b4: 2b00 cmp r3, #0 80072b6: dce9 bgt.n 800728c 80072b8: e000 b.n 80072bc } else { break; 80072ba: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; 80072bc: 687b ldr r3, [r7, #4] 80072be: 22ff movs r2, #255 @ 0xff 80072c0: f883 2044 strb.w r2, [r3, #68] @ 0x44 } taskEXIT_CRITICAL(); 80072c4: f000 fc8a bl 8007bdc } 80072c8: bf00 nop 80072ca: 3710 adds r7, #16 80072cc: 46bd mov sp, r7 80072ce: bd80 pop {r7, pc} 080072d0 : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { 80072d0: b580 push {r7, lr} 80072d2: b084 sub sp, #16 80072d4: af00 add r7, sp, #0 80072d6: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); 80072d8: f000 fc4e bl 8007b78 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) 80072dc: 687b ldr r3, [r7, #4] 80072de: 6b9a ldr r2, [r3, #56] @ 0x38 80072e0: 687b ldr r3, [r7, #4] 80072e2: 6bdb ldr r3, [r3, #60] @ 0x3c 80072e4: 429a cmp r2, r3 80072e6: d102 bne.n 80072ee { xReturn = pdTRUE; 80072e8: 2301 movs r3, #1 80072ea: 60fb str r3, [r7, #12] 80072ec: e001 b.n 80072f2 } else { xReturn = pdFALSE; 80072ee: 2300 movs r3, #0 80072f0: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); 80072f2: f000 fc73 bl 8007bdc return xReturn; 80072f6: 68fb ldr r3, [r7, #12] } 80072f8: 4618 mov r0, r3 80072fa: 3710 adds r7, #16 80072fc: 46bd mov sp, r7 80072fe: bd80 pop {r7, pc} 08007300 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { 8007300: b480 push {r7} 8007302: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; 8007304: 4b04 ldr r3, [pc, #16] @ (8007318 ) 8007306: 681b ldr r3, [r3, #0] 8007308: 3301 adds r3, #1 800730a: 4a03 ldr r2, [pc, #12] @ (8007318 ) 800730c: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } 800730e: bf00 nop 8007310: 46bd mov sp, r7 8007312: f85d 7b04 ldr.w r7, [sp], #4 8007316: 4770 bx lr 8007318: 200003bc .word 0x200003bc 0800731c : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { 800731c: b580 push {r7, lr} 800731e: b084 sub sp, #16 8007320: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; 8007322: 2300 movs r3, #0 8007324: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; 8007326: 2300 movs r3, #0 8007328: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); 800732a: 4b42 ldr r3, [pc, #264] @ (8007434 ) 800732c: 681b ldr r3, [r3, #0] 800732e: 2b00 cmp r3, #0 8007330: d10b bne.n 800734a __asm volatile 8007332: f04f 0350 mov.w r3, #80 @ 0x50 8007336: f383 8811 msr BASEPRI, r3 800733a: f3bf 8f6f isb sy 800733e: f3bf 8f4f dsb sy 8007342: 603b str r3, [r7, #0] } 8007344: bf00 nop 8007346: bf00 nop 8007348: e7fd b.n 8007346 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); 800734a: f000 fc15 bl 8007b78 { --uxSchedulerSuspended; 800734e: 4b39 ldr r3, [pc, #228] @ (8007434 ) 8007350: 681b ldr r3, [r3, #0] 8007352: 3b01 subs r3, #1 8007354: 4a37 ldr r2, [pc, #220] @ (8007434 ) 8007356: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8007358: 4b36 ldr r3, [pc, #216] @ (8007434 ) 800735a: 681b ldr r3, [r3, #0] 800735c: 2b00 cmp r3, #0 800735e: d161 bne.n 8007424 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) 8007360: 4b35 ldr r3, [pc, #212] @ (8007438 ) 8007362: 681b ldr r3, [r3, #0] 8007364: 2b00 cmp r3, #0 8007366: d05d beq.n 8007424 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 8007368: e02e b.n 80073c8 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800736a: 4b34 ldr r3, [pc, #208] @ (800743c ) 800736c: 68db ldr r3, [r3, #12] 800736e: 68db ldr r3, [r3, #12] 8007370: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8007372: 68fb ldr r3, [r7, #12] 8007374: 3318 adds r3, #24 8007376: 4618 mov r0, r3 8007378: f7ff fce5 bl 8006d46 ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 800737c: 68fb ldr r3, [r7, #12] 800737e: 3304 adds r3, #4 8007380: 4618 mov r0, r3 8007382: f7ff fce0 bl 8006d46 prvAddTaskToReadyList( pxTCB ); 8007386: 68fb ldr r3, [r7, #12] 8007388: 6adb ldr r3, [r3, #44] @ 0x2c 800738a: 2201 movs r2, #1 800738c: 409a lsls r2, r3 800738e: 4b2c ldr r3, [pc, #176] @ (8007440 ) 8007390: 681b ldr r3, [r3, #0] 8007392: 4313 orrs r3, r2 8007394: 4a2a ldr r2, [pc, #168] @ (8007440 ) 8007396: 6013 str r3, [r2, #0] 8007398: 68fb ldr r3, [r7, #12] 800739a: 6ada ldr r2, [r3, #44] @ 0x2c 800739c: 4613 mov r3, r2 800739e: 009b lsls r3, r3, #2 80073a0: 4413 add r3, r2 80073a2: 009b lsls r3, r3, #2 80073a4: 4a27 ldr r2, [pc, #156] @ (8007444 ) 80073a6: 441a add r2, r3 80073a8: 68fb ldr r3, [r7, #12] 80073aa: 3304 adds r3, #4 80073ac: 4619 mov r1, r3 80073ae: 4610 mov r0, r2 80073b0: f7ff fc6c bl 8006c8c /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 80073b4: 68fb ldr r3, [r7, #12] 80073b6: 6ada ldr r2, [r3, #44] @ 0x2c 80073b8: 4b23 ldr r3, [pc, #140] @ (8007448 ) 80073ba: 681b ldr r3, [r3, #0] 80073bc: 6adb ldr r3, [r3, #44] @ 0x2c 80073be: 429a cmp r2, r3 80073c0: d302 bcc.n 80073c8 { xYieldPending = pdTRUE; 80073c2: 4b22 ldr r3, [pc, #136] @ (800744c ) 80073c4: 2201 movs r2, #1 80073c6: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) 80073c8: 4b1c ldr r3, [pc, #112] @ (800743c ) 80073ca: 681b ldr r3, [r3, #0] 80073cc: 2b00 cmp r3, #0 80073ce: d1cc bne.n 800736a { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) 80073d0: 68fb ldr r3, [r7, #12] 80073d2: 2b00 cmp r3, #0 80073d4: d001 beq.n 80073da which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); 80073d6: f000 fa8b bl 80078f0 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ 80073da: 4b1d ldr r3, [pc, #116] @ (8007450 ) 80073dc: 681b ldr r3, [r3, #0] 80073de: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) 80073e0: 687b ldr r3, [r7, #4] 80073e2: 2b00 cmp r3, #0 80073e4: d010 beq.n 8007408 { do { if( xTaskIncrementTick() != pdFALSE ) 80073e6: f000 f837 bl 8007458 80073ea: 4603 mov r3, r0 80073ec: 2b00 cmp r3, #0 80073ee: d002 beq.n 80073f6 { xYieldPending = pdTRUE; 80073f0: 4b16 ldr r3, [pc, #88] @ (800744c ) 80073f2: 2201 movs r2, #1 80073f4: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; 80073f6: 687b ldr r3, [r7, #4] 80073f8: 3b01 subs r3, #1 80073fa: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); 80073fc: 687b ldr r3, [r7, #4] 80073fe: 2b00 cmp r3, #0 8007400: d1f1 bne.n 80073e6 xPendedTicks = 0; 8007402: 4b13 ldr r3, [pc, #76] @ (8007450 ) 8007404: 2200 movs r2, #0 8007406: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) 8007408: 4b10 ldr r3, [pc, #64] @ (800744c ) 800740a: 681b ldr r3, [r3, #0] 800740c: 2b00 cmp r3, #0 800740e: d009 beq.n 8007424 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; 8007410: 2301 movs r3, #1 8007412: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); 8007414: 4b0f ldr r3, [pc, #60] @ (8007454 ) 8007416: f04f 5280 mov.w r2, #268435456 @ 0x10000000 800741a: 601a str r2, [r3, #0] 800741c: f3bf 8f4f dsb sy 8007420: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); 8007424: f000 fbda bl 8007bdc return xAlreadyYielded; 8007428: 68bb ldr r3, [r7, #8] } 800742a: 4618 mov r0, r3 800742c: 3710 adds r7, #16 800742e: 46bd mov sp, r7 8007430: bd80 pop {r7, pc} 8007432: bf00 nop 8007434: 200003bc .word 0x200003bc 8007438: 2000039c .word 0x2000039c 800743c: 20000374 .word 0x20000374 8007440: 200003a4 .word 0x200003a4 8007444: 200002e0 .word 0x200002e0 8007448: 200002dc .word 0x200002dc 800744c: 200003b0 .word 0x200003b0 8007450: 200003ac .word 0x200003ac 8007454: e000ed04 .word 0xe000ed04 08007458 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { 8007458: b580 push {r7, lr} 800745a: b086 sub sp, #24 800745c: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; 800745e: 2300 movs r3, #0 8007460: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8007462: 4b4f ldr r3, [pc, #316] @ (80075a0 ) 8007464: 681b ldr r3, [r3, #0] 8007466: 2b00 cmp r3, #0 8007468: f040 808f bne.w 800758a { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; 800746c: 4b4d ldr r3, [pc, #308] @ (80075a4 ) 800746e: 681b ldr r3, [r3, #0] 8007470: 3301 adds r3, #1 8007472: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; 8007474: 4a4b ldr r2, [pc, #300] @ (80075a4 ) 8007476: 693b ldr r3, [r7, #16] 8007478: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ 800747a: 693b ldr r3, [r7, #16] 800747c: 2b00 cmp r3, #0 800747e: d121 bne.n 80074c4 { taskSWITCH_DELAYED_LISTS(); 8007480: 4b49 ldr r3, [pc, #292] @ (80075a8 ) 8007482: 681b ldr r3, [r3, #0] 8007484: 681b ldr r3, [r3, #0] 8007486: 2b00 cmp r3, #0 8007488: d00b beq.n 80074a2 __asm volatile 800748a: f04f 0350 mov.w r3, #80 @ 0x50 800748e: f383 8811 msr BASEPRI, r3 8007492: f3bf 8f6f isb sy 8007496: f3bf 8f4f dsb sy 800749a: 603b str r3, [r7, #0] } 800749c: bf00 nop 800749e: bf00 nop 80074a0: e7fd b.n 800749e 80074a2: 4b41 ldr r3, [pc, #260] @ (80075a8 ) 80074a4: 681b ldr r3, [r3, #0] 80074a6: 60fb str r3, [r7, #12] 80074a8: 4b40 ldr r3, [pc, #256] @ (80075ac ) 80074aa: 681b ldr r3, [r3, #0] 80074ac: 4a3e ldr r2, [pc, #248] @ (80075a8 ) 80074ae: 6013 str r3, [r2, #0] 80074b0: 4a3e ldr r2, [pc, #248] @ (80075ac ) 80074b2: 68fb ldr r3, [r7, #12] 80074b4: 6013 str r3, [r2, #0] 80074b6: 4b3e ldr r3, [pc, #248] @ (80075b0 ) 80074b8: 681b ldr r3, [r3, #0] 80074ba: 3301 adds r3, #1 80074bc: 4a3c ldr r2, [pc, #240] @ (80075b0 ) 80074be: 6013 str r3, [r2, #0] 80074c0: f000 fa16 bl 80078f0 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) 80074c4: 4b3b ldr r3, [pc, #236] @ (80075b4 ) 80074c6: 681b ldr r3, [r3, #0] 80074c8: 693a ldr r2, [r7, #16] 80074ca: 429a cmp r2, r3 80074cc: d348 bcc.n 8007560 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80074ce: 4b36 ldr r3, [pc, #216] @ (80075a8 ) 80074d0: 681b ldr r3, [r3, #0] 80074d2: 681b ldr r3, [r3, #0] 80074d4: 2b00 cmp r3, #0 80074d6: d104 bne.n 80074e2 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 80074d8: 4b36 ldr r3, [pc, #216] @ (80075b4 ) 80074da: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 80074de: 601a str r2, [r3, #0] break; 80074e0: e03e b.n 8007560 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 80074e2: 4b31 ldr r3, [pc, #196] @ (80075a8 ) 80074e4: 681b ldr r3, [r3, #0] 80074e6: 68db ldr r3, [r3, #12] 80074e8: 68db ldr r3, [r3, #12] 80074ea: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); 80074ec: 68bb ldr r3, [r7, #8] 80074ee: 685b ldr r3, [r3, #4] 80074f0: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) 80074f2: 693a ldr r2, [r7, #16] 80074f4: 687b ldr r3, [r7, #4] 80074f6: 429a cmp r2, r3 80074f8: d203 bcs.n 8007502 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; 80074fa: 4a2e ldr r2, [pc, #184] @ (80075b4 ) 80074fc: 687b ldr r3, [r7, #4] 80074fe: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ 8007500: e02e b.n 8007560 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); 8007502: 68bb ldr r3, [r7, #8] 8007504: 3304 adds r3, #4 8007506: 4618 mov r0, r3 8007508: f7ff fc1d bl 8006d46 /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) 800750c: 68bb ldr r3, [r7, #8] 800750e: 6a9b ldr r3, [r3, #40] @ 0x28 8007510: 2b00 cmp r3, #0 8007512: d004 beq.n 800751e { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); 8007514: 68bb ldr r3, [r7, #8] 8007516: 3318 adds r3, #24 8007518: 4618 mov r0, r3 800751a: f7ff fc14 bl 8006d46 mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); 800751e: 68bb ldr r3, [r7, #8] 8007520: 6adb ldr r3, [r3, #44] @ 0x2c 8007522: 2201 movs r2, #1 8007524: 409a lsls r2, r3 8007526: 4b24 ldr r3, [pc, #144] @ (80075b8 ) 8007528: 681b ldr r3, [r3, #0] 800752a: 4313 orrs r3, r2 800752c: 4a22 ldr r2, [pc, #136] @ (80075b8 ) 800752e: 6013 str r3, [r2, #0] 8007530: 68bb ldr r3, [r7, #8] 8007532: 6ada ldr r2, [r3, #44] @ 0x2c 8007534: 4613 mov r3, r2 8007536: 009b lsls r3, r3, #2 8007538: 4413 add r3, r2 800753a: 009b lsls r3, r3, #2 800753c: 4a1f ldr r2, [pc, #124] @ (80075bc ) 800753e: 441a add r2, r3 8007540: 68bb ldr r3, [r7, #8] 8007542: 3304 adds r3, #4 8007544: 4619 mov r1, r3 8007546: 4610 mov r0, r2 8007548: f7ff fba0 bl 8006c8c { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) 800754c: 68bb ldr r3, [r7, #8] 800754e: 6ada ldr r2, [r3, #44] @ 0x2c 8007550: 4b1b ldr r3, [pc, #108] @ (80075c0 ) 8007552: 681b ldr r3, [r3, #0] 8007554: 6adb ldr r3, [r3, #44] @ 0x2c 8007556: 429a cmp r2, r3 8007558: d3b9 bcc.n 80074ce { xSwitchRequired = pdTRUE; 800755a: 2301 movs r3, #1 800755c: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 800755e: e7b6 b.n 80074ce /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) 8007560: 4b17 ldr r3, [pc, #92] @ (80075c0 ) 8007562: 681b ldr r3, [r3, #0] 8007564: 6ada ldr r2, [r3, #44] @ 0x2c 8007566: 4915 ldr r1, [pc, #84] @ (80075bc ) 8007568: 4613 mov r3, r2 800756a: 009b lsls r3, r3, #2 800756c: 4413 add r3, r2 800756e: 009b lsls r3, r3, #2 8007570: 440b add r3, r1 8007572: 681b ldr r3, [r3, #0] 8007574: 2b01 cmp r3, #1 8007576: d901 bls.n 800757c { xSwitchRequired = pdTRUE; 8007578: 2301 movs r3, #1 800757a: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) 800757c: 4b11 ldr r3, [pc, #68] @ (80075c4 ) 800757e: 681b ldr r3, [r3, #0] 8007580: 2b00 cmp r3, #0 8007582: d007 beq.n 8007594 { xSwitchRequired = pdTRUE; 8007584: 2301 movs r3, #1 8007586: 617b str r3, [r7, #20] 8007588: e004 b.n 8007594 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; 800758a: 4b0f ldr r3, [pc, #60] @ (80075c8 ) 800758c: 681b ldr r3, [r3, #0] 800758e: 3301 adds r3, #1 8007590: 4a0d ldr r2, [pc, #52] @ (80075c8 ) 8007592: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; 8007594: 697b ldr r3, [r7, #20] } 8007596: 4618 mov r0, r3 8007598: 3718 adds r7, #24 800759a: 46bd mov sp, r7 800759c: bd80 pop {r7, pc} 800759e: bf00 nop 80075a0: 200003bc .word 0x200003bc 80075a4: 200003a0 .word 0x200003a0 80075a8: 2000036c .word 0x2000036c 80075ac: 20000370 .word 0x20000370 80075b0: 200003b4 .word 0x200003b4 80075b4: 200003b8 .word 0x200003b8 80075b8: 200003a4 .word 0x200003a4 80075bc: 200002e0 .word 0x200002e0 80075c0: 200002dc .word 0x200002dc 80075c4: 200003b0 .word 0x200003b0 80075c8: 200003ac .word 0x200003ac 080075cc : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { 80075cc: b580 push {r7, lr} 80075ce: b088 sub sp, #32 80075d0: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) 80075d2: 4b3a ldr r3, [pc, #232] @ (80076bc ) 80075d4: 681b ldr r3, [r3, #0] 80075d6: 2b00 cmp r3, #0 80075d8: d003 beq.n 80075e2 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; 80075da: 4b39 ldr r3, [pc, #228] @ (80076c0 ) 80075dc: 2201 movs r2, #1 80075de: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } 80075e0: e067 b.n 80076b2 xYieldPending = pdFALSE; 80075e2: 4b37 ldr r3, [pc, #220] @ (80076c0 ) 80075e4: 2200 movs r2, #0 80075e6: 601a str r2, [r3, #0] taskCHECK_FOR_STACK_OVERFLOW(); 80075e8: 4b36 ldr r3, [pc, #216] @ (80076c4 ) 80075ea: 681b ldr r3, [r3, #0] 80075ec: 6b1b ldr r3, [r3, #48] @ 0x30 80075ee: 61fb str r3, [r7, #28] 80075f0: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5 80075f4: 61bb str r3, [r7, #24] 80075f6: 69fb ldr r3, [r7, #28] 80075f8: 681b ldr r3, [r3, #0] 80075fa: 69ba ldr r2, [r7, #24] 80075fc: 429a cmp r2, r3 80075fe: d111 bne.n 8007624 8007600: 69fb ldr r3, [r7, #28] 8007602: 3304 adds r3, #4 8007604: 681b ldr r3, [r3, #0] 8007606: 69ba ldr r2, [r7, #24] 8007608: 429a cmp r2, r3 800760a: d10b bne.n 8007624 800760c: 69fb ldr r3, [r7, #28] 800760e: 3308 adds r3, #8 8007610: 681b ldr r3, [r3, #0] 8007612: 69ba ldr r2, [r7, #24] 8007614: 429a cmp r2, r3 8007616: d105 bne.n 8007624 8007618: 69fb ldr r3, [r7, #28] 800761a: 330c adds r3, #12 800761c: 681b ldr r3, [r3, #0] 800761e: 69ba ldr r2, [r7, #24] 8007620: 429a cmp r2, r3 8007622: d008 beq.n 8007636 8007624: 4b27 ldr r3, [pc, #156] @ (80076c4 ) 8007626: 681a ldr r2, [r3, #0] 8007628: 4b26 ldr r3, [pc, #152] @ (80076c4 ) 800762a: 681b ldr r3, [r3, #0] 800762c: 3334 adds r3, #52 @ 0x34 800762e: 4619 mov r1, r3 8007630: 4610 mov r0, r2 8007632: f7f8 ffaf bl 8000594 taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8007636: 4b24 ldr r3, [pc, #144] @ (80076c8 ) 8007638: 681b ldr r3, [r3, #0] 800763a: 60fb str r3, [r7, #12] __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" ); 800763c: 68fb ldr r3, [r7, #12] 800763e: fab3 f383 clz r3, r3 8007642: 72fb strb r3, [r7, #11] return ucReturn; 8007644: 7afb ldrb r3, [r7, #11] 8007646: f1c3 031f rsb r3, r3, #31 800764a: 617b str r3, [r7, #20] 800764c: 491f ldr r1, [pc, #124] @ (80076cc ) 800764e: 697a ldr r2, [r7, #20] 8007650: 4613 mov r3, r2 8007652: 009b lsls r3, r3, #2 8007654: 4413 add r3, r2 8007656: 009b lsls r3, r3, #2 8007658: 440b add r3, r1 800765a: 681b ldr r3, [r3, #0] 800765c: 2b00 cmp r3, #0 800765e: d10b bne.n 8007678 __asm volatile 8007660: f04f 0350 mov.w r3, #80 @ 0x50 8007664: f383 8811 msr BASEPRI, r3 8007668: f3bf 8f6f isb sy 800766c: f3bf 8f4f dsb sy 8007670: 607b str r3, [r7, #4] } 8007672: bf00 nop 8007674: bf00 nop 8007676: e7fd b.n 8007674 8007678: 697a ldr r2, [r7, #20] 800767a: 4613 mov r3, r2 800767c: 009b lsls r3, r3, #2 800767e: 4413 add r3, r2 8007680: 009b lsls r3, r3, #2 8007682: 4a12 ldr r2, [pc, #72] @ (80076cc ) 8007684: 4413 add r3, r2 8007686: 613b str r3, [r7, #16] 8007688: 693b ldr r3, [r7, #16] 800768a: 685b ldr r3, [r3, #4] 800768c: 685a ldr r2, [r3, #4] 800768e: 693b ldr r3, [r7, #16] 8007690: 605a str r2, [r3, #4] 8007692: 693b ldr r3, [r7, #16] 8007694: 685a ldr r2, [r3, #4] 8007696: 693b ldr r3, [r7, #16] 8007698: 3308 adds r3, #8 800769a: 429a cmp r2, r3 800769c: d104 bne.n 80076a8 800769e: 693b ldr r3, [r7, #16] 80076a0: 685b ldr r3, [r3, #4] 80076a2: 685a ldr r2, [r3, #4] 80076a4: 693b ldr r3, [r7, #16] 80076a6: 605a str r2, [r3, #4] 80076a8: 693b ldr r3, [r7, #16] 80076aa: 685b ldr r3, [r3, #4] 80076ac: 68db ldr r3, [r3, #12] 80076ae: 4a05 ldr r2, [pc, #20] @ (80076c4 ) 80076b0: 6013 str r3, [r2, #0] } 80076b2: bf00 nop 80076b4: 3720 adds r7, #32 80076b6: 46bd mov sp, r7 80076b8: bd80 pop {r7, pc} 80076ba: bf00 nop 80076bc: 200003bc .word 0x200003bc 80076c0: 200003b0 .word 0x200003b0 80076c4: 200002dc .word 0x200002dc 80076c8: 200003a4 .word 0x200003a4 80076cc: 200002e0 .word 0x200002e0 080076d0 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { 80076d0: b580 push {r7, lr} 80076d2: b084 sub sp, #16 80076d4: af00 add r7, sp, #0 80076d6: 6078 str r0, [r7, #4] 80076d8: 6039 str r1, [r7, #0] configASSERT( pxEventList ); 80076da: 687b ldr r3, [r7, #4] 80076dc: 2b00 cmp r3, #0 80076de: d10b bne.n 80076f8 __asm volatile 80076e0: f04f 0350 mov.w r3, #80 @ 0x50 80076e4: f383 8811 msr BASEPRI, r3 80076e8: f3bf 8f6f isb sy 80076ec: f3bf 8f4f dsb sy 80076f0: 60fb str r3, [r7, #12] } 80076f2: bf00 nop 80076f4: bf00 nop 80076f6: e7fd b.n 80076f4 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); 80076f8: 4b07 ldr r3, [pc, #28] @ (8007718 ) 80076fa: 681b ldr r3, [r3, #0] 80076fc: 3318 adds r3, #24 80076fe: 4619 mov r1, r3 8007700: 6878 ldr r0, [r7, #4] 8007702: f7ff fae7 bl 8006cd4 prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); 8007706: 2101 movs r1, #1 8007708: 6838 ldr r0, [r7, #0] 800770a: f000 f9b7 bl 8007a7c } 800770e: bf00 nop 8007710: 3710 adds r7, #16 8007712: 46bd mov sp, r7 8007714: bd80 pop {r7, pc} 8007716: bf00 nop 8007718: 200002dc .word 0x200002dc 0800771c : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { 800771c: b580 push {r7, lr} 800771e: b086 sub sp, #24 8007720: af00 add r7, sp, #0 8007722: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 8007724: 687b ldr r3, [r7, #4] 8007726: 68db ldr r3, [r3, #12] 8007728: 68db ldr r3, [r3, #12] 800772a: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); 800772c: 693b ldr r3, [r7, #16] 800772e: 2b00 cmp r3, #0 8007730: d10b bne.n 800774a __asm volatile 8007732: f04f 0350 mov.w r3, #80 @ 0x50 8007736: f383 8811 msr BASEPRI, r3 800773a: f3bf 8f6f isb sy 800773e: f3bf 8f4f dsb sy 8007742: 60fb str r3, [r7, #12] } 8007744: bf00 nop 8007746: bf00 nop 8007748: e7fd b.n 8007746 ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); 800774a: 693b ldr r3, [r7, #16] 800774c: 3318 adds r3, #24 800774e: 4618 mov r0, r3 8007750: f7ff faf9 bl 8006d46 if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8007754: 4b1d ldr r3, [pc, #116] @ (80077cc ) 8007756: 681b ldr r3, [r3, #0] 8007758: 2b00 cmp r3, #0 800775a: d11c bne.n 8007796 { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); 800775c: 693b ldr r3, [r7, #16] 800775e: 3304 adds r3, #4 8007760: 4618 mov r0, r3 8007762: f7ff faf0 bl 8006d46 prvAddTaskToReadyList( pxUnblockedTCB ); 8007766: 693b ldr r3, [r7, #16] 8007768: 6adb ldr r3, [r3, #44] @ 0x2c 800776a: 2201 movs r2, #1 800776c: 409a lsls r2, r3 800776e: 4b18 ldr r3, [pc, #96] @ (80077d0 ) 8007770: 681b ldr r3, [r3, #0] 8007772: 4313 orrs r3, r2 8007774: 4a16 ldr r2, [pc, #88] @ (80077d0 ) 8007776: 6013 str r3, [r2, #0] 8007778: 693b ldr r3, [r7, #16] 800777a: 6ada ldr r2, [r3, #44] @ 0x2c 800777c: 4613 mov r3, r2 800777e: 009b lsls r3, r3, #2 8007780: 4413 add r3, r2 8007782: 009b lsls r3, r3, #2 8007784: 4a13 ldr r2, [pc, #76] @ (80077d4 ) 8007786: 441a add r2, r3 8007788: 693b ldr r3, [r7, #16] 800778a: 3304 adds r3, #4 800778c: 4619 mov r1, r3 800778e: 4610 mov r0, r2 8007790: f7ff fa7c bl 8006c8c 8007794: e005 b.n 80077a2 } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); 8007796: 693b ldr r3, [r7, #16] 8007798: 3318 adds r3, #24 800779a: 4619 mov r1, r3 800779c: 480e ldr r0, [pc, #56] @ (80077d8 ) 800779e: f7ff fa75 bl 8006c8c } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) 80077a2: 693b ldr r3, [r7, #16] 80077a4: 6ada ldr r2, [r3, #44] @ 0x2c 80077a6: 4b0d ldr r3, [pc, #52] @ (80077dc ) 80077a8: 681b ldr r3, [r3, #0] 80077aa: 6adb ldr r3, [r3, #44] @ 0x2c 80077ac: 429a cmp r2, r3 80077ae: d905 bls.n 80077bc { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; 80077b0: 2301 movs r3, #1 80077b2: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; 80077b4: 4b0a ldr r3, [pc, #40] @ (80077e0 ) 80077b6: 2201 movs r2, #1 80077b8: 601a str r2, [r3, #0] 80077ba: e001 b.n 80077c0 } else { xReturn = pdFALSE; 80077bc: 2300 movs r3, #0 80077be: 617b str r3, [r7, #20] } return xReturn; 80077c0: 697b ldr r3, [r7, #20] } 80077c2: 4618 mov r0, r3 80077c4: 3718 adds r7, #24 80077c6: 46bd mov sp, r7 80077c8: bd80 pop {r7, pc} 80077ca: bf00 nop 80077cc: 200003bc .word 0x200003bc 80077d0: 200003a4 .word 0x200003a4 80077d4: 200002e0 .word 0x200002e0 80077d8: 20000374 .word 0x20000374 80077dc: 200002dc .word 0x200002dc 80077e0: 200003b0 .word 0x200003b0 080077e4 : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { 80077e4: b480 push {r7} 80077e6: b083 sub sp, #12 80077e8: af00 add r7, sp, #0 80077ea: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; 80077ec: 4b06 ldr r3, [pc, #24] @ (8007808 ) 80077ee: 681a ldr r2, [r3, #0] 80077f0: 687b ldr r3, [r7, #4] 80077f2: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; 80077f4: 4b05 ldr r3, [pc, #20] @ (800780c ) 80077f6: 681a ldr r2, [r3, #0] 80077f8: 687b ldr r3, [r7, #4] 80077fa: 605a str r2, [r3, #4] } 80077fc: bf00 nop 80077fe: 370c adds r7, #12 8007800: 46bd mov sp, r7 8007802: f85d 7b04 ldr.w r7, [sp], #4 8007806: 4770 bx lr 8007808: 200003b4 .word 0x200003b4 800780c: 200003a0 .word 0x200003a0 08007810 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { 8007810: b580 push {r7, lr} 8007812: b088 sub sp, #32 8007814: af00 add r7, sp, #0 8007816: 6078 str r0, [r7, #4] 8007818: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); 800781a: 687b ldr r3, [r7, #4] 800781c: 2b00 cmp r3, #0 800781e: d10b bne.n 8007838 __asm volatile 8007820: f04f 0350 mov.w r3, #80 @ 0x50 8007824: f383 8811 msr BASEPRI, r3 8007828: f3bf 8f6f isb sy 800782c: f3bf 8f4f dsb sy 8007830: 613b str r3, [r7, #16] } 8007832: bf00 nop 8007834: bf00 nop 8007836: e7fd b.n 8007834 configASSERT( pxTicksToWait ); 8007838: 683b ldr r3, [r7, #0] 800783a: 2b00 cmp r3, #0 800783c: d10b bne.n 8007856 __asm volatile 800783e: f04f 0350 mov.w r3, #80 @ 0x50 8007842: f383 8811 msr BASEPRI, r3 8007846: f3bf 8f6f isb sy 800784a: f3bf 8f4f dsb sy 800784e: 60fb str r3, [r7, #12] } 8007850: bf00 nop 8007852: bf00 nop 8007854: e7fd b.n 8007852 taskENTER_CRITICAL(); 8007856: f000 f98f bl 8007b78 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; 800785a: 4b1d ldr r3, [pc, #116] @ (80078d0 ) 800785c: 681b ldr r3, [r3, #0] 800785e: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; 8007860: 687b ldr r3, [r7, #4] 8007862: 685b ldr r3, [r3, #4] 8007864: 69ba ldr r2, [r7, #24] 8007866: 1ad3 subs r3, r2, r3 8007868: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) 800786a: 683b ldr r3, [r7, #0] 800786c: 681b ldr r3, [r3, #0] 800786e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8007872: d102 bne.n 800787a { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; 8007874: 2300 movs r3, #0 8007876: 61fb str r3, [r7, #28] 8007878: e023 b.n 80078c2 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ 800787a: 687b ldr r3, [r7, #4] 800787c: 681a ldr r2, [r3, #0] 800787e: 4b15 ldr r3, [pc, #84] @ (80078d4 ) 8007880: 681b ldr r3, [r3, #0] 8007882: 429a cmp r2, r3 8007884: d007 beq.n 8007896 8007886: 687b ldr r3, [r7, #4] 8007888: 685b ldr r3, [r3, #4] 800788a: 69ba ldr r2, [r7, #24] 800788c: 429a cmp r2, r3 800788e: d302 bcc.n 8007896 /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; 8007890: 2301 movs r3, #1 8007892: 61fb str r3, [r7, #28] 8007894: e015 b.n 80078c2 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ 8007896: 683b ldr r3, [r7, #0] 8007898: 681b ldr r3, [r3, #0] 800789a: 697a ldr r2, [r7, #20] 800789c: 429a cmp r2, r3 800789e: d20b bcs.n 80078b8 { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; 80078a0: 683b ldr r3, [r7, #0] 80078a2: 681a ldr r2, [r3, #0] 80078a4: 697b ldr r3, [r7, #20] 80078a6: 1ad2 subs r2, r2, r3 80078a8: 683b ldr r3, [r7, #0] 80078aa: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); 80078ac: 6878 ldr r0, [r7, #4] 80078ae: f7ff ff99 bl 80077e4 xReturn = pdFALSE; 80078b2: 2300 movs r3, #0 80078b4: 61fb str r3, [r7, #28] 80078b6: e004 b.n 80078c2 } else { *pxTicksToWait = 0; 80078b8: 683b ldr r3, [r7, #0] 80078ba: 2200 movs r2, #0 80078bc: 601a str r2, [r3, #0] xReturn = pdTRUE; 80078be: 2301 movs r3, #1 80078c0: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); 80078c2: f000 f98b bl 8007bdc return xReturn; 80078c6: 69fb ldr r3, [r7, #28] } 80078c8: 4618 mov r0, r3 80078ca: 3720 adds r7, #32 80078cc: 46bd mov sp, r7 80078ce: bd80 pop {r7, pc} 80078d0: 200003a0 .word 0x200003a0 80078d4: 200003b4 .word 0x200003b4 080078d8 : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { 80078d8: b480 push {r7} 80078da: af00 add r7, sp, #0 xYieldPending = pdTRUE; 80078dc: 4b03 ldr r3, [pc, #12] @ (80078ec ) 80078de: 2201 movs r2, #1 80078e0: 601a str r2, [r3, #0] } 80078e2: bf00 nop 80078e4: 46bd mov sp, r7 80078e6: f85d 7b04 ldr.w r7, [sp], #4 80078ea: 4770 bx lr 80078ec: 200003b0 .word 0x200003b0 080078f0 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { 80078f0: b480 push {r7} 80078f2: b083 sub sp, #12 80078f4: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) 80078f6: 4b0c ldr r3, [pc, #48] @ (8007928 ) 80078f8: 681b ldr r3, [r3, #0] 80078fa: 681b ldr r3, [r3, #0] 80078fc: 2b00 cmp r3, #0 80078fe: d104 bne.n 800790a { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; 8007900: 4b0a ldr r3, [pc, #40] @ (800792c ) 8007902: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff 8007906: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } 8007908: e008 b.n 800791c ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ 800790a: 4b07 ldr r3, [pc, #28] @ (8007928 ) 800790c: 681b ldr r3, [r3, #0] 800790e: 68db ldr r3, [r3, #12] 8007910: 68db ldr r3, [r3, #12] 8007912: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); 8007914: 687b ldr r3, [r7, #4] 8007916: 685b ldr r3, [r3, #4] 8007918: 4a04 ldr r2, [pc, #16] @ (800792c ) 800791a: 6013 str r3, [r2, #0] } 800791c: bf00 nop 800791e: 370c adds r7, #12 8007920: 46bd mov sp, r7 8007922: f85d 7b04 ldr.w r7, [sp], #4 8007926: 4770 bx lr 8007928: 2000036c .word 0x2000036c 800792c: 200003b8 .word 0x200003b8 08007930 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { 8007930: b480 push {r7} 8007932: b083 sub sp, #12 8007934: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) 8007936: 4b0b ldr r3, [pc, #44] @ (8007964 ) 8007938: 681b ldr r3, [r3, #0] 800793a: 2b00 cmp r3, #0 800793c: d102 bne.n 8007944 { xReturn = taskSCHEDULER_NOT_STARTED; 800793e: 2301 movs r3, #1 8007940: 607b str r3, [r7, #4] 8007942: e008 b.n 8007956 } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) 8007944: 4b08 ldr r3, [pc, #32] @ (8007968 ) 8007946: 681b ldr r3, [r3, #0] 8007948: 2b00 cmp r3, #0 800794a: d102 bne.n 8007952 { xReturn = taskSCHEDULER_RUNNING; 800794c: 2302 movs r3, #2 800794e: 607b str r3, [r7, #4] 8007950: e001 b.n 8007956 } else { xReturn = taskSCHEDULER_SUSPENDED; 8007952: 2300 movs r3, #0 8007954: 607b str r3, [r7, #4] } } return xReturn; 8007956: 687b ldr r3, [r7, #4] } 8007958: 4618 mov r0, r3 800795a: 370c adds r7, #12 800795c: 46bd mov sp, r7 800795e: f85d 7b04 ldr.w r7, [sp], #4 8007962: 4770 bx lr 8007964: 200003a8 .word 0x200003a8 8007968: 200003bc .word 0x200003bc 0800796c : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { 800796c: b580 push {r7, lr} 800796e: b086 sub sp, #24 8007970: af00 add r7, sp, #0 8007972: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; 8007974: 687b ldr r3, [r7, #4] 8007976: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; 8007978: 2300 movs r3, #0 800797a: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) 800797c: 687b ldr r3, [r7, #4] 800797e: 2b00 cmp r3, #0 8007980: d070 beq.n 8007a64 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); 8007982: 4b3b ldr r3, [pc, #236] @ (8007a70 ) 8007984: 681b ldr r3, [r3, #0] 8007986: 693a ldr r2, [r7, #16] 8007988: 429a cmp r2, r3 800798a: d00b beq.n 80079a4 __asm volatile 800798c: f04f 0350 mov.w r3, #80 @ 0x50 8007990: f383 8811 msr BASEPRI, r3 8007994: f3bf 8f6f isb sy 8007998: f3bf 8f4f dsb sy 800799c: 60fb str r3, [r7, #12] } 800799e: bf00 nop 80079a0: bf00 nop 80079a2: e7fd b.n 80079a0 configASSERT( pxTCB->uxMutexesHeld ); 80079a4: 693b ldr r3, [r7, #16] 80079a6: 6c9b ldr r3, [r3, #72] @ 0x48 80079a8: 2b00 cmp r3, #0 80079aa: d10b bne.n 80079c4 __asm volatile 80079ac: f04f 0350 mov.w r3, #80 @ 0x50 80079b0: f383 8811 msr BASEPRI, r3 80079b4: f3bf 8f6f isb sy 80079b8: f3bf 8f4f dsb sy 80079bc: 60bb str r3, [r7, #8] } 80079be: bf00 nop 80079c0: bf00 nop 80079c2: e7fd b.n 80079c0 ( pxTCB->uxMutexesHeld )--; 80079c4: 693b ldr r3, [r7, #16] 80079c6: 6c9b ldr r3, [r3, #72] @ 0x48 80079c8: 1e5a subs r2, r3, #1 80079ca: 693b ldr r3, [r7, #16] 80079cc: 649a str r2, [r3, #72] @ 0x48 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) 80079ce: 693b ldr r3, [r7, #16] 80079d0: 6ada ldr r2, [r3, #44] @ 0x2c 80079d2: 693b ldr r3, [r7, #16] 80079d4: 6c5b ldr r3, [r3, #68] @ 0x44 80079d6: 429a cmp r2, r3 80079d8: d044 beq.n 8007a64 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) 80079da: 693b ldr r3, [r7, #16] 80079dc: 6c9b ldr r3, [r3, #72] @ 0x48 80079de: 2b00 cmp r3, #0 80079e0: d140 bne.n 8007a64 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 80079e2: 693b ldr r3, [r7, #16] 80079e4: 3304 adds r3, #4 80079e6: 4618 mov r0, r3 80079e8: f7ff f9ad bl 8006d46 80079ec: 4603 mov r3, r0 80079ee: 2b00 cmp r3, #0 80079f0: d115 bne.n 8007a1e { taskRESET_READY_PRIORITY( pxTCB->uxPriority ); 80079f2: 693b ldr r3, [r7, #16] 80079f4: 6ada ldr r2, [r3, #44] @ 0x2c 80079f6: 491f ldr r1, [pc, #124] @ (8007a74 ) 80079f8: 4613 mov r3, r2 80079fa: 009b lsls r3, r3, #2 80079fc: 4413 add r3, r2 80079fe: 009b lsls r3, r3, #2 8007a00: 440b add r3, r1 8007a02: 681b ldr r3, [r3, #0] 8007a04: 2b00 cmp r3, #0 8007a06: d10a bne.n 8007a1e 8007a08: 693b ldr r3, [r7, #16] 8007a0a: 6adb ldr r3, [r3, #44] @ 0x2c 8007a0c: 2201 movs r2, #1 8007a0e: fa02 f303 lsl.w r3, r2, r3 8007a12: 43da mvns r2, r3 8007a14: 4b18 ldr r3, [pc, #96] @ (8007a78 ) 8007a16: 681b ldr r3, [r3, #0] 8007a18: 4013 ands r3, r2 8007a1a: 4a17 ldr r2, [pc, #92] @ (8007a78 ) 8007a1c: 6013 str r3, [r2, #0] } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; 8007a1e: 693b ldr r3, [r7, #16] 8007a20: 6c5a ldr r2, [r3, #68] @ 0x44 8007a22: 693b ldr r3, [r7, #16] 8007a24: 62da str r2, [r3, #44] @ 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ 8007a26: 693b ldr r3, [r7, #16] 8007a28: 6adb ldr r3, [r3, #44] @ 0x2c 8007a2a: f1c3 0207 rsb r2, r3, #7 8007a2e: 693b ldr r3, [r7, #16] 8007a30: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); 8007a32: 693b ldr r3, [r7, #16] 8007a34: 6adb ldr r3, [r3, #44] @ 0x2c 8007a36: 2201 movs r2, #1 8007a38: 409a lsls r2, r3 8007a3a: 4b0f ldr r3, [pc, #60] @ (8007a78 ) 8007a3c: 681b ldr r3, [r3, #0] 8007a3e: 4313 orrs r3, r2 8007a40: 4a0d ldr r2, [pc, #52] @ (8007a78 ) 8007a42: 6013 str r3, [r2, #0] 8007a44: 693b ldr r3, [r7, #16] 8007a46: 6ada ldr r2, [r3, #44] @ 0x2c 8007a48: 4613 mov r3, r2 8007a4a: 009b lsls r3, r3, #2 8007a4c: 4413 add r3, r2 8007a4e: 009b lsls r3, r3, #2 8007a50: 4a08 ldr r2, [pc, #32] @ (8007a74 ) 8007a52: 441a add r2, r3 8007a54: 693b ldr r3, [r7, #16] 8007a56: 3304 adds r3, #4 8007a58: 4619 mov r1, r3 8007a5a: 4610 mov r0, r2 8007a5c: f7ff f916 bl 8006c8c in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; 8007a60: 2301 movs r3, #1 8007a62: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; 8007a64: 697b ldr r3, [r7, #20] } 8007a66: 4618 mov r0, r3 8007a68: 3718 adds r7, #24 8007a6a: 46bd mov sp, r7 8007a6c: bd80 pop {r7, pc} 8007a6e: bf00 nop 8007a70: 200002dc .word 0x200002dc 8007a74: 200002e0 .word 0x200002e0 8007a78: 200003a4 .word 0x200003a4 08007a7c : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { 8007a7c: b580 push {r7, lr} 8007a7e: b084 sub sp, #16 8007a80: af00 add r7, sp, #0 8007a82: 6078 str r0, [r7, #4] 8007a84: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; 8007a86: 4b29 ldr r3, [pc, #164] @ (8007b2c ) 8007a88: 681b ldr r3, [r3, #0] 8007a8a: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) 8007a8c: 4b28 ldr r3, [pc, #160] @ (8007b30 ) 8007a8e: 681b ldr r3, [r3, #0] 8007a90: 3304 adds r3, #4 8007a92: 4618 mov r0, r3 8007a94: f7ff f957 bl 8006d46 8007a98: 4603 mov r3, r0 8007a9a: 2b00 cmp r3, #0 8007a9c: d10b bne.n 8007ab6 { /* The current task must be in a ready list, so there is no need to check, and the port reset macro can be called directly. */ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ 8007a9e: 4b24 ldr r3, [pc, #144] @ (8007b30 ) 8007aa0: 681b ldr r3, [r3, #0] 8007aa2: 6adb ldr r3, [r3, #44] @ 0x2c 8007aa4: 2201 movs r2, #1 8007aa6: fa02 f303 lsl.w r3, r2, r3 8007aaa: 43da mvns r2, r3 8007aac: 4b21 ldr r3, [pc, #132] @ (8007b34 ) 8007aae: 681b ldr r3, [r3, #0] 8007ab0: 4013 ands r3, r2 8007ab2: 4a20 ldr r2, [pc, #128] @ (8007b34 ) 8007ab4: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) 8007ab6: 687b ldr r3, [r7, #4] 8007ab8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff 8007abc: d10a bne.n 8007ad4 8007abe: 683b ldr r3, [r7, #0] 8007ac0: 2b00 cmp r3, #0 8007ac2: d007 beq.n 8007ad4 { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007ac4: 4b1a ldr r3, [pc, #104] @ (8007b30 ) 8007ac6: 681b ldr r3, [r3, #0] 8007ac8: 3304 adds r3, #4 8007aca: 4619 mov r1, r3 8007acc: 481a ldr r0, [pc, #104] @ (8007b38 ) 8007ace: f7ff f8dd bl 8006c8c /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } 8007ad2: e026 b.n 8007b22 xTimeToWake = xConstTickCount + xTicksToWait; 8007ad4: 68fa ldr r2, [r7, #12] 8007ad6: 687b ldr r3, [r7, #4] 8007ad8: 4413 add r3, r2 8007ada: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); 8007adc: 4b14 ldr r3, [pc, #80] @ (8007b30 ) 8007ade: 681b ldr r3, [r3, #0] 8007ae0: 68ba ldr r2, [r7, #8] 8007ae2: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) 8007ae4: 68ba ldr r2, [r7, #8] 8007ae6: 68fb ldr r3, [r7, #12] 8007ae8: 429a cmp r2, r3 8007aea: d209 bcs.n 8007b00 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007aec: 4b13 ldr r3, [pc, #76] @ (8007b3c ) 8007aee: 681a ldr r2, [r3, #0] 8007af0: 4b0f ldr r3, [pc, #60] @ (8007b30 ) 8007af2: 681b ldr r3, [r3, #0] 8007af4: 3304 adds r3, #4 8007af6: 4619 mov r1, r3 8007af8: 4610 mov r0, r2 8007afa: f7ff f8eb bl 8006cd4 } 8007afe: e010 b.n 8007b22 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); 8007b00: 4b0f ldr r3, [pc, #60] @ (8007b40 ) 8007b02: 681a ldr r2, [r3, #0] 8007b04: 4b0a ldr r3, [pc, #40] @ (8007b30 ) 8007b06: 681b ldr r3, [r3, #0] 8007b08: 3304 adds r3, #4 8007b0a: 4619 mov r1, r3 8007b0c: 4610 mov r0, r2 8007b0e: f7ff f8e1 bl 8006cd4 if( xTimeToWake < xNextTaskUnblockTime ) 8007b12: 4b0c ldr r3, [pc, #48] @ (8007b44 ) 8007b14: 681b ldr r3, [r3, #0] 8007b16: 68ba ldr r2, [r7, #8] 8007b18: 429a cmp r2, r3 8007b1a: d202 bcs.n 8007b22 xNextTaskUnblockTime = xTimeToWake; 8007b1c: 4a09 ldr r2, [pc, #36] @ (8007b44 ) 8007b1e: 68bb ldr r3, [r7, #8] 8007b20: 6013 str r3, [r2, #0] } 8007b22: bf00 nop 8007b24: 3710 adds r7, #16 8007b26: 46bd mov sp, r7 8007b28: bd80 pop {r7, pc} 8007b2a: bf00 nop 8007b2c: 200003a0 .word 0x200003a0 8007b30: 200002dc .word 0x200002dc 8007b34: 200003a4 .word 0x200003a4 8007b38: 20000388 .word 0x20000388 8007b3c: 20000370 .word 0x20000370 8007b40: 2000036c .word 0x2000036c 8007b44: 200003b8 .word 0x200003b8 ... 08007b50 : } /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( 8007b50: 4b07 ldr r3, [pc, #28] @ (8007b70 ) 8007b52: 6819 ldr r1, [r3, #0] 8007b54: 6808 ldr r0, [r1, #0] 8007b56: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007b5a: f380 8809 msr PSP, r0 8007b5e: f3bf 8f6f isb sy 8007b62: f04f 0000 mov.w r0, #0 8007b66: f380 8811 msr BASEPRI, r0 8007b6a: 4770 bx lr 8007b6c: f3af 8000 nop.w 08007b70 : 8007b70: 200002dc .word 0x200002dc " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } 8007b74: bf00 nop 8007b76: bf00 nop 08007b78 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { 8007b78: b480 push {r7} 8007b7a: b083 sub sp, #12 8007b7c: af00 add r7, sp, #0 __asm volatile 8007b7e: f04f 0350 mov.w r3, #80 @ 0x50 8007b82: f383 8811 msr BASEPRI, r3 8007b86: f3bf 8f6f isb sy 8007b8a: f3bf 8f4f dsb sy 8007b8e: 607b str r3, [r7, #4] } 8007b90: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; 8007b92: 4b10 ldr r3, [pc, #64] @ (8007bd4 ) 8007b94: 681b ldr r3, [r3, #0] 8007b96: 3301 adds r3, #1 8007b98: 4a0e ldr r2, [pc, #56] @ (8007bd4 ) 8007b9a: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) 8007b9c: 4b0d ldr r3, [pc, #52] @ (8007bd4 ) 8007b9e: 681b ldr r3, [r3, #0] 8007ba0: 2b01 cmp r3, #1 8007ba2: d110 bne.n 8007bc6 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); 8007ba4: 4b0c ldr r3, [pc, #48] @ (8007bd8 ) 8007ba6: 681b ldr r3, [r3, #0] 8007ba8: b2db uxtb r3, r3 8007baa: 2b00 cmp r3, #0 8007bac: d00b beq.n 8007bc6 __asm volatile 8007bae: f04f 0350 mov.w r3, #80 @ 0x50 8007bb2: f383 8811 msr BASEPRI, r3 8007bb6: f3bf 8f6f isb sy 8007bba: f3bf 8f4f dsb sy 8007bbe: 603b str r3, [r7, #0] } 8007bc0: bf00 nop 8007bc2: bf00 nop 8007bc4: e7fd b.n 8007bc2 } } 8007bc6: bf00 nop 8007bc8: 370c adds r7, #12 8007bca: 46bd mov sp, r7 8007bcc: f85d 7b04 ldr.w r7, [sp], #4 8007bd0: 4770 bx lr 8007bd2: bf00 nop 8007bd4: 2000000c .word 0x2000000c 8007bd8: e000ed04 .word 0xe000ed04 08007bdc : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { 8007bdc: b480 push {r7} 8007bde: b083 sub sp, #12 8007be0: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); 8007be2: 4b12 ldr r3, [pc, #72] @ (8007c2c ) 8007be4: 681b ldr r3, [r3, #0] 8007be6: 2b00 cmp r3, #0 8007be8: d10b bne.n 8007c02 __asm volatile 8007bea: f04f 0350 mov.w r3, #80 @ 0x50 8007bee: f383 8811 msr BASEPRI, r3 8007bf2: f3bf 8f6f isb sy 8007bf6: f3bf 8f4f dsb sy 8007bfa: 607b str r3, [r7, #4] } 8007bfc: bf00 nop 8007bfe: bf00 nop 8007c00: e7fd b.n 8007bfe uxCriticalNesting--; 8007c02: 4b0a ldr r3, [pc, #40] @ (8007c2c ) 8007c04: 681b ldr r3, [r3, #0] 8007c06: 3b01 subs r3, #1 8007c08: 4a08 ldr r2, [pc, #32] @ (8007c2c ) 8007c0a: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) 8007c0c: 4b07 ldr r3, [pc, #28] @ (8007c2c ) 8007c0e: 681b ldr r3, [r3, #0] 8007c10: 2b00 cmp r3, #0 8007c12: d105 bne.n 8007c20 8007c14: 2300 movs r3, #0 8007c16: 603b str r3, [r7, #0] __asm volatile 8007c18: 683b ldr r3, [r7, #0] 8007c1a: f383 8811 msr BASEPRI, r3 } 8007c1e: bf00 nop { portENABLE_INTERRUPTS(); } } 8007c20: bf00 nop 8007c22: 370c adds r7, #12 8007c24: 46bd mov sp, r7 8007c26: f85d 7b04 ldr.w r7, [sp], #4 8007c2a: 4770 bx lr 8007c2c: 2000000c .word 0x2000000c 08007c30 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile 8007c30: f3ef 8009 mrs r0, PSP 8007c34: f3bf 8f6f isb sy 8007c38: 4b15 ldr r3, [pc, #84] @ (8007c90 ) 8007c3a: 681a ldr r2, [r3, #0] 8007c3c: f01e 0f10 tst.w lr, #16 8007c40: bf08 it eq 8007c42: ed20 8a10 vstmdbeq r0!, {s16-s31} 8007c46: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007c4a: 6010 str r0, [r2, #0] 8007c4c: e92d 0009 stmdb sp!, {r0, r3} 8007c50: f04f 0050 mov.w r0, #80 @ 0x50 8007c54: f380 8811 msr BASEPRI, r0 8007c58: f3bf 8f4f dsb sy 8007c5c: f3bf 8f6f isb sy 8007c60: f7ff fcb4 bl 80075cc 8007c64: f04f 0000 mov.w r0, #0 8007c68: f380 8811 msr BASEPRI, r0 8007c6c: bc09 pop {r0, r3} 8007c6e: 6819 ldr r1, [r3, #0] 8007c70: 6808 ldr r0, [r1, #0] 8007c72: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007c76: f01e 0f10 tst.w lr, #16 8007c7a: bf08 it eq 8007c7c: ecb0 8a10 vldmiaeq r0!, {s16-s31} 8007c80: f380 8809 msr PSP, r0 8007c84: f3bf 8f6f isb sy 8007c88: 4770 bx lr 8007c8a: bf00 nop 8007c8c: f3af 8000 nop.w 08007c90 : 8007c90: 200002dc .word 0x200002dc " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } 8007c94: bf00 nop 8007c96: bf00 nop 08007c98 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { 8007c98: b580 push {r7, lr} 8007c9a: b082 sub sp, #8 8007c9c: af00 add r7, sp, #0 __asm volatile 8007c9e: f04f 0350 mov.w r3, #80 @ 0x50 8007ca2: f383 8811 msr BASEPRI, r3 8007ca6: f3bf 8f6f isb sy 8007caa: f3bf 8f4f dsb sy 8007cae: 607b str r3, [r7, #4] } 8007cb0: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) 8007cb2: f7ff fbd1 bl 8007458 8007cb6: 4603 mov r3, r0 8007cb8: 2b00 cmp r3, #0 8007cba: d003 beq.n 8007cc4 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; 8007cbc: 4b06 ldr r3, [pc, #24] @ (8007cd8 ) 8007cbe: f04f 5280 mov.w r2, #268435456 @ 0x10000000 8007cc2: 601a str r2, [r3, #0] 8007cc4: 2300 movs r3, #0 8007cc6: 603b str r3, [r7, #0] __asm volatile 8007cc8: 683b ldr r3, [r7, #0] 8007cca: f383 8811 msr BASEPRI, r3 } 8007cce: bf00 nop } } portENABLE_INTERRUPTS(); } 8007cd0: bf00 nop 8007cd2: 3708 adds r7, #8 8007cd4: 46bd mov sp, r7 8007cd6: bd80 pop {r7, pc} 8007cd8: e000ed04 .word 0xe000ed04 08007cdc : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { 8007cdc: b480 push {r7} 8007cde: b085 sub sp, #20 8007ce0: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); 8007ce2: f3ef 8305 mrs r3, IPSR 8007ce6: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) 8007ce8: 68fb ldr r3, [r7, #12] 8007cea: 2b0f cmp r3, #15 8007cec: d915 bls.n 8007d1a { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; 8007cee: 4a18 ldr r2, [pc, #96] @ (8007d50 ) 8007cf0: 68fb ldr r3, [r7, #12] 8007cf2: 4413 add r3, r2 8007cf4: 781b ldrb r3, [r3, #0] 8007cf6: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); 8007cf8: 4b16 ldr r3, [pc, #88] @ (8007d54 ) 8007cfa: 781b ldrb r3, [r3, #0] 8007cfc: 7afa ldrb r2, [r7, #11] 8007cfe: 429a cmp r2, r3 8007d00: d20b bcs.n 8007d1a __asm volatile 8007d02: f04f 0350 mov.w r3, #80 @ 0x50 8007d06: f383 8811 msr BASEPRI, r3 8007d0a: f3bf 8f6f isb sy 8007d0e: f3bf 8f4f dsb sy 8007d12: 607b str r3, [r7, #4] } 8007d14: bf00 nop 8007d16: bf00 nop 8007d18: e7fd b.n 8007d16 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); 8007d1a: 4b0f ldr r3, [pc, #60] @ (8007d58 ) 8007d1c: 681b ldr r3, [r3, #0] 8007d1e: f403 62e0 and.w r2, r3, #1792 @ 0x700 8007d22: 4b0e ldr r3, [pc, #56] @ (8007d5c ) 8007d24: 681b ldr r3, [r3, #0] 8007d26: 429a cmp r2, r3 8007d28: d90b bls.n 8007d42 __asm volatile 8007d2a: f04f 0350 mov.w r3, #80 @ 0x50 8007d2e: f383 8811 msr BASEPRI, r3 8007d32: f3bf 8f6f isb sy 8007d36: f3bf 8f4f dsb sy 8007d3a: 603b str r3, [r7, #0] } 8007d3c: bf00 nop 8007d3e: bf00 nop 8007d40: e7fd b.n 8007d3e } 8007d42: bf00 nop 8007d44: 3714 adds r7, #20 8007d46: 46bd mov sp, r7 8007d48: f85d 7b04 ldr.w r7, [sp], #4 8007d4c: 4770 bx lr 8007d4e: bf00 nop 8007d50: e000e3f0 .word 0xe000e3f0 8007d54: 200003c0 .word 0x200003c0 8007d58: e000ed0c .word 0xe000ed0c 8007d5c: 200003c4 .word 0x200003c4 08007d60 : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) { 8007d60: b580 push {r7, lr} 8007d62: b082 sub sp, #8 8007d64: af00 add r7, sp, #0 8007d66: 6078 str r0, [r7, #4] USBH_LL_IncTimer(hhcd->pData); 8007d68: 687b ldr r3, [r7, #4] 8007d6a: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007d6e: 4618 mov r0, r3 8007d70: f7fe fe3c bl 80069ec } 8007d74: bf00 nop 8007d76: 3708 adds r7, #8 8007d78: 46bd mov sp, r7 8007d7a: bd80 pop {r7, pc} 08007d7c : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) { 8007d7c: b580 push {r7, lr} 8007d7e: b082 sub sp, #8 8007d80: af00 add r7, sp, #0 8007d82: 6078 str r0, [r7, #4] USBH_LL_Connect(hhcd->pData); 8007d84: 687b ldr r3, [r7, #4] 8007d86: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007d8a: 4618 mov r0, r3 8007d8c: f7fe fe7c bl 8006a88 } 8007d90: bf00 nop 8007d92: 3708 adds r7, #8 8007d94: 46bd mov sp, r7 8007d96: bd80 pop {r7, pc} 08007d98 : * @brief SOF callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) { 8007d98: b580 push {r7, lr} 8007d9a: b082 sub sp, #8 8007d9c: af00 add r7, sp, #0 8007d9e: 6078 str r0, [r7, #4] USBH_LL_Disconnect(hhcd->pData); 8007da0: 687b ldr r3, [r7, #4] 8007da2: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007da6: 4618 mov r0, r3 8007da8: f7fe fe89 bl 8006abe } 8007dac: bf00 nop 8007dae: 3708 adds r7, #8 8007db0: 46bd mov sp, r7 8007db2: bd80 pop {r7, pc} 08007db4 : * @param chnum: channel number * @param urb_state: state * @retval None */ void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) { 8007db4: b580 push {r7, lr} 8007db6: b082 sub sp, #8 8007db8: af00 add r7, sp, #0 8007dba: 6078 str r0, [r7, #4] 8007dbc: 460b mov r3, r1 8007dbe: 70fb strb r3, [r7, #3] 8007dc0: 4613 mov r3, r2 8007dc2: 70bb strb r3, [r7, #2] /* To be used with OS to sync URB state with the global state machine */ #if (USBH_USE_OS == 1) USBH_LL_NotifyURBChange(hhcd->pData); 8007dc4: 687b ldr r3, [r7, #4] 8007dc6: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007dca: 4618 mov r0, r3 8007dcc: f7fe fec8 bl 8006b60 #endif } 8007dd0: bf00 nop 8007dd2: 3708 adds r7, #8 8007dd4: 46bd mov sp, r7 8007dd6: bd80 pop {r7, pc} 08007dd8 : * @brief Port Port Enabled callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) { 8007dd8: b580 push {r7, lr} 8007dda: b082 sub sp, #8 8007ddc: af00 add r7, sp, #0 8007dde: 6078 str r0, [r7, #4] USBH_LL_PortEnabled(hhcd->pData); 8007de0: 687b ldr r3, [r7, #4] 8007de2: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007de6: 4618 mov r0, r3 8007de8: f7fe fe2a bl 8006a40 } 8007dec: bf00 nop 8007dee: 3708 adds r7, #8 8007df0: 46bd mov sp, r7 8007df2: bd80 pop {r7, pc} 08007df4 : * @brief Port Port Disabled callback. * @param hhcd: HCD handle * @retval None */ void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) { 8007df4: b580 push {r7, lr} 8007df6: b082 sub sp, #8 8007df8: af00 add r7, sp, #0 8007dfa: 6078 str r0, [r7, #4] USBH_LL_PortDisabled(hhcd->pData); 8007dfc: 687b ldr r3, [r7, #4] 8007dfe: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc 8007e02: 4618 mov r0, r3 8007e04: f7fe fe2e bl 8006a64 } 8007e08: bf00 nop 8007e0a: 3708 adds r7, #8 8007e0c: 46bd mov sp, r7 8007e0e: bd80 pop {r7, pc} 08007e10 : * @brief Stop the low level portion of the host driver. * @param phost: Host handle * @retval USBH status */ USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost) { 8007e10: b580 push {r7, lr} 8007e12: b084 sub sp, #16 8007e14: af00 add r7, sp, #0 8007e16: 6078 str r0, [r7, #4] HAL_StatusTypeDef hal_status = HAL_OK; 8007e18: 2300 movs r3, #0 8007e1a: 73fb strb r3, [r7, #15] USBH_StatusTypeDef usb_status = USBH_OK; 8007e1c: 2300 movs r3, #0 8007e1e: 73bb strb r3, [r7, #14] hal_status = HAL_HCD_Stop(phost->pData); 8007e20: 687b ldr r3, [r7, #4] 8007e22: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0 8007e26: 4618 mov r0, r3 8007e28: f7fa fa1d bl 8002266 8007e2c: 4603 mov r3, r0 8007e2e: 73fb strb r3, [r7, #15] usb_status = USBH_Get_USB_Status(hal_status); 8007e30: 7bfb ldrb r3, [r7, #15] 8007e32: 4618 mov r0, r3 8007e34: f000 f808 bl 8007e48 8007e38: 4603 mov r3, r0 8007e3a: 73bb strb r3, [r7, #14] return usb_status; 8007e3c: 7bbb ldrb r3, [r7, #14] } 8007e3e: 4618 mov r0, r3 8007e40: 3710 adds r7, #16 8007e42: 46bd mov sp, r7 8007e44: bd80 pop {r7, pc} ... 08007e48 : * @brief Returns the USB status depending on the HAL status: * @param hal_status: HAL status * @retval USB status */ USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status) { 8007e48: b480 push {r7} 8007e4a: b085 sub sp, #20 8007e4c: af00 add r7, sp, #0 8007e4e: 4603 mov r3, r0 8007e50: 71fb strb r3, [r7, #7] USBH_StatusTypeDef usb_status = USBH_OK; 8007e52: 2300 movs r3, #0 8007e54: 73fb strb r3, [r7, #15] switch (hal_status) 8007e56: 79fb ldrb r3, [r7, #7] 8007e58: 2b03 cmp r3, #3 8007e5a: d817 bhi.n 8007e8c 8007e5c: a201 add r2, pc, #4 @ (adr r2, 8007e64 ) 8007e5e: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8007e62: bf00 nop 8007e64: 08007e75 .word 0x08007e75 8007e68: 08007e7b .word 0x08007e7b 8007e6c: 08007e81 .word 0x08007e81 8007e70: 08007e87 .word 0x08007e87 { case HAL_OK : usb_status = USBH_OK; 8007e74: 2300 movs r3, #0 8007e76: 73fb strb r3, [r7, #15] break; 8007e78: e00b b.n 8007e92 case HAL_ERROR : usb_status = USBH_FAIL; 8007e7a: 2302 movs r3, #2 8007e7c: 73fb strb r3, [r7, #15] break; 8007e7e: e008 b.n 8007e92 case HAL_BUSY : usb_status = USBH_BUSY; 8007e80: 2301 movs r3, #1 8007e82: 73fb strb r3, [r7, #15] break; 8007e84: e005 b.n 8007e92 case HAL_TIMEOUT : usb_status = USBH_FAIL; 8007e86: 2302 movs r3, #2 8007e88: 73fb strb r3, [r7, #15] break; 8007e8a: e002 b.n 8007e92 default : usb_status = USBH_FAIL; 8007e8c: 2302 movs r3, #2 8007e8e: 73fb strb r3, [r7, #15] break; 8007e90: bf00 nop } return usb_status; 8007e92: 7bfb ldrb r3, [r7, #15] } 8007e94: 4618 mov r0, r3 8007e96: 3714 adds r7, #20 8007e98: 46bd mov sp, r7 8007e9a: f85d 7b04 ldr.w r7, [sp], #4 8007e9e: 4770 bx lr 08007ea0 : 8007ea0: 4402 add r2, r0 8007ea2: 4603 mov r3, r0 8007ea4: 4293 cmp r3, r2 8007ea6: d100 bne.n 8007eaa 8007ea8: 4770 bx lr 8007eaa: f803 1b01 strb.w r1, [r3], #1 8007eae: e7f9 b.n 8007ea4 08007eb0 <__libc_init_array>: 8007eb0: b570 push {r4, r5, r6, lr} 8007eb2: 4d0d ldr r5, [pc, #52] @ (8007ee8 <__libc_init_array+0x38>) 8007eb4: 4c0d ldr r4, [pc, #52] @ (8007eec <__libc_init_array+0x3c>) 8007eb6: 1b64 subs r4, r4, r5 8007eb8: 10a4 asrs r4, r4, #2 8007eba: 2600 movs r6, #0 8007ebc: 42a6 cmp r6, r4 8007ebe: d109 bne.n 8007ed4 <__libc_init_array+0x24> 8007ec0: 4d0b ldr r5, [pc, #44] @ (8007ef0 <__libc_init_array+0x40>) 8007ec2: 4c0c ldr r4, [pc, #48] @ (8007ef4 <__libc_init_array+0x44>) 8007ec4: f000 f826 bl 8007f14 <_init> 8007ec8: 1b64 subs r4, r4, r5 8007eca: 10a4 asrs r4, r4, #2 8007ecc: 2600 movs r6, #0 8007ece: 42a6 cmp r6, r4 8007ed0: d105 bne.n 8007ede <__libc_init_array+0x2e> 8007ed2: bd70 pop {r4, r5, r6, pc} 8007ed4: f855 3b04 ldr.w r3, [r5], #4 8007ed8: 4798 blx r3 8007eda: 3601 adds r6, #1 8007edc: e7ee b.n 8007ebc <__libc_init_array+0xc> 8007ede: f855 3b04 ldr.w r3, [r5], #4 8007ee2: 4798 blx r3 8007ee4: 3601 adds r6, #1 8007ee6: e7f2 b.n 8007ece <__libc_init_array+0x1e> 8007ee8: 08007f4c .word 0x08007f4c 8007eec: 08007f4c .word 0x08007f4c 8007ef0: 08007f4c .word 0x08007f4c 8007ef4: 08007f50 .word 0x08007f50 08007ef8 : 8007ef8: 440a add r2, r1 8007efa: 4291 cmp r1, r2 8007efc: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff 8007f00: d100 bne.n 8007f04 8007f02: 4770 bx lr 8007f04: b510 push {r4, lr} 8007f06: f811 4b01 ldrb.w r4, [r1], #1 8007f0a: f803 4f01 strb.w r4, [r3, #1]! 8007f0e: 4291 cmp r1, r2 8007f10: d1f9 bne.n 8007f06 8007f12: bd10 pop {r4, pc} 08007f14 <_init>: 8007f14: b5f8 push {r3, r4, r5, r6, r7, lr} 8007f16: bf00 nop 8007f18: bcf8 pop {r3, r4, r5, r6, r7} 8007f1a: bc08 pop {r3} 8007f1c: 469e mov lr, r3 8007f1e: 4770 bx lr 08007f20 <_fini>: 8007f20: b5f8 push {r3, r4, r5, r6, r7, lr} 8007f22: bf00 nop 8007f24: bcf8 pop {r3, r4, r5, r6, r7} 8007f26: bc08 pop {r3} 8007f28: 469e mov lr, r3 8007f2a: 4770 bx lr