35617 lines
1.3 MiB
35617 lines
1.3 MiB
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MyNewProject.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001ac 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 0000cef0 080001b0 080001b0 000011b0 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000084 0800d0a0 0800d0a0 0000e0a0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 0800d124 0800d124 0000f080 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 0800d124 0800d124 0000e124 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 0800d12c 0800d12c 0000f080 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 0800d12c 0800d12c 0000e12c 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 0800d130 0800d130 0000e130 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000080 20000000 0800d134 0000f000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .ccmram 00000000 10000000 10000000 0000f080 2**0
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CONTENTS
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10 .bss 00008f90 20000080 20000080 0000f080 2**2
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ALLOC
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11 ._user_heap_stack 00000600 20009010 20009010 0000f080 2**0
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ALLOC
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12 .ARM.attributes 00000030 00000000 00000000 0000f080 2**0
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CONTENTS, READONLY
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13 .debug_info 00029606 00000000 00000000 0000f0b0 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_abbrev 00005ca1 00000000 00000000 000386b6 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_aranges 000022d8 00000000 00000000 0003e358 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_rnglists 00001afe 00000000 00000000 00040630 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_macro 0002b2dd 00000000 00000000 0004212e 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_line 00029dc1 00000000 00000000 0006d40b 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_str 000f5708 00000000 00000000 000971cc 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .comment 00000043 00000000 00000000 0018c8d4 2**0
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CONTENTS, READONLY
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21 .debug_frame 0000979c 00000000 00000000 0018c918 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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22 .debug_line_str 0000004c 00000000 00000000 001960b4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001b0 <__do_global_dtors_aux>:
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80001b0: b510 push {r4, lr}
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80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>)
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80001b4: 7823 ldrb r3, [r4, #0]
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80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16>
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80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>)
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80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12>
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80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>)
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80001be: f3af 8000 nop.w
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80001c2: 2301 movs r3, #1
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80001c4: 7023 strb r3, [r4, #0]
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80001c6: bd10 pop {r4, pc}
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80001c8: 20000080 .word 0x20000080
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80001cc: 00000000 .word 0x00000000
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80001d0: 0800d088 .word 0x0800d088
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080001d4 <frame_dummy>:
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80001d4: b508 push {r3, lr}
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80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 <frame_dummy+0x10>)
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80001d8: b11b cbz r3, 80001e2 <frame_dummy+0xe>
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80001da: 4903 ldr r1, [pc, #12] @ (80001e8 <frame_dummy+0x14>)
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80001dc: 4803 ldr r0, [pc, #12] @ (80001ec <frame_dummy+0x18>)
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80001de: f3af 8000 nop.w
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80001e2: bd08 pop {r3, pc}
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80001e4: 00000000 .word 0x00000000
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80001e8: 20000084 .word 0x20000084
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80001ec: 0800d088 .word 0x0800d088
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080001f0 <__aeabi_uldivmod>:
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80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18>
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80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18>
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80001f4: 2900 cmp r1, #0
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80001f6: bf08 it eq
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80001f8: 2800 cmpeq r0, #0
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80001fa: bf1c itt ne
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80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000204: f000 b988 b.w 8000518 <__aeabi_idiv0>
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8000208: f1ad 0c08 sub.w ip, sp, #8
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800020c: e96d ce04 strd ip, lr, [sp, #-16]!
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8000210: f000 f806 bl 8000220 <__udivmoddi4>
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8000214: f8dd e004 ldr.w lr, [sp, #4]
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8000218: e9dd 2302 ldrd r2, r3, [sp, #8]
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800021c: b004 add sp, #16
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800021e: 4770 bx lr
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08000220 <__udivmoddi4>:
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8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000224: 9d08 ldr r5, [sp, #32]
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8000226: 468e mov lr, r1
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8000228: 4604 mov r4, r0
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800022a: 4688 mov r8, r1
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800022c: 2b00 cmp r3, #0
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800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6>
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8000230: 428a cmp r2, r1
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8000232: 4617 mov r7, r2
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8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc>
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8000236: fab2 f682 clz r6, r2
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800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30>
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800023c: f1c6 0320 rsb r3, r6, #32
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8000240: fa01 f806 lsl.w r8, r1, r6
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8000244: fa20 f303 lsr.w r3, r0, r3
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8000248: 40b7 lsls r7, r6
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800024a: ea43 0808 orr.w r8, r3, r8
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800024e: 40b4 lsls r4, r6
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8000250: ea4f 4e17 mov.w lr, r7, lsr #16
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8000254: fa1f fc87 uxth.w ip, r7
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8000258: fbb8 f1fe udiv r1, r8, lr
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800025c: 0c23 lsrs r3, r4, #16
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800025e: fb0e 8811 mls r8, lr, r1, r8
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8000262: ea43 4308 orr.w r3, r3, r8, lsl #16
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8000266: fb01 f20c mul.w r2, r1, ip
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800026a: 429a cmp r2, r3
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800026c: d909 bls.n 8000282 <__udivmoddi4+0x62>
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800026e: 18fb adds r3, r7, r3
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8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c>
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8000278: 429a cmp r2, r3
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800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c>
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800027e: 3902 subs r1, #2
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8000280: 443b add r3, r7
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8000282: 1a9a subs r2, r3, r2
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8000284: b2a3 uxth r3, r4
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8000286: fbb2 f0fe udiv r0, r2, lr
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800028a: fb0e 2210 mls r2, lr, r0, r2
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800028e: ea43 4302 orr.w r3, r3, r2, lsl #16
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8000292: fb00 fc0c mul.w ip, r0, ip
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8000296: 459c cmp ip, r3
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8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e>
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800029a: 18fb adds r3, r7, r3
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800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230>
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80002a4: 459c cmp ip, r3
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80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230>
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80002aa: 443b add r3, r7
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80002ac: 3802 subs r0, #2
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80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002b2: eba3 030c sub.w r3, r3, ip
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80002b6: 2100 movs r1, #0
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80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2>
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80002ba: 40f3 lsrs r3, r6
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80002bc: 2200 movs r2, #0
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80002be: e9c5 3200 strd r3, r2, [r5]
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80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002c6: 428b cmp r3, r1
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80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6>
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80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0>
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80002cc: e9c5 0100 strd r0, r1, [r5]
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80002d0: 2100 movs r1, #0
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80002d2: 4608 mov r0, r1
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80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2>
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80002d6: fab3 f183 clz r1, r3
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80002da: 2900 cmp r1, #0
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80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c>
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80002de: 4573 cmp r3, lr
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80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8>
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80002e2: 4282 cmp r2, r0
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80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2>
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80002e8: 1a84 subs r4, r0, r2
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80002ea: eb6e 0203 sbc.w r2, lr, r3
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80002ee: 2001 movs r0, #1
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80002f0: 4690 mov r8, r2
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80002f2: 2d00 cmp r5, #0
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80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2>
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80002f6: e9c5 4800 strd r4, r8, [r5]
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80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2>
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80002fc: 2a00 cmp r2, #0
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80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202>
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8000302: fab2 f682 clz r6, r2
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8000306: 2e00 cmp r6, #0
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8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234>
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800030c: 1a8a subs r2, r1, r2
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800030e: 0c03 lsrs r3, r0, #16
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8000310: ea4f 4e17 mov.w lr, r7, lsr #16
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8000314: b280 uxth r0, r0
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8000316: b2bc uxth r4, r7
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8000318: 2101 movs r1, #1
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800031a: fbb2 fcfe udiv ip, r2, lr
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800031e: fb0e 221c mls r2, lr, ip, r2
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8000322: ea43 4302 orr.w r3, r3, r2, lsl #16
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8000326: fb04 f20c mul.w r2, r4, ip
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800032a: 429a cmp r2, r3
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800032c: d907 bls.n 800033e <__udivmoddi4+0x11e>
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800032e: 18fb adds r3, r7, r3
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8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c>
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8000336: 429a cmp r2, r3
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8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc>
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800033c: 46c4 mov ip, r8
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800033e: 1a9b subs r3, r3, r2
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8000340: fbb3 f2fe udiv r2, r3, lr
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8000344: fb0e 3312 mls r3, lr, r2, r3
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8000348: ea40 4303 orr.w r3, r0, r3, lsl #16
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800034c: fb02 f404 mul.w r4, r2, r4
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8000350: 429c cmp r4, r3
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8000352: d907 bls.n 8000364 <__udivmoddi4+0x144>
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8000354: 18fb adds r3, r7, r3
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8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142>
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800035c: 429c cmp r4, r3
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800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6>
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8000362: 4602 mov r2, r0
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8000364: 1b1b subs r3, r3, r4
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8000366: ea42 400c orr.w r0, r2, ip, lsl #16
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800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98>
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800036c: f1c1 0620 rsb r6, r1, #32
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8000370: 408b lsls r3, r1
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8000372: fa22 f706 lsr.w r7, r2, r6
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8000376: 431f orrs r7, r3
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8000378: fa0e f401 lsl.w r4, lr, r1
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800037c: fa20 f306 lsr.w r3, r0, r6
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8000380: fa2e fe06 lsr.w lr, lr, r6
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8000384: ea4f 4917 mov.w r9, r7, lsr #16
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8000388: 4323 orrs r3, r4
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800038a: fa00 f801 lsl.w r8, r0, r1
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800038e: fa1f fc87 uxth.w ip, r7
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8000392: fbbe f0f9 udiv r0, lr, r9
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8000396: 0c1c lsrs r4, r3, #16
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8000398: fb09 ee10 mls lr, r9, r0, lr
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800039c: ea44 440e orr.w r4, r4, lr, lsl #16
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80003a0: fb00 fe0c mul.w lr, r0, ip
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80003a4: 45a6 cmp lr, r4
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80003a6: fa02 f201 lsl.w r2, r2, r1
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80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0>
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80003ac: 193c adds r4, r7, r4
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80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce>
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80003b6: 45a6 cmp lr, r4
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80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce>
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80003bc: 3802 subs r0, #2
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80003be: 443c add r4, r7
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80003c0: eba4 040e sub.w r4, r4, lr
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80003c4: fa1f fe83 uxth.w lr, r3
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80003c8: fbb4 f3f9 udiv r3, r4, r9
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80003cc: fb09 4413 mls r4, r9, r3, r4
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80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003d4: fb03 fc0c mul.w ip, r3, ip
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80003d8: 45a4 cmp ip, r4
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80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce>
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80003dc: 193c adds r4, r7, r4
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80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca>
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80003e6: 45a4 cmp ip, r4
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80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca>
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80003ea: 3b02 subs r3, #2
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80003ec: 443c add r4, r7
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80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16
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80003f2: eba4 040c sub.w r4, r4, ip
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80003f6: fba0 ec02 umull lr, ip, r0, r2
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80003fa: 4564 cmp r4, ip
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80003fc: 4673 mov r3, lr
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80003fe: 46e1 mov r9, ip
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8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8>
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8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4>
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8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe>
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8000406: ebb8 0203 subs.w r2, r8, r3
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800040a: eb64 0409 sbc.w r4, r4, r9
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800040e: fa04 f606 lsl.w r6, r4, r6
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8000412: fa22 f301 lsr.w r3, r2, r1
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8000416: 431e orrs r6, r3
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8000418: 40cc lsrs r4, r1
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800041a: e9c5 6400 strd r6, r4, [r5]
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800041e: 2100 movs r1, #0
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8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2>
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8000422: fbb1 fcf2 udiv ip, r1, r2
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8000426: 0c01 lsrs r1, r0, #16
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8000428: ea41 410e orr.w r1, r1, lr, lsl #16
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800042c: b280 uxth r0, r0
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800042e: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000432: 463b mov r3, r7
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8000434: 4638 mov r0, r7
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8000436: 463c mov r4, r7
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8000438: 46b8 mov r8, r7
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800043a: 46be mov lr, r7
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800043c: 2620 movs r6, #32
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800043e: fbb1 f1f7 udiv r1, r1, r7
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8000442: eba2 0208 sub.w r2, r2, r8
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8000446: ea41 410c orr.w r1, r1, ip, lsl #16
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800044a: e766 b.n 800031a <__udivmoddi4+0xfa>
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800044c: 4601 mov r1, r0
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800044e: e718 b.n 8000282 <__udivmoddi4+0x62>
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8000450: 4610 mov r0, r2
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8000452: e72c b.n 80002ae <__udivmoddi4+0x8e>
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8000454: f1c6 0220 rsb r2, r6, #32
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8000458: fa2e f302 lsr.w r3, lr, r2
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800045c: 40b7 lsls r7, r6
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800045e: 40b1 lsls r1, r6
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8000460: fa20 f202 lsr.w r2, r0, r2
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8000464: ea4f 4e17 mov.w lr, r7, lsr #16
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8000468: 430a orrs r2, r1
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800046a: fbb3 f8fe udiv r8, r3, lr
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800046e: b2bc uxth r4, r7
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8000470: fb0e 3318 mls r3, lr, r8, r3
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8000474: 0c11 lsrs r1, r2, #16
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8000476: ea41 4103 orr.w r1, r1, r3, lsl #16
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800047a: fb08 f904 mul.w r9, r8, r4
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800047e: 40b0 lsls r0, r6
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8000480: 4589 cmp r9, r1
|
|
8000482: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000486: b280 uxth r0, r0
|
|
8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8>
|
|
800048a: 1879 adds r1, r7, r1
|
|
800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276>
|
|
8000492: 4589 cmp r9, r1
|
|
8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6>
|
|
8000496: eba1 0109 sub.w r1, r1, r9
|
|
800049a: fbb1 f9fe udiv r9, r1, lr
|
|
800049e: fb09 f804 mul.w r8, r9, r4
|
|
80004a2: fb0e 1119 mls r1, lr, r9, r1
|
|
80004a6: b292 uxth r2, r2
|
|
80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004ac: 4542 cmp r2, r8
|
|
80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4>
|
|
80004b0: 18ba adds r2, r7, r2
|
|
80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222>
|
|
80004b8: 4542 cmp r2, r8
|
|
80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222>
|
|
80004bc: f1a9 0102 sub.w r1, r9, #2
|
|
80004c0: 443a add r2, r7
|
|
80004c2: e7be b.n 8000442 <__udivmoddi4+0x222>
|
|
80004c4: 45f0 cmp r8, lr
|
|
80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4>
|
|
80004c8: ebbe 0302 subs.w r3, lr, r2
|
|
80004cc: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004d0: 3801 subs r0, #1
|
|
80004d2: 46e1 mov r9, ip
|
|
80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4>
|
|
80004d6: eba7 0909 sub.w r9, r7, r9
|
|
80004da: 4449 add r1, r9
|
|
80004dc: f1a8 0c02 sub.w ip, r8, #2
|
|
80004e0: fbb1 f9fe udiv r9, r1, lr
|
|
80004e4: fb09 f804 mul.w r8, r9, r4
|
|
80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282>
|
|
80004ea: 4673 mov r3, lr
|
|
80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce>
|
|
80004ee: 4650 mov r0, sl
|
|
80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0>
|
|
80004f2: 4608 mov r0, r1
|
|
80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2>
|
|
80004f6: 443b add r3, r7
|
|
80004f8: 3a02 subs r2, #2
|
|
80004fa: e733 b.n 8000364 <__udivmoddi4+0x144>
|
|
80004fc: f1ac 0c02 sub.w ip, ip, #2
|
|
8000500: 443b add r3, r7
|
|
8000502: e71c b.n 800033e <__udivmoddi4+0x11e>
|
|
8000504: 4649 mov r1, r9
|
|
8000506: e79c b.n 8000442 <__udivmoddi4+0x222>
|
|
8000508: eba1 0109 sub.w r1, r1, r9
|
|
800050c: 46c4 mov ip, r8
|
|
800050e: fbb1 f9fe udiv r9, r1, lr
|
|
8000512: fb09 f804 mul.w r8, r9, r4
|
|
8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282>
|
|
|
|
08000518 <__aeabi_idiv0>:
|
|
8000518: 4770 bx lr
|
|
800051a: bf00 nop
|
|
|
|
0800051c <vApplicationIdleHook>:
|
|
void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName);
|
|
void vApplicationMallocFailedHook(void);
|
|
|
|
/* USER CODE BEGIN 2 */
|
|
__weak void vApplicationIdleHook( void )
|
|
{
|
|
800051c: b480 push {r7}
|
|
800051e: af00 add r7, sp, #0
|
|
specified, or call vTaskDelay()). If the application makes use of the
|
|
vTaskDelete() API function (as this demo application does) then it is also
|
|
important that vApplicationIdleHook() is permitted to return to its calling
|
|
function, because it is the responsibility of the idle task to clean up
|
|
memory allocated by the kernel to any task that has since been deleted. */
|
|
}
|
|
8000520: bf00 nop
|
|
8000522: 46bd mov sp, r7
|
|
8000524: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000528: 4770 bx lr
|
|
|
|
0800052a <vApplicationStackOverflowHook>:
|
|
/* USER CODE END 2 */
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
|
|
{
|
|
800052a: b480 push {r7}
|
|
800052c: b083 sub sp, #12
|
|
800052e: af00 add r7, sp, #0
|
|
8000530: 6078 str r0, [r7, #4]
|
|
8000532: 6039 str r1, [r7, #0]
|
|
/* Run time stack overflow checking is performed if
|
|
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
|
|
called if a stack overflow is detected. */
|
|
}
|
|
8000534: bf00 nop
|
|
8000536: 370c adds r7, #12
|
|
8000538: 46bd mov sp, r7
|
|
800053a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800053e: 4770 bx lr
|
|
|
|
08000540 <vApplicationMallocFailedHook>:
|
|
/* USER CODE END 4 */
|
|
|
|
/* USER CODE BEGIN 5 */
|
|
__weak void vApplicationMallocFailedHook(void)
|
|
{
|
|
8000540: b480 push {r7}
|
|
8000542: af00 add r7, sp, #0
|
|
demo application. If heap_1.c or heap_2.c are used, then the size of the
|
|
heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
|
|
FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
|
|
to query the size of free heap space that remains (although it does not
|
|
provide information on how the remaining heap might be fragmented). */
|
|
}
|
|
8000544: bf00 nop
|
|
8000546: 46bd mov sp, r7
|
|
8000548: f85d 7b04 ldr.w r7, [sp], #4
|
|
800054c: 4770 bx lr
|
|
...
|
|
|
|
08000550 <vApplicationGetIdleTaskMemory>:
|
|
/* USER CODE BEGIN GET_IDLE_TASK_MEMORY */
|
|
static StaticTask_t xIdleTaskTCBBuffer;
|
|
static StackType_t xIdleStack[configMINIMAL_STACK_SIZE];
|
|
|
|
void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
|
|
{
|
|
8000550: b480 push {r7}
|
|
8000552: b085 sub sp, #20
|
|
8000554: af00 add r7, sp, #0
|
|
8000556: 60f8 str r0, [r7, #12]
|
|
8000558: 60b9 str r1, [r7, #8]
|
|
800055a: 607a str r2, [r7, #4]
|
|
*ppxIdleTaskTCBBuffer = &xIdleTaskTCBBuffer;
|
|
800055c: 68fb ldr r3, [r7, #12]
|
|
800055e: 4a07 ldr r2, [pc, #28] @ (800057c <vApplicationGetIdleTaskMemory+0x2c>)
|
|
8000560: 601a str r2, [r3, #0]
|
|
*ppxIdleTaskStackBuffer = &xIdleStack[0];
|
|
8000562: 68bb ldr r3, [r7, #8]
|
|
8000564: 4a06 ldr r2, [pc, #24] @ (8000580 <vApplicationGetIdleTaskMemory+0x30>)
|
|
8000566: 601a str r2, [r3, #0]
|
|
*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
|
|
8000568: 687b ldr r3, [r7, #4]
|
|
800056a: 2280 movs r2, #128 @ 0x80
|
|
800056c: 601a str r2, [r3, #0]
|
|
/* place for user code */
|
|
}
|
|
800056e: bf00 nop
|
|
8000570: 3714 adds r7, #20
|
|
8000572: 46bd mov sp, r7
|
|
8000574: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000578: 4770 bx lr
|
|
800057a: bf00 nop
|
|
800057c: 2000009c .word 0x2000009c
|
|
8000580: 200000f4 .word 0x200000f4
|
|
|
|
08000584 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000584: b5b0 push {r4, r5, r7, lr}
|
|
8000586: b088 sub sp, #32
|
|
8000588: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
800058a: f001 f871 bl 8001670 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800058e: f000 f83d bl 800060c <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000592: f000 faab bl 8000aec <MX_GPIO_Init>
|
|
MX_CRC_Init();
|
|
8000596: f000 f8a3 bl 80006e0 <MX_CRC_Init>
|
|
MX_DMA2D_Init();
|
|
800059a: f000 f8b5 bl 8000708 <MX_DMA2D_Init>
|
|
MX_FMC_Init();
|
|
800059e: f000 fa55 bl 8000a4c <MX_FMC_Init>
|
|
MX_I2C3_Init();
|
|
80005a2: f000 f8e3 bl 800076c <MX_I2C3_Init>
|
|
MX_LTDC_Init();
|
|
80005a6: f000 f921 bl 80007ec <MX_LTDC_Init>
|
|
MX_SPI5_Init();
|
|
80005aa: f000 f99f bl 80008ec <MX_SPI5_Init>
|
|
MX_TIM1_Init();
|
|
80005ae: f000 f9d3 bl 8000958 <MX_TIM1_Init>
|
|
MX_USART1_UART_Init();
|
|
80005b2: f000 fa21 bl 80009f8 <MX_USART1_UART_Init>
|
|
/* add queues, ... */
|
|
/* USER CODE END RTOS_QUEUES */
|
|
|
|
/* Create the thread(s) */
|
|
/* definition and creation of defaultTask */
|
|
osThreadDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096);
|
|
80005b6: 4b12 ldr r3, [pc, #72] @ (8000600 <main+0x7c>)
|
|
80005b8: 1d3c adds r4, r7, #4
|
|
80005ba: 461d mov r5, r3
|
|
80005bc: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
80005be: c40f stmia r4!, {r0, r1, r2, r3}
|
|
80005c0: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
80005c4: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
|
|
80005c8: 1d3b adds r3, r7, #4
|
|
80005ca: 2100 movs r1, #0
|
|
80005cc: 4618 mov r0, r3
|
|
80005ce: f009 fe12 bl 800a1f6 <osThreadCreate>
|
|
80005d2: 4603 mov r3, r0
|
|
80005d4: 4a0b ldr r2, [pc, #44] @ (8000604 <main+0x80>)
|
|
80005d6: 6013 str r3, [r2, #0]
|
|
/* USER CODE BEGIN RTOS_THREADS */
|
|
/* add threads, ... */
|
|
/* USER CODE END RTOS_THREADS */
|
|
|
|
/* Start scheduler */
|
|
osKernelStart();
|
|
80005d8: f009 fe06 bl 800a1e8 <osKernelStart>
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
// Flashing lights go here
|
|
// Toggle LD3
|
|
HAL_GPIO_TogglePin(LD3_GPIO_Port, LD3_Pin);
|
|
80005dc: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
80005e0: 4809 ldr r0, [pc, #36] @ (8000608 <main+0x84>)
|
|
80005e2: f001 fd5a bl 800209a <HAL_GPIO_TogglePin>
|
|
// Insert delay 100ms
|
|
HAL_Delay(200);
|
|
80005e6: 20c8 movs r0, #200 @ 0xc8
|
|
80005e8: f001 f884 bl 80016f4 <HAL_Delay>
|
|
|
|
// Toggle LD4
|
|
HAL_GPIO_TogglePin(LD4_GPIO_Port, LD4_Pin);
|
|
80005ec: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
80005f0: 4805 ldr r0, [pc, #20] @ (8000608 <main+0x84>)
|
|
80005f2: f001 fd52 bl 800209a <HAL_GPIO_TogglePin>
|
|
// Insert delay 200ms
|
|
HAL_Delay(100);
|
|
80005f6: 2064 movs r0, #100 @ 0x64
|
|
80005f8: f001 f87c bl 80016f4 <HAL_Delay>
|
|
HAL_GPIO_TogglePin(LD3_GPIO_Port, LD3_Pin);
|
|
80005fc: bf00 nop
|
|
80005fe: e7ed b.n 80005dc <main+0x58>
|
|
8000600: 0800d0ac .word 0x0800d0ac
|
|
8000604: 20000554 .word 0x20000554
|
|
8000608: 40021800 .word 0x40021800
|
|
|
|
0800060c <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
800060c: b580 push {r7, lr}
|
|
800060e: b094 sub sp, #80 @ 0x50
|
|
8000610: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000612: f107 0320 add.w r3, r7, #32
|
|
8000616: 2230 movs r2, #48 @ 0x30
|
|
8000618: 2100 movs r1, #0
|
|
800061a: 4618 mov r0, r3
|
|
800061c: f00c fc98 bl 800cf50 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8000620: f107 030c add.w r3, r7, #12
|
|
8000624: 2200 movs r2, #0
|
|
8000626: 601a str r2, [r3, #0]
|
|
8000628: 605a str r2, [r3, #4]
|
|
800062a: 609a str r2, [r3, #8]
|
|
800062c: 60da str r2, [r3, #12]
|
|
800062e: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000630: 2300 movs r3, #0
|
|
8000632: 60bb str r3, [r7, #8]
|
|
8000634: 4b28 ldr r3, [pc, #160] @ (80006d8 <SystemClock_Config+0xcc>)
|
|
8000636: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000638: 4a27 ldr r2, [pc, #156] @ (80006d8 <SystemClock_Config+0xcc>)
|
|
800063a: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800063e: 6413 str r3, [r2, #64] @ 0x40
|
|
8000640: 4b25 ldr r3, [pc, #148] @ (80006d8 <SystemClock_Config+0xcc>)
|
|
8000642: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000644: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000648: 60bb str r3, [r7, #8]
|
|
800064a: 68bb ldr r3, [r7, #8]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
800064c: 2300 movs r3, #0
|
|
800064e: 607b str r3, [r7, #4]
|
|
8000650: 4b22 ldr r3, [pc, #136] @ (80006dc <SystemClock_Config+0xd0>)
|
|
8000652: 681b ldr r3, [r3, #0]
|
|
8000654: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
8000658: 4a20 ldr r2, [pc, #128] @ (80006dc <SystemClock_Config+0xd0>)
|
|
800065a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800065e: 6013 str r3, [r2, #0]
|
|
8000660: 4b1e ldr r3, [pc, #120] @ (80006dc <SystemClock_Config+0xd0>)
|
|
8000662: 681b ldr r3, [r3, #0]
|
|
8000664: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
8000668: 607b str r3, [r7, #4]
|
|
800066a: 687b ldr r3, [r7, #4]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
800066c: 2301 movs r3, #1
|
|
800066e: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
8000670: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
8000674: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8000676: 2302 movs r3, #2
|
|
8000678: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
800067a: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
800067e: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
8000680: 2304 movs r3, #4
|
|
8000682: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLN = 72;
|
|
8000684: 2348 movs r3, #72 @ 0x48
|
|
8000686: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
8000688: 2302 movs r3, #2
|
|
800068a: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLQ = 3;
|
|
800068c: 2303 movs r3, #3
|
|
800068e: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000690: f107 0320 add.w r3, r7, #32
|
|
8000694: 4618 mov r0, r3
|
|
8000696: f004 fafb bl 8004c90 <HAL_RCC_OscConfig>
|
|
800069a: 4603 mov r3, r0
|
|
800069c: 2b00 cmp r3, #0
|
|
800069e: d001 beq.n 80006a4 <SystemClock_Config+0x98>
|
|
{
|
|
Error_Handler();
|
|
80006a0: f000 fb50 bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
80006a4: 230f movs r3, #15
|
|
80006a6: 60fb str r3, [r7, #12]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
80006a8: 2302 movs r3, #2
|
|
80006aa: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
80006ac: 2300 movs r3, #0
|
|
80006ae: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
80006b0: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80006b4: 61bb str r3, [r7, #24]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
80006b6: 2300 movs r3, #0
|
|
80006b8: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
|
80006ba: f107 030c add.w r3, r7, #12
|
|
80006be: 2102 movs r1, #2
|
|
80006c0: 4618 mov r0, r3
|
|
80006c2: f004 fd5d bl 8005180 <HAL_RCC_ClockConfig>
|
|
80006c6: 4603 mov r3, r0
|
|
80006c8: 2b00 cmp r3, #0
|
|
80006ca: d001 beq.n 80006d0 <SystemClock_Config+0xc4>
|
|
{
|
|
Error_Handler();
|
|
80006cc: f000 fb3a bl 8000d44 <Error_Handler>
|
|
}
|
|
}
|
|
80006d0: bf00 nop
|
|
80006d2: 3750 adds r7, #80 @ 0x50
|
|
80006d4: 46bd mov sp, r7
|
|
80006d6: bd80 pop {r7, pc}
|
|
80006d8: 40023800 .word 0x40023800
|
|
80006dc: 40007000 .word 0x40007000
|
|
|
|
080006e0 <MX_CRC_Init>:
|
|
* @brief CRC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_CRC_Init(void)
|
|
{
|
|
80006e0: b580 push {r7, lr}
|
|
80006e2: af00 add r7, sp, #0
|
|
/* USER CODE END CRC_Init 0 */
|
|
|
|
/* USER CODE BEGIN CRC_Init 1 */
|
|
|
|
/* USER CODE END CRC_Init 1 */
|
|
hcrc.Instance = CRC;
|
|
80006e4: 4b06 ldr r3, [pc, #24] @ (8000700 <MX_CRC_Init+0x20>)
|
|
80006e6: 4a07 ldr r2, [pc, #28] @ (8000704 <MX_CRC_Init+0x24>)
|
|
80006e8: 601a str r2, [r3, #0]
|
|
if (HAL_CRC_Init(&hcrc) != HAL_OK)
|
|
80006ea: 4805 ldr r0, [pc, #20] @ (8000700 <MX_CRC_Init+0x20>)
|
|
80006ec: f001 f908 bl 8001900 <HAL_CRC_Init>
|
|
80006f0: 4603 mov r3, r0
|
|
80006f2: 2b00 cmp r3, #0
|
|
80006f4: d001 beq.n 80006fa <MX_CRC_Init+0x1a>
|
|
{
|
|
Error_Handler();
|
|
80006f6: f000 fb25 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN CRC_Init 2 */
|
|
|
|
/* USER CODE END CRC_Init 2 */
|
|
|
|
}
|
|
80006fa: bf00 nop
|
|
80006fc: bd80 pop {r7, pc}
|
|
80006fe: bf00 nop
|
|
8000700: 200002f4 .word 0x200002f4
|
|
8000704: 40023000 .word 0x40023000
|
|
|
|
08000708 <MX_DMA2D_Init>:
|
|
* @brief DMA2D Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DMA2D_Init(void)
|
|
{
|
|
8000708: b580 push {r7, lr}
|
|
800070a: af00 add r7, sp, #0
|
|
/* USER CODE END DMA2D_Init 0 */
|
|
|
|
/* USER CODE BEGIN DMA2D_Init 1 */
|
|
|
|
/* USER CODE END DMA2D_Init 1 */
|
|
hdma2d.Instance = DMA2D;
|
|
800070c: 4b15 ldr r3, [pc, #84] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
800070e: 4a16 ldr r2, [pc, #88] @ (8000768 <MX_DMA2D_Init+0x60>)
|
|
8000710: 601a str r2, [r3, #0]
|
|
hdma2d.Init.Mode = DMA2D_M2M;
|
|
8000712: 4b14 ldr r3, [pc, #80] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000714: 2200 movs r2, #0
|
|
8000716: 605a str r2, [r3, #4]
|
|
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
|
|
8000718: 4b12 ldr r3, [pc, #72] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
800071a: 2200 movs r2, #0
|
|
800071c: 609a str r2, [r3, #8]
|
|
hdma2d.Init.OutputOffset = 0;
|
|
800071e: 4b11 ldr r3, [pc, #68] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000720: 2200 movs r2, #0
|
|
8000722: 60da str r2, [r3, #12]
|
|
hdma2d.LayerCfg[1].InputOffset = 0;
|
|
8000724: 4b0f ldr r3, [pc, #60] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000726: 2200 movs r2, #0
|
|
8000728: 629a str r2, [r3, #40] @ 0x28
|
|
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
|
|
800072a: 4b0e ldr r3, [pc, #56] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
800072c: 2200 movs r2, #0
|
|
800072e: 62da str r2, [r3, #44] @ 0x2c
|
|
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
|
|
8000730: 4b0c ldr r3, [pc, #48] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000732: 2200 movs r2, #0
|
|
8000734: 631a str r2, [r3, #48] @ 0x30
|
|
hdma2d.LayerCfg[1].InputAlpha = 0;
|
|
8000736: 4b0b ldr r3, [pc, #44] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000738: 2200 movs r2, #0
|
|
800073a: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
|
|
800073c: 4809 ldr r0, [pc, #36] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
800073e: f001 f8fb bl 8001938 <HAL_DMA2D_Init>
|
|
8000742: 4603 mov r3, r0
|
|
8000744: 2b00 cmp r3, #0
|
|
8000746: d001 beq.n 800074c <MX_DMA2D_Init+0x44>
|
|
{
|
|
Error_Handler();
|
|
8000748: f000 fafc bl 8000d44 <Error_Handler>
|
|
}
|
|
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
|
|
800074c: 2101 movs r1, #1
|
|
800074e: 4805 ldr r0, [pc, #20] @ (8000764 <MX_DMA2D_Init+0x5c>)
|
|
8000750: f001 fa4c bl 8001bec <HAL_DMA2D_ConfigLayer>
|
|
8000754: 4603 mov r3, r0
|
|
8000756: 2b00 cmp r3, #0
|
|
8000758: d001 beq.n 800075e <MX_DMA2D_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
800075a: f000 faf3 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DMA2D_Init 2 */
|
|
|
|
/* USER CODE END DMA2D_Init 2 */
|
|
|
|
}
|
|
800075e: bf00 nop
|
|
8000760: bd80 pop {r7, pc}
|
|
8000762: bf00 nop
|
|
8000764: 200002fc .word 0x200002fc
|
|
8000768: 4002b000 .word 0x4002b000
|
|
|
|
0800076c <MX_I2C3_Init>:
|
|
* @brief I2C3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C3_Init(void)
|
|
{
|
|
800076c: b580 push {r7, lr}
|
|
800076e: af00 add r7, sp, #0
|
|
/* USER CODE END I2C3_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C3_Init 1 */
|
|
|
|
/* USER CODE END I2C3_Init 1 */
|
|
hi2c3.Instance = I2C3;
|
|
8000770: 4b1b ldr r3, [pc, #108] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
8000772: 4a1c ldr r2, [pc, #112] @ (80007e4 <MX_I2C3_Init+0x78>)
|
|
8000774: 601a str r2, [r3, #0]
|
|
hi2c3.Init.ClockSpeed = 100000;
|
|
8000776: 4b1a ldr r3, [pc, #104] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
8000778: 4a1b ldr r2, [pc, #108] @ (80007e8 <MX_I2C3_Init+0x7c>)
|
|
800077a: 605a str r2, [r3, #4]
|
|
hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
800077c: 4b18 ldr r3, [pc, #96] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
800077e: 2200 movs r2, #0
|
|
8000780: 609a str r2, [r3, #8]
|
|
hi2c3.Init.OwnAddress1 = 0;
|
|
8000782: 4b17 ldr r3, [pc, #92] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
8000784: 2200 movs r2, #0
|
|
8000786: 60da str r2, [r3, #12]
|
|
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8000788: 4b15 ldr r3, [pc, #84] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
800078a: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
800078e: 611a str r2, [r3, #16]
|
|
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000790: 4b13 ldr r3, [pc, #76] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
8000792: 2200 movs r2, #0
|
|
8000794: 615a str r2, [r3, #20]
|
|
hi2c3.Init.OwnAddress2 = 0;
|
|
8000796: 4b12 ldr r3, [pc, #72] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
8000798: 2200 movs r2, #0
|
|
800079a: 619a str r2, [r3, #24]
|
|
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
800079c: 4b10 ldr r3, [pc, #64] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
800079e: 2200 movs r2, #0
|
|
80007a0: 61da str r2, [r3, #28]
|
|
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
80007a2: 4b0f ldr r3, [pc, #60] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
80007a4: 2200 movs r2, #0
|
|
80007a6: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
|
|
80007a8: 480d ldr r0, [pc, #52] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
80007aa: f003 fda1 bl 80042f0 <HAL_I2C_Init>
|
|
80007ae: 4603 mov r3, r0
|
|
80007b0: 2b00 cmp r3, #0
|
|
80007b2: d001 beq.n 80007b8 <MX_I2C3_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
80007b4: f000 fac6 bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
80007b8: 2100 movs r1, #0
|
|
80007ba: 4809 ldr r0, [pc, #36] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
80007bc: f003 fedc bl 8004578 <HAL_I2CEx_ConfigAnalogFilter>
|
|
80007c0: 4603 mov r3, r0
|
|
80007c2: 2b00 cmp r3, #0
|
|
80007c4: d001 beq.n 80007ca <MX_I2C3_Init+0x5e>
|
|
{
|
|
Error_Handler();
|
|
80007c6: f000 fabd bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
|
|
80007ca: 2100 movs r1, #0
|
|
80007cc: 4804 ldr r0, [pc, #16] @ (80007e0 <MX_I2C3_Init+0x74>)
|
|
80007ce: f003 ff0f bl 80045f0 <HAL_I2CEx_ConfigDigitalFilter>
|
|
80007d2: 4603 mov r3, r0
|
|
80007d4: 2b00 cmp r3, #0
|
|
80007d6: d001 beq.n 80007dc <MX_I2C3_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
80007d8: f000 fab4 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C3_Init 2 */
|
|
|
|
/* USER CODE END I2C3_Init 2 */
|
|
|
|
}
|
|
80007dc: bf00 nop
|
|
80007de: bd80 pop {r7, pc}
|
|
80007e0: 2000033c .word 0x2000033c
|
|
80007e4: 40005c00 .word 0x40005c00
|
|
80007e8: 000186a0 .word 0x000186a0
|
|
|
|
080007ec <MX_LTDC_Init>:
|
|
* @brief LTDC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_LTDC_Init(void)
|
|
{
|
|
80007ec: b580 push {r7, lr}
|
|
80007ee: b08e sub sp, #56 @ 0x38
|
|
80007f0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN LTDC_Init 0 */
|
|
|
|
/* USER CODE END LTDC_Init 0 */
|
|
|
|
LTDC_LayerCfgTypeDef pLayerCfg = {0};
|
|
80007f2: 1d3b adds r3, r7, #4
|
|
80007f4: 2234 movs r2, #52 @ 0x34
|
|
80007f6: 2100 movs r1, #0
|
|
80007f8: 4618 mov r0, r3
|
|
80007fa: f00c fba9 bl 800cf50 <memset>
|
|
|
|
/* USER CODE BEGIN LTDC_Init 1 */
|
|
|
|
/* USER CODE END LTDC_Init 1 */
|
|
hltdc.Instance = LTDC;
|
|
80007fe: 4b39 ldr r3, [pc, #228] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000800: 4a39 ldr r2, [pc, #228] @ (80008e8 <MX_LTDC_Init+0xfc>)
|
|
8000802: 601a str r2, [r3, #0]
|
|
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
|
8000804: 4b37 ldr r3, [pc, #220] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000806: 2200 movs r2, #0
|
|
8000808: 605a str r2, [r3, #4]
|
|
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
|
800080a: 4b36 ldr r3, [pc, #216] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800080c: 2200 movs r2, #0
|
|
800080e: 609a str r2, [r3, #8]
|
|
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
|
8000810: 4b34 ldr r3, [pc, #208] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000812: 2200 movs r2, #0
|
|
8000814: 60da str r2, [r3, #12]
|
|
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
|
8000816: 4b33 ldr r3, [pc, #204] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000818: 2200 movs r2, #0
|
|
800081a: 611a str r2, [r3, #16]
|
|
hltdc.Init.HorizontalSync = 9;
|
|
800081c: 4b31 ldr r3, [pc, #196] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800081e: 2209 movs r2, #9
|
|
8000820: 615a str r2, [r3, #20]
|
|
hltdc.Init.VerticalSync = 1;
|
|
8000822: 4b30 ldr r3, [pc, #192] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000824: 2201 movs r2, #1
|
|
8000826: 619a str r2, [r3, #24]
|
|
hltdc.Init.AccumulatedHBP = 29;
|
|
8000828: 4b2e ldr r3, [pc, #184] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800082a: 221d movs r2, #29
|
|
800082c: 61da str r2, [r3, #28]
|
|
hltdc.Init.AccumulatedVBP = 3;
|
|
800082e: 4b2d ldr r3, [pc, #180] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000830: 2203 movs r2, #3
|
|
8000832: 621a str r2, [r3, #32]
|
|
hltdc.Init.AccumulatedActiveW = 269;
|
|
8000834: 4b2b ldr r3, [pc, #172] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000836: f240 120d movw r2, #269 @ 0x10d
|
|
800083a: 625a str r2, [r3, #36] @ 0x24
|
|
hltdc.Init.AccumulatedActiveH = 323;
|
|
800083c: 4b29 ldr r3, [pc, #164] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800083e: f240 1243 movw r2, #323 @ 0x143
|
|
8000842: 629a str r2, [r3, #40] @ 0x28
|
|
hltdc.Init.TotalWidth = 279;
|
|
8000844: 4b27 ldr r3, [pc, #156] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000846: f240 1217 movw r2, #279 @ 0x117
|
|
800084a: 62da str r2, [r3, #44] @ 0x2c
|
|
hltdc.Init.TotalHeigh = 327;
|
|
800084c: 4b25 ldr r3, [pc, #148] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800084e: f240 1247 movw r2, #327 @ 0x147
|
|
8000852: 631a str r2, [r3, #48] @ 0x30
|
|
hltdc.Init.Backcolor.Blue = 0;
|
|
8000854: 4b23 ldr r3, [pc, #140] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000856: 2200 movs r2, #0
|
|
8000858: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
hltdc.Init.Backcolor.Green = 0;
|
|
800085c: 4b21 ldr r3, [pc, #132] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800085e: 2200 movs r2, #0
|
|
8000860: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
hltdc.Init.Backcolor.Red = 0;
|
|
8000864: 4b1f ldr r3, [pc, #124] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
8000866: 2200 movs r2, #0
|
|
8000868: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
|
|
800086c: 481d ldr r0, [pc, #116] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
800086e: f003 fefe bl 800466e <HAL_LTDC_Init>
|
|
8000872: 4603 mov r3, r0
|
|
8000874: 2b00 cmp r3, #0
|
|
8000876: d001 beq.n 800087c <MX_LTDC_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
8000878: f000 fa64 bl 8000d44 <Error_Handler>
|
|
}
|
|
pLayerCfg.WindowX0 = 0;
|
|
800087c: 2300 movs r3, #0
|
|
800087e: 607b str r3, [r7, #4]
|
|
pLayerCfg.WindowX1 = 240;
|
|
8000880: 23f0 movs r3, #240 @ 0xf0
|
|
8000882: 60bb str r3, [r7, #8]
|
|
pLayerCfg.WindowY0 = 0;
|
|
8000884: 2300 movs r3, #0
|
|
8000886: 60fb str r3, [r7, #12]
|
|
pLayerCfg.WindowY1 = 320;
|
|
8000888: f44f 73a0 mov.w r3, #320 @ 0x140
|
|
800088c: 613b str r3, [r7, #16]
|
|
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
|
|
800088e: 2302 movs r3, #2
|
|
8000890: 617b str r3, [r7, #20]
|
|
pLayerCfg.Alpha = 255;
|
|
8000892: 23ff movs r3, #255 @ 0xff
|
|
8000894: 61bb str r3, [r7, #24]
|
|
pLayerCfg.Alpha0 = 0;
|
|
8000896: 2300 movs r3, #0
|
|
8000898: 61fb str r3, [r7, #28]
|
|
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
|
|
800089a: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
800089e: 623b str r3, [r7, #32]
|
|
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
|
|
80008a0: 2307 movs r3, #7
|
|
80008a2: 627b str r3, [r7, #36] @ 0x24
|
|
pLayerCfg.FBStartAdress = 0xD0000000;
|
|
80008a4: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000
|
|
80008a8: 62bb str r3, [r7, #40] @ 0x28
|
|
pLayerCfg.ImageWidth = 240;
|
|
80008aa: 23f0 movs r3, #240 @ 0xf0
|
|
80008ac: 62fb str r3, [r7, #44] @ 0x2c
|
|
pLayerCfg.ImageHeight = 320;
|
|
80008ae: f44f 73a0 mov.w r3, #320 @ 0x140
|
|
80008b2: 633b str r3, [r7, #48] @ 0x30
|
|
pLayerCfg.Backcolor.Blue = 0;
|
|
80008b4: 2300 movs r3, #0
|
|
80008b6: f887 3034 strb.w r3, [r7, #52] @ 0x34
|
|
pLayerCfg.Backcolor.Green = 0;
|
|
80008ba: 2300 movs r3, #0
|
|
80008bc: f887 3035 strb.w r3, [r7, #53] @ 0x35
|
|
pLayerCfg.Backcolor.Red = 0;
|
|
80008c0: 2300 movs r3, #0
|
|
80008c2: f887 3036 strb.w r3, [r7, #54] @ 0x36
|
|
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
|
|
80008c6: 1d3b adds r3, r7, #4
|
|
80008c8: 2200 movs r2, #0
|
|
80008ca: 4619 mov r1, r3
|
|
80008cc: 4805 ldr r0, [pc, #20] @ (80008e4 <MX_LTDC_Init+0xf8>)
|
|
80008ce: f004 f82d bl 800492c <HAL_LTDC_ConfigLayer>
|
|
80008d2: 4603 mov r3, r0
|
|
80008d4: 2b00 cmp r3, #0
|
|
80008d6: d001 beq.n 80008dc <MX_LTDC_Init+0xf0>
|
|
{
|
|
Error_Handler();
|
|
80008d8: f000 fa34 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN LTDC_Init 2 */
|
|
|
|
/* USER CODE END LTDC_Init 2 */
|
|
|
|
}
|
|
80008dc: bf00 nop
|
|
80008de: 3738 adds r7, #56 @ 0x38
|
|
80008e0: 46bd mov sp, r7
|
|
80008e2: bd80 pop {r7, pc}
|
|
80008e4: 20000390 .word 0x20000390
|
|
80008e8: 40016800 .word 0x40016800
|
|
|
|
080008ec <MX_SPI5_Init>:
|
|
* @brief SPI5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI5_Init(void)
|
|
{
|
|
80008ec: b580 push {r7, lr}
|
|
80008ee: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI5_Init 1 */
|
|
|
|
/* USER CODE END SPI5_Init 1 */
|
|
/* SPI5 parameter configuration*/
|
|
hspi5.Instance = SPI5;
|
|
80008f0: 4b17 ldr r3, [pc, #92] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
80008f2: 4a18 ldr r2, [pc, #96] @ (8000954 <MX_SPI5_Init+0x68>)
|
|
80008f4: 601a str r2, [r3, #0]
|
|
hspi5.Init.Mode = SPI_MODE_MASTER;
|
|
80008f6: 4b16 ldr r3, [pc, #88] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
80008f8: f44f 7282 mov.w r2, #260 @ 0x104
|
|
80008fc: 605a str r2, [r3, #4]
|
|
hspi5.Init.Direction = SPI_DIRECTION_2LINES;
|
|
80008fe: 4b14 ldr r3, [pc, #80] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000900: 2200 movs r2, #0
|
|
8000902: 609a str r2, [r3, #8]
|
|
hspi5.Init.DataSize = SPI_DATASIZE_8BIT;
|
|
8000904: 4b12 ldr r3, [pc, #72] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000906: 2200 movs r2, #0
|
|
8000908: 60da str r2, [r3, #12]
|
|
hspi5.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
800090a: 4b11 ldr r3, [pc, #68] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
800090c: 2200 movs r2, #0
|
|
800090e: 611a str r2, [r3, #16]
|
|
hspi5.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8000910: 4b0f ldr r3, [pc, #60] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000912: 2200 movs r2, #0
|
|
8000914: 615a str r2, [r3, #20]
|
|
hspi5.Init.NSS = SPI_NSS_SOFT;
|
|
8000916: 4b0e ldr r3, [pc, #56] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000918: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800091c: 619a str r2, [r3, #24]
|
|
hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
|
800091e: 4b0c ldr r3, [pc, #48] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000920: 2218 movs r2, #24
|
|
8000922: 61da str r2, [r3, #28]
|
|
hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
8000924: 4b0a ldr r3, [pc, #40] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000926: 2200 movs r2, #0
|
|
8000928: 621a str r2, [r3, #32]
|
|
hspi5.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
800092a: 4b09 ldr r3, [pc, #36] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
800092c: 2200 movs r2, #0
|
|
800092e: 625a str r2, [r3, #36] @ 0x24
|
|
hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8000930: 4b07 ldr r3, [pc, #28] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000932: 2200 movs r2, #0
|
|
8000934: 629a str r2, [r3, #40] @ 0x28
|
|
hspi5.Init.CRCPolynomial = 10;
|
|
8000936: 4b06 ldr r3, [pc, #24] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
8000938: 220a movs r2, #10
|
|
800093a: 62da str r2, [r3, #44] @ 0x2c
|
|
if (HAL_SPI_Init(&hspi5) != HAL_OK)
|
|
800093c: 4804 ldr r0, [pc, #16] @ (8000950 <MX_SPI5_Init+0x64>)
|
|
800093e: f005 f865 bl 8005a0c <HAL_SPI_Init>
|
|
8000942: 4603 mov r3, r0
|
|
8000944: 2b00 cmp r3, #0
|
|
8000946: d001 beq.n 800094c <MX_SPI5_Init+0x60>
|
|
{
|
|
Error_Handler();
|
|
8000948: f000 f9fc bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI5_Init 2 */
|
|
|
|
/* USER CODE END SPI5_Init 2 */
|
|
|
|
}
|
|
800094c: bf00 nop
|
|
800094e: bd80 pop {r7, pc}
|
|
8000950: 20000438 .word 0x20000438
|
|
8000954: 40015000 .word 0x40015000
|
|
|
|
08000958 <MX_TIM1_Init>:
|
|
* @brief TIM1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM1_Init(void)
|
|
{
|
|
8000958: b580 push {r7, lr}
|
|
800095a: b086 sub sp, #24
|
|
800095c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
800095e: f107 0308 add.w r3, r7, #8
|
|
8000962: 2200 movs r2, #0
|
|
8000964: 601a str r2, [r3, #0]
|
|
8000966: 605a str r2, [r3, #4]
|
|
8000968: 609a str r2, [r3, #8]
|
|
800096a: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
800096c: 463b mov r3, r7
|
|
800096e: 2200 movs r2, #0
|
|
8000970: 601a str r2, [r3, #0]
|
|
8000972: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
htim1.Instance = TIM1;
|
|
8000974: 4b1e ldr r3, [pc, #120] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
8000976: 4a1f ldr r2, [pc, #124] @ (80009f4 <MX_TIM1_Init+0x9c>)
|
|
8000978: 601a str r2, [r3, #0]
|
|
htim1.Init.Prescaler = 0;
|
|
800097a: 4b1d ldr r3, [pc, #116] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
800097c: 2200 movs r2, #0
|
|
800097e: 605a str r2, [r3, #4]
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000980: 4b1b ldr r3, [pc, #108] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
8000982: 2200 movs r2, #0
|
|
8000984: 609a str r2, [r3, #8]
|
|
htim1.Init.Period = 65535;
|
|
8000986: 4b1a ldr r3, [pc, #104] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
8000988: f64f 72ff movw r2, #65535 @ 0xffff
|
|
800098c: 60da str r2, [r3, #12]
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800098e: 4b18 ldr r3, [pc, #96] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
8000990: 2200 movs r2, #0
|
|
8000992: 611a str r2, [r3, #16]
|
|
htim1.Init.RepetitionCounter = 0;
|
|
8000994: 4b16 ldr r3, [pc, #88] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
8000996: 2200 movs r2, #0
|
|
8000998: 615a str r2, [r3, #20]
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
800099a: 4b15 ldr r3, [pc, #84] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
800099c: 2200 movs r2, #0
|
|
800099e: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
80009a0: 4813 ldr r0, [pc, #76] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
80009a2: f005 f8bc bl 8005b1e <HAL_TIM_Base_Init>
|
|
80009a6: 4603 mov r3, r0
|
|
80009a8: 2b00 cmp r3, #0
|
|
80009aa: d001 beq.n 80009b0 <MX_TIM1_Init+0x58>
|
|
{
|
|
Error_Handler();
|
|
80009ac: f000 f9ca bl 8000d44 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
80009b0: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
80009b4: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
80009b6: f107 0308 add.w r3, r7, #8
|
|
80009ba: 4619 mov r1, r3
|
|
80009bc: 480c ldr r0, [pc, #48] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
80009be: f005 fa5d bl 8005e7c <HAL_TIM_ConfigClockSource>
|
|
80009c2: 4603 mov r3, r0
|
|
80009c4: 2b00 cmp r3, #0
|
|
80009c6: d001 beq.n 80009cc <MX_TIM1_Init+0x74>
|
|
{
|
|
Error_Handler();
|
|
80009c8: f000 f9bc bl 8000d44 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
80009cc: 2300 movs r3, #0
|
|
80009ce: 603b str r3, [r7, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
80009d0: 2300 movs r3, #0
|
|
80009d2: 607b str r3, [r7, #4]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
80009d4: 463b mov r3, r7
|
|
80009d6: 4619 mov r1, r3
|
|
80009d8: 4805 ldr r0, [pc, #20] @ (80009f0 <MX_TIM1_Init+0x98>)
|
|
80009da: f005 fc7f bl 80062dc <HAL_TIMEx_MasterConfigSynchronization>
|
|
80009de: 4603 mov r3, r0
|
|
80009e0: 2b00 cmp r3, #0
|
|
80009e2: d001 beq.n 80009e8 <MX_TIM1_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
80009e4: f000 f9ae bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
|
}
|
|
80009e8: bf00 nop
|
|
80009ea: 3718 adds r7, #24
|
|
80009ec: 46bd mov sp, r7
|
|
80009ee: bd80 pop {r7, pc}
|
|
80009f0: 20000490 .word 0x20000490
|
|
80009f4: 40010000 .word 0x40010000
|
|
|
|
080009f8 <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
80009f8: b580 push {r7, lr}
|
|
80009fa: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
80009fc: 4b11 ldr r3, [pc, #68] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
80009fe: 4a12 ldr r2, [pc, #72] @ (8000a48 <MX_USART1_UART_Init+0x50>)
|
|
8000a00: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8000a02: 4b10 ldr r3, [pc, #64] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a04: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000a08: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8000a0a: 4b0e ldr r3, [pc, #56] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a0c: 2200 movs r2, #0
|
|
8000a0e: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8000a10: 4b0c ldr r3, [pc, #48] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a12: 2200 movs r2, #0
|
|
8000a14: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8000a16: 4b0b ldr r3, [pc, #44] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a18: 2200 movs r2, #0
|
|
8000a1a: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8000a1c: 4b09 ldr r3, [pc, #36] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a1e: 220c movs r2, #12
|
|
8000a20: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8000a22: 4b08 ldr r3, [pc, #32] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a24: 2200 movs r2, #0
|
|
8000a26: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8000a28: 4b06 ldr r3, [pc, #24] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a2a: 2200 movs r2, #0
|
|
8000a2c: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8000a2e: 4805 ldr r0, [pc, #20] @ (8000a44 <MX_USART1_UART_Init+0x4c>)
|
|
8000a30: f005 fce4 bl 80063fc <HAL_UART_Init>
|
|
8000a34: 4603 mov r3, r0
|
|
8000a36: 2b00 cmp r3, #0
|
|
8000a38: d001 beq.n 8000a3e <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
8000a3a: f000 f983 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8000a3e: bf00 nop
|
|
8000a40: bd80 pop {r7, pc}
|
|
8000a42: bf00 nop
|
|
8000a44: 200004d8 .word 0x200004d8
|
|
8000a48: 40011000 .word 0x40011000
|
|
|
|
08000a4c <MX_FMC_Init>:
|
|
|
|
/* FMC initialization function */
|
|
static void MX_FMC_Init(void)
|
|
{
|
|
8000a4c: b580 push {r7, lr}
|
|
8000a4e: b088 sub sp, #32
|
|
8000a50: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN FMC_Init 0 */
|
|
|
|
/* USER CODE END FMC_Init 0 */
|
|
|
|
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
|
|
8000a52: 1d3b adds r3, r7, #4
|
|
8000a54: 2200 movs r2, #0
|
|
8000a56: 601a str r2, [r3, #0]
|
|
8000a58: 605a str r2, [r3, #4]
|
|
8000a5a: 609a str r2, [r3, #8]
|
|
8000a5c: 60da str r2, [r3, #12]
|
|
8000a5e: 611a str r2, [r3, #16]
|
|
8000a60: 615a str r2, [r3, #20]
|
|
8000a62: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE END FMC_Init 1 */
|
|
|
|
/** Perform the SDRAM1 memory initialization sequence
|
|
*/
|
|
hsdram1.Instance = FMC_SDRAM_DEVICE;
|
|
8000a64: 4b1f ldr r3, [pc, #124] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a66: 4a20 ldr r2, [pc, #128] @ (8000ae8 <MX_FMC_Init+0x9c>)
|
|
8000a68: 601a str r2, [r3, #0]
|
|
/* hsdram1.Init */
|
|
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
|
|
8000a6a: 4b1e ldr r3, [pc, #120] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a6c: 2201 movs r2, #1
|
|
8000a6e: 605a str r2, [r3, #4]
|
|
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
|
8000a70: 4b1c ldr r3, [pc, #112] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a72: 2200 movs r2, #0
|
|
8000a74: 609a str r2, [r3, #8]
|
|
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
|
8000a76: 4b1b ldr r3, [pc, #108] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a78: 2204 movs r2, #4
|
|
8000a7a: 60da str r2, [r3, #12]
|
|
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
|
|
8000a7c: 4b19 ldr r3, [pc, #100] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a7e: 2210 movs r2, #16
|
|
8000a80: 611a str r2, [r3, #16]
|
|
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
|
8000a82: 4b18 ldr r3, [pc, #96] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a84: 2240 movs r2, #64 @ 0x40
|
|
8000a86: 615a str r2, [r3, #20]
|
|
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
|
|
8000a88: 4b16 ldr r3, [pc, #88] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a8a: f44f 72c0 mov.w r2, #384 @ 0x180
|
|
8000a8e: 619a str r2, [r3, #24]
|
|
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
|
8000a90: 4b14 ldr r3, [pc, #80] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a92: 2200 movs r2, #0
|
|
8000a94: 61da str r2, [r3, #28]
|
|
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
|
|
8000a96: 4b13 ldr r3, [pc, #76] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000a98: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8000a9c: 621a str r2, [r3, #32]
|
|
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
|
|
8000a9e: 4b11 ldr r3, [pc, #68] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000aa0: 2200 movs r2, #0
|
|
8000aa2: 625a str r2, [r3, #36] @ 0x24
|
|
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
|
|
8000aa4: 4b0f ldr r3, [pc, #60] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000aa6: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8000aaa: 629a str r2, [r3, #40] @ 0x28
|
|
/* SdramTiming */
|
|
SdramTiming.LoadToActiveDelay = 2;
|
|
8000aac: 2302 movs r3, #2
|
|
8000aae: 607b str r3, [r7, #4]
|
|
SdramTiming.ExitSelfRefreshDelay = 7;
|
|
8000ab0: 2307 movs r3, #7
|
|
8000ab2: 60bb str r3, [r7, #8]
|
|
SdramTiming.SelfRefreshTime = 4;
|
|
8000ab4: 2304 movs r3, #4
|
|
8000ab6: 60fb str r3, [r7, #12]
|
|
SdramTiming.RowCycleDelay = 7;
|
|
8000ab8: 2307 movs r3, #7
|
|
8000aba: 613b str r3, [r7, #16]
|
|
SdramTiming.WriteRecoveryTime = 3;
|
|
8000abc: 2303 movs r3, #3
|
|
8000abe: 617b str r3, [r7, #20]
|
|
SdramTiming.RPDelay = 2;
|
|
8000ac0: 2302 movs r3, #2
|
|
8000ac2: 61bb str r3, [r7, #24]
|
|
SdramTiming.RCDDelay = 2;
|
|
8000ac4: 2302 movs r3, #2
|
|
8000ac6: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
|
|
8000ac8: 1d3b adds r3, r7, #4
|
|
8000aca: 4619 mov r1, r3
|
|
8000acc: 4805 ldr r0, [pc, #20] @ (8000ae4 <MX_FMC_Init+0x98>)
|
|
8000ace: f004 ff69 bl 80059a4 <HAL_SDRAM_Init>
|
|
8000ad2: 4603 mov r3, r0
|
|
8000ad4: 2b00 cmp r3, #0
|
|
8000ad6: d001 beq.n 8000adc <MX_FMC_Init+0x90>
|
|
{
|
|
Error_Handler( );
|
|
8000ad8: f000 f934 bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN FMC_Init 2 */
|
|
|
|
/* USER CODE END FMC_Init 2 */
|
|
}
|
|
8000adc: bf00 nop
|
|
8000ade: 3720 adds r7, #32
|
|
8000ae0: 46bd mov sp, r7
|
|
8000ae2: bd80 pop {r7, pc}
|
|
8000ae4: 20000520 .word 0x20000520
|
|
8000ae8: a0000140 .word 0xa0000140
|
|
|
|
08000aec <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000aec: b580 push {r7, lr}
|
|
8000aee: b08e sub sp, #56 @ 0x38
|
|
8000af0: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000af2: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000af6: 2200 movs r2, #0
|
|
8000af8: 601a str r2, [r3, #0]
|
|
8000afa: 605a str r2, [r3, #4]
|
|
8000afc: 609a str r2, [r3, #8]
|
|
8000afe: 60da str r2, [r3, #12]
|
|
8000b00: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000b02: 2300 movs r3, #0
|
|
8000b04: 623b str r3, [r7, #32]
|
|
8000b06: 4b7b ldr r3, [pc, #492] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b08: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b0a: 4a7a ldr r2, [pc, #488] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b0c: f043 0304 orr.w r3, r3, #4
|
|
8000b10: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b12: 4b78 ldr r3, [pc, #480] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b14: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b16: f003 0304 and.w r3, r3, #4
|
|
8000b1a: 623b str r3, [r7, #32]
|
|
8000b1c: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8000b1e: 2300 movs r3, #0
|
|
8000b20: 61fb str r3, [r7, #28]
|
|
8000b22: 4b74 ldr r3, [pc, #464] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b24: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b26: 4a73 ldr r2, [pc, #460] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b28: f043 0320 orr.w r3, r3, #32
|
|
8000b2c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b2e: 4b71 ldr r3, [pc, #452] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b30: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b32: f003 0320 and.w r3, r3, #32
|
|
8000b36: 61fb str r3, [r7, #28]
|
|
8000b38: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000b3a: 2300 movs r3, #0
|
|
8000b3c: 61bb str r3, [r7, #24]
|
|
8000b3e: 4b6d ldr r3, [pc, #436] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b40: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b42: 4a6c ldr r2, [pc, #432] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b44: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000b48: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b4a: 4b6a ldr r3, [pc, #424] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b4c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b4e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8000b52: 61bb str r3, [r7, #24]
|
|
8000b54: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000b56: 2300 movs r3, #0
|
|
8000b58: 617b str r3, [r7, #20]
|
|
8000b5a: 4b66 ldr r3, [pc, #408] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b5e: 4a65 ldr r2, [pc, #404] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b60: f043 0301 orr.w r3, r3, #1
|
|
8000b64: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b66: 4b63 ldr r3, [pc, #396] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b68: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b6a: f003 0301 and.w r3, r3, #1
|
|
8000b6e: 617b str r3, [r7, #20]
|
|
8000b70: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000b72: 2300 movs r3, #0
|
|
8000b74: 613b str r3, [r7, #16]
|
|
8000b76: 4b5f ldr r3, [pc, #380] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b78: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b7a: 4a5e ldr r2, [pc, #376] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b7c: f043 0302 orr.w r3, r3, #2
|
|
8000b80: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b82: 4b5c ldr r3, [pc, #368] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b84: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b86: f003 0302 and.w r3, r3, #2
|
|
8000b8a: 613b str r3, [r7, #16]
|
|
8000b8c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8000b8e: 2300 movs r3, #0
|
|
8000b90: 60fb str r3, [r7, #12]
|
|
8000b92: 4b58 ldr r3, [pc, #352] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b96: 4a57 ldr r2, [pc, #348] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000b98: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8000b9c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b9e: 4b55 ldr r3, [pc, #340] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000ba0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ba2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8000ba6: 60fb str r3, [r7, #12]
|
|
8000ba8: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8000baa: 2300 movs r3, #0
|
|
8000bac: 60bb str r3, [r7, #8]
|
|
8000bae: 4b51 ldr r3, [pc, #324] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bb0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bb2: 4a50 ldr r2, [pc, #320] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bb4: f043 0310 orr.w r3, r3, #16
|
|
8000bb8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bba: 4b4e ldr r3, [pc, #312] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bbc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bbe: f003 0310 and.w r3, r3, #16
|
|
8000bc2: 60bb str r3, [r7, #8]
|
|
8000bc4: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000bc6: 2300 movs r3, #0
|
|
8000bc8: 607b str r3, [r7, #4]
|
|
8000bca: 4b4a ldr r3, [pc, #296] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bcc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bce: 4a49 ldr r2, [pc, #292] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bd0: f043 0308 orr.w r3, r3, #8
|
|
8000bd4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000bd6: 4b47 ldr r3, [pc, #284] @ (8000cf4 <MX_GPIO_Init+0x208>)
|
|
8000bd8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000bda: f003 0308 and.w r3, r3, #8
|
|
8000bde: 607b str r3, [r7, #4]
|
|
8000be0: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET);
|
|
8000be2: 2200 movs r2, #0
|
|
8000be4: 2116 movs r1, #22
|
|
8000be6: 4844 ldr r0, [pc, #272] @ (8000cf8 <MX_GPIO_Init+0x20c>)
|
|
8000be8: f001 fa3e bl 8002068 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET);
|
|
8000bec: 2200 movs r2, #0
|
|
8000bee: 2180 movs r1, #128 @ 0x80
|
|
8000bf0: 4842 ldr r0, [pc, #264] @ (8000cfc <MX_GPIO_Init+0x210>)
|
|
8000bf2: f001 fa39 bl 8002068 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET);
|
|
8000bf6: 2200 movs r2, #0
|
|
8000bf8: f44f 5140 mov.w r1, #12288 @ 0x3000
|
|
8000bfc: 4840 ldr r0, [pc, #256] @ (8000d00 <MX_GPIO_Init+0x214>)
|
|
8000bfe: f001 fa33 bl 8002068 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET);
|
|
8000c02: 2200 movs r2, #0
|
|
8000c04: f44f 41c0 mov.w r1, #24576 @ 0x6000
|
|
8000c08: 483e ldr r0, [pc, #248] @ (8000d04 <MX_GPIO_Init+0x218>)
|
|
8000c0a: f001 fa2d bl 8002068 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */
|
|
GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin;
|
|
8000c0e: 2316 movs r3, #22
|
|
8000c10: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c12: 2301 movs r3, #1
|
|
8000c14: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c16: 2300 movs r3, #0
|
|
8000c18: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c1a: 2300 movs r3, #0
|
|
8000c1c: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000c1e: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c22: 4619 mov r1, r3
|
|
8000c24: 4834 ldr r0, [pc, #208] @ (8000cf8 <MX_GPIO_Init+0x20c>)
|
|
8000c26: f001 f873 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */
|
|
GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin;
|
|
8000c2a: f248 0307 movw r3, #32775 @ 0x8007
|
|
8000c2e: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8000c30: f44f 1390 mov.w r3, #1179648 @ 0x120000
|
|
8000c34: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c36: 2300 movs r3, #0
|
|
8000c38: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000c3a: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c3e: 4619 mov r1, r3
|
|
8000c40: 482e ldr r0, [pc, #184] @ (8000cfc <MX_GPIO_Init+0x210>)
|
|
8000c42: f001 f865 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ACP_RST_Pin */
|
|
GPIO_InitStruct.Pin = ACP_RST_Pin;
|
|
8000c46: 2380 movs r3, #128 @ 0x80
|
|
8000c48: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c4a: 2301 movs r3, #1
|
|
8000c4c: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c4e: 2300 movs r3, #0
|
|
8000c50: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c52: 2300 movs r3, #0
|
|
8000c54: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct);
|
|
8000c56: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c5a: 4619 mov r1, r3
|
|
8000c5c: 4827 ldr r0, [pc, #156] @ (8000cfc <MX_GPIO_Init+0x210>)
|
|
8000c5e: f001 f857 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : OTG_FS_OC_Pin */
|
|
GPIO_InitStruct.Pin = OTG_FS_OC_Pin;
|
|
8000c62: 2320 movs r3, #32
|
|
8000c64: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8000c66: f44f 1390 mov.w r3, #1179648 @ 0x120000
|
|
8000c6a: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c6c: 2300 movs r3, #0
|
|
8000c6e: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct);
|
|
8000c70: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c74: 4619 mov r1, r3
|
|
8000c76: 4820 ldr r0, [pc, #128] @ (8000cf8 <MX_GPIO_Init+0x20c>)
|
|
8000c78: f001 f84a bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : BOOT1_Pin */
|
|
GPIO_InitStruct.Pin = BOOT1_Pin;
|
|
8000c7c: 2304 movs r3, #4
|
|
8000c7e: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c80: 2300 movs r3, #0
|
|
8000c82: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c84: 2300 movs r3, #0
|
|
8000c86: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
|
|
8000c88: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c8c: 4619 mov r1, r3
|
|
8000c8e: 481e ldr r0, [pc, #120] @ (8000d08 <MX_GPIO_Init+0x21c>)
|
|
8000c90: f001 f83e bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : TE_Pin */
|
|
GPIO_InitStruct.Pin = TE_Pin;
|
|
8000c94: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
8000c98: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c9a: 2300 movs r3, #0
|
|
8000c9c: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c9e: 2300 movs r3, #0
|
|
8000ca0: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct);
|
|
8000ca2: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000ca6: 4619 mov r1, r3
|
|
8000ca8: 4815 ldr r0, [pc, #84] @ (8000d00 <MX_GPIO_Init+0x214>)
|
|
8000caa: f001 f831 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */
|
|
GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin;
|
|
8000cae: f44f 5340 mov.w r3, #12288 @ 0x3000
|
|
8000cb2: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000cb4: 2301 movs r3, #1
|
|
8000cb6: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000cb8: 2300 movs r3, #0
|
|
8000cba: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000cbc: 2300 movs r3, #0
|
|
8000cbe: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8000cc0: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000cc4: 4619 mov r1, r3
|
|
8000cc6: 480e ldr r0, [pc, #56] @ (8000d00 <MX_GPIO_Init+0x214>)
|
|
8000cc8: f001 f822 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LD3_Pin LD4_Pin */
|
|
GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin;
|
|
8000ccc: f44f 43c0 mov.w r3, #24576 @ 0x6000
|
|
8000cd0: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000cd2: 2301 movs r3, #1
|
|
8000cd4: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000cd6: 2300 movs r3, #0
|
|
8000cd8: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000cda: 2300 movs r3, #0
|
|
8000cdc: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8000cde: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000ce2: 4619 mov r1, r3
|
|
8000ce4: 4807 ldr r0, [pc, #28] @ (8000d04 <MX_GPIO_Init+0x218>)
|
|
8000ce6: f001 f813 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000cea: bf00 nop
|
|
8000cec: 3738 adds r7, #56 @ 0x38
|
|
8000cee: 46bd mov sp, r7
|
|
8000cf0: bd80 pop {r7, pc}
|
|
8000cf2: bf00 nop
|
|
8000cf4: 40023800 .word 0x40023800
|
|
8000cf8: 40020800 .word 0x40020800
|
|
8000cfc: 40020000 .word 0x40020000
|
|
8000d00: 40020c00 .word 0x40020c00
|
|
8000d04: 40021800 .word 0x40021800
|
|
8000d08: 40020400 .word 0x40020400
|
|
|
|
08000d0c <StartDefaultTask>:
|
|
* @param argument: Not used
|
|
* @retval None
|
|
*/
|
|
/* USER CODE END Header_StartDefaultTask */
|
|
void StartDefaultTask(void const * argument)
|
|
{
|
|
8000d0c: b580 push {r7, lr}
|
|
8000d0e: b082 sub sp, #8
|
|
8000d10: af00 add r7, sp, #0
|
|
8000d12: 6078 str r0, [r7, #4]
|
|
/* init code for USB_HOST */
|
|
MX_USB_HOST_Init();
|
|
8000d14: f00b fd66 bl 800c7e4 <MX_USB_HOST_Init>
|
|
/* USER CODE BEGIN 5 */
|
|
/* Infinite loop */
|
|
for(;;)
|
|
{
|
|
osDelay(1);
|
|
8000d18: 2001 movs r0, #1
|
|
8000d1a: f009 fab8 bl 800a28e <osDelay>
|
|
8000d1e: e7fb b.n 8000d18 <StartDefaultTask+0xc>
|
|
|
|
08000d20 <HAL_TIM_PeriodElapsedCallback>:
|
|
* a global variable "uwTick" used as application time base.
|
|
* @param htim : TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8000d20: b580 push {r7, lr}
|
|
8000d22: b082 sub sp, #8
|
|
8000d24: af00 add r7, sp, #0
|
|
8000d26: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Callback 0 */
|
|
|
|
/* USER CODE END Callback 0 */
|
|
if (htim->Instance == TIM6)
|
|
8000d28: 687b ldr r3, [r7, #4]
|
|
8000d2a: 681b ldr r3, [r3, #0]
|
|
8000d2c: 4a04 ldr r2, [pc, #16] @ (8000d40 <HAL_TIM_PeriodElapsedCallback+0x20>)
|
|
8000d2e: 4293 cmp r3, r2
|
|
8000d30: d101 bne.n 8000d36 <HAL_TIM_PeriodElapsedCallback+0x16>
|
|
{
|
|
HAL_IncTick();
|
|
8000d32: f000 fcbf bl 80016b4 <HAL_IncTick>
|
|
}
|
|
/* USER CODE BEGIN Callback 1 */
|
|
|
|
/* USER CODE END Callback 1 */
|
|
}
|
|
8000d36: bf00 nop
|
|
8000d38: 3708 adds r7, #8
|
|
8000d3a: 46bd mov sp, r7
|
|
8000d3c: bd80 pop {r7, pc}
|
|
8000d3e: bf00 nop
|
|
8000d40: 40001000 .word 0x40001000
|
|
|
|
08000d44 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000d44: b480 push {r7}
|
|
8000d46: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000d48: b672 cpsid i
|
|
}
|
|
8000d4a: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000d4c: bf00 nop
|
|
8000d4e: e7fd b.n 8000d4c <Error_Handler+0x8>
|
|
|
|
08000d50 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000d50: b580 push {r7, lr}
|
|
8000d52: b082 sub sp, #8
|
|
8000d54: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000d56: 2300 movs r3, #0
|
|
8000d58: 607b str r3, [r7, #4]
|
|
8000d5a: 4b12 ldr r3, [pc, #72] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d5c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000d5e: 4a11 ldr r2, [pc, #68] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d60: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000d64: 6453 str r3, [r2, #68] @ 0x44
|
|
8000d66: 4b0f ldr r3, [pc, #60] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d68: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000d6a: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000d6e: 607b str r3, [r7, #4]
|
|
8000d70: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000d72: 2300 movs r3, #0
|
|
8000d74: 603b str r3, [r7, #0]
|
|
8000d76: 4b0b ldr r3, [pc, #44] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d78: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d7a: 4a0a ldr r2, [pc, #40] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d7c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000d80: 6413 str r3, [r2, #64] @ 0x40
|
|
8000d82: 4b08 ldr r3, [pc, #32] @ (8000da4 <HAL_MspInit+0x54>)
|
|
8000d84: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000d86: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000d8a: 603b str r3, [r7, #0]
|
|
8000d8c: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
/* PendSV_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
|
8000d8e: 2200 movs r2, #0
|
|
8000d90: 210f movs r1, #15
|
|
8000d92: f06f 0001 mvn.w r0, #1
|
|
8000d96: f000 fd89 bl 80018ac <HAL_NVIC_SetPriority>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000d9a: bf00 nop
|
|
8000d9c: 3708 adds r7, #8
|
|
8000d9e: 46bd mov sp, r7
|
|
8000da0: bd80 pop {r7, pc}
|
|
8000da2: bf00 nop
|
|
8000da4: 40023800 .word 0x40023800
|
|
|
|
08000da8 <HAL_CRC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hcrc: CRC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
|
|
{
|
|
8000da8: b480 push {r7}
|
|
8000daa: b085 sub sp, #20
|
|
8000dac: af00 add r7, sp, #0
|
|
8000dae: 6078 str r0, [r7, #4]
|
|
if(hcrc->Instance==CRC)
|
|
8000db0: 687b ldr r3, [r7, #4]
|
|
8000db2: 681b ldr r3, [r3, #0]
|
|
8000db4: 4a0b ldr r2, [pc, #44] @ (8000de4 <HAL_CRC_MspInit+0x3c>)
|
|
8000db6: 4293 cmp r3, r2
|
|
8000db8: d10d bne.n 8000dd6 <HAL_CRC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN CRC_MspInit 0 */
|
|
|
|
/* USER CODE END CRC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_CRC_CLK_ENABLE();
|
|
8000dba: 2300 movs r3, #0
|
|
8000dbc: 60fb str r3, [r7, #12]
|
|
8000dbe: 4b0a ldr r3, [pc, #40] @ (8000de8 <HAL_CRC_MspInit+0x40>)
|
|
8000dc0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dc2: 4a09 ldr r2, [pc, #36] @ (8000de8 <HAL_CRC_MspInit+0x40>)
|
|
8000dc4: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
8000dc8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000dca: 4b07 ldr r3, [pc, #28] @ (8000de8 <HAL_CRC_MspInit+0x40>)
|
|
8000dcc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dce: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8000dd2: 60fb str r3, [r7, #12]
|
|
8000dd4: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END CRC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000dd6: bf00 nop
|
|
8000dd8: 3714 adds r7, #20
|
|
8000dda: 46bd mov sp, r7
|
|
8000ddc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000de0: 4770 bx lr
|
|
8000de2: bf00 nop
|
|
8000de4: 40023000 .word 0x40023000
|
|
8000de8: 40023800 .word 0x40023800
|
|
|
|
08000dec <HAL_DMA2D_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdma2d: DMA2D handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
|
|
{
|
|
8000dec: b580 push {r7, lr}
|
|
8000dee: b084 sub sp, #16
|
|
8000df0: af00 add r7, sp, #0
|
|
8000df2: 6078 str r0, [r7, #4]
|
|
if(hdma2d->Instance==DMA2D)
|
|
8000df4: 687b ldr r3, [r7, #4]
|
|
8000df6: 681b ldr r3, [r3, #0]
|
|
8000df8: 4a0e ldr r2, [pc, #56] @ (8000e34 <HAL_DMA2D_MspInit+0x48>)
|
|
8000dfa: 4293 cmp r3, r2
|
|
8000dfc: d115 bne.n 8000e2a <HAL_DMA2D_MspInit+0x3e>
|
|
{
|
|
/* USER CODE BEGIN DMA2D_MspInit 0 */
|
|
|
|
/* USER CODE END DMA2D_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DMA2D_CLK_ENABLE();
|
|
8000dfe: 2300 movs r3, #0
|
|
8000e00: 60fb str r3, [r7, #12]
|
|
8000e02: 4b0d ldr r3, [pc, #52] @ (8000e38 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000e04: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e06: 4a0c ldr r2, [pc, #48] @ (8000e38 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000e08: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
8000e0c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000e0e: 4b0a ldr r3, [pc, #40] @ (8000e38 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000e10: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e12: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8000e16: 60fb str r3, [r7, #12]
|
|
8000e18: 68fb ldr r3, [r7, #12]
|
|
/* DMA2D interrupt Init */
|
|
HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
|
|
8000e1a: 2200 movs r2, #0
|
|
8000e1c: 2105 movs r1, #5
|
|
8000e1e: 205a movs r0, #90 @ 0x5a
|
|
8000e20: f000 fd44 bl 80018ac <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
|
|
8000e24: 205a movs r0, #90 @ 0x5a
|
|
8000e26: f000 fd5d bl 80018e4 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END DMA2D_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000e2a: bf00 nop
|
|
8000e2c: 3710 adds r7, #16
|
|
8000e2e: 46bd mov sp, r7
|
|
8000e30: bd80 pop {r7, pc}
|
|
8000e32: bf00 nop
|
|
8000e34: 4002b000 .word 0x4002b000
|
|
8000e38: 40023800 .word 0x40023800
|
|
|
|
08000e3c <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8000e3c: b580 push {r7, lr}
|
|
8000e3e: b08a sub sp, #40 @ 0x28
|
|
8000e40: af00 add r7, sp, #0
|
|
8000e42: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000e44: f107 0314 add.w r3, r7, #20
|
|
8000e48: 2200 movs r2, #0
|
|
8000e4a: 601a str r2, [r3, #0]
|
|
8000e4c: 605a str r2, [r3, #4]
|
|
8000e4e: 609a str r2, [r3, #8]
|
|
8000e50: 60da str r2, [r3, #12]
|
|
8000e52: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C3)
|
|
8000e54: 687b ldr r3, [r7, #4]
|
|
8000e56: 681b ldr r3, [r3, #0]
|
|
8000e58: 4a29 ldr r2, [pc, #164] @ (8000f00 <HAL_I2C_MspInit+0xc4>)
|
|
8000e5a: 4293 cmp r3, r2
|
|
8000e5c: d14b bne.n 8000ef6 <HAL_I2C_MspInit+0xba>
|
|
{
|
|
/* USER CODE BEGIN I2C3_MspInit 0 */
|
|
|
|
/* USER CODE END I2C3_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000e5e: 2300 movs r3, #0
|
|
8000e60: 613b str r3, [r7, #16]
|
|
8000e62: 4b28 ldr r3, [pc, #160] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e64: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e66: 4a27 ldr r2, [pc, #156] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e68: f043 0304 orr.w r3, r3, #4
|
|
8000e6c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000e6e: 4b25 ldr r3, [pc, #148] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e70: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e72: f003 0304 and.w r3, r3, #4
|
|
8000e76: 613b str r3, [r7, #16]
|
|
8000e78: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000e7a: 2300 movs r3, #0
|
|
8000e7c: 60fb str r3, [r7, #12]
|
|
8000e7e: 4b21 ldr r3, [pc, #132] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e80: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e82: 4a20 ldr r2, [pc, #128] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e84: f043 0301 orr.w r3, r3, #1
|
|
8000e88: 6313 str r3, [r2, #48] @ 0x30
|
|
8000e8a: 4b1e ldr r3, [pc, #120] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000e8c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000e8e: f003 0301 and.w r3, r3, #1
|
|
8000e92: 60fb str r3, [r7, #12]
|
|
8000e94: 68fb ldr r3, [r7, #12]
|
|
/**I2C3 GPIO Configuration
|
|
PC9 ------> I2C3_SDA
|
|
PA8 ------> I2C3_SCL
|
|
*/
|
|
GPIO_InitStruct.Pin = I2C3_SDA_Pin;
|
|
8000e96: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8000e9a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000e9c: 2312 movs r3, #18
|
|
8000e9e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8000ea0: 2301 movs r3, #1
|
|
8000ea2: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000ea4: 2300 movs r3, #0
|
|
8000ea6: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
|
|
8000ea8: 2304 movs r3, #4
|
|
8000eaa: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct);
|
|
8000eac: f107 0314 add.w r3, r7, #20
|
|
8000eb0: 4619 mov r1, r3
|
|
8000eb2: 4815 ldr r0, [pc, #84] @ (8000f08 <HAL_I2C_MspInit+0xcc>)
|
|
8000eb4: f000 ff2c bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = I2C3_SCL_Pin;
|
|
8000eb8: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000ebc: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000ebe: 2312 movs r3, #18
|
|
8000ec0: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8000ec2: 2301 movs r3, #1
|
|
8000ec4: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000ec6: 2300 movs r3, #0
|
|
8000ec8: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
|
|
8000eca: 2304 movs r3, #4
|
|
8000ecc: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct);
|
|
8000ece: f107 0314 add.w r3, r7, #20
|
|
8000ed2: 4619 mov r1, r3
|
|
8000ed4: 480d ldr r0, [pc, #52] @ (8000f0c <HAL_I2C_MspInit+0xd0>)
|
|
8000ed6: f000 ff1b bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C3_CLK_ENABLE();
|
|
8000eda: 2300 movs r3, #0
|
|
8000edc: 60bb str r3, [r7, #8]
|
|
8000ede: 4b09 ldr r3, [pc, #36] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000ee0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ee2: 4a08 ldr r2, [pc, #32] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000ee4: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
8000ee8: 6413 str r3, [r2, #64] @ 0x40
|
|
8000eea: 4b06 ldr r3, [pc, #24] @ (8000f04 <HAL_I2C_MspInit+0xc8>)
|
|
8000eec: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000eee: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8000ef2: 60bb str r3, [r7, #8]
|
|
8000ef4: 68bb ldr r3, [r7, #8]
|
|
|
|
/* USER CODE END I2C3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000ef6: bf00 nop
|
|
8000ef8: 3728 adds r7, #40 @ 0x28
|
|
8000efa: 46bd mov sp, r7
|
|
8000efc: bd80 pop {r7, pc}
|
|
8000efe: bf00 nop
|
|
8000f00: 40005c00 .word 0x40005c00
|
|
8000f04: 40023800 .word 0x40023800
|
|
8000f08: 40020800 .word 0x40020800
|
|
8000f0c: 40020000 .word 0x40020000
|
|
|
|
08000f10 <HAL_LTDC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hltdc: LTDC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
|
|
{
|
|
8000f10: b580 push {r7, lr}
|
|
8000f12: b09a sub sp, #104 @ 0x68
|
|
8000f14: af00 add r7, sp, #0
|
|
8000f16: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000f18: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8000f1c: 2200 movs r2, #0
|
|
8000f1e: 601a str r2, [r3, #0]
|
|
8000f20: 605a str r2, [r3, #4]
|
|
8000f22: 609a str r2, [r3, #8]
|
|
8000f24: 60da str r2, [r3, #12]
|
|
8000f26: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8000f28: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000f2c: 2230 movs r2, #48 @ 0x30
|
|
8000f2e: 2100 movs r1, #0
|
|
8000f30: 4618 mov r0, r3
|
|
8000f32: f00c f80d bl 800cf50 <memset>
|
|
if(hltdc->Instance==LTDC)
|
|
8000f36: 687b ldr r3, [r7, #4]
|
|
8000f38: 681b ldr r3, [r3, #0]
|
|
8000f3a: 4a85 ldr r2, [pc, #532] @ (8001150 <HAL_LTDC_MspInit+0x240>)
|
|
8000f3c: 4293 cmp r3, r2
|
|
8000f3e: f040 8102 bne.w 8001146 <HAL_LTDC_MspInit+0x236>
|
|
|
|
/* USER CODE END LTDC_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
|
|
8000f42: 2308 movs r3, #8
|
|
8000f44: 627b str r3, [r7, #36] @ 0x24
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIN = 50;
|
|
8000f46: 2332 movs r3, #50 @ 0x32
|
|
8000f48: 637b str r3, [r7, #52] @ 0x34
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
|
|
8000f4a: 2302 movs r3, #2
|
|
8000f4c: 63fb str r3, [r7, #60] @ 0x3c
|
|
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
|
|
8000f4e: 2300 movs r3, #0
|
|
8000f50: 64bb str r3, [r7, #72] @ 0x48
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8000f52: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000f56: 4618 mov r0, r3
|
|
8000f58: f004 fb64 bl 8005624 <HAL_RCCEx_PeriphCLKConfig>
|
|
8000f5c: 4603 mov r3, r0
|
|
8000f5e: 2b00 cmp r3, #0
|
|
8000f60: d001 beq.n 8000f66 <HAL_LTDC_MspInit+0x56>
|
|
{
|
|
Error_Handler();
|
|
8000f62: f7ff feef bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_LTDC_CLK_ENABLE();
|
|
8000f66: 2300 movs r3, #0
|
|
8000f68: 623b str r3, [r7, #32]
|
|
8000f6a: 4b7a ldr r3, [pc, #488] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f6c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000f6e: 4a79 ldr r2, [pc, #484] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f70: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8000f74: 6453 str r3, [r2, #68] @ 0x44
|
|
8000f76: 4b77 ldr r3, [pc, #476] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f78: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000f7a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8000f7e: 623b str r3, [r7, #32]
|
|
8000f80: 6a3b ldr r3, [r7, #32]
|
|
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8000f82: 2300 movs r3, #0
|
|
8000f84: 61fb str r3, [r7, #28]
|
|
8000f86: 4b73 ldr r3, [pc, #460] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f88: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f8a: 4a72 ldr r2, [pc, #456] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f8c: f043 0320 orr.w r3, r3, #32
|
|
8000f90: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f92: 4b70 ldr r3, [pc, #448] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000f94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f96: f003 0320 and.w r3, r3, #32
|
|
8000f9a: 61fb str r3, [r7, #28]
|
|
8000f9c: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000f9e: 2300 movs r3, #0
|
|
8000fa0: 61bb str r3, [r7, #24]
|
|
8000fa2: 4b6c ldr r3, [pc, #432] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fa4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fa6: 4a6b ldr r2, [pc, #428] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fa8: f043 0301 orr.w r3, r3, #1
|
|
8000fac: 6313 str r3, [r2, #48] @ 0x30
|
|
8000fae: 4b69 ldr r3, [pc, #420] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fb0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fb2: f003 0301 and.w r3, r3, #1
|
|
8000fb6: 61bb str r3, [r7, #24]
|
|
8000fb8: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000fba: 2300 movs r3, #0
|
|
8000fbc: 617b str r3, [r7, #20]
|
|
8000fbe: 4b65 ldr r3, [pc, #404] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fc0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fc2: 4a64 ldr r2, [pc, #400] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fc4: f043 0302 orr.w r3, r3, #2
|
|
8000fc8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000fca: 4b62 ldr r3, [pc, #392] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fcc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fce: f003 0302 and.w r3, r3, #2
|
|
8000fd2: 617b str r3, [r7, #20]
|
|
8000fd4: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8000fd6: 2300 movs r3, #0
|
|
8000fd8: 613b str r3, [r7, #16]
|
|
8000fda: 4b5e ldr r3, [pc, #376] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fdc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fde: 4a5d ldr r2, [pc, #372] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fe0: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8000fe4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000fe6: 4b5b ldr r3, [pc, #364] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000fe8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000fea: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8000fee: 613b str r3, [r7, #16]
|
|
8000ff0: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000ff2: 2300 movs r3, #0
|
|
8000ff4: 60fb str r3, [r7, #12]
|
|
8000ff6: 4b57 ldr r3, [pc, #348] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000ff8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ffa: 4a56 ldr r2, [pc, #344] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8000ffc: f043 0304 orr.w r3, r3, #4
|
|
8001000: 6313 str r3, [r2, #48] @ 0x30
|
|
8001002: 4b54 ldr r3, [pc, #336] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8001004: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001006: f003 0304 and.w r3, r3, #4
|
|
800100a: 60fb str r3, [r7, #12]
|
|
800100c: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
800100e: 2300 movs r3, #0
|
|
8001010: 60bb str r3, [r7, #8]
|
|
8001012: 4b50 ldr r3, [pc, #320] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8001014: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001016: 4a4f ldr r2, [pc, #316] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8001018: f043 0308 orr.w r3, r3, #8
|
|
800101c: 6313 str r3, [r2, #48] @ 0x30
|
|
800101e: 4b4d ldr r3, [pc, #308] @ (8001154 <HAL_LTDC_MspInit+0x244>)
|
|
8001020: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001022: f003 0308 and.w r3, r3, #8
|
|
8001026: 60bb str r3, [r7, #8]
|
|
8001028: 68bb ldr r3, [r7, #8]
|
|
PG11 ------> LTDC_B3
|
|
PG12 ------> LTDC_B4
|
|
PB8 ------> LTDC_B6
|
|
PB9 ------> LTDC_B7
|
|
*/
|
|
GPIO_InitStruct.Pin = ENABLE_Pin;
|
|
800102a: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
800102e: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001030: 2302 movs r3, #2
|
|
8001032: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001034: 2300 movs r3, #0
|
|
8001036: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001038: 2300 movs r3, #0
|
|
800103a: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800103c: 230e movs r3, #14
|
|
800103e: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct);
|
|
8001040: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001044: 4619 mov r1, r3
|
|
8001046: 4844 ldr r0, [pc, #272] @ (8001158 <HAL_LTDC_MspInit+0x248>)
|
|
8001048: f000 fe62 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin
|
|
800104c: f641 0358 movw r3, #6232 @ 0x1858
|
|
8001050: 657b str r3, [r7, #84] @ 0x54
|
|
|R5_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001052: 2302 movs r3, #2
|
|
8001054: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001056: 2300 movs r3, #0
|
|
8001058: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800105a: 2300 movs r3, #0
|
|
800105c: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800105e: 230e movs r3, #14
|
|
8001060: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001062: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001066: 4619 mov r1, r3
|
|
8001068: 483c ldr r0, [pc, #240] @ (800115c <HAL_LTDC_MspInit+0x24c>)
|
|
800106a: f000 fe51 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = R3_Pin|R6_Pin;
|
|
800106e: 2303 movs r3, #3
|
|
8001070: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001072: 2302 movs r3, #2
|
|
8001074: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001076: 2300 movs r3, #0
|
|
8001078: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800107a: 2300 movs r3, #0
|
|
800107c: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
|
|
800107e: 2309 movs r3, #9
|
|
8001080: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001082: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001086: 4619 mov r1, r3
|
|
8001088: 4835 ldr r0, [pc, #212] @ (8001160 <HAL_LTDC_MspInit+0x250>)
|
|
800108a: f000 fe41 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin;
|
|
800108e: f44f 6370 mov.w r3, #3840 @ 0xf00
|
|
8001092: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001094: 2302 movs r3, #2
|
|
8001096: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001098: 2300 movs r3, #0
|
|
800109a: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800109c: 2300 movs r3, #0
|
|
800109e: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
80010a0: 230e movs r3, #14
|
|
80010a2: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80010a4: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
80010a8: 4619 mov r1, r3
|
|
80010aa: 482d ldr r0, [pc, #180] @ (8001160 <HAL_LTDC_MspInit+0x250>)
|
|
80010ac: f000 fe30 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin;
|
|
80010b0: f44f 630c mov.w r3, #2240 @ 0x8c0
|
|
80010b4: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80010b6: 2302 movs r3, #2
|
|
80010b8: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80010ba: 2300 movs r3, #0
|
|
80010bc: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80010be: 2300 movs r3, #0
|
|
80010c0: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
80010c2: 230e movs r3, #14
|
|
80010c4: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
80010c6: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
80010ca: 4619 mov r1, r3
|
|
80010cc: 4825 ldr r0, [pc, #148] @ (8001164 <HAL_LTDC_MspInit+0x254>)
|
|
80010ce: f000 fe1f bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin;
|
|
80010d2: f44f 6398 mov.w r3, #1216 @ 0x4c0
|
|
80010d6: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80010d8: 2302 movs r3, #2
|
|
80010da: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80010dc: 2300 movs r3, #0
|
|
80010de: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80010e0: 2300 movs r3, #0
|
|
80010e2: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
80010e4: 230e movs r3, #14
|
|
80010e6: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80010e8: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
80010ec: 4619 mov r1, r3
|
|
80010ee: 481e ldr r0, [pc, #120] @ (8001168 <HAL_LTDC_MspInit+0x258>)
|
|
80010f0: f000 fe0e bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G7_Pin|B2_Pin;
|
|
80010f4: 2348 movs r3, #72 @ 0x48
|
|
80010f6: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80010f8: 2302 movs r3, #2
|
|
80010fa: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80010fc: 2300 movs r3, #0
|
|
80010fe: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001100: 2300 movs r3, #0
|
|
8001102: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8001104: 230e movs r3, #14
|
|
8001106: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8001108: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
800110c: 4619 mov r1, r3
|
|
800110e: 4817 ldr r0, [pc, #92] @ (800116c <HAL_LTDC_MspInit+0x25c>)
|
|
8001110: f000 fdfe bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G3_Pin|B4_Pin;
|
|
8001114: f44f 53a0 mov.w r3, #5120 @ 0x1400
|
|
8001118: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800111a: 2302 movs r3, #2
|
|
800111c: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800111e: 2300 movs r3, #0
|
|
8001120: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001122: 2300 movs r3, #0
|
|
8001124: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
|
|
8001126: 2309 movs r3, #9
|
|
8001128: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
800112a: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
800112e: 4619 mov r1, r3
|
|
8001130: 480c ldr r0, [pc, #48] @ (8001164 <HAL_LTDC_MspInit+0x254>)
|
|
8001132: f000 fded bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* LTDC interrupt Init */
|
|
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
|
|
8001136: 2200 movs r2, #0
|
|
8001138: 2105 movs r1, #5
|
|
800113a: 2058 movs r0, #88 @ 0x58
|
|
800113c: f000 fbb6 bl 80018ac <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(LTDC_IRQn);
|
|
8001140: 2058 movs r0, #88 @ 0x58
|
|
8001142: f000 fbcf bl 80018e4 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END LTDC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001146: bf00 nop
|
|
8001148: 3768 adds r7, #104 @ 0x68
|
|
800114a: 46bd mov sp, r7
|
|
800114c: bd80 pop {r7, pc}
|
|
800114e: bf00 nop
|
|
8001150: 40016800 .word 0x40016800
|
|
8001154: 40023800 .word 0x40023800
|
|
8001158: 40021400 .word 0x40021400
|
|
800115c: 40020000 .word 0x40020000
|
|
8001160: 40020400 .word 0x40020400
|
|
8001164: 40021800 .word 0x40021800
|
|
8001168: 40020800 .word 0x40020800
|
|
800116c: 40020c00 .word 0x40020c00
|
|
|
|
08001170 <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
8001170: b580 push {r7, lr}
|
|
8001172: b08a sub sp, #40 @ 0x28
|
|
8001174: af00 add r7, sp, #0
|
|
8001176: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001178: f107 0314 add.w r3, r7, #20
|
|
800117c: 2200 movs r2, #0
|
|
800117e: 601a str r2, [r3, #0]
|
|
8001180: 605a str r2, [r3, #4]
|
|
8001182: 609a str r2, [r3, #8]
|
|
8001184: 60da str r2, [r3, #12]
|
|
8001186: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI5)
|
|
8001188: 687b ldr r3, [r7, #4]
|
|
800118a: 681b ldr r3, [r3, #0]
|
|
800118c: 4a19 ldr r2, [pc, #100] @ (80011f4 <HAL_SPI_MspInit+0x84>)
|
|
800118e: 4293 cmp r3, r2
|
|
8001190: d12c bne.n 80011ec <HAL_SPI_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN SPI5_MspInit 0 */
|
|
|
|
/* USER CODE END SPI5_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI5_CLK_ENABLE();
|
|
8001192: 2300 movs r3, #0
|
|
8001194: 613b str r3, [r7, #16]
|
|
8001196: 4b18 ldr r3, [pc, #96] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
8001198: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800119a: 4a17 ldr r2, [pc, #92] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
800119c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80011a0: 6453 str r3, [r2, #68] @ 0x44
|
|
80011a2: 4b15 ldr r3, [pc, #84] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
80011a4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80011a6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80011aa: 613b str r3, [r7, #16]
|
|
80011ac: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
80011ae: 2300 movs r3, #0
|
|
80011b0: 60fb str r3, [r7, #12]
|
|
80011b2: 4b11 ldr r3, [pc, #68] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
80011b4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011b6: 4a10 ldr r2, [pc, #64] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
80011b8: f043 0320 orr.w r3, r3, #32
|
|
80011bc: 6313 str r3, [r2, #48] @ 0x30
|
|
80011be: 4b0e ldr r3, [pc, #56] @ (80011f8 <HAL_SPI_MspInit+0x88>)
|
|
80011c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011c2: f003 0320 and.w r3, r3, #32
|
|
80011c6: 60fb str r3, [r7, #12]
|
|
80011c8: 68fb ldr r3, [r7, #12]
|
|
/**SPI5 GPIO Configuration
|
|
PF7 ------> SPI5_SCK
|
|
PF8 ------> SPI5_MISO
|
|
PF9 ------> SPI5_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin;
|
|
80011ca: f44f 7360 mov.w r3, #896 @ 0x380
|
|
80011ce: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80011d0: 2302 movs r3, #2
|
|
80011d2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80011d4: 2300 movs r3, #0
|
|
80011d6: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80011d8: 2300 movs r3, #0
|
|
80011da: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
|
|
80011dc: 2305 movs r3, #5
|
|
80011de: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
80011e0: f107 0314 add.w r3, r7, #20
|
|
80011e4: 4619 mov r1, r3
|
|
80011e6: 4805 ldr r0, [pc, #20] @ (80011fc <HAL_SPI_MspInit+0x8c>)
|
|
80011e8: f000 fd92 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI5_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80011ec: bf00 nop
|
|
80011ee: 3728 adds r7, #40 @ 0x28
|
|
80011f0: 46bd mov sp, r7
|
|
80011f2: bd80 pop {r7, pc}
|
|
80011f4: 40015000 .word 0x40015000
|
|
80011f8: 40023800 .word 0x40023800
|
|
80011fc: 40021400 .word 0x40021400
|
|
|
|
08001200 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
8001200: b480 push {r7}
|
|
8001202: b085 sub sp, #20
|
|
8001204: af00 add r7, sp, #0
|
|
8001206: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM1)
|
|
8001208: 687b ldr r3, [r7, #4]
|
|
800120a: 681b ldr r3, [r3, #0]
|
|
800120c: 4a0b ldr r2, [pc, #44] @ (800123c <HAL_TIM_Base_MspInit+0x3c>)
|
|
800120e: 4293 cmp r3, r2
|
|
8001210: d10d bne.n 800122e <HAL_TIM_Base_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
8001212: 2300 movs r3, #0
|
|
8001214: 60fb str r3, [r7, #12]
|
|
8001216: 4b0a ldr r3, [pc, #40] @ (8001240 <HAL_TIM_Base_MspInit+0x40>)
|
|
8001218: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800121a: 4a09 ldr r2, [pc, #36] @ (8001240 <HAL_TIM_Base_MspInit+0x40>)
|
|
800121c: f043 0301 orr.w r3, r3, #1
|
|
8001220: 6453 str r3, [r2, #68] @ 0x44
|
|
8001222: 4b07 ldr r3, [pc, #28] @ (8001240 <HAL_TIM_Base_MspInit+0x40>)
|
|
8001224: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001226: f003 0301 and.w r3, r3, #1
|
|
800122a: 60fb str r3, [r7, #12]
|
|
800122c: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800122e: bf00 nop
|
|
8001230: 3714 adds r7, #20
|
|
8001232: 46bd mov sp, r7
|
|
8001234: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001238: 4770 bx lr
|
|
800123a: bf00 nop
|
|
800123c: 40010000 .word 0x40010000
|
|
8001240: 40023800 .word 0x40023800
|
|
|
|
08001244 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8001244: b580 push {r7, lr}
|
|
8001246: b08a sub sp, #40 @ 0x28
|
|
8001248: af00 add r7, sp, #0
|
|
800124a: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800124c: f107 0314 add.w r3, r7, #20
|
|
8001250: 2200 movs r2, #0
|
|
8001252: 601a str r2, [r3, #0]
|
|
8001254: 605a str r2, [r3, #4]
|
|
8001256: 609a str r2, [r3, #8]
|
|
8001258: 60da str r2, [r3, #12]
|
|
800125a: 611a str r2, [r3, #16]
|
|
if(huart->Instance==USART1)
|
|
800125c: 687b ldr r3, [r7, #4]
|
|
800125e: 681b ldr r3, [r3, #0]
|
|
8001260: 4a19 ldr r2, [pc, #100] @ (80012c8 <HAL_UART_MspInit+0x84>)
|
|
8001262: 4293 cmp r3, r2
|
|
8001264: d12c bne.n 80012c0 <HAL_UART_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8001266: 2300 movs r3, #0
|
|
8001268: 613b str r3, [r7, #16]
|
|
800126a: 4b18 ldr r3, [pc, #96] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
800126c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800126e: 4a17 ldr r2, [pc, #92] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
8001270: f043 0310 orr.w r3, r3, #16
|
|
8001274: 6453 str r3, [r2, #68] @ 0x44
|
|
8001276: 4b15 ldr r3, [pc, #84] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
8001278: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800127a: f003 0310 and.w r3, r3, #16
|
|
800127e: 613b str r3, [r7, #16]
|
|
8001280: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001282: 2300 movs r3, #0
|
|
8001284: 60fb str r3, [r7, #12]
|
|
8001286: 4b11 ldr r3, [pc, #68] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
8001288: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800128a: 4a10 ldr r2, [pc, #64] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
800128c: f043 0301 orr.w r3, r3, #1
|
|
8001290: 6313 str r3, [r2, #48] @ 0x30
|
|
8001292: 4b0e ldr r3, [pc, #56] @ (80012cc <HAL_UART_MspInit+0x88>)
|
|
8001294: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001296: f003 0301 and.w r3, r3, #1
|
|
800129a: 60fb str r3, [r7, #12]
|
|
800129c: 68fb ldr r3, [r7, #12]
|
|
/**USART1 GPIO Configuration
|
|
PA9 ------> USART1_TX
|
|
PA10 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
|
|
800129e: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
80012a2: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012a4: 2302 movs r3, #2
|
|
80012a6: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012a8: 2300 movs r3, #0
|
|
80012aa: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012ac: 2303 movs r3, #3
|
|
80012ae: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
80012b0: 2307 movs r3, #7
|
|
80012b2: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80012b4: f107 0314 add.w r3, r7, #20
|
|
80012b8: 4619 mov r1, r3
|
|
80012ba: 4805 ldr r0, [pc, #20] @ (80012d0 <HAL_UART_MspInit+0x8c>)
|
|
80012bc: f000 fd28 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80012c0: bf00 nop
|
|
80012c2: 3728 adds r7, #40 @ 0x28
|
|
80012c4: 46bd mov sp, r7
|
|
80012c6: bd80 pop {r7, pc}
|
|
80012c8: 40011000 .word 0x40011000
|
|
80012cc: 40023800 .word 0x40023800
|
|
80012d0: 40020000 .word 0x40020000
|
|
|
|
080012d4 <HAL_FMC_MspInit>:
|
|
|
|
}
|
|
|
|
static uint32_t FMC_Initialized = 0;
|
|
|
|
static void HAL_FMC_MspInit(void){
|
|
80012d4: b580 push {r7, lr}
|
|
80012d6: b086 sub sp, #24
|
|
80012d8: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN FMC_MspInit 0 */
|
|
|
|
/* USER CODE END FMC_MspInit 0 */
|
|
GPIO_InitTypeDef GPIO_InitStruct ={0};
|
|
80012da: 1d3b adds r3, r7, #4
|
|
80012dc: 2200 movs r2, #0
|
|
80012de: 601a str r2, [r3, #0]
|
|
80012e0: 605a str r2, [r3, #4]
|
|
80012e2: 609a str r2, [r3, #8]
|
|
80012e4: 60da str r2, [r3, #12]
|
|
80012e6: 611a str r2, [r3, #16]
|
|
if (FMC_Initialized) {
|
|
80012e8: 4b3b ldr r3, [pc, #236] @ (80013d8 <HAL_FMC_MspInit+0x104>)
|
|
80012ea: 681b ldr r3, [r3, #0]
|
|
80012ec: 2b00 cmp r3, #0
|
|
80012ee: d16f bne.n 80013d0 <HAL_FMC_MspInit+0xfc>
|
|
return;
|
|
}
|
|
FMC_Initialized = 1;
|
|
80012f0: 4b39 ldr r3, [pc, #228] @ (80013d8 <HAL_FMC_MspInit+0x104>)
|
|
80012f2: 2201 movs r2, #1
|
|
80012f4: 601a str r2, [r3, #0]
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_FMC_CLK_ENABLE();
|
|
80012f6: 2300 movs r3, #0
|
|
80012f8: 603b str r3, [r7, #0]
|
|
80012fa: 4b38 ldr r3, [pc, #224] @ (80013dc <HAL_FMC_MspInit+0x108>)
|
|
80012fc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80012fe: 4a37 ldr r2, [pc, #220] @ (80013dc <HAL_FMC_MspInit+0x108>)
|
|
8001300: f043 0301 orr.w r3, r3, #1
|
|
8001304: 6393 str r3, [r2, #56] @ 0x38
|
|
8001306: 4b35 ldr r3, [pc, #212] @ (80013dc <HAL_FMC_MspInit+0x108>)
|
|
8001308: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800130a: f003 0301 and.w r3, r3, #1
|
|
800130e: 603b str r3, [r7, #0]
|
|
8001310: 683b ldr r3, [r7, #0]
|
|
PB5 ------> FMC_SDCKE1
|
|
PB6 ------> FMC_SDNE1
|
|
PE0 ------> FMC_NBL0
|
|
PE1 ------> FMC_NBL1
|
|
*/
|
|
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
|
|
8001312: f64f 033f movw r3, #63551 @ 0xf83f
|
|
8001316: 607b str r3, [r7, #4]
|
|
|A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin
|
|
|A7_Pin|A8_Pin|A9_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001318: 2302 movs r3, #2
|
|
800131a: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800131c: 2300 movs r3, #0
|
|
800131e: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001320: 2303 movs r3, #3
|
|
8001322: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8001324: 230c movs r3, #12
|
|
8001326: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
8001328: 1d3b adds r3, r7, #4
|
|
800132a: 4619 mov r1, r3
|
|
800132c: 482c ldr r0, [pc, #176] @ (80013e0 <HAL_FMC_MspInit+0x10c>)
|
|
800132e: f000 fcef bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = SDNWE_Pin;
|
|
8001332: 2301 movs r3, #1
|
|
8001334: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001336: 2302 movs r3, #2
|
|
8001338: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800133a: 2300 movs r3, #0
|
|
800133c: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800133e: 2303 movs r3, #3
|
|
8001340: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8001342: 230c movs r3, #12
|
|
8001344: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
|
|
8001346: 1d3b adds r3, r7, #4
|
|
8001348: 4619 mov r1, r3
|
|
800134a: 4826 ldr r0, [pc, #152] @ (80013e4 <HAL_FMC_MspInit+0x110>)
|
|
800134c: f000 fce0 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin
|
|
8001350: f248 1333 movw r3, #33075 @ 0x8133
|
|
8001354: 607b str r3, [r7, #4]
|
|
|SDCLK_Pin|SDNCAS_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001356: 2302 movs r3, #2
|
|
8001358: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800135a: 2300 movs r3, #0
|
|
800135c: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800135e: 2303 movs r3, #3
|
|
8001360: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8001362: 230c movs r3, #12
|
|
8001364: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8001366: 1d3b adds r3, r7, #4
|
|
8001368: 4619 mov r1, r3
|
|
800136a: 481f ldr r0, [pc, #124] @ (80013e8 <HAL_FMC_MspInit+0x114>)
|
|
800136c: f000 fcd0 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin
|
|
8001370: f64f 7383 movw r3, #65411 @ 0xff83
|
|
8001374: 607b str r3, [r7, #4]
|
|
|D8_Pin|D9_Pin|D10_Pin|D11_Pin
|
|
|D12_Pin|NBL0_Pin|NBL1_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001376: 2302 movs r3, #2
|
|
8001378: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800137a: 2300 movs r3, #0
|
|
800137c: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800137e: 2303 movs r3, #3
|
|
8001380: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8001382: 230c movs r3, #12
|
|
8001384: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
8001386: 1d3b adds r3, r7, #4
|
|
8001388: 4619 mov r1, r3
|
|
800138a: 4818 ldr r0, [pc, #96] @ (80013ec <HAL_FMC_MspInit+0x118>)
|
|
800138c: f000 fcc0 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin
|
|
8001390: f24c 7303 movw r3, #50947 @ 0xc703
|
|
8001394: 607b str r3, [r7, #4]
|
|
|D1_Pin|D2_Pin|D3_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001396: 2302 movs r3, #2
|
|
8001398: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800139a: 2300 movs r3, #0
|
|
800139c: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800139e: 2303 movs r3, #3
|
|
80013a0: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
80013a2: 230c movs r3, #12
|
|
80013a4: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
80013a6: 1d3b adds r3, r7, #4
|
|
80013a8: 4619 mov r1, r3
|
|
80013aa: 4811 ldr r0, [pc, #68] @ (80013f0 <HAL_FMC_MspInit+0x11c>)
|
|
80013ac: f000 fcb0 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin;
|
|
80013b0: 2360 movs r3, #96 @ 0x60
|
|
80013b2: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80013b4: 2302 movs r3, #2
|
|
80013b6: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80013b8: 2300 movs r3, #0
|
|
80013ba: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80013bc: 2303 movs r3, #3
|
|
80013be: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
80013c0: 230c movs r3, #12
|
|
80013c2: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80013c4: 1d3b adds r3, r7, #4
|
|
80013c6: 4619 mov r1, r3
|
|
80013c8: 480a ldr r0, [pc, #40] @ (80013f4 <HAL_FMC_MspInit+0x120>)
|
|
80013ca: f000 fca1 bl 8001d10 <HAL_GPIO_Init>
|
|
80013ce: e000 b.n 80013d2 <HAL_FMC_MspInit+0xfe>
|
|
return;
|
|
80013d0: bf00 nop
|
|
|
|
/* USER CODE BEGIN FMC_MspInit 1 */
|
|
|
|
/* USER CODE END FMC_MspInit 1 */
|
|
}
|
|
80013d2: 3718 adds r7, #24
|
|
80013d4: 46bd mov sp, r7
|
|
80013d6: bd80 pop {r7, pc}
|
|
80013d8: 20000558 .word 0x20000558
|
|
80013dc: 40023800 .word 0x40023800
|
|
80013e0: 40021400 .word 0x40021400
|
|
80013e4: 40020800 .word 0x40020800
|
|
80013e8: 40021800 .word 0x40021800
|
|
80013ec: 40021000 .word 0x40021000
|
|
80013f0: 40020c00 .word 0x40020c00
|
|
80013f4: 40020400 .word 0x40020400
|
|
|
|
080013f8 <HAL_SDRAM_MspInit>:
|
|
|
|
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
|
|
80013f8: b580 push {r7, lr}
|
|
80013fa: b082 sub sp, #8
|
|
80013fc: af00 add r7, sp, #0
|
|
80013fe: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN SDRAM_MspInit 0 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 0 */
|
|
HAL_FMC_MspInit();
|
|
8001400: f7ff ff68 bl 80012d4 <HAL_FMC_MspInit>
|
|
/* USER CODE BEGIN SDRAM_MspInit 1 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 1 */
|
|
}
|
|
8001404: bf00 nop
|
|
8001406: 3708 adds r7, #8
|
|
8001408: 46bd mov sp, r7
|
|
800140a: bd80 pop {r7, pc}
|
|
|
|
0800140c <HAL_InitTick>:
|
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
800140c: b580 push {r7, lr}
|
|
800140e: b08e sub sp, #56 @ 0x38
|
|
8001410: af00 add r7, sp, #0
|
|
8001412: 6078 str r0, [r7, #4]
|
|
RCC_ClkInitTypeDef clkconfig;
|
|
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
|
|
8001414: 2300 movs r3, #0
|
|
8001416: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
uint32_t uwPrescalerValue = 0U;
|
|
8001418: 2300 movs r3, #0
|
|
800141a: 62bb str r3, [r7, #40] @ 0x28
|
|
uint32_t pFLatency;
|
|
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Enable TIM6 clock */
|
|
__HAL_RCC_TIM6_CLK_ENABLE();
|
|
800141c: 2300 movs r3, #0
|
|
800141e: 60fb str r3, [r7, #12]
|
|
8001420: 4b33 ldr r3, [pc, #204] @ (80014f0 <HAL_InitTick+0xe4>)
|
|
8001422: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001424: 4a32 ldr r2, [pc, #200] @ (80014f0 <HAL_InitTick+0xe4>)
|
|
8001426: f043 0310 orr.w r3, r3, #16
|
|
800142a: 6413 str r3, [r2, #64] @ 0x40
|
|
800142c: 4b30 ldr r3, [pc, #192] @ (80014f0 <HAL_InitTick+0xe4>)
|
|
800142e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001430: f003 0310 and.w r3, r3, #16
|
|
8001434: 60fb str r3, [r7, #12]
|
|
8001436: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Get clock configuration */
|
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
|
8001438: f107 0210 add.w r2, r7, #16
|
|
800143c: f107 0314 add.w r3, r7, #20
|
|
8001440: 4611 mov r1, r2
|
|
8001442: 4618 mov r0, r3
|
|
8001444: f004 f8bc bl 80055c0 <HAL_RCC_GetClockConfig>
|
|
|
|
/* Get APB1 prescaler */
|
|
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
|
|
8001448: 6a3b ldr r3, [r7, #32]
|
|
800144a: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Compute TIM6 clock */
|
|
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
|
|
800144c: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800144e: 2b00 cmp r3, #0
|
|
8001450: d103 bne.n 800145a <HAL_InitTick+0x4e>
|
|
{
|
|
uwTimclock = HAL_RCC_GetPCLK1Freq();
|
|
8001452: f004 f88d bl 8005570 <HAL_RCC_GetPCLK1Freq>
|
|
8001456: 6378 str r0, [r7, #52] @ 0x34
|
|
8001458: e004 b.n 8001464 <HAL_InitTick+0x58>
|
|
}
|
|
else
|
|
{
|
|
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
|
|
800145a: f004 f889 bl 8005570 <HAL_RCC_GetPCLK1Freq>
|
|
800145e: 4603 mov r3, r0
|
|
8001460: 005b lsls r3, r3, #1
|
|
8001462: 637b str r3, [r7, #52] @ 0x34
|
|
}
|
|
|
|
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
|
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
|
8001464: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8001466: 4a23 ldr r2, [pc, #140] @ (80014f4 <HAL_InitTick+0xe8>)
|
|
8001468: fba2 2303 umull r2, r3, r2, r3
|
|
800146c: 0c9b lsrs r3, r3, #18
|
|
800146e: 3b01 subs r3, #1
|
|
8001470: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Initialize TIM6 */
|
|
htim6.Instance = TIM6;
|
|
8001472: 4b21 ldr r3, [pc, #132] @ (80014f8 <HAL_InitTick+0xec>)
|
|
8001474: 4a21 ldr r2, [pc, #132] @ (80014fc <HAL_InitTick+0xf0>)
|
|
8001476: 601a str r2, [r3, #0]
|
|
* Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
|
|
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
|
* ClockDivision = 0
|
|
* Counter direction = Up
|
|
*/
|
|
htim6.Init.Period = (1000000U / 1000U) - 1U;
|
|
8001478: 4b1f ldr r3, [pc, #124] @ (80014f8 <HAL_InitTick+0xec>)
|
|
800147a: f240 32e7 movw r2, #999 @ 0x3e7
|
|
800147e: 60da str r2, [r3, #12]
|
|
htim6.Init.Prescaler = uwPrescalerValue;
|
|
8001480: 4a1d ldr r2, [pc, #116] @ (80014f8 <HAL_InitTick+0xec>)
|
|
8001482: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8001484: 6053 str r3, [r2, #4]
|
|
htim6.Init.ClockDivision = 0;
|
|
8001486: 4b1c ldr r3, [pc, #112] @ (80014f8 <HAL_InitTick+0xec>)
|
|
8001488: 2200 movs r2, #0
|
|
800148a: 611a str r2, [r3, #16]
|
|
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
800148c: 4b1a ldr r3, [pc, #104] @ (80014f8 <HAL_InitTick+0xec>)
|
|
800148e: 2200 movs r2, #0
|
|
8001490: 609a str r2, [r3, #8]
|
|
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001492: 4b19 ldr r3, [pc, #100] @ (80014f8 <HAL_InitTick+0xec>)
|
|
8001494: 2200 movs r2, #0
|
|
8001496: 619a str r2, [r3, #24]
|
|
|
|
status = HAL_TIM_Base_Init(&htim6);
|
|
8001498: 4817 ldr r0, [pc, #92] @ (80014f8 <HAL_InitTick+0xec>)
|
|
800149a: f004 fb40 bl 8005b1e <HAL_TIM_Base_Init>
|
|
800149e: 4603 mov r3, r0
|
|
80014a0: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
if (status == HAL_OK)
|
|
80014a4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
80014a8: 2b00 cmp r3, #0
|
|
80014aa: d11b bne.n 80014e4 <HAL_InitTick+0xd8>
|
|
{
|
|
/* Start the TIM time Base generation in interrupt mode */
|
|
status = HAL_TIM_Base_Start_IT(&htim6);
|
|
80014ac: 4812 ldr r0, [pc, #72] @ (80014f8 <HAL_InitTick+0xec>)
|
|
80014ae: f004 fb85 bl 8005bbc <HAL_TIM_Base_Start_IT>
|
|
80014b2: 4603 mov r3, r0
|
|
80014b4: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
if (status == HAL_OK)
|
|
80014b8: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
80014bc: 2b00 cmp r3, #0
|
|
80014be: d111 bne.n 80014e4 <HAL_InitTick+0xd8>
|
|
{
|
|
/* Enable the TIM6 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
|
80014c0: 2036 movs r0, #54 @ 0x36
|
|
80014c2: f000 fa0f bl 80018e4 <HAL_NVIC_EnableIRQ>
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80014c6: 687b ldr r3, [r7, #4]
|
|
80014c8: 2b0f cmp r3, #15
|
|
80014ca: d808 bhi.n 80014de <HAL_InitTick+0xd2>
|
|
{
|
|
/* Configure the TIM IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
|
|
80014cc: 2200 movs r2, #0
|
|
80014ce: 6879 ldr r1, [r7, #4]
|
|
80014d0: 2036 movs r0, #54 @ 0x36
|
|
80014d2: f000 f9eb bl 80018ac <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80014d6: 4a0a ldr r2, [pc, #40] @ (8001500 <HAL_InitTick+0xf4>)
|
|
80014d8: 687b ldr r3, [r7, #4]
|
|
80014da: 6013 str r3, [r2, #0]
|
|
80014dc: e002 b.n 80014e4 <HAL_InitTick+0xd8>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
80014de: 2301 movs r3, #1
|
|
80014e0: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80014e4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
}
|
|
80014e8: 4618 mov r0, r3
|
|
80014ea: 3738 adds r7, #56 @ 0x38
|
|
80014ec: 46bd mov sp, r7
|
|
80014ee: bd80 pop {r7, pc}
|
|
80014f0: 40023800 .word 0x40023800
|
|
80014f4: 431bde83 .word 0x431bde83
|
|
80014f8: 2000055c .word 0x2000055c
|
|
80014fc: 40001000 .word 0x40001000
|
|
8001500: 20000004 .word 0x20000004
|
|
|
|
08001504 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8001504: b480 push {r7}
|
|
8001506: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001508: bf00 nop
|
|
800150a: e7fd b.n 8001508 <NMI_Handler+0x4>
|
|
|
|
0800150c <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800150c: b480 push {r7}
|
|
800150e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8001510: bf00 nop
|
|
8001512: e7fd b.n 8001510 <HardFault_Handler+0x4>
|
|
|
|
08001514 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8001514: b480 push {r7}
|
|
8001516: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8001518: bf00 nop
|
|
800151a: e7fd b.n 8001518 <MemManage_Handler+0x4>
|
|
|
|
0800151c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800151c: b480 push {r7}
|
|
800151e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8001520: bf00 nop
|
|
8001522: e7fd b.n 8001520 <BusFault_Handler+0x4>
|
|
|
|
08001524 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8001524: b480 push {r7}
|
|
8001526: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8001528: bf00 nop
|
|
800152a: e7fd b.n 8001528 <UsageFault_Handler+0x4>
|
|
|
|
0800152c <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800152c: b480 push {r7}
|
|
800152e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
8001530: bf00 nop
|
|
8001532: 46bd mov sp, r7
|
|
8001534: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001538: 4770 bx lr
|
|
...
|
|
|
|
0800153c <TIM6_DAC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
|
|
*/
|
|
void TIM6_DAC_IRQHandler(void)
|
|
{
|
|
800153c: b580 push {r7, lr}
|
|
800153e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim6);
|
|
8001540: 4802 ldr r0, [pc, #8] @ (800154c <TIM6_DAC_IRQHandler+0x10>)
|
|
8001542: f004 fbab bl 8005c9c <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 1 */
|
|
}
|
|
8001546: bf00 nop
|
|
8001548: bd80 pop {r7, pc}
|
|
800154a: bf00 nop
|
|
800154c: 2000055c .word 0x2000055c
|
|
|
|
08001550 <OTG_HS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go HS global interrupt.
|
|
*/
|
|
void OTG_HS_IRQHandler(void)
|
|
{
|
|
8001550: b580 push {r7, lr}
|
|
8001552: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_HS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_HS_IRQn 0 */
|
|
HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS);
|
|
8001554: 4802 ldr r0, [pc, #8] @ (8001560 <OTG_HS_IRQHandler+0x10>)
|
|
8001556: f001 f877 bl 8002648 <HAL_HCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_HS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_HS_IRQn 1 */
|
|
}
|
|
800155a: bf00 nop
|
|
800155c: bd80 pop {r7, pc}
|
|
800155e: bf00 nop
|
|
8001560: 20008ae8 .word 0x20008ae8
|
|
|
|
08001564 <LTDC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles LTDC global interrupt.
|
|
*/
|
|
void LTDC_IRQHandler(void)
|
|
{
|
|
8001564: b580 push {r7, lr}
|
|
8001566: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN LTDC_IRQn 0 */
|
|
|
|
/* USER CODE END LTDC_IRQn 0 */
|
|
HAL_LTDC_IRQHandler(&hltdc);
|
|
8001568: 4802 ldr r0, [pc, #8] @ (8001574 <LTDC_IRQHandler+0x10>)
|
|
800156a: f003 f91d bl 80047a8 <HAL_LTDC_IRQHandler>
|
|
/* USER CODE BEGIN LTDC_IRQn 1 */
|
|
|
|
/* USER CODE END LTDC_IRQn 1 */
|
|
}
|
|
800156e: bf00 nop
|
|
8001570: bd80 pop {r7, pc}
|
|
8001572: bf00 nop
|
|
8001574: 20000390 .word 0x20000390
|
|
|
|
08001578 <DMA2D_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2D global interrupt.
|
|
*/
|
|
void DMA2D_IRQHandler(void)
|
|
{
|
|
8001578: b580 push {r7, lr}
|
|
800157a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2D_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2D_IRQn 0 */
|
|
HAL_DMA2D_IRQHandler(&hdma2d);
|
|
800157c: 4802 ldr r0, [pc, #8] @ (8001588 <DMA2D_IRQHandler+0x10>)
|
|
800157e: f000 fa24 bl 80019ca <HAL_DMA2D_IRQHandler>
|
|
/* USER CODE BEGIN DMA2D_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2D_IRQn 1 */
|
|
}
|
|
8001582: bf00 nop
|
|
8001584: bd80 pop {r7, pc}
|
|
8001586: bf00 nop
|
|
8001588: 200002fc .word 0x200002fc
|
|
|
|
0800158c <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
800158c: b580 push {r7, lr}
|
|
800158e: b086 sub sp, #24
|
|
8001590: af00 add r7, sp, #0
|
|
8001592: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
8001594: 4a14 ldr r2, [pc, #80] @ (80015e8 <_sbrk+0x5c>)
|
|
8001596: 4b15 ldr r3, [pc, #84] @ (80015ec <_sbrk+0x60>)
|
|
8001598: 1ad3 subs r3, r2, r3
|
|
800159a: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
800159c: 697b ldr r3, [r7, #20]
|
|
800159e: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
80015a0: 4b13 ldr r3, [pc, #76] @ (80015f0 <_sbrk+0x64>)
|
|
80015a2: 681b ldr r3, [r3, #0]
|
|
80015a4: 2b00 cmp r3, #0
|
|
80015a6: d102 bne.n 80015ae <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
80015a8: 4b11 ldr r3, [pc, #68] @ (80015f0 <_sbrk+0x64>)
|
|
80015aa: 4a12 ldr r2, [pc, #72] @ (80015f4 <_sbrk+0x68>)
|
|
80015ac: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
80015ae: 4b10 ldr r3, [pc, #64] @ (80015f0 <_sbrk+0x64>)
|
|
80015b0: 681a ldr r2, [r3, #0]
|
|
80015b2: 687b ldr r3, [r7, #4]
|
|
80015b4: 4413 add r3, r2
|
|
80015b6: 693a ldr r2, [r7, #16]
|
|
80015b8: 429a cmp r2, r3
|
|
80015ba: d207 bcs.n 80015cc <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
80015bc: f00b fce0 bl 800cf80 <__errno>
|
|
80015c0: 4603 mov r3, r0
|
|
80015c2: 220c movs r2, #12
|
|
80015c4: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
80015c6: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80015ca: e009 b.n 80015e0 <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
80015cc: 4b08 ldr r3, [pc, #32] @ (80015f0 <_sbrk+0x64>)
|
|
80015ce: 681b ldr r3, [r3, #0]
|
|
80015d0: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
80015d2: 4b07 ldr r3, [pc, #28] @ (80015f0 <_sbrk+0x64>)
|
|
80015d4: 681a ldr r2, [r3, #0]
|
|
80015d6: 687b ldr r3, [r7, #4]
|
|
80015d8: 4413 add r3, r2
|
|
80015da: 4a05 ldr r2, [pc, #20] @ (80015f0 <_sbrk+0x64>)
|
|
80015dc: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80015de: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80015e0: 4618 mov r0, r3
|
|
80015e2: 3718 adds r7, #24
|
|
80015e4: 46bd mov sp, r7
|
|
80015e6: bd80 pop {r7, pc}
|
|
80015e8: 20030000 .word 0x20030000
|
|
80015ec: 00000400 .word 0x00000400
|
|
80015f0: 200005a4 .word 0x200005a4
|
|
80015f4: 20009010 .word 0x20009010
|
|
|
|
080015f8 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80015f8: b480 push {r7}
|
|
80015fa: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80015fc: 4b06 ldr r3, [pc, #24] @ (8001618 <SystemInit+0x20>)
|
|
80015fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001602: 4a05 ldr r2, [pc, #20] @ (8001618 <SystemInit+0x20>)
|
|
8001604: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001608: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
800160c: bf00 nop
|
|
800160e: 46bd mov sp, r7
|
|
8001610: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001614: 4770 bx lr
|
|
8001616: bf00 nop
|
|
8001618: e000ed00 .word 0xe000ed00
|
|
|
|
0800161c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
800161c: f8df d034 ldr.w sp, [pc, #52] @ 8001654 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001620: f7ff ffea bl 80015f8 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001624: 480c ldr r0, [pc, #48] @ (8001658 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001626: 490d ldr r1, [pc, #52] @ (800165c <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001628: 4a0d ldr r2, [pc, #52] @ (8001660 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
800162a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800162c: e002 b.n 8001634 <LoopCopyDataInit>
|
|
|
|
0800162e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800162e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001630: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001632: 3304 adds r3, #4
|
|
|
|
08001634 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001634: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001636: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001638: d3f9 bcc.n 800162e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800163a: 4a0a ldr r2, [pc, #40] @ (8001664 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
800163c: 4c0a ldr r4, [pc, #40] @ (8001668 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
800163e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001640: e001 b.n 8001646 <LoopFillZerobss>
|
|
|
|
08001642 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001642: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001644: 3204 adds r2, #4
|
|
|
|
08001646 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001646: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001648: d3fb bcc.n 8001642 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800164a: f00b fc9f bl 800cf8c <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800164e: f7fe ff99 bl 8000584 <main>
|
|
bx lr
|
|
8001652: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001654: 20030000 .word 0x20030000
|
|
ldr r0, =_sdata
|
|
8001658: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800165c: 20000080 .word 0x20000080
|
|
ldr r2, =_sidata
|
|
8001660: 0800d134 .word 0x0800d134
|
|
ldr r2, =_sbss
|
|
8001664: 20000080 .word 0x20000080
|
|
ldr r4, =_ebss
|
|
8001668: 20009010 .word 0x20009010
|
|
|
|
0800166c <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800166c: e7fe b.n 800166c <ADC_IRQHandler>
|
|
...
|
|
|
|
08001670 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001670: b580 push {r7, lr}
|
|
8001672: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001674: 4b0e ldr r3, [pc, #56] @ (80016b0 <HAL_Init+0x40>)
|
|
8001676: 681b ldr r3, [r3, #0]
|
|
8001678: 4a0d ldr r2, [pc, #52] @ (80016b0 <HAL_Init+0x40>)
|
|
800167a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800167e: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8001680: 4b0b ldr r3, [pc, #44] @ (80016b0 <HAL_Init+0x40>)
|
|
8001682: 681b ldr r3, [r3, #0]
|
|
8001684: 4a0a ldr r2, [pc, #40] @ (80016b0 <HAL_Init+0x40>)
|
|
8001686: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800168a: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
800168c: 4b08 ldr r3, [pc, #32] @ (80016b0 <HAL_Init+0x40>)
|
|
800168e: 681b ldr r3, [r3, #0]
|
|
8001690: 4a07 ldr r2, [pc, #28] @ (80016b0 <HAL_Init+0x40>)
|
|
8001692: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001696: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001698: 2003 movs r0, #3
|
|
800169a: f000 f8fc bl 8001896 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800169e: 2000 movs r0, #0
|
|
80016a0: f7ff feb4 bl 800140c <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80016a4: f7ff fb54 bl 8000d50 <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80016a8: 2300 movs r3, #0
|
|
}
|
|
80016aa: 4618 mov r0, r3
|
|
80016ac: bd80 pop {r7, pc}
|
|
80016ae: bf00 nop
|
|
80016b0: 40023c00 .word 0x40023c00
|
|
|
|
080016b4 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80016b4: b480 push {r7}
|
|
80016b6: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80016b8: 4b06 ldr r3, [pc, #24] @ (80016d4 <HAL_IncTick+0x20>)
|
|
80016ba: 781b ldrb r3, [r3, #0]
|
|
80016bc: 461a mov r2, r3
|
|
80016be: 4b06 ldr r3, [pc, #24] @ (80016d8 <HAL_IncTick+0x24>)
|
|
80016c0: 681b ldr r3, [r3, #0]
|
|
80016c2: 4413 add r3, r2
|
|
80016c4: 4a04 ldr r2, [pc, #16] @ (80016d8 <HAL_IncTick+0x24>)
|
|
80016c6: 6013 str r3, [r2, #0]
|
|
}
|
|
80016c8: bf00 nop
|
|
80016ca: 46bd mov sp, r7
|
|
80016cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016d0: 4770 bx lr
|
|
80016d2: bf00 nop
|
|
80016d4: 20000008 .word 0x20000008
|
|
80016d8: 200005a8 .word 0x200005a8
|
|
|
|
080016dc <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80016dc: b480 push {r7}
|
|
80016de: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80016e0: 4b03 ldr r3, [pc, #12] @ (80016f0 <HAL_GetTick+0x14>)
|
|
80016e2: 681b ldr r3, [r3, #0]
|
|
}
|
|
80016e4: 4618 mov r0, r3
|
|
80016e6: 46bd mov sp, r7
|
|
80016e8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016ec: 4770 bx lr
|
|
80016ee: bf00 nop
|
|
80016f0: 200005a8 .word 0x200005a8
|
|
|
|
080016f4 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
80016f4: b580 push {r7, lr}
|
|
80016f6: b084 sub sp, #16
|
|
80016f8: af00 add r7, sp, #0
|
|
80016fa: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
80016fc: f7ff ffee bl 80016dc <HAL_GetTick>
|
|
8001700: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001702: 687b ldr r3, [r7, #4]
|
|
8001704: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001706: 68fb ldr r3, [r7, #12]
|
|
8001708: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800170c: d005 beq.n 800171a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800170e: 4b0a ldr r3, [pc, #40] @ (8001738 <HAL_Delay+0x44>)
|
|
8001710: 781b ldrb r3, [r3, #0]
|
|
8001712: 461a mov r2, r3
|
|
8001714: 68fb ldr r3, [r7, #12]
|
|
8001716: 4413 add r3, r2
|
|
8001718: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
800171a: bf00 nop
|
|
800171c: f7ff ffde bl 80016dc <HAL_GetTick>
|
|
8001720: 4602 mov r2, r0
|
|
8001722: 68bb ldr r3, [r7, #8]
|
|
8001724: 1ad3 subs r3, r2, r3
|
|
8001726: 68fa ldr r2, [r7, #12]
|
|
8001728: 429a cmp r2, r3
|
|
800172a: d8f7 bhi.n 800171c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
800172c: bf00 nop
|
|
800172e: bf00 nop
|
|
8001730: 3710 adds r7, #16
|
|
8001732: 46bd mov sp, r7
|
|
8001734: bd80 pop {r7, pc}
|
|
8001736: bf00 nop
|
|
8001738: 20000008 .word 0x20000008
|
|
|
|
0800173c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800173c: b480 push {r7}
|
|
800173e: b085 sub sp, #20
|
|
8001740: af00 add r7, sp, #0
|
|
8001742: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001744: 687b ldr r3, [r7, #4]
|
|
8001746: f003 0307 and.w r3, r3, #7
|
|
800174a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
800174c: 4b0c ldr r3, [pc, #48] @ (8001780 <__NVIC_SetPriorityGrouping+0x44>)
|
|
800174e: 68db ldr r3, [r3, #12]
|
|
8001750: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8001752: 68ba ldr r2, [r7, #8]
|
|
8001754: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001758: 4013 ands r3, r2
|
|
800175a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
800175c: 68fb ldr r3, [r7, #12]
|
|
800175e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8001760: 68bb ldr r3, [r7, #8]
|
|
8001762: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8001764: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8001768: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
800176c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
800176e: 4a04 ldr r2, [pc, #16] @ (8001780 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001770: 68bb ldr r3, [r7, #8]
|
|
8001772: 60d3 str r3, [r2, #12]
|
|
}
|
|
8001774: bf00 nop
|
|
8001776: 3714 adds r7, #20
|
|
8001778: 46bd mov sp, r7
|
|
800177a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800177e: 4770 bx lr
|
|
8001780: e000ed00 .word 0xe000ed00
|
|
|
|
08001784 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8001784: b480 push {r7}
|
|
8001786: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001788: 4b04 ldr r3, [pc, #16] @ (800179c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800178a: 68db ldr r3, [r3, #12]
|
|
800178c: 0a1b lsrs r3, r3, #8
|
|
800178e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8001792: 4618 mov r0, r3
|
|
8001794: 46bd mov sp, r7
|
|
8001796: f85d 7b04 ldr.w r7, [sp], #4
|
|
800179a: 4770 bx lr
|
|
800179c: e000ed00 .word 0xe000ed00
|
|
|
|
080017a0 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80017a0: b480 push {r7}
|
|
80017a2: b083 sub sp, #12
|
|
80017a4: af00 add r7, sp, #0
|
|
80017a6: 4603 mov r3, r0
|
|
80017a8: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80017aa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80017ae: 2b00 cmp r3, #0
|
|
80017b0: db0b blt.n 80017ca <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80017b2: 79fb ldrb r3, [r7, #7]
|
|
80017b4: f003 021f and.w r2, r3, #31
|
|
80017b8: 4907 ldr r1, [pc, #28] @ (80017d8 <__NVIC_EnableIRQ+0x38>)
|
|
80017ba: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80017be: 095b lsrs r3, r3, #5
|
|
80017c0: 2001 movs r0, #1
|
|
80017c2: fa00 f202 lsl.w r2, r0, r2
|
|
80017c6: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
80017ca: bf00 nop
|
|
80017cc: 370c adds r7, #12
|
|
80017ce: 46bd mov sp, r7
|
|
80017d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80017d4: 4770 bx lr
|
|
80017d6: bf00 nop
|
|
80017d8: e000e100 .word 0xe000e100
|
|
|
|
080017dc <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
80017dc: b480 push {r7}
|
|
80017de: b083 sub sp, #12
|
|
80017e0: af00 add r7, sp, #0
|
|
80017e2: 4603 mov r3, r0
|
|
80017e4: 6039 str r1, [r7, #0]
|
|
80017e6: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80017e8: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80017ec: 2b00 cmp r3, #0
|
|
80017ee: db0a blt.n 8001806 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80017f0: 683b ldr r3, [r7, #0]
|
|
80017f2: b2da uxtb r2, r3
|
|
80017f4: 490c ldr r1, [pc, #48] @ (8001828 <__NVIC_SetPriority+0x4c>)
|
|
80017f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80017fa: 0112 lsls r2, r2, #4
|
|
80017fc: b2d2 uxtb r2, r2
|
|
80017fe: 440b add r3, r1
|
|
8001800: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001804: e00a b.n 800181c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001806: 683b ldr r3, [r7, #0]
|
|
8001808: b2da uxtb r2, r3
|
|
800180a: 4908 ldr r1, [pc, #32] @ (800182c <__NVIC_SetPriority+0x50>)
|
|
800180c: 79fb ldrb r3, [r7, #7]
|
|
800180e: f003 030f and.w r3, r3, #15
|
|
8001812: 3b04 subs r3, #4
|
|
8001814: 0112 lsls r2, r2, #4
|
|
8001816: b2d2 uxtb r2, r2
|
|
8001818: 440b add r3, r1
|
|
800181a: 761a strb r2, [r3, #24]
|
|
}
|
|
800181c: bf00 nop
|
|
800181e: 370c adds r7, #12
|
|
8001820: 46bd mov sp, r7
|
|
8001822: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001826: 4770 bx lr
|
|
8001828: e000e100 .word 0xe000e100
|
|
800182c: e000ed00 .word 0xe000ed00
|
|
|
|
08001830 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001830: b480 push {r7}
|
|
8001832: b089 sub sp, #36 @ 0x24
|
|
8001834: af00 add r7, sp, #0
|
|
8001836: 60f8 str r0, [r7, #12]
|
|
8001838: 60b9 str r1, [r7, #8]
|
|
800183a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800183c: 68fb ldr r3, [r7, #12]
|
|
800183e: f003 0307 and.w r3, r3, #7
|
|
8001842: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001844: 69fb ldr r3, [r7, #28]
|
|
8001846: f1c3 0307 rsb r3, r3, #7
|
|
800184a: 2b04 cmp r3, #4
|
|
800184c: bf28 it cs
|
|
800184e: 2304 movcs r3, #4
|
|
8001850: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8001852: 69fb ldr r3, [r7, #28]
|
|
8001854: 3304 adds r3, #4
|
|
8001856: 2b06 cmp r3, #6
|
|
8001858: d902 bls.n 8001860 <NVIC_EncodePriority+0x30>
|
|
800185a: 69fb ldr r3, [r7, #28]
|
|
800185c: 3b03 subs r3, #3
|
|
800185e: e000 b.n 8001862 <NVIC_EncodePriority+0x32>
|
|
8001860: 2300 movs r3, #0
|
|
8001862: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001864: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8001868: 69bb ldr r3, [r7, #24]
|
|
800186a: fa02 f303 lsl.w r3, r2, r3
|
|
800186e: 43da mvns r2, r3
|
|
8001870: 68bb ldr r3, [r7, #8]
|
|
8001872: 401a ands r2, r3
|
|
8001874: 697b ldr r3, [r7, #20]
|
|
8001876: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8001878: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
800187c: 697b ldr r3, [r7, #20]
|
|
800187e: fa01 f303 lsl.w r3, r1, r3
|
|
8001882: 43d9 mvns r1, r3
|
|
8001884: 687b ldr r3, [r7, #4]
|
|
8001886: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001888: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
800188a: 4618 mov r0, r3
|
|
800188c: 3724 adds r7, #36 @ 0x24
|
|
800188e: 46bd mov sp, r7
|
|
8001890: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001894: 4770 bx lr
|
|
|
|
08001896 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001896: b580 push {r7, lr}
|
|
8001898: b082 sub sp, #8
|
|
800189a: af00 add r7, sp, #0
|
|
800189c: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
800189e: 6878 ldr r0, [r7, #4]
|
|
80018a0: f7ff ff4c bl 800173c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
80018a4: bf00 nop
|
|
80018a6: 3708 adds r7, #8
|
|
80018a8: 46bd mov sp, r7
|
|
80018aa: bd80 pop {r7, pc}
|
|
|
|
080018ac <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80018ac: b580 push {r7, lr}
|
|
80018ae: b086 sub sp, #24
|
|
80018b0: af00 add r7, sp, #0
|
|
80018b2: 4603 mov r3, r0
|
|
80018b4: 60b9 str r1, [r7, #8]
|
|
80018b6: 607a str r2, [r7, #4]
|
|
80018b8: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
80018ba: 2300 movs r3, #0
|
|
80018bc: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
80018be: f7ff ff61 bl 8001784 <__NVIC_GetPriorityGrouping>
|
|
80018c2: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
80018c4: 687a ldr r2, [r7, #4]
|
|
80018c6: 68b9 ldr r1, [r7, #8]
|
|
80018c8: 6978 ldr r0, [r7, #20]
|
|
80018ca: f7ff ffb1 bl 8001830 <NVIC_EncodePriority>
|
|
80018ce: 4602 mov r2, r0
|
|
80018d0: f997 300f ldrsb.w r3, [r7, #15]
|
|
80018d4: 4611 mov r1, r2
|
|
80018d6: 4618 mov r0, r3
|
|
80018d8: f7ff ff80 bl 80017dc <__NVIC_SetPriority>
|
|
}
|
|
80018dc: bf00 nop
|
|
80018de: 3718 adds r7, #24
|
|
80018e0: 46bd mov sp, r7
|
|
80018e2: bd80 pop {r7, pc}
|
|
|
|
080018e4 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80018e4: b580 push {r7, lr}
|
|
80018e6: b082 sub sp, #8
|
|
80018e8: af00 add r7, sp, #0
|
|
80018ea: 4603 mov r3, r0
|
|
80018ec: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
80018ee: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80018f2: 4618 mov r0, r3
|
|
80018f4: f7ff ff54 bl 80017a0 <__NVIC_EnableIRQ>
|
|
}
|
|
80018f8: bf00 nop
|
|
80018fa: 3708 adds r7, #8
|
|
80018fc: 46bd mov sp, r7
|
|
80018fe: bd80 pop {r7, pc}
|
|
|
|
08001900 <HAL_CRC_Init>:
|
|
* parameters in the CRC_InitTypeDef and create the associated handle.
|
|
* @param hcrc CRC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
|
{
|
|
8001900: b580 push {r7, lr}
|
|
8001902: b082 sub sp, #8
|
|
8001904: af00 add r7, sp, #0
|
|
8001906: 6078 str r0, [r7, #4]
|
|
/* Check the CRC handle allocation */
|
|
if (hcrc == NULL)
|
|
8001908: 687b ldr r3, [r7, #4]
|
|
800190a: 2b00 cmp r3, #0
|
|
800190c: d101 bne.n 8001912 <HAL_CRC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800190e: 2301 movs r3, #1
|
|
8001910: e00e b.n 8001930 <HAL_CRC_Init+0x30>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
|
|
|
if (hcrc->State == HAL_CRC_STATE_RESET)
|
|
8001912: 687b ldr r3, [r7, #4]
|
|
8001914: 795b ldrb r3, [r3, #5]
|
|
8001916: b2db uxtb r3, r3
|
|
8001918: 2b00 cmp r3, #0
|
|
800191a: d105 bne.n 8001928 <HAL_CRC_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hcrc->Lock = HAL_UNLOCKED;
|
|
800191c: 687b ldr r3, [r7, #4]
|
|
800191e: 2200 movs r2, #0
|
|
8001920: 711a strb r2, [r3, #4]
|
|
/* Init the low level hardware */
|
|
HAL_CRC_MspInit(hcrc);
|
|
8001922: 6878 ldr r0, [r7, #4]
|
|
8001924: f7ff fa40 bl 8000da8 <HAL_CRC_MspInit>
|
|
}
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_READY;
|
|
8001928: 687b ldr r3, [r7, #4]
|
|
800192a: 2201 movs r2, #1
|
|
800192c: 715a strb r2, [r3, #5]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800192e: 2300 movs r3, #0
|
|
}
|
|
8001930: 4618 mov r0, r3
|
|
8001932: 3708 adds r7, #8
|
|
8001934: 46bd mov sp, r7
|
|
8001936: bd80 pop {r7, pc}
|
|
|
|
08001938 <HAL_DMA2D_Init>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001938: b580 push {r7, lr}
|
|
800193a: b082 sub sp, #8
|
|
800193c: af00 add r7, sp, #0
|
|
800193e: 6078 str r0, [r7, #4]
|
|
/* Check the DMA2D peripheral state */
|
|
if (hdma2d == NULL)
|
|
8001940: 687b ldr r3, [r7, #4]
|
|
8001942: 2b00 cmp r3, #0
|
|
8001944: d101 bne.n 800194a <HAL_DMA2D_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001946: 2301 movs r3, #1
|
|
8001948: e03b b.n 80019c2 <HAL_DMA2D_Init+0x8a>
|
|
|
|
/* Init the low level hardware */
|
|
hdma2d->MspInitCallback(hdma2d);
|
|
}
|
|
#else
|
|
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
|
|
800194a: 687b ldr r3, [r7, #4]
|
|
800194c: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
|
|
8001950: b2db uxtb r3, r3
|
|
8001952: 2b00 cmp r3, #0
|
|
8001954: d106 bne.n 8001964 <HAL_DMA2D_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hdma2d->Lock = HAL_UNLOCKED;
|
|
8001956: 687b ldr r3, [r7, #4]
|
|
8001958: 2200 movs r2, #0
|
|
800195a: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
/* Init the low level hardware */
|
|
HAL_DMA2D_MspInit(hdma2d);
|
|
800195e: 6878 ldr r0, [r7, #4]
|
|
8001960: f7ff fa44 bl 8000dec <HAL_DMA2D_MspInit>
|
|
}
|
|
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8001964: 687b ldr r3, [r7, #4]
|
|
8001966: 2202 movs r2, #2
|
|
8001968: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* DMA2D CR register configuration -------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
|
|
800196c: 687b ldr r3, [r7, #4]
|
|
800196e: 681b ldr r3, [r3, #0]
|
|
8001970: 681b ldr r3, [r3, #0]
|
|
8001972: f423 3140 bic.w r1, r3, #196608 @ 0x30000
|
|
8001976: 687b ldr r3, [r7, #4]
|
|
8001978: 685a ldr r2, [r3, #4]
|
|
800197a: 687b ldr r3, [r7, #4]
|
|
800197c: 681b ldr r3, [r3, #0]
|
|
800197e: 430a orrs r2, r1
|
|
8001980: 601a str r2, [r3, #0]
|
|
|
|
/* DMA2D OPFCCR register configuration ---------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
|
|
8001982: 687b ldr r3, [r7, #4]
|
|
8001984: 681b ldr r3, [r3, #0]
|
|
8001986: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001988: f023 0107 bic.w r1, r3, #7
|
|
800198c: 687b ldr r3, [r7, #4]
|
|
800198e: 689a ldr r2, [r3, #8]
|
|
8001990: 687b ldr r3, [r7, #4]
|
|
8001992: 681b ldr r3, [r3, #0]
|
|
8001994: 430a orrs r2, r1
|
|
8001996: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* DMA2D OOR register configuration ------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
|
|
8001998: 687b ldr r3, [r7, #4]
|
|
800199a: 681b ldr r3, [r3, #0]
|
|
800199c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800199e: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
|
|
80019a2: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
80019a6: 687a ldr r2, [r7, #4]
|
|
80019a8: 68d1 ldr r1, [r2, #12]
|
|
80019aa: 687a ldr r2, [r7, #4]
|
|
80019ac: 6812 ldr r2, [r2, #0]
|
|
80019ae: 430b orrs r3, r1
|
|
80019b0: 6413 str r3, [r2, #64] @ 0x40
|
|
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
|
|
80019b2: 687b ldr r3, [r7, #4]
|
|
80019b4: 2200 movs r2, #0
|
|
80019b6: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
80019b8: 687b ldr r3, [r7, #4]
|
|
80019ba: 2201 movs r2, #1
|
|
80019bc: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
return HAL_OK;
|
|
80019c0: 2300 movs r3, #0
|
|
}
|
|
80019c2: 4618 mov r0, r3
|
|
80019c4: 3708 adds r7, #8
|
|
80019c6: 46bd mov sp, r7
|
|
80019c8: bd80 pop {r7, pc}
|
|
|
|
080019ca <HAL_DMA2D_IRQHandler>:
|
|
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
80019ca: b580 push {r7, lr}
|
|
80019cc: b084 sub sp, #16
|
|
80019ce: af00 add r7, sp, #0
|
|
80019d0: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
|
|
80019d2: 687b ldr r3, [r7, #4]
|
|
80019d4: 681b ldr r3, [r3, #0]
|
|
80019d6: 685b ldr r3, [r3, #4]
|
|
80019d8: 60fb str r3, [r7, #12]
|
|
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
|
|
80019da: 687b ldr r3, [r7, #4]
|
|
80019dc: 681b ldr r3, [r3, #0]
|
|
80019de: 681b ldr r3, [r3, #0]
|
|
80019e0: 60bb str r3, [r7, #8]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if ((isrflags & DMA2D_FLAG_TE) != 0U)
|
|
80019e2: 68fb ldr r3, [r7, #12]
|
|
80019e4: f003 0301 and.w r3, r3, #1
|
|
80019e8: 2b00 cmp r3, #0
|
|
80019ea: d026 beq.n 8001a3a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
if ((crflags & DMA2D_IT_TE) != 0U)
|
|
80019ec: 68bb ldr r3, [r7, #8]
|
|
80019ee: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80019f2: 2b00 cmp r3, #0
|
|
80019f4: d021 beq.n 8001a3a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
/* Disable the transfer Error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
|
|
80019f6: 687b ldr r3, [r7, #4]
|
|
80019f8: 681b ldr r3, [r3, #0]
|
|
80019fa: 681a ldr r2, [r3, #0]
|
|
80019fc: 687b ldr r3, [r7, #4]
|
|
80019fe: 681b ldr r3, [r3, #0]
|
|
8001a00: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001a04: 601a str r2, [r3, #0]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
|
|
8001a06: 687b ldr r3, [r7, #4]
|
|
8001a08: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8001a0a: f043 0201 orr.w r2, r3, #1
|
|
8001a0e: 687b ldr r3, [r7, #4]
|
|
8001a10: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Clear the transfer error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
|
|
8001a12: 687b ldr r3, [r7, #4]
|
|
8001a14: 681b ldr r3, [r3, #0]
|
|
8001a16: 2201 movs r2, #1
|
|
8001a18: 609a str r2, [r3, #8]
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
8001a1a: 687b ldr r3, [r7, #4]
|
|
8001a1c: 2204 movs r2, #4
|
|
8001a1e: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001a22: 687b ldr r3, [r7, #4]
|
|
8001a24: 2200 movs r2, #0
|
|
8001a26: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
8001a2a: 687b ldr r3, [r7, #4]
|
|
8001a2c: 695b ldr r3, [r3, #20]
|
|
8001a2e: 2b00 cmp r3, #0
|
|
8001a30: d003 beq.n 8001a3a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
8001a32: 687b ldr r3, [r7, #4]
|
|
8001a34: 695b ldr r3, [r3, #20]
|
|
8001a36: 6878 ldr r0, [r7, #4]
|
|
8001a38: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* Configuration Error Interrupt management **********************************/
|
|
if ((isrflags & DMA2D_FLAG_CE) != 0U)
|
|
8001a3a: 68fb ldr r3, [r7, #12]
|
|
8001a3c: f003 0320 and.w r3, r3, #32
|
|
8001a40: 2b00 cmp r3, #0
|
|
8001a42: d026 beq.n 8001a92 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
if ((crflags & DMA2D_IT_CE) != 0U)
|
|
8001a44: 68bb ldr r3, [r7, #8]
|
|
8001a46: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
8001a4a: 2b00 cmp r3, #0
|
|
8001a4c: d021 beq.n 8001a92 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
/* Disable the Configuration Error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
|
|
8001a4e: 687b ldr r3, [r7, #4]
|
|
8001a50: 681b ldr r3, [r3, #0]
|
|
8001a52: 681a ldr r2, [r3, #0]
|
|
8001a54: 687b ldr r3, [r7, #4]
|
|
8001a56: 681b ldr r3, [r3, #0]
|
|
8001a58: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8001a5c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the Configuration error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
|
|
8001a5e: 687b ldr r3, [r7, #4]
|
|
8001a60: 681b ldr r3, [r3, #0]
|
|
8001a62: 2220 movs r2, #32
|
|
8001a64: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
|
|
8001a66: 687b ldr r3, [r7, #4]
|
|
8001a68: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8001a6a: f043 0202 orr.w r2, r3, #2
|
|
8001a6e: 687b ldr r3, [r7, #4]
|
|
8001a70: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
8001a72: 687b ldr r3, [r7, #4]
|
|
8001a74: 2204 movs r2, #4
|
|
8001a76: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001a7a: 687b ldr r3, [r7, #4]
|
|
8001a7c: 2200 movs r2, #0
|
|
8001a7e: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
8001a82: 687b ldr r3, [r7, #4]
|
|
8001a84: 695b ldr r3, [r3, #20]
|
|
8001a86: 2b00 cmp r3, #0
|
|
8001a88: d003 beq.n 8001a92 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
8001a8a: 687b ldr r3, [r7, #4]
|
|
8001a8c: 695b ldr r3, [r3, #20]
|
|
8001a8e: 6878 ldr r0, [r7, #4]
|
|
8001a90: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* CLUT access Error Interrupt management ***********************************/
|
|
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
|
|
8001a92: 68fb ldr r3, [r7, #12]
|
|
8001a94: f003 0308 and.w r3, r3, #8
|
|
8001a98: 2b00 cmp r3, #0
|
|
8001a9a: d026 beq.n 8001aea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
if ((crflags & DMA2D_IT_CAE) != 0U)
|
|
8001a9c: 68bb ldr r3, [r7, #8]
|
|
8001a9e: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8001aa2: 2b00 cmp r3, #0
|
|
8001aa4: d021 beq.n 8001aea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
/* Disable the CLUT access error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
|
|
8001aa6: 687b ldr r3, [r7, #4]
|
|
8001aa8: 681b ldr r3, [r3, #0]
|
|
8001aaa: 681a ldr r2, [r3, #0]
|
|
8001aac: 687b ldr r3, [r7, #4]
|
|
8001aae: 681b ldr r3, [r3, #0]
|
|
8001ab0: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8001ab4: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the CLUT access error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
|
|
8001ab6: 687b ldr r3, [r7, #4]
|
|
8001ab8: 681b ldr r3, [r3, #0]
|
|
8001aba: 2208 movs r2, #8
|
|
8001abc: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
|
|
8001abe: 687b ldr r3, [r7, #4]
|
|
8001ac0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8001ac2: f043 0204 orr.w r2, r3, #4
|
|
8001ac6: 687b ldr r3, [r7, #4]
|
|
8001ac8: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
8001aca: 687b ldr r3, [r7, #4]
|
|
8001acc: 2204 movs r2, #4
|
|
8001ace: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001ad2: 687b ldr r3, [r7, #4]
|
|
8001ad4: 2200 movs r2, #0
|
|
8001ad6: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
8001ada: 687b ldr r3, [r7, #4]
|
|
8001adc: 695b ldr r3, [r3, #20]
|
|
8001ade: 2b00 cmp r3, #0
|
|
8001ae0: d003 beq.n 8001aea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
8001ae2: 687b ldr r3, [r7, #4]
|
|
8001ae4: 695b ldr r3, [r3, #20]
|
|
8001ae6: 6878 ldr r0, [r7, #4]
|
|
8001ae8: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* Transfer watermark Interrupt management **********************************/
|
|
if ((isrflags & DMA2D_FLAG_TW) != 0U)
|
|
8001aea: 68fb ldr r3, [r7, #12]
|
|
8001aec: f003 0304 and.w r3, r3, #4
|
|
8001af0: 2b00 cmp r3, #0
|
|
8001af2: d013 beq.n 8001b1c <HAL_DMA2D_IRQHandler+0x152>
|
|
{
|
|
if ((crflags & DMA2D_IT_TW) != 0U)
|
|
8001af4: 68bb ldr r3, [r7, #8]
|
|
8001af6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8001afa: 2b00 cmp r3, #0
|
|
8001afc: d00e beq.n 8001b1c <HAL_DMA2D_IRQHandler+0x152>
|
|
{
|
|
/* Disable the transfer watermark interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
|
|
8001afe: 687b ldr r3, [r7, #4]
|
|
8001b00: 681b ldr r3, [r3, #0]
|
|
8001b02: 681a ldr r2, [r3, #0]
|
|
8001b04: 687b ldr r3, [r7, #4]
|
|
8001b06: 681b ldr r3, [r3, #0]
|
|
8001b08: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8001b0c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer watermark flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
|
|
8001b0e: 687b ldr r3, [r7, #4]
|
|
8001b10: 681b ldr r3, [r3, #0]
|
|
8001b12: 2204 movs r2, #4
|
|
8001b14: 609a str r2, [r3, #8]
|
|
|
|
/* Transfer watermark Callback */
|
|
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
|
hdma2d->LineEventCallback(hdma2d);
|
|
#else
|
|
HAL_DMA2D_LineEventCallback(hdma2d);
|
|
8001b16: 6878 ldr r0, [r7, #4]
|
|
8001b18: f000 f853 bl 8001bc2 <HAL_DMA2D_LineEventCallback>
|
|
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
|
|
|
}
|
|
}
|
|
/* Transfer Complete Interrupt management ************************************/
|
|
if ((isrflags & DMA2D_FLAG_TC) != 0U)
|
|
8001b1c: 68fb ldr r3, [r7, #12]
|
|
8001b1e: f003 0302 and.w r3, r3, #2
|
|
8001b22: 2b00 cmp r3, #0
|
|
8001b24: d024 beq.n 8001b70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
if ((crflags & DMA2D_IT_TC) != 0U)
|
|
8001b26: 68bb ldr r3, [r7, #8]
|
|
8001b28: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001b2c: 2b00 cmp r3, #0
|
|
8001b2e: d01f beq.n 8001b70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
/* Disable the transfer complete interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
|
|
8001b30: 687b ldr r3, [r7, #4]
|
|
8001b32: 681b ldr r3, [r3, #0]
|
|
8001b34: 681a ldr r2, [r3, #0]
|
|
8001b36: 687b ldr r3, [r7, #4]
|
|
8001b38: 681b ldr r3, [r3, #0]
|
|
8001b3a: f422 7200 bic.w r2, r2, #512 @ 0x200
|
|
8001b3e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer complete flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
|
|
8001b40: 687b ldr r3, [r7, #4]
|
|
8001b42: 681b ldr r3, [r3, #0]
|
|
8001b44: 2202 movs r2, #2
|
|
8001b46: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
|
|
8001b48: 687b ldr r3, [r7, #4]
|
|
8001b4a: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8001b4c: 687b ldr r3, [r7, #4]
|
|
8001b4e: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001b50: 687b ldr r3, [r7, #4]
|
|
8001b52: 2201 movs r2, #1
|
|
8001b54: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001b58: 687b ldr r3, [r7, #4]
|
|
8001b5a: 2200 movs r2, #0
|
|
8001b5c: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferCpltCallback != NULL)
|
|
8001b60: 687b ldr r3, [r7, #4]
|
|
8001b62: 691b ldr r3, [r3, #16]
|
|
8001b64: 2b00 cmp r3, #0
|
|
8001b66: d003 beq.n 8001b70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
/* Transfer complete Callback */
|
|
hdma2d->XferCpltCallback(hdma2d);
|
|
8001b68: 687b ldr r3, [r7, #4]
|
|
8001b6a: 691b ldr r3, [r3, #16]
|
|
8001b6c: 6878 ldr r0, [r7, #4]
|
|
8001b6e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* CLUT Transfer Complete Interrupt management ******************************/
|
|
if ((isrflags & DMA2D_FLAG_CTC) != 0U)
|
|
8001b70: 68fb ldr r3, [r7, #12]
|
|
8001b72: f003 0310 and.w r3, r3, #16
|
|
8001b76: 2b00 cmp r3, #0
|
|
8001b78: d01f beq.n 8001bba <HAL_DMA2D_IRQHandler+0x1f0>
|
|
{
|
|
if ((crflags & DMA2D_IT_CTC) != 0U)
|
|
8001b7a: 68bb ldr r3, [r7, #8]
|
|
8001b7c: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8001b80: 2b00 cmp r3, #0
|
|
8001b82: d01a beq.n 8001bba <HAL_DMA2D_IRQHandler+0x1f0>
|
|
{
|
|
/* Disable the CLUT transfer complete interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
|
|
8001b84: 687b ldr r3, [r7, #4]
|
|
8001b86: 681b ldr r3, [r3, #0]
|
|
8001b88: 681a ldr r2, [r3, #0]
|
|
8001b8a: 687b ldr r3, [r7, #4]
|
|
8001b8c: 681b ldr r3, [r3, #0]
|
|
8001b8e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8001b92: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the CLUT transfer complete flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
|
|
8001b94: 687b ldr r3, [r7, #4]
|
|
8001b96: 681b ldr r3, [r3, #0]
|
|
8001b98: 2210 movs r2, #16
|
|
8001b9a: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
|
|
8001b9c: 687b ldr r3, [r7, #4]
|
|
8001b9e: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8001ba0: 687b ldr r3, [r7, #4]
|
|
8001ba2: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001ba4: 687b ldr r3, [r7, #4]
|
|
8001ba6: 2201 movs r2, #1
|
|
8001ba8: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001bac: 687b ldr r3, [r7, #4]
|
|
8001bae: 2200 movs r2, #0
|
|
8001bb0: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* CLUT Transfer complete Callback */
|
|
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
|
hdma2d->CLUTLoadingCpltCallback(hdma2d);
|
|
#else
|
|
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
|
|
8001bb4: 6878 ldr r0, [r7, #4]
|
|
8001bb6: f000 f80e bl 8001bd6 <HAL_DMA2D_CLUTLoadingCpltCallback>
|
|
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
}
|
|
8001bba: bf00 nop
|
|
8001bbc: 3710 adds r7, #16
|
|
8001bbe: 46bd mov sp, r7
|
|
8001bc0: bd80 pop {r7, pc}
|
|
|
|
08001bc2 <HAL_DMA2D_LineEventCallback>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001bc2: b480 push {r7}
|
|
8001bc4: b083 sub sp, #12
|
|
8001bc6: af00 add r7, sp, #0
|
|
8001bc8: 6078 str r0, [r7, #4]
|
|
UNUSED(hdma2d);
|
|
|
|
/* NOTE : This function should not be modified; when the callback is needed,
|
|
the HAL_DMA2D_LineEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8001bca: bf00 nop
|
|
8001bcc: 370c adds r7, #12
|
|
8001bce: 46bd mov sp, r7
|
|
8001bd0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001bd4: 4770 bx lr
|
|
|
|
08001bd6 <HAL_DMA2D_CLUTLoadingCpltCallback>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001bd6: b480 push {r7}
|
|
8001bd8: b083 sub sp, #12
|
|
8001bda: af00 add r7, sp, #0
|
|
8001bdc: 6078 str r0, [r7, #4]
|
|
UNUSED(hdma2d);
|
|
|
|
/* NOTE : This function should not be modified; when the callback is needed,
|
|
the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8001bde: bf00 nop
|
|
8001be0: 370c adds r7, #12
|
|
8001be2: 46bd mov sp, r7
|
|
8001be4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001be8: 4770 bx lr
|
|
...
|
|
|
|
08001bec <HAL_DMA2D_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
|
|
{
|
|
8001bec: b480 push {r7}
|
|
8001bee: b087 sub sp, #28
|
|
8001bf0: af00 add r7, sp, #0
|
|
8001bf2: 6078 str r0, [r7, #4]
|
|
8001bf4: 6039 str r1, [r7, #0]
|
|
uint32_t regValue;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA2D_LAYER(LayerIdx));
|
|
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
|
|
if (hdma2d->Init.Mode != DMA2D_R2M)
|
|
8001bf6: 687b ldr r3, [r7, #4]
|
|
8001bf8: 685b ldr r3, [r3, #4]
|
|
8001bfa: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
|
|
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
|
|
}
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma2d);
|
|
8001bfe: 687b ldr r3, [r7, #4]
|
|
8001c00: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8001c04: 2b01 cmp r3, #1
|
|
8001c06: d101 bne.n 8001c0c <HAL_DMA2D_ConfigLayer+0x20>
|
|
8001c08: 2302 movs r3, #2
|
|
8001c0a: e079 b.n 8001d00 <HAL_DMA2D_ConfigLayer+0x114>
|
|
8001c0c: 687b ldr r3, [r7, #4]
|
|
8001c0e: 2201 movs r2, #1
|
|
8001c10: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8001c14: 687b ldr r3, [r7, #4]
|
|
8001c16: 2202 movs r2, #2
|
|
8001c18: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
|
|
8001c1c: 683b ldr r3, [r7, #0]
|
|
8001c1e: 011b lsls r3, r3, #4
|
|
8001c20: 3318 adds r3, #24
|
|
8001c22: 687a ldr r2, [r7, #4]
|
|
8001c24: 4413 add r3, r2
|
|
8001c26: 613b str r3, [r7, #16]
|
|
|
|
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
|
|
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
|
|
8001c28: 693b ldr r3, [r7, #16]
|
|
8001c2a: 685a ldr r2, [r3, #4]
|
|
8001c2c: 693b ldr r3, [r7, #16]
|
|
8001c2e: 689b ldr r3, [r3, #8]
|
|
8001c30: 041b lsls r3, r3, #16
|
|
8001c32: 4313 orrs r3, r2
|
|
8001c34: 617b str r3, [r7, #20]
|
|
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
|
|
8001c36: 4b35 ldr r3, [pc, #212] @ (8001d0c <HAL_DMA2D_ConfigLayer+0x120>)
|
|
8001c38: 60fb str r3, [r7, #12]
|
|
|
|
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001c3a: 693b ldr r3, [r7, #16]
|
|
8001c3c: 685b ldr r3, [r3, #4]
|
|
8001c3e: 2b0a cmp r3, #10
|
|
8001c40: d003 beq.n 8001c4a <HAL_DMA2D_ConfigLayer+0x5e>
|
|
8001c42: 693b ldr r3, [r7, #16]
|
|
8001c44: 685b ldr r3, [r3, #4]
|
|
8001c46: 2b09 cmp r3, #9
|
|
8001c48: d107 bne.n 8001c5a <HAL_DMA2D_ConfigLayer+0x6e>
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
|
|
8001c4a: 693b ldr r3, [r7, #16]
|
|
8001c4c: 68db ldr r3, [r3, #12]
|
|
8001c4e: f003 437f and.w r3, r3, #4278190080 @ 0xff000000
|
|
8001c52: 697a ldr r2, [r7, #20]
|
|
8001c54: 4313 orrs r3, r2
|
|
8001c56: 617b str r3, [r7, #20]
|
|
8001c58: e005 b.n 8001c66 <HAL_DMA2D_ConfigLayer+0x7a>
|
|
}
|
|
else
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
|
|
8001c5a: 693b ldr r3, [r7, #16]
|
|
8001c5c: 68db ldr r3, [r3, #12]
|
|
8001c5e: 061b lsls r3, r3, #24
|
|
8001c60: 697a ldr r2, [r7, #20]
|
|
8001c62: 4313 orrs r3, r2
|
|
8001c64: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Configure the background DMA2D layer */
|
|
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
|
|
8001c66: 683b ldr r3, [r7, #0]
|
|
8001c68: 2b00 cmp r3, #0
|
|
8001c6a: d120 bne.n 8001cae <HAL_DMA2D_ConfigLayer+0xc2>
|
|
{
|
|
/* Write DMA2D BGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
|
|
8001c6c: 687b ldr r3, [r7, #4]
|
|
8001c6e: 681b ldr r3, [r3, #0]
|
|
8001c70: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8001c72: 68fb ldr r3, [r7, #12]
|
|
8001c74: 43db mvns r3, r3
|
|
8001c76: ea02 0103 and.w r1, r2, r3
|
|
8001c7a: 687b ldr r3, [r7, #4]
|
|
8001c7c: 681b ldr r3, [r3, #0]
|
|
8001c7e: 697a ldr r2, [r7, #20]
|
|
8001c80: 430a orrs r2, r1
|
|
8001c82: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* DMA2D BGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
|
|
8001c84: 687b ldr r3, [r7, #4]
|
|
8001c86: 681b ldr r3, [r3, #0]
|
|
8001c88: 693a ldr r2, [r7, #16]
|
|
8001c8a: 6812 ldr r2, [r2, #0]
|
|
8001c8c: 619a str r2, [r3, #24]
|
|
|
|
/* DMA2D BGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001c8e: 693b ldr r3, [r7, #16]
|
|
8001c90: 685b ldr r3, [r3, #4]
|
|
8001c92: 2b0a cmp r3, #10
|
|
8001c94: d003 beq.n 8001c9e <HAL_DMA2D_ConfigLayer+0xb2>
|
|
8001c96: 693b ldr r3, [r7, #16]
|
|
8001c98: 685b ldr r3, [r3, #4]
|
|
8001c9a: 2b09 cmp r3, #9
|
|
8001c9c: d127 bne.n 8001cee <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
|
|
8001c9e: 693b ldr r3, [r7, #16]
|
|
8001ca0: 68da ldr r2, [r3, #12]
|
|
8001ca2: 687b ldr r3, [r7, #4]
|
|
8001ca4: 681b ldr r3, [r3, #0]
|
|
8001ca6: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
|
|
8001caa: 629a str r2, [r3, #40] @ 0x28
|
|
8001cac: e01f b.n 8001cee <HAL_DMA2D_ConfigLayer+0x102>
|
|
else
|
|
{
|
|
|
|
|
|
/* Write DMA2D FGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
|
|
8001cae: 687b ldr r3, [r7, #4]
|
|
8001cb0: 681b ldr r3, [r3, #0]
|
|
8001cb2: 69da ldr r2, [r3, #28]
|
|
8001cb4: 68fb ldr r3, [r7, #12]
|
|
8001cb6: 43db mvns r3, r3
|
|
8001cb8: ea02 0103 and.w r1, r2, r3
|
|
8001cbc: 687b ldr r3, [r7, #4]
|
|
8001cbe: 681b ldr r3, [r3, #0]
|
|
8001cc0: 697a ldr r2, [r7, #20]
|
|
8001cc2: 430a orrs r2, r1
|
|
8001cc4: 61da str r2, [r3, #28]
|
|
|
|
/* DMA2D FGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
|
|
8001cc6: 687b ldr r3, [r7, #4]
|
|
8001cc8: 681b ldr r3, [r3, #0]
|
|
8001cca: 693a ldr r2, [r7, #16]
|
|
8001ccc: 6812 ldr r2, [r2, #0]
|
|
8001cce: 611a str r2, [r3, #16]
|
|
|
|
/* DMA2D FGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001cd0: 693b ldr r3, [r7, #16]
|
|
8001cd2: 685b ldr r3, [r3, #4]
|
|
8001cd4: 2b0a cmp r3, #10
|
|
8001cd6: d003 beq.n 8001ce0 <HAL_DMA2D_ConfigLayer+0xf4>
|
|
8001cd8: 693b ldr r3, [r7, #16]
|
|
8001cda: 685b ldr r3, [r3, #4]
|
|
8001cdc: 2b09 cmp r3, #9
|
|
8001cde: d106 bne.n 8001cee <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
|
|
8001ce0: 693b ldr r3, [r7, #16]
|
|
8001ce2: 68da ldr r2, [r3, #12]
|
|
8001ce4: 687b ldr r3, [r7, #4]
|
|
8001ce6: 681b ldr r3, [r3, #0]
|
|
8001ce8: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
|
|
8001cec: 621a str r2, [r3, #32]
|
|
DMA2D_FGCOLR_RED));
|
|
}
|
|
}
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001cee: 687b ldr r3, [r7, #4]
|
|
8001cf0: 2201 movs r2, #1
|
|
8001cf2: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001cf6: 687b ldr r3, [r7, #4]
|
|
8001cf8: 2200 movs r2, #0
|
|
8001cfa: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
return HAL_OK;
|
|
8001cfe: 2300 movs r3, #0
|
|
}
|
|
8001d00: 4618 mov r0, r3
|
|
8001d02: 371c adds r7, #28
|
|
8001d04: 46bd mov sp, r7
|
|
8001d06: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001d0a: 4770 bx lr
|
|
8001d0c: ff03000f .word 0xff03000f
|
|
|
|
08001d10 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8001d10: b480 push {r7}
|
|
8001d12: b089 sub sp, #36 @ 0x24
|
|
8001d14: af00 add r7, sp, #0
|
|
8001d16: 6078 str r0, [r7, #4]
|
|
8001d18: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
8001d1a: 2300 movs r3, #0
|
|
8001d1c: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
8001d1e: 2300 movs r3, #0
|
|
8001d20: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
8001d22: 2300 movs r3, #0
|
|
8001d24: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8001d26: 2300 movs r3, #0
|
|
8001d28: 61fb str r3, [r7, #28]
|
|
8001d2a: e177 b.n 800201c <HAL_GPIO_Init+0x30c>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
8001d2c: 2201 movs r2, #1
|
|
8001d2e: 69fb ldr r3, [r7, #28]
|
|
8001d30: fa02 f303 lsl.w r3, r2, r3
|
|
8001d34: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8001d36: 683b ldr r3, [r7, #0]
|
|
8001d38: 681b ldr r3, [r3, #0]
|
|
8001d3a: 697a ldr r2, [r7, #20]
|
|
8001d3c: 4013 ands r3, r2
|
|
8001d3e: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
8001d40: 693a ldr r2, [r7, #16]
|
|
8001d42: 697b ldr r3, [r7, #20]
|
|
8001d44: 429a cmp r2, r3
|
|
8001d46: f040 8166 bne.w 8002016 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
8001d4a: 683b ldr r3, [r7, #0]
|
|
8001d4c: 685b ldr r3, [r3, #4]
|
|
8001d4e: f003 0303 and.w r3, r3, #3
|
|
8001d52: 2b01 cmp r3, #1
|
|
8001d54: d005 beq.n 8001d62 <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001d56: 683b ldr r3, [r7, #0]
|
|
8001d58: 685b ldr r3, [r3, #4]
|
|
8001d5a: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
8001d5e: 2b02 cmp r3, #2
|
|
8001d60: d130 bne.n 8001dc4 <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8001d62: 687b ldr r3, [r7, #4]
|
|
8001d64: 689b ldr r3, [r3, #8]
|
|
8001d66: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
8001d68: 69fb ldr r3, [r7, #28]
|
|
8001d6a: 005b lsls r3, r3, #1
|
|
8001d6c: 2203 movs r2, #3
|
|
8001d6e: fa02 f303 lsl.w r3, r2, r3
|
|
8001d72: 43db mvns r3, r3
|
|
8001d74: 69ba ldr r2, [r7, #24]
|
|
8001d76: 4013 ands r3, r2
|
|
8001d78: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001d7a: 683b ldr r3, [r7, #0]
|
|
8001d7c: 68da ldr r2, [r3, #12]
|
|
8001d7e: 69fb ldr r3, [r7, #28]
|
|
8001d80: 005b lsls r3, r3, #1
|
|
8001d82: fa02 f303 lsl.w r3, r2, r3
|
|
8001d86: 69ba ldr r2, [r7, #24]
|
|
8001d88: 4313 orrs r3, r2
|
|
8001d8a: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001d8c: 687b ldr r3, [r7, #4]
|
|
8001d8e: 69ba ldr r2, [r7, #24]
|
|
8001d90: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8001d92: 687b ldr r3, [r7, #4]
|
|
8001d94: 685b ldr r3, [r3, #4]
|
|
8001d96: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8001d98: 2201 movs r2, #1
|
|
8001d9a: 69fb ldr r3, [r7, #28]
|
|
8001d9c: fa02 f303 lsl.w r3, r2, r3
|
|
8001da0: 43db mvns r3, r3
|
|
8001da2: 69ba ldr r2, [r7, #24]
|
|
8001da4: 4013 ands r3, r2
|
|
8001da6: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001da8: 683b ldr r3, [r7, #0]
|
|
8001daa: 685b ldr r3, [r3, #4]
|
|
8001dac: 091b lsrs r3, r3, #4
|
|
8001dae: f003 0201 and.w r2, r3, #1
|
|
8001db2: 69fb ldr r3, [r7, #28]
|
|
8001db4: fa02 f303 lsl.w r3, r2, r3
|
|
8001db8: 69ba ldr r2, [r7, #24]
|
|
8001dba: 4313 orrs r3, r2
|
|
8001dbc: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8001dbe: 687b ldr r3, [r7, #4]
|
|
8001dc0: 69ba ldr r2, [r7, #24]
|
|
8001dc2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8001dc4: 683b ldr r3, [r7, #0]
|
|
8001dc6: 685b ldr r3, [r3, #4]
|
|
8001dc8: f003 0303 and.w r3, r3, #3
|
|
8001dcc: 2b03 cmp r3, #3
|
|
8001dce: d017 beq.n 8001e00 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8001dd0: 687b ldr r3, [r7, #4]
|
|
8001dd2: 68db ldr r3, [r3, #12]
|
|
8001dd4: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
8001dd6: 69fb ldr r3, [r7, #28]
|
|
8001dd8: 005b lsls r3, r3, #1
|
|
8001dda: 2203 movs r2, #3
|
|
8001ddc: fa02 f303 lsl.w r3, r2, r3
|
|
8001de0: 43db mvns r3, r3
|
|
8001de2: 69ba ldr r2, [r7, #24]
|
|
8001de4: 4013 ands r3, r2
|
|
8001de6: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001de8: 683b ldr r3, [r7, #0]
|
|
8001dea: 689a ldr r2, [r3, #8]
|
|
8001dec: 69fb ldr r3, [r7, #28]
|
|
8001dee: 005b lsls r3, r3, #1
|
|
8001df0: fa02 f303 lsl.w r3, r2, r3
|
|
8001df4: 69ba ldr r2, [r7, #24]
|
|
8001df6: 4313 orrs r3, r2
|
|
8001df8: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
8001dfa: 687b ldr r3, [r7, #4]
|
|
8001dfc: 69ba ldr r2, [r7, #24]
|
|
8001dfe: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001e00: 683b ldr r3, [r7, #0]
|
|
8001e02: 685b ldr r3, [r3, #4]
|
|
8001e04: f003 0303 and.w r3, r3, #3
|
|
8001e08: 2b02 cmp r3, #2
|
|
8001e0a: d123 bne.n 8001e54 <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
8001e0c: 69fb ldr r3, [r7, #28]
|
|
8001e0e: 08da lsrs r2, r3, #3
|
|
8001e10: 687b ldr r3, [r7, #4]
|
|
8001e12: 3208 adds r2, #8
|
|
8001e14: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8001e18: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
8001e1a: 69fb ldr r3, [r7, #28]
|
|
8001e1c: f003 0307 and.w r3, r3, #7
|
|
8001e20: 009b lsls r3, r3, #2
|
|
8001e22: 220f movs r2, #15
|
|
8001e24: fa02 f303 lsl.w r3, r2, r3
|
|
8001e28: 43db mvns r3, r3
|
|
8001e2a: 69ba ldr r2, [r7, #24]
|
|
8001e2c: 4013 ands r3, r2
|
|
8001e2e: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
8001e30: 683b ldr r3, [r7, #0]
|
|
8001e32: 691a ldr r2, [r3, #16]
|
|
8001e34: 69fb ldr r3, [r7, #28]
|
|
8001e36: f003 0307 and.w r3, r3, #7
|
|
8001e3a: 009b lsls r3, r3, #2
|
|
8001e3c: fa02 f303 lsl.w r3, r2, r3
|
|
8001e40: 69ba ldr r2, [r7, #24]
|
|
8001e42: 4313 orrs r3, r2
|
|
8001e44: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
8001e46: 69fb ldr r3, [r7, #28]
|
|
8001e48: 08da lsrs r2, r3, #3
|
|
8001e4a: 687b ldr r3, [r7, #4]
|
|
8001e4c: 3208 adds r2, #8
|
|
8001e4e: 69b9 ldr r1, [r7, #24]
|
|
8001e50: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8001e54: 687b ldr r3, [r7, #4]
|
|
8001e56: 681b ldr r3, [r3, #0]
|
|
8001e58: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
8001e5a: 69fb ldr r3, [r7, #28]
|
|
8001e5c: 005b lsls r3, r3, #1
|
|
8001e5e: 2203 movs r2, #3
|
|
8001e60: fa02 f303 lsl.w r3, r2, r3
|
|
8001e64: 43db mvns r3, r3
|
|
8001e66: 69ba ldr r2, [r7, #24]
|
|
8001e68: 4013 ands r3, r2
|
|
8001e6a: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001e6c: 683b ldr r3, [r7, #0]
|
|
8001e6e: 685b ldr r3, [r3, #4]
|
|
8001e70: f003 0203 and.w r2, r3, #3
|
|
8001e74: 69fb ldr r3, [r7, #28]
|
|
8001e76: 005b lsls r3, r3, #1
|
|
8001e78: fa02 f303 lsl.w r3, r2, r3
|
|
8001e7c: 69ba ldr r2, [r7, #24]
|
|
8001e7e: 4313 orrs r3, r2
|
|
8001e80: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8001e82: 687b ldr r3, [r7, #4]
|
|
8001e84: 69ba ldr r2, [r7, #24]
|
|
8001e86: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8001e88: 683b ldr r3, [r7, #0]
|
|
8001e8a: 685b ldr r3, [r3, #4]
|
|
8001e8c: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001e90: 2b00 cmp r3, #0
|
|
8001e92: f000 80c0 beq.w 8002016 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001e96: 2300 movs r3, #0
|
|
8001e98: 60fb str r3, [r7, #12]
|
|
8001e9a: 4b66 ldr r3, [pc, #408] @ (8002034 <HAL_GPIO_Init+0x324>)
|
|
8001e9c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001e9e: 4a65 ldr r2, [pc, #404] @ (8002034 <HAL_GPIO_Init+0x324>)
|
|
8001ea0: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8001ea4: 6453 str r3, [r2, #68] @ 0x44
|
|
8001ea6: 4b63 ldr r3, [pc, #396] @ (8002034 <HAL_GPIO_Init+0x324>)
|
|
8001ea8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001eaa: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001eae: 60fb str r3, [r7, #12]
|
|
8001eb0: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8001eb2: 4a61 ldr r2, [pc, #388] @ (8002038 <HAL_GPIO_Init+0x328>)
|
|
8001eb4: 69fb ldr r3, [r7, #28]
|
|
8001eb6: 089b lsrs r3, r3, #2
|
|
8001eb8: 3302 adds r3, #2
|
|
8001eba: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001ebe: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8001ec0: 69fb ldr r3, [r7, #28]
|
|
8001ec2: f003 0303 and.w r3, r3, #3
|
|
8001ec6: 009b lsls r3, r3, #2
|
|
8001ec8: 220f movs r2, #15
|
|
8001eca: fa02 f303 lsl.w r3, r2, r3
|
|
8001ece: 43db mvns r3, r3
|
|
8001ed0: 69ba ldr r2, [r7, #24]
|
|
8001ed2: 4013 ands r3, r2
|
|
8001ed4: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8001ed6: 687b ldr r3, [r7, #4]
|
|
8001ed8: 4a58 ldr r2, [pc, #352] @ (800203c <HAL_GPIO_Init+0x32c>)
|
|
8001eda: 4293 cmp r3, r2
|
|
8001edc: d037 beq.n 8001f4e <HAL_GPIO_Init+0x23e>
|
|
8001ede: 687b ldr r3, [r7, #4]
|
|
8001ee0: 4a57 ldr r2, [pc, #348] @ (8002040 <HAL_GPIO_Init+0x330>)
|
|
8001ee2: 4293 cmp r3, r2
|
|
8001ee4: d031 beq.n 8001f4a <HAL_GPIO_Init+0x23a>
|
|
8001ee6: 687b ldr r3, [r7, #4]
|
|
8001ee8: 4a56 ldr r2, [pc, #344] @ (8002044 <HAL_GPIO_Init+0x334>)
|
|
8001eea: 4293 cmp r3, r2
|
|
8001eec: d02b beq.n 8001f46 <HAL_GPIO_Init+0x236>
|
|
8001eee: 687b ldr r3, [r7, #4]
|
|
8001ef0: 4a55 ldr r2, [pc, #340] @ (8002048 <HAL_GPIO_Init+0x338>)
|
|
8001ef2: 4293 cmp r3, r2
|
|
8001ef4: d025 beq.n 8001f42 <HAL_GPIO_Init+0x232>
|
|
8001ef6: 687b ldr r3, [r7, #4]
|
|
8001ef8: 4a54 ldr r2, [pc, #336] @ (800204c <HAL_GPIO_Init+0x33c>)
|
|
8001efa: 4293 cmp r3, r2
|
|
8001efc: d01f beq.n 8001f3e <HAL_GPIO_Init+0x22e>
|
|
8001efe: 687b ldr r3, [r7, #4]
|
|
8001f00: 4a53 ldr r2, [pc, #332] @ (8002050 <HAL_GPIO_Init+0x340>)
|
|
8001f02: 4293 cmp r3, r2
|
|
8001f04: d019 beq.n 8001f3a <HAL_GPIO_Init+0x22a>
|
|
8001f06: 687b ldr r3, [r7, #4]
|
|
8001f08: 4a52 ldr r2, [pc, #328] @ (8002054 <HAL_GPIO_Init+0x344>)
|
|
8001f0a: 4293 cmp r3, r2
|
|
8001f0c: d013 beq.n 8001f36 <HAL_GPIO_Init+0x226>
|
|
8001f0e: 687b ldr r3, [r7, #4]
|
|
8001f10: 4a51 ldr r2, [pc, #324] @ (8002058 <HAL_GPIO_Init+0x348>)
|
|
8001f12: 4293 cmp r3, r2
|
|
8001f14: d00d beq.n 8001f32 <HAL_GPIO_Init+0x222>
|
|
8001f16: 687b ldr r3, [r7, #4]
|
|
8001f18: 4a50 ldr r2, [pc, #320] @ (800205c <HAL_GPIO_Init+0x34c>)
|
|
8001f1a: 4293 cmp r3, r2
|
|
8001f1c: d007 beq.n 8001f2e <HAL_GPIO_Init+0x21e>
|
|
8001f1e: 687b ldr r3, [r7, #4]
|
|
8001f20: 4a4f ldr r2, [pc, #316] @ (8002060 <HAL_GPIO_Init+0x350>)
|
|
8001f22: 4293 cmp r3, r2
|
|
8001f24: d101 bne.n 8001f2a <HAL_GPIO_Init+0x21a>
|
|
8001f26: 2309 movs r3, #9
|
|
8001f28: e012 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f2a: 230a movs r3, #10
|
|
8001f2c: e010 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f2e: 2308 movs r3, #8
|
|
8001f30: e00e b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f32: 2307 movs r3, #7
|
|
8001f34: e00c b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f36: 2306 movs r3, #6
|
|
8001f38: e00a b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f3a: 2305 movs r3, #5
|
|
8001f3c: e008 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f3e: 2304 movs r3, #4
|
|
8001f40: e006 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f42: 2303 movs r3, #3
|
|
8001f44: e004 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f46: 2302 movs r3, #2
|
|
8001f48: e002 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f4a: 2301 movs r3, #1
|
|
8001f4c: e000 b.n 8001f50 <HAL_GPIO_Init+0x240>
|
|
8001f4e: 2300 movs r3, #0
|
|
8001f50: 69fa ldr r2, [r7, #28]
|
|
8001f52: f002 0203 and.w r2, r2, #3
|
|
8001f56: 0092 lsls r2, r2, #2
|
|
8001f58: 4093 lsls r3, r2
|
|
8001f5a: 69ba ldr r2, [r7, #24]
|
|
8001f5c: 4313 orrs r3, r2
|
|
8001f5e: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8001f60: 4935 ldr r1, [pc, #212] @ (8002038 <HAL_GPIO_Init+0x328>)
|
|
8001f62: 69fb ldr r3, [r7, #28]
|
|
8001f64: 089b lsrs r3, r3, #2
|
|
8001f66: 3302 adds r3, #2
|
|
8001f68: 69ba ldr r2, [r7, #24]
|
|
8001f6a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8001f6e: 4b3d ldr r3, [pc, #244] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001f70: 689b ldr r3, [r3, #8]
|
|
8001f72: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001f74: 693b ldr r3, [r7, #16]
|
|
8001f76: 43db mvns r3, r3
|
|
8001f78: 69ba ldr r2, [r7, #24]
|
|
8001f7a: 4013 ands r3, r2
|
|
8001f7c: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001f7e: 683b ldr r3, [r7, #0]
|
|
8001f80: 685b ldr r3, [r3, #4]
|
|
8001f82: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001f86: 2b00 cmp r3, #0
|
|
8001f88: d003 beq.n 8001f92 <HAL_GPIO_Init+0x282>
|
|
{
|
|
temp |= iocurrent;
|
|
8001f8a: 69ba ldr r2, [r7, #24]
|
|
8001f8c: 693b ldr r3, [r7, #16]
|
|
8001f8e: 4313 orrs r3, r2
|
|
8001f90: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001f92: 4a34 ldr r2, [pc, #208] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001f94: 69bb ldr r3, [r7, #24]
|
|
8001f96: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8001f98: 4b32 ldr r3, [pc, #200] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001f9a: 68db ldr r3, [r3, #12]
|
|
8001f9c: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001f9e: 693b ldr r3, [r7, #16]
|
|
8001fa0: 43db mvns r3, r3
|
|
8001fa2: 69ba ldr r2, [r7, #24]
|
|
8001fa4: 4013 ands r3, r2
|
|
8001fa6: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001fa8: 683b ldr r3, [r7, #0]
|
|
8001faa: 685b ldr r3, [r3, #4]
|
|
8001fac: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001fb0: 2b00 cmp r3, #0
|
|
8001fb2: d003 beq.n 8001fbc <HAL_GPIO_Init+0x2ac>
|
|
{
|
|
temp |= iocurrent;
|
|
8001fb4: 69ba ldr r2, [r7, #24]
|
|
8001fb6: 693b ldr r3, [r7, #16]
|
|
8001fb8: 4313 orrs r3, r2
|
|
8001fba: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8001fbc: 4a29 ldr r2, [pc, #164] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001fbe: 69bb ldr r3, [r7, #24]
|
|
8001fc0: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001fc2: 4b28 ldr r3, [pc, #160] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001fc4: 685b ldr r3, [r3, #4]
|
|
8001fc6: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001fc8: 693b ldr r3, [r7, #16]
|
|
8001fca: 43db mvns r3, r3
|
|
8001fcc: 69ba ldr r2, [r7, #24]
|
|
8001fce: 4013 ands r3, r2
|
|
8001fd0: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001fd2: 683b ldr r3, [r7, #0]
|
|
8001fd4: 685b ldr r3, [r3, #4]
|
|
8001fd6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001fda: 2b00 cmp r3, #0
|
|
8001fdc: d003 beq.n 8001fe6 <HAL_GPIO_Init+0x2d6>
|
|
{
|
|
temp |= iocurrent;
|
|
8001fde: 69ba ldr r2, [r7, #24]
|
|
8001fe0: 693b ldr r3, [r7, #16]
|
|
8001fe2: 4313 orrs r3, r2
|
|
8001fe4: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8001fe6: 4a1f ldr r2, [pc, #124] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001fe8: 69bb ldr r3, [r7, #24]
|
|
8001fea: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8001fec: 4b1d ldr r3, [pc, #116] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8001fee: 681b ldr r3, [r3, #0]
|
|
8001ff0: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001ff2: 693b ldr r3, [r7, #16]
|
|
8001ff4: 43db mvns r3, r3
|
|
8001ff6: 69ba ldr r2, [r7, #24]
|
|
8001ff8: 4013 ands r3, r2
|
|
8001ffa: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001ffc: 683b ldr r3, [r7, #0]
|
|
8001ffe: 685b ldr r3, [r3, #4]
|
|
8002000: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002004: 2b00 cmp r3, #0
|
|
8002006: d003 beq.n 8002010 <HAL_GPIO_Init+0x300>
|
|
{
|
|
temp |= iocurrent;
|
|
8002008: 69ba ldr r2, [r7, #24]
|
|
800200a: 693b ldr r3, [r7, #16]
|
|
800200c: 4313 orrs r3, r2
|
|
800200e: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8002010: 4a14 ldr r2, [pc, #80] @ (8002064 <HAL_GPIO_Init+0x354>)
|
|
8002012: 69bb ldr r3, [r7, #24]
|
|
8002014: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8002016: 69fb ldr r3, [r7, #28]
|
|
8002018: 3301 adds r3, #1
|
|
800201a: 61fb str r3, [r7, #28]
|
|
800201c: 69fb ldr r3, [r7, #28]
|
|
800201e: 2b0f cmp r3, #15
|
|
8002020: f67f ae84 bls.w 8001d2c <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8002024: bf00 nop
|
|
8002026: bf00 nop
|
|
8002028: 3724 adds r7, #36 @ 0x24
|
|
800202a: 46bd mov sp, r7
|
|
800202c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002030: 4770 bx lr
|
|
8002032: bf00 nop
|
|
8002034: 40023800 .word 0x40023800
|
|
8002038: 40013800 .word 0x40013800
|
|
800203c: 40020000 .word 0x40020000
|
|
8002040: 40020400 .word 0x40020400
|
|
8002044: 40020800 .word 0x40020800
|
|
8002048: 40020c00 .word 0x40020c00
|
|
800204c: 40021000 .word 0x40021000
|
|
8002050: 40021400 .word 0x40021400
|
|
8002054: 40021800 .word 0x40021800
|
|
8002058: 40021c00 .word 0x40021c00
|
|
800205c: 40022000 .word 0x40022000
|
|
8002060: 40022400 .word 0x40022400
|
|
8002064: 40013c00 .word 0x40013c00
|
|
|
|
08002068 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8002068: b480 push {r7}
|
|
800206a: b083 sub sp, #12
|
|
800206c: af00 add r7, sp, #0
|
|
800206e: 6078 str r0, [r7, #4]
|
|
8002070: 460b mov r3, r1
|
|
8002072: 807b strh r3, [r7, #2]
|
|
8002074: 4613 mov r3, r2
|
|
8002076: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8002078: 787b ldrb r3, [r7, #1]
|
|
800207a: 2b00 cmp r3, #0
|
|
800207c: d003 beq.n 8002086 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
800207e: 887a ldrh r2, [r7, #2]
|
|
8002080: 687b ldr r3, [r7, #4]
|
|
8002082: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8002084: e003 b.n 800208e <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8002086: 887b ldrh r3, [r7, #2]
|
|
8002088: 041a lsls r2, r3, #16
|
|
800208a: 687b ldr r3, [r7, #4]
|
|
800208c: 619a str r2, [r3, #24]
|
|
}
|
|
800208e: bf00 nop
|
|
8002090: 370c adds r7, #12
|
|
8002092: 46bd mov sp, r7
|
|
8002094: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002098: 4770 bx lr
|
|
|
|
0800209a <HAL_GPIO_TogglePin>:
|
|
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
|
|
* @param GPIO_Pin Specifies the pins to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
800209a: b480 push {r7}
|
|
800209c: b085 sub sp, #20
|
|
800209e: af00 add r7, sp, #0
|
|
80020a0: 6078 str r0, [r7, #4]
|
|
80020a2: 460b mov r3, r1
|
|
80020a4: 807b strh r3, [r7, #2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Output Data Register value */
|
|
odr = GPIOx->ODR;
|
|
80020a6: 687b ldr r3, [r7, #4]
|
|
80020a8: 695b ldr r3, [r3, #20]
|
|
80020aa: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
80020ac: 887a ldrh r2, [r7, #2]
|
|
80020ae: 68fb ldr r3, [r7, #12]
|
|
80020b0: 4013 ands r3, r2
|
|
80020b2: 041a lsls r2, r3, #16
|
|
80020b4: 68fb ldr r3, [r7, #12]
|
|
80020b6: 43d9 mvns r1, r3
|
|
80020b8: 887b ldrh r3, [r7, #2]
|
|
80020ba: 400b ands r3, r1
|
|
80020bc: 431a orrs r2, r3
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
80020c0: 619a str r2, [r3, #24]
|
|
}
|
|
80020c2: bf00 nop
|
|
80020c4: 3714 adds r7, #20
|
|
80020c6: 46bd mov sp, r7
|
|
80020c8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80020cc: 4770 bx lr
|
|
|
|
080020ce <HAL_HCD_Init>:
|
|
* @brief Initialize the host driver.
|
|
* @param hhcd HCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
80020ce: b580 push {r7, lr}
|
|
80020d0: b086 sub sp, #24
|
|
80020d2: af02 add r7, sp, #8
|
|
80020d4: 6078 str r0, [r7, #4]
|
|
#if defined (USB_OTG_FS)
|
|
const USB_OTG_GlobalTypeDef *USBx;
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Check the HCD handle allocation */
|
|
if (hhcd == NULL)
|
|
80020d6: 687b ldr r3, [r7, #4]
|
|
80020d8: 2b00 cmp r3, #0
|
|
80020da: d101 bne.n 80020e0 <HAL_HCD_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80020dc: 2301 movs r3, #1
|
|
80020de: e059 b.n 8002194 <HAL_HCD_Init+0xc6>
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
|
|
|
|
#if defined (USB_OTG_FS)
|
|
USBx = hhcd->Instance;
|
|
80020e0: 687b ldr r3, [r7, #4]
|
|
80020e2: 681b ldr r3, [r3, #0]
|
|
80020e4: 60fb str r3, [r7, #12]
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
if (hhcd->State == HAL_HCD_STATE_RESET)
|
|
80020e6: 687b ldr r3, [r7, #4]
|
|
80020e8: f893 33d5 ldrb.w r3, [r3, #981] @ 0x3d5
|
|
80020ec: b2db uxtb r3, r3
|
|
80020ee: 2b00 cmp r3, #0
|
|
80020f0: d106 bne.n 8002100 <HAL_HCD_Init+0x32>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hhcd->Lock = HAL_UNLOCKED;
|
|
80020f2: 687b ldr r3, [r7, #4]
|
|
80020f4: 2200 movs r2, #0
|
|
80020f6: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
|
|
/* Init the low level hardware */
|
|
hhcd->MspInitCallback(hhcd);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_HCD_MspInit(hhcd);
|
|
80020fa: 6878 ldr r0, [r7, #4]
|
|
80020fc: f00a fbc6 bl 800c88c <HAL_HCD_MspInit>
|
|
#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
hhcd->State = HAL_HCD_STATE_BUSY;
|
|
8002100: 687b ldr r3, [r7, #4]
|
|
8002102: 2203 movs r2, #3
|
|
8002104: f883 23d5 strb.w r2, [r3, #981] @ 0x3d5
|
|
|
|
#if defined (USB_OTG_FS)
|
|
/* Disable DMA mode for FS instance */
|
|
if (USBx == USB_OTG_FS)
|
|
8002108: 68fb ldr r3, [r7, #12]
|
|
800210a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
|
|
800210e: d102 bne.n 8002116 <HAL_HCD_Init+0x48>
|
|
{
|
|
hhcd->Init.dma_enable = 0U;
|
|
8002110: 687b ldr r3, [r7, #4]
|
|
8002112: 2200 movs r2, #0
|
|
8002114: 719a strb r2, [r3, #6]
|
|
}
|
|
#endif /* defined (USB_OTG_FS) */
|
|
|
|
/* Disable the Interrupts */
|
|
__HAL_HCD_DISABLE(hhcd);
|
|
8002116: 687b ldr r3, [r7, #4]
|
|
8002118: 681b ldr r3, [r3, #0]
|
|
800211a: 4618 mov r0, r3
|
|
800211c: f004 fd6d bl 8006bfa <USB_DisableGlobalInt>
|
|
|
|
/* Init the Core (common init.) */
|
|
if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
|
|
8002120: 687b ldr r3, [r7, #4]
|
|
8002122: 6818 ldr r0, [r3, #0]
|
|
8002124: 687b ldr r3, [r7, #4]
|
|
8002126: 7c1a ldrb r2, [r3, #16]
|
|
8002128: f88d 2000 strb.w r2, [sp]
|
|
800212c: 3304 adds r3, #4
|
|
800212e: cb0e ldmia r3, {r1, r2, r3}
|
|
8002130: f004 fcee bl 8006b10 <USB_CoreInit>
|
|
8002134: 4603 mov r3, r0
|
|
8002136: 2b00 cmp r3, #0
|
|
8002138: d005 beq.n 8002146 <HAL_HCD_Init+0x78>
|
|
{
|
|
hhcd->State = HAL_HCD_STATE_ERROR;
|
|
800213a: 687b ldr r3, [r7, #4]
|
|
800213c: 2202 movs r2, #2
|
|
800213e: f883 23d5 strb.w r2, [r3, #981] @ 0x3d5
|
|
return HAL_ERROR;
|
|
8002142: 2301 movs r3, #1
|
|
8002144: e026 b.n 8002194 <HAL_HCD_Init+0xc6>
|
|
}
|
|
|
|
/* Force Host Mode */
|
|
if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
|
|
8002146: 687b ldr r3, [r7, #4]
|
|
8002148: 681b ldr r3, [r3, #0]
|
|
800214a: 2101 movs r1, #1
|
|
800214c: 4618 mov r0, r3
|
|
800214e: f004 fd65 bl 8006c1c <USB_SetCurrentMode>
|
|
8002152: 4603 mov r3, r0
|
|
8002154: 2b00 cmp r3, #0
|
|
8002156: d005 beq.n 8002164 <HAL_HCD_Init+0x96>
|
|
{
|
|
hhcd->State = HAL_HCD_STATE_ERROR;
|
|
8002158: 687b ldr r3, [r7, #4]
|
|
800215a: 2202 movs r2, #2
|
|
800215c: f883 23d5 strb.w r2, [r3, #981] @ 0x3d5
|
|
return HAL_ERROR;
|
|
8002160: 2301 movs r3, #1
|
|
8002162: e017 b.n 8002194 <HAL_HCD_Init+0xc6>
|
|
}
|
|
|
|
/* Init Host */
|
|
if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
|
|
8002164: 687b ldr r3, [r7, #4]
|
|
8002166: 6818 ldr r0, [r3, #0]
|
|
8002168: 687b ldr r3, [r7, #4]
|
|
800216a: 7c1a ldrb r2, [r3, #16]
|
|
800216c: f88d 2000 strb.w r2, [sp]
|
|
8002170: 3304 adds r3, #4
|
|
8002172: cb0e ldmia r3, {r1, r2, r3}
|
|
8002174: f004 ff0e bl 8006f94 <USB_HostInit>
|
|
8002178: 4603 mov r3, r0
|
|
800217a: 2b00 cmp r3, #0
|
|
800217c: d005 beq.n 800218a <HAL_HCD_Init+0xbc>
|
|
{
|
|
hhcd->State = HAL_HCD_STATE_ERROR;
|
|
800217e: 687b ldr r3, [r7, #4]
|
|
8002180: 2202 movs r2, #2
|
|
8002182: f883 23d5 strb.w r2, [r3, #981] @ 0x3d5
|
|
return HAL_ERROR;
|
|
8002186: 2301 movs r3, #1
|
|
8002188: e004 b.n 8002194 <HAL_HCD_Init+0xc6>
|
|
}
|
|
|
|
hhcd->State = HAL_HCD_STATE_READY;
|
|
800218a: 687b ldr r3, [r7, #4]
|
|
800218c: 2201 movs r2, #1
|
|
800218e: f883 23d5 strb.w r2, [r3, #981] @ 0x3d5
|
|
|
|
return HAL_OK;
|
|
8002192: 2300 movs r3, #0
|
|
}
|
|
8002194: 4618 mov r0, r3
|
|
8002196: 3710 adds r7, #16
|
|
8002198: 46bd mov sp, r7
|
|
800219a: bd80 pop {r7, pc}
|
|
|
|
0800219c <HAL_HCD_HC_Init>:
|
|
* This parameter can be a value from 0 to32K
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum,
|
|
uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
|
|
{
|
|
800219c: b590 push {r4, r7, lr}
|
|
800219e: b08b sub sp, #44 @ 0x2c
|
|
80021a0: af04 add r7, sp, #16
|
|
80021a2: 6078 str r0, [r7, #4]
|
|
80021a4: 4608 mov r0, r1
|
|
80021a6: 4611 mov r1, r2
|
|
80021a8: 461a mov r2, r3
|
|
80021aa: 4603 mov r3, r0
|
|
80021ac: 70fb strb r3, [r7, #3]
|
|
80021ae: 460b mov r3, r1
|
|
80021b0: 70bb strb r3, [r7, #2]
|
|
80021b2: 4613 mov r3, r2
|
|
80021b4: 707b strb r3, [r7, #1]
|
|
HAL_StatusTypeDef status;
|
|
uint32_t HostCoreSpeed;
|
|
uint32_t HCcharMps = mps;
|
|
80021b6: 8e3b ldrh r3, [r7, #48] @ 0x30
|
|
80021b8: 617b str r3, [r7, #20]
|
|
|
|
__HAL_LOCK(hhcd);
|
|
80021ba: 687b ldr r3, [r7, #4]
|
|
80021bc: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4
|
|
80021c0: 2b01 cmp r3, #1
|
|
80021c2: d101 bne.n 80021c8 <HAL_HCD_HC_Init+0x2c>
|
|
80021c4: 2302 movs r3, #2
|
|
80021c6: e09d b.n 8002304 <HAL_HCD_HC_Init+0x168>
|
|
80021c8: 687b ldr r3, [r7, #4]
|
|
80021ca: 2201 movs r2, #1
|
|
80021cc: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
hhcd->hc[ch_num].do_ping = 0U;
|
|
80021d0: 78fa ldrb r2, [r7, #3]
|
|
80021d2: 6879 ldr r1, [r7, #4]
|
|
80021d4: 4613 mov r3, r2
|
|
80021d6: 011b lsls r3, r3, #4
|
|
80021d8: 1a9b subs r3, r3, r2
|
|
80021da: 009b lsls r3, r3, #2
|
|
80021dc: 440b add r3, r1
|
|
80021de: 3319 adds r3, #25
|
|
80021e0: 2200 movs r2, #0
|
|
80021e2: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].dev_addr = dev_address;
|
|
80021e4: 78fa ldrb r2, [r7, #3]
|
|
80021e6: 6879 ldr r1, [r7, #4]
|
|
80021e8: 4613 mov r3, r2
|
|
80021ea: 011b lsls r3, r3, #4
|
|
80021ec: 1a9b subs r3, r3, r2
|
|
80021ee: 009b lsls r3, r3, #2
|
|
80021f0: 440b add r3, r1
|
|
80021f2: 3314 adds r3, #20
|
|
80021f4: 787a ldrb r2, [r7, #1]
|
|
80021f6: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].ch_num = ch_num;
|
|
80021f8: 78fa ldrb r2, [r7, #3]
|
|
80021fa: 6879 ldr r1, [r7, #4]
|
|
80021fc: 4613 mov r3, r2
|
|
80021fe: 011b lsls r3, r3, #4
|
|
8002200: 1a9b subs r3, r3, r2
|
|
8002202: 009b lsls r3, r3, #2
|
|
8002204: 440b add r3, r1
|
|
8002206: 3315 adds r3, #21
|
|
8002208: 78fa ldrb r2, [r7, #3]
|
|
800220a: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].ep_type = ep_type;
|
|
800220c: 78fa ldrb r2, [r7, #3]
|
|
800220e: 6879 ldr r1, [r7, #4]
|
|
8002210: 4613 mov r3, r2
|
|
8002212: 011b lsls r3, r3, #4
|
|
8002214: 1a9b subs r3, r3, r2
|
|
8002216: 009b lsls r3, r3, #2
|
|
8002218: 440b add r3, r1
|
|
800221a: 3326 adds r3, #38 @ 0x26
|
|
800221c: f897 202c ldrb.w r2, [r7, #44] @ 0x2c
|
|
8002220: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
|
|
8002222: 78fa ldrb r2, [r7, #3]
|
|
8002224: 78bb ldrb r3, [r7, #2]
|
|
8002226: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
800222a: b2d8 uxtb r0, r3
|
|
800222c: 6879 ldr r1, [r7, #4]
|
|
800222e: 4613 mov r3, r2
|
|
8002230: 011b lsls r3, r3, #4
|
|
8002232: 1a9b subs r3, r3, r2
|
|
8002234: 009b lsls r3, r3, #2
|
|
8002236: 440b add r3, r1
|
|
8002238: 3316 adds r3, #22
|
|
800223a: 4602 mov r2, r0
|
|
800223c: 701a strb r2, [r3, #0]
|
|
|
|
(void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
|
|
800223e: 78fb ldrb r3, [r7, #3]
|
|
8002240: 4619 mov r1, r3
|
|
8002242: 6878 ldr r0, [r7, #4]
|
|
8002244: f000 fba4 bl 8002990 <HAL_HCD_HC_ClearHubInfo>
|
|
|
|
if ((epnum & 0x80U) == 0x80U)
|
|
8002248: f997 3002 ldrsb.w r3, [r7, #2]
|
|
800224c: 2b00 cmp r3, #0
|
|
800224e: da0a bge.n 8002266 <HAL_HCD_HC_Init+0xca>
|
|
{
|
|
hhcd->hc[ch_num].ep_is_in = 1U;
|
|
8002250: 78fa ldrb r2, [r7, #3]
|
|
8002252: 6879 ldr r1, [r7, #4]
|
|
8002254: 4613 mov r3, r2
|
|
8002256: 011b lsls r3, r3, #4
|
|
8002258: 1a9b subs r3, r3, r2
|
|
800225a: 009b lsls r3, r3, #2
|
|
800225c: 440b add r3, r1
|
|
800225e: 3317 adds r3, #23
|
|
8002260: 2201 movs r2, #1
|
|
8002262: 701a strb r2, [r3, #0]
|
|
8002264: e009 b.n 800227a <HAL_HCD_HC_Init+0xde>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[ch_num].ep_is_in = 0U;
|
|
8002266: 78fa ldrb r2, [r7, #3]
|
|
8002268: 6879 ldr r1, [r7, #4]
|
|
800226a: 4613 mov r3, r2
|
|
800226c: 011b lsls r3, r3, #4
|
|
800226e: 1a9b subs r3, r3, r2
|
|
8002270: 009b lsls r3, r3, #2
|
|
8002272: 440b add r3, r1
|
|
8002274: 3317 adds r3, #23
|
|
8002276: 2200 movs r2, #0
|
|
8002278: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
|
|
800227a: 687b ldr r3, [r7, #4]
|
|
800227c: 681b ldr r3, [r3, #0]
|
|
800227e: 4618 mov r0, r3
|
|
8002280: f004 ffec bl 800725c <USB_GetHostSpeed>
|
|
8002284: 6138 str r0, [r7, #16]
|
|
|
|
if (ep_type == EP_TYPE_ISOC)
|
|
8002286: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
800228a: 2b01 cmp r3, #1
|
|
800228c: d10b bne.n 80022a6 <HAL_HCD_HC_Init+0x10a>
|
|
{
|
|
/* FS device plugged to HS HUB */
|
|
if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
|
|
800228e: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8002292: 2b01 cmp r3, #1
|
|
8002294: d107 bne.n 80022a6 <HAL_HCD_HC_Init+0x10a>
|
|
8002296: 693b ldr r3, [r7, #16]
|
|
8002298: 2b00 cmp r3, #0
|
|
800229a: d104 bne.n 80022a6 <HAL_HCD_HC_Init+0x10a>
|
|
{
|
|
if (HCcharMps > ISO_SPLT_MPS)
|
|
800229c: 697b ldr r3, [r7, #20]
|
|
800229e: 2bbc cmp r3, #188 @ 0xbc
|
|
80022a0: d901 bls.n 80022a6 <HAL_HCD_HC_Init+0x10a>
|
|
{
|
|
/* ISO Max Packet Size for Split mode */
|
|
HCcharMps = ISO_SPLT_MPS;
|
|
80022a2: 23bc movs r3, #188 @ 0xbc
|
|
80022a4: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
hhcd->hc[ch_num].speed = speed;
|
|
80022a6: 78fa ldrb r2, [r7, #3]
|
|
80022a8: 6879 ldr r1, [r7, #4]
|
|
80022aa: 4613 mov r3, r2
|
|
80022ac: 011b lsls r3, r3, #4
|
|
80022ae: 1a9b subs r3, r3, r2
|
|
80022b0: 009b lsls r3, r3, #2
|
|
80022b2: 440b add r3, r1
|
|
80022b4: 3318 adds r3, #24
|
|
80022b6: f897 2028 ldrb.w r2, [r7, #40] @ 0x28
|
|
80022ba: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
|
|
80022bc: 78fa ldrb r2, [r7, #3]
|
|
80022be: 697b ldr r3, [r7, #20]
|
|
80022c0: b298 uxth r0, r3
|
|
80022c2: 6879 ldr r1, [r7, #4]
|
|
80022c4: 4613 mov r3, r2
|
|
80022c6: 011b lsls r3, r3, #4
|
|
80022c8: 1a9b subs r3, r3, r2
|
|
80022ca: 009b lsls r3, r3, #2
|
|
80022cc: 440b add r3, r1
|
|
80022ce: 3328 adds r3, #40 @ 0x28
|
|
80022d0: 4602 mov r2, r0
|
|
80022d2: 801a strh r2, [r3, #0]
|
|
|
|
status = USB_HC_Init(hhcd->Instance, ch_num, epnum,
|
|
80022d4: 687b ldr r3, [r7, #4]
|
|
80022d6: 6818 ldr r0, [r3, #0]
|
|
80022d8: 697b ldr r3, [r7, #20]
|
|
80022da: b29b uxth r3, r3
|
|
80022dc: 787c ldrb r4, [r7, #1]
|
|
80022de: 78ba ldrb r2, [r7, #2]
|
|
80022e0: 78f9 ldrb r1, [r7, #3]
|
|
80022e2: 9302 str r3, [sp, #8]
|
|
80022e4: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
80022e8: 9301 str r3, [sp, #4]
|
|
80022ea: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
80022ee: 9300 str r3, [sp, #0]
|
|
80022f0: 4623 mov r3, r4
|
|
80022f2: f004 ffdb bl 80072ac <USB_HC_Init>
|
|
80022f6: 4603 mov r3, r0
|
|
80022f8: 73fb strb r3, [r7, #15]
|
|
dev_address, speed, ep_type, (uint16_t)HCcharMps);
|
|
|
|
__HAL_UNLOCK(hhcd);
|
|
80022fa: 687b ldr r3, [r7, #4]
|
|
80022fc: 2200 movs r2, #0
|
|
80022fe: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
|
|
return status;
|
|
8002302: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8002304: 4618 mov r0, r3
|
|
8002306: 371c adds r7, #28
|
|
8002308: 46bd mov sp, r7
|
|
800230a: bd90 pop {r4, r7, pc}
|
|
|
|
0800230c <HAL_HCD_HC_SubmitRequest>:
|
|
uint8_t ep_type,
|
|
uint8_t token,
|
|
uint8_t *pbuff,
|
|
uint16_t length,
|
|
uint8_t do_ping)
|
|
{
|
|
800230c: b580 push {r7, lr}
|
|
800230e: b082 sub sp, #8
|
|
8002310: af00 add r7, sp, #0
|
|
8002312: 6078 str r0, [r7, #4]
|
|
8002314: 4608 mov r0, r1
|
|
8002316: 4611 mov r1, r2
|
|
8002318: 461a mov r2, r3
|
|
800231a: 4603 mov r3, r0
|
|
800231c: 70fb strb r3, [r7, #3]
|
|
800231e: 460b mov r3, r1
|
|
8002320: 70bb strb r3, [r7, #2]
|
|
8002322: 4613 mov r3, r2
|
|
8002324: 707b strb r3, [r7, #1]
|
|
hhcd->hc[ch_num].ep_is_in = direction;
|
|
8002326: 78fa ldrb r2, [r7, #3]
|
|
8002328: 6879 ldr r1, [r7, #4]
|
|
800232a: 4613 mov r3, r2
|
|
800232c: 011b lsls r3, r3, #4
|
|
800232e: 1a9b subs r3, r3, r2
|
|
8002330: 009b lsls r3, r3, #2
|
|
8002332: 440b add r3, r1
|
|
8002334: 3317 adds r3, #23
|
|
8002336: 78ba ldrb r2, [r7, #2]
|
|
8002338: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].ep_type = ep_type;
|
|
800233a: 78fa ldrb r2, [r7, #3]
|
|
800233c: 6879 ldr r1, [r7, #4]
|
|
800233e: 4613 mov r3, r2
|
|
8002340: 011b lsls r3, r3, #4
|
|
8002342: 1a9b subs r3, r3, r2
|
|
8002344: 009b lsls r3, r3, #2
|
|
8002346: 440b add r3, r1
|
|
8002348: 3326 adds r3, #38 @ 0x26
|
|
800234a: 787a ldrb r2, [r7, #1]
|
|
800234c: 701a strb r2, [r3, #0]
|
|
|
|
if (token == 0U)
|
|
800234e: 7c3b ldrb r3, [r7, #16]
|
|
8002350: 2b00 cmp r3, #0
|
|
8002352: d114 bne.n 800237e <HAL_HCD_HC_SubmitRequest+0x72>
|
|
{
|
|
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
|
|
8002354: 78fa ldrb r2, [r7, #3]
|
|
8002356: 6879 ldr r1, [r7, #4]
|
|
8002358: 4613 mov r3, r2
|
|
800235a: 011b lsls r3, r3, #4
|
|
800235c: 1a9b subs r3, r3, r2
|
|
800235e: 009b lsls r3, r3, #2
|
|
8002360: 440b add r3, r1
|
|
8002362: 332a adds r3, #42 @ 0x2a
|
|
8002364: 2203 movs r2, #3
|
|
8002366: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].do_ping = do_ping;
|
|
8002368: 78fa ldrb r2, [r7, #3]
|
|
800236a: 6879 ldr r1, [r7, #4]
|
|
800236c: 4613 mov r3, r2
|
|
800236e: 011b lsls r3, r3, #4
|
|
8002370: 1a9b subs r3, r3, r2
|
|
8002372: 009b lsls r3, r3, #2
|
|
8002374: 440b add r3, r1
|
|
8002376: 3319 adds r3, #25
|
|
8002378: 7f3a ldrb r2, [r7, #28]
|
|
800237a: 701a strb r2, [r3, #0]
|
|
800237c: e009 b.n 8002392 <HAL_HCD_HC_SubmitRequest+0x86>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
800237e: 78fa ldrb r2, [r7, #3]
|
|
8002380: 6879 ldr r1, [r7, #4]
|
|
8002382: 4613 mov r3, r2
|
|
8002384: 011b lsls r3, r3, #4
|
|
8002386: 1a9b subs r3, r3, r2
|
|
8002388: 009b lsls r3, r3, #2
|
|
800238a: 440b add r3, r1
|
|
800238c: 332a adds r3, #42 @ 0x2a
|
|
800238e: 2202 movs r2, #2
|
|
8002390: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Manage Data Toggle */
|
|
switch (ep_type)
|
|
8002392: 787b ldrb r3, [r7, #1]
|
|
8002394: 2b03 cmp r3, #3
|
|
8002396: f200 8102 bhi.w 800259e <HAL_HCD_HC_SubmitRequest+0x292>
|
|
800239a: a201 add r2, pc, #4 @ (adr r2, 80023a0 <HAL_HCD_HC_SubmitRequest+0x94>)
|
|
800239c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80023a0: 080023b1 .word 0x080023b1
|
|
80023a4: 08002589 .word 0x08002589
|
|
80023a8: 08002475 .word 0x08002475
|
|
80023ac: 080024ff .word 0x080024ff
|
|
{
|
|
case EP_TYPE_CTRL:
|
|
if (token == 1U) /* send data */
|
|
80023b0: 7c3b ldrb r3, [r7, #16]
|
|
80023b2: 2b01 cmp r3, #1
|
|
80023b4: f040 80f5 bne.w 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
{
|
|
if (direction == 0U)
|
|
80023b8: 78bb ldrb r3, [r7, #2]
|
|
80023ba: 2b00 cmp r3, #0
|
|
80023bc: d12d bne.n 800241a <HAL_HCD_HC_SubmitRequest+0x10e>
|
|
{
|
|
if (length == 0U)
|
|
80023be: 8b3b ldrh r3, [r7, #24]
|
|
80023c0: 2b00 cmp r3, #0
|
|
80023c2: d109 bne.n 80023d8 <HAL_HCD_HC_SubmitRequest+0xcc>
|
|
{
|
|
/* For Status OUT stage, Length == 0U, Status Out PID = 1 */
|
|
hhcd->hc[ch_num].toggle_out = 1U;
|
|
80023c4: 78fa ldrb r2, [r7, #3]
|
|
80023c6: 6879 ldr r1, [r7, #4]
|
|
80023c8: 4613 mov r3, r2
|
|
80023ca: 011b lsls r3, r3, #4
|
|
80023cc: 1a9b subs r3, r3, r2
|
|
80023ce: 009b lsls r3, r3, #2
|
|
80023d0: 440b add r3, r1
|
|
80023d2: 333d adds r3, #61 @ 0x3d
|
|
80023d4: 2201 movs r2, #1
|
|
80023d6: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Set the Data Toggle bit as per the Flag */
|
|
if (hhcd->hc[ch_num].toggle_out == 0U)
|
|
80023d8: 78fa ldrb r2, [r7, #3]
|
|
80023da: 6879 ldr r1, [r7, #4]
|
|
80023dc: 4613 mov r3, r2
|
|
80023de: 011b lsls r3, r3, #4
|
|
80023e0: 1a9b subs r3, r3, r2
|
|
80023e2: 009b lsls r3, r3, #2
|
|
80023e4: 440b add r3, r1
|
|
80023e6: 333d adds r3, #61 @ 0x3d
|
|
80023e8: 781b ldrb r3, [r3, #0]
|
|
80023ea: 2b00 cmp r3, #0
|
|
80023ec: d10a bne.n 8002404 <HAL_HCD_HC_SubmitRequest+0xf8>
|
|
{
|
|
/* Put the PID 0 */
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
80023ee: 78fa ldrb r2, [r7, #3]
|
|
80023f0: 6879 ldr r1, [r7, #4]
|
|
80023f2: 4613 mov r3, r2
|
|
80023f4: 011b lsls r3, r3, #4
|
|
80023f6: 1a9b subs r3, r3, r2
|
|
80023f8: 009b lsls r3, r3, #2
|
|
80023fa: 440b add r3, r1
|
|
80023fc: 332a adds r3, #42 @ 0x2a
|
|
80023fe: 2200 movs r2, #0
|
|
8002400: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
8002402: e0ce b.n 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
8002404: 78fa ldrb r2, [r7, #3]
|
|
8002406: 6879 ldr r1, [r7, #4]
|
|
8002408: 4613 mov r3, r2
|
|
800240a: 011b lsls r3, r3, #4
|
|
800240c: 1a9b subs r3, r3, r2
|
|
800240e: 009b lsls r3, r3, #2
|
|
8002410: 440b add r3, r1
|
|
8002412: 332a adds r3, #42 @ 0x2a
|
|
8002414: 2202 movs r2, #2
|
|
8002416: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002418: e0c3 b.n 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
if (hhcd->hc[ch_num].do_ssplit == 1U)
|
|
800241a: 78fa ldrb r2, [r7, #3]
|
|
800241c: 6879 ldr r1, [r7, #4]
|
|
800241e: 4613 mov r3, r2
|
|
8002420: 011b lsls r3, r3, #4
|
|
8002422: 1a9b subs r3, r3, r2
|
|
8002424: 009b lsls r3, r3, #2
|
|
8002426: 440b add r3, r1
|
|
8002428: 331a adds r3, #26
|
|
800242a: 781b ldrb r3, [r3, #0]
|
|
800242c: 2b01 cmp r3, #1
|
|
800242e: f040 80b8 bne.w 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
if (hhcd->hc[ch_num].toggle_in == 0U)
|
|
8002432: 78fa ldrb r2, [r7, #3]
|
|
8002434: 6879 ldr r1, [r7, #4]
|
|
8002436: 4613 mov r3, r2
|
|
8002438: 011b lsls r3, r3, #4
|
|
800243a: 1a9b subs r3, r3, r2
|
|
800243c: 009b lsls r3, r3, #2
|
|
800243e: 440b add r3, r1
|
|
8002440: 333c adds r3, #60 @ 0x3c
|
|
8002442: 781b ldrb r3, [r3, #0]
|
|
8002444: 2b00 cmp r3, #0
|
|
8002446: d10a bne.n 800245e <HAL_HCD_HC_SubmitRequest+0x152>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
8002448: 78fa ldrb r2, [r7, #3]
|
|
800244a: 6879 ldr r1, [r7, #4]
|
|
800244c: 4613 mov r3, r2
|
|
800244e: 011b lsls r3, r3, #4
|
|
8002450: 1a9b subs r3, r3, r2
|
|
8002452: 009b lsls r3, r3, #2
|
|
8002454: 440b add r3, r1
|
|
8002456: 332a adds r3, #42 @ 0x2a
|
|
8002458: 2200 movs r2, #0
|
|
800245a: 701a strb r2, [r3, #0]
|
|
break;
|
|
800245c: e0a1 b.n 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
800245e: 78fa ldrb r2, [r7, #3]
|
|
8002460: 6879 ldr r1, [r7, #4]
|
|
8002462: 4613 mov r3, r2
|
|
8002464: 011b lsls r3, r3, #4
|
|
8002466: 1a9b subs r3, r3, r2
|
|
8002468: 009b lsls r3, r3, #2
|
|
800246a: 440b add r3, r1
|
|
800246c: 332a adds r3, #42 @ 0x2a
|
|
800246e: 2202 movs r2, #2
|
|
8002470: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002472: e096 b.n 80025a2 <HAL_HCD_HC_SubmitRequest+0x296>
|
|
|
|
case EP_TYPE_BULK:
|
|
if (direction == 0U)
|
|
8002474: 78bb ldrb r3, [r7, #2]
|
|
8002476: 2b00 cmp r3, #0
|
|
8002478: d120 bne.n 80024bc <HAL_HCD_HC_SubmitRequest+0x1b0>
|
|
{
|
|
/* Set the Data Toggle bit as per the Flag */
|
|
if (hhcd->hc[ch_num].toggle_out == 0U)
|
|
800247a: 78fa ldrb r2, [r7, #3]
|
|
800247c: 6879 ldr r1, [r7, #4]
|
|
800247e: 4613 mov r3, r2
|
|
8002480: 011b lsls r3, r3, #4
|
|
8002482: 1a9b subs r3, r3, r2
|
|
8002484: 009b lsls r3, r3, #2
|
|
8002486: 440b add r3, r1
|
|
8002488: 333d adds r3, #61 @ 0x3d
|
|
800248a: 781b ldrb r3, [r3, #0]
|
|
800248c: 2b00 cmp r3, #0
|
|
800248e: d10a bne.n 80024a6 <HAL_HCD_HC_SubmitRequest+0x19a>
|
|
{
|
|
/* Put the PID 0 */
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
8002490: 78fa ldrb r2, [r7, #3]
|
|
8002492: 6879 ldr r1, [r7, #4]
|
|
8002494: 4613 mov r3, r2
|
|
8002496: 011b lsls r3, r3, #4
|
|
8002498: 1a9b subs r3, r3, r2
|
|
800249a: 009b lsls r3, r3, #2
|
|
800249c: 440b add r3, r1
|
|
800249e: 332a adds r3, #42 @ 0x2a
|
|
80024a0: 2200 movs r2, #0
|
|
80024a2: 701a strb r2, [r3, #0]
|
|
{
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
}
|
|
}
|
|
|
|
break;
|
|
80024a4: e07e b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
80024a6: 78fa ldrb r2, [r7, #3]
|
|
80024a8: 6879 ldr r1, [r7, #4]
|
|
80024aa: 4613 mov r3, r2
|
|
80024ac: 011b lsls r3, r3, #4
|
|
80024ae: 1a9b subs r3, r3, r2
|
|
80024b0: 009b lsls r3, r3, #2
|
|
80024b2: 440b add r3, r1
|
|
80024b4: 332a adds r3, #42 @ 0x2a
|
|
80024b6: 2202 movs r2, #2
|
|
80024b8: 701a strb r2, [r3, #0]
|
|
break;
|
|
80024ba: e073 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
if (hhcd->hc[ch_num].toggle_in == 0U)
|
|
80024bc: 78fa ldrb r2, [r7, #3]
|
|
80024be: 6879 ldr r1, [r7, #4]
|
|
80024c0: 4613 mov r3, r2
|
|
80024c2: 011b lsls r3, r3, #4
|
|
80024c4: 1a9b subs r3, r3, r2
|
|
80024c6: 009b lsls r3, r3, #2
|
|
80024c8: 440b add r3, r1
|
|
80024ca: 333c adds r3, #60 @ 0x3c
|
|
80024cc: 781b ldrb r3, [r3, #0]
|
|
80024ce: 2b00 cmp r3, #0
|
|
80024d0: d10a bne.n 80024e8 <HAL_HCD_HC_SubmitRequest+0x1dc>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
80024d2: 78fa ldrb r2, [r7, #3]
|
|
80024d4: 6879 ldr r1, [r7, #4]
|
|
80024d6: 4613 mov r3, r2
|
|
80024d8: 011b lsls r3, r3, #4
|
|
80024da: 1a9b subs r3, r3, r2
|
|
80024dc: 009b lsls r3, r3, #2
|
|
80024de: 440b add r3, r1
|
|
80024e0: 332a adds r3, #42 @ 0x2a
|
|
80024e2: 2200 movs r2, #0
|
|
80024e4: 701a strb r2, [r3, #0]
|
|
break;
|
|
80024e6: e05d b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
80024e8: 78fa ldrb r2, [r7, #3]
|
|
80024ea: 6879 ldr r1, [r7, #4]
|
|
80024ec: 4613 mov r3, r2
|
|
80024ee: 011b lsls r3, r3, #4
|
|
80024f0: 1a9b subs r3, r3, r2
|
|
80024f2: 009b lsls r3, r3, #2
|
|
80024f4: 440b add r3, r1
|
|
80024f6: 332a adds r3, #42 @ 0x2a
|
|
80024f8: 2202 movs r2, #2
|
|
80024fa: 701a strb r2, [r3, #0]
|
|
break;
|
|
80024fc: e052 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
case EP_TYPE_INTR:
|
|
if (direction == 0U)
|
|
80024fe: 78bb ldrb r3, [r7, #2]
|
|
8002500: 2b00 cmp r3, #0
|
|
8002502: d120 bne.n 8002546 <HAL_HCD_HC_SubmitRequest+0x23a>
|
|
{
|
|
/* Set the Data Toggle bit as per the Flag */
|
|
if (hhcd->hc[ch_num].toggle_out == 0U)
|
|
8002504: 78fa ldrb r2, [r7, #3]
|
|
8002506: 6879 ldr r1, [r7, #4]
|
|
8002508: 4613 mov r3, r2
|
|
800250a: 011b lsls r3, r3, #4
|
|
800250c: 1a9b subs r3, r3, r2
|
|
800250e: 009b lsls r3, r3, #2
|
|
8002510: 440b add r3, r1
|
|
8002512: 333d adds r3, #61 @ 0x3d
|
|
8002514: 781b ldrb r3, [r3, #0]
|
|
8002516: 2b00 cmp r3, #0
|
|
8002518: d10a bne.n 8002530 <HAL_HCD_HC_SubmitRequest+0x224>
|
|
{
|
|
/* Put the PID 0 */
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
800251a: 78fa ldrb r2, [r7, #3]
|
|
800251c: 6879 ldr r1, [r7, #4]
|
|
800251e: 4613 mov r3, r2
|
|
8002520: 011b lsls r3, r3, #4
|
|
8002522: 1a9b subs r3, r3, r2
|
|
8002524: 009b lsls r3, r3, #2
|
|
8002526: 440b add r3, r1
|
|
8002528: 332a adds r3, #42 @ 0x2a
|
|
800252a: 2200 movs r2, #0
|
|
800252c: 701a strb r2, [r3, #0]
|
|
else
|
|
{
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
}
|
|
}
|
|
break;
|
|
800252e: e039 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
8002530: 78fa ldrb r2, [r7, #3]
|
|
8002532: 6879 ldr r1, [r7, #4]
|
|
8002534: 4613 mov r3, r2
|
|
8002536: 011b lsls r3, r3, #4
|
|
8002538: 1a9b subs r3, r3, r2
|
|
800253a: 009b lsls r3, r3, #2
|
|
800253c: 440b add r3, r1
|
|
800253e: 332a adds r3, #42 @ 0x2a
|
|
8002540: 2202 movs r2, #2
|
|
8002542: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002544: e02e b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
if (hhcd->hc[ch_num].toggle_in == 0U)
|
|
8002546: 78fa ldrb r2, [r7, #3]
|
|
8002548: 6879 ldr r1, [r7, #4]
|
|
800254a: 4613 mov r3, r2
|
|
800254c: 011b lsls r3, r3, #4
|
|
800254e: 1a9b subs r3, r3, r2
|
|
8002550: 009b lsls r3, r3, #2
|
|
8002552: 440b add r3, r1
|
|
8002554: 333c adds r3, #60 @ 0x3c
|
|
8002556: 781b ldrb r3, [r3, #0]
|
|
8002558: 2b00 cmp r3, #0
|
|
800255a: d10a bne.n 8002572 <HAL_HCD_HC_SubmitRequest+0x266>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
800255c: 78fa ldrb r2, [r7, #3]
|
|
800255e: 6879 ldr r1, [r7, #4]
|
|
8002560: 4613 mov r3, r2
|
|
8002562: 011b lsls r3, r3, #4
|
|
8002564: 1a9b subs r3, r3, r2
|
|
8002566: 009b lsls r3, r3, #2
|
|
8002568: 440b add r3, r1
|
|
800256a: 332a adds r3, #42 @ 0x2a
|
|
800256c: 2200 movs r2, #0
|
|
800256e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002570: e018 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
|
|
8002572: 78fa ldrb r2, [r7, #3]
|
|
8002574: 6879 ldr r1, [r7, #4]
|
|
8002576: 4613 mov r3, r2
|
|
8002578: 011b lsls r3, r3, #4
|
|
800257a: 1a9b subs r3, r3, r2
|
|
800257c: 009b lsls r3, r3, #2
|
|
800257e: 440b add r3, r1
|
|
8002580: 332a adds r3, #42 @ 0x2a
|
|
8002582: 2202 movs r2, #2
|
|
8002584: 701a strb r2, [r3, #0]
|
|
break;
|
|
8002586: e00d b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
|
|
case EP_TYPE_ISOC:
|
|
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
|
|
8002588: 78fa ldrb r2, [r7, #3]
|
|
800258a: 6879 ldr r1, [r7, #4]
|
|
800258c: 4613 mov r3, r2
|
|
800258e: 011b lsls r3, r3, #4
|
|
8002590: 1a9b subs r3, r3, r2
|
|
8002592: 009b lsls r3, r3, #2
|
|
8002594: 440b add r3, r1
|
|
8002596: 332a adds r3, #42 @ 0x2a
|
|
8002598: 2200 movs r2, #0
|
|
800259a: 701a strb r2, [r3, #0]
|
|
break;
|
|
800259c: e002 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
|
|
default:
|
|
break;
|
|
800259e: bf00 nop
|
|
80025a0: e000 b.n 80025a4 <HAL_HCD_HC_SubmitRequest+0x298>
|
|
break;
|
|
80025a2: bf00 nop
|
|
}
|
|
|
|
hhcd->hc[ch_num].xfer_buff = pbuff;
|
|
80025a4: 78fa ldrb r2, [r7, #3]
|
|
80025a6: 6879 ldr r1, [r7, #4]
|
|
80025a8: 4613 mov r3, r2
|
|
80025aa: 011b lsls r3, r3, #4
|
|
80025ac: 1a9b subs r3, r3, r2
|
|
80025ae: 009b lsls r3, r3, #2
|
|
80025b0: 440b add r3, r1
|
|
80025b2: 332c adds r3, #44 @ 0x2c
|
|
80025b4: 697a ldr r2, [r7, #20]
|
|
80025b6: 601a str r2, [r3, #0]
|
|
hhcd->hc[ch_num].xfer_len = length;
|
|
80025b8: 78fa ldrb r2, [r7, #3]
|
|
80025ba: 8b39 ldrh r1, [r7, #24]
|
|
80025bc: 6878 ldr r0, [r7, #4]
|
|
80025be: 4613 mov r3, r2
|
|
80025c0: 011b lsls r3, r3, #4
|
|
80025c2: 1a9b subs r3, r3, r2
|
|
80025c4: 009b lsls r3, r3, #2
|
|
80025c6: 4403 add r3, r0
|
|
80025c8: 3334 adds r3, #52 @ 0x34
|
|
80025ca: 6019 str r1, [r3, #0]
|
|
hhcd->hc[ch_num].urb_state = URB_IDLE;
|
|
80025cc: 78fa ldrb r2, [r7, #3]
|
|
80025ce: 6879 ldr r1, [r7, #4]
|
|
80025d0: 4613 mov r3, r2
|
|
80025d2: 011b lsls r3, r3, #4
|
|
80025d4: 1a9b subs r3, r3, r2
|
|
80025d6: 009b lsls r3, r3, #2
|
|
80025d8: 440b add r3, r1
|
|
80025da: 334c adds r3, #76 @ 0x4c
|
|
80025dc: 2200 movs r2, #0
|
|
80025de: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].xfer_count = 0U;
|
|
80025e0: 78fa ldrb r2, [r7, #3]
|
|
80025e2: 6879 ldr r1, [r7, #4]
|
|
80025e4: 4613 mov r3, r2
|
|
80025e6: 011b lsls r3, r3, #4
|
|
80025e8: 1a9b subs r3, r3, r2
|
|
80025ea: 009b lsls r3, r3, #2
|
|
80025ec: 440b add r3, r1
|
|
80025ee: 3338 adds r3, #56 @ 0x38
|
|
80025f0: 2200 movs r2, #0
|
|
80025f2: 601a str r2, [r3, #0]
|
|
hhcd->hc[ch_num].ch_num = ch_num;
|
|
80025f4: 78fa ldrb r2, [r7, #3]
|
|
80025f6: 6879 ldr r1, [r7, #4]
|
|
80025f8: 4613 mov r3, r2
|
|
80025fa: 011b lsls r3, r3, #4
|
|
80025fc: 1a9b subs r3, r3, r2
|
|
80025fe: 009b lsls r3, r3, #2
|
|
8002600: 440b add r3, r1
|
|
8002602: 3315 adds r3, #21
|
|
8002604: 78fa ldrb r2, [r7, #3]
|
|
8002606: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].state = HC_IDLE;
|
|
8002608: 78fa ldrb r2, [r7, #3]
|
|
800260a: 6879 ldr r1, [r7, #4]
|
|
800260c: 4613 mov r3, r2
|
|
800260e: 011b lsls r3, r3, #4
|
|
8002610: 1a9b subs r3, r3, r2
|
|
8002612: 009b lsls r3, r3, #2
|
|
8002614: 440b add r3, r1
|
|
8002616: 334d adds r3, #77 @ 0x4d
|
|
8002618: 2200 movs r2, #0
|
|
800261a: 701a strb r2, [r3, #0]
|
|
|
|
return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable);
|
|
800261c: 687b ldr r3, [r7, #4]
|
|
800261e: 6818 ldr r0, [r3, #0]
|
|
8002620: 78fa ldrb r2, [r7, #3]
|
|
8002622: 4613 mov r3, r2
|
|
8002624: 011b lsls r3, r3, #4
|
|
8002626: 1a9b subs r3, r3, r2
|
|
8002628: 009b lsls r3, r3, #2
|
|
800262a: 3310 adds r3, #16
|
|
800262c: 687a ldr r2, [r7, #4]
|
|
800262e: 4413 add r3, r2
|
|
8002630: 1d19 adds r1, r3, #4
|
|
8002632: 687b ldr r3, [r7, #4]
|
|
8002634: 799b ldrb r3, [r3, #6]
|
|
8002636: 461a mov r2, r3
|
|
8002638: f004 ff64 bl 8007504 <USB_HC_StartXfer>
|
|
800263c: 4603 mov r3, r0
|
|
}
|
|
800263e: 4618 mov r0, r3
|
|
8002640: 3708 adds r7, #8
|
|
8002642: 46bd mov sp, r7
|
|
8002644: bd80 pop {r7, pc}
|
|
8002646: bf00 nop
|
|
|
|
08002648 <HAL_HCD_IRQHandler>:
|
|
* @brief Handle HCD interrupt request.
|
|
* @param hhcd HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8002648: b580 push {r7, lr}
|
|
800264a: b086 sub sp, #24
|
|
800264c: af00 add r7, sp, #0
|
|
800264e: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8002650: 687b ldr r3, [r7, #4]
|
|
8002652: 681b ldr r3, [r3, #0]
|
|
8002654: 613b str r3, [r7, #16]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002656: 693b ldr r3, [r7, #16]
|
|
8002658: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
uint32_t interrupt;
|
|
|
|
/* Ensure that we are in device mode */
|
|
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
|
|
800265a: 687b ldr r3, [r7, #4]
|
|
800265c: 681b ldr r3, [r3, #0]
|
|
800265e: 4618 mov r0, r3
|
|
8002660: f004 fc52 bl 8006f08 <USB_GetMode>
|
|
8002664: 4603 mov r3, r0
|
|
8002666: 2b01 cmp r3, #1
|
|
8002668: f040 80fb bne.w 8002862 <HAL_HCD_IRQHandler+0x21a>
|
|
{
|
|
/* Avoid spurious interrupt */
|
|
if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
|
|
800266c: 687b ldr r3, [r7, #4]
|
|
800266e: 681b ldr r3, [r3, #0]
|
|
8002670: 4618 mov r0, r3
|
|
8002672: f004 fc15 bl 8006ea0 <USB_ReadInterrupts>
|
|
8002676: 4603 mov r3, r0
|
|
8002678: 2b00 cmp r3, #0
|
|
800267a: f000 80f1 beq.w 8002860 <HAL_HCD_IRQHandler+0x218>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
800267e: 687b ldr r3, [r7, #4]
|
|
8002680: 681b ldr r3, [r3, #0]
|
|
8002682: 4618 mov r0, r3
|
|
8002684: f004 fc0c bl 8006ea0 <USB_ReadInterrupts>
|
|
8002688: 4603 mov r3, r0
|
|
800268a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
800268e: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
8002692: d104 bne.n 800269e <HAL_HCD_IRQHandler+0x56>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
8002694: 687b ldr r3, [r7, #4]
|
|
8002696: 681b ldr r3, [r3, #0]
|
|
8002698: f44f 1200 mov.w r2, #2097152 @ 0x200000
|
|
800269c: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
800269e: 687b ldr r3, [r7, #4]
|
|
80026a0: 681b ldr r3, [r3, #0]
|
|
80026a2: 4618 mov r0, r3
|
|
80026a4: f004 fbfc bl 8006ea0 <USB_ReadInterrupts>
|
|
80026a8: 4603 mov r3, r0
|
|
80026aa: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80026ae: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
80026b2: d104 bne.n 80026be <HAL_HCD_IRQHandler+0x76>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
80026b4: 687b ldr r3, [r7, #4]
|
|
80026b6: 681b ldr r3, [r3, #0]
|
|
80026b8: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
80026bc: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
|
|
80026be: 687b ldr r3, [r7, #4]
|
|
80026c0: 681b ldr r3, [r3, #0]
|
|
80026c2: 4618 mov r0, r3
|
|
80026c4: f004 fbec bl 8006ea0 <USB_ReadInterrupts>
|
|
80026c8: 4603 mov r3, r0
|
|
80026ca: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
80026ce: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
80026d2: d104 bne.n 80026de <HAL_HCD_IRQHandler+0x96>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
|
|
80026d4: 687b ldr r3, [r7, #4]
|
|
80026d6: 681b ldr r3, [r3, #0]
|
|
80026d8: f04f 6280 mov.w r2, #67108864 @ 0x4000000
|
|
80026dc: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
|
|
80026de: 687b ldr r3, [r7, #4]
|
|
80026e0: 681b ldr r3, [r3, #0]
|
|
80026e2: 4618 mov r0, r3
|
|
80026e4: f004 fbdc bl 8006ea0 <USB_ReadInterrupts>
|
|
80026e8: 4603 mov r3, r0
|
|
80026ea: f003 0302 and.w r3, r3, #2
|
|
80026ee: 2b02 cmp r3, #2
|
|
80026f0: d103 bne.n 80026fa <HAL_HCD_IRQHandler+0xb2>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
|
|
80026f2: 687b ldr r3, [r7, #4]
|
|
80026f4: 681b ldr r3, [r3, #0]
|
|
80026f6: 2202 movs r2, #2
|
|
80026f8: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Host Disconnect Interrupts */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
|
|
80026fa: 687b ldr r3, [r7, #4]
|
|
80026fc: 681b ldr r3, [r3, #0]
|
|
80026fe: 4618 mov r0, r3
|
|
8002700: f004 fbce bl 8006ea0 <USB_ReadInterrupts>
|
|
8002704: 4603 mov r3, r0
|
|
8002706: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
800270a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800270e: d120 bne.n 8002752 <HAL_HCD_IRQHandler+0x10a>
|
|
{
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
|
|
8002710: 687b ldr r3, [r7, #4]
|
|
8002712: 681b ldr r3, [r3, #0]
|
|
8002714: f04f 5200 mov.w r2, #536870912 @ 0x20000000
|
|
8002718: 615a str r2, [r3, #20]
|
|
|
|
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
|
|
800271a: 68fb ldr r3, [r7, #12]
|
|
800271c: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8002720: 681b ldr r3, [r3, #0]
|
|
8002722: f003 0301 and.w r3, r3, #1
|
|
8002726: 2b00 cmp r3, #0
|
|
8002728: d113 bne.n 8002752 <HAL_HCD_IRQHandler+0x10a>
|
|
{
|
|
/* Flush USB Fifo */
|
|
(void)USB_FlushTxFifo(USBx, 0x10U);
|
|
800272a: 2110 movs r1, #16
|
|
800272c: 6938 ldr r0, [r7, #16]
|
|
800272e: f004 fac1 bl 8006cb4 <USB_FlushTxFifo>
|
|
(void)USB_FlushRxFifo(USBx);
|
|
8002732: 6938 ldr r0, [r7, #16]
|
|
8002734: f004 faf0 bl 8006d18 <USB_FlushRxFifo>
|
|
|
|
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
|
|
8002738: 687b ldr r3, [r7, #4]
|
|
800273a: 7a5b ldrb r3, [r3, #9]
|
|
800273c: 2b02 cmp r3, #2
|
|
800273e: d105 bne.n 800274c <HAL_HCD_IRQHandler+0x104>
|
|
{
|
|
/* Restore FS Clock */
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
|
|
8002740: 687b ldr r3, [r7, #4]
|
|
8002742: 681b ldr r3, [r3, #0]
|
|
8002744: 2101 movs r1, #1
|
|
8002746: 4618 mov r0, r3
|
|
8002748: f004 fce8 bl 800711c <USB_InitFSLSPClkSel>
|
|
|
|
/* Handle Host Port Disconnect Interrupt */
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->DisconnectCallback(hhcd);
|
|
#else
|
|
HAL_HCD_Disconnect_Callback(hhcd);
|
|
800274c: 6878 ldr r0, [r7, #4]
|
|
800274e: f00a f917 bl 800c980 <HAL_HCD_Disconnect_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Handle Host Port Interrupts */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
|
|
8002752: 687b ldr r3, [r7, #4]
|
|
8002754: 681b ldr r3, [r3, #0]
|
|
8002756: 4618 mov r0, r3
|
|
8002758: f004 fba2 bl 8006ea0 <USB_ReadInterrupts>
|
|
800275c: 4603 mov r3, r0
|
|
800275e: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
8002762: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8002766: d102 bne.n 800276e <HAL_HCD_IRQHandler+0x126>
|
|
{
|
|
HCD_Port_IRQHandler(hhcd);
|
|
8002768: 6878 ldr r0, [r7, #4]
|
|
800276a: f001 fd4d bl 8004208 <HCD_Port_IRQHandler>
|
|
}
|
|
|
|
/* Handle Host SOF Interrupt */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
|
|
800276e: 687b ldr r3, [r7, #4]
|
|
8002770: 681b ldr r3, [r3, #0]
|
|
8002772: 4618 mov r0, r3
|
|
8002774: f004 fb94 bl 8006ea0 <USB_ReadInterrupts>
|
|
8002778: 4603 mov r3, r0
|
|
800277a: f003 0308 and.w r3, r3, #8
|
|
800277e: 2b08 cmp r3, #8
|
|
8002780: d106 bne.n 8002790 <HAL_HCD_IRQHandler+0x148>
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->SOFCallback(hhcd);
|
|
#else
|
|
HAL_HCD_SOF_Callback(hhcd);
|
|
8002782: 6878 ldr r0, [r7, #4]
|
|
8002784: f00a f8e0 bl 800c948 <HAL_HCD_SOF_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
|
|
8002788: 687b ldr r3, [r7, #4]
|
|
800278a: 681b ldr r3, [r3, #0]
|
|
800278c: 2208 movs r2, #8
|
|
800278e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Host channel Interrupt */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
|
|
8002790: 687b ldr r3, [r7, #4]
|
|
8002792: 681b ldr r3, [r3, #0]
|
|
8002794: 4618 mov r0, r3
|
|
8002796: f004 fb83 bl 8006ea0 <USB_ReadInterrupts>
|
|
800279a: 4603 mov r3, r0
|
|
800279c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80027a0: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
80027a4: d139 bne.n 800281a <HAL_HCD_IRQHandler+0x1d2>
|
|
{
|
|
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
|
|
80027a6: 687b ldr r3, [r7, #4]
|
|
80027a8: 681b ldr r3, [r3, #0]
|
|
80027aa: 4618 mov r0, r3
|
|
80027ac: f005 f924 bl 80079f8 <USB_HC_ReadInterrupt>
|
|
80027b0: 60b8 str r0, [r7, #8]
|
|
for (i = 0U; i < hhcd->Init.Host_channels; i++)
|
|
80027b2: 2300 movs r3, #0
|
|
80027b4: 617b str r3, [r7, #20]
|
|
80027b6: e025 b.n 8002804 <HAL_HCD_IRQHandler+0x1bc>
|
|
{
|
|
if ((interrupt & (1UL << (i & 0xFU))) != 0U)
|
|
80027b8: 697b ldr r3, [r7, #20]
|
|
80027ba: f003 030f and.w r3, r3, #15
|
|
80027be: 68ba ldr r2, [r7, #8]
|
|
80027c0: fa22 f303 lsr.w r3, r2, r3
|
|
80027c4: f003 0301 and.w r3, r3, #1
|
|
80027c8: 2b00 cmp r3, #0
|
|
80027ca: d018 beq.n 80027fe <HAL_HCD_IRQHandler+0x1b6>
|
|
{
|
|
if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
|
|
80027cc: 697b ldr r3, [r7, #20]
|
|
80027ce: 015a lsls r2, r3, #5
|
|
80027d0: 68fb ldr r3, [r7, #12]
|
|
80027d2: 4413 add r3, r2
|
|
80027d4: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80027d8: 681b ldr r3, [r3, #0]
|
|
80027da: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80027de: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80027e2: d106 bne.n 80027f2 <HAL_HCD_IRQHandler+0x1aa>
|
|
{
|
|
HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
|
|
80027e4: 697b ldr r3, [r7, #20]
|
|
80027e6: b2db uxtb r3, r3
|
|
80027e8: 4619 mov r1, r3
|
|
80027ea: 6878 ldr r0, [r7, #4]
|
|
80027ec: f000 f905 bl 80029fa <HCD_HC_IN_IRQHandler>
|
|
80027f0: e005 b.n 80027fe <HAL_HCD_IRQHandler+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
|
|
80027f2: 697b ldr r3, [r7, #20]
|
|
80027f4: b2db uxtb r3, r3
|
|
80027f6: 4619 mov r1, r3
|
|
80027f8: 6878 ldr r0, [r7, #4]
|
|
80027fa: f000 ff67 bl 80036cc <HCD_HC_OUT_IRQHandler>
|
|
for (i = 0U; i < hhcd->Init.Host_channels; i++)
|
|
80027fe: 697b ldr r3, [r7, #20]
|
|
8002800: 3301 adds r3, #1
|
|
8002802: 617b str r3, [r7, #20]
|
|
8002804: 687b ldr r3, [r7, #4]
|
|
8002806: 795b ldrb r3, [r3, #5]
|
|
8002808: 461a mov r2, r3
|
|
800280a: 697b ldr r3, [r7, #20]
|
|
800280c: 4293 cmp r3, r2
|
|
800280e: d3d3 bcc.n 80027b8 <HAL_HCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
}
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
|
|
8002810: 687b ldr r3, [r7, #4]
|
|
8002812: 681b ldr r3, [r3, #0]
|
|
8002814: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
8002818: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Rx Queue Level Interrupts */
|
|
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
|
800281a: 687b ldr r3, [r7, #4]
|
|
800281c: 681b ldr r3, [r3, #0]
|
|
800281e: 4618 mov r0, r3
|
|
8002820: f004 fb3e bl 8006ea0 <USB_ReadInterrupts>
|
|
8002824: 4603 mov r3, r0
|
|
8002826: f003 0310 and.w r3, r3, #16
|
|
800282a: 2b10 cmp r3, #16
|
|
800282c: d101 bne.n 8002832 <HAL_HCD_IRQHandler+0x1ea>
|
|
800282e: 2301 movs r3, #1
|
|
8002830: e000 b.n 8002834 <HAL_HCD_IRQHandler+0x1ec>
|
|
8002832: 2300 movs r3, #0
|
|
8002834: 2b00 cmp r3, #0
|
|
8002836: d014 beq.n 8002862 <HAL_HCD_IRQHandler+0x21a>
|
|
{
|
|
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
8002838: 687b ldr r3, [r7, #4]
|
|
800283a: 681b ldr r3, [r3, #0]
|
|
800283c: 699a ldr r2, [r3, #24]
|
|
800283e: 687b ldr r3, [r7, #4]
|
|
8002840: 681b ldr r3, [r3, #0]
|
|
8002842: f022 0210 bic.w r2, r2, #16
|
|
8002846: 619a str r2, [r3, #24]
|
|
|
|
HCD_RXQLVL_IRQHandler(hhcd);
|
|
8002848: 6878 ldr r0, [r7, #4]
|
|
800284a: f001 fbfe bl 800404a <HCD_RXQLVL_IRQHandler>
|
|
|
|
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
800284e: 687b ldr r3, [r7, #4]
|
|
8002850: 681b ldr r3, [r3, #0]
|
|
8002852: 699a ldr r2, [r3, #24]
|
|
8002854: 687b ldr r3, [r7, #4]
|
|
8002856: 681b ldr r3, [r3, #0]
|
|
8002858: f042 0210 orr.w r2, r2, #16
|
|
800285c: 619a str r2, [r3, #24]
|
|
800285e: e000 b.n 8002862 <HAL_HCD_IRQHandler+0x21a>
|
|
return;
|
|
8002860: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
8002862: 3718 adds r7, #24
|
|
8002864: 46bd mov sp, r7
|
|
8002866: bd80 pop {r7, pc}
|
|
|
|
08002868 <HAL_HCD_Start>:
|
|
* @brief Start the host driver.
|
|
* @param hhcd HCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8002868: b580 push {r7, lr}
|
|
800286a: b082 sub sp, #8
|
|
800286c: af00 add r7, sp, #0
|
|
800286e: 6078 str r0, [r7, #4]
|
|
__HAL_LOCK(hhcd);
|
|
8002870: 687b ldr r3, [r7, #4]
|
|
8002872: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4
|
|
8002876: 2b01 cmp r3, #1
|
|
8002878: d101 bne.n 800287e <HAL_HCD_Start+0x16>
|
|
800287a: 2302 movs r3, #2
|
|
800287c: e013 b.n 80028a6 <HAL_HCD_Start+0x3e>
|
|
800287e: 687b ldr r3, [r7, #4]
|
|
8002880: 2201 movs r2, #1
|
|
8002882: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
/* Enable port power */
|
|
(void)USB_DriveVbus(hhcd->Instance, 1U);
|
|
8002886: 687b ldr r3, [r7, #4]
|
|
8002888: 681b ldr r3, [r3, #0]
|
|
800288a: 2101 movs r1, #1
|
|
800288c: 4618 mov r0, r3
|
|
800288e: f004 fcac bl 80071ea <USB_DriveVbus>
|
|
|
|
/* Enable global interrupt */
|
|
__HAL_HCD_ENABLE(hhcd);
|
|
8002892: 687b ldr r3, [r7, #4]
|
|
8002894: 681b ldr r3, [r3, #0]
|
|
8002896: 4618 mov r0, r3
|
|
8002898: f004 f99e bl 8006bd8 <USB_EnableGlobalInt>
|
|
__HAL_UNLOCK(hhcd);
|
|
800289c: 687b ldr r3, [r7, #4]
|
|
800289e: 2200 movs r2, #0
|
|
80028a0: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
|
|
return HAL_OK;
|
|
80028a4: 2300 movs r3, #0
|
|
}
|
|
80028a6: 4618 mov r0, r3
|
|
80028a8: 3708 adds r7, #8
|
|
80028aa: 46bd mov sp, r7
|
|
80028ac: bd80 pop {r7, pc}
|
|
|
|
080028ae <HAL_HCD_Stop>:
|
|
* @param hhcd HCD handle
|
|
* @retval HAL status
|
|
*/
|
|
|
|
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
80028ae: b580 push {r7, lr}
|
|
80028b0: b082 sub sp, #8
|
|
80028b2: af00 add r7, sp, #0
|
|
80028b4: 6078 str r0, [r7, #4]
|
|
__HAL_LOCK(hhcd);
|
|
80028b6: 687b ldr r3, [r7, #4]
|
|
80028b8: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4
|
|
80028bc: 2b01 cmp r3, #1
|
|
80028be: d101 bne.n 80028c4 <HAL_HCD_Stop+0x16>
|
|
80028c0: 2302 movs r3, #2
|
|
80028c2: e00d b.n 80028e0 <HAL_HCD_Stop+0x32>
|
|
80028c4: 687b ldr r3, [r7, #4]
|
|
80028c6: 2201 movs r2, #1
|
|
80028c8: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
(void)USB_StopHost(hhcd->Instance);
|
|
80028cc: 687b ldr r3, [r7, #4]
|
|
80028ce: 681b ldr r3, [r3, #0]
|
|
80028d0: 4618 mov r0, r3
|
|
80028d2: f005 f9ff bl 8007cd4 <USB_StopHost>
|
|
__HAL_UNLOCK(hhcd);
|
|
80028d6: 687b ldr r3, [r7, #4]
|
|
80028d8: 2200 movs r2, #0
|
|
80028da: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
|
|
return HAL_OK;
|
|
80028de: 2300 movs r3, #0
|
|
}
|
|
80028e0: 4618 mov r0, r3
|
|
80028e2: 3708 adds r7, #8
|
|
80028e4: 46bd mov sp, r7
|
|
80028e6: bd80 pop {r7, pc}
|
|
|
|
080028e8 <HAL_HCD_ResetPort>:
|
|
* @brief Reset the host port.
|
|
* @param hhcd HCD handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
80028e8: b580 push {r7, lr}
|
|
80028ea: b082 sub sp, #8
|
|
80028ec: af00 add r7, sp, #0
|
|
80028ee: 6078 str r0, [r7, #4]
|
|
return (USB_ResetPort(hhcd->Instance));
|
|
80028f0: 687b ldr r3, [r7, #4]
|
|
80028f2: 681b ldr r3, [r3, #0]
|
|
80028f4: 4618 mov r0, r3
|
|
80028f6: f004 fc4e bl 8007196 <USB_ResetPort>
|
|
80028fa: 4603 mov r3, r0
|
|
}
|
|
80028fc: 4618 mov r0, r3
|
|
80028fe: 3708 adds r7, #8
|
|
8002900: 46bd mov sp, r7
|
|
8002902: bd80 pop {r7, pc}
|
|
|
|
08002904 <HAL_HCD_HC_GetURBState>:
|
|
* URB_NYET/
|
|
* URB_ERROR/
|
|
* URB_STALL
|
|
*/
|
|
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
|
|
{
|
|
8002904: b480 push {r7}
|
|
8002906: b083 sub sp, #12
|
|
8002908: af00 add r7, sp, #0
|
|
800290a: 6078 str r0, [r7, #4]
|
|
800290c: 460b mov r3, r1
|
|
800290e: 70fb strb r3, [r7, #3]
|
|
return hhcd->hc[chnum].urb_state;
|
|
8002910: 78fa ldrb r2, [r7, #3]
|
|
8002912: 6879 ldr r1, [r7, #4]
|
|
8002914: 4613 mov r3, r2
|
|
8002916: 011b lsls r3, r3, #4
|
|
8002918: 1a9b subs r3, r3, r2
|
|
800291a: 009b lsls r3, r3, #2
|
|
800291c: 440b add r3, r1
|
|
800291e: 334c adds r3, #76 @ 0x4c
|
|
8002920: 781b ldrb r3, [r3, #0]
|
|
}
|
|
8002922: 4618 mov r0, r3
|
|
8002924: 370c adds r7, #12
|
|
8002926: 46bd mov sp, r7
|
|
8002928: f85d 7b04 ldr.w r7, [sp], #4
|
|
800292c: 4770 bx lr
|
|
|
|
0800292e <HAL_HCD_HC_GetXferCount>:
|
|
* @param chnum Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval last transfer size in byte
|
|
*/
|
|
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
|
|
{
|
|
800292e: b480 push {r7}
|
|
8002930: b083 sub sp, #12
|
|
8002932: af00 add r7, sp, #0
|
|
8002934: 6078 str r0, [r7, #4]
|
|
8002936: 460b mov r3, r1
|
|
8002938: 70fb strb r3, [r7, #3]
|
|
return hhcd->hc[chnum].xfer_count;
|
|
800293a: 78fa ldrb r2, [r7, #3]
|
|
800293c: 6879 ldr r1, [r7, #4]
|
|
800293e: 4613 mov r3, r2
|
|
8002940: 011b lsls r3, r3, #4
|
|
8002942: 1a9b subs r3, r3, r2
|
|
8002944: 009b lsls r3, r3, #2
|
|
8002946: 440b add r3, r1
|
|
8002948: 3338 adds r3, #56 @ 0x38
|
|
800294a: 681b ldr r3, [r3, #0]
|
|
}
|
|
800294c: 4618 mov r0, r3
|
|
800294e: 370c adds r7, #12
|
|
8002950: 46bd mov sp, r7
|
|
8002952: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002956: 4770 bx lr
|
|
|
|
08002958 <HAL_HCD_GetCurrentFrame>:
|
|
* @brief Return the current Host frame number.
|
|
* @param hhcd HCD handle
|
|
* @retval Current Host frame number
|
|
*/
|
|
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8002958: b580 push {r7, lr}
|
|
800295a: b082 sub sp, #8
|
|
800295c: af00 add r7, sp, #0
|
|
800295e: 6078 str r0, [r7, #4]
|
|
return (USB_GetCurrentFrame(hhcd->Instance));
|
|
8002960: 687b ldr r3, [r7, #4]
|
|
8002962: 681b ldr r3, [r3, #0]
|
|
8002964: 4618 mov r0, r3
|
|
8002966: f004 fc90 bl 800728a <USB_GetCurrentFrame>
|
|
800296a: 4603 mov r3, r0
|
|
}
|
|
800296c: 4618 mov r0, r3
|
|
800296e: 3708 adds r7, #8
|
|
8002970: 46bd mov sp, r7
|
|
8002972: bd80 pop {r7, pc}
|
|
|
|
08002974 <HAL_HCD_GetCurrentSpeed>:
|
|
* @brief Return the Host enumeration speed.
|
|
* @param hhcd HCD handle
|
|
* @retval Enumeration speed
|
|
*/
|
|
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8002974: b580 push {r7, lr}
|
|
8002976: b082 sub sp, #8
|
|
8002978: af00 add r7, sp, #0
|
|
800297a: 6078 str r0, [r7, #4]
|
|
return (USB_GetHostSpeed(hhcd->Instance));
|
|
800297c: 687b ldr r3, [r7, #4]
|
|
800297e: 681b ldr r3, [r3, #0]
|
|
8002980: 4618 mov r0, r3
|
|
8002982: f004 fc6b bl 800725c <USB_GetHostSpeed>
|
|
8002986: 4603 mov r3, r0
|
|
}
|
|
8002988: 4618 mov r0, r3
|
|
800298a: 3708 adds r7, #8
|
|
800298c: 46bd mov sp, r7
|
|
800298e: bd80 pop {r7, pc}
|
|
|
|
08002990 <HAL_HCD_HC_ClearHubInfo>:
|
|
* @param ch_num Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
|
|
{
|
|
8002990: b480 push {r7}
|
|
8002992: b083 sub sp, #12
|
|
8002994: af00 add r7, sp, #0
|
|
8002996: 6078 str r0, [r7, #4]
|
|
8002998: 460b mov r3, r1
|
|
800299a: 70fb strb r3, [r7, #3]
|
|
hhcd->hc[ch_num].do_ssplit = 0U;
|
|
800299c: 78fa ldrb r2, [r7, #3]
|
|
800299e: 6879 ldr r1, [r7, #4]
|
|
80029a0: 4613 mov r3, r2
|
|
80029a2: 011b lsls r3, r3, #4
|
|
80029a4: 1a9b subs r3, r3, r2
|
|
80029a6: 009b lsls r3, r3, #2
|
|
80029a8: 440b add r3, r1
|
|
80029aa: 331a adds r3, #26
|
|
80029ac: 2200 movs r2, #0
|
|
80029ae: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].do_csplit = 0U;
|
|
80029b0: 78fa ldrb r2, [r7, #3]
|
|
80029b2: 6879 ldr r1, [r7, #4]
|
|
80029b4: 4613 mov r3, r2
|
|
80029b6: 011b lsls r3, r3, #4
|
|
80029b8: 1a9b subs r3, r3, r2
|
|
80029ba: 009b lsls r3, r3, #2
|
|
80029bc: 440b add r3, r1
|
|
80029be: 331b adds r3, #27
|
|
80029c0: 2200 movs r2, #0
|
|
80029c2: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].hub_addr = 0U;
|
|
80029c4: 78fa ldrb r2, [r7, #3]
|
|
80029c6: 6879 ldr r1, [r7, #4]
|
|
80029c8: 4613 mov r3, r2
|
|
80029ca: 011b lsls r3, r3, #4
|
|
80029cc: 1a9b subs r3, r3, r2
|
|
80029ce: 009b lsls r3, r3, #2
|
|
80029d0: 440b add r3, r1
|
|
80029d2: 3325 adds r3, #37 @ 0x25
|
|
80029d4: 2200 movs r2, #0
|
|
80029d6: 701a strb r2, [r3, #0]
|
|
hhcd->hc[ch_num].hub_port_nbr = 0U;
|
|
80029d8: 78fa ldrb r2, [r7, #3]
|
|
80029da: 6879 ldr r1, [r7, #4]
|
|
80029dc: 4613 mov r3, r2
|
|
80029de: 011b lsls r3, r3, #4
|
|
80029e0: 1a9b subs r3, r3, r2
|
|
80029e2: 009b lsls r3, r3, #2
|
|
80029e4: 440b add r3, r1
|
|
80029e6: 3324 adds r3, #36 @ 0x24
|
|
80029e8: 2200 movs r2, #0
|
|
80029ea: 701a strb r2, [r3, #0]
|
|
|
|
return HAL_OK;
|
|
80029ec: 2300 movs r3, #0
|
|
}
|
|
80029ee: 4618 mov r0, r3
|
|
80029f0: 370c adds r7, #12
|
|
80029f2: 46bd mov sp, r7
|
|
80029f4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80029f8: 4770 bx lr
|
|
|
|
080029fa <HCD_HC_IN_IRQHandler>:
|
|
* @param chnum Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval none
|
|
*/
|
|
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|
{
|
|
80029fa: b580 push {r7, lr}
|
|
80029fc: b086 sub sp, #24
|
|
80029fe: af00 add r7, sp, #0
|
|
8002a00: 6078 str r0, [r7, #4]
|
|
8002a02: 460b mov r3, r1
|
|
8002a04: 70fb strb r3, [r7, #3]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8002a06: 687b ldr r3, [r7, #4]
|
|
8002a08: 681b ldr r3, [r3, #0]
|
|
8002a0a: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002a0c: 697b ldr r3, [r7, #20]
|
|
8002a0e: 613b str r3, [r7, #16]
|
|
uint32_t tmpreg;
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
|
|
8002a10: 687b ldr r3, [r7, #4]
|
|
8002a12: 681b ldr r3, [r3, #0]
|
|
8002a14: 78fa ldrb r2, [r7, #3]
|
|
8002a16: 4611 mov r1, r2
|
|
8002a18: 4618 mov r0, r3
|
|
8002a1a: f004 fa54 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002a1e: 4603 mov r3, r0
|
|
8002a20: f003 0304 and.w r3, r3, #4
|
|
8002a24: 2b04 cmp r3, #4
|
|
8002a26: d11a bne.n 8002a5e <HCD_HC_IN_IRQHandler+0x64>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
|
|
8002a28: 78fb ldrb r3, [r7, #3]
|
|
8002a2a: 015a lsls r2, r3, #5
|
|
8002a2c: 693b ldr r3, [r7, #16]
|
|
8002a2e: 4413 add r3, r2
|
|
8002a30: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002a34: 461a mov r2, r3
|
|
8002a36: 2304 movs r3, #4
|
|
8002a38: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8002a3a: 78fa ldrb r2, [r7, #3]
|
|
8002a3c: 6879 ldr r1, [r7, #4]
|
|
8002a3e: 4613 mov r3, r2
|
|
8002a40: 011b lsls r3, r3, #4
|
|
8002a42: 1a9b subs r3, r3, r2
|
|
8002a44: 009b lsls r3, r3, #2
|
|
8002a46: 440b add r3, r1
|
|
8002a48: 334d adds r3, #77 @ 0x4d
|
|
8002a4a: 2207 movs r2, #7
|
|
8002a4c: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002a4e: 687b ldr r3, [r7, #4]
|
|
8002a50: 681b ldr r3, [r3, #0]
|
|
8002a52: 78fa ldrb r2, [r7, #3]
|
|
8002a54: 4611 mov r1, r2
|
|
8002a56: 4618 mov r0, r3
|
|
8002a58: f004 ffdf bl 8007a1a <USB_HC_Halt>
|
|
8002a5c: e09e b.n 8002b9c <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
|
|
8002a5e: 687b ldr r3, [r7, #4]
|
|
8002a60: 681b ldr r3, [r3, #0]
|
|
8002a62: 78fa ldrb r2, [r7, #3]
|
|
8002a64: 4611 mov r1, r2
|
|
8002a66: 4618 mov r0, r3
|
|
8002a68: f004 fa2d bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002a6c: 4603 mov r3, r0
|
|
8002a6e: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8002a72: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
8002a76: d11b bne.n 8002ab0 <HCD_HC_IN_IRQHandler+0xb6>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
|
|
8002a78: 78fb ldrb r3, [r7, #3]
|
|
8002a7a: 015a lsls r2, r3, #5
|
|
8002a7c: 693b ldr r3, [r7, #16]
|
|
8002a7e: 4413 add r3, r2
|
|
8002a80: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002a84: 461a mov r2, r3
|
|
8002a86: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8002a8a: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_BBLERR;
|
|
8002a8c: 78fa ldrb r2, [r7, #3]
|
|
8002a8e: 6879 ldr r1, [r7, #4]
|
|
8002a90: 4613 mov r3, r2
|
|
8002a92: 011b lsls r3, r3, #4
|
|
8002a94: 1a9b subs r3, r3, r2
|
|
8002a96: 009b lsls r3, r3, #2
|
|
8002a98: 440b add r3, r1
|
|
8002a9a: 334d adds r3, #77 @ 0x4d
|
|
8002a9c: 2208 movs r2, #8
|
|
8002a9e: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002aa0: 687b ldr r3, [r7, #4]
|
|
8002aa2: 681b ldr r3, [r3, #0]
|
|
8002aa4: 78fa ldrb r2, [r7, #3]
|
|
8002aa6: 4611 mov r1, r2
|
|
8002aa8: 4618 mov r0, r3
|
|
8002aaa: f004 ffb6 bl 8007a1a <USB_HC_Halt>
|
|
8002aae: e075 b.n 8002b9c <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
|
|
8002ab0: 687b ldr r3, [r7, #4]
|
|
8002ab2: 681b ldr r3, [r3, #0]
|
|
8002ab4: 78fa ldrb r2, [r7, #3]
|
|
8002ab6: 4611 mov r1, r2
|
|
8002ab8: 4618 mov r0, r3
|
|
8002aba: f004 fa04 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002abe: 4603 mov r3, r0
|
|
8002ac0: f003 0308 and.w r3, r3, #8
|
|
8002ac4: 2b08 cmp r3, #8
|
|
8002ac6: d11a bne.n 8002afe <HCD_HC_IN_IRQHandler+0x104>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
|
|
8002ac8: 78fb ldrb r3, [r7, #3]
|
|
8002aca: 015a lsls r2, r3, #5
|
|
8002acc: 693b ldr r3, [r7, #16]
|
|
8002ace: 4413 add r3, r2
|
|
8002ad0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002ad4: 461a mov r2, r3
|
|
8002ad6: 2308 movs r3, #8
|
|
8002ad8: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_STALL;
|
|
8002ada: 78fa ldrb r2, [r7, #3]
|
|
8002adc: 6879 ldr r1, [r7, #4]
|
|
8002ade: 4613 mov r3, r2
|
|
8002ae0: 011b lsls r3, r3, #4
|
|
8002ae2: 1a9b subs r3, r3, r2
|
|
8002ae4: 009b lsls r3, r3, #2
|
|
8002ae6: 440b add r3, r1
|
|
8002ae8: 334d adds r3, #77 @ 0x4d
|
|
8002aea: 2206 movs r2, #6
|
|
8002aec: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002aee: 687b ldr r3, [r7, #4]
|
|
8002af0: 681b ldr r3, [r3, #0]
|
|
8002af2: 78fa ldrb r2, [r7, #3]
|
|
8002af4: 4611 mov r1, r2
|
|
8002af6: 4618 mov r0, r3
|
|
8002af8: f004 ff8f bl 8007a1a <USB_HC_Halt>
|
|
8002afc: e04e b.n 8002b9c <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
|
|
8002afe: 687b ldr r3, [r7, #4]
|
|
8002b00: 681b ldr r3, [r3, #0]
|
|
8002b02: 78fa ldrb r2, [r7, #3]
|
|
8002b04: 4611 mov r1, r2
|
|
8002b06: 4618 mov r0, r3
|
|
8002b08: f004 f9dd bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002b0c: 4603 mov r3, r0
|
|
8002b0e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002b12: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002b16: d11b bne.n 8002b50 <HCD_HC_IN_IRQHandler+0x156>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
|
|
8002b18: 78fb ldrb r3, [r7, #3]
|
|
8002b1a: 015a lsls r2, r3, #5
|
|
8002b1c: 693b ldr r3, [r7, #16]
|
|
8002b1e: 4413 add r3, r2
|
|
8002b20: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002b24: 461a mov r2, r3
|
|
8002b26: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8002b2a: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_DATATGLERR;
|
|
8002b2c: 78fa ldrb r2, [r7, #3]
|
|
8002b2e: 6879 ldr r1, [r7, #4]
|
|
8002b30: 4613 mov r3, r2
|
|
8002b32: 011b lsls r3, r3, #4
|
|
8002b34: 1a9b subs r3, r3, r2
|
|
8002b36: 009b lsls r3, r3, #2
|
|
8002b38: 440b add r3, r1
|
|
8002b3a: 334d adds r3, #77 @ 0x4d
|
|
8002b3c: 2209 movs r2, #9
|
|
8002b3e: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002b40: 687b ldr r3, [r7, #4]
|
|
8002b42: 681b ldr r3, [r3, #0]
|
|
8002b44: 78fa ldrb r2, [r7, #3]
|
|
8002b46: 4611 mov r1, r2
|
|
8002b48: 4618 mov r0, r3
|
|
8002b4a: f004 ff66 bl 8007a1a <USB_HC_Halt>
|
|
8002b4e: e025 b.n 8002b9c <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
|
|
8002b50: 687b ldr r3, [r7, #4]
|
|
8002b52: 681b ldr r3, [r3, #0]
|
|
8002b54: 78fa ldrb r2, [r7, #3]
|
|
8002b56: 4611 mov r1, r2
|
|
8002b58: 4618 mov r0, r3
|
|
8002b5a: f004 f9b4 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002b5e: 4603 mov r3, r0
|
|
8002b60: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002b64: 2b80 cmp r3, #128 @ 0x80
|
|
8002b66: d119 bne.n 8002b9c <HCD_HC_IN_IRQHandler+0x1a2>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
|
|
8002b68: 78fb ldrb r3, [r7, #3]
|
|
8002b6a: 015a lsls r2, r3, #5
|
|
8002b6c: 693b ldr r3, [r7, #16]
|
|
8002b6e: 4413 add r3, r2
|
|
8002b70: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002b74: 461a mov r2, r3
|
|
8002b76: 2380 movs r3, #128 @ 0x80
|
|
8002b78: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8002b7a: 78fa ldrb r2, [r7, #3]
|
|
8002b7c: 6879 ldr r1, [r7, #4]
|
|
8002b7e: 4613 mov r3, r2
|
|
8002b80: 011b lsls r3, r3, #4
|
|
8002b82: 1a9b subs r3, r3, r2
|
|
8002b84: 009b lsls r3, r3, #2
|
|
8002b86: 440b add r3, r1
|
|
8002b88: 334d adds r3, #77 @ 0x4d
|
|
8002b8a: 2207 movs r2, #7
|
|
8002b8c: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002b8e: 687b ldr r3, [r7, #4]
|
|
8002b90: 681b ldr r3, [r3, #0]
|
|
8002b92: 78fa ldrb r2, [r7, #3]
|
|
8002b94: 4611 mov r1, r2
|
|
8002b96: 4618 mov r0, r3
|
|
8002b98: f004 ff3f bl 8007a1a <USB_HC_Halt>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
|
|
8002b9c: 687b ldr r3, [r7, #4]
|
|
8002b9e: 681b ldr r3, [r3, #0]
|
|
8002ba0: 78fa ldrb r2, [r7, #3]
|
|
8002ba2: 4611 mov r1, r2
|
|
8002ba4: 4618 mov r0, r3
|
|
8002ba6: f004 f98e bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002baa: 4603 mov r3, r0
|
|
8002bac: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8002bb0: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8002bb4: d112 bne.n 8002bdc <HCD_HC_IN_IRQHandler+0x1e2>
|
|
{
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002bb6: 687b ldr r3, [r7, #4]
|
|
8002bb8: 681b ldr r3, [r3, #0]
|
|
8002bba: 78fa ldrb r2, [r7, #3]
|
|
8002bbc: 4611 mov r1, r2
|
|
8002bbe: 4618 mov r0, r3
|
|
8002bc0: f004 ff2b bl 8007a1a <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
|
|
8002bc4: 78fb ldrb r3, [r7, #3]
|
|
8002bc6: 015a lsls r2, r3, #5
|
|
8002bc8: 693b ldr r3, [r7, #16]
|
|
8002bca: 4413 add r3, r2
|
|
8002bcc: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002bd0: 461a mov r2, r3
|
|
8002bd2: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8002bd6: 6093 str r3, [r2, #8]
|
|
8002bd8: f000 bd75 b.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
|
|
8002bdc: 687b ldr r3, [r7, #4]
|
|
8002bde: 681b ldr r3, [r3, #0]
|
|
8002be0: 78fa ldrb r2, [r7, #3]
|
|
8002be2: 4611 mov r1, r2
|
|
8002be4: 4618 mov r0, r3
|
|
8002be6: f004 f96e bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002bea: 4603 mov r3, r0
|
|
8002bec: f003 0301 and.w r3, r3, #1
|
|
8002bf0: 2b01 cmp r3, #1
|
|
8002bf2: f040 8128 bne.w 8002e46 <HCD_HC_IN_IRQHandler+0x44c>
|
|
{
|
|
/* Clear any pending ACK IT */
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
8002bf6: 78fb ldrb r3, [r7, #3]
|
|
8002bf8: 015a lsls r2, r3, #5
|
|
8002bfa: 693b ldr r3, [r7, #16]
|
|
8002bfc: 4413 add r3, r2
|
|
8002bfe: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002c02: 461a mov r2, r3
|
|
8002c04: 2320 movs r3, #32
|
|
8002c06: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8002c08: 78fa ldrb r2, [r7, #3]
|
|
8002c0a: 6879 ldr r1, [r7, #4]
|
|
8002c0c: 4613 mov r3, r2
|
|
8002c0e: 011b lsls r3, r3, #4
|
|
8002c10: 1a9b subs r3, r3, r2
|
|
8002c12: 009b lsls r3, r3, #2
|
|
8002c14: 440b add r3, r1
|
|
8002c16: 331b adds r3, #27
|
|
8002c18: 781b ldrb r3, [r3, #0]
|
|
8002c1a: 2b01 cmp r3, #1
|
|
8002c1c: d119 bne.n 8002c52 <HCD_HC_IN_IRQHandler+0x258>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8002c1e: 78fa ldrb r2, [r7, #3]
|
|
8002c20: 6879 ldr r1, [r7, #4]
|
|
8002c22: 4613 mov r3, r2
|
|
8002c24: 011b lsls r3, r3, #4
|
|
8002c26: 1a9b subs r3, r3, r2
|
|
8002c28: 009b lsls r3, r3, #2
|
|
8002c2a: 440b add r3, r1
|
|
8002c2c: 331b adds r3, #27
|
|
8002c2e: 2200 movs r2, #0
|
|
8002c30: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8002c32: 78fb ldrb r3, [r7, #3]
|
|
8002c34: 015a lsls r2, r3, #5
|
|
8002c36: 693b ldr r3, [r7, #16]
|
|
8002c38: 4413 add r3, r2
|
|
8002c3a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002c3e: 685b ldr r3, [r3, #4]
|
|
8002c40: 78fa ldrb r2, [r7, #3]
|
|
8002c42: 0151 lsls r1, r2, #5
|
|
8002c44: 693a ldr r2, [r7, #16]
|
|
8002c46: 440a add r2, r1
|
|
8002c48: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002c4c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002c50: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (hhcd->Init.dma_enable != 0U)
|
|
8002c52: 687b ldr r3, [r7, #4]
|
|
8002c54: 799b ldrb r3, [r3, #6]
|
|
8002c56: 2b00 cmp r3, #0
|
|
8002c58: d01b beq.n 8002c92 <HCD_HC_IN_IRQHandler+0x298>
|
|
{
|
|
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
|
|
8002c5a: 78fa ldrb r2, [r7, #3]
|
|
8002c5c: 6879 ldr r1, [r7, #4]
|
|
8002c5e: 4613 mov r3, r2
|
|
8002c60: 011b lsls r3, r3, #4
|
|
8002c62: 1a9b subs r3, r3, r2
|
|
8002c64: 009b lsls r3, r3, #2
|
|
8002c66: 440b add r3, r1
|
|
8002c68: 3330 adds r3, #48 @ 0x30
|
|
8002c6a: 6819 ldr r1, [r3, #0]
|
|
8002c6c: 78fb ldrb r3, [r7, #3]
|
|
8002c6e: 015a lsls r2, r3, #5
|
|
8002c70: 693b ldr r3, [r7, #16]
|
|
8002c72: 4413 add r3, r2
|
|
8002c74: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002c78: 691b ldr r3, [r3, #16]
|
|
8002c7a: f3c3 0312 ubfx r3, r3, #0, #19
|
|
8002c7e: 78fa ldrb r2, [r7, #3]
|
|
8002c80: 1ac9 subs r1, r1, r3
|
|
8002c82: 6878 ldr r0, [r7, #4]
|
|
8002c84: 4613 mov r3, r2
|
|
8002c86: 011b lsls r3, r3, #4
|
|
8002c88: 1a9b subs r3, r3, r2
|
|
8002c8a: 009b lsls r3, r3, #2
|
|
8002c8c: 4403 add r3, r0
|
|
8002c8e: 3338 adds r3, #56 @ 0x38
|
|
8002c90: 6019 str r1, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].state = HC_XFRC;
|
|
8002c92: 78fa ldrb r2, [r7, #3]
|
|
8002c94: 6879 ldr r1, [r7, #4]
|
|
8002c96: 4613 mov r3, r2
|
|
8002c98: 011b lsls r3, r3, #4
|
|
8002c9a: 1a9b subs r3, r3, r2
|
|
8002c9c: 009b lsls r3, r3, #2
|
|
8002c9e: 440b add r3, r1
|
|
8002ca0: 334d adds r3, #77 @ 0x4d
|
|
8002ca2: 2201 movs r2, #1
|
|
8002ca4: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002ca6: 78fa ldrb r2, [r7, #3]
|
|
8002ca8: 6879 ldr r1, [r7, #4]
|
|
8002caa: 4613 mov r3, r2
|
|
8002cac: 011b lsls r3, r3, #4
|
|
8002cae: 1a9b subs r3, r3, r2
|
|
8002cb0: 009b lsls r3, r3, #2
|
|
8002cb2: 440b add r3, r1
|
|
8002cb4: 3344 adds r3, #68 @ 0x44
|
|
8002cb6: 2200 movs r2, #0
|
|
8002cb8: 601a str r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
|
|
8002cba: 78fb ldrb r3, [r7, #3]
|
|
8002cbc: 015a lsls r2, r3, #5
|
|
8002cbe: 693b ldr r3, [r7, #16]
|
|
8002cc0: 4413 add r3, r2
|
|
8002cc2: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002cc6: 461a mov r2, r3
|
|
8002cc8: 2301 movs r3, #1
|
|
8002cca: 6093 str r3, [r2, #8]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002ccc: 78fa ldrb r2, [r7, #3]
|
|
8002cce: 6879 ldr r1, [r7, #4]
|
|
8002cd0: 4613 mov r3, r2
|
|
8002cd2: 011b lsls r3, r3, #4
|
|
8002cd4: 1a9b subs r3, r3, r2
|
|
8002cd6: 009b lsls r3, r3, #2
|
|
8002cd8: 440b add r3, r1
|
|
8002cda: 3326 adds r3, #38 @ 0x26
|
|
8002cdc: 781b ldrb r3, [r3, #0]
|
|
8002cde: 2b00 cmp r3, #0
|
|
8002ce0: d00a beq.n 8002cf8 <HCD_HC_IN_IRQHandler+0x2fe>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002ce2: 78fa ldrb r2, [r7, #3]
|
|
8002ce4: 6879 ldr r1, [r7, #4]
|
|
8002ce6: 4613 mov r3, r2
|
|
8002ce8: 011b lsls r3, r3, #4
|
|
8002cea: 1a9b subs r3, r3, r2
|
|
8002cec: 009b lsls r3, r3, #2
|
|
8002cee: 440b add r3, r1
|
|
8002cf0: 3326 adds r3, #38 @ 0x26
|
|
8002cf2: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002cf4: 2b02 cmp r3, #2
|
|
8002cf6: d110 bne.n 8002d1a <HCD_HC_IN_IRQHandler+0x320>
|
|
{
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002cf8: 687b ldr r3, [r7, #4]
|
|
8002cfa: 681b ldr r3, [r3, #0]
|
|
8002cfc: 78fa ldrb r2, [r7, #3]
|
|
8002cfe: 4611 mov r1, r2
|
|
8002d00: 4618 mov r0, r3
|
|
8002d02: f004 fe8a bl 8007a1a <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
8002d06: 78fb ldrb r3, [r7, #3]
|
|
8002d08: 015a lsls r2, r3, #5
|
|
8002d0a: 693b ldr r3, [r7, #16]
|
|
8002d0c: 4413 add r3, r2
|
|
8002d0e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002d12: 461a mov r2, r3
|
|
8002d14: 2310 movs r3, #16
|
|
8002d16: 6093 str r3, [r2, #8]
|
|
8002d18: e03d b.n 8002d96 <HCD_HC_IN_IRQHandler+0x39c>
|
|
}
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
|
|
8002d1a: 78fa ldrb r2, [r7, #3]
|
|
8002d1c: 6879 ldr r1, [r7, #4]
|
|
8002d1e: 4613 mov r3, r2
|
|
8002d20: 011b lsls r3, r3, #4
|
|
8002d22: 1a9b subs r3, r3, r2
|
|
8002d24: 009b lsls r3, r3, #2
|
|
8002d26: 440b add r3, r1
|
|
8002d28: 3326 adds r3, #38 @ 0x26
|
|
8002d2a: 781b ldrb r3, [r3, #0]
|
|
8002d2c: 2b03 cmp r3, #3
|
|
8002d2e: d00a beq.n 8002d46 <HCD_HC_IN_IRQHandler+0x34c>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
|
|
8002d30: 78fa ldrb r2, [r7, #3]
|
|
8002d32: 6879 ldr r1, [r7, #4]
|
|
8002d34: 4613 mov r3, r2
|
|
8002d36: 011b lsls r3, r3, #4
|
|
8002d38: 1a9b subs r3, r3, r2
|
|
8002d3a: 009b lsls r3, r3, #2
|
|
8002d3c: 440b add r3, r1
|
|
8002d3e: 3326 adds r3, #38 @ 0x26
|
|
8002d40: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
|
|
8002d42: 2b01 cmp r3, #1
|
|
8002d44: d127 bne.n 8002d96 <HCD_HC_IN_IRQHandler+0x39c>
|
|
{
|
|
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
|
|
8002d46: 78fb ldrb r3, [r7, #3]
|
|
8002d48: 015a lsls r2, r3, #5
|
|
8002d4a: 693b ldr r3, [r7, #16]
|
|
8002d4c: 4413 add r3, r2
|
|
8002d4e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002d52: 681b ldr r3, [r3, #0]
|
|
8002d54: 78fa ldrb r2, [r7, #3]
|
|
8002d56: 0151 lsls r1, r2, #5
|
|
8002d58: 693a ldr r2, [r7, #16]
|
|
8002d5a: 440a add r2, r1
|
|
8002d5c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002d60: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8002d64: 6013 str r3, [r2, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
8002d66: 78fa ldrb r2, [r7, #3]
|
|
8002d68: 6879 ldr r1, [r7, #4]
|
|
8002d6a: 4613 mov r3, r2
|
|
8002d6c: 011b lsls r3, r3, #4
|
|
8002d6e: 1a9b subs r3, r3, r2
|
|
8002d70: 009b lsls r3, r3, #2
|
|
8002d72: 440b add r3, r1
|
|
8002d74: 334c adds r3, #76 @ 0x4c
|
|
8002d76: 2201 movs r2, #1
|
|
8002d78: 701a strb r2, [r3, #0]
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
8002d7a: 78fa ldrb r2, [r7, #3]
|
|
8002d7c: 6879 ldr r1, [r7, #4]
|
|
8002d7e: 4613 mov r3, r2
|
|
8002d80: 011b lsls r3, r3, #4
|
|
8002d82: 1a9b subs r3, r3, r2
|
|
8002d84: 009b lsls r3, r3, #2
|
|
8002d86: 440b add r3, r1
|
|
8002d88: 334c adds r3, #76 @ 0x4c
|
|
8002d8a: 781a ldrb r2, [r3, #0]
|
|
8002d8c: 78fb ldrb r3, [r7, #3]
|
|
8002d8e: 4619 mov r1, r3
|
|
8002d90: 6878 ldr r0, [r7, #4]
|
|
8002d92: f009 fe03 bl 800c99c <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (hhcd->Init.dma_enable == 1U)
|
|
8002d96: 687b ldr r3, [r7, #4]
|
|
8002d98: 799b ldrb r3, [r3, #6]
|
|
8002d9a: 2b01 cmp r3, #1
|
|
8002d9c: d13b bne.n 8002e16 <HCD_HC_IN_IRQHandler+0x41c>
|
|
{
|
|
if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
|
|
8002d9e: 78fa ldrb r2, [r7, #3]
|
|
8002da0: 6879 ldr r1, [r7, #4]
|
|
8002da2: 4613 mov r3, r2
|
|
8002da4: 011b lsls r3, r3, #4
|
|
8002da6: 1a9b subs r3, r3, r2
|
|
8002da8: 009b lsls r3, r3, #2
|
|
8002daa: 440b add r3, r1
|
|
8002dac: 3338 adds r3, #56 @ 0x38
|
|
8002dae: 6819 ldr r1, [r3, #0]
|
|
8002db0: 78fa ldrb r2, [r7, #3]
|
|
8002db2: 6878 ldr r0, [r7, #4]
|
|
8002db4: 4613 mov r3, r2
|
|
8002db6: 011b lsls r3, r3, #4
|
|
8002db8: 1a9b subs r3, r3, r2
|
|
8002dba: 009b lsls r3, r3, #2
|
|
8002dbc: 4403 add r3, r0
|
|
8002dbe: 3328 adds r3, #40 @ 0x28
|
|
8002dc0: 881b ldrh r3, [r3, #0]
|
|
8002dc2: 440b add r3, r1
|
|
8002dc4: 1e59 subs r1, r3, #1
|
|
8002dc6: 78fa ldrb r2, [r7, #3]
|
|
8002dc8: 6878 ldr r0, [r7, #4]
|
|
8002dca: 4613 mov r3, r2
|
|
8002dcc: 011b lsls r3, r3, #4
|
|
8002dce: 1a9b subs r3, r3, r2
|
|
8002dd0: 009b lsls r3, r3, #2
|
|
8002dd2: 4403 add r3, r0
|
|
8002dd4: 3328 adds r3, #40 @ 0x28
|
|
8002dd6: 881b ldrh r3, [r3, #0]
|
|
8002dd8: fbb1 f3f3 udiv r3, r1, r3
|
|
8002ddc: f003 0301 and.w r3, r3, #1
|
|
8002de0: 2b00 cmp r3, #0
|
|
8002de2: f000 8470 beq.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
8002de6: 78fa ldrb r2, [r7, #3]
|
|
8002de8: 6879 ldr r1, [r7, #4]
|
|
8002dea: 4613 mov r3, r2
|
|
8002dec: 011b lsls r3, r3, #4
|
|
8002dee: 1a9b subs r3, r3, r2
|
|
8002df0: 009b lsls r3, r3, #2
|
|
8002df2: 440b add r3, r1
|
|
8002df4: 333c adds r3, #60 @ 0x3c
|
|
8002df6: 781b ldrb r3, [r3, #0]
|
|
8002df8: 78fa ldrb r2, [r7, #3]
|
|
8002dfa: f083 0301 eor.w r3, r3, #1
|
|
8002dfe: b2d8 uxtb r0, r3
|
|
8002e00: 6879 ldr r1, [r7, #4]
|
|
8002e02: 4613 mov r3, r2
|
|
8002e04: 011b lsls r3, r3, #4
|
|
8002e06: 1a9b subs r3, r3, r2
|
|
8002e08: 009b lsls r3, r3, #2
|
|
8002e0a: 440b add r3, r1
|
|
8002e0c: 333c adds r3, #60 @ 0x3c
|
|
8002e0e: 4602 mov r2, r0
|
|
8002e10: 701a strb r2, [r3, #0]
|
|
8002e12: f000 bc58 b.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
8002e16: 78fa ldrb r2, [r7, #3]
|
|
8002e18: 6879 ldr r1, [r7, #4]
|
|
8002e1a: 4613 mov r3, r2
|
|
8002e1c: 011b lsls r3, r3, #4
|
|
8002e1e: 1a9b subs r3, r3, r2
|
|
8002e20: 009b lsls r3, r3, #2
|
|
8002e22: 440b add r3, r1
|
|
8002e24: 333c adds r3, #60 @ 0x3c
|
|
8002e26: 781b ldrb r3, [r3, #0]
|
|
8002e28: 78fa ldrb r2, [r7, #3]
|
|
8002e2a: f083 0301 eor.w r3, r3, #1
|
|
8002e2e: b2d8 uxtb r0, r3
|
|
8002e30: 6879 ldr r1, [r7, #4]
|
|
8002e32: 4613 mov r3, r2
|
|
8002e34: 011b lsls r3, r3, #4
|
|
8002e36: 1a9b subs r3, r3, r2
|
|
8002e38: 009b lsls r3, r3, #2
|
|
8002e3a: 440b add r3, r1
|
|
8002e3c: 333c adds r3, #60 @ 0x3c
|
|
8002e3e: 4602 mov r2, r0
|
|
8002e40: 701a strb r2, [r3, #0]
|
|
8002e42: f000 bc40 b.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
|
|
8002e46: 687b ldr r3, [r7, #4]
|
|
8002e48: 681b ldr r3, [r3, #0]
|
|
8002e4a: 78fa ldrb r2, [r7, #3]
|
|
8002e4c: 4611 mov r1, r2
|
|
8002e4e: 4618 mov r0, r3
|
|
8002e50: f004 f839 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002e54: 4603 mov r3, r0
|
|
8002e56: f003 0320 and.w r3, r3, #32
|
|
8002e5a: 2b20 cmp r3, #32
|
|
8002e5c: d131 bne.n 8002ec2 <HCD_HC_IN_IRQHandler+0x4c8>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
8002e5e: 78fb ldrb r3, [r7, #3]
|
|
8002e60: 015a lsls r2, r3, #5
|
|
8002e62: 693b ldr r3, [r7, #16]
|
|
8002e64: 4413 add r3, r2
|
|
8002e66: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002e6a: 461a mov r2, r3
|
|
8002e6c: 2320 movs r3, #32
|
|
8002e6e: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 1U)
|
|
8002e70: 78fa ldrb r2, [r7, #3]
|
|
8002e72: 6879 ldr r1, [r7, #4]
|
|
8002e74: 4613 mov r3, r2
|
|
8002e76: 011b lsls r3, r3, #4
|
|
8002e78: 1a9b subs r3, r3, r2
|
|
8002e7a: 009b lsls r3, r3, #2
|
|
8002e7c: 440b add r3, r1
|
|
8002e7e: 331a adds r3, #26
|
|
8002e80: 781b ldrb r3, [r3, #0]
|
|
8002e82: 2b01 cmp r3, #1
|
|
8002e84: f040 841f bne.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 1U;
|
|
8002e88: 78fa ldrb r2, [r7, #3]
|
|
8002e8a: 6879 ldr r1, [r7, #4]
|
|
8002e8c: 4613 mov r3, r2
|
|
8002e8e: 011b lsls r3, r3, #4
|
|
8002e90: 1a9b subs r3, r3, r2
|
|
8002e92: 009b lsls r3, r3, #2
|
|
8002e94: 440b add r3, r1
|
|
8002e96: 331b adds r3, #27
|
|
8002e98: 2201 movs r2, #1
|
|
8002e9a: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
8002e9c: 78fa ldrb r2, [r7, #3]
|
|
8002e9e: 6879 ldr r1, [r7, #4]
|
|
8002ea0: 4613 mov r3, r2
|
|
8002ea2: 011b lsls r3, r3, #4
|
|
8002ea4: 1a9b subs r3, r3, r2
|
|
8002ea6: 009b lsls r3, r3, #2
|
|
8002ea8: 440b add r3, r1
|
|
8002eaa: 334d adds r3, #77 @ 0x4d
|
|
8002eac: 2203 movs r2, #3
|
|
8002eae: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002eb0: 687b ldr r3, [r7, #4]
|
|
8002eb2: 681b ldr r3, [r3, #0]
|
|
8002eb4: 78fa ldrb r2, [r7, #3]
|
|
8002eb6: 4611 mov r1, r2
|
|
8002eb8: 4618 mov r0, r3
|
|
8002eba: f004 fdae bl 8007a1a <USB_HC_Halt>
|
|
8002ebe: f000 bc02 b.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
|
|
8002ec2: 687b ldr r3, [r7, #4]
|
|
8002ec4: 681b ldr r3, [r3, #0]
|
|
8002ec6: 78fa ldrb r2, [r7, #3]
|
|
8002ec8: 4611 mov r1, r2
|
|
8002eca: 4618 mov r0, r3
|
|
8002ecc: f003 fffb bl 8006ec6 <USB_ReadChInterrupts>
|
|
8002ed0: 4603 mov r3, r0
|
|
8002ed2: f003 0302 and.w r3, r3, #2
|
|
8002ed6: 2b02 cmp r3, #2
|
|
8002ed8: f040 8305 bne.w 80034e6 <HCD_HC_IN_IRQHandler+0xaec>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
|
|
8002edc: 78fb ldrb r3, [r7, #3]
|
|
8002ede: 015a lsls r2, r3, #5
|
|
8002ee0: 693b ldr r3, [r7, #16]
|
|
8002ee2: 4413 add r3, r2
|
|
8002ee4: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002ee8: 461a mov r2, r3
|
|
8002eea: 2302 movs r3, #2
|
|
8002eec: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].state == HC_XFRC)
|
|
8002eee: 78fa ldrb r2, [r7, #3]
|
|
8002ef0: 6879 ldr r1, [r7, #4]
|
|
8002ef2: 4613 mov r3, r2
|
|
8002ef4: 011b lsls r3, r3, #4
|
|
8002ef6: 1a9b subs r3, r3, r2
|
|
8002ef8: 009b lsls r3, r3, #2
|
|
8002efa: 440b add r3, r1
|
|
8002efc: 334d adds r3, #77 @ 0x4d
|
|
8002efe: 781b ldrb r3, [r3, #0]
|
|
8002f00: 2b01 cmp r3, #1
|
|
8002f02: d114 bne.n 8002f2e <HCD_HC_IN_IRQHandler+0x534>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002f04: 78fa ldrb r2, [r7, #3]
|
|
8002f06: 6879 ldr r1, [r7, #4]
|
|
8002f08: 4613 mov r3, r2
|
|
8002f0a: 011b lsls r3, r3, #4
|
|
8002f0c: 1a9b subs r3, r3, r2
|
|
8002f0e: 009b lsls r3, r3, #2
|
|
8002f10: 440b add r3, r1
|
|
8002f12: 334d adds r3, #77 @ 0x4d
|
|
8002f14: 2202 movs r2, #2
|
|
8002f16: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
8002f18: 78fa ldrb r2, [r7, #3]
|
|
8002f1a: 6879 ldr r1, [r7, #4]
|
|
8002f1c: 4613 mov r3, r2
|
|
8002f1e: 011b lsls r3, r3, #4
|
|
8002f20: 1a9b subs r3, r3, r2
|
|
8002f22: 009b lsls r3, r3, #2
|
|
8002f24: 440b add r3, r1
|
|
8002f26: 334c adds r3, #76 @ 0x4c
|
|
8002f28: 2201 movs r2, #1
|
|
8002f2a: 701a strb r2, [r3, #0]
|
|
8002f2c: e2cc b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_STALL)
|
|
8002f2e: 78fa ldrb r2, [r7, #3]
|
|
8002f30: 6879 ldr r1, [r7, #4]
|
|
8002f32: 4613 mov r3, r2
|
|
8002f34: 011b lsls r3, r3, #4
|
|
8002f36: 1a9b subs r3, r3, r2
|
|
8002f38: 009b lsls r3, r3, #2
|
|
8002f3a: 440b add r3, r1
|
|
8002f3c: 334d adds r3, #77 @ 0x4d
|
|
8002f3e: 781b ldrb r3, [r3, #0]
|
|
8002f40: 2b06 cmp r3, #6
|
|
8002f42: d114 bne.n 8002f6e <HCD_HC_IN_IRQHandler+0x574>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002f44: 78fa ldrb r2, [r7, #3]
|
|
8002f46: 6879 ldr r1, [r7, #4]
|
|
8002f48: 4613 mov r3, r2
|
|
8002f4a: 011b lsls r3, r3, #4
|
|
8002f4c: 1a9b subs r3, r3, r2
|
|
8002f4e: 009b lsls r3, r3, #2
|
|
8002f50: 440b add r3, r1
|
|
8002f52: 334d adds r3, #77 @ 0x4d
|
|
8002f54: 2202 movs r2, #2
|
|
8002f56: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_STALL;
|
|
8002f58: 78fa ldrb r2, [r7, #3]
|
|
8002f5a: 6879 ldr r1, [r7, #4]
|
|
8002f5c: 4613 mov r3, r2
|
|
8002f5e: 011b lsls r3, r3, #4
|
|
8002f60: 1a9b subs r3, r3, r2
|
|
8002f62: 009b lsls r3, r3, #2
|
|
8002f64: 440b add r3, r1
|
|
8002f66: 334c adds r3, #76 @ 0x4c
|
|
8002f68: 2205 movs r2, #5
|
|
8002f6a: 701a strb r2, [r3, #0]
|
|
8002f6c: e2ac b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
8002f6e: 78fa ldrb r2, [r7, #3]
|
|
8002f70: 6879 ldr r1, [r7, #4]
|
|
8002f72: 4613 mov r3, r2
|
|
8002f74: 011b lsls r3, r3, #4
|
|
8002f76: 1a9b subs r3, r3, r2
|
|
8002f78: 009b lsls r3, r3, #2
|
|
8002f7a: 440b add r3, r1
|
|
8002f7c: 334d adds r3, #77 @ 0x4d
|
|
8002f7e: 781b ldrb r3, [r3, #0]
|
|
8002f80: 2b07 cmp r3, #7
|
|
8002f82: d00b beq.n 8002f9c <HCD_HC_IN_IRQHandler+0x5a2>
|
|
(hhcd->hc[chnum].state == HC_DATATGLERR))
|
|
8002f84: 78fa ldrb r2, [r7, #3]
|
|
8002f86: 6879 ldr r1, [r7, #4]
|
|
8002f88: 4613 mov r3, r2
|
|
8002f8a: 011b lsls r3, r3, #4
|
|
8002f8c: 1a9b subs r3, r3, r2
|
|
8002f8e: 009b lsls r3, r3, #2
|
|
8002f90: 440b add r3, r1
|
|
8002f92: 334d adds r3, #77 @ 0x4d
|
|
8002f94: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
8002f96: 2b09 cmp r3, #9
|
|
8002f98: f040 80a6 bne.w 80030e8 <HCD_HC_IN_IRQHandler+0x6ee>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002f9c: 78fa ldrb r2, [r7, #3]
|
|
8002f9e: 6879 ldr r1, [r7, #4]
|
|
8002fa0: 4613 mov r3, r2
|
|
8002fa2: 011b lsls r3, r3, #4
|
|
8002fa4: 1a9b subs r3, r3, r2
|
|
8002fa6: 009b lsls r3, r3, #2
|
|
8002fa8: 440b add r3, r1
|
|
8002faa: 334d adds r3, #77 @ 0x4d
|
|
8002fac: 2202 movs r2, #2
|
|
8002fae: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8002fb0: 78fa ldrb r2, [r7, #3]
|
|
8002fb2: 6879 ldr r1, [r7, #4]
|
|
8002fb4: 4613 mov r3, r2
|
|
8002fb6: 011b lsls r3, r3, #4
|
|
8002fb8: 1a9b subs r3, r3, r2
|
|
8002fba: 009b lsls r3, r3, #2
|
|
8002fbc: 440b add r3, r1
|
|
8002fbe: 3344 adds r3, #68 @ 0x44
|
|
8002fc0: 681b ldr r3, [r3, #0]
|
|
8002fc2: 1c59 adds r1, r3, #1
|
|
8002fc4: 6878 ldr r0, [r7, #4]
|
|
8002fc6: 4613 mov r3, r2
|
|
8002fc8: 011b lsls r3, r3, #4
|
|
8002fca: 1a9b subs r3, r3, r2
|
|
8002fcc: 009b lsls r3, r3, #2
|
|
8002fce: 4403 add r3, r0
|
|
8002fd0: 3344 adds r3, #68 @ 0x44
|
|
8002fd2: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8002fd4: 78fa ldrb r2, [r7, #3]
|
|
8002fd6: 6879 ldr r1, [r7, #4]
|
|
8002fd8: 4613 mov r3, r2
|
|
8002fda: 011b lsls r3, r3, #4
|
|
8002fdc: 1a9b subs r3, r3, r2
|
|
8002fde: 009b lsls r3, r3, #2
|
|
8002fe0: 440b add r3, r1
|
|
8002fe2: 3344 adds r3, #68 @ 0x44
|
|
8002fe4: 681b ldr r3, [r3, #0]
|
|
8002fe6: 2b02 cmp r3, #2
|
|
8002fe8: d943 bls.n 8003072 <HCD_HC_IN_IRQHandler+0x678>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002fea: 78fa ldrb r2, [r7, #3]
|
|
8002fec: 6879 ldr r1, [r7, #4]
|
|
8002fee: 4613 mov r3, r2
|
|
8002ff0: 011b lsls r3, r3, #4
|
|
8002ff2: 1a9b subs r3, r3, r2
|
|
8002ff4: 009b lsls r3, r3, #2
|
|
8002ff6: 440b add r3, r1
|
|
8002ff8: 3344 adds r3, #68 @ 0x44
|
|
8002ffa: 2200 movs r2, #0
|
|
8002ffc: 601a str r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 1U)
|
|
8002ffe: 78fa ldrb r2, [r7, #3]
|
|
8003000: 6879 ldr r1, [r7, #4]
|
|
8003002: 4613 mov r3, r2
|
|
8003004: 011b lsls r3, r3, #4
|
|
8003006: 1a9b subs r3, r3, r2
|
|
8003008: 009b lsls r3, r3, #2
|
|
800300a: 440b add r3, r1
|
|
800300c: 331a adds r3, #26
|
|
800300e: 781b ldrb r3, [r3, #0]
|
|
8003010: 2b01 cmp r3, #1
|
|
8003012: d123 bne.n 800305c <HCD_HC_IN_IRQHandler+0x662>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8003014: 78fa ldrb r2, [r7, #3]
|
|
8003016: 6879 ldr r1, [r7, #4]
|
|
8003018: 4613 mov r3, r2
|
|
800301a: 011b lsls r3, r3, #4
|
|
800301c: 1a9b subs r3, r3, r2
|
|
800301e: 009b lsls r3, r3, #2
|
|
8003020: 440b add r3, r1
|
|
8003022: 331b adds r3, #27
|
|
8003024: 2200 movs r2, #0
|
|
8003026: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ep_ss_schedule = 0U;
|
|
8003028: 78fa ldrb r2, [r7, #3]
|
|
800302a: 6879 ldr r1, [r7, #4]
|
|
800302c: 4613 mov r3, r2
|
|
800302e: 011b lsls r3, r3, #4
|
|
8003030: 1a9b subs r3, r3, r2
|
|
8003032: 009b lsls r3, r3, #2
|
|
8003034: 440b add r3, r1
|
|
8003036: 331c adds r3, #28
|
|
8003038: 2200 movs r2, #0
|
|
800303a: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
800303c: 78fb ldrb r3, [r7, #3]
|
|
800303e: 015a lsls r2, r3, #5
|
|
8003040: 693b ldr r3, [r7, #16]
|
|
8003042: 4413 add r3, r2
|
|
8003044: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003048: 685b ldr r3, [r3, #4]
|
|
800304a: 78fa ldrb r2, [r7, #3]
|
|
800304c: 0151 lsls r1, r2, #5
|
|
800304e: 693a ldr r2, [r7, #16]
|
|
8003050: 440a add r2, r1
|
|
8003052: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8003056: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800305a: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
800305c: 78fa ldrb r2, [r7, #3]
|
|
800305e: 6879 ldr r1, [r7, #4]
|
|
8003060: 4613 mov r3, r2
|
|
8003062: 011b lsls r3, r3, #4
|
|
8003064: 1a9b subs r3, r3, r2
|
|
8003066: 009b lsls r3, r3, #2
|
|
8003068: 440b add r3, r1
|
|
800306a: 334c adds r3, #76 @ 0x4c
|
|
800306c: 2204 movs r2, #4
|
|
800306e: 701a strb r2, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8003070: e229 b.n 80034c6 <HCD_HC_IN_IRQHandler+0xacc>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003072: 78fa ldrb r2, [r7, #3]
|
|
8003074: 6879 ldr r1, [r7, #4]
|
|
8003076: 4613 mov r3, r2
|
|
8003078: 011b lsls r3, r3, #4
|
|
800307a: 1a9b subs r3, r3, r2
|
|
800307c: 009b lsls r3, r3, #2
|
|
800307e: 440b add r3, r1
|
|
8003080: 334c adds r3, #76 @ 0x4c
|
|
8003082: 2202 movs r2, #2
|
|
8003084: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8003086: 78fa ldrb r2, [r7, #3]
|
|
8003088: 6879 ldr r1, [r7, #4]
|
|
800308a: 4613 mov r3, r2
|
|
800308c: 011b lsls r3, r3, #4
|
|
800308e: 1a9b subs r3, r3, r2
|
|
8003090: 009b lsls r3, r3, #2
|
|
8003092: 440b add r3, r1
|
|
8003094: 3326 adds r3, #38 @ 0x26
|
|
8003096: 781b ldrb r3, [r3, #0]
|
|
8003098: 2b00 cmp r3, #0
|
|
800309a: d00b beq.n 80030b4 <HCD_HC_IN_IRQHandler+0x6ba>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
800309c: 78fa ldrb r2, [r7, #3]
|
|
800309e: 6879 ldr r1, [r7, #4]
|
|
80030a0: 4613 mov r3, r2
|
|
80030a2: 011b lsls r3, r3, #4
|
|
80030a4: 1a9b subs r3, r3, r2
|
|
80030a6: 009b lsls r3, r3, #2
|
|
80030a8: 440b add r3, r1
|
|
80030aa: 3326 adds r3, #38 @ 0x26
|
|
80030ac: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80030ae: 2b02 cmp r3, #2
|
|
80030b0: f040 8209 bne.w 80034c6 <HCD_HC_IN_IRQHandler+0xacc>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
80030b4: 78fb ldrb r3, [r7, #3]
|
|
80030b6: 015a lsls r2, r3, #5
|
|
80030b8: 693b ldr r3, [r7, #16]
|
|
80030ba: 4413 add r3, r2
|
|
80030bc: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80030c0: 681b ldr r3, [r3, #0]
|
|
80030c2: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
80030c4: 68fb ldr r3, [r7, #12]
|
|
80030c6: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
80030ca: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
80030cc: 68fb ldr r3, [r7, #12]
|
|
80030ce: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80030d2: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
80030d4: 78fb ldrb r3, [r7, #3]
|
|
80030d6: 015a lsls r2, r3, #5
|
|
80030d8: 693b ldr r3, [r7, #16]
|
|
80030da: 4413 add r3, r2
|
|
80030dc: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80030e0: 461a mov r2, r3
|
|
80030e2: 68fb ldr r3, [r7, #12]
|
|
80030e4: 6013 str r3, [r2, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
80030e6: e1ee b.n 80034c6 <HCD_HC_IN_IRQHandler+0xacc>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NYET)
|
|
80030e8: 78fa ldrb r2, [r7, #3]
|
|
80030ea: 6879 ldr r1, [r7, #4]
|
|
80030ec: 4613 mov r3, r2
|
|
80030ee: 011b lsls r3, r3, #4
|
|
80030f0: 1a9b subs r3, r3, r2
|
|
80030f2: 009b lsls r3, r3, #2
|
|
80030f4: 440b add r3, r1
|
|
80030f6: 334d adds r3, #77 @ 0x4d
|
|
80030f8: 781b ldrb r3, [r3, #0]
|
|
80030fa: 2b05 cmp r3, #5
|
|
80030fc: f040 80c8 bne.w 8003290 <HCD_HC_IN_IRQHandler+0x896>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003100: 78fa ldrb r2, [r7, #3]
|
|
8003102: 6879 ldr r1, [r7, #4]
|
|
8003104: 4613 mov r3, r2
|
|
8003106: 011b lsls r3, r3, #4
|
|
8003108: 1a9b subs r3, r3, r2
|
|
800310a: 009b lsls r3, r3, #2
|
|
800310c: 440b add r3, r1
|
|
800310e: 334d adds r3, #77 @ 0x4d
|
|
8003110: 2202 movs r2, #2
|
|
8003112: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003114: 78fa ldrb r2, [r7, #3]
|
|
8003116: 6879 ldr r1, [r7, #4]
|
|
8003118: 4613 mov r3, r2
|
|
800311a: 011b lsls r3, r3, #4
|
|
800311c: 1a9b subs r3, r3, r2
|
|
800311e: 009b lsls r3, r3, #2
|
|
8003120: 440b add r3, r1
|
|
8003122: 331b adds r3, #27
|
|
8003124: 781b ldrb r3, [r3, #0]
|
|
8003126: 2b01 cmp r3, #1
|
|
8003128: f040 81ce bne.w 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
|
|
800312c: 78fa ldrb r2, [r7, #3]
|
|
800312e: 6879 ldr r1, [r7, #4]
|
|
8003130: 4613 mov r3, r2
|
|
8003132: 011b lsls r3, r3, #4
|
|
8003134: 1a9b subs r3, r3, r2
|
|
8003136: 009b lsls r3, r3, #2
|
|
8003138: 440b add r3, r1
|
|
800313a: 3326 adds r3, #38 @ 0x26
|
|
800313c: 781b ldrb r3, [r3, #0]
|
|
800313e: 2b03 cmp r3, #3
|
|
8003140: d16b bne.n 800321a <HCD_HC_IN_IRQHandler+0x820>
|
|
{
|
|
hhcd->hc[chnum].NyetErrCnt++;
|
|
8003142: 78fa ldrb r2, [r7, #3]
|
|
8003144: 6879 ldr r1, [r7, #4]
|
|
8003146: 4613 mov r3, r2
|
|
8003148: 011b lsls r3, r3, #4
|
|
800314a: 1a9b subs r3, r3, r2
|
|
800314c: 009b lsls r3, r3, #2
|
|
800314e: 440b add r3, r1
|
|
8003150: 3348 adds r3, #72 @ 0x48
|
|
8003152: 681b ldr r3, [r3, #0]
|
|
8003154: 1c59 adds r1, r3, #1
|
|
8003156: 6878 ldr r0, [r7, #4]
|
|
8003158: 4613 mov r3, r2
|
|
800315a: 011b lsls r3, r3, #4
|
|
800315c: 1a9b subs r3, r3, r2
|
|
800315e: 009b lsls r3, r3, #2
|
|
8003160: 4403 add r3, r0
|
|
8003162: 3348 adds r3, #72 @ 0x48
|
|
8003164: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].NyetErrCnt > 2U)
|
|
8003166: 78fa ldrb r2, [r7, #3]
|
|
8003168: 6879 ldr r1, [r7, #4]
|
|
800316a: 4613 mov r3, r2
|
|
800316c: 011b lsls r3, r3, #4
|
|
800316e: 1a9b subs r3, r3, r2
|
|
8003170: 009b lsls r3, r3, #2
|
|
8003172: 440b add r3, r1
|
|
8003174: 3348 adds r3, #72 @ 0x48
|
|
8003176: 681b ldr r3, [r3, #0]
|
|
8003178: 2b02 cmp r3, #2
|
|
800317a: d943 bls.n 8003204 <HCD_HC_IN_IRQHandler+0x80a>
|
|
{
|
|
hhcd->hc[chnum].NyetErrCnt = 0U;
|
|
800317c: 78fa ldrb r2, [r7, #3]
|
|
800317e: 6879 ldr r1, [r7, #4]
|
|
8003180: 4613 mov r3, r2
|
|
8003182: 011b lsls r3, r3, #4
|
|
8003184: 1a9b subs r3, r3, r2
|
|
8003186: 009b lsls r3, r3, #2
|
|
8003188: 440b add r3, r1
|
|
800318a: 3348 adds r3, #72 @ 0x48
|
|
800318c: 2200 movs r2, #0
|
|
800318e: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8003190: 78fa ldrb r2, [r7, #3]
|
|
8003192: 6879 ldr r1, [r7, #4]
|
|
8003194: 4613 mov r3, r2
|
|
8003196: 011b lsls r3, r3, #4
|
|
8003198: 1a9b subs r3, r3, r2
|
|
800319a: 009b lsls r3, r3, #2
|
|
800319c: 440b add r3, r1
|
|
800319e: 331b adds r3, #27
|
|
80031a0: 2200 movs r2, #0
|
|
80031a2: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].ErrCnt < 3U)
|
|
80031a4: 78fa ldrb r2, [r7, #3]
|
|
80031a6: 6879 ldr r1, [r7, #4]
|
|
80031a8: 4613 mov r3, r2
|
|
80031aa: 011b lsls r3, r3, #4
|
|
80031ac: 1a9b subs r3, r3, r2
|
|
80031ae: 009b lsls r3, r3, #2
|
|
80031b0: 440b add r3, r1
|
|
80031b2: 3344 adds r3, #68 @ 0x44
|
|
80031b4: 681b ldr r3, [r3, #0]
|
|
80031b6: 2b02 cmp r3, #2
|
|
80031b8: d809 bhi.n 80031ce <HCD_HC_IN_IRQHandler+0x7d4>
|
|
{
|
|
hhcd->hc[chnum].ep_ss_schedule = 1U;
|
|
80031ba: 78fa ldrb r2, [r7, #3]
|
|
80031bc: 6879 ldr r1, [r7, #4]
|
|
80031be: 4613 mov r3, r2
|
|
80031c0: 011b lsls r3, r3, #4
|
|
80031c2: 1a9b subs r3, r3, r2
|
|
80031c4: 009b lsls r3, r3, #2
|
|
80031c6: 440b add r3, r1
|
|
80031c8: 331c adds r3, #28
|
|
80031ca: 2201 movs r2, #1
|
|
80031cc: 701a strb r2, [r3, #0]
|
|
}
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
80031ce: 78fb ldrb r3, [r7, #3]
|
|
80031d0: 015a lsls r2, r3, #5
|
|
80031d2: 693b ldr r3, [r7, #16]
|
|
80031d4: 4413 add r3, r2
|
|
80031d6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80031da: 685b ldr r3, [r3, #4]
|
|
80031dc: 78fa ldrb r2, [r7, #3]
|
|
80031de: 0151 lsls r1, r2, #5
|
|
80031e0: 693a ldr r2, [r7, #16]
|
|
80031e2: 440a add r2, r1
|
|
80031e4: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80031e8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80031ec: 6053 str r3, [r2, #4]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
80031ee: 78fa ldrb r2, [r7, #3]
|
|
80031f0: 6879 ldr r1, [r7, #4]
|
|
80031f2: 4613 mov r3, r2
|
|
80031f4: 011b lsls r3, r3, #4
|
|
80031f6: 1a9b subs r3, r3, r2
|
|
80031f8: 009b lsls r3, r3, #2
|
|
80031fa: 440b add r3, r1
|
|
80031fc: 334c adds r3, #76 @ 0x4c
|
|
80031fe: 2204 movs r2, #4
|
|
8003200: 701a strb r2, [r3, #0]
|
|
8003202: e014 b.n 800322e <HCD_HC_IN_IRQHandler+0x834>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003204: 78fa ldrb r2, [r7, #3]
|
|
8003206: 6879 ldr r1, [r7, #4]
|
|
8003208: 4613 mov r3, r2
|
|
800320a: 011b lsls r3, r3, #4
|
|
800320c: 1a9b subs r3, r3, r2
|
|
800320e: 009b lsls r3, r3, #2
|
|
8003210: 440b add r3, r1
|
|
8003212: 334c adds r3, #76 @ 0x4c
|
|
8003214: 2202 movs r2, #2
|
|
8003216: 701a strb r2, [r3, #0]
|
|
8003218: e009 b.n 800322e <HCD_HC_IN_IRQHandler+0x834>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
800321a: 78fa ldrb r2, [r7, #3]
|
|
800321c: 6879 ldr r1, [r7, #4]
|
|
800321e: 4613 mov r3, r2
|
|
8003220: 011b lsls r3, r3, #4
|
|
8003222: 1a9b subs r3, r3, r2
|
|
8003224: 009b lsls r3, r3, #2
|
|
8003226: 440b add r3, r1
|
|
8003228: 334c adds r3, #76 @ 0x4c
|
|
800322a: 2202 movs r2, #2
|
|
800322c: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
800322e: 78fa ldrb r2, [r7, #3]
|
|
8003230: 6879 ldr r1, [r7, #4]
|
|
8003232: 4613 mov r3, r2
|
|
8003234: 011b lsls r3, r3, #4
|
|
8003236: 1a9b subs r3, r3, r2
|
|
8003238: 009b lsls r3, r3, #2
|
|
800323a: 440b add r3, r1
|
|
800323c: 3326 adds r3, #38 @ 0x26
|
|
800323e: 781b ldrb r3, [r3, #0]
|
|
8003240: 2b00 cmp r3, #0
|
|
8003242: d00b beq.n 800325c <HCD_HC_IN_IRQHandler+0x862>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8003244: 78fa ldrb r2, [r7, #3]
|
|
8003246: 6879 ldr r1, [r7, #4]
|
|
8003248: 4613 mov r3, r2
|
|
800324a: 011b lsls r3, r3, #4
|
|
800324c: 1a9b subs r3, r3, r2
|
|
800324e: 009b lsls r3, r3, #2
|
|
8003250: 440b add r3, r1
|
|
8003252: 3326 adds r3, #38 @ 0x26
|
|
8003254: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8003256: 2b02 cmp r3, #2
|
|
8003258: f040 8136 bne.w 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
800325c: 78fb ldrb r3, [r7, #3]
|
|
800325e: 015a lsls r2, r3, #5
|
|
8003260: 693b ldr r3, [r7, #16]
|
|
8003262: 4413 add r3, r2
|
|
8003264: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003268: 681b ldr r3, [r3, #0]
|
|
800326a: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
800326c: 68fb ldr r3, [r7, #12]
|
|
800326e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003272: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8003274: 68fb ldr r3, [r7, #12]
|
|
8003276: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800327a: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
800327c: 78fb ldrb r3, [r7, #3]
|
|
800327e: 015a lsls r2, r3, #5
|
|
8003280: 693b ldr r3, [r7, #16]
|
|
8003282: 4413 add r3, r2
|
|
8003284: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003288: 461a mov r2, r3
|
|
800328a: 68fb ldr r3, [r7, #12]
|
|
800328c: 6013 str r3, [r2, #0]
|
|
800328e: e11b b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_ACK)
|
|
8003290: 78fa ldrb r2, [r7, #3]
|
|
8003292: 6879 ldr r1, [r7, #4]
|
|
8003294: 4613 mov r3, r2
|
|
8003296: 011b lsls r3, r3, #4
|
|
8003298: 1a9b subs r3, r3, r2
|
|
800329a: 009b lsls r3, r3, #2
|
|
800329c: 440b add r3, r1
|
|
800329e: 334d adds r3, #77 @ 0x4d
|
|
80032a0: 781b ldrb r3, [r3, #0]
|
|
80032a2: 2b03 cmp r3, #3
|
|
80032a4: f040 8081 bne.w 80033aa <HCD_HC_IN_IRQHandler+0x9b0>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
80032a8: 78fa ldrb r2, [r7, #3]
|
|
80032aa: 6879 ldr r1, [r7, #4]
|
|
80032ac: 4613 mov r3, r2
|
|
80032ae: 011b lsls r3, r3, #4
|
|
80032b0: 1a9b subs r3, r3, r2
|
|
80032b2: 009b lsls r3, r3, #2
|
|
80032b4: 440b add r3, r1
|
|
80032b6: 334d adds r3, #77 @ 0x4d
|
|
80032b8: 2202 movs r2, #2
|
|
80032ba: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
80032bc: 78fa ldrb r2, [r7, #3]
|
|
80032be: 6879 ldr r1, [r7, #4]
|
|
80032c0: 4613 mov r3, r2
|
|
80032c2: 011b lsls r3, r3, #4
|
|
80032c4: 1a9b subs r3, r3, r2
|
|
80032c6: 009b lsls r3, r3, #2
|
|
80032c8: 440b add r3, r1
|
|
80032ca: 331b adds r3, #27
|
|
80032cc: 781b ldrb r3, [r3, #0]
|
|
80032ce: 2b01 cmp r3, #1
|
|
80032d0: f040 80fa bne.w 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
80032d4: 78fa ldrb r2, [r7, #3]
|
|
80032d6: 6879 ldr r1, [r7, #4]
|
|
80032d8: 4613 mov r3, r2
|
|
80032da: 011b lsls r3, r3, #4
|
|
80032dc: 1a9b subs r3, r3, r2
|
|
80032de: 009b lsls r3, r3, #2
|
|
80032e0: 440b add r3, r1
|
|
80032e2: 334c adds r3, #76 @ 0x4c
|
|
80032e4: 2202 movs r2, #2
|
|
80032e6: 701a strb r2, [r3, #0]
|
|
|
|
/* Set Complete split and re-activate the channel */
|
|
USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
|
|
80032e8: 78fb ldrb r3, [r7, #3]
|
|
80032ea: 015a lsls r2, r3, #5
|
|
80032ec: 693b ldr r3, [r7, #16]
|
|
80032ee: 4413 add r3, r2
|
|
80032f0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80032f4: 685b ldr r3, [r3, #4]
|
|
80032f6: 78fa ldrb r2, [r7, #3]
|
|
80032f8: 0151 lsls r1, r2, #5
|
|
80032fa: 693a ldr r2, [r7, #16]
|
|
80032fc: 440a add r2, r1
|
|
80032fe: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8003302: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003306: 6053 str r3, [r2, #4]
|
|
USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
|
|
8003308: 78fb ldrb r3, [r7, #3]
|
|
800330a: 015a lsls r2, r3, #5
|
|
800330c: 693b ldr r3, [r7, #16]
|
|
800330e: 4413 add r3, r2
|
|
8003310: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003314: 68db ldr r3, [r3, #12]
|
|
8003316: 78fa ldrb r2, [r7, #3]
|
|
8003318: 0151 lsls r1, r2, #5
|
|
800331a: 693a ldr r2, [r7, #16]
|
|
800331c: 440a add r2, r1
|
|
800331e: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8003322: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8003326: 60d3 str r3, [r2, #12]
|
|
USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
|
|
8003328: 78fb ldrb r3, [r7, #3]
|
|
800332a: 015a lsls r2, r3, #5
|
|
800332c: 693b ldr r3, [r7, #16]
|
|
800332e: 4413 add r3, r2
|
|
8003330: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003334: 68db ldr r3, [r3, #12]
|
|
8003336: 78fa ldrb r2, [r7, #3]
|
|
8003338: 0151 lsls r1, r2, #5
|
|
800333a: 693a ldr r2, [r7, #16]
|
|
800333c: 440a add r2, r1
|
|
800333e: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8003342: f023 0320 bic.w r3, r3, #32
|
|
8003346: 60d3 str r3, [r2, #12]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8003348: 78fa ldrb r2, [r7, #3]
|
|
800334a: 6879 ldr r1, [r7, #4]
|
|
800334c: 4613 mov r3, r2
|
|
800334e: 011b lsls r3, r3, #4
|
|
8003350: 1a9b subs r3, r3, r2
|
|
8003352: 009b lsls r3, r3, #2
|
|
8003354: 440b add r3, r1
|
|
8003356: 3326 adds r3, #38 @ 0x26
|
|
8003358: 781b ldrb r3, [r3, #0]
|
|
800335a: 2b00 cmp r3, #0
|
|
800335c: d00b beq.n 8003376 <HCD_HC_IN_IRQHandler+0x97c>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
800335e: 78fa ldrb r2, [r7, #3]
|
|
8003360: 6879 ldr r1, [r7, #4]
|
|
8003362: 4613 mov r3, r2
|
|
8003364: 011b lsls r3, r3, #4
|
|
8003366: 1a9b subs r3, r3, r2
|
|
8003368: 009b lsls r3, r3, #2
|
|
800336a: 440b add r3, r1
|
|
800336c: 3326 adds r3, #38 @ 0x26
|
|
800336e: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8003370: 2b02 cmp r3, #2
|
|
8003372: f040 80a9 bne.w 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8003376: 78fb ldrb r3, [r7, #3]
|
|
8003378: 015a lsls r2, r3, #5
|
|
800337a: 693b ldr r3, [r7, #16]
|
|
800337c: 4413 add r3, r2
|
|
800337e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003382: 681b ldr r3, [r3, #0]
|
|
8003384: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8003386: 68fb ldr r3, [r7, #12]
|
|
8003388: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
800338c: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
800338e: 68fb ldr r3, [r7, #12]
|
|
8003390: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003394: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8003396: 78fb ldrb r3, [r7, #3]
|
|
8003398: 015a lsls r2, r3, #5
|
|
800339a: 693b ldr r3, [r7, #16]
|
|
800339c: 4413 add r3, r2
|
|
800339e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80033a2: 461a mov r2, r3
|
|
80033a4: 68fb ldr r3, [r7, #12]
|
|
80033a6: 6013 str r3, [r2, #0]
|
|
80033a8: e08e b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NAK)
|
|
80033aa: 78fa ldrb r2, [r7, #3]
|
|
80033ac: 6879 ldr r1, [r7, #4]
|
|
80033ae: 4613 mov r3, r2
|
|
80033b0: 011b lsls r3, r3, #4
|
|
80033b2: 1a9b subs r3, r3, r2
|
|
80033b4: 009b lsls r3, r3, #2
|
|
80033b6: 440b add r3, r1
|
|
80033b8: 334d adds r3, #77 @ 0x4d
|
|
80033ba: 781b ldrb r3, [r3, #0]
|
|
80033bc: 2b04 cmp r3, #4
|
|
80033be: d143 bne.n 8003448 <HCD_HC_IN_IRQHandler+0xa4e>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
80033c0: 78fa ldrb r2, [r7, #3]
|
|
80033c2: 6879 ldr r1, [r7, #4]
|
|
80033c4: 4613 mov r3, r2
|
|
80033c6: 011b lsls r3, r3, #4
|
|
80033c8: 1a9b subs r3, r3, r2
|
|
80033ca: 009b lsls r3, r3, #2
|
|
80033cc: 440b add r3, r1
|
|
80033ce: 334d adds r3, #77 @ 0x4d
|
|
80033d0: 2202 movs r2, #2
|
|
80033d2: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
80033d4: 78fa ldrb r2, [r7, #3]
|
|
80033d6: 6879 ldr r1, [r7, #4]
|
|
80033d8: 4613 mov r3, r2
|
|
80033da: 011b lsls r3, r3, #4
|
|
80033dc: 1a9b subs r3, r3, r2
|
|
80033de: 009b lsls r3, r3, #2
|
|
80033e0: 440b add r3, r1
|
|
80033e2: 334c adds r3, #76 @ 0x4c
|
|
80033e4: 2202 movs r2, #2
|
|
80033e6: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80033e8: 78fa ldrb r2, [r7, #3]
|
|
80033ea: 6879 ldr r1, [r7, #4]
|
|
80033ec: 4613 mov r3, r2
|
|
80033ee: 011b lsls r3, r3, #4
|
|
80033f0: 1a9b subs r3, r3, r2
|
|
80033f2: 009b lsls r3, r3, #2
|
|
80033f4: 440b add r3, r1
|
|
80033f6: 3326 adds r3, #38 @ 0x26
|
|
80033f8: 781b ldrb r3, [r3, #0]
|
|
80033fa: 2b00 cmp r3, #0
|
|
80033fc: d00a beq.n 8003414 <HCD_HC_IN_IRQHandler+0xa1a>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
80033fe: 78fa ldrb r2, [r7, #3]
|
|
8003400: 6879 ldr r1, [r7, #4]
|
|
8003402: 4613 mov r3, r2
|
|
8003404: 011b lsls r3, r3, #4
|
|
8003406: 1a9b subs r3, r3, r2
|
|
8003408: 009b lsls r3, r3, #2
|
|
800340a: 440b add r3, r1
|
|
800340c: 3326 adds r3, #38 @ 0x26
|
|
800340e: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8003410: 2b02 cmp r3, #2
|
|
8003412: d159 bne.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8003414: 78fb ldrb r3, [r7, #3]
|
|
8003416: 015a lsls r2, r3, #5
|
|
8003418: 693b ldr r3, [r7, #16]
|
|
800341a: 4413 add r3, r2
|
|
800341c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003420: 681b ldr r3, [r3, #0]
|
|
8003422: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8003424: 68fb ldr r3, [r7, #12]
|
|
8003426: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
800342a: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
800342c: 68fb ldr r3, [r7, #12]
|
|
800342e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003432: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8003434: 78fb ldrb r3, [r7, #3]
|
|
8003436: 015a lsls r2, r3, #5
|
|
8003438: 693b ldr r3, [r7, #16]
|
|
800343a: 4413 add r3, r2
|
|
800343c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003440: 461a mov r2, r3
|
|
8003442: 68fb ldr r3, [r7, #12]
|
|
8003444: 6013 str r3, [r2, #0]
|
|
8003446: e03f b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_BBLERR)
|
|
8003448: 78fa ldrb r2, [r7, #3]
|
|
800344a: 6879 ldr r1, [r7, #4]
|
|
800344c: 4613 mov r3, r2
|
|
800344e: 011b lsls r3, r3, #4
|
|
8003450: 1a9b subs r3, r3, r2
|
|
8003452: 009b lsls r3, r3, #2
|
|
8003454: 440b add r3, r1
|
|
8003456: 334d adds r3, #77 @ 0x4d
|
|
8003458: 781b ldrb r3, [r3, #0]
|
|
800345a: 2b08 cmp r3, #8
|
|
800345c: d126 bne.n 80034ac <HCD_HC_IN_IRQHandler+0xab2>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
800345e: 78fa ldrb r2, [r7, #3]
|
|
8003460: 6879 ldr r1, [r7, #4]
|
|
8003462: 4613 mov r3, r2
|
|
8003464: 011b lsls r3, r3, #4
|
|
8003466: 1a9b subs r3, r3, r2
|
|
8003468: 009b lsls r3, r3, #2
|
|
800346a: 440b add r3, r1
|
|
800346c: 334d adds r3, #77 @ 0x4d
|
|
800346e: 2202 movs r2, #2
|
|
8003470: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8003472: 78fa ldrb r2, [r7, #3]
|
|
8003474: 6879 ldr r1, [r7, #4]
|
|
8003476: 4613 mov r3, r2
|
|
8003478: 011b lsls r3, r3, #4
|
|
800347a: 1a9b subs r3, r3, r2
|
|
800347c: 009b lsls r3, r3, #2
|
|
800347e: 440b add r3, r1
|
|
8003480: 3344 adds r3, #68 @ 0x44
|
|
8003482: 681b ldr r3, [r3, #0]
|
|
8003484: 1c59 adds r1, r3, #1
|
|
8003486: 6878 ldr r0, [r7, #4]
|
|
8003488: 4613 mov r3, r2
|
|
800348a: 011b lsls r3, r3, #4
|
|
800348c: 1a9b subs r3, r3, r2
|
|
800348e: 009b lsls r3, r3, #2
|
|
8003490: 4403 add r3, r0
|
|
8003492: 3344 adds r3, #68 @ 0x44
|
|
8003494: 6019 str r1, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8003496: 78fa ldrb r2, [r7, #3]
|
|
8003498: 6879 ldr r1, [r7, #4]
|
|
800349a: 4613 mov r3, r2
|
|
800349c: 011b lsls r3, r3, #4
|
|
800349e: 1a9b subs r3, r3, r2
|
|
80034a0: 009b lsls r3, r3, #2
|
|
80034a2: 440b add r3, r1
|
|
80034a4: 334c adds r3, #76 @ 0x4c
|
|
80034a6: 2204 movs r2, #4
|
|
80034a8: 701a strb r2, [r3, #0]
|
|
80034aa: e00d b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else
|
|
{
|
|
if (hhcd->hc[chnum].state == HC_HALTED)
|
|
80034ac: 78fa ldrb r2, [r7, #3]
|
|
80034ae: 6879 ldr r1, [r7, #4]
|
|
80034b0: 4613 mov r3, r2
|
|
80034b2: 011b lsls r3, r3, #4
|
|
80034b4: 1a9b subs r3, r3, r2
|
|
80034b6: 009b lsls r3, r3, #2
|
|
80034b8: 440b add r3, r1
|
|
80034ba: 334d adds r3, #77 @ 0x4d
|
|
80034bc: 781b ldrb r3, [r3, #0]
|
|
80034be: 2b02 cmp r3, #2
|
|
80034c0: f000 8100 beq.w 80036c4 <HCD_HC_IN_IRQHandler+0xcca>
|
|
80034c4: e000 b.n 80034c8 <HCD_HC_IN_IRQHandler+0xace>
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
80034c6: bf00 nop
|
|
}
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
80034c8: 78fa ldrb r2, [r7, #3]
|
|
80034ca: 6879 ldr r1, [r7, #4]
|
|
80034cc: 4613 mov r3, r2
|
|
80034ce: 011b lsls r3, r3, #4
|
|
80034d0: 1a9b subs r3, r3, r2
|
|
80034d2: 009b lsls r3, r3, #2
|
|
80034d4: 440b add r3, r1
|
|
80034d6: 334c adds r3, #76 @ 0x4c
|
|
80034d8: 781a ldrb r2, [r3, #0]
|
|
80034da: 78fb ldrb r3, [r7, #3]
|
|
80034dc: 4619 mov r1, r3
|
|
80034de: 6878 ldr r0, [r7, #4]
|
|
80034e0: f009 fa5c bl 800c99c <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
80034e4: e0ef b.n 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
80034e6: 687b ldr r3, [r7, #4]
|
|
80034e8: 681b ldr r3, [r3, #0]
|
|
80034ea: 78fa ldrb r2, [r7, #3]
|
|
80034ec: 4611 mov r1, r2
|
|
80034ee: 4618 mov r0, r3
|
|
80034f0: f003 fce9 bl 8006ec6 <USB_ReadChInterrupts>
|
|
80034f4: 4603 mov r3, r0
|
|
80034f6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80034fa: 2b40 cmp r3, #64 @ 0x40
|
|
80034fc: d12f bne.n 800355e <HCD_HC_IN_IRQHandler+0xb64>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
80034fe: 78fb ldrb r3, [r7, #3]
|
|
8003500: 015a lsls r2, r3, #5
|
|
8003502: 693b ldr r3, [r7, #16]
|
|
8003504: 4413 add r3, r2
|
|
8003506: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800350a: 461a mov r2, r3
|
|
800350c: 2340 movs r3, #64 @ 0x40
|
|
800350e: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_NYET;
|
|
8003510: 78fa ldrb r2, [r7, #3]
|
|
8003512: 6879 ldr r1, [r7, #4]
|
|
8003514: 4613 mov r3, r2
|
|
8003516: 011b lsls r3, r3, #4
|
|
8003518: 1a9b subs r3, r3, r2
|
|
800351a: 009b lsls r3, r3, #2
|
|
800351c: 440b add r3, r1
|
|
800351e: 334d adds r3, #77 @ 0x4d
|
|
8003520: 2205 movs r2, #5
|
|
8003522: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 0U)
|
|
8003524: 78fa ldrb r2, [r7, #3]
|
|
8003526: 6879 ldr r1, [r7, #4]
|
|
8003528: 4613 mov r3, r2
|
|
800352a: 011b lsls r3, r3, #4
|
|
800352c: 1a9b subs r3, r3, r2
|
|
800352e: 009b lsls r3, r3, #2
|
|
8003530: 440b add r3, r1
|
|
8003532: 331a adds r3, #26
|
|
8003534: 781b ldrb r3, [r3, #0]
|
|
8003536: 2b00 cmp r3, #0
|
|
8003538: d109 bne.n 800354e <HCD_HC_IN_IRQHandler+0xb54>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
800353a: 78fa ldrb r2, [r7, #3]
|
|
800353c: 6879 ldr r1, [r7, #4]
|
|
800353e: 4613 mov r3, r2
|
|
8003540: 011b lsls r3, r3, #4
|
|
8003542: 1a9b subs r3, r3, r2
|
|
8003544: 009b lsls r3, r3, #2
|
|
8003546: 440b add r3, r1
|
|
8003548: 3344 adds r3, #68 @ 0x44
|
|
800354a: 2200 movs r2, #0
|
|
800354c: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800354e: 687b ldr r3, [r7, #4]
|
|
8003550: 681b ldr r3, [r3, #0]
|
|
8003552: 78fa ldrb r2, [r7, #3]
|
|
8003554: 4611 mov r1, r2
|
|
8003556: 4618 mov r0, r3
|
|
8003558: f004 fa5f bl 8007a1a <USB_HC_Halt>
|
|
800355c: e0b3 b.n 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
|
|
800355e: 687b ldr r3, [r7, #4]
|
|
8003560: 681b ldr r3, [r3, #0]
|
|
8003562: 78fa ldrb r2, [r7, #3]
|
|
8003564: 4611 mov r1, r2
|
|
8003566: 4618 mov r0, r3
|
|
8003568: f003 fcad bl 8006ec6 <USB_ReadChInterrupts>
|
|
800356c: 4603 mov r3, r0
|
|
800356e: f003 0310 and.w r3, r3, #16
|
|
8003572: 2b10 cmp r3, #16
|
|
8003574: f040 80a7 bne.w 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
|
|
8003578: 78fa ldrb r2, [r7, #3]
|
|
800357a: 6879 ldr r1, [r7, #4]
|
|
800357c: 4613 mov r3, r2
|
|
800357e: 011b lsls r3, r3, #4
|
|
8003580: 1a9b subs r3, r3, r2
|
|
8003582: 009b lsls r3, r3, #2
|
|
8003584: 440b add r3, r1
|
|
8003586: 3326 adds r3, #38 @ 0x26
|
|
8003588: 781b ldrb r3, [r3, #0]
|
|
800358a: 2b03 cmp r3, #3
|
|
800358c: d11b bne.n 80035c6 <HCD_HC_IN_IRQHandler+0xbcc>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
800358e: 78fa ldrb r2, [r7, #3]
|
|
8003590: 6879 ldr r1, [r7, #4]
|
|
8003592: 4613 mov r3, r2
|
|
8003594: 011b lsls r3, r3, #4
|
|
8003596: 1a9b subs r3, r3, r2
|
|
8003598: 009b lsls r3, r3, #2
|
|
800359a: 440b add r3, r1
|
|
800359c: 3344 adds r3, #68 @ 0x44
|
|
800359e: 2200 movs r2, #0
|
|
80035a0: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
80035a2: 78fa ldrb r2, [r7, #3]
|
|
80035a4: 6879 ldr r1, [r7, #4]
|
|
80035a6: 4613 mov r3, r2
|
|
80035a8: 011b lsls r3, r3, #4
|
|
80035aa: 1a9b subs r3, r3, r2
|
|
80035ac: 009b lsls r3, r3, #2
|
|
80035ae: 440b add r3, r1
|
|
80035b0: 334d adds r3, #77 @ 0x4d
|
|
80035b2: 2204 movs r2, #4
|
|
80035b4: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80035b6: 687b ldr r3, [r7, #4]
|
|
80035b8: 681b ldr r3, [r3, #0]
|
|
80035ba: 78fa ldrb r2, [r7, #3]
|
|
80035bc: 4611 mov r1, r2
|
|
80035be: 4618 mov r0, r3
|
|
80035c0: f004 fa2b bl 8007a1a <USB_HC_Halt>
|
|
80035c4: e03f b.n 8003646 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
}
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80035c6: 78fa ldrb r2, [r7, #3]
|
|
80035c8: 6879 ldr r1, [r7, #4]
|
|
80035ca: 4613 mov r3, r2
|
|
80035cc: 011b lsls r3, r3, #4
|
|
80035ce: 1a9b subs r3, r3, r2
|
|
80035d0: 009b lsls r3, r3, #2
|
|
80035d2: 440b add r3, r1
|
|
80035d4: 3326 adds r3, #38 @ 0x26
|
|
80035d6: 781b ldrb r3, [r3, #0]
|
|
80035d8: 2b00 cmp r3, #0
|
|
80035da: d00a beq.n 80035f2 <HCD_HC_IN_IRQHandler+0xbf8>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
80035dc: 78fa ldrb r2, [r7, #3]
|
|
80035de: 6879 ldr r1, [r7, #4]
|
|
80035e0: 4613 mov r3, r2
|
|
80035e2: 011b lsls r3, r3, #4
|
|
80035e4: 1a9b subs r3, r3, r2
|
|
80035e6: 009b lsls r3, r3, #2
|
|
80035e8: 440b add r3, r1
|
|
80035ea: 3326 adds r3, #38 @ 0x26
|
|
80035ec: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80035ee: 2b02 cmp r3, #2
|
|
80035f0: d129 bne.n 8003646 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80035f2: 78fa ldrb r2, [r7, #3]
|
|
80035f4: 6879 ldr r1, [r7, #4]
|
|
80035f6: 4613 mov r3, r2
|
|
80035f8: 011b lsls r3, r3, #4
|
|
80035fa: 1a9b subs r3, r3, r2
|
|
80035fc: 009b lsls r3, r3, #2
|
|
80035fe: 440b add r3, r1
|
|
8003600: 3344 adds r3, #68 @ 0x44
|
|
8003602: 2200 movs r2, #0
|
|
8003604: 601a str r2, [r3, #0]
|
|
|
|
if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
|
|
8003606: 687b ldr r3, [r7, #4]
|
|
8003608: 799b ldrb r3, [r3, #6]
|
|
800360a: 2b00 cmp r3, #0
|
|
800360c: d00a beq.n 8003624 <HCD_HC_IN_IRQHandler+0xc2a>
|
|
800360e: 78fa ldrb r2, [r7, #3]
|
|
8003610: 6879 ldr r1, [r7, #4]
|
|
8003612: 4613 mov r3, r2
|
|
8003614: 011b lsls r3, r3, #4
|
|
8003616: 1a9b subs r3, r3, r2
|
|
8003618: 009b lsls r3, r3, #2
|
|
800361a: 440b add r3, r1
|
|
800361c: 331b adds r3, #27
|
|
800361e: 781b ldrb r3, [r3, #0]
|
|
8003620: 2b01 cmp r3, #1
|
|
8003622: d110 bne.n 8003646 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
{
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
8003624: 78fa ldrb r2, [r7, #3]
|
|
8003626: 6879 ldr r1, [r7, #4]
|
|
8003628: 4613 mov r3, r2
|
|
800362a: 011b lsls r3, r3, #4
|
|
800362c: 1a9b subs r3, r3, r2
|
|
800362e: 009b lsls r3, r3, #2
|
|
8003630: 440b add r3, r1
|
|
8003632: 334d adds r3, #77 @ 0x4d
|
|
8003634: 2204 movs r2, #4
|
|
8003636: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003638: 687b ldr r3, [r7, #4]
|
|
800363a: 681b ldr r3, [r3, #0]
|
|
800363c: 78fa ldrb r2, [r7, #3]
|
|
800363e: 4611 mov r1, r2
|
|
8003640: 4618 mov r0, r3
|
|
8003642: f004 f9ea bl 8007a1a <USB_HC_Halt>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003646: 78fa ldrb r2, [r7, #3]
|
|
8003648: 6879 ldr r1, [r7, #4]
|
|
800364a: 4613 mov r3, r2
|
|
800364c: 011b lsls r3, r3, #4
|
|
800364e: 1a9b subs r3, r3, r2
|
|
8003650: 009b lsls r3, r3, #2
|
|
8003652: 440b add r3, r1
|
|
8003654: 331b adds r3, #27
|
|
8003656: 781b ldrb r3, [r3, #0]
|
|
8003658: 2b01 cmp r3, #1
|
|
800365a: d129 bne.n 80036b0 <HCD_HC_IN_IRQHandler+0xcb6>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
800365c: 78fa ldrb r2, [r7, #3]
|
|
800365e: 6879 ldr r1, [r7, #4]
|
|
8003660: 4613 mov r3, r2
|
|
8003662: 011b lsls r3, r3, #4
|
|
8003664: 1a9b subs r3, r3, r2
|
|
8003666: 009b lsls r3, r3, #2
|
|
8003668: 440b add r3, r1
|
|
800366a: 331b adds r3, #27
|
|
800366c: 2200 movs r2, #0
|
|
800366e: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8003670: 78fb ldrb r3, [r7, #3]
|
|
8003672: 015a lsls r2, r3, #5
|
|
8003674: 693b ldr r3, [r7, #16]
|
|
8003676: 4413 add r3, r2
|
|
8003678: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800367c: 685b ldr r3, [r3, #4]
|
|
800367e: 78fa ldrb r2, [r7, #3]
|
|
8003680: 0151 lsls r1, r2, #5
|
|
8003682: 693a ldr r2, [r7, #16]
|
|
8003684: 440a add r2, r1
|
|
8003686: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800368a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800368e: 6053 str r3, [r2, #4]
|
|
__HAL_HCD_UNMASK_ACK_HC_INT(chnum);
|
|
8003690: 78fb ldrb r3, [r7, #3]
|
|
8003692: 015a lsls r2, r3, #5
|
|
8003694: 693b ldr r3, [r7, #16]
|
|
8003696: 4413 add r3, r2
|
|
8003698: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800369c: 68db ldr r3, [r3, #12]
|
|
800369e: 78fa ldrb r2, [r7, #3]
|
|
80036a0: 0151 lsls r1, r2, #5
|
|
80036a2: 693a ldr r2, [r7, #16]
|
|
80036a4: 440a add r2, r1
|
|
80036a6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80036aa: f043 0320 orr.w r3, r3, #32
|
|
80036ae: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
80036b0: 78fb ldrb r3, [r7, #3]
|
|
80036b2: 015a lsls r2, r3, #5
|
|
80036b4: 693b ldr r3, [r7, #16]
|
|
80036b6: 4413 add r3, r2
|
|
80036b8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80036bc: 461a mov r2, r3
|
|
80036be: 2310 movs r3, #16
|
|
80036c0: 6093 str r3, [r2, #8]
|
|
80036c2: e000 b.n 80036c6 <HCD_HC_IN_IRQHandler+0xccc>
|
|
return;
|
|
80036c4: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
}
|
|
80036c6: 3718 adds r7, #24
|
|
80036c8: 46bd mov sp, r7
|
|
80036ca: bd80 pop {r7, pc}
|
|
|
|
080036cc <HCD_HC_OUT_IRQHandler>:
|
|
* @param chnum Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval none
|
|
*/
|
|
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|
{
|
|
80036cc: b580 push {r7, lr}
|
|
80036ce: b086 sub sp, #24
|
|
80036d0: af00 add r7, sp, #0
|
|
80036d2: 6078 str r0, [r7, #4]
|
|
80036d4: 460b mov r3, r1
|
|
80036d6: 70fb strb r3, [r7, #3]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
80036d8: 687b ldr r3, [r7, #4]
|
|
80036da: 681b ldr r3, [r3, #0]
|
|
80036dc: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80036de: 697b ldr r3, [r7, #20]
|
|
80036e0: 613b str r3, [r7, #16]
|
|
uint32_t tmpreg;
|
|
uint32_t num_packets;
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
|
|
80036e2: 687b ldr r3, [r7, #4]
|
|
80036e4: 681b ldr r3, [r3, #0]
|
|
80036e6: 78fa ldrb r2, [r7, #3]
|
|
80036e8: 4611 mov r1, r2
|
|
80036ea: 4618 mov r0, r3
|
|
80036ec: f003 fbeb bl 8006ec6 <USB_ReadChInterrupts>
|
|
80036f0: 4603 mov r3, r0
|
|
80036f2: f003 0304 and.w r3, r3, #4
|
|
80036f6: 2b04 cmp r3, #4
|
|
80036f8: d11b bne.n 8003732 <HCD_HC_OUT_IRQHandler+0x66>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
|
|
80036fa: 78fb ldrb r3, [r7, #3]
|
|
80036fc: 015a lsls r2, r3, #5
|
|
80036fe: 693b ldr r3, [r7, #16]
|
|
8003700: 4413 add r3, r2
|
|
8003702: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003706: 461a mov r2, r3
|
|
8003708: 2304 movs r3, #4
|
|
800370a: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
800370c: 78fa ldrb r2, [r7, #3]
|
|
800370e: 6879 ldr r1, [r7, #4]
|
|
8003710: 4613 mov r3, r2
|
|
8003712: 011b lsls r3, r3, #4
|
|
8003714: 1a9b subs r3, r3, r2
|
|
8003716: 009b lsls r3, r3, #2
|
|
8003718: 440b add r3, r1
|
|
800371a: 334d adds r3, #77 @ 0x4d
|
|
800371c: 2207 movs r2, #7
|
|
800371e: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003720: 687b ldr r3, [r7, #4]
|
|
8003722: 681b ldr r3, [r3, #0]
|
|
8003724: 78fa ldrb r2, [r7, #3]
|
|
8003726: 4611 mov r1, r2
|
|
8003728: 4618 mov r0, r3
|
|
800372a: f004 f976 bl 8007a1a <USB_HC_Halt>
|
|
800372e: f000 bc89 b.w 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
|
|
8003732: 687b ldr r3, [r7, #4]
|
|
8003734: 681b ldr r3, [r3, #0]
|
|
8003736: 78fa ldrb r2, [r7, #3]
|
|
8003738: 4611 mov r1, r2
|
|
800373a: 4618 mov r0, r3
|
|
800373c: f003 fbc3 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003740: 4603 mov r3, r0
|
|
8003742: f003 0320 and.w r3, r3, #32
|
|
8003746: 2b20 cmp r3, #32
|
|
8003748: f040 8082 bne.w 8003850 <HCD_HC_OUT_IRQHandler+0x184>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
800374c: 78fb ldrb r3, [r7, #3]
|
|
800374e: 015a lsls r2, r3, #5
|
|
8003750: 693b ldr r3, [r7, #16]
|
|
8003752: 4413 add r3, r2
|
|
8003754: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003758: 461a mov r2, r3
|
|
800375a: 2320 movs r3, #32
|
|
800375c: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_ping == 1U)
|
|
800375e: 78fa ldrb r2, [r7, #3]
|
|
8003760: 6879 ldr r1, [r7, #4]
|
|
8003762: 4613 mov r3, r2
|
|
8003764: 011b lsls r3, r3, #4
|
|
8003766: 1a9b subs r3, r3, r2
|
|
8003768: 009b lsls r3, r3, #2
|
|
800376a: 440b add r3, r1
|
|
800376c: 3319 adds r3, #25
|
|
800376e: 781b ldrb r3, [r3, #0]
|
|
8003770: 2b01 cmp r3, #1
|
|
8003772: d124 bne.n 80037be <HCD_HC_OUT_IRQHandler+0xf2>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 0U;
|
|
8003774: 78fa ldrb r2, [r7, #3]
|
|
8003776: 6879 ldr r1, [r7, #4]
|
|
8003778: 4613 mov r3, r2
|
|
800377a: 011b lsls r3, r3, #4
|
|
800377c: 1a9b subs r3, r3, r2
|
|
800377e: 009b lsls r3, r3, #2
|
|
8003780: 440b add r3, r1
|
|
8003782: 3319 adds r3, #25
|
|
8003784: 2200 movs r2, #0
|
|
8003786: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003788: 78fa ldrb r2, [r7, #3]
|
|
800378a: 6879 ldr r1, [r7, #4]
|
|
800378c: 4613 mov r3, r2
|
|
800378e: 011b lsls r3, r3, #4
|
|
8003790: 1a9b subs r3, r3, r2
|
|
8003792: 009b lsls r3, r3, #2
|
|
8003794: 440b add r3, r1
|
|
8003796: 334c adds r3, #76 @ 0x4c
|
|
8003798: 2202 movs r2, #2
|
|
800379a: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
800379c: 78fa ldrb r2, [r7, #3]
|
|
800379e: 6879 ldr r1, [r7, #4]
|
|
80037a0: 4613 mov r3, r2
|
|
80037a2: 011b lsls r3, r3, #4
|
|
80037a4: 1a9b subs r3, r3, r2
|
|
80037a6: 009b lsls r3, r3, #2
|
|
80037a8: 440b add r3, r1
|
|
80037aa: 334d adds r3, #77 @ 0x4d
|
|
80037ac: 2203 movs r2, #3
|
|
80037ae: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80037b0: 687b ldr r3, [r7, #4]
|
|
80037b2: 681b ldr r3, [r3, #0]
|
|
80037b4: 78fa ldrb r2, [r7, #3]
|
|
80037b6: 4611 mov r1, r2
|
|
80037b8: 4618 mov r0, r3
|
|
80037ba: f004 f92e bl 8007a1a <USB_HC_Halt>
|
|
}
|
|
|
|
if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
|
|
80037be: 78fa ldrb r2, [r7, #3]
|
|
80037c0: 6879 ldr r1, [r7, #4]
|
|
80037c2: 4613 mov r3, r2
|
|
80037c4: 011b lsls r3, r3, #4
|
|
80037c6: 1a9b subs r3, r3, r2
|
|
80037c8: 009b lsls r3, r3, #2
|
|
80037ca: 440b add r3, r1
|
|
80037cc: 331a adds r3, #26
|
|
80037ce: 781b ldrb r3, [r3, #0]
|
|
80037d0: 2b01 cmp r3, #1
|
|
80037d2: f040 8437 bne.w 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
80037d6: 78fa ldrb r2, [r7, #3]
|
|
80037d8: 6879 ldr r1, [r7, #4]
|
|
80037da: 4613 mov r3, r2
|
|
80037dc: 011b lsls r3, r3, #4
|
|
80037de: 1a9b subs r3, r3, r2
|
|
80037e0: 009b lsls r3, r3, #2
|
|
80037e2: 440b add r3, r1
|
|
80037e4: 331b adds r3, #27
|
|
80037e6: 781b ldrb r3, [r3, #0]
|
|
80037e8: 2b00 cmp r3, #0
|
|
80037ea: f040 842b bne.w 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
|
|
80037ee: 78fa ldrb r2, [r7, #3]
|
|
80037f0: 6879 ldr r1, [r7, #4]
|
|
80037f2: 4613 mov r3, r2
|
|
80037f4: 011b lsls r3, r3, #4
|
|
80037f6: 1a9b subs r3, r3, r2
|
|
80037f8: 009b lsls r3, r3, #2
|
|
80037fa: 440b add r3, r1
|
|
80037fc: 3326 adds r3, #38 @ 0x26
|
|
80037fe: 781b ldrb r3, [r3, #0]
|
|
8003800: 2b01 cmp r3, #1
|
|
8003802: d009 beq.n 8003818 <HCD_HC_OUT_IRQHandler+0x14c>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 1U;
|
|
8003804: 78fa ldrb r2, [r7, #3]
|
|
8003806: 6879 ldr r1, [r7, #4]
|
|
8003808: 4613 mov r3, r2
|
|
800380a: 011b lsls r3, r3, #4
|
|
800380c: 1a9b subs r3, r3, r2
|
|
800380e: 009b lsls r3, r3, #2
|
|
8003810: 440b add r3, r1
|
|
8003812: 331b adds r3, #27
|
|
8003814: 2201 movs r2, #1
|
|
8003816: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
8003818: 78fa ldrb r2, [r7, #3]
|
|
800381a: 6879 ldr r1, [r7, #4]
|
|
800381c: 4613 mov r3, r2
|
|
800381e: 011b lsls r3, r3, #4
|
|
8003820: 1a9b subs r3, r3, r2
|
|
8003822: 009b lsls r3, r3, #2
|
|
8003824: 440b add r3, r1
|
|
8003826: 334d adds r3, #77 @ 0x4d
|
|
8003828: 2203 movs r2, #3
|
|
800382a: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800382c: 687b ldr r3, [r7, #4]
|
|
800382e: 681b ldr r3, [r3, #0]
|
|
8003830: 78fa ldrb r2, [r7, #3]
|
|
8003832: 4611 mov r1, r2
|
|
8003834: 4618 mov r0, r3
|
|
8003836: f004 f8f0 bl 8007a1a <USB_HC_Halt>
|
|
|
|
/* reset error_count */
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
800383a: 78fa ldrb r2, [r7, #3]
|
|
800383c: 6879 ldr r1, [r7, #4]
|
|
800383e: 4613 mov r3, r2
|
|
8003840: 011b lsls r3, r3, #4
|
|
8003842: 1a9b subs r3, r3, r2
|
|
8003844: 009b lsls r3, r3, #2
|
|
8003846: 440b add r3, r1
|
|
8003848: 3344 adds r3, #68 @ 0x44
|
|
800384a: 2200 movs r2, #0
|
|
800384c: 601a str r2, [r3, #0]
|
|
800384e: e3f9 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
|
|
8003850: 687b ldr r3, [r7, #4]
|
|
8003852: 681b ldr r3, [r3, #0]
|
|
8003854: 78fa ldrb r2, [r7, #3]
|
|
8003856: 4611 mov r1, r2
|
|
8003858: 4618 mov r0, r3
|
|
800385a: f003 fb34 bl 8006ec6 <USB_ReadChInterrupts>
|
|
800385e: 4603 mov r3, r0
|
|
8003860: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003864: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8003868: d111 bne.n 800388e <HCD_HC_OUT_IRQHandler+0x1c2>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
|
|
800386a: 78fb ldrb r3, [r7, #3]
|
|
800386c: 015a lsls r2, r3, #5
|
|
800386e: 693b ldr r3, [r7, #16]
|
|
8003870: 4413 add r3, r2
|
|
8003872: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003876: 461a mov r2, r3
|
|
8003878: f44f 7300 mov.w r3, #512 @ 0x200
|
|
800387c: 6093 str r3, [r2, #8]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800387e: 687b ldr r3, [r7, #4]
|
|
8003880: 681b ldr r3, [r3, #0]
|
|
8003882: 78fa ldrb r2, [r7, #3]
|
|
8003884: 4611 mov r1, r2
|
|
8003886: 4618 mov r0, r3
|
|
8003888: f004 f8c7 bl 8007a1a <USB_HC_Halt>
|
|
800388c: e3da b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
|
|
800388e: 687b ldr r3, [r7, #4]
|
|
8003890: 681b ldr r3, [r3, #0]
|
|
8003892: 78fa ldrb r2, [r7, #3]
|
|
8003894: 4611 mov r1, r2
|
|
8003896: 4618 mov r0, r3
|
|
8003898: f003 fb15 bl 8006ec6 <USB_ReadChInterrupts>
|
|
800389c: 4603 mov r3, r0
|
|
800389e: f003 0301 and.w r3, r3, #1
|
|
80038a2: 2b01 cmp r3, #1
|
|
80038a4: d168 bne.n 8003978 <HCD_HC_OUT_IRQHandler+0x2ac>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80038a6: 78fa ldrb r2, [r7, #3]
|
|
80038a8: 6879 ldr r1, [r7, #4]
|
|
80038aa: 4613 mov r3, r2
|
|
80038ac: 011b lsls r3, r3, #4
|
|
80038ae: 1a9b subs r3, r3, r2
|
|
80038b0: 009b lsls r3, r3, #2
|
|
80038b2: 440b add r3, r1
|
|
80038b4: 3344 adds r3, #68 @ 0x44
|
|
80038b6: 2200 movs r2, #0
|
|
80038b8: 601a str r2, [r3, #0]
|
|
|
|
/* transaction completed with NYET state, update do ping state */
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
80038ba: 687b ldr r3, [r7, #4]
|
|
80038bc: 681b ldr r3, [r3, #0]
|
|
80038be: 78fa ldrb r2, [r7, #3]
|
|
80038c0: 4611 mov r1, r2
|
|
80038c2: 4618 mov r0, r3
|
|
80038c4: f003 faff bl 8006ec6 <USB_ReadChInterrupts>
|
|
80038c8: 4603 mov r3, r0
|
|
80038ca: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80038ce: 2b40 cmp r3, #64 @ 0x40
|
|
80038d0: d112 bne.n 80038f8 <HCD_HC_OUT_IRQHandler+0x22c>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
80038d2: 78fa ldrb r2, [r7, #3]
|
|
80038d4: 6879 ldr r1, [r7, #4]
|
|
80038d6: 4613 mov r3, r2
|
|
80038d8: 011b lsls r3, r3, #4
|
|
80038da: 1a9b subs r3, r3, r2
|
|
80038dc: 009b lsls r3, r3, #2
|
|
80038de: 440b add r3, r1
|
|
80038e0: 3319 adds r3, #25
|
|
80038e2: 2201 movs r2, #1
|
|
80038e4: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
80038e6: 78fb ldrb r3, [r7, #3]
|
|
80038e8: 015a lsls r2, r3, #5
|
|
80038ea: 693b ldr r3, [r7, #16]
|
|
80038ec: 4413 add r3, r2
|
|
80038ee: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80038f2: 461a mov r2, r3
|
|
80038f4: 2340 movs r3, #64 @ 0x40
|
|
80038f6: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (hhcd->hc[chnum].do_csplit != 0U)
|
|
80038f8: 78fa ldrb r2, [r7, #3]
|
|
80038fa: 6879 ldr r1, [r7, #4]
|
|
80038fc: 4613 mov r3, r2
|
|
80038fe: 011b lsls r3, r3, #4
|
|
8003900: 1a9b subs r3, r3, r2
|
|
8003902: 009b lsls r3, r3, #2
|
|
8003904: 440b add r3, r1
|
|
8003906: 331b adds r3, #27
|
|
8003908: 781b ldrb r3, [r3, #0]
|
|
800390a: 2b00 cmp r3, #0
|
|
800390c: d019 beq.n 8003942 <HCD_HC_OUT_IRQHandler+0x276>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
800390e: 78fa ldrb r2, [r7, #3]
|
|
8003910: 6879 ldr r1, [r7, #4]
|
|
8003912: 4613 mov r3, r2
|
|
8003914: 011b lsls r3, r3, #4
|
|
8003916: 1a9b subs r3, r3, r2
|
|
8003918: 009b lsls r3, r3, #2
|
|
800391a: 440b add r3, r1
|
|
800391c: 331b adds r3, #27
|
|
800391e: 2200 movs r2, #0
|
|
8003920: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8003922: 78fb ldrb r3, [r7, #3]
|
|
8003924: 015a lsls r2, r3, #5
|
|
8003926: 693b ldr r3, [r7, #16]
|
|
8003928: 4413 add r3, r2
|
|
800392a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800392e: 685b ldr r3, [r3, #4]
|
|
8003930: 78fa ldrb r2, [r7, #3]
|
|
8003932: 0151 lsls r1, r2, #5
|
|
8003934: 693a ldr r2, [r7, #16]
|
|
8003936: 440a add r2, r1
|
|
8003938: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800393c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8003940: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
|
|
8003942: 78fb ldrb r3, [r7, #3]
|
|
8003944: 015a lsls r2, r3, #5
|
|
8003946: 693b ldr r3, [r7, #16]
|
|
8003948: 4413 add r3, r2
|
|
800394a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800394e: 461a mov r2, r3
|
|
8003950: 2301 movs r3, #1
|
|
8003952: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XFRC;
|
|
8003954: 78fa ldrb r2, [r7, #3]
|
|
8003956: 6879 ldr r1, [r7, #4]
|
|
8003958: 4613 mov r3, r2
|
|
800395a: 011b lsls r3, r3, #4
|
|
800395c: 1a9b subs r3, r3, r2
|
|
800395e: 009b lsls r3, r3, #2
|
|
8003960: 440b add r3, r1
|
|
8003962: 334d adds r3, #77 @ 0x4d
|
|
8003964: 2201 movs r2, #1
|
|
8003966: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003968: 687b ldr r3, [r7, #4]
|
|
800396a: 681b ldr r3, [r3, #0]
|
|
800396c: 78fa ldrb r2, [r7, #3]
|
|
800396e: 4611 mov r1, r2
|
|
8003970: 4618 mov r0, r3
|
|
8003972: f004 f852 bl 8007a1a <USB_HC_Halt>
|
|
8003976: e365 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
8003978: 687b ldr r3, [r7, #4]
|
|
800397a: 681b ldr r3, [r3, #0]
|
|
800397c: 78fa ldrb r2, [r7, #3]
|
|
800397e: 4611 mov r1, r2
|
|
8003980: 4618 mov r0, r3
|
|
8003982: f003 faa0 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003986: 4603 mov r3, r0
|
|
8003988: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800398c: 2b40 cmp r3, #64 @ 0x40
|
|
800398e: d139 bne.n 8003a04 <HCD_HC_OUT_IRQHandler+0x338>
|
|
{
|
|
hhcd->hc[chnum].state = HC_NYET;
|
|
8003990: 78fa ldrb r2, [r7, #3]
|
|
8003992: 6879 ldr r1, [r7, #4]
|
|
8003994: 4613 mov r3, r2
|
|
8003996: 011b lsls r3, r3, #4
|
|
8003998: 1a9b subs r3, r3, r2
|
|
800399a: 009b lsls r3, r3, #2
|
|
800399c: 440b add r3, r1
|
|
800399e: 334d adds r3, #77 @ 0x4d
|
|
80039a0: 2205 movs r2, #5
|
|
80039a2: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 0U)
|
|
80039a4: 78fa ldrb r2, [r7, #3]
|
|
80039a6: 6879 ldr r1, [r7, #4]
|
|
80039a8: 4613 mov r3, r2
|
|
80039aa: 011b lsls r3, r3, #4
|
|
80039ac: 1a9b subs r3, r3, r2
|
|
80039ae: 009b lsls r3, r3, #2
|
|
80039b0: 440b add r3, r1
|
|
80039b2: 331a adds r3, #26
|
|
80039b4: 781b ldrb r3, [r3, #0]
|
|
80039b6: 2b00 cmp r3, #0
|
|
80039b8: d109 bne.n 80039ce <HCD_HC_OUT_IRQHandler+0x302>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
80039ba: 78fa ldrb r2, [r7, #3]
|
|
80039bc: 6879 ldr r1, [r7, #4]
|
|
80039be: 4613 mov r3, r2
|
|
80039c0: 011b lsls r3, r3, #4
|
|
80039c2: 1a9b subs r3, r3, r2
|
|
80039c4: 009b lsls r3, r3, #2
|
|
80039c6: 440b add r3, r1
|
|
80039c8: 3319 adds r3, #25
|
|
80039ca: 2201 movs r2, #1
|
|
80039cc: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80039ce: 78fa ldrb r2, [r7, #3]
|
|
80039d0: 6879 ldr r1, [r7, #4]
|
|
80039d2: 4613 mov r3, r2
|
|
80039d4: 011b lsls r3, r3, #4
|
|
80039d6: 1a9b subs r3, r3, r2
|
|
80039d8: 009b lsls r3, r3, #2
|
|
80039da: 440b add r3, r1
|
|
80039dc: 3344 adds r3, #68 @ 0x44
|
|
80039de: 2200 movs r2, #0
|
|
80039e0: 601a str r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80039e2: 687b ldr r3, [r7, #4]
|
|
80039e4: 681b ldr r3, [r3, #0]
|
|
80039e6: 78fa ldrb r2, [r7, #3]
|
|
80039e8: 4611 mov r1, r2
|
|
80039ea: 4618 mov r0, r3
|
|
80039ec: f004 f815 bl 8007a1a <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
80039f0: 78fb ldrb r3, [r7, #3]
|
|
80039f2: 015a lsls r2, r3, #5
|
|
80039f4: 693b ldr r3, [r7, #16]
|
|
80039f6: 4413 add r3, r2
|
|
80039f8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80039fc: 461a mov r2, r3
|
|
80039fe: 2340 movs r3, #64 @ 0x40
|
|
8003a00: 6093 str r3, [r2, #8]
|
|
8003a02: e31f b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
|
|
8003a04: 687b ldr r3, [r7, #4]
|
|
8003a06: 681b ldr r3, [r3, #0]
|
|
8003a08: 78fa ldrb r2, [r7, #3]
|
|
8003a0a: 4611 mov r1, r2
|
|
8003a0c: 4618 mov r0, r3
|
|
8003a0e: f003 fa5a bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003a12: 4603 mov r3, r0
|
|
8003a14: f003 0308 and.w r3, r3, #8
|
|
8003a18: 2b08 cmp r3, #8
|
|
8003a1a: d11a bne.n 8003a52 <HCD_HC_OUT_IRQHandler+0x386>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
|
|
8003a1c: 78fb ldrb r3, [r7, #3]
|
|
8003a1e: 015a lsls r2, r3, #5
|
|
8003a20: 693b ldr r3, [r7, #16]
|
|
8003a22: 4413 add r3, r2
|
|
8003a24: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003a28: 461a mov r2, r3
|
|
8003a2a: 2308 movs r3, #8
|
|
8003a2c: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_STALL;
|
|
8003a2e: 78fa ldrb r2, [r7, #3]
|
|
8003a30: 6879 ldr r1, [r7, #4]
|
|
8003a32: 4613 mov r3, r2
|
|
8003a34: 011b lsls r3, r3, #4
|
|
8003a36: 1a9b subs r3, r3, r2
|
|
8003a38: 009b lsls r3, r3, #2
|
|
8003a3a: 440b add r3, r1
|
|
8003a3c: 334d adds r3, #77 @ 0x4d
|
|
8003a3e: 2206 movs r2, #6
|
|
8003a40: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003a42: 687b ldr r3, [r7, #4]
|
|
8003a44: 681b ldr r3, [r3, #0]
|
|
8003a46: 78fa ldrb r2, [r7, #3]
|
|
8003a48: 4611 mov r1, r2
|
|
8003a4a: 4618 mov r0, r3
|
|
8003a4c: f003 ffe5 bl 8007a1a <USB_HC_Halt>
|
|
8003a50: e2f8 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
|
|
8003a52: 687b ldr r3, [r7, #4]
|
|
8003a54: 681b ldr r3, [r3, #0]
|
|
8003a56: 78fa ldrb r2, [r7, #3]
|
|
8003a58: 4611 mov r1, r2
|
|
8003a5a: 4618 mov r0, r3
|
|
8003a5c: f003 fa33 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003a60: 4603 mov r3, r0
|
|
8003a62: f003 0310 and.w r3, r3, #16
|
|
8003a66: 2b10 cmp r3, #16
|
|
8003a68: d144 bne.n 8003af4 <HCD_HC_OUT_IRQHandler+0x428>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8003a6a: 78fa ldrb r2, [r7, #3]
|
|
8003a6c: 6879 ldr r1, [r7, #4]
|
|
8003a6e: 4613 mov r3, r2
|
|
8003a70: 011b lsls r3, r3, #4
|
|
8003a72: 1a9b subs r3, r3, r2
|
|
8003a74: 009b lsls r3, r3, #2
|
|
8003a76: 440b add r3, r1
|
|
8003a78: 3344 adds r3, #68 @ 0x44
|
|
8003a7a: 2200 movs r2, #0
|
|
8003a7c: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
8003a7e: 78fa ldrb r2, [r7, #3]
|
|
8003a80: 6879 ldr r1, [r7, #4]
|
|
8003a82: 4613 mov r3, r2
|
|
8003a84: 011b lsls r3, r3, #4
|
|
8003a86: 1a9b subs r3, r3, r2
|
|
8003a88: 009b lsls r3, r3, #2
|
|
8003a8a: 440b add r3, r1
|
|
8003a8c: 334d adds r3, #77 @ 0x4d
|
|
8003a8e: 2204 movs r2, #4
|
|
8003a90: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ping == 0U)
|
|
8003a92: 78fa ldrb r2, [r7, #3]
|
|
8003a94: 6879 ldr r1, [r7, #4]
|
|
8003a96: 4613 mov r3, r2
|
|
8003a98: 011b lsls r3, r3, #4
|
|
8003a9a: 1a9b subs r3, r3, r2
|
|
8003a9c: 009b lsls r3, r3, #2
|
|
8003a9e: 440b add r3, r1
|
|
8003aa0: 3319 adds r3, #25
|
|
8003aa2: 781b ldrb r3, [r3, #0]
|
|
8003aa4: 2b00 cmp r3, #0
|
|
8003aa6: d114 bne.n 8003ad2 <HCD_HC_OUT_IRQHandler+0x406>
|
|
{
|
|
if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
|
|
8003aa8: 78fa ldrb r2, [r7, #3]
|
|
8003aaa: 6879 ldr r1, [r7, #4]
|
|
8003aac: 4613 mov r3, r2
|
|
8003aae: 011b lsls r3, r3, #4
|
|
8003ab0: 1a9b subs r3, r3, r2
|
|
8003ab2: 009b lsls r3, r3, #2
|
|
8003ab4: 440b add r3, r1
|
|
8003ab6: 3318 adds r3, #24
|
|
8003ab8: 781b ldrb r3, [r3, #0]
|
|
8003aba: 2b00 cmp r3, #0
|
|
8003abc: d109 bne.n 8003ad2 <HCD_HC_OUT_IRQHandler+0x406>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
8003abe: 78fa ldrb r2, [r7, #3]
|
|
8003ac0: 6879 ldr r1, [r7, #4]
|
|
8003ac2: 4613 mov r3, r2
|
|
8003ac4: 011b lsls r3, r3, #4
|
|
8003ac6: 1a9b subs r3, r3, r2
|
|
8003ac8: 009b lsls r3, r3, #2
|
|
8003aca: 440b add r3, r1
|
|
8003acc: 3319 adds r3, #25
|
|
8003ace: 2201 movs r2, #1
|
|
8003ad0: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003ad2: 687b ldr r3, [r7, #4]
|
|
8003ad4: 681b ldr r3, [r3, #0]
|
|
8003ad6: 78fa ldrb r2, [r7, #3]
|
|
8003ad8: 4611 mov r1, r2
|
|
8003ada: 4618 mov r0, r3
|
|
8003adc: f003 ff9d bl 8007a1a <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
8003ae0: 78fb ldrb r3, [r7, #3]
|
|
8003ae2: 015a lsls r2, r3, #5
|
|
8003ae4: 693b ldr r3, [r7, #16]
|
|
8003ae6: 4413 add r3, r2
|
|
8003ae8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003aec: 461a mov r2, r3
|
|
8003aee: 2310 movs r3, #16
|
|
8003af0: 6093 str r3, [r2, #8]
|
|
8003af2: e2a7 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
|
|
8003af4: 687b ldr r3, [r7, #4]
|
|
8003af6: 681b ldr r3, [r3, #0]
|
|
8003af8: 78fa ldrb r2, [r7, #3]
|
|
8003afa: 4611 mov r1, r2
|
|
8003afc: 4618 mov r0, r3
|
|
8003afe: f003 f9e2 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003b02: 4603 mov r3, r0
|
|
8003b04: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003b08: 2b80 cmp r3, #128 @ 0x80
|
|
8003b0a: f040 8083 bne.w 8003c14 <HCD_HC_OUT_IRQHandler+0x548>
|
|
{
|
|
if (hhcd->Init.dma_enable == 0U)
|
|
8003b0e: 687b ldr r3, [r7, #4]
|
|
8003b10: 799b ldrb r3, [r3, #6]
|
|
8003b12: 2b00 cmp r3, #0
|
|
8003b14: d111 bne.n 8003b3a <HCD_HC_OUT_IRQHandler+0x46e>
|
|
{
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8003b16: 78fa ldrb r2, [r7, #3]
|
|
8003b18: 6879 ldr r1, [r7, #4]
|
|
8003b1a: 4613 mov r3, r2
|
|
8003b1c: 011b lsls r3, r3, #4
|
|
8003b1e: 1a9b subs r3, r3, r2
|
|
8003b20: 009b lsls r3, r3, #2
|
|
8003b22: 440b add r3, r1
|
|
8003b24: 334d adds r3, #77 @ 0x4d
|
|
8003b26: 2207 movs r2, #7
|
|
8003b28: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003b2a: 687b ldr r3, [r7, #4]
|
|
8003b2c: 681b ldr r3, [r3, #0]
|
|
8003b2e: 78fa ldrb r2, [r7, #3]
|
|
8003b30: 4611 mov r1, r2
|
|
8003b32: 4618 mov r0, r3
|
|
8003b34: f003 ff71 bl 8007a1a <USB_HC_Halt>
|
|
8003b38: e062 b.n 8003c00 <HCD_HC_OUT_IRQHandler+0x534>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8003b3a: 78fa ldrb r2, [r7, #3]
|
|
8003b3c: 6879 ldr r1, [r7, #4]
|
|
8003b3e: 4613 mov r3, r2
|
|
8003b40: 011b lsls r3, r3, #4
|
|
8003b42: 1a9b subs r3, r3, r2
|
|
8003b44: 009b lsls r3, r3, #2
|
|
8003b46: 440b add r3, r1
|
|
8003b48: 3344 adds r3, #68 @ 0x44
|
|
8003b4a: 681b ldr r3, [r3, #0]
|
|
8003b4c: 1c59 adds r1, r3, #1
|
|
8003b4e: 6878 ldr r0, [r7, #4]
|
|
8003b50: 4613 mov r3, r2
|
|
8003b52: 011b lsls r3, r3, #4
|
|
8003b54: 1a9b subs r3, r3, r2
|
|
8003b56: 009b lsls r3, r3, #2
|
|
8003b58: 4403 add r3, r0
|
|
8003b5a: 3344 adds r3, #68 @ 0x44
|
|
8003b5c: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8003b5e: 78fa ldrb r2, [r7, #3]
|
|
8003b60: 6879 ldr r1, [r7, #4]
|
|
8003b62: 4613 mov r3, r2
|
|
8003b64: 011b lsls r3, r3, #4
|
|
8003b66: 1a9b subs r3, r3, r2
|
|
8003b68: 009b lsls r3, r3, #2
|
|
8003b6a: 440b add r3, r1
|
|
8003b6c: 3344 adds r3, #68 @ 0x44
|
|
8003b6e: 681b ldr r3, [r3, #0]
|
|
8003b70: 2b02 cmp r3, #2
|
|
8003b72: d922 bls.n 8003bba <HCD_HC_OUT_IRQHandler+0x4ee>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8003b74: 78fa ldrb r2, [r7, #3]
|
|
8003b76: 6879 ldr r1, [r7, #4]
|
|
8003b78: 4613 mov r3, r2
|
|
8003b7a: 011b lsls r3, r3, #4
|
|
8003b7c: 1a9b subs r3, r3, r2
|
|
8003b7e: 009b lsls r3, r3, #2
|
|
8003b80: 440b add r3, r1
|
|
8003b82: 3344 adds r3, #68 @ 0x44
|
|
8003b84: 2200 movs r2, #0
|
|
8003b86: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8003b88: 78fa ldrb r2, [r7, #3]
|
|
8003b8a: 6879 ldr r1, [r7, #4]
|
|
8003b8c: 4613 mov r3, r2
|
|
8003b8e: 011b lsls r3, r3, #4
|
|
8003b90: 1a9b subs r3, r3, r2
|
|
8003b92: 009b lsls r3, r3, #2
|
|
8003b94: 440b add r3, r1
|
|
8003b96: 334c adds r3, #76 @ 0x4c
|
|
8003b98: 2204 movs r2, #4
|
|
8003b9a: 701a strb r2, [r3, #0]
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
8003b9c: 78fa ldrb r2, [r7, #3]
|
|
8003b9e: 6879 ldr r1, [r7, #4]
|
|
8003ba0: 4613 mov r3, r2
|
|
8003ba2: 011b lsls r3, r3, #4
|
|
8003ba4: 1a9b subs r3, r3, r2
|
|
8003ba6: 009b lsls r3, r3, #2
|
|
8003ba8: 440b add r3, r1
|
|
8003baa: 334c adds r3, #76 @ 0x4c
|
|
8003bac: 781a ldrb r2, [r3, #0]
|
|
8003bae: 78fb ldrb r3, [r7, #3]
|
|
8003bb0: 4619 mov r1, r3
|
|
8003bb2: 6878 ldr r0, [r7, #4]
|
|
8003bb4: f008 fef2 bl 800c99c <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
8003bb8: e022 b.n 8003c00 <HCD_HC_OUT_IRQHandler+0x534>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003bba: 78fa ldrb r2, [r7, #3]
|
|
8003bbc: 6879 ldr r1, [r7, #4]
|
|
8003bbe: 4613 mov r3, r2
|
|
8003bc0: 011b lsls r3, r3, #4
|
|
8003bc2: 1a9b subs r3, r3, r2
|
|
8003bc4: 009b lsls r3, r3, #2
|
|
8003bc6: 440b add r3, r1
|
|
8003bc8: 334c adds r3, #76 @ 0x4c
|
|
8003bca: 2202 movs r2, #2
|
|
8003bcc: 701a strb r2, [r3, #0]
|
|
|
|
/* Re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8003bce: 78fb ldrb r3, [r7, #3]
|
|
8003bd0: 015a lsls r2, r3, #5
|
|
8003bd2: 693b ldr r3, [r7, #16]
|
|
8003bd4: 4413 add r3, r2
|
|
8003bd6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003bda: 681b ldr r3, [r3, #0]
|
|
8003bdc: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8003bde: 68fb ldr r3, [r7, #12]
|
|
8003be0: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003be4: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8003be6: 68fb ldr r3, [r7, #12]
|
|
8003be8: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003bec: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8003bee: 78fb ldrb r3, [r7, #3]
|
|
8003bf0: 015a lsls r2, r3, #5
|
|
8003bf2: 693b ldr r3, [r7, #16]
|
|
8003bf4: 4413 add r3, r2
|
|
8003bf6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003bfa: 461a mov r2, r3
|
|
8003bfc: 68fb ldr r3, [r7, #12]
|
|
8003bfe: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
|
|
8003c00: 78fb ldrb r3, [r7, #3]
|
|
8003c02: 015a lsls r2, r3, #5
|
|
8003c04: 693b ldr r3, [r7, #16]
|
|
8003c06: 4413 add r3, r2
|
|
8003c08: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003c0c: 461a mov r2, r3
|
|
8003c0e: 2380 movs r3, #128 @ 0x80
|
|
8003c10: 6093 str r3, [r2, #8]
|
|
8003c12: e217 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
|
|
8003c14: 687b ldr r3, [r7, #4]
|
|
8003c16: 681b ldr r3, [r3, #0]
|
|
8003c18: 78fa ldrb r2, [r7, #3]
|
|
8003c1a: 4611 mov r1, r2
|
|
8003c1c: 4618 mov r0, r3
|
|
8003c1e: f003 f952 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003c22: 4603 mov r3, r0
|
|
8003c24: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003c28: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003c2c: d11b bne.n 8003c66 <HCD_HC_OUT_IRQHandler+0x59a>
|
|
{
|
|
hhcd->hc[chnum].state = HC_DATATGLERR;
|
|
8003c2e: 78fa ldrb r2, [r7, #3]
|
|
8003c30: 6879 ldr r1, [r7, #4]
|
|
8003c32: 4613 mov r3, r2
|
|
8003c34: 011b lsls r3, r3, #4
|
|
8003c36: 1a9b subs r3, r3, r2
|
|
8003c38: 009b lsls r3, r3, #2
|
|
8003c3a: 440b add r3, r1
|
|
8003c3c: 334d adds r3, #77 @ 0x4d
|
|
8003c3e: 2209 movs r2, #9
|
|
8003c40: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003c42: 687b ldr r3, [r7, #4]
|
|
8003c44: 681b ldr r3, [r3, #0]
|
|
8003c46: 78fa ldrb r2, [r7, #3]
|
|
8003c48: 4611 mov r1, r2
|
|
8003c4a: 4618 mov r0, r3
|
|
8003c4c: f003 fee5 bl 8007a1a <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
|
|
8003c50: 78fb ldrb r3, [r7, #3]
|
|
8003c52: 015a lsls r2, r3, #5
|
|
8003c54: 693b ldr r3, [r7, #16]
|
|
8003c56: 4413 add r3, r2
|
|
8003c58: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003c5c: 461a mov r2, r3
|
|
8003c5e: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8003c62: 6093 str r3, [r2, #8]
|
|
8003c64: e1ee b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
|
|
8003c66: 687b ldr r3, [r7, #4]
|
|
8003c68: 681b ldr r3, [r3, #0]
|
|
8003c6a: 78fa ldrb r2, [r7, #3]
|
|
8003c6c: 4611 mov r1, r2
|
|
8003c6e: 4618 mov r0, r3
|
|
8003c70: f003 f929 bl 8006ec6 <USB_ReadChInterrupts>
|
|
8003c74: 4603 mov r3, r0
|
|
8003c76: f003 0302 and.w r3, r3, #2
|
|
8003c7a: 2b02 cmp r3, #2
|
|
8003c7c: f040 81df bne.w 800403e <HCD_HC_OUT_IRQHandler+0x972>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
|
|
8003c80: 78fb ldrb r3, [r7, #3]
|
|
8003c82: 015a lsls r2, r3, #5
|
|
8003c84: 693b ldr r3, [r7, #16]
|
|
8003c86: 4413 add r3, r2
|
|
8003c88: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003c8c: 461a mov r2, r3
|
|
8003c8e: 2302 movs r3, #2
|
|
8003c90: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].state == HC_XFRC)
|
|
8003c92: 78fa ldrb r2, [r7, #3]
|
|
8003c94: 6879 ldr r1, [r7, #4]
|
|
8003c96: 4613 mov r3, r2
|
|
8003c98: 011b lsls r3, r3, #4
|
|
8003c9a: 1a9b subs r3, r3, r2
|
|
8003c9c: 009b lsls r3, r3, #2
|
|
8003c9e: 440b add r3, r1
|
|
8003ca0: 334d adds r3, #77 @ 0x4d
|
|
8003ca2: 781b ldrb r3, [r3, #0]
|
|
8003ca4: 2b01 cmp r3, #1
|
|
8003ca6: f040 8093 bne.w 8003dd0 <HCD_HC_OUT_IRQHandler+0x704>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003caa: 78fa ldrb r2, [r7, #3]
|
|
8003cac: 6879 ldr r1, [r7, #4]
|
|
8003cae: 4613 mov r3, r2
|
|
8003cb0: 011b lsls r3, r3, #4
|
|
8003cb2: 1a9b subs r3, r3, r2
|
|
8003cb4: 009b lsls r3, r3, #2
|
|
8003cb6: 440b add r3, r1
|
|
8003cb8: 334d adds r3, #77 @ 0x4d
|
|
8003cba: 2202 movs r2, #2
|
|
8003cbc: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
8003cbe: 78fa ldrb r2, [r7, #3]
|
|
8003cc0: 6879 ldr r1, [r7, #4]
|
|
8003cc2: 4613 mov r3, r2
|
|
8003cc4: 011b lsls r3, r3, #4
|
|
8003cc6: 1a9b subs r3, r3, r2
|
|
8003cc8: 009b lsls r3, r3, #2
|
|
8003cca: 440b add r3, r1
|
|
8003ccc: 334c adds r3, #76 @ 0x4c
|
|
8003cce: 2201 movs r2, #1
|
|
8003cd0: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
|
|
8003cd2: 78fa ldrb r2, [r7, #3]
|
|
8003cd4: 6879 ldr r1, [r7, #4]
|
|
8003cd6: 4613 mov r3, r2
|
|
8003cd8: 011b lsls r3, r3, #4
|
|
8003cda: 1a9b subs r3, r3, r2
|
|
8003cdc: 009b lsls r3, r3, #2
|
|
8003cde: 440b add r3, r1
|
|
8003ce0: 3326 adds r3, #38 @ 0x26
|
|
8003ce2: 781b ldrb r3, [r3, #0]
|
|
8003ce4: 2b02 cmp r3, #2
|
|
8003ce6: d00b beq.n 8003d00 <HCD_HC_OUT_IRQHandler+0x634>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
|
|
8003ce8: 78fa ldrb r2, [r7, #3]
|
|
8003cea: 6879 ldr r1, [r7, #4]
|
|
8003cec: 4613 mov r3, r2
|
|
8003cee: 011b lsls r3, r3, #4
|
|
8003cf0: 1a9b subs r3, r3, r2
|
|
8003cf2: 009b lsls r3, r3, #2
|
|
8003cf4: 440b add r3, r1
|
|
8003cf6: 3326 adds r3, #38 @ 0x26
|
|
8003cf8: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
|
|
8003cfa: 2b03 cmp r3, #3
|
|
8003cfc: f040 8190 bne.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
if (hhcd->Init.dma_enable == 0U)
|
|
8003d00: 687b ldr r3, [r7, #4]
|
|
8003d02: 799b ldrb r3, [r3, #6]
|
|
8003d04: 2b00 cmp r3, #0
|
|
8003d06: d115 bne.n 8003d34 <HCD_HC_OUT_IRQHandler+0x668>
|
|
{
|
|
hhcd->hc[chnum].toggle_out ^= 1U;
|
|
8003d08: 78fa ldrb r2, [r7, #3]
|
|
8003d0a: 6879 ldr r1, [r7, #4]
|
|
8003d0c: 4613 mov r3, r2
|
|
8003d0e: 011b lsls r3, r3, #4
|
|
8003d10: 1a9b subs r3, r3, r2
|
|
8003d12: 009b lsls r3, r3, #2
|
|
8003d14: 440b add r3, r1
|
|
8003d16: 333d adds r3, #61 @ 0x3d
|
|
8003d18: 781b ldrb r3, [r3, #0]
|
|
8003d1a: 78fa ldrb r2, [r7, #3]
|
|
8003d1c: f083 0301 eor.w r3, r3, #1
|
|
8003d20: b2d8 uxtb r0, r3
|
|
8003d22: 6879 ldr r1, [r7, #4]
|
|
8003d24: 4613 mov r3, r2
|
|
8003d26: 011b lsls r3, r3, #4
|
|
8003d28: 1a9b subs r3, r3, r2
|
|
8003d2a: 009b lsls r3, r3, #2
|
|
8003d2c: 440b add r3, r1
|
|
8003d2e: 333d adds r3, #61 @ 0x3d
|
|
8003d30: 4602 mov r2, r0
|
|
8003d32: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
|
|
8003d34: 687b ldr r3, [r7, #4]
|
|
8003d36: 799b ldrb r3, [r3, #6]
|
|
8003d38: 2b01 cmp r3, #1
|
|
8003d3a: f040 8171 bne.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
8003d3e: 78fa ldrb r2, [r7, #3]
|
|
8003d40: 6879 ldr r1, [r7, #4]
|
|
8003d42: 4613 mov r3, r2
|
|
8003d44: 011b lsls r3, r3, #4
|
|
8003d46: 1a9b subs r3, r3, r2
|
|
8003d48: 009b lsls r3, r3, #2
|
|
8003d4a: 440b add r3, r1
|
|
8003d4c: 3334 adds r3, #52 @ 0x34
|
|
8003d4e: 681b ldr r3, [r3, #0]
|
|
8003d50: 2b00 cmp r3, #0
|
|
8003d52: f000 8165 beq.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
|
|
8003d56: 78fa ldrb r2, [r7, #3]
|
|
8003d58: 6879 ldr r1, [r7, #4]
|
|
8003d5a: 4613 mov r3, r2
|
|
8003d5c: 011b lsls r3, r3, #4
|
|
8003d5e: 1a9b subs r3, r3, r2
|
|
8003d60: 009b lsls r3, r3, #2
|
|
8003d62: 440b add r3, r1
|
|
8003d64: 3334 adds r3, #52 @ 0x34
|
|
8003d66: 6819 ldr r1, [r3, #0]
|
|
8003d68: 78fa ldrb r2, [r7, #3]
|
|
8003d6a: 6878 ldr r0, [r7, #4]
|
|
8003d6c: 4613 mov r3, r2
|
|
8003d6e: 011b lsls r3, r3, #4
|
|
8003d70: 1a9b subs r3, r3, r2
|
|
8003d72: 009b lsls r3, r3, #2
|
|
8003d74: 4403 add r3, r0
|
|
8003d76: 3328 adds r3, #40 @ 0x28
|
|
8003d78: 881b ldrh r3, [r3, #0]
|
|
8003d7a: 440b add r3, r1
|
|
8003d7c: 1e59 subs r1, r3, #1
|
|
8003d7e: 78fa ldrb r2, [r7, #3]
|
|
8003d80: 6878 ldr r0, [r7, #4]
|
|
8003d82: 4613 mov r3, r2
|
|
8003d84: 011b lsls r3, r3, #4
|
|
8003d86: 1a9b subs r3, r3, r2
|
|
8003d88: 009b lsls r3, r3, #2
|
|
8003d8a: 4403 add r3, r0
|
|
8003d8c: 3328 adds r3, #40 @ 0x28
|
|
8003d8e: 881b ldrh r3, [r3, #0]
|
|
8003d90: fbb1 f3f3 udiv r3, r1, r3
|
|
8003d94: 60bb str r3, [r7, #8]
|
|
|
|
if ((num_packets & 1U) != 0U)
|
|
8003d96: 68bb ldr r3, [r7, #8]
|
|
8003d98: f003 0301 and.w r3, r3, #1
|
|
8003d9c: 2b00 cmp r3, #0
|
|
8003d9e: f000 813f beq.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].toggle_out ^= 1U;
|
|
8003da2: 78fa ldrb r2, [r7, #3]
|
|
8003da4: 6879 ldr r1, [r7, #4]
|
|
8003da6: 4613 mov r3, r2
|
|
8003da8: 011b lsls r3, r3, #4
|
|
8003daa: 1a9b subs r3, r3, r2
|
|
8003dac: 009b lsls r3, r3, #2
|
|
8003dae: 440b add r3, r1
|
|
8003db0: 333d adds r3, #61 @ 0x3d
|
|
8003db2: 781b ldrb r3, [r3, #0]
|
|
8003db4: 78fa ldrb r2, [r7, #3]
|
|
8003db6: f083 0301 eor.w r3, r3, #1
|
|
8003dba: b2d8 uxtb r0, r3
|
|
8003dbc: 6879 ldr r1, [r7, #4]
|
|
8003dbe: 4613 mov r3, r2
|
|
8003dc0: 011b lsls r3, r3, #4
|
|
8003dc2: 1a9b subs r3, r3, r2
|
|
8003dc4: 009b lsls r3, r3, #2
|
|
8003dc6: 440b add r3, r1
|
|
8003dc8: 333d adds r3, #61 @ 0x3d
|
|
8003dca: 4602 mov r2, r0
|
|
8003dcc: 701a strb r2, [r3, #0]
|
|
8003dce: e127 b.n 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_ACK)
|
|
8003dd0: 78fa ldrb r2, [r7, #3]
|
|
8003dd2: 6879 ldr r1, [r7, #4]
|
|
8003dd4: 4613 mov r3, r2
|
|
8003dd6: 011b lsls r3, r3, #4
|
|
8003dd8: 1a9b subs r3, r3, r2
|
|
8003dda: 009b lsls r3, r3, #2
|
|
8003ddc: 440b add r3, r1
|
|
8003dde: 334d adds r3, #77 @ 0x4d
|
|
8003de0: 781b ldrb r3, [r3, #0]
|
|
8003de2: 2b03 cmp r3, #3
|
|
8003de4: d120 bne.n 8003e28 <HCD_HC_OUT_IRQHandler+0x75c>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003de6: 78fa ldrb r2, [r7, #3]
|
|
8003de8: 6879 ldr r1, [r7, #4]
|
|
8003dea: 4613 mov r3, r2
|
|
8003dec: 011b lsls r3, r3, #4
|
|
8003dee: 1a9b subs r3, r3, r2
|
|
8003df0: 009b lsls r3, r3, #2
|
|
8003df2: 440b add r3, r1
|
|
8003df4: 334d adds r3, #77 @ 0x4d
|
|
8003df6: 2202 movs r2, #2
|
|
8003df8: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003dfa: 78fa ldrb r2, [r7, #3]
|
|
8003dfc: 6879 ldr r1, [r7, #4]
|
|
8003dfe: 4613 mov r3, r2
|
|
8003e00: 011b lsls r3, r3, #4
|
|
8003e02: 1a9b subs r3, r3, r2
|
|
8003e04: 009b lsls r3, r3, #2
|
|
8003e06: 440b add r3, r1
|
|
8003e08: 331b adds r3, #27
|
|
8003e0a: 781b ldrb r3, [r3, #0]
|
|
8003e0c: 2b01 cmp r3, #1
|
|
8003e0e: f040 8107 bne.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003e12: 78fa ldrb r2, [r7, #3]
|
|
8003e14: 6879 ldr r1, [r7, #4]
|
|
8003e16: 4613 mov r3, r2
|
|
8003e18: 011b lsls r3, r3, #4
|
|
8003e1a: 1a9b subs r3, r3, r2
|
|
8003e1c: 009b lsls r3, r3, #2
|
|
8003e1e: 440b add r3, r1
|
|
8003e20: 334c adds r3, #76 @ 0x4c
|
|
8003e22: 2202 movs r2, #2
|
|
8003e24: 701a strb r2, [r3, #0]
|
|
8003e26: e0fb b.n 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NAK)
|
|
8003e28: 78fa ldrb r2, [r7, #3]
|
|
8003e2a: 6879 ldr r1, [r7, #4]
|
|
8003e2c: 4613 mov r3, r2
|
|
8003e2e: 011b lsls r3, r3, #4
|
|
8003e30: 1a9b subs r3, r3, r2
|
|
8003e32: 009b lsls r3, r3, #2
|
|
8003e34: 440b add r3, r1
|
|
8003e36: 334d adds r3, #77 @ 0x4d
|
|
8003e38: 781b ldrb r3, [r3, #0]
|
|
8003e3a: 2b04 cmp r3, #4
|
|
8003e3c: d13a bne.n 8003eb4 <HCD_HC_OUT_IRQHandler+0x7e8>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003e3e: 78fa ldrb r2, [r7, #3]
|
|
8003e40: 6879 ldr r1, [r7, #4]
|
|
8003e42: 4613 mov r3, r2
|
|
8003e44: 011b lsls r3, r3, #4
|
|
8003e46: 1a9b subs r3, r3, r2
|
|
8003e48: 009b lsls r3, r3, #2
|
|
8003e4a: 440b add r3, r1
|
|
8003e4c: 334d adds r3, #77 @ 0x4d
|
|
8003e4e: 2202 movs r2, #2
|
|
8003e50: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003e52: 78fa ldrb r2, [r7, #3]
|
|
8003e54: 6879 ldr r1, [r7, #4]
|
|
8003e56: 4613 mov r3, r2
|
|
8003e58: 011b lsls r3, r3, #4
|
|
8003e5a: 1a9b subs r3, r3, r2
|
|
8003e5c: 009b lsls r3, r3, #2
|
|
8003e5e: 440b add r3, r1
|
|
8003e60: 334c adds r3, #76 @ 0x4c
|
|
8003e62: 2202 movs r2, #2
|
|
8003e64: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003e66: 78fa ldrb r2, [r7, #3]
|
|
8003e68: 6879 ldr r1, [r7, #4]
|
|
8003e6a: 4613 mov r3, r2
|
|
8003e6c: 011b lsls r3, r3, #4
|
|
8003e6e: 1a9b subs r3, r3, r2
|
|
8003e70: 009b lsls r3, r3, #2
|
|
8003e72: 440b add r3, r1
|
|
8003e74: 331b adds r3, #27
|
|
8003e76: 781b ldrb r3, [r3, #0]
|
|
8003e78: 2b01 cmp r3, #1
|
|
8003e7a: f040 80d1 bne.w 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8003e7e: 78fa ldrb r2, [r7, #3]
|
|
8003e80: 6879 ldr r1, [r7, #4]
|
|
8003e82: 4613 mov r3, r2
|
|
8003e84: 011b lsls r3, r3, #4
|
|
8003e86: 1a9b subs r3, r3, r2
|
|
8003e88: 009b lsls r3, r3, #2
|
|
8003e8a: 440b add r3, r1
|
|
8003e8c: 331b adds r3, #27
|
|
8003e8e: 2200 movs r2, #0
|
|
8003e90: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8003e92: 78fb ldrb r3, [r7, #3]
|
|
8003e94: 015a lsls r2, r3, #5
|
|
8003e96: 693b ldr r3, [r7, #16]
|
|
8003e98: 4413 add r3, r2
|
|
8003e9a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003e9e: 685b ldr r3, [r3, #4]
|
|
8003ea0: 78fa ldrb r2, [r7, #3]
|
|
8003ea2: 0151 lsls r1, r2, #5
|
|
8003ea4: 693a ldr r2, [r7, #16]
|
|
8003ea6: 440a add r2, r1
|
|
8003ea8: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8003eac: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8003eb0: 6053 str r3, [r2, #4]
|
|
8003eb2: e0b5 b.n 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NYET)
|
|
8003eb4: 78fa ldrb r2, [r7, #3]
|
|
8003eb6: 6879 ldr r1, [r7, #4]
|
|
8003eb8: 4613 mov r3, r2
|
|
8003eba: 011b lsls r3, r3, #4
|
|
8003ebc: 1a9b subs r3, r3, r2
|
|
8003ebe: 009b lsls r3, r3, #2
|
|
8003ec0: 440b add r3, r1
|
|
8003ec2: 334d adds r3, #77 @ 0x4d
|
|
8003ec4: 781b ldrb r3, [r3, #0]
|
|
8003ec6: 2b05 cmp r3, #5
|
|
8003ec8: d114 bne.n 8003ef4 <HCD_HC_OUT_IRQHandler+0x828>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003eca: 78fa ldrb r2, [r7, #3]
|
|
8003ecc: 6879 ldr r1, [r7, #4]
|
|
8003ece: 4613 mov r3, r2
|
|
8003ed0: 011b lsls r3, r3, #4
|
|
8003ed2: 1a9b subs r3, r3, r2
|
|
8003ed4: 009b lsls r3, r3, #2
|
|
8003ed6: 440b add r3, r1
|
|
8003ed8: 334d adds r3, #77 @ 0x4d
|
|
8003eda: 2202 movs r2, #2
|
|
8003edc: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003ede: 78fa ldrb r2, [r7, #3]
|
|
8003ee0: 6879 ldr r1, [r7, #4]
|
|
8003ee2: 4613 mov r3, r2
|
|
8003ee4: 011b lsls r3, r3, #4
|
|
8003ee6: 1a9b subs r3, r3, r2
|
|
8003ee8: 009b lsls r3, r3, #2
|
|
8003eea: 440b add r3, r1
|
|
8003eec: 334c adds r3, #76 @ 0x4c
|
|
8003eee: 2202 movs r2, #2
|
|
8003ef0: 701a strb r2, [r3, #0]
|
|
8003ef2: e095 b.n 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_STALL)
|
|
8003ef4: 78fa ldrb r2, [r7, #3]
|
|
8003ef6: 6879 ldr r1, [r7, #4]
|
|
8003ef8: 4613 mov r3, r2
|
|
8003efa: 011b lsls r3, r3, #4
|
|
8003efc: 1a9b subs r3, r3, r2
|
|
8003efe: 009b lsls r3, r3, #2
|
|
8003f00: 440b add r3, r1
|
|
8003f02: 334d adds r3, #77 @ 0x4d
|
|
8003f04: 781b ldrb r3, [r3, #0]
|
|
8003f06: 2b06 cmp r3, #6
|
|
8003f08: d114 bne.n 8003f34 <HCD_HC_OUT_IRQHandler+0x868>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003f0a: 78fa ldrb r2, [r7, #3]
|
|
8003f0c: 6879 ldr r1, [r7, #4]
|
|
8003f0e: 4613 mov r3, r2
|
|
8003f10: 011b lsls r3, r3, #4
|
|
8003f12: 1a9b subs r3, r3, r2
|
|
8003f14: 009b lsls r3, r3, #2
|
|
8003f16: 440b add r3, r1
|
|
8003f18: 334d adds r3, #77 @ 0x4d
|
|
8003f1a: 2202 movs r2, #2
|
|
8003f1c: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_STALL;
|
|
8003f1e: 78fa ldrb r2, [r7, #3]
|
|
8003f20: 6879 ldr r1, [r7, #4]
|
|
8003f22: 4613 mov r3, r2
|
|
8003f24: 011b lsls r3, r3, #4
|
|
8003f26: 1a9b subs r3, r3, r2
|
|
8003f28: 009b lsls r3, r3, #2
|
|
8003f2a: 440b add r3, r1
|
|
8003f2c: 334c adds r3, #76 @ 0x4c
|
|
8003f2e: 2205 movs r2, #5
|
|
8003f30: 701a strb r2, [r3, #0]
|
|
8003f32: e075 b.n 8004020 <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
8003f34: 78fa ldrb r2, [r7, #3]
|
|
8003f36: 6879 ldr r1, [r7, #4]
|
|
8003f38: 4613 mov r3, r2
|
|
8003f3a: 011b lsls r3, r3, #4
|
|
8003f3c: 1a9b subs r3, r3, r2
|
|
8003f3e: 009b lsls r3, r3, #2
|
|
8003f40: 440b add r3, r1
|
|
8003f42: 334d adds r3, #77 @ 0x4d
|
|
8003f44: 781b ldrb r3, [r3, #0]
|
|
8003f46: 2b07 cmp r3, #7
|
|
8003f48: d00a beq.n 8003f60 <HCD_HC_OUT_IRQHandler+0x894>
|
|
(hhcd->hc[chnum].state == HC_DATATGLERR))
|
|
8003f4a: 78fa ldrb r2, [r7, #3]
|
|
8003f4c: 6879 ldr r1, [r7, #4]
|
|
8003f4e: 4613 mov r3, r2
|
|
8003f50: 011b lsls r3, r3, #4
|
|
8003f52: 1a9b subs r3, r3, r2
|
|
8003f54: 009b lsls r3, r3, #2
|
|
8003f56: 440b add r3, r1
|
|
8003f58: 334d adds r3, #77 @ 0x4d
|
|
8003f5a: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
8003f5c: 2b09 cmp r3, #9
|
|
8003f5e: d170 bne.n 8004042 <HCD_HC_OUT_IRQHandler+0x976>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003f60: 78fa ldrb r2, [r7, #3]
|
|
8003f62: 6879 ldr r1, [r7, #4]
|
|
8003f64: 4613 mov r3, r2
|
|
8003f66: 011b lsls r3, r3, #4
|
|
8003f68: 1a9b subs r3, r3, r2
|
|
8003f6a: 009b lsls r3, r3, #2
|
|
8003f6c: 440b add r3, r1
|
|
8003f6e: 334d adds r3, #77 @ 0x4d
|
|
8003f70: 2202 movs r2, #2
|
|
8003f72: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8003f74: 78fa ldrb r2, [r7, #3]
|
|
8003f76: 6879 ldr r1, [r7, #4]
|
|
8003f78: 4613 mov r3, r2
|
|
8003f7a: 011b lsls r3, r3, #4
|
|
8003f7c: 1a9b subs r3, r3, r2
|
|
8003f7e: 009b lsls r3, r3, #2
|
|
8003f80: 440b add r3, r1
|
|
8003f82: 3344 adds r3, #68 @ 0x44
|
|
8003f84: 681b ldr r3, [r3, #0]
|
|
8003f86: 1c59 adds r1, r3, #1
|
|
8003f88: 6878 ldr r0, [r7, #4]
|
|
8003f8a: 4613 mov r3, r2
|
|
8003f8c: 011b lsls r3, r3, #4
|
|
8003f8e: 1a9b subs r3, r3, r2
|
|
8003f90: 009b lsls r3, r3, #2
|
|
8003f92: 4403 add r3, r0
|
|
8003f94: 3344 adds r3, #68 @ 0x44
|
|
8003f96: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8003f98: 78fa ldrb r2, [r7, #3]
|
|
8003f9a: 6879 ldr r1, [r7, #4]
|
|
8003f9c: 4613 mov r3, r2
|
|
8003f9e: 011b lsls r3, r3, #4
|
|
8003fa0: 1a9b subs r3, r3, r2
|
|
8003fa2: 009b lsls r3, r3, #2
|
|
8003fa4: 440b add r3, r1
|
|
8003fa6: 3344 adds r3, #68 @ 0x44
|
|
8003fa8: 681b ldr r3, [r3, #0]
|
|
8003faa: 2b02 cmp r3, #2
|
|
8003fac: d914 bls.n 8003fd8 <HCD_HC_OUT_IRQHandler+0x90c>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8003fae: 78fa ldrb r2, [r7, #3]
|
|
8003fb0: 6879 ldr r1, [r7, #4]
|
|
8003fb2: 4613 mov r3, r2
|
|
8003fb4: 011b lsls r3, r3, #4
|
|
8003fb6: 1a9b subs r3, r3, r2
|
|
8003fb8: 009b lsls r3, r3, #2
|
|
8003fba: 440b add r3, r1
|
|
8003fbc: 3344 adds r3, #68 @ 0x44
|
|
8003fbe: 2200 movs r2, #0
|
|
8003fc0: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8003fc2: 78fa ldrb r2, [r7, #3]
|
|
8003fc4: 6879 ldr r1, [r7, #4]
|
|
8003fc6: 4613 mov r3, r2
|
|
8003fc8: 011b lsls r3, r3, #4
|
|
8003fca: 1a9b subs r3, r3, r2
|
|
8003fcc: 009b lsls r3, r3, #2
|
|
8003fce: 440b add r3, r1
|
|
8003fd0: 334c adds r3, #76 @ 0x4c
|
|
8003fd2: 2204 movs r2, #4
|
|
8003fd4: 701a strb r2, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8003fd6: e022 b.n 800401e <HCD_HC_OUT_IRQHandler+0x952>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003fd8: 78fa ldrb r2, [r7, #3]
|
|
8003fda: 6879 ldr r1, [r7, #4]
|
|
8003fdc: 4613 mov r3, r2
|
|
8003fde: 011b lsls r3, r3, #4
|
|
8003fe0: 1a9b subs r3, r3, r2
|
|
8003fe2: 009b lsls r3, r3, #2
|
|
8003fe4: 440b add r3, r1
|
|
8003fe6: 334c adds r3, #76 @ 0x4c
|
|
8003fe8: 2202 movs r2, #2
|
|
8003fea: 701a strb r2, [r3, #0]
|
|
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8003fec: 78fb ldrb r3, [r7, #3]
|
|
8003fee: 015a lsls r2, r3, #5
|
|
8003ff0: 693b ldr r3, [r7, #16]
|
|
8003ff2: 4413 add r3, r2
|
|
8003ff4: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003ff8: 681b ldr r3, [r3, #0]
|
|
8003ffa: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8003ffc: 68fb ldr r3, [r7, #12]
|
|
8003ffe: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8004002: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8004004: 68fb ldr r3, [r7, #12]
|
|
8004006: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800400a: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
800400c: 78fb ldrb r3, [r7, #3]
|
|
800400e: 015a lsls r2, r3, #5
|
|
8004010: 693b ldr r3, [r7, #16]
|
|
8004012: 4413 add r3, r2
|
|
8004014: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8004018: 461a mov r2, r3
|
|
800401a: 68fb ldr r3, [r7, #12]
|
|
800401c: 6013 str r3, [r2, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
800401e: bf00 nop
|
|
}
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
8004020: 78fa ldrb r2, [r7, #3]
|
|
8004022: 6879 ldr r1, [r7, #4]
|
|
8004024: 4613 mov r3, r2
|
|
8004026: 011b lsls r3, r3, #4
|
|
8004028: 1a9b subs r3, r3, r2
|
|
800402a: 009b lsls r3, r3, #2
|
|
800402c: 440b add r3, r1
|
|
800402e: 334c adds r3, #76 @ 0x4c
|
|
8004030: 781a ldrb r2, [r3, #0]
|
|
8004032: 78fb ldrb r3, [r7, #3]
|
|
8004034: 4619 mov r1, r3
|
|
8004036: 6878 ldr r0, [r7, #4]
|
|
8004038: f008 fcb0 bl 800c99c <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
800403c: e002 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
return;
|
|
800403e: bf00 nop
|
|
8004040: e000 b.n 8004044 <HCD_HC_OUT_IRQHandler+0x978>
|
|
return;
|
|
8004042: bf00 nop
|
|
}
|
|
}
|
|
8004044: 3718 adds r7, #24
|
|
8004046: 46bd mov sp, r7
|
|
8004048: bd80 pop {r7, pc}
|
|
|
|
0800404a <HCD_RXQLVL_IRQHandler>:
|
|
* @brief Handle Rx Queue Level interrupt requests.
|
|
* @param hhcd HCD handle
|
|
* @retval none
|
|
*/
|
|
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800404a: b580 push {r7, lr}
|
|
800404c: b08a sub sp, #40 @ 0x28
|
|
800404e: af00 add r7, sp, #0
|
|
8004050: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8004052: 687b ldr r3, [r7, #4]
|
|
8004054: 681b ldr r3, [r3, #0]
|
|
8004056: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8004058: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800405a: 623b str r3, [r7, #32]
|
|
uint32_t GrxstspReg;
|
|
uint32_t xferSizePktCnt;
|
|
uint32_t tmpreg;
|
|
uint32_t chnum;
|
|
|
|
GrxstspReg = hhcd->Instance->GRXSTSP;
|
|
800405c: 687b ldr r3, [r7, #4]
|
|
800405e: 681b ldr r3, [r3, #0]
|
|
8004060: 6a1b ldr r3, [r3, #32]
|
|
8004062: 61fb str r3, [r7, #28]
|
|
chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
|
|
8004064: 69fb ldr r3, [r7, #28]
|
|
8004066: f003 030f and.w r3, r3, #15
|
|
800406a: 61bb str r3, [r7, #24]
|
|
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
|
800406c: 69fb ldr r3, [r7, #28]
|
|
800406e: 0c5b lsrs r3, r3, #17
|
|
8004070: f003 030f and.w r3, r3, #15
|
|
8004074: 617b str r3, [r7, #20]
|
|
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
8004076: 69fb ldr r3, [r7, #28]
|
|
8004078: 091b lsrs r3, r3, #4
|
|
800407a: f3c3 030a ubfx r3, r3, #0, #11
|
|
800407e: 613b str r3, [r7, #16]
|
|
|
|
switch (pktsts)
|
|
8004080: 697b ldr r3, [r7, #20]
|
|
8004082: 2b02 cmp r3, #2
|
|
8004084: d004 beq.n 8004090 <HCD_RXQLVL_IRQHandler+0x46>
|
|
8004086: 697b ldr r3, [r7, #20]
|
|
8004088: 2b05 cmp r3, #5
|
|
800408a: f000 80b6 beq.w 80041fa <HCD_RXQLVL_IRQHandler+0x1b0>
|
|
break;
|
|
|
|
case GRXSTS_PKTSTS_IN_XFER_COMP:
|
|
case GRXSTS_PKTSTS_CH_HALTED:
|
|
default:
|
|
break;
|
|
800408e: e0b7 b.n 8004200 <HCD_RXQLVL_IRQHandler+0x1b6>
|
|
if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
|
|
8004090: 693b ldr r3, [r7, #16]
|
|
8004092: 2b00 cmp r3, #0
|
|
8004094: f000 80b3 beq.w 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
8004098: 6879 ldr r1, [r7, #4]
|
|
800409a: 69ba ldr r2, [r7, #24]
|
|
800409c: 4613 mov r3, r2
|
|
800409e: 011b lsls r3, r3, #4
|
|
80040a0: 1a9b subs r3, r3, r2
|
|
80040a2: 009b lsls r3, r3, #2
|
|
80040a4: 440b add r3, r1
|
|
80040a6: 332c adds r3, #44 @ 0x2c
|
|
80040a8: 681b ldr r3, [r3, #0]
|
|
80040aa: 2b00 cmp r3, #0
|
|
80040ac: f000 80a7 beq.w 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
|
|
80040b0: 6879 ldr r1, [r7, #4]
|
|
80040b2: 69ba ldr r2, [r7, #24]
|
|
80040b4: 4613 mov r3, r2
|
|
80040b6: 011b lsls r3, r3, #4
|
|
80040b8: 1a9b subs r3, r3, r2
|
|
80040ba: 009b lsls r3, r3, #2
|
|
80040bc: 440b add r3, r1
|
|
80040be: 3338 adds r3, #56 @ 0x38
|
|
80040c0: 681a ldr r2, [r3, #0]
|
|
80040c2: 693b ldr r3, [r7, #16]
|
|
80040c4: 18d1 adds r1, r2, r3
|
|
80040c6: 6878 ldr r0, [r7, #4]
|
|
80040c8: 69ba ldr r2, [r7, #24]
|
|
80040ca: 4613 mov r3, r2
|
|
80040cc: 011b lsls r3, r3, #4
|
|
80040ce: 1a9b subs r3, r3, r2
|
|
80040d0: 009b lsls r3, r3, #2
|
|
80040d2: 4403 add r3, r0
|
|
80040d4: 3334 adds r3, #52 @ 0x34
|
|
80040d6: 681b ldr r3, [r3, #0]
|
|
80040d8: 4299 cmp r1, r3
|
|
80040da: f200 8083 bhi.w 80041e4 <HCD_RXQLVL_IRQHandler+0x19a>
|
|
(void)USB_ReadPacket(hhcd->Instance,
|
|
80040de: 687b ldr r3, [r7, #4]
|
|
80040e0: 6818 ldr r0, [r3, #0]
|
|
80040e2: 6879 ldr r1, [r7, #4]
|
|
80040e4: 69ba ldr r2, [r7, #24]
|
|
80040e6: 4613 mov r3, r2
|
|
80040e8: 011b lsls r3, r3, #4
|
|
80040ea: 1a9b subs r3, r3, r2
|
|
80040ec: 009b lsls r3, r3, #2
|
|
80040ee: 440b add r3, r1
|
|
80040f0: 332c adds r3, #44 @ 0x2c
|
|
80040f2: 681b ldr r3, [r3, #0]
|
|
80040f4: 693a ldr r2, [r7, #16]
|
|
80040f6: b292 uxth r2, r2
|
|
80040f8: 4619 mov r1, r3
|
|
80040fa: f002 fe79 bl 8006df0 <USB_ReadPacket>
|
|
hhcd->hc[chnum].xfer_buff += pktcnt;
|
|
80040fe: 6879 ldr r1, [r7, #4]
|
|
8004100: 69ba ldr r2, [r7, #24]
|
|
8004102: 4613 mov r3, r2
|
|
8004104: 011b lsls r3, r3, #4
|
|
8004106: 1a9b subs r3, r3, r2
|
|
8004108: 009b lsls r3, r3, #2
|
|
800410a: 440b add r3, r1
|
|
800410c: 332c adds r3, #44 @ 0x2c
|
|
800410e: 681a ldr r2, [r3, #0]
|
|
8004110: 693b ldr r3, [r7, #16]
|
|
8004112: 18d1 adds r1, r2, r3
|
|
8004114: 6878 ldr r0, [r7, #4]
|
|
8004116: 69ba ldr r2, [r7, #24]
|
|
8004118: 4613 mov r3, r2
|
|
800411a: 011b lsls r3, r3, #4
|
|
800411c: 1a9b subs r3, r3, r2
|
|
800411e: 009b lsls r3, r3, #2
|
|
8004120: 4403 add r3, r0
|
|
8004122: 332c adds r3, #44 @ 0x2c
|
|
8004124: 6019 str r1, [r3, #0]
|
|
hhcd->hc[chnum].xfer_count += pktcnt;
|
|
8004126: 6879 ldr r1, [r7, #4]
|
|
8004128: 69ba ldr r2, [r7, #24]
|
|
800412a: 4613 mov r3, r2
|
|
800412c: 011b lsls r3, r3, #4
|
|
800412e: 1a9b subs r3, r3, r2
|
|
8004130: 009b lsls r3, r3, #2
|
|
8004132: 440b add r3, r1
|
|
8004134: 3338 adds r3, #56 @ 0x38
|
|
8004136: 681a ldr r2, [r3, #0]
|
|
8004138: 693b ldr r3, [r7, #16]
|
|
800413a: 18d1 adds r1, r2, r3
|
|
800413c: 6878 ldr r0, [r7, #4]
|
|
800413e: 69ba ldr r2, [r7, #24]
|
|
8004140: 4613 mov r3, r2
|
|
8004142: 011b lsls r3, r3, #4
|
|
8004144: 1a9b subs r3, r3, r2
|
|
8004146: 009b lsls r3, r3, #2
|
|
8004148: 4403 add r3, r0
|
|
800414a: 3338 adds r3, #56 @ 0x38
|
|
800414c: 6019 str r1, [r3, #0]
|
|
xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
|
|
800414e: 69bb ldr r3, [r7, #24]
|
|
8004150: 015a lsls r2, r3, #5
|
|
8004152: 6a3b ldr r3, [r7, #32]
|
|
8004154: 4413 add r3, r2
|
|
8004156: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800415a: 691b ldr r3, [r3, #16]
|
|
800415c: 0cdb lsrs r3, r3, #19
|
|
800415e: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8004162: 60fb str r3, [r7, #12]
|
|
if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
|
|
8004164: 6879 ldr r1, [r7, #4]
|
|
8004166: 69ba ldr r2, [r7, #24]
|
|
8004168: 4613 mov r3, r2
|
|
800416a: 011b lsls r3, r3, #4
|
|
800416c: 1a9b subs r3, r3, r2
|
|
800416e: 009b lsls r3, r3, #2
|
|
8004170: 440b add r3, r1
|
|
8004172: 3328 adds r3, #40 @ 0x28
|
|
8004174: 881b ldrh r3, [r3, #0]
|
|
8004176: 461a mov r2, r3
|
|
8004178: 693b ldr r3, [r7, #16]
|
|
800417a: 4293 cmp r3, r2
|
|
800417c: d13f bne.n 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
800417e: 68fb ldr r3, [r7, #12]
|
|
8004180: 2b00 cmp r3, #0
|
|
8004182: d03c beq.n 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8004184: 69bb ldr r3, [r7, #24]
|
|
8004186: 015a lsls r2, r3, #5
|
|
8004188: 6a3b ldr r3, [r7, #32]
|
|
800418a: 4413 add r3, r2
|
|
800418c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8004190: 681b ldr r3, [r3, #0]
|
|
8004192: 60bb str r3, [r7, #8]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8004194: 68bb ldr r3, [r7, #8]
|
|
8004196: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
800419a: 60bb str r3, [r7, #8]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
800419c: 68bb ldr r3, [r7, #8]
|
|
800419e: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80041a2: 60bb str r3, [r7, #8]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
80041a4: 69bb ldr r3, [r7, #24]
|
|
80041a6: 015a lsls r2, r3, #5
|
|
80041a8: 6a3b ldr r3, [r7, #32]
|
|
80041aa: 4413 add r3, r2
|
|
80041ac: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80041b0: 461a mov r2, r3
|
|
80041b2: 68bb ldr r3, [r7, #8]
|
|
80041b4: 6013 str r3, [r2, #0]
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
80041b6: 6879 ldr r1, [r7, #4]
|
|
80041b8: 69ba ldr r2, [r7, #24]
|
|
80041ba: 4613 mov r3, r2
|
|
80041bc: 011b lsls r3, r3, #4
|
|
80041be: 1a9b subs r3, r3, r2
|
|
80041c0: 009b lsls r3, r3, #2
|
|
80041c2: 440b add r3, r1
|
|
80041c4: 333c adds r3, #60 @ 0x3c
|
|
80041c6: 781b ldrb r3, [r3, #0]
|
|
80041c8: f083 0301 eor.w r3, r3, #1
|
|
80041cc: b2d8 uxtb r0, r3
|
|
80041ce: 6879 ldr r1, [r7, #4]
|
|
80041d0: 69ba ldr r2, [r7, #24]
|
|
80041d2: 4613 mov r3, r2
|
|
80041d4: 011b lsls r3, r3, #4
|
|
80041d6: 1a9b subs r3, r3, r2
|
|
80041d8: 009b lsls r3, r3, #2
|
|
80041da: 440b add r3, r1
|
|
80041dc: 333c adds r3, #60 @ 0x3c
|
|
80041de: 4602 mov r2, r0
|
|
80041e0: 701a strb r2, [r3, #0]
|
|
break;
|
|
80041e2: e00c b.n 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
80041e4: 6879 ldr r1, [r7, #4]
|
|
80041e6: 69ba ldr r2, [r7, #24]
|
|
80041e8: 4613 mov r3, r2
|
|
80041ea: 011b lsls r3, r3, #4
|
|
80041ec: 1a9b subs r3, r3, r2
|
|
80041ee: 009b lsls r3, r3, #2
|
|
80041f0: 440b add r3, r1
|
|
80041f2: 334c adds r3, #76 @ 0x4c
|
|
80041f4: 2204 movs r2, #4
|
|
80041f6: 701a strb r2, [r3, #0]
|
|
break;
|
|
80041f8: e001 b.n 80041fe <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
break;
|
|
80041fa: bf00 nop
|
|
80041fc: e000 b.n 8004200 <HCD_RXQLVL_IRQHandler+0x1b6>
|
|
break;
|
|
80041fe: bf00 nop
|
|
}
|
|
}
|
|
8004200: bf00 nop
|
|
8004202: 3728 adds r7, #40 @ 0x28
|
|
8004204: 46bd mov sp, r7
|
|
8004206: bd80 pop {r7, pc}
|
|
|
|
08004208 <HCD_Port_IRQHandler>:
|
|
* @brief Handle Host Port interrupt requests.
|
|
* @param hhcd HCD handle
|
|
* @retval None
|
|
*/
|
|
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8004208: b580 push {r7, lr}
|
|
800420a: b086 sub sp, #24
|
|
800420c: af00 add r7, sp, #0
|
|
800420e: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8004210: 687b ldr r3, [r7, #4]
|
|
8004212: 681b ldr r3, [r3, #0]
|
|
8004214: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8004216: 697b ldr r3, [r7, #20]
|
|
8004218: 613b str r3, [r7, #16]
|
|
__IO uint32_t hprt0;
|
|
__IO uint32_t hprt0_dup;
|
|
|
|
/* Handle Host Port Interrupts */
|
|
hprt0 = USBx_HPRT0;
|
|
800421a: 693b ldr r3, [r7, #16]
|
|
800421c: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8004220: 681b ldr r3, [r3, #0]
|
|
8004222: 60fb str r3, [r7, #12]
|
|
hprt0_dup = USBx_HPRT0;
|
|
8004224: 693b ldr r3, [r7, #16]
|
|
8004226: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
800422a: 681b ldr r3, [r3, #0]
|
|
800422c: 60bb str r3, [r7, #8]
|
|
|
|
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
|
|
800422e: 68bb ldr r3, [r7, #8]
|
|
8004230: f023 032e bic.w r3, r3, #46 @ 0x2e
|
|
8004234: 60bb str r3, [r7, #8]
|
|
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
|
|
|
|
/* Check whether Port Connect detected */
|
|
if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
|
|
8004236: 68fb ldr r3, [r7, #12]
|
|
8004238: f003 0302 and.w r3, r3, #2
|
|
800423c: 2b02 cmp r3, #2
|
|
800423e: d10b bne.n 8004258 <HCD_Port_IRQHandler+0x50>
|
|
{
|
|
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
|
|
8004240: 68fb ldr r3, [r7, #12]
|
|
8004242: f003 0301 and.w r3, r3, #1
|
|
8004246: 2b01 cmp r3, #1
|
|
8004248: d102 bne.n 8004250 <HCD_Port_IRQHandler+0x48>
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->ConnectCallback(hhcd);
|
|
#else
|
|
HAL_HCD_Connect_Callback(hhcd);
|
|
800424a: 6878 ldr r0, [r7, #4]
|
|
800424c: f008 fb8a bl 800c964 <HAL_HCD_Connect_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
hprt0_dup |= USB_OTG_HPRT_PCDET;
|
|
8004250: 68bb ldr r3, [r7, #8]
|
|
8004252: f043 0302 orr.w r3, r3, #2
|
|
8004256: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
/* Check whether Port Enable Changed */
|
|
if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
|
|
8004258: 68fb ldr r3, [r7, #12]
|
|
800425a: f003 0308 and.w r3, r3, #8
|
|
800425e: 2b08 cmp r3, #8
|
|
8004260: d132 bne.n 80042c8 <HCD_Port_IRQHandler+0xc0>
|
|
{
|
|
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
|
|
8004262: 68bb ldr r3, [r7, #8]
|
|
8004264: f043 0308 orr.w r3, r3, #8
|
|
8004268: 60bb str r3, [r7, #8]
|
|
|
|
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
|
|
800426a: 68fb ldr r3, [r7, #12]
|
|
800426c: f003 0304 and.w r3, r3, #4
|
|
8004270: 2b04 cmp r3, #4
|
|
8004272: d126 bne.n 80042c2 <HCD_Port_IRQHandler+0xba>
|
|
{
|
|
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
|
|
8004274: 687b ldr r3, [r7, #4]
|
|
8004276: 7a5b ldrb r3, [r3, #9]
|
|
8004278: 2b02 cmp r3, #2
|
|
800427a: d113 bne.n 80042a4 <HCD_Port_IRQHandler+0x9c>
|
|
{
|
|
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
|
|
800427c: 68fb ldr r3, [r7, #12]
|
|
800427e: f403 23c0 and.w r3, r3, #393216 @ 0x60000
|
|
8004282: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8004286: d106 bne.n 8004296 <HCD_Port_IRQHandler+0x8e>
|
|
{
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
|
|
8004288: 687b ldr r3, [r7, #4]
|
|
800428a: 681b ldr r3, [r3, #0]
|
|
800428c: 2102 movs r1, #2
|
|
800428e: 4618 mov r0, r3
|
|
8004290: f002 ff44 bl 800711c <USB_InitFSLSPClkSel>
|
|
8004294: e011 b.n 80042ba <HCD_Port_IRQHandler+0xb2>
|
|
}
|
|
else
|
|
{
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
|
|
8004296: 687b ldr r3, [r7, #4]
|
|
8004298: 681b ldr r3, [r3, #0]
|
|
800429a: 2101 movs r1, #1
|
|
800429c: 4618 mov r0, r3
|
|
800429e: f002 ff3d bl 800711c <USB_InitFSLSPClkSel>
|
|
80042a2: e00a b.n 80042ba <HCD_Port_IRQHandler+0xb2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (hhcd->Init.speed == HCD_SPEED_FULL)
|
|
80042a4: 687b ldr r3, [r7, #4]
|
|
80042a6: 79db ldrb r3, [r3, #7]
|
|
80042a8: 2b01 cmp r3, #1
|
|
80042aa: d106 bne.n 80042ba <HCD_Port_IRQHandler+0xb2>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_60_MHZ;
|
|
80042ac: 693b ldr r3, [r7, #16]
|
|
80042ae: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80042b2: 461a mov r2, r3
|
|
80042b4: f64e 2360 movw r3, #60000 @ 0xea60
|
|
80042b8: 6053 str r3, [r2, #4]
|
|
}
|
|
}
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->PortEnabledCallback(hhcd);
|
|
#else
|
|
HAL_HCD_PortEnabled_Callback(hhcd);
|
|
80042ba: 6878 ldr r0, [r7, #4]
|
|
80042bc: f008 fb80 bl 800c9c0 <HAL_HCD_PortEnabled_Callback>
|
|
80042c0: e002 b.n 80042c8 <HCD_Port_IRQHandler+0xc0>
|
|
else
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->PortDisabledCallback(hhcd);
|
|
#else
|
|
HAL_HCD_PortDisabled_Callback(hhcd);
|
|
80042c2: 6878 ldr r0, [r7, #4]
|
|
80042c4: f008 fb8a bl 800c9dc <HAL_HCD_PortDisabled_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Check for an overcurrent */
|
|
if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
|
|
80042c8: 68fb ldr r3, [r7, #12]
|
|
80042ca: f003 0320 and.w r3, r3, #32
|
|
80042ce: 2b20 cmp r3, #32
|
|
80042d0: d103 bne.n 80042da <HCD_Port_IRQHandler+0xd2>
|
|
{
|
|
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
|
|
80042d2: 68bb ldr r3, [r7, #8]
|
|
80042d4: f043 0320 orr.w r3, r3, #32
|
|
80042d8: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
/* Clear Port Interrupts */
|
|
USBx_HPRT0 = hprt0_dup;
|
|
80042da: 693b ldr r3, [r7, #16]
|
|
80042dc: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
80042e0: 461a mov r2, r3
|
|
80042e2: 68bb ldr r3, [r7, #8]
|
|
80042e4: 6013 str r3, [r2, #0]
|
|
}
|
|
80042e6: bf00 nop
|
|
80042e8: 3718 adds r7, #24
|
|
80042ea: 46bd mov sp, r7
|
|
80042ec: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080042f0 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
80042f0: b580 push {r7, lr}
|
|
80042f2: b084 sub sp, #16
|
|
80042f4: af00 add r7, sp, #0
|
|
80042f6: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
80042f8: 687b ldr r3, [r7, #4]
|
|
80042fa: 2b00 cmp r3, #0
|
|
80042fc: d101 bne.n 8004302 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80042fe: 2301 movs r3, #1
|
|
8004300: e12b b.n 800455a <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8004302: 687b ldr r3, [r7, #4]
|
|
8004304: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004308: b2db uxtb r3, r3
|
|
800430a: 2b00 cmp r3, #0
|
|
800430c: d106 bne.n 800431c <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
800430e: 687b ldr r3, [r7, #4]
|
|
8004310: 2200 movs r2, #0
|
|
8004312: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8004316: 6878 ldr r0, [r7, #4]
|
|
8004318: f7fc fd90 bl 8000e3c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800431c: 687b ldr r3, [r7, #4]
|
|
800431e: 2224 movs r2, #36 @ 0x24
|
|
8004320: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8004324: 687b ldr r3, [r7, #4]
|
|
8004326: 681b ldr r3, [r3, #0]
|
|
8004328: 681a ldr r2, [r3, #0]
|
|
800432a: 687b ldr r3, [r7, #4]
|
|
800432c: 681b ldr r3, [r3, #0]
|
|
800432e: f022 0201 bic.w r2, r2, #1
|
|
8004332: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8004334: 687b ldr r3, [r7, #4]
|
|
8004336: 681b ldr r3, [r3, #0]
|
|
8004338: 681a ldr r2, [r3, #0]
|
|
800433a: 687b ldr r3, [r7, #4]
|
|
800433c: 681b ldr r3, [r3, #0]
|
|
800433e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8004342: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8004344: 687b ldr r3, [r7, #4]
|
|
8004346: 681b ldr r3, [r3, #0]
|
|
8004348: 681a ldr r2, [r3, #0]
|
|
800434a: 687b ldr r3, [r7, #4]
|
|
800434c: 681b ldr r3, [r3, #0]
|
|
800434e: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8004352: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8004354: f001 f90c bl 8005570 <HAL_RCC_GetPCLK1Freq>
|
|
8004358: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
800435a: 687b ldr r3, [r7, #4]
|
|
800435c: 685b ldr r3, [r3, #4]
|
|
800435e: 4a81 ldr r2, [pc, #516] @ (8004564 <HAL_I2C_Init+0x274>)
|
|
8004360: 4293 cmp r3, r2
|
|
8004362: d807 bhi.n 8004374 <HAL_I2C_Init+0x84>
|
|
8004364: 68fb ldr r3, [r7, #12]
|
|
8004366: 4a80 ldr r2, [pc, #512] @ (8004568 <HAL_I2C_Init+0x278>)
|
|
8004368: 4293 cmp r3, r2
|
|
800436a: bf94 ite ls
|
|
800436c: 2301 movls r3, #1
|
|
800436e: 2300 movhi r3, #0
|
|
8004370: b2db uxtb r3, r3
|
|
8004372: e006 b.n 8004382 <HAL_I2C_Init+0x92>
|
|
8004374: 68fb ldr r3, [r7, #12]
|
|
8004376: 4a7d ldr r2, [pc, #500] @ (800456c <HAL_I2C_Init+0x27c>)
|
|
8004378: 4293 cmp r3, r2
|
|
800437a: bf94 ite ls
|
|
800437c: 2301 movls r3, #1
|
|
800437e: 2300 movhi r3, #0
|
|
8004380: b2db uxtb r3, r3
|
|
8004382: 2b00 cmp r3, #0
|
|
8004384: d001 beq.n 800438a <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8004386: 2301 movs r3, #1
|
|
8004388: e0e7 b.n 800455a <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
800438a: 68fb ldr r3, [r7, #12]
|
|
800438c: 4a78 ldr r2, [pc, #480] @ (8004570 <HAL_I2C_Init+0x280>)
|
|
800438e: fba2 2303 umull r2, r3, r2, r3
|
|
8004392: 0c9b lsrs r3, r3, #18
|
|
8004394: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8004396: 687b ldr r3, [r7, #4]
|
|
8004398: 681b ldr r3, [r3, #0]
|
|
800439a: 685b ldr r3, [r3, #4]
|
|
800439c: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80043a0: 687b ldr r3, [r7, #4]
|
|
80043a2: 681b ldr r3, [r3, #0]
|
|
80043a4: 68ba ldr r2, [r7, #8]
|
|
80043a6: 430a orrs r2, r1
|
|
80043a8: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
80043aa: 687b ldr r3, [r7, #4]
|
|
80043ac: 681b ldr r3, [r3, #0]
|
|
80043ae: 6a1b ldr r3, [r3, #32]
|
|
80043b0: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
80043b4: 687b ldr r3, [r7, #4]
|
|
80043b6: 685b ldr r3, [r3, #4]
|
|
80043b8: 4a6a ldr r2, [pc, #424] @ (8004564 <HAL_I2C_Init+0x274>)
|
|
80043ba: 4293 cmp r3, r2
|
|
80043bc: d802 bhi.n 80043c4 <HAL_I2C_Init+0xd4>
|
|
80043be: 68bb ldr r3, [r7, #8]
|
|
80043c0: 3301 adds r3, #1
|
|
80043c2: e009 b.n 80043d8 <HAL_I2C_Init+0xe8>
|
|
80043c4: 68bb ldr r3, [r7, #8]
|
|
80043c6: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
80043ca: fb02 f303 mul.w r3, r2, r3
|
|
80043ce: 4a69 ldr r2, [pc, #420] @ (8004574 <HAL_I2C_Init+0x284>)
|
|
80043d0: fba2 2303 umull r2, r3, r2, r3
|
|
80043d4: 099b lsrs r3, r3, #6
|
|
80043d6: 3301 adds r3, #1
|
|
80043d8: 687a ldr r2, [r7, #4]
|
|
80043da: 6812 ldr r2, [r2, #0]
|
|
80043dc: 430b orrs r3, r1
|
|
80043de: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
80043e0: 687b ldr r3, [r7, #4]
|
|
80043e2: 681b ldr r3, [r3, #0]
|
|
80043e4: 69db ldr r3, [r3, #28]
|
|
80043e6: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
80043ea: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
80043ee: 687b ldr r3, [r7, #4]
|
|
80043f0: 685b ldr r3, [r3, #4]
|
|
80043f2: 495c ldr r1, [pc, #368] @ (8004564 <HAL_I2C_Init+0x274>)
|
|
80043f4: 428b cmp r3, r1
|
|
80043f6: d819 bhi.n 800442c <HAL_I2C_Init+0x13c>
|
|
80043f8: 68fb ldr r3, [r7, #12]
|
|
80043fa: 1e59 subs r1, r3, #1
|
|
80043fc: 687b ldr r3, [r7, #4]
|
|
80043fe: 685b ldr r3, [r3, #4]
|
|
8004400: 005b lsls r3, r3, #1
|
|
8004402: fbb1 f3f3 udiv r3, r1, r3
|
|
8004406: 1c59 adds r1, r3, #1
|
|
8004408: f640 73fc movw r3, #4092 @ 0xffc
|
|
800440c: 400b ands r3, r1
|
|
800440e: 2b00 cmp r3, #0
|
|
8004410: d00a beq.n 8004428 <HAL_I2C_Init+0x138>
|
|
8004412: 68fb ldr r3, [r7, #12]
|
|
8004414: 1e59 subs r1, r3, #1
|
|
8004416: 687b ldr r3, [r7, #4]
|
|
8004418: 685b ldr r3, [r3, #4]
|
|
800441a: 005b lsls r3, r3, #1
|
|
800441c: fbb1 f3f3 udiv r3, r1, r3
|
|
8004420: 3301 adds r3, #1
|
|
8004422: f3c3 030b ubfx r3, r3, #0, #12
|
|
8004426: e051 b.n 80044cc <HAL_I2C_Init+0x1dc>
|
|
8004428: 2304 movs r3, #4
|
|
800442a: e04f b.n 80044cc <HAL_I2C_Init+0x1dc>
|
|
800442c: 687b ldr r3, [r7, #4]
|
|
800442e: 689b ldr r3, [r3, #8]
|
|
8004430: 2b00 cmp r3, #0
|
|
8004432: d111 bne.n 8004458 <HAL_I2C_Init+0x168>
|
|
8004434: 68fb ldr r3, [r7, #12]
|
|
8004436: 1e58 subs r0, r3, #1
|
|
8004438: 687b ldr r3, [r7, #4]
|
|
800443a: 6859 ldr r1, [r3, #4]
|
|
800443c: 460b mov r3, r1
|
|
800443e: 005b lsls r3, r3, #1
|
|
8004440: 440b add r3, r1
|
|
8004442: fbb0 f3f3 udiv r3, r0, r3
|
|
8004446: 3301 adds r3, #1
|
|
8004448: f3c3 030b ubfx r3, r3, #0, #12
|
|
800444c: 2b00 cmp r3, #0
|
|
800444e: bf0c ite eq
|
|
8004450: 2301 moveq r3, #1
|
|
8004452: 2300 movne r3, #0
|
|
8004454: b2db uxtb r3, r3
|
|
8004456: e012 b.n 800447e <HAL_I2C_Init+0x18e>
|
|
8004458: 68fb ldr r3, [r7, #12]
|
|
800445a: 1e58 subs r0, r3, #1
|
|
800445c: 687b ldr r3, [r7, #4]
|
|
800445e: 6859 ldr r1, [r3, #4]
|
|
8004460: 460b mov r3, r1
|
|
8004462: 009b lsls r3, r3, #2
|
|
8004464: 440b add r3, r1
|
|
8004466: 0099 lsls r1, r3, #2
|
|
8004468: 440b add r3, r1
|
|
800446a: fbb0 f3f3 udiv r3, r0, r3
|
|
800446e: 3301 adds r3, #1
|
|
8004470: f3c3 030b ubfx r3, r3, #0, #12
|
|
8004474: 2b00 cmp r3, #0
|
|
8004476: bf0c ite eq
|
|
8004478: 2301 moveq r3, #1
|
|
800447a: 2300 movne r3, #0
|
|
800447c: b2db uxtb r3, r3
|
|
800447e: 2b00 cmp r3, #0
|
|
8004480: d001 beq.n 8004486 <HAL_I2C_Init+0x196>
|
|
8004482: 2301 movs r3, #1
|
|
8004484: e022 b.n 80044cc <HAL_I2C_Init+0x1dc>
|
|
8004486: 687b ldr r3, [r7, #4]
|
|
8004488: 689b ldr r3, [r3, #8]
|
|
800448a: 2b00 cmp r3, #0
|
|
800448c: d10e bne.n 80044ac <HAL_I2C_Init+0x1bc>
|
|
800448e: 68fb ldr r3, [r7, #12]
|
|
8004490: 1e58 subs r0, r3, #1
|
|
8004492: 687b ldr r3, [r7, #4]
|
|
8004494: 6859 ldr r1, [r3, #4]
|
|
8004496: 460b mov r3, r1
|
|
8004498: 005b lsls r3, r3, #1
|
|
800449a: 440b add r3, r1
|
|
800449c: fbb0 f3f3 udiv r3, r0, r3
|
|
80044a0: 3301 adds r3, #1
|
|
80044a2: f3c3 030b ubfx r3, r3, #0, #12
|
|
80044a6: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
80044aa: e00f b.n 80044cc <HAL_I2C_Init+0x1dc>
|
|
80044ac: 68fb ldr r3, [r7, #12]
|
|
80044ae: 1e58 subs r0, r3, #1
|
|
80044b0: 687b ldr r3, [r7, #4]
|
|
80044b2: 6859 ldr r1, [r3, #4]
|
|
80044b4: 460b mov r3, r1
|
|
80044b6: 009b lsls r3, r3, #2
|
|
80044b8: 440b add r3, r1
|
|
80044ba: 0099 lsls r1, r3, #2
|
|
80044bc: 440b add r3, r1
|
|
80044be: fbb0 f3f3 udiv r3, r0, r3
|
|
80044c2: 3301 adds r3, #1
|
|
80044c4: f3c3 030b ubfx r3, r3, #0, #12
|
|
80044c8: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
80044cc: 6879 ldr r1, [r7, #4]
|
|
80044ce: 6809 ldr r1, [r1, #0]
|
|
80044d0: 4313 orrs r3, r2
|
|
80044d2: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
80044d4: 687b ldr r3, [r7, #4]
|
|
80044d6: 681b ldr r3, [r3, #0]
|
|
80044d8: 681b ldr r3, [r3, #0]
|
|
80044da: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
80044de: 687b ldr r3, [r7, #4]
|
|
80044e0: 69da ldr r2, [r3, #28]
|
|
80044e2: 687b ldr r3, [r7, #4]
|
|
80044e4: 6a1b ldr r3, [r3, #32]
|
|
80044e6: 431a orrs r2, r3
|
|
80044e8: 687b ldr r3, [r7, #4]
|
|
80044ea: 681b ldr r3, [r3, #0]
|
|
80044ec: 430a orrs r2, r1
|
|
80044ee: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
80044f0: 687b ldr r3, [r7, #4]
|
|
80044f2: 681b ldr r3, [r3, #0]
|
|
80044f4: 689b ldr r3, [r3, #8]
|
|
80044f6: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
80044fa: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
80044fe: 687a ldr r2, [r7, #4]
|
|
8004500: 6911 ldr r1, [r2, #16]
|
|
8004502: 687a ldr r2, [r7, #4]
|
|
8004504: 68d2 ldr r2, [r2, #12]
|
|
8004506: 4311 orrs r1, r2
|
|
8004508: 687a ldr r2, [r7, #4]
|
|
800450a: 6812 ldr r2, [r2, #0]
|
|
800450c: 430b orrs r3, r1
|
|
800450e: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8004510: 687b ldr r3, [r7, #4]
|
|
8004512: 681b ldr r3, [r3, #0]
|
|
8004514: 68db ldr r3, [r3, #12]
|
|
8004516: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
800451a: 687b ldr r3, [r7, #4]
|
|
800451c: 695a ldr r2, [r3, #20]
|
|
800451e: 687b ldr r3, [r7, #4]
|
|
8004520: 699b ldr r3, [r3, #24]
|
|
8004522: 431a orrs r2, r3
|
|
8004524: 687b ldr r3, [r7, #4]
|
|
8004526: 681b ldr r3, [r3, #0]
|
|
8004528: 430a orrs r2, r1
|
|
800452a: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
800452c: 687b ldr r3, [r7, #4]
|
|
800452e: 681b ldr r3, [r3, #0]
|
|
8004530: 681a ldr r2, [r3, #0]
|
|
8004532: 687b ldr r3, [r7, #4]
|
|
8004534: 681b ldr r3, [r3, #0]
|
|
8004536: f042 0201 orr.w r2, r2, #1
|
|
800453a: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
800453c: 687b ldr r3, [r7, #4]
|
|
800453e: 2200 movs r2, #0
|
|
8004540: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004542: 687b ldr r3, [r7, #4]
|
|
8004544: 2220 movs r2, #32
|
|
8004546: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
800454a: 687b ldr r3, [r7, #4]
|
|
800454c: 2200 movs r2, #0
|
|
800454e: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8004550: 687b ldr r3, [r7, #4]
|
|
8004552: 2200 movs r2, #0
|
|
8004554: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8004558: 2300 movs r3, #0
|
|
}
|
|
800455a: 4618 mov r0, r3
|
|
800455c: 3710 adds r7, #16
|
|
800455e: 46bd mov sp, r7
|
|
8004560: bd80 pop {r7, pc}
|
|
8004562: bf00 nop
|
|
8004564: 000186a0 .word 0x000186a0
|
|
8004568: 001e847f .word 0x001e847f
|
|
800456c: 003d08ff .word 0x003d08ff
|
|
8004570: 431bde83 .word 0x431bde83
|
|
8004574: 10624dd3 .word 0x10624dd3
|
|
|
|
08004578 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter new state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8004578: b480 push {r7}
|
|
800457a: b083 sub sp, #12
|
|
800457c: af00 add r7, sp, #0
|
|
800457e: 6078 str r0, [r7, #4]
|
|
8004580: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8004582: 687b ldr r3, [r7, #4]
|
|
8004584: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004588: b2db uxtb r3, r3
|
|
800458a: 2b20 cmp r3, #32
|
|
800458c: d129 bne.n 80045e2 <HAL_I2CEx_ConfigAnalogFilter+0x6a>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800458e: 687b ldr r3, [r7, #4]
|
|
8004590: 2224 movs r2, #36 @ 0x24
|
|
8004592: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8004596: 687b ldr r3, [r7, #4]
|
|
8004598: 681b ldr r3, [r3, #0]
|
|
800459a: 681a ldr r2, [r3, #0]
|
|
800459c: 687b ldr r3, [r7, #4]
|
|
800459e: 681b ldr r3, [r3, #0]
|
|
80045a0: f022 0201 bic.w r2, r2, #1
|
|
80045a4: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
|
|
80045a6: 687b ldr r3, [r7, #4]
|
|
80045a8: 681b ldr r3, [r3, #0]
|
|
80045aa: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
80045ac: 687b ldr r3, [r7, #4]
|
|
80045ae: 681b ldr r3, [r3, #0]
|
|
80045b0: f022 0210 bic.w r2, r2, #16
|
|
80045b4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Disable the analog filter */
|
|
hi2c->Instance->FLTR |= AnalogFilter;
|
|
80045b6: 687b ldr r3, [r7, #4]
|
|
80045b8: 681b ldr r3, [r3, #0]
|
|
80045ba: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
80045bc: 687b ldr r3, [r7, #4]
|
|
80045be: 681b ldr r3, [r3, #0]
|
|
80045c0: 683a ldr r2, [r7, #0]
|
|
80045c2: 430a orrs r2, r1
|
|
80045c4: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
80045c6: 687b ldr r3, [r7, #4]
|
|
80045c8: 681b ldr r3, [r3, #0]
|
|
80045ca: 681a ldr r2, [r3, #0]
|
|
80045cc: 687b ldr r3, [r7, #4]
|
|
80045ce: 681b ldr r3, [r3, #0]
|
|
80045d0: f042 0201 orr.w r2, r2, #1
|
|
80045d4: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80045d6: 687b ldr r3, [r7, #4]
|
|
80045d8: 2220 movs r2, #32
|
|
80045da: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80045de: 2300 movs r3, #0
|
|
80045e0: e000 b.n 80045e4 <HAL_I2CEx_ConfigAnalogFilter+0x6c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80045e2: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80045e4: 4618 mov r0, r3
|
|
80045e6: 370c adds r7, #12
|
|
80045e8: 46bd mov sp, r7
|
|
80045ea: f85d 7b04 ldr.w r7, [sp], #4
|
|
80045ee: 4770 bx lr
|
|
|
|
080045f0 <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
80045f0: b480 push {r7}
|
|
80045f2: b085 sub sp, #20
|
|
80045f4: af00 add r7, sp, #0
|
|
80045f6: 6078 str r0, [r7, #4]
|
|
80045f8: 6039 str r1, [r7, #0]
|
|
uint16_t tmpreg = 0;
|
|
80045fa: 2300 movs r3, #0
|
|
80045fc: 81fb strh r3, [r7, #14]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
80045fe: 687b ldr r3, [r7, #4]
|
|
8004600: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8004604: b2db uxtb r3, r3
|
|
8004606: 2b20 cmp r3, #32
|
|
8004608: d12a bne.n 8004660 <HAL_I2CEx_ConfigDigitalFilter+0x70>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800460a: 687b ldr r3, [r7, #4]
|
|
800460c: 2224 movs r2, #36 @ 0x24
|
|
800460e: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8004612: 687b ldr r3, [r7, #4]
|
|
8004614: 681b ldr r3, [r3, #0]
|
|
8004616: 681a ldr r2, [r3, #0]
|
|
8004618: 687b ldr r3, [r7, #4]
|
|
800461a: 681b ldr r3, [r3, #0]
|
|
800461c: f022 0201 bic.w r2, r2, #1
|
|
8004620: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->FLTR;
|
|
8004622: 687b ldr r3, [r7, #4]
|
|
8004624: 681b ldr r3, [r3, #0]
|
|
8004626: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004628: 81fb strh r3, [r7, #14]
|
|
|
|
/* Reset I2Cx DNF bit [3:0] */
|
|
tmpreg &= ~(I2C_FLTR_DNF);
|
|
800462a: 89fb ldrh r3, [r7, #14]
|
|
800462c: f023 030f bic.w r3, r3, #15
|
|
8004630: 81fb strh r3, [r7, #14]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter;
|
|
8004632: 683b ldr r3, [r7, #0]
|
|
8004634: b29a uxth r2, r3
|
|
8004636: 89fb ldrh r3, [r7, #14]
|
|
8004638: 4313 orrs r3, r2
|
|
800463a: 81fb strh r3, [r7, #14]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->FLTR = tmpreg;
|
|
800463c: 687b ldr r3, [r7, #4]
|
|
800463e: 681b ldr r3, [r3, #0]
|
|
8004640: 89fa ldrh r2, [r7, #14]
|
|
8004642: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8004644: 687b ldr r3, [r7, #4]
|
|
8004646: 681b ldr r3, [r3, #0]
|
|
8004648: 681a ldr r2, [r3, #0]
|
|
800464a: 687b ldr r3, [r7, #4]
|
|
800464c: 681b ldr r3, [r3, #0]
|
|
800464e: f042 0201 orr.w r2, r2, #1
|
|
8004652: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8004654: 687b ldr r3, [r7, #4]
|
|
8004656: 2220 movs r2, #32
|
|
8004658: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
800465c: 2300 movs r3, #0
|
|
800465e: e000 b.n 8004662 <HAL_I2CEx_ConfigDigitalFilter+0x72>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004660: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004662: 4618 mov r0, r3
|
|
8004664: 3714 adds r7, #20
|
|
8004666: 46bd mov sp, r7
|
|
8004668: f85d 7b04 ldr.w r7, [sp], #4
|
|
800466c: 4770 bx lr
|
|
|
|
0800466e <HAL_LTDC_Init>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
800466e: b580 push {r7, lr}
|
|
8004670: b084 sub sp, #16
|
|
8004672: af00 add r7, sp, #0
|
|
8004674: 6078 str r0, [r7, #4]
|
|
uint32_t tmp;
|
|
uint32_t tmp1;
|
|
|
|
/* Check the LTDC peripheral state */
|
|
if (hltdc == NULL)
|
|
8004676: 687b ldr r3, [r7, #4]
|
|
8004678: 2b00 cmp r3, #0
|
|
800467a: d101 bne.n 8004680 <HAL_LTDC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800467c: 2301 movs r3, #1
|
|
800467e: e08f b.n 80047a0 <HAL_LTDC_Init+0x132>
|
|
}
|
|
/* Init the low level hardware */
|
|
hltdc->MspInitCallback(hltdc);
|
|
}
|
|
#else
|
|
if (hltdc->State == HAL_LTDC_STATE_RESET)
|
|
8004680: 687b ldr r3, [r7, #4]
|
|
8004682: f893 30a1 ldrb.w r3, [r3, #161] @ 0xa1
|
|
8004686: b2db uxtb r3, r3
|
|
8004688: 2b00 cmp r3, #0
|
|
800468a: d106 bne.n 800469a <HAL_LTDC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hltdc->Lock = HAL_UNLOCKED;
|
|
800468c: 687b ldr r3, [r7, #4]
|
|
800468e: 2200 movs r2, #0
|
|
8004690: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
/* Init the low level hardware */
|
|
HAL_LTDC_MspInit(hltdc);
|
|
8004694: 6878 ldr r0, [r7, #4]
|
|
8004696: f7fc fc3b bl 8000f10 <HAL_LTDC_MspInit>
|
|
}
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
800469a: 687b ldr r3, [r7, #4]
|
|
800469c: 2202 movs r2, #2
|
|
800469e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Configure the HS, VS, DE and PC polarity */
|
|
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
|
|
80046a2: 687b ldr r3, [r7, #4]
|
|
80046a4: 681b ldr r3, [r3, #0]
|
|
80046a6: 699a ldr r2, [r3, #24]
|
|
80046a8: 687b ldr r3, [r7, #4]
|
|
80046aa: 681b ldr r3, [r3, #0]
|
|
80046ac: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000
|
|
80046b0: 619a str r2, [r3, #24]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
80046b2: 687b ldr r3, [r7, #4]
|
|
80046b4: 681b ldr r3, [r3, #0]
|
|
80046b6: 6999 ldr r1, [r3, #24]
|
|
80046b8: 687b ldr r3, [r7, #4]
|
|
80046ba: 685a ldr r2, [r3, #4]
|
|
80046bc: 687b ldr r3, [r7, #4]
|
|
80046be: 689b ldr r3, [r3, #8]
|
|
80046c0: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
80046c2: 687b ldr r3, [r7, #4]
|
|
80046c4: 68db ldr r3, [r3, #12]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
80046c6: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
80046c8: 687b ldr r3, [r7, #4]
|
|
80046ca: 691b ldr r3, [r3, #16]
|
|
80046cc: 431a orrs r2, r3
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
80046ce: 687b ldr r3, [r7, #4]
|
|
80046d0: 681b ldr r3, [r3, #0]
|
|
80046d2: 430a orrs r2, r1
|
|
80046d4: 619a str r2, [r3, #24]
|
|
|
|
/* Set Synchronization size */
|
|
tmp = (hltdc->Init.HorizontalSync << 16U);
|
|
80046d6: 687b ldr r3, [r7, #4]
|
|
80046d8: 695b ldr r3, [r3, #20]
|
|
80046da: 041b lsls r3, r3, #16
|
|
80046dc: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
|
|
80046de: 687b ldr r3, [r7, #4]
|
|
80046e0: 6999 ldr r1, [r3, #24]
|
|
80046e2: 687b ldr r3, [r7, #4]
|
|
80046e4: 681b ldr r3, [r3, #0]
|
|
80046e6: 68fa ldr r2, [r7, #12]
|
|
80046e8: 430a orrs r2, r1
|
|
80046ea: 609a str r2, [r3, #8]
|
|
|
|
/* Set Accumulated Back porch */
|
|
tmp = (hltdc->Init.AccumulatedHBP << 16U);
|
|
80046ec: 687b ldr r3, [r7, #4]
|
|
80046ee: 69db ldr r3, [r3, #28]
|
|
80046f0: 041b lsls r3, r3, #16
|
|
80046f2: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
|
|
80046f4: 687b ldr r3, [r7, #4]
|
|
80046f6: 6a19 ldr r1, [r3, #32]
|
|
80046f8: 687b ldr r3, [r7, #4]
|
|
80046fa: 681b ldr r3, [r3, #0]
|
|
80046fc: 68fa ldr r2, [r7, #12]
|
|
80046fe: 430a orrs r2, r1
|
|
8004700: 60da str r2, [r3, #12]
|
|
|
|
/* Set Accumulated Active Width */
|
|
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
|
|
8004702: 687b ldr r3, [r7, #4]
|
|
8004704: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004706: 041b lsls r3, r3, #16
|
|
8004708: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
|
|
800470a: 687b ldr r3, [r7, #4]
|
|
800470c: 6a99 ldr r1, [r3, #40] @ 0x28
|
|
800470e: 687b ldr r3, [r7, #4]
|
|
8004710: 681b ldr r3, [r3, #0]
|
|
8004712: 68fa ldr r2, [r7, #12]
|
|
8004714: 430a orrs r2, r1
|
|
8004716: 611a str r2, [r3, #16]
|
|
|
|
/* Set Total Width */
|
|
tmp = (hltdc->Init.TotalWidth << 16U);
|
|
8004718: 687b ldr r3, [r7, #4]
|
|
800471a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800471c: 041b lsls r3, r3, #16
|
|
800471e: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
|
|
8004720: 687b ldr r3, [r7, #4]
|
|
8004722: 6b19 ldr r1, [r3, #48] @ 0x30
|
|
8004724: 687b ldr r3, [r7, #4]
|
|
8004726: 681b ldr r3, [r3, #0]
|
|
8004728: 68fa ldr r2, [r7, #12]
|
|
800472a: 430a orrs r2, r1
|
|
800472c: 615a str r2, [r3, #20]
|
|
|
|
/* Set the background color value */
|
|
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
|
|
800472e: 687b ldr r3, [r7, #4]
|
|
8004730: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8004734: 021b lsls r3, r3, #8
|
|
8004736: 60fb str r3, [r7, #12]
|
|
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
|
|
8004738: 687b ldr r3, [r7, #4]
|
|
800473a: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
800473e: 041b lsls r3, r3, #16
|
|
8004740: 60bb str r3, [r7, #8]
|
|
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
|
|
8004742: 687b ldr r3, [r7, #4]
|
|
8004744: 681b ldr r3, [r3, #0]
|
|
8004746: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8004748: 687b ldr r3, [r7, #4]
|
|
800474a: 681b ldr r3, [r3, #0]
|
|
800474c: f002 427f and.w r2, r2, #4278190080 @ 0xff000000
|
|
8004750: 62da str r2, [r3, #44] @ 0x2c
|
|
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
|
|
8004752: 687b ldr r3, [r7, #4]
|
|
8004754: 681b ldr r3, [r3, #0]
|
|
8004756: 6ad9 ldr r1, [r3, #44] @ 0x2c
|
|
8004758: 68ba ldr r2, [r7, #8]
|
|
800475a: 68fb ldr r3, [r7, #12]
|
|
800475c: 4313 orrs r3, r2
|
|
800475e: 687a ldr r2, [r7, #4]
|
|
8004760: f892 2034 ldrb.w r2, [r2, #52] @ 0x34
|
|
8004764: 431a orrs r2, r3
|
|
8004766: 687b ldr r3, [r7, #4]
|
|
8004768: 681b ldr r3, [r3, #0]
|
|
800476a: 430a orrs r2, r1
|
|
800476c: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Enable the Transfer Error and FIFO underrun interrupts */
|
|
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
|
|
800476e: 687b ldr r3, [r7, #4]
|
|
8004770: 681b ldr r3, [r3, #0]
|
|
8004772: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8004774: 687b ldr r3, [r7, #4]
|
|
8004776: 681b ldr r3, [r3, #0]
|
|
8004778: f042 0206 orr.w r2, r2, #6
|
|
800477c: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Enable LTDC by setting LTDCEN bit */
|
|
__HAL_LTDC_ENABLE(hltdc);
|
|
800477e: 687b ldr r3, [r7, #4]
|
|
8004780: 681b ldr r3, [r3, #0]
|
|
8004782: 699a ldr r2, [r3, #24]
|
|
8004784: 687b ldr r3, [r7, #4]
|
|
8004786: 681b ldr r3, [r3, #0]
|
|
8004788: f042 0201 orr.w r2, r2, #1
|
|
800478c: 619a str r2, [r3, #24]
|
|
|
|
/* Initialize the error code */
|
|
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
|
|
800478e: 687b ldr r3, [r7, #4]
|
|
8004790: 2200 movs r2, #0
|
|
8004792: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8004796: 687b ldr r3, [r7, #4]
|
|
8004798: 2201 movs r2, #1
|
|
800479a: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
return HAL_OK;
|
|
800479e: 2300 movs r3, #0
|
|
}
|
|
80047a0: 4618 mov r0, r3
|
|
80047a2: 3710 adds r7, #16
|
|
80047a4: 46bd mov sp, r7
|
|
80047a6: bd80 pop {r7, pc}
|
|
|
|
080047a8 <HAL_LTDC_IRQHandler>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
80047a8: b580 push {r7, lr}
|
|
80047aa: b084 sub sp, #16
|
|
80047ac: af00 add r7, sp, #0
|
|
80047ae: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
|
|
80047b0: 687b ldr r3, [r7, #4]
|
|
80047b2: 681b ldr r3, [r3, #0]
|
|
80047b4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80047b6: 60fb str r3, [r7, #12]
|
|
uint32_t itsources = READ_REG(hltdc->Instance->IER);
|
|
80047b8: 687b ldr r3, [r7, #4]
|
|
80047ba: 681b ldr r3, [r3, #0]
|
|
80047bc: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
80047be: 60bb str r3, [r7, #8]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
|
|
80047c0: 68fb ldr r3, [r7, #12]
|
|
80047c2: f003 0304 and.w r3, r3, #4
|
|
80047c6: 2b00 cmp r3, #0
|
|
80047c8: d023 beq.n 8004812 <HAL_LTDC_IRQHandler+0x6a>
|
|
80047ca: 68bb ldr r3, [r7, #8]
|
|
80047cc: f003 0304 and.w r3, r3, #4
|
|
80047d0: 2b00 cmp r3, #0
|
|
80047d2: d01e beq.n 8004812 <HAL_LTDC_IRQHandler+0x6a>
|
|
{
|
|
/* Disable the transfer Error interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
|
|
80047d4: 687b ldr r3, [r7, #4]
|
|
80047d6: 681b ldr r3, [r3, #0]
|
|
80047d8: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80047da: 687b ldr r3, [r7, #4]
|
|
80047dc: 681b ldr r3, [r3, #0]
|
|
80047de: f022 0204 bic.w r2, r2, #4
|
|
80047e2: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the transfer error flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
|
|
80047e4: 687b ldr r3, [r7, #4]
|
|
80047e6: 681b ldr r3, [r3, #0]
|
|
80047e8: 2204 movs r2, #4
|
|
80047ea: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
|
|
80047ec: 687b ldr r3, [r7, #4]
|
|
80047ee: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
|
|
80047f2: f043 0201 orr.w r2, r3, #1
|
|
80047f6: 687b ldr r3, [r7, #4]
|
|
80047f8: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
80047fc: 687b ldr r3, [r7, #4]
|
|
80047fe: 2204 movs r2, #4
|
|
8004800: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004804: 687b ldr r3, [r7, #4]
|
|
8004806: 2200 movs r2, #0
|
|
8004808: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
800480c: 6878 ldr r0, [r7, #4]
|
|
800480e: f000 f86f bl 80048f0 <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* FIFO underrun Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
|
|
8004812: 68fb ldr r3, [r7, #12]
|
|
8004814: f003 0302 and.w r3, r3, #2
|
|
8004818: 2b00 cmp r3, #0
|
|
800481a: d023 beq.n 8004864 <HAL_LTDC_IRQHandler+0xbc>
|
|
800481c: 68bb ldr r3, [r7, #8]
|
|
800481e: f003 0302 and.w r3, r3, #2
|
|
8004822: 2b00 cmp r3, #0
|
|
8004824: d01e beq.n 8004864 <HAL_LTDC_IRQHandler+0xbc>
|
|
{
|
|
/* Disable the FIFO underrun interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
|
|
8004826: 687b ldr r3, [r7, #4]
|
|
8004828: 681b ldr r3, [r3, #0]
|
|
800482a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800482c: 687b ldr r3, [r7, #4]
|
|
800482e: 681b ldr r3, [r3, #0]
|
|
8004830: f022 0202 bic.w r2, r2, #2
|
|
8004834: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the FIFO underrun flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
|
|
8004836: 687b ldr r3, [r7, #4]
|
|
8004838: 681b ldr r3, [r3, #0]
|
|
800483a: 2202 movs r2, #2
|
|
800483c: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
|
|
800483e: 687b ldr r3, [r7, #4]
|
|
8004840: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
|
|
8004844: f043 0202 orr.w r2, r3, #2
|
|
8004848: 687b ldr r3, [r7, #4]
|
|
800484a: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
800484e: 687b ldr r3, [r7, #4]
|
|
8004850: 2204 movs r2, #4
|
|
8004852: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004856: 687b ldr r3, [r7, #4]
|
|
8004858: 2200 movs r2, #0
|
|
800485a: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
800485e: 6878 ldr r0, [r7, #4]
|
|
8004860: f000 f846 bl 80048f0 <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Line Interrupt management ************************************************/
|
|
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
|
|
8004864: 68fb ldr r3, [r7, #12]
|
|
8004866: f003 0301 and.w r3, r3, #1
|
|
800486a: 2b00 cmp r3, #0
|
|
800486c: d01b beq.n 80048a6 <HAL_LTDC_IRQHandler+0xfe>
|
|
800486e: 68bb ldr r3, [r7, #8]
|
|
8004870: f003 0301 and.w r3, r3, #1
|
|
8004874: 2b00 cmp r3, #0
|
|
8004876: d016 beq.n 80048a6 <HAL_LTDC_IRQHandler+0xfe>
|
|
{
|
|
/* Disable the Line interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
|
|
8004878: 687b ldr r3, [r7, #4]
|
|
800487a: 681b ldr r3, [r3, #0]
|
|
800487c: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
800487e: 687b ldr r3, [r7, #4]
|
|
8004880: 681b ldr r3, [r3, #0]
|
|
8004882: f022 0201 bic.w r2, r2, #1
|
|
8004886: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the Line interrupt flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
|
|
8004888: 687b ldr r3, [r7, #4]
|
|
800488a: 681b ldr r3, [r3, #0]
|
|
800488c: 2201 movs r2, #1
|
|
800488e: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8004890: 687b ldr r3, [r7, #4]
|
|
8004892: 2201 movs r2, #1
|
|
8004894: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004898: 687b ldr r3, [r7, #4]
|
|
800489a: 2200 movs r2, #0
|
|
800489c: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Line Event callback */
|
|
hltdc->LineEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Line Event callback */
|
|
HAL_LTDC_LineEventCallback(hltdc);
|
|
80048a0: 6878 ldr r0, [r7, #4]
|
|
80048a2: f000 f82f bl 8004904 <HAL_LTDC_LineEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Register reload Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
|
|
80048a6: 68fb ldr r3, [r7, #12]
|
|
80048a8: f003 0308 and.w r3, r3, #8
|
|
80048ac: 2b00 cmp r3, #0
|
|
80048ae: d01b beq.n 80048e8 <HAL_LTDC_IRQHandler+0x140>
|
|
80048b0: 68bb ldr r3, [r7, #8]
|
|
80048b2: f003 0308 and.w r3, r3, #8
|
|
80048b6: 2b00 cmp r3, #0
|
|
80048b8: d016 beq.n 80048e8 <HAL_LTDC_IRQHandler+0x140>
|
|
{
|
|
/* Disable the register reload interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
|
|
80048ba: 687b ldr r3, [r7, #4]
|
|
80048bc: 681b ldr r3, [r3, #0]
|
|
80048be: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80048c0: 687b ldr r3, [r7, #4]
|
|
80048c2: 681b ldr r3, [r3, #0]
|
|
80048c4: f022 0208 bic.w r2, r2, #8
|
|
80048c8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the register reload flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
|
|
80048ca: 687b ldr r3, [r7, #4]
|
|
80048cc: 681b ldr r3, [r3, #0]
|
|
80048ce: 2208 movs r2, #8
|
|
80048d0: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
80048d2: 687b ldr r3, [r7, #4]
|
|
80048d4: 2201 movs r2, #1
|
|
80048d6: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
80048da: 687b ldr r3, [r7, #4]
|
|
80048dc: 2200 movs r2, #0
|
|
80048de: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered reload Event callback */
|
|
hltdc->ReloadEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Reload Event callback */
|
|
HAL_LTDC_ReloadEventCallback(hltdc);
|
|
80048e2: 6878 ldr r0, [r7, #4]
|
|
80048e4: f000 f818 bl 8004918 <HAL_LTDC_ReloadEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
80048e8: bf00 nop
|
|
80048ea: 3710 adds r7, #16
|
|
80048ec: 46bd mov sp, r7
|
|
80048ee: bd80 pop {r7, pc}
|
|
|
|
080048f0 <HAL_LTDC_ErrorCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
80048f0: b480 push {r7}
|
|
80048f2: b083 sub sp, #12
|
|
80048f4: af00 add r7, sp, #0
|
|
80048f6: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80048f8: bf00 nop
|
|
80048fa: 370c adds r7, #12
|
|
80048fc: 46bd mov sp, r7
|
|
80048fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004902: 4770 bx lr
|
|
|
|
08004904 <HAL_LTDC_LineEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8004904: b480 push {r7}
|
|
8004906: b083 sub sp, #12
|
|
8004908: af00 add r7, sp, #0
|
|
800490a: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_LineEventCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800490c: bf00 nop
|
|
800490e: 370c adds r7, #12
|
|
8004910: 46bd mov sp, r7
|
|
8004912: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004916: 4770 bx lr
|
|
|
|
08004918 <HAL_LTDC_ReloadEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8004918: b480 push {r7}
|
|
800491a: b083 sub sp, #12
|
|
800491c: af00 add r7, sp, #0
|
|
800491e: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004920: bf00 nop
|
|
8004922: 370c adds r7, #12
|
|
8004924: 46bd mov sp, r7
|
|
8004926: f85d 7b04 ldr.w r7, [sp], #4
|
|
800492a: 4770 bx lr
|
|
|
|
0800492c <HAL_LTDC_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
800492c: b5b0 push {r4, r5, r7, lr}
|
|
800492e: b084 sub sp, #16
|
|
8004930: af00 add r7, sp, #0
|
|
8004932: 60f8 str r0, [r7, #12]
|
|
8004934: 60b9 str r1, [r7, #8]
|
|
8004936: 607a str r2, [r7, #4]
|
|
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
|
|
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
|
|
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hltdc);
|
|
8004938: 68fb ldr r3, [r7, #12]
|
|
800493a: f893 30a0 ldrb.w r3, [r3, #160] @ 0xa0
|
|
800493e: 2b01 cmp r3, #1
|
|
8004940: d101 bne.n 8004946 <HAL_LTDC_ConfigLayer+0x1a>
|
|
8004942: 2302 movs r3, #2
|
|
8004944: e02c b.n 80049a0 <HAL_LTDC_ConfigLayer+0x74>
|
|
8004946: 68fb ldr r3, [r7, #12]
|
|
8004948: 2201 movs r2, #1
|
|
800494a: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
800494e: 68fb ldr r3, [r7, #12]
|
|
8004950: 2202 movs r2, #2
|
|
8004952: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Copy new layer configuration into handle structure */
|
|
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
|
|
8004956: 68fa ldr r2, [r7, #12]
|
|
8004958: 687b ldr r3, [r7, #4]
|
|
800495a: 2134 movs r1, #52 @ 0x34
|
|
800495c: fb01 f303 mul.w r3, r1, r3
|
|
8004960: 4413 add r3, r2
|
|
8004962: f103 0238 add.w r2, r3, #56 @ 0x38
|
|
8004966: 68bb ldr r3, [r7, #8]
|
|
8004968: 4614 mov r4, r2
|
|
800496a: 461d mov r5, r3
|
|
800496c: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800496e: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8004970: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8004972: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8004974: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
8004976: c40f stmia r4!, {r0, r1, r2, r3}
|
|
8004978: 682b ldr r3, [r5, #0]
|
|
800497a: 6023 str r3, [r4, #0]
|
|
|
|
/* Configure the LTDC Layer */
|
|
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
|
|
800497c: 687a ldr r2, [r7, #4]
|
|
800497e: 68b9 ldr r1, [r7, #8]
|
|
8004980: 68f8 ldr r0, [r7, #12]
|
|
8004982: f000 f811 bl 80049a8 <LTDC_SetConfig>
|
|
|
|
/* Set the Immediate Reload type */
|
|
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
|
|
8004986: 68fb ldr r3, [r7, #12]
|
|
8004988: 681b ldr r3, [r3, #0]
|
|
800498a: 2201 movs r2, #1
|
|
800498c: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
800498e: 68fb ldr r3, [r7, #12]
|
|
8004990: 2201 movs r2, #1
|
|
8004992: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004996: 68fb ldr r3, [r7, #12]
|
|
8004998: 2200 movs r2, #0
|
|
800499a: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
|
|
return HAL_OK;
|
|
800499e: 2300 movs r3, #0
|
|
}
|
|
80049a0: 4618 mov r0, r3
|
|
80049a2: 3710 adds r7, #16
|
|
80049a4: 46bd mov sp, r7
|
|
80049a6: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
080049a8 <LTDC_SetConfig>:
|
|
* @param LayerIdx LTDC Layer index.
|
|
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval None
|
|
*/
|
|
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
80049a8: b480 push {r7}
|
|
80049aa: b089 sub sp, #36 @ 0x24
|
|
80049ac: af00 add r7, sp, #0
|
|
80049ae: 60f8 str r0, [r7, #12]
|
|
80049b0: 60b9 str r1, [r7, #8]
|
|
80049b2: 607a str r2, [r7, #4]
|
|
uint32_t tmp;
|
|
uint32_t tmp1;
|
|
uint32_t tmp2;
|
|
|
|
/* Configure the horizontal start and stop position */
|
|
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
|
|
80049b4: 68bb ldr r3, [r7, #8]
|
|
80049b6: 685a ldr r2, [r3, #4]
|
|
80049b8: 68fb ldr r3, [r7, #12]
|
|
80049ba: 681b ldr r3, [r3, #0]
|
|
80049bc: 68db ldr r3, [r3, #12]
|
|
80049be: 0c1b lsrs r3, r3, #16
|
|
80049c0: f3c3 030b ubfx r3, r3, #0, #12
|
|
80049c4: 4413 add r3, r2
|
|
80049c6: 041b lsls r3, r3, #16
|
|
80049c8: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
|
|
80049ca: 68fb ldr r3, [r7, #12]
|
|
80049cc: 681b ldr r3, [r3, #0]
|
|
80049ce: 461a mov r2, r3
|
|
80049d0: 687b ldr r3, [r7, #4]
|
|
80049d2: 01db lsls r3, r3, #7
|
|
80049d4: 4413 add r3, r2
|
|
80049d6: 3384 adds r3, #132 @ 0x84
|
|
80049d8: 685b ldr r3, [r3, #4]
|
|
80049da: 68fa ldr r2, [r7, #12]
|
|
80049dc: 6812 ldr r2, [r2, #0]
|
|
80049de: 4611 mov r1, r2
|
|
80049e0: 687a ldr r2, [r7, #4]
|
|
80049e2: 01d2 lsls r2, r2, #7
|
|
80049e4: 440a add r2, r1
|
|
80049e6: 3284 adds r2, #132 @ 0x84
|
|
80049e8: f403 4370 and.w r3, r3, #61440 @ 0xf000
|
|
80049ec: 6053 str r3, [r2, #4]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
80049ee: 68bb ldr r3, [r7, #8]
|
|
80049f0: 681a ldr r2, [r3, #0]
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
80049f2: 68fb ldr r3, [r7, #12]
|
|
80049f4: 681b ldr r3, [r3, #0]
|
|
80049f6: 68db ldr r3, [r3, #12]
|
|
80049f8: 0c1b lsrs r3, r3, #16
|
|
80049fa: f3c3 030b ubfx r3, r3, #0, #12
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
80049fe: 4413 add r3, r2
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
8004a00: 1c5a adds r2, r3, #1
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
8004a02: 68fb ldr r3, [r7, #12]
|
|
8004a04: 681b ldr r3, [r3, #0]
|
|
8004a06: 4619 mov r1, r3
|
|
8004a08: 687b ldr r3, [r7, #4]
|
|
8004a0a: 01db lsls r3, r3, #7
|
|
8004a0c: 440b add r3, r1
|
|
8004a0e: 3384 adds r3, #132 @ 0x84
|
|
8004a10: 4619 mov r1, r3
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
8004a12: 69fb ldr r3, [r7, #28]
|
|
8004a14: 4313 orrs r3, r2
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
8004a16: 604b str r3, [r1, #4]
|
|
|
|
/* Configure the vertical start and stop position */
|
|
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
|
|
8004a18: 68bb ldr r3, [r7, #8]
|
|
8004a1a: 68da ldr r2, [r3, #12]
|
|
8004a1c: 68fb ldr r3, [r7, #12]
|
|
8004a1e: 681b ldr r3, [r3, #0]
|
|
8004a20: 68db ldr r3, [r3, #12]
|
|
8004a22: f3c3 030a ubfx r3, r3, #0, #11
|
|
8004a26: 4413 add r3, r2
|
|
8004a28: 041b lsls r3, r3, #16
|
|
8004a2a: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
|
|
8004a2c: 68fb ldr r3, [r7, #12]
|
|
8004a2e: 681b ldr r3, [r3, #0]
|
|
8004a30: 461a mov r2, r3
|
|
8004a32: 687b ldr r3, [r7, #4]
|
|
8004a34: 01db lsls r3, r3, #7
|
|
8004a36: 4413 add r3, r2
|
|
8004a38: 3384 adds r3, #132 @ 0x84
|
|
8004a3a: 689b ldr r3, [r3, #8]
|
|
8004a3c: 68fa ldr r2, [r7, #12]
|
|
8004a3e: 6812 ldr r2, [r2, #0]
|
|
8004a40: 4611 mov r1, r2
|
|
8004a42: 687a ldr r2, [r7, #4]
|
|
8004a44: 01d2 lsls r2, r2, #7
|
|
8004a46: 440a add r2, r1
|
|
8004a48: 3284 adds r2, #132 @ 0x84
|
|
8004a4a: f403 4370 and.w r3, r3, #61440 @ 0xf000
|
|
8004a4e: 6093 str r3, [r2, #8]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
|
|
8004a50: 68bb ldr r3, [r7, #8]
|
|
8004a52: 689a ldr r2, [r3, #8]
|
|
8004a54: 68fb ldr r3, [r7, #12]
|
|
8004a56: 681b ldr r3, [r3, #0]
|
|
8004a58: 68db ldr r3, [r3, #12]
|
|
8004a5a: f3c3 030a ubfx r3, r3, #0, #11
|
|
8004a5e: 4413 add r3, r2
|
|
8004a60: 1c5a adds r2, r3, #1
|
|
8004a62: 68fb ldr r3, [r7, #12]
|
|
8004a64: 681b ldr r3, [r3, #0]
|
|
8004a66: 4619 mov r1, r3
|
|
8004a68: 687b ldr r3, [r7, #4]
|
|
8004a6a: 01db lsls r3, r3, #7
|
|
8004a6c: 440b add r3, r1
|
|
8004a6e: 3384 adds r3, #132 @ 0x84
|
|
8004a70: 4619 mov r1, r3
|
|
8004a72: 69fb ldr r3, [r7, #28]
|
|
8004a74: 4313 orrs r3, r2
|
|
8004a76: 608b str r3, [r1, #8]
|
|
|
|
/* Specifies the pixel format */
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
|
|
8004a78: 68fb ldr r3, [r7, #12]
|
|
8004a7a: 681b ldr r3, [r3, #0]
|
|
8004a7c: 461a mov r2, r3
|
|
8004a7e: 687b ldr r3, [r7, #4]
|
|
8004a80: 01db lsls r3, r3, #7
|
|
8004a82: 4413 add r3, r2
|
|
8004a84: 3384 adds r3, #132 @ 0x84
|
|
8004a86: 691b ldr r3, [r3, #16]
|
|
8004a88: 68fa ldr r2, [r7, #12]
|
|
8004a8a: 6812 ldr r2, [r2, #0]
|
|
8004a8c: 4611 mov r1, r2
|
|
8004a8e: 687a ldr r2, [r7, #4]
|
|
8004a90: 01d2 lsls r2, r2, #7
|
|
8004a92: 440a add r2, r1
|
|
8004a94: 3284 adds r2, #132 @ 0x84
|
|
8004a96: f023 0307 bic.w r3, r3, #7
|
|
8004a9a: 6113 str r3, [r2, #16]
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
|
|
8004a9c: 68fb ldr r3, [r7, #12]
|
|
8004a9e: 681b ldr r3, [r3, #0]
|
|
8004aa0: 461a mov r2, r3
|
|
8004aa2: 687b ldr r3, [r7, #4]
|
|
8004aa4: 01db lsls r3, r3, #7
|
|
8004aa6: 4413 add r3, r2
|
|
8004aa8: 3384 adds r3, #132 @ 0x84
|
|
8004aaa: 461a mov r2, r3
|
|
8004aac: 68bb ldr r3, [r7, #8]
|
|
8004aae: 691b ldr r3, [r3, #16]
|
|
8004ab0: 6113 str r3, [r2, #16]
|
|
|
|
/* Configure the default color values */
|
|
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
|
|
8004ab2: 68bb ldr r3, [r7, #8]
|
|
8004ab4: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
8004ab8: 021b lsls r3, r3, #8
|
|
8004aba: 61fb str r3, [r7, #28]
|
|
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
|
|
8004abc: 68bb ldr r3, [r7, #8]
|
|
8004abe: f893 3032 ldrb.w r3, [r3, #50] @ 0x32
|
|
8004ac2: 041b lsls r3, r3, #16
|
|
8004ac4: 61bb str r3, [r7, #24]
|
|
tmp2 = (pLayerCfg->Alpha0 << 24U);
|
|
8004ac6: 68bb ldr r3, [r7, #8]
|
|
8004ac8: 699b ldr r3, [r3, #24]
|
|
8004aca: 061b lsls r3, r3, #24
|
|
8004acc: 617b str r3, [r7, #20]
|
|
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2));
|
|
8004ace: 68bb ldr r3, [r7, #8]
|
|
8004ad0: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
8004ad4: 461a mov r2, r3
|
|
8004ad6: 69fb ldr r3, [r7, #28]
|
|
8004ad8: 431a orrs r2, r3
|
|
8004ada: 69bb ldr r3, [r7, #24]
|
|
8004adc: 431a orrs r2, r3
|
|
8004ade: 68fb ldr r3, [r7, #12]
|
|
8004ae0: 681b ldr r3, [r3, #0]
|
|
8004ae2: 4619 mov r1, r3
|
|
8004ae4: 687b ldr r3, [r7, #4]
|
|
8004ae6: 01db lsls r3, r3, #7
|
|
8004ae8: 440b add r3, r1
|
|
8004aea: 3384 adds r3, #132 @ 0x84
|
|
8004aec: 4619 mov r1, r3
|
|
8004aee: 697b ldr r3, [r7, #20]
|
|
8004af0: 4313 orrs r3, r2
|
|
8004af2: 618b str r3, [r1, #24]
|
|
|
|
/* Specifies the constant alpha value */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
|
|
8004af4: 68fb ldr r3, [r7, #12]
|
|
8004af6: 681b ldr r3, [r3, #0]
|
|
8004af8: 461a mov r2, r3
|
|
8004afa: 687b ldr r3, [r7, #4]
|
|
8004afc: 01db lsls r3, r3, #7
|
|
8004afe: 4413 add r3, r2
|
|
8004b00: 3384 adds r3, #132 @ 0x84
|
|
8004b02: 695b ldr r3, [r3, #20]
|
|
8004b04: 68fa ldr r2, [r7, #12]
|
|
8004b06: 6812 ldr r2, [r2, #0]
|
|
8004b08: 4611 mov r1, r2
|
|
8004b0a: 687a ldr r2, [r7, #4]
|
|
8004b0c: 01d2 lsls r2, r2, #7
|
|
8004b0e: 440a add r2, r1
|
|
8004b10: 3284 adds r2, #132 @ 0x84
|
|
8004b12: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8004b16: 6153 str r3, [r2, #20]
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
|
|
8004b18: 68fb ldr r3, [r7, #12]
|
|
8004b1a: 681b ldr r3, [r3, #0]
|
|
8004b1c: 461a mov r2, r3
|
|
8004b1e: 687b ldr r3, [r7, #4]
|
|
8004b20: 01db lsls r3, r3, #7
|
|
8004b22: 4413 add r3, r2
|
|
8004b24: 3384 adds r3, #132 @ 0x84
|
|
8004b26: 461a mov r2, r3
|
|
8004b28: 68bb ldr r3, [r7, #8]
|
|
8004b2a: 695b ldr r3, [r3, #20]
|
|
8004b2c: 6153 str r3, [r2, #20]
|
|
|
|
/* Specifies the blending factors */
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
|
|
8004b2e: 68fb ldr r3, [r7, #12]
|
|
8004b30: 681b ldr r3, [r3, #0]
|
|
8004b32: 461a mov r2, r3
|
|
8004b34: 687b ldr r3, [r7, #4]
|
|
8004b36: 01db lsls r3, r3, #7
|
|
8004b38: 4413 add r3, r2
|
|
8004b3a: 3384 adds r3, #132 @ 0x84
|
|
8004b3c: 69db ldr r3, [r3, #28]
|
|
8004b3e: 68fa ldr r2, [r7, #12]
|
|
8004b40: 6812 ldr r2, [r2, #0]
|
|
8004b42: 4611 mov r1, r2
|
|
8004b44: 687a ldr r2, [r7, #4]
|
|
8004b46: 01d2 lsls r2, r2, #7
|
|
8004b48: 440a add r2, r1
|
|
8004b4a: 3284 adds r2, #132 @ 0x84
|
|
8004b4c: f423 63e0 bic.w r3, r3, #1792 @ 0x700
|
|
8004b50: f023 0307 bic.w r3, r3, #7
|
|
8004b54: 61d3 str r3, [r2, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
|
|
8004b56: 68bb ldr r3, [r7, #8]
|
|
8004b58: 69da ldr r2, [r3, #28]
|
|
8004b5a: 68bb ldr r3, [r7, #8]
|
|
8004b5c: 6a1b ldr r3, [r3, #32]
|
|
8004b5e: 68f9 ldr r1, [r7, #12]
|
|
8004b60: 6809 ldr r1, [r1, #0]
|
|
8004b62: 4608 mov r0, r1
|
|
8004b64: 6879 ldr r1, [r7, #4]
|
|
8004b66: 01c9 lsls r1, r1, #7
|
|
8004b68: 4401 add r1, r0
|
|
8004b6a: 3184 adds r1, #132 @ 0x84
|
|
8004b6c: 4313 orrs r3, r2
|
|
8004b6e: 61cb str r3, [r1, #28]
|
|
|
|
/* Configure the color frame buffer start address */
|
|
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress);
|
|
8004b70: 68fb ldr r3, [r7, #12]
|
|
8004b72: 681b ldr r3, [r3, #0]
|
|
8004b74: 461a mov r2, r3
|
|
8004b76: 687b ldr r3, [r7, #4]
|
|
8004b78: 01db lsls r3, r3, #7
|
|
8004b7a: 4413 add r3, r2
|
|
8004b7c: 3384 adds r3, #132 @ 0x84
|
|
8004b7e: 461a mov r2, r3
|
|
8004b80: 68bb ldr r3, [r7, #8]
|
|
8004b82: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004b84: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
|
|
8004b86: 68bb ldr r3, [r7, #8]
|
|
8004b88: 691b ldr r3, [r3, #16]
|
|
8004b8a: 2b00 cmp r3, #0
|
|
8004b8c: d102 bne.n 8004b94 <LTDC_SetConfig+0x1ec>
|
|
{
|
|
tmp = 4U;
|
|
8004b8e: 2304 movs r3, #4
|
|
8004b90: 61fb str r3, [r7, #28]
|
|
8004b92: e01b b.n 8004bcc <LTDC_SetConfig+0x224>
|
|
}
|
|
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
|
|
8004b94: 68bb ldr r3, [r7, #8]
|
|
8004b96: 691b ldr r3, [r3, #16]
|
|
8004b98: 2b01 cmp r3, #1
|
|
8004b9a: d102 bne.n 8004ba2 <LTDC_SetConfig+0x1fa>
|
|
{
|
|
tmp = 3U;
|
|
8004b9c: 2303 movs r3, #3
|
|
8004b9e: 61fb str r3, [r7, #28]
|
|
8004ba0: e014 b.n 8004bcc <LTDC_SetConfig+0x224>
|
|
}
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
8004ba2: 68bb ldr r3, [r7, #8]
|
|
8004ba4: 691b ldr r3, [r3, #16]
|
|
8004ba6: 2b04 cmp r3, #4
|
|
8004ba8: d00b beq.n 8004bc2 <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
8004baa: 68bb ldr r3, [r7, #8]
|
|
8004bac: 691b ldr r3, [r3, #16]
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
8004bae: 2b02 cmp r3, #2
|
|
8004bb0: d007 beq.n 8004bc2 <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
8004bb2: 68bb ldr r3, [r7, #8]
|
|
8004bb4: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
8004bb6: 2b03 cmp r3, #3
|
|
8004bb8: d003 beq.n 8004bc2 <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
|
|
8004bba: 68bb ldr r3, [r7, #8]
|
|
8004bbc: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
8004bbe: 2b07 cmp r3, #7
|
|
8004bc0: d102 bne.n 8004bc8 <LTDC_SetConfig+0x220>
|
|
{
|
|
tmp = 2U;
|
|
8004bc2: 2302 movs r3, #2
|
|
8004bc4: 61fb str r3, [r7, #28]
|
|
8004bc6: e001 b.n 8004bcc <LTDC_SetConfig+0x224>
|
|
}
|
|
else
|
|
{
|
|
tmp = 1U;
|
|
8004bc8: 2301 movs r3, #1
|
|
8004bca: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Configure the color frame buffer pitch in byte */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
|
|
8004bcc: 68fb ldr r3, [r7, #12]
|
|
8004bce: 681b ldr r3, [r3, #0]
|
|
8004bd0: 461a mov r2, r3
|
|
8004bd2: 687b ldr r3, [r7, #4]
|
|
8004bd4: 01db lsls r3, r3, #7
|
|
8004bd6: 4413 add r3, r2
|
|
8004bd8: 3384 adds r3, #132 @ 0x84
|
|
8004bda: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004bdc: 68fa ldr r2, [r7, #12]
|
|
8004bde: 6812 ldr r2, [r2, #0]
|
|
8004be0: 4611 mov r1, r2
|
|
8004be2: 687a ldr r2, [r7, #4]
|
|
8004be4: 01d2 lsls r2, r2, #7
|
|
8004be6: 440a add r2, r1
|
|
8004be8: 3284 adds r2, #132 @ 0x84
|
|
8004bea: f003 23e0 and.w r3, r3, #3758153728 @ 0xe000e000
|
|
8004bee: 62d3 str r3, [r2, #44] @ 0x2c
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
|
|
8004bf0: 68bb ldr r3, [r7, #8]
|
|
8004bf2: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004bf4: 69fa ldr r2, [r7, #28]
|
|
8004bf6: fb02 f303 mul.w r3, r2, r3
|
|
8004bfa: 041a lsls r2, r3, #16
|
|
(((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
|
|
8004bfc: 68bb ldr r3, [r7, #8]
|
|
8004bfe: 6859 ldr r1, [r3, #4]
|
|
8004c00: 68bb ldr r3, [r7, #8]
|
|
8004c02: 681b ldr r3, [r3, #0]
|
|
8004c04: 1acb subs r3, r1, r3
|
|
8004c06: 69f9 ldr r1, [r7, #28]
|
|
8004c08: fb01 f303 mul.w r3, r1, r3
|
|
8004c0c: 3303 adds r3, #3
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
|
|
8004c0e: 68f9 ldr r1, [r7, #12]
|
|
8004c10: 6809 ldr r1, [r1, #0]
|
|
8004c12: 4608 mov r0, r1
|
|
8004c14: 6879 ldr r1, [r7, #4]
|
|
8004c16: 01c9 lsls r1, r1, #7
|
|
8004c18: 4401 add r1, r0
|
|
8004c1a: 3184 adds r1, #132 @ 0x84
|
|
8004c1c: 4313 orrs r3, r2
|
|
8004c1e: 62cb str r3, [r1, #44] @ 0x2c
|
|
/* Configure the frame buffer line number */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
|
|
8004c20: 68fb ldr r3, [r7, #12]
|
|
8004c22: 681b ldr r3, [r3, #0]
|
|
8004c24: 461a mov r2, r3
|
|
8004c26: 687b ldr r3, [r7, #4]
|
|
8004c28: 01db lsls r3, r3, #7
|
|
8004c2a: 4413 add r3, r2
|
|
8004c2c: 3384 adds r3, #132 @ 0x84
|
|
8004c2e: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8004c30: 68fa ldr r2, [r7, #12]
|
|
8004c32: 6812 ldr r2, [r2, #0]
|
|
8004c34: 4611 mov r1, r2
|
|
8004c36: 687a ldr r2, [r7, #4]
|
|
8004c38: 01d2 lsls r2, r2, #7
|
|
8004c3a: 440a add r2, r1
|
|
8004c3c: 3284 adds r2, #132 @ 0x84
|
|
8004c3e: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
8004c42: f023 0307 bic.w r3, r3, #7
|
|
8004c46: 6313 str r3, [r2, #48] @ 0x30
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
|
|
8004c48: 68fb ldr r3, [r7, #12]
|
|
8004c4a: 681b ldr r3, [r3, #0]
|
|
8004c4c: 461a mov r2, r3
|
|
8004c4e: 687b ldr r3, [r7, #4]
|
|
8004c50: 01db lsls r3, r3, #7
|
|
8004c52: 4413 add r3, r2
|
|
8004c54: 3384 adds r3, #132 @ 0x84
|
|
8004c56: 461a mov r2, r3
|
|
8004c58: 68bb ldr r3, [r7, #8]
|
|
8004c5a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004c5c: 6313 str r3, [r2, #48] @ 0x30
|
|
|
|
/* Enable LTDC_Layer by setting LEN bit */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
|
|
8004c5e: 68fb ldr r3, [r7, #12]
|
|
8004c60: 681b ldr r3, [r3, #0]
|
|
8004c62: 461a mov r2, r3
|
|
8004c64: 687b ldr r3, [r7, #4]
|
|
8004c66: 01db lsls r3, r3, #7
|
|
8004c68: 4413 add r3, r2
|
|
8004c6a: 3384 adds r3, #132 @ 0x84
|
|
8004c6c: 681b ldr r3, [r3, #0]
|
|
8004c6e: 68fa ldr r2, [r7, #12]
|
|
8004c70: 6812 ldr r2, [r2, #0]
|
|
8004c72: 4611 mov r1, r2
|
|
8004c74: 687a ldr r2, [r7, #4]
|
|
8004c76: 01d2 lsls r2, r2, #7
|
|
8004c78: 440a add r2, r1
|
|
8004c7a: 3284 adds r2, #132 @ 0x84
|
|
8004c7c: f043 0301 orr.w r3, r3, #1
|
|
8004c80: 6013 str r3, [r2, #0]
|
|
}
|
|
8004c82: bf00 nop
|
|
8004c84: 3724 adds r7, #36 @ 0x24
|
|
8004c86: 46bd mov sp, r7
|
|
8004c88: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004c8c: 4770 bx lr
|
|
...
|
|
|
|
08004c90 <HAL_RCC_OscConfig>:
|
|
* supported by this API. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8004c90: b580 push {r7, lr}
|
|
8004c92: b086 sub sp, #24
|
|
8004c94: af00 add r7, sp, #0
|
|
8004c96: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8004c98: 687b ldr r3, [r7, #4]
|
|
8004c9a: 2b00 cmp r3, #0
|
|
8004c9c: d101 bne.n 8004ca2 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004c9e: 2301 movs r3, #1
|
|
8004ca0: e267 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8004ca2: 687b ldr r3, [r7, #4]
|
|
8004ca4: 681b ldr r3, [r3, #0]
|
|
8004ca6: f003 0301 and.w r3, r3, #1
|
|
8004caa: 2b00 cmp r3, #0
|
|
8004cac: d075 beq.n 8004d9a <HAL_RCC_OscConfig+0x10a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
|
|
8004cae: 4b88 ldr r3, [pc, #544] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cb0: 689b ldr r3, [r3, #8]
|
|
8004cb2: f003 030c and.w r3, r3, #12
|
|
8004cb6: 2b04 cmp r3, #4
|
|
8004cb8: d00c beq.n 8004cd4 <HAL_RCC_OscConfig+0x44>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004cba: 4b85 ldr r3, [pc, #532] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cbc: 689b ldr r3, [r3, #8]
|
|
8004cbe: f003 030c and.w r3, r3, #12
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
|
|
8004cc2: 2b08 cmp r3, #8
|
|
8004cc4: d112 bne.n 8004cec <HAL_RCC_OscConfig+0x5c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
8004cc6: 4b82 ldr r3, [pc, #520] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cc8: 685b ldr r3, [r3, #4]
|
|
8004cca: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004cce: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
8004cd2: d10b bne.n 8004cec <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004cd4: 4b7e ldr r3, [pc, #504] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cd6: 681b ldr r3, [r3, #0]
|
|
8004cd8: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004cdc: 2b00 cmp r3, #0
|
|
8004cde: d05b beq.n 8004d98 <HAL_RCC_OscConfig+0x108>
|
|
8004ce0: 687b ldr r3, [r7, #4]
|
|
8004ce2: 685b ldr r3, [r3, #4]
|
|
8004ce4: 2b00 cmp r3, #0
|
|
8004ce6: d157 bne.n 8004d98 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_ERROR;
|
|
8004ce8: 2301 movs r3, #1
|
|
8004cea: e242 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004cec: 687b ldr r3, [r7, #4]
|
|
8004cee: 685b ldr r3, [r3, #4]
|
|
8004cf0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004cf4: d106 bne.n 8004d04 <HAL_RCC_OscConfig+0x74>
|
|
8004cf6: 4b76 ldr r3, [pc, #472] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cf8: 681b ldr r3, [r3, #0]
|
|
8004cfa: 4a75 ldr r2, [pc, #468] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004cfc: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004d00: 6013 str r3, [r2, #0]
|
|
8004d02: e01d b.n 8004d40 <HAL_RCC_OscConfig+0xb0>
|
|
8004d04: 687b ldr r3, [r7, #4]
|
|
8004d06: 685b ldr r3, [r3, #4]
|
|
8004d08: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004d0c: d10c bne.n 8004d28 <HAL_RCC_OscConfig+0x98>
|
|
8004d0e: 4b70 ldr r3, [pc, #448] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d10: 681b ldr r3, [r3, #0]
|
|
8004d12: 4a6f ldr r2, [pc, #444] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d14: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004d18: 6013 str r3, [r2, #0]
|
|
8004d1a: 4b6d ldr r3, [pc, #436] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d1c: 681b ldr r3, [r3, #0]
|
|
8004d1e: 4a6c ldr r2, [pc, #432] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d20: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004d24: 6013 str r3, [r2, #0]
|
|
8004d26: e00b b.n 8004d40 <HAL_RCC_OscConfig+0xb0>
|
|
8004d28: 4b69 ldr r3, [pc, #420] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d2a: 681b ldr r3, [r3, #0]
|
|
8004d2c: 4a68 ldr r2, [pc, #416] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d2e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004d32: 6013 str r3, [r2, #0]
|
|
8004d34: 4b66 ldr r3, [pc, #408] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d36: 681b ldr r3, [r3, #0]
|
|
8004d38: 4a65 ldr r2, [pc, #404] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d3a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8004d3e: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
8004d40: 687b ldr r3, [r7, #4]
|
|
8004d42: 685b ldr r3, [r3, #4]
|
|
8004d44: 2b00 cmp r3, #0
|
|
8004d46: d013 beq.n 8004d70 <HAL_RCC_OscConfig+0xe0>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004d48: f7fc fcc8 bl 80016dc <HAL_GetTick>
|
|
8004d4c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d4e: e008 b.n 8004d62 <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004d50: f7fc fcc4 bl 80016dc <HAL_GetTick>
|
|
8004d54: 4602 mov r2, r0
|
|
8004d56: 693b ldr r3, [r7, #16]
|
|
8004d58: 1ad3 subs r3, r2, r3
|
|
8004d5a: 2b64 cmp r3, #100 @ 0x64
|
|
8004d5c: d901 bls.n 8004d62 <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004d5e: 2303 movs r3, #3
|
|
8004d60: e207 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004d62: 4b5b ldr r3, [pc, #364] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d64: 681b ldr r3, [r3, #0]
|
|
8004d66: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004d6a: 2b00 cmp r3, #0
|
|
8004d6c: d0f0 beq.n 8004d50 <HAL_RCC_OscConfig+0xc0>
|
|
8004d6e: e014 b.n 8004d9a <HAL_RCC_OscConfig+0x10a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004d70: f7fc fcb4 bl 80016dc <HAL_GetTick>
|
|
8004d74: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004d76: e008 b.n 8004d8a <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8004d78: f7fc fcb0 bl 80016dc <HAL_GetTick>
|
|
8004d7c: 4602 mov r2, r0
|
|
8004d7e: 693b ldr r3, [r7, #16]
|
|
8004d80: 1ad3 subs r3, r2, r3
|
|
8004d82: 2b64 cmp r3, #100 @ 0x64
|
|
8004d84: d901 bls.n 8004d8a <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004d86: 2303 movs r3, #3
|
|
8004d88: e1f3 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
8004d8a: 4b51 ldr r3, [pc, #324] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004d8c: 681b ldr r3, [r3, #0]
|
|
8004d8e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004d92: 2b00 cmp r3, #0
|
|
8004d94: d1f0 bne.n 8004d78 <HAL_RCC_OscConfig+0xe8>
|
|
8004d96: e000 b.n 8004d9a <HAL_RCC_OscConfig+0x10a>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004d98: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8004d9a: 687b ldr r3, [r7, #4]
|
|
8004d9c: 681b ldr r3, [r3, #0]
|
|
8004d9e: f003 0302 and.w r3, r3, #2
|
|
8004da2: 2b00 cmp r3, #0
|
|
8004da4: d063 beq.n 8004e6e <HAL_RCC_OscConfig+0x1de>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
|
|
8004da6: 4b4a ldr r3, [pc, #296] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004da8: 689b ldr r3, [r3, #8]
|
|
8004daa: f003 030c and.w r3, r3, #12
|
|
8004dae: 2b00 cmp r3, #0
|
|
8004db0: d00b beq.n 8004dca <HAL_RCC_OscConfig+0x13a>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004db2: 4b47 ldr r3, [pc, #284] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004db4: 689b ldr r3, [r3, #8]
|
|
8004db6: f003 030c and.w r3, r3, #12
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
|
|
8004dba: 2b08 cmp r3, #8
|
|
8004dbc: d11c bne.n 8004df8 <HAL_RCC_OscConfig+0x168>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
8004dbe: 4b44 ldr r3, [pc, #272] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004dc0: 685b ldr r3, [r3, #4]
|
|
8004dc2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004dc6: 2b00 cmp r3, #0
|
|
8004dc8: d116 bne.n 8004df8 <HAL_RCC_OscConfig+0x168>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004dca: 4b41 ldr r3, [pc, #260] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004dcc: 681b ldr r3, [r3, #0]
|
|
8004dce: f003 0302 and.w r3, r3, #2
|
|
8004dd2: 2b00 cmp r3, #0
|
|
8004dd4: d005 beq.n 8004de2 <HAL_RCC_OscConfig+0x152>
|
|
8004dd6: 687b ldr r3, [r7, #4]
|
|
8004dd8: 68db ldr r3, [r3, #12]
|
|
8004dda: 2b01 cmp r3, #1
|
|
8004ddc: d001 beq.n 8004de2 <HAL_RCC_OscConfig+0x152>
|
|
{
|
|
return HAL_ERROR;
|
|
8004dde: 2301 movs r3, #1
|
|
8004de0: e1c7 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004de2: 4b3b ldr r3, [pc, #236] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004de4: 681b ldr r3, [r3, #0]
|
|
8004de6: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004dea: 687b ldr r3, [r7, #4]
|
|
8004dec: 691b ldr r3, [r3, #16]
|
|
8004dee: 00db lsls r3, r3, #3
|
|
8004df0: 4937 ldr r1, [pc, #220] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004df2: 4313 orrs r3, r2
|
|
8004df4: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004df6: e03a b.n 8004e6e <HAL_RCC_OscConfig+0x1de>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8004df8: 687b ldr r3, [r7, #4]
|
|
8004dfa: 68db ldr r3, [r3, #12]
|
|
8004dfc: 2b00 cmp r3, #0
|
|
8004dfe: d020 beq.n 8004e42 <HAL_RCC_OscConfig+0x1b2>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8004e00: 4b34 ldr r3, [pc, #208] @ (8004ed4 <HAL_RCC_OscConfig+0x244>)
|
|
8004e02: 2201 movs r2, #1
|
|
8004e04: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004e06: f7fc fc69 bl 80016dc <HAL_GetTick>
|
|
8004e0a: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004e0c: e008 b.n 8004e20 <HAL_RCC_OscConfig+0x190>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004e0e: f7fc fc65 bl 80016dc <HAL_GetTick>
|
|
8004e12: 4602 mov r2, r0
|
|
8004e14: 693b ldr r3, [r7, #16]
|
|
8004e16: 1ad3 subs r3, r2, r3
|
|
8004e18: 2b02 cmp r3, #2
|
|
8004e1a: d901 bls.n 8004e20 <HAL_RCC_OscConfig+0x190>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e1c: 2303 movs r3, #3
|
|
8004e1e: e1a8 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004e20: 4b2b ldr r3, [pc, #172] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004e22: 681b ldr r3, [r3, #0]
|
|
8004e24: f003 0302 and.w r3, r3, #2
|
|
8004e28: 2b00 cmp r3, #0
|
|
8004e2a: d0f0 beq.n 8004e0e <HAL_RCC_OscConfig+0x17e>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004e2c: 4b28 ldr r3, [pc, #160] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004e2e: 681b ldr r3, [r3, #0]
|
|
8004e30: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004e34: 687b ldr r3, [r7, #4]
|
|
8004e36: 691b ldr r3, [r3, #16]
|
|
8004e38: 00db lsls r3, r3, #3
|
|
8004e3a: 4925 ldr r1, [pc, #148] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004e3c: 4313 orrs r3, r2
|
|
8004e3e: 600b str r3, [r1, #0]
|
|
8004e40: e015 b.n 8004e6e <HAL_RCC_OscConfig+0x1de>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8004e42: 4b24 ldr r3, [pc, #144] @ (8004ed4 <HAL_RCC_OscConfig+0x244>)
|
|
8004e44: 2200 movs r2, #0
|
|
8004e46: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004e48: f7fc fc48 bl 80016dc <HAL_GetTick>
|
|
8004e4c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004e4e: e008 b.n 8004e62 <HAL_RCC_OscConfig+0x1d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8004e50: f7fc fc44 bl 80016dc <HAL_GetTick>
|
|
8004e54: 4602 mov r2, r0
|
|
8004e56: 693b ldr r3, [r7, #16]
|
|
8004e58: 1ad3 subs r3, r2, r3
|
|
8004e5a: 2b02 cmp r3, #2
|
|
8004e5c: d901 bls.n 8004e62 <HAL_RCC_OscConfig+0x1d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e5e: 2303 movs r3, #3
|
|
8004e60: e187 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
8004e62: 4b1b ldr r3, [pc, #108] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004e64: 681b ldr r3, [r3, #0]
|
|
8004e66: f003 0302 and.w r3, r3, #2
|
|
8004e6a: 2b00 cmp r3, #0
|
|
8004e6c: d1f0 bne.n 8004e50 <HAL_RCC_OscConfig+0x1c0>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8004e6e: 687b ldr r3, [r7, #4]
|
|
8004e70: 681b ldr r3, [r3, #0]
|
|
8004e72: f003 0308 and.w r3, r3, #8
|
|
8004e76: 2b00 cmp r3, #0
|
|
8004e78: d036 beq.n 8004ee8 <HAL_RCC_OscConfig+0x258>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
8004e7a: 687b ldr r3, [r7, #4]
|
|
8004e7c: 695b ldr r3, [r3, #20]
|
|
8004e7e: 2b00 cmp r3, #0
|
|
8004e80: d016 beq.n 8004eb0 <HAL_RCC_OscConfig+0x220>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8004e82: 4b15 ldr r3, [pc, #84] @ (8004ed8 <HAL_RCC_OscConfig+0x248>)
|
|
8004e84: 2201 movs r2, #1
|
|
8004e86: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004e88: f7fc fc28 bl 80016dc <HAL_GetTick>
|
|
8004e8c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004e8e: e008 b.n 8004ea2 <HAL_RCC_OscConfig+0x212>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004e90: f7fc fc24 bl 80016dc <HAL_GetTick>
|
|
8004e94: 4602 mov r2, r0
|
|
8004e96: 693b ldr r3, [r7, #16]
|
|
8004e98: 1ad3 subs r3, r2, r3
|
|
8004e9a: 2b02 cmp r3, #2
|
|
8004e9c: d901 bls.n 8004ea2 <HAL_RCC_OscConfig+0x212>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004e9e: 2303 movs r3, #3
|
|
8004ea0: e167 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
8004ea2: 4b0b ldr r3, [pc, #44] @ (8004ed0 <HAL_RCC_OscConfig+0x240>)
|
|
8004ea4: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004ea6: f003 0302 and.w r3, r3, #2
|
|
8004eaa: 2b00 cmp r3, #0
|
|
8004eac: d0f0 beq.n 8004e90 <HAL_RCC_OscConfig+0x200>
|
|
8004eae: e01b b.n 8004ee8 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8004eb0: 4b09 ldr r3, [pc, #36] @ (8004ed8 <HAL_RCC_OscConfig+0x248>)
|
|
8004eb2: 2200 movs r2, #0
|
|
8004eb4: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004eb6: f7fc fc11 bl 80016dc <HAL_GetTick>
|
|
8004eba: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004ebc: e00e b.n 8004edc <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8004ebe: f7fc fc0d bl 80016dc <HAL_GetTick>
|
|
8004ec2: 4602 mov r2, r0
|
|
8004ec4: 693b ldr r3, [r7, #16]
|
|
8004ec6: 1ad3 subs r3, r2, r3
|
|
8004ec8: 2b02 cmp r3, #2
|
|
8004eca: d907 bls.n 8004edc <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004ecc: 2303 movs r3, #3
|
|
8004ece: e150 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
8004ed0: 40023800 .word 0x40023800
|
|
8004ed4: 42470000 .word 0x42470000
|
|
8004ed8: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004edc: 4b88 ldr r3, [pc, #544] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004ede: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004ee0: f003 0302 and.w r3, r3, #2
|
|
8004ee4: 2b00 cmp r3, #0
|
|
8004ee6: d1ea bne.n 8004ebe <HAL_RCC_OscConfig+0x22e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8004ee8: 687b ldr r3, [r7, #4]
|
|
8004eea: 681b ldr r3, [r3, #0]
|
|
8004eec: f003 0304 and.w r3, r3, #4
|
|
8004ef0: 2b00 cmp r3, #0
|
|
8004ef2: f000 8097 beq.w 8005024 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8004ef6: 2300 movs r3, #0
|
|
8004ef8: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004efa: 4b81 ldr r3, [pc, #516] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004efc: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004efe: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004f02: 2b00 cmp r3, #0
|
|
8004f04: d10f bne.n 8004f26 <HAL_RCC_OscConfig+0x296>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004f06: 2300 movs r3, #0
|
|
8004f08: 60bb str r3, [r7, #8]
|
|
8004f0a: 4b7d ldr r3, [pc, #500] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f0c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004f0e: 4a7c ldr r2, [pc, #496] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f10: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004f14: 6413 str r3, [r2, #64] @ 0x40
|
|
8004f16: 4b7a ldr r3, [pc, #488] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f18: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004f1a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8004f1e: 60bb str r3, [r7, #8]
|
|
8004f20: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8004f22: 2301 movs r3, #1
|
|
8004f24: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004f26: 4b77 ldr r3, [pc, #476] @ (8005104 <HAL_RCC_OscConfig+0x474>)
|
|
8004f28: 681b ldr r3, [r3, #0]
|
|
8004f2a: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004f2e: 2b00 cmp r3, #0
|
|
8004f30: d118 bne.n 8004f64 <HAL_RCC_OscConfig+0x2d4>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
8004f32: 4b74 ldr r3, [pc, #464] @ (8005104 <HAL_RCC_OscConfig+0x474>)
|
|
8004f34: 681b ldr r3, [r3, #0]
|
|
8004f36: 4a73 ldr r2, [pc, #460] @ (8005104 <HAL_RCC_OscConfig+0x474>)
|
|
8004f38: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004f3c: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8004f3e: f7fc fbcd bl 80016dc <HAL_GetTick>
|
|
8004f42: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004f44: e008 b.n 8004f58 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004f46: f7fc fbc9 bl 80016dc <HAL_GetTick>
|
|
8004f4a: 4602 mov r2, r0
|
|
8004f4c: 693b ldr r3, [r7, #16]
|
|
8004f4e: 1ad3 subs r3, r2, r3
|
|
8004f50: 2b02 cmp r3, #2
|
|
8004f52: d901 bls.n 8004f58 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004f54: 2303 movs r3, #3
|
|
8004f56: e10c b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004f58: 4b6a ldr r3, [pc, #424] @ (8005104 <HAL_RCC_OscConfig+0x474>)
|
|
8004f5a: 681b ldr r3, [r3, #0]
|
|
8004f5c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004f60: 2b00 cmp r3, #0
|
|
8004f62: d0f0 beq.n 8004f46 <HAL_RCC_OscConfig+0x2b6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8004f64: 687b ldr r3, [r7, #4]
|
|
8004f66: 689b ldr r3, [r3, #8]
|
|
8004f68: 2b01 cmp r3, #1
|
|
8004f6a: d106 bne.n 8004f7a <HAL_RCC_OscConfig+0x2ea>
|
|
8004f6c: 4b64 ldr r3, [pc, #400] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f6e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004f70: 4a63 ldr r2, [pc, #396] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f72: f043 0301 orr.w r3, r3, #1
|
|
8004f76: 6713 str r3, [r2, #112] @ 0x70
|
|
8004f78: e01c b.n 8004fb4 <HAL_RCC_OscConfig+0x324>
|
|
8004f7a: 687b ldr r3, [r7, #4]
|
|
8004f7c: 689b ldr r3, [r3, #8]
|
|
8004f7e: 2b05 cmp r3, #5
|
|
8004f80: d10c bne.n 8004f9c <HAL_RCC_OscConfig+0x30c>
|
|
8004f82: 4b5f ldr r3, [pc, #380] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f84: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004f86: 4a5e ldr r2, [pc, #376] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f88: f043 0304 orr.w r3, r3, #4
|
|
8004f8c: 6713 str r3, [r2, #112] @ 0x70
|
|
8004f8e: 4b5c ldr r3, [pc, #368] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f90: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004f92: 4a5b ldr r2, [pc, #364] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f94: f043 0301 orr.w r3, r3, #1
|
|
8004f98: 6713 str r3, [r2, #112] @ 0x70
|
|
8004f9a: e00b b.n 8004fb4 <HAL_RCC_OscConfig+0x324>
|
|
8004f9c: 4b58 ldr r3, [pc, #352] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004f9e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fa0: 4a57 ldr r2, [pc, #348] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004fa2: f023 0301 bic.w r3, r3, #1
|
|
8004fa6: 6713 str r3, [r2, #112] @ 0x70
|
|
8004fa8: 4b55 ldr r3, [pc, #340] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004faa: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fac: 4a54 ldr r2, [pc, #336] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004fae: f023 0304 bic.w r3, r3, #4
|
|
8004fb2: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
8004fb4: 687b ldr r3, [r7, #4]
|
|
8004fb6: 689b ldr r3, [r3, #8]
|
|
8004fb8: 2b00 cmp r3, #0
|
|
8004fba: d015 beq.n 8004fe8 <HAL_RCC_OscConfig+0x358>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004fbc: f7fc fb8e bl 80016dc <HAL_GetTick>
|
|
8004fc0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004fc2: e00a b.n 8004fda <HAL_RCC_OscConfig+0x34a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004fc4: f7fc fb8a bl 80016dc <HAL_GetTick>
|
|
8004fc8: 4602 mov r2, r0
|
|
8004fca: 693b ldr r3, [r7, #16]
|
|
8004fcc: 1ad3 subs r3, r2, r3
|
|
8004fce: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004fd2: 4293 cmp r3, r2
|
|
8004fd4: d901 bls.n 8004fda <HAL_RCC_OscConfig+0x34a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004fd6: 2303 movs r3, #3
|
|
8004fd8: e0cb b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004fda: 4b49 ldr r3, [pc, #292] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8004fdc: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004fde: f003 0302 and.w r3, r3, #2
|
|
8004fe2: 2b00 cmp r3, #0
|
|
8004fe4: d0ee beq.n 8004fc4 <HAL_RCC_OscConfig+0x334>
|
|
8004fe6: e014 b.n 8005012 <HAL_RCC_OscConfig+0x382>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004fe8: f7fc fb78 bl 80016dc <HAL_GetTick>
|
|
8004fec: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004fee: e00a b.n 8005006 <HAL_RCC_OscConfig+0x376>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004ff0: f7fc fb74 bl 80016dc <HAL_GetTick>
|
|
8004ff4: 4602 mov r2, r0
|
|
8004ff6: 693b ldr r3, [r7, #16]
|
|
8004ff8: 1ad3 subs r3, r2, r3
|
|
8004ffa: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004ffe: 4293 cmp r3, r2
|
|
8005000: d901 bls.n 8005006 <HAL_RCC_OscConfig+0x376>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005002: 2303 movs r3, #3
|
|
8005004: e0b5 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8005006: 4b3e ldr r3, [pc, #248] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8005008: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800500a: f003 0302 and.w r3, r3, #2
|
|
800500e: 2b00 cmp r3, #0
|
|
8005010: d1ee bne.n 8004ff0 <HAL_RCC_OscConfig+0x360>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8005012: 7dfb ldrb r3, [r7, #23]
|
|
8005014: 2b01 cmp r3, #1
|
|
8005016: d105 bne.n 8005024 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8005018: 4b39 ldr r3, [pc, #228] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
800501a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800501c: 4a38 ldr r2, [pc, #224] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
800501e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8005022: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8005024: 687b ldr r3, [r7, #4]
|
|
8005026: 699b ldr r3, [r3, #24]
|
|
8005028: 2b00 cmp r3, #0
|
|
800502a: f000 80a1 beq.w 8005170 <HAL_RCC_OscConfig+0x4e0>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
800502e: 4b34 ldr r3, [pc, #208] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8005030: 689b ldr r3, [r3, #8]
|
|
8005032: f003 030c and.w r3, r3, #12
|
|
8005036: 2b08 cmp r3, #8
|
|
8005038: d05c beq.n 80050f4 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
800503a: 687b ldr r3, [r7, #4]
|
|
800503c: 699b ldr r3, [r3, #24]
|
|
800503e: 2b02 cmp r3, #2
|
|
8005040: d141 bne.n 80050c6 <HAL_RCC_OscConfig+0x436>
|
|
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8005042: 4b31 ldr r3, [pc, #196] @ (8005108 <HAL_RCC_OscConfig+0x478>)
|
|
8005044: 2200 movs r2, #0
|
|
8005046: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005048: f7fc fb48 bl 80016dc <HAL_GetTick>
|
|
800504c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800504e: e008 b.n 8005062 <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8005050: f7fc fb44 bl 80016dc <HAL_GetTick>
|
|
8005054: 4602 mov r2, r0
|
|
8005056: 693b ldr r3, [r7, #16]
|
|
8005058: 1ad3 subs r3, r2, r3
|
|
800505a: 2b02 cmp r3, #2
|
|
800505c: d901 bls.n 8005062 <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800505e: 2303 movs r3, #3
|
|
8005060: e087 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8005062: 4b27 ldr r3, [pc, #156] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8005064: 681b ldr r3, [r3, #0]
|
|
8005066: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800506a: 2b00 cmp r3, #0
|
|
800506c: d1f0 bne.n 8005050 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
800506e: 687b ldr r3, [r7, #4]
|
|
8005070: 69da ldr r2, [r3, #28]
|
|
8005072: 687b ldr r3, [r7, #4]
|
|
8005074: 6a1b ldr r3, [r3, #32]
|
|
8005076: 431a orrs r2, r3
|
|
8005078: 687b ldr r3, [r7, #4]
|
|
800507a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800507c: 019b lsls r3, r3, #6
|
|
800507e: 431a orrs r2, r3
|
|
8005080: 687b ldr r3, [r7, #4]
|
|
8005082: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005084: 085b lsrs r3, r3, #1
|
|
8005086: 3b01 subs r3, #1
|
|
8005088: 041b lsls r3, r3, #16
|
|
800508a: 431a orrs r2, r3
|
|
800508c: 687b ldr r3, [r7, #4]
|
|
800508e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8005090: 061b lsls r3, r3, #24
|
|
8005092: 491b ldr r1, [pc, #108] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
8005094: 4313 orrs r3, r2
|
|
8005096: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLM | \
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8005098: 4b1b ldr r3, [pc, #108] @ (8005108 <HAL_RCC_OscConfig+0x478>)
|
|
800509a: 2201 movs r2, #1
|
|
800509c: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800509e: f7fc fb1d bl 80016dc <HAL_GetTick>
|
|
80050a2: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80050a4: e008 b.n 80050b8 <HAL_RCC_OscConfig+0x428>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80050a6: f7fc fb19 bl 80016dc <HAL_GetTick>
|
|
80050aa: 4602 mov r2, r0
|
|
80050ac: 693b ldr r3, [r7, #16]
|
|
80050ae: 1ad3 subs r3, r2, r3
|
|
80050b0: 2b02 cmp r3, #2
|
|
80050b2: d901 bls.n 80050b8 <HAL_RCC_OscConfig+0x428>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050b4: 2303 movs r3, #3
|
|
80050b6: e05c b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80050b8: 4b11 ldr r3, [pc, #68] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
80050ba: 681b ldr r3, [r3, #0]
|
|
80050bc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80050c0: 2b00 cmp r3, #0
|
|
80050c2: d0f0 beq.n 80050a6 <HAL_RCC_OscConfig+0x416>
|
|
80050c4: e054 b.n 8005170 <HAL_RCC_OscConfig+0x4e0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80050c6: 4b10 ldr r3, [pc, #64] @ (8005108 <HAL_RCC_OscConfig+0x478>)
|
|
80050c8: 2200 movs r2, #0
|
|
80050ca: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80050cc: f7fc fb06 bl 80016dc <HAL_GetTick>
|
|
80050d0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80050d2: e008 b.n 80050e6 <HAL_RCC_OscConfig+0x456>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80050d4: f7fc fb02 bl 80016dc <HAL_GetTick>
|
|
80050d8: 4602 mov r2, r0
|
|
80050da: 693b ldr r3, [r7, #16]
|
|
80050dc: 1ad3 subs r3, r2, r3
|
|
80050de: 2b02 cmp r3, #2
|
|
80050e0: d901 bls.n 80050e6 <HAL_RCC_OscConfig+0x456>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050e2: 2303 movs r3, #3
|
|
80050e4: e045 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80050e6: 4b06 ldr r3, [pc, #24] @ (8005100 <HAL_RCC_OscConfig+0x470>)
|
|
80050e8: 681b ldr r3, [r3, #0]
|
|
80050ea: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80050ee: 2b00 cmp r3, #0
|
|
80050f0: d1f0 bne.n 80050d4 <HAL_RCC_OscConfig+0x444>
|
|
80050f2: e03d b.n 8005170 <HAL_RCC_OscConfig+0x4e0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
80050f4: 687b ldr r3, [r7, #4]
|
|
80050f6: 699b ldr r3, [r3, #24]
|
|
80050f8: 2b01 cmp r3, #1
|
|
80050fa: d107 bne.n 800510c <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_ERROR;
|
|
80050fc: 2301 movs r3, #1
|
|
80050fe: e038 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
8005100: 40023800 .word 0x40023800
|
|
8005104: 40007000 .word 0x40007000
|
|
8005108: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
800510c: 4b1b ldr r3, [pc, #108] @ (800517c <HAL_RCC_OscConfig+0x4ec>)
|
|
800510e: 685b ldr r3, [r3, #4]
|
|
8005110: 60fb str r3, [r7, #12]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
#else
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8005112: 687b ldr r3, [r7, #4]
|
|
8005114: 699b ldr r3, [r3, #24]
|
|
8005116: 2b01 cmp r3, #1
|
|
8005118: d028 beq.n 800516c <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800511a: 68fb ldr r3, [r7, #12]
|
|
800511c: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
8005120: 687b ldr r3, [r7, #4]
|
|
8005122: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8005124: 429a cmp r2, r3
|
|
8005126: d121 bne.n 800516c <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8005128: 68fb ldr r3, [r7, #12]
|
|
800512a: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
800512e: 687b ldr r3, [r7, #4]
|
|
8005130: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8005132: 429a cmp r2, r3
|
|
8005134: d11a bne.n 800516c <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8005136: 68fa ldr r2, [r7, #12]
|
|
8005138: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
800513c: 4013 ands r3, r2
|
|
800513e: 687a ldr r2, [r7, #4]
|
|
8005140: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
8005142: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8005144: 4293 cmp r3, r2
|
|
8005146: d111 bne.n 800516c <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8005148: 68fb ldr r3, [r7, #12]
|
|
800514a: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
800514e: 687b ldr r3, [r7, #4]
|
|
8005150: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005152: 085b lsrs r3, r3, #1
|
|
8005154: 3b01 subs r3, #1
|
|
8005156: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8005158: 429a cmp r2, r3
|
|
800515a: d107 bne.n 800516c <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
800515c: 68fb ldr r3, [r7, #12]
|
|
800515e: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
8005162: 687b ldr r3, [r7, #4]
|
|
8005164: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8005166: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8005168: 429a cmp r2, r3
|
|
800516a: d001 beq.n 8005170 <HAL_RCC_OscConfig+0x4e0>
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
800516c: 2301 movs r3, #1
|
|
800516e: e000 b.n 8005172 <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8005170: 2300 movs r3, #0
|
|
}
|
|
8005172: 4618 mov r0, r3
|
|
8005174: 3718 adds r7, #24
|
|
8005176: 46bd mov sp, r7
|
|
8005178: bd80 pop {r7, pc}
|
|
800517a: bf00 nop
|
|
800517c: 40023800 .word 0x40023800
|
|
|
|
08005180 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8005180: b580 push {r7, lr}
|
|
8005182: b084 sub sp, #16
|
|
8005184: af00 add r7, sp, #0
|
|
8005186: 6078 str r0, [r7, #4]
|
|
8005188: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800518a: 687b ldr r3, [r7, #4]
|
|
800518c: 2b00 cmp r3, #0
|
|
800518e: d101 bne.n 8005194 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8005190: 2301 movs r3, #1
|
|
8005192: e0cc b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8005194: 4b68 ldr r3, [pc, #416] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8005196: 681b ldr r3, [r3, #0]
|
|
8005198: f003 030f and.w r3, r3, #15
|
|
800519c: 683a ldr r2, [r7, #0]
|
|
800519e: 429a cmp r2, r3
|
|
80051a0: d90c bls.n 80051bc <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80051a2: 4b65 ldr r3, [pc, #404] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80051a4: 683a ldr r2, [r7, #0]
|
|
80051a6: b2d2 uxtb r2, r2
|
|
80051a8: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80051aa: 4b63 ldr r3, [pc, #396] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80051ac: 681b ldr r3, [r3, #0]
|
|
80051ae: f003 030f and.w r3, r3, #15
|
|
80051b2: 683a ldr r2, [r7, #0]
|
|
80051b4: 429a cmp r2, r3
|
|
80051b6: d001 beq.n 80051bc <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
80051b8: 2301 movs r3, #1
|
|
80051ba: e0b8 b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80051bc: 687b ldr r3, [r7, #4]
|
|
80051be: 681b ldr r3, [r3, #0]
|
|
80051c0: f003 0302 and.w r3, r3, #2
|
|
80051c4: 2b00 cmp r3, #0
|
|
80051c6: d020 beq.n 800520a <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80051c8: 687b ldr r3, [r7, #4]
|
|
80051ca: 681b ldr r3, [r3, #0]
|
|
80051cc: f003 0304 and.w r3, r3, #4
|
|
80051d0: 2b00 cmp r3, #0
|
|
80051d2: d005 beq.n 80051e0 <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
80051d4: 4b59 ldr r3, [pc, #356] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80051d6: 689b ldr r3, [r3, #8]
|
|
80051d8: 4a58 ldr r2, [pc, #352] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80051da: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
80051de: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80051e0: 687b ldr r3, [r7, #4]
|
|
80051e2: 681b ldr r3, [r3, #0]
|
|
80051e4: f003 0308 and.w r3, r3, #8
|
|
80051e8: 2b00 cmp r3, #0
|
|
80051ea: d005 beq.n 80051f8 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
80051ec: 4b53 ldr r3, [pc, #332] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80051ee: 689b ldr r3, [r3, #8]
|
|
80051f0: 4a52 ldr r2, [pc, #328] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80051f2: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
80051f6: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80051f8: 4b50 ldr r3, [pc, #320] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80051fa: 689b ldr r3, [r3, #8]
|
|
80051fc: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8005200: 687b ldr r3, [r7, #4]
|
|
8005202: 689b ldr r3, [r3, #8]
|
|
8005204: 494d ldr r1, [pc, #308] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005206: 4313 orrs r3, r2
|
|
8005208: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800520a: 687b ldr r3, [r7, #4]
|
|
800520c: 681b ldr r3, [r3, #0]
|
|
800520e: f003 0301 and.w r3, r3, #1
|
|
8005212: 2b00 cmp r3, #0
|
|
8005214: d044 beq.n 80052a0 <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8005216: 687b ldr r3, [r7, #4]
|
|
8005218: 685b ldr r3, [r3, #4]
|
|
800521a: 2b01 cmp r3, #1
|
|
800521c: d107 bne.n 800522e <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800521e: 4b47 ldr r3, [pc, #284] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005220: 681b ldr r3, [r3, #0]
|
|
8005222: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8005226: 2b00 cmp r3, #0
|
|
8005228: d119 bne.n 800525e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800522a: 2301 movs r3, #1
|
|
800522c: e07f b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800522e: 687b ldr r3, [r7, #4]
|
|
8005230: 685b ldr r3, [r3, #4]
|
|
8005232: 2b02 cmp r3, #2
|
|
8005234: d003 beq.n 800523e <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
8005236: 687b ldr r3, [r7, #4]
|
|
8005238: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
800523a: 2b03 cmp r3, #3
|
|
800523c: d107 bne.n 800524e <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
800523e: 4b3f ldr r3, [pc, #252] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005240: 681b ldr r3, [r3, #0]
|
|
8005242: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8005246: 2b00 cmp r3, #0
|
|
8005248: d109 bne.n 800525e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800524a: 2301 movs r3, #1
|
|
800524c: e06f b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800524e: 4b3b ldr r3, [pc, #236] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005250: 681b ldr r3, [r3, #0]
|
|
8005252: f003 0302 and.w r3, r3, #2
|
|
8005256: 2b00 cmp r3, #0
|
|
8005258: d101 bne.n 800525e <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
800525a: 2301 movs r3, #1
|
|
800525c: e067 b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
800525e: 4b37 ldr r3, [pc, #220] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005260: 689b ldr r3, [r3, #8]
|
|
8005262: f023 0203 bic.w r2, r3, #3
|
|
8005266: 687b ldr r3, [r7, #4]
|
|
8005268: 685b ldr r3, [r3, #4]
|
|
800526a: 4934 ldr r1, [pc, #208] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800526c: 4313 orrs r3, r2
|
|
800526e: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8005270: f7fc fa34 bl 80016dc <HAL_GetTick>
|
|
8005274: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8005276: e00a b.n 800528e <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8005278: f7fc fa30 bl 80016dc <HAL_GetTick>
|
|
800527c: 4602 mov r2, r0
|
|
800527e: 68fb ldr r3, [r7, #12]
|
|
8005280: 1ad3 subs r3, r2, r3
|
|
8005282: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005286: 4293 cmp r3, r2
|
|
8005288: d901 bls.n 800528e <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800528a: 2303 movs r3, #3
|
|
800528c: e04f b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800528e: 4b2b ldr r3, [pc, #172] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005290: 689b ldr r3, [r3, #8]
|
|
8005292: f003 020c and.w r2, r3, #12
|
|
8005296: 687b ldr r3, [r7, #4]
|
|
8005298: 685b ldr r3, [r3, #4]
|
|
800529a: 009b lsls r3, r3, #2
|
|
800529c: 429a cmp r2, r3
|
|
800529e: d1eb bne.n 8005278 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
80052a0: 4b25 ldr r3, [pc, #148] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80052a2: 681b ldr r3, [r3, #0]
|
|
80052a4: f003 030f and.w r3, r3, #15
|
|
80052a8: 683a ldr r2, [r7, #0]
|
|
80052aa: 429a cmp r2, r3
|
|
80052ac: d20c bcs.n 80052c8 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80052ae: 4b22 ldr r3, [pc, #136] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80052b0: 683a ldr r2, [r7, #0]
|
|
80052b2: b2d2 uxtb r2, r2
|
|
80052b4: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80052b6: 4b20 ldr r3, [pc, #128] @ (8005338 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80052b8: 681b ldr r3, [r3, #0]
|
|
80052ba: f003 030f and.w r3, r3, #15
|
|
80052be: 683a ldr r2, [r7, #0]
|
|
80052c0: 429a cmp r2, r3
|
|
80052c2: d001 beq.n 80052c8 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
80052c4: 2301 movs r3, #1
|
|
80052c6: e032 b.n 800532e <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80052c8: 687b ldr r3, [r7, #4]
|
|
80052ca: 681b ldr r3, [r3, #0]
|
|
80052cc: f003 0304 and.w r3, r3, #4
|
|
80052d0: 2b00 cmp r3, #0
|
|
80052d2: d008 beq.n 80052e6 <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
80052d4: 4b19 ldr r3, [pc, #100] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80052d6: 689b ldr r3, [r3, #8]
|
|
80052d8: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
80052dc: 687b ldr r3, [r7, #4]
|
|
80052de: 68db ldr r3, [r3, #12]
|
|
80052e0: 4916 ldr r1, [pc, #88] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80052e2: 4313 orrs r3, r2
|
|
80052e4: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80052e6: 687b ldr r3, [r7, #4]
|
|
80052e8: 681b ldr r3, [r3, #0]
|
|
80052ea: f003 0308 and.w r3, r3, #8
|
|
80052ee: 2b00 cmp r3, #0
|
|
80052f0: d009 beq.n 8005306 <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
80052f2: 4b12 ldr r3, [pc, #72] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
80052f4: 689b ldr r3, [r3, #8]
|
|
80052f6: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
80052fa: 687b ldr r3, [r7, #4]
|
|
80052fc: 691b ldr r3, [r3, #16]
|
|
80052fe: 00db lsls r3, r3, #3
|
|
8005300: 490e ldr r1, [pc, #56] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
8005302: 4313 orrs r3, r2
|
|
8005304: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8005306: f000 f821 bl 800534c <HAL_RCC_GetSysClockFreq>
|
|
800530a: 4602 mov r2, r0
|
|
800530c: 4b0b ldr r3, [pc, #44] @ (800533c <HAL_RCC_ClockConfig+0x1bc>)
|
|
800530e: 689b ldr r3, [r3, #8]
|
|
8005310: 091b lsrs r3, r3, #4
|
|
8005312: f003 030f and.w r3, r3, #15
|
|
8005316: 490a ldr r1, [pc, #40] @ (8005340 <HAL_RCC_ClockConfig+0x1c0>)
|
|
8005318: 5ccb ldrb r3, [r1, r3]
|
|
800531a: fa22 f303 lsr.w r3, r2, r3
|
|
800531e: 4a09 ldr r2, [pc, #36] @ (8005344 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8005320: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
8005322: 4b09 ldr r3, [pc, #36] @ (8005348 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8005324: 681b ldr r3, [r3, #0]
|
|
8005326: 4618 mov r0, r3
|
|
8005328: f7fc f870 bl 800140c <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
800532c: 2300 movs r3, #0
|
|
}
|
|
800532e: 4618 mov r0, r3
|
|
8005330: 3710 adds r7, #16
|
|
8005332: 46bd mov sp, r7
|
|
8005334: bd80 pop {r7, pc}
|
|
8005336: bf00 nop
|
|
8005338: 40023c00 .word 0x40023c00
|
|
800533c: 40023800 .word 0x40023800
|
|
8005340: 0800d10c .word 0x0800d10c
|
|
8005344: 20000000 .word 0x20000000
|
|
8005348: 20000004 .word 0x20000004
|
|
|
|
0800534c <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
800534c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8005350: b094 sub sp, #80 @ 0x50
|
|
8005352: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8005354: 2300 movs r3, #0
|
|
8005356: 647b str r3, [r7, #68] @ 0x44
|
|
uint32_t pllvco = 0U;
|
|
8005358: 2300 movs r3, #0
|
|
800535a: 64fb str r3, [r7, #76] @ 0x4c
|
|
uint32_t pllp = 0U;
|
|
800535c: 2300 movs r3, #0
|
|
800535e: 643b str r3, [r7, #64] @ 0x40
|
|
uint32_t sysclockfreq = 0U;
|
|
8005360: 2300 movs r3, #0
|
|
8005362: 64bb str r3, [r7, #72] @ 0x48
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8005364: 4b79 ldr r3, [pc, #484] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8005366: 689b ldr r3, [r3, #8]
|
|
8005368: f003 030c and.w r3, r3, #12
|
|
800536c: 2b08 cmp r3, #8
|
|
800536e: d00d beq.n 800538c <HAL_RCC_GetSysClockFreq+0x40>
|
|
8005370: 2b08 cmp r3, #8
|
|
8005372: f200 80e1 bhi.w 8005538 <HAL_RCC_GetSysClockFreq+0x1ec>
|
|
8005376: 2b00 cmp r3, #0
|
|
8005378: d002 beq.n 8005380 <HAL_RCC_GetSysClockFreq+0x34>
|
|
800537a: 2b04 cmp r3, #4
|
|
800537c: d003 beq.n 8005386 <HAL_RCC_GetSysClockFreq+0x3a>
|
|
800537e: e0db b.n 8005538 <HAL_RCC_GetSysClockFreq+0x1ec>
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8005380: 4b73 ldr r3, [pc, #460] @ (8005550 <HAL_RCC_GetSysClockFreq+0x204>)
|
|
8005382: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8005384: e0db b.n 800553e <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8005386: 4b73 ldr r3, [pc, #460] @ (8005554 <HAL_RCC_GetSysClockFreq+0x208>)
|
|
8005388: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
800538a: e0d8 b.n 800553e <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
800538c: 4b6f ldr r3, [pc, #444] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
800538e: 685b ldr r3, [r3, #4]
|
|
8005390: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8005394: 647b str r3, [r7, #68] @ 0x44
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8005396: 4b6d ldr r3, [pc, #436] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8005398: 685b ldr r3, [r3, #4]
|
|
800539a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
800539e: 2b00 cmp r3, #0
|
|
80053a0: d063 beq.n 800546a <HAL_RCC_GetSysClockFreq+0x11e>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
80053a2: 4b6a ldr r3, [pc, #424] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
80053a4: 685b ldr r3, [r3, #4]
|
|
80053a6: 099b lsrs r3, r3, #6
|
|
80053a8: 2200 movs r2, #0
|
|
80053aa: 63bb str r3, [r7, #56] @ 0x38
|
|
80053ac: 63fa str r2, [r7, #60] @ 0x3c
|
|
80053ae: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80053b0: f3c3 0308 ubfx r3, r3, #0, #9
|
|
80053b4: 633b str r3, [r7, #48] @ 0x30
|
|
80053b6: 2300 movs r3, #0
|
|
80053b8: 637b str r3, [r7, #52] @ 0x34
|
|
80053ba: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
80053be: 4622 mov r2, r4
|
|
80053c0: 462b mov r3, r5
|
|
80053c2: f04f 0000 mov.w r0, #0
|
|
80053c6: f04f 0100 mov.w r1, #0
|
|
80053ca: 0159 lsls r1, r3, #5
|
|
80053cc: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
80053d0: 0150 lsls r0, r2, #5
|
|
80053d2: 4602 mov r2, r0
|
|
80053d4: 460b mov r3, r1
|
|
80053d6: 4621 mov r1, r4
|
|
80053d8: 1a51 subs r1, r2, r1
|
|
80053da: 6139 str r1, [r7, #16]
|
|
80053dc: 4629 mov r1, r5
|
|
80053de: eb63 0301 sbc.w r3, r3, r1
|
|
80053e2: 617b str r3, [r7, #20]
|
|
80053e4: f04f 0200 mov.w r2, #0
|
|
80053e8: f04f 0300 mov.w r3, #0
|
|
80053ec: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
80053f0: 4659 mov r1, fp
|
|
80053f2: 018b lsls r3, r1, #6
|
|
80053f4: 4651 mov r1, sl
|
|
80053f6: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
80053fa: 4651 mov r1, sl
|
|
80053fc: 018a lsls r2, r1, #6
|
|
80053fe: 4651 mov r1, sl
|
|
8005400: ebb2 0801 subs.w r8, r2, r1
|
|
8005404: 4659 mov r1, fp
|
|
8005406: eb63 0901 sbc.w r9, r3, r1
|
|
800540a: f04f 0200 mov.w r2, #0
|
|
800540e: f04f 0300 mov.w r3, #0
|
|
8005412: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8005416: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
800541a: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
800541e: 4690 mov r8, r2
|
|
8005420: 4699 mov r9, r3
|
|
8005422: 4623 mov r3, r4
|
|
8005424: eb18 0303 adds.w r3, r8, r3
|
|
8005428: 60bb str r3, [r7, #8]
|
|
800542a: 462b mov r3, r5
|
|
800542c: eb49 0303 adc.w r3, r9, r3
|
|
8005430: 60fb str r3, [r7, #12]
|
|
8005432: f04f 0200 mov.w r2, #0
|
|
8005436: f04f 0300 mov.w r3, #0
|
|
800543a: e9d7 4502 ldrd r4, r5, [r7, #8]
|
|
800543e: 4629 mov r1, r5
|
|
8005440: 024b lsls r3, r1, #9
|
|
8005442: 4621 mov r1, r4
|
|
8005444: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8005448: 4621 mov r1, r4
|
|
800544a: 024a lsls r2, r1, #9
|
|
800544c: 4610 mov r0, r2
|
|
800544e: 4619 mov r1, r3
|
|
8005450: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8005452: 2200 movs r2, #0
|
|
8005454: 62bb str r3, [r7, #40] @ 0x28
|
|
8005456: 62fa str r2, [r7, #44] @ 0x2c
|
|
8005458: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
800545c: f7fa fec8 bl 80001f0 <__aeabi_uldivmod>
|
|
8005460: 4602 mov r2, r0
|
|
8005462: 460b mov r3, r1
|
|
8005464: 4613 mov r3, r2
|
|
8005466: 64fb str r3, [r7, #76] @ 0x4c
|
|
8005468: e058 b.n 800551c <HAL_RCC_GetSysClockFreq+0x1d0>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
800546a: 4b38 ldr r3, [pc, #224] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
800546c: 685b ldr r3, [r3, #4]
|
|
800546e: 099b lsrs r3, r3, #6
|
|
8005470: 2200 movs r2, #0
|
|
8005472: 4618 mov r0, r3
|
|
8005474: 4611 mov r1, r2
|
|
8005476: f3c0 0308 ubfx r3, r0, #0, #9
|
|
800547a: 623b str r3, [r7, #32]
|
|
800547c: 2300 movs r3, #0
|
|
800547e: 627b str r3, [r7, #36] @ 0x24
|
|
8005480: e9d7 8908 ldrd r8, r9, [r7, #32]
|
|
8005484: 4642 mov r2, r8
|
|
8005486: 464b mov r3, r9
|
|
8005488: f04f 0000 mov.w r0, #0
|
|
800548c: f04f 0100 mov.w r1, #0
|
|
8005490: 0159 lsls r1, r3, #5
|
|
8005492: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8005496: 0150 lsls r0, r2, #5
|
|
8005498: 4602 mov r2, r0
|
|
800549a: 460b mov r3, r1
|
|
800549c: 4641 mov r1, r8
|
|
800549e: ebb2 0a01 subs.w sl, r2, r1
|
|
80054a2: 4649 mov r1, r9
|
|
80054a4: eb63 0b01 sbc.w fp, r3, r1
|
|
80054a8: f04f 0200 mov.w r2, #0
|
|
80054ac: f04f 0300 mov.w r3, #0
|
|
80054b0: ea4f 138b mov.w r3, fp, lsl #6
|
|
80054b4: ea43 639a orr.w r3, r3, sl, lsr #26
|
|
80054b8: ea4f 128a mov.w r2, sl, lsl #6
|
|
80054bc: ebb2 040a subs.w r4, r2, sl
|
|
80054c0: eb63 050b sbc.w r5, r3, fp
|
|
80054c4: f04f 0200 mov.w r2, #0
|
|
80054c8: f04f 0300 mov.w r3, #0
|
|
80054cc: 00eb lsls r3, r5, #3
|
|
80054ce: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
80054d2: 00e2 lsls r2, r4, #3
|
|
80054d4: 4614 mov r4, r2
|
|
80054d6: 461d mov r5, r3
|
|
80054d8: 4643 mov r3, r8
|
|
80054da: 18e3 adds r3, r4, r3
|
|
80054dc: 603b str r3, [r7, #0]
|
|
80054de: 464b mov r3, r9
|
|
80054e0: eb45 0303 adc.w r3, r5, r3
|
|
80054e4: 607b str r3, [r7, #4]
|
|
80054e6: f04f 0200 mov.w r2, #0
|
|
80054ea: f04f 0300 mov.w r3, #0
|
|
80054ee: e9d7 4500 ldrd r4, r5, [r7]
|
|
80054f2: 4629 mov r1, r5
|
|
80054f4: 028b lsls r3, r1, #10
|
|
80054f6: 4621 mov r1, r4
|
|
80054f8: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
80054fc: 4621 mov r1, r4
|
|
80054fe: 028a lsls r2, r1, #10
|
|
8005500: 4610 mov r0, r2
|
|
8005502: 4619 mov r1, r3
|
|
8005504: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8005506: 2200 movs r2, #0
|
|
8005508: 61bb str r3, [r7, #24]
|
|
800550a: 61fa str r2, [r7, #28]
|
|
800550c: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8005510: f7fa fe6e bl 80001f0 <__aeabi_uldivmod>
|
|
8005514: 4602 mov r2, r0
|
|
8005516: 460b mov r3, r1
|
|
8005518: 4613 mov r3, r2
|
|
800551a: 64fb str r3, [r7, #76] @ 0x4c
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
800551c: 4b0b ldr r3, [pc, #44] @ (800554c <HAL_RCC_GetSysClockFreq+0x200>)
|
|
800551e: 685b ldr r3, [r3, #4]
|
|
8005520: 0c1b lsrs r3, r3, #16
|
|
8005522: f003 0303 and.w r3, r3, #3
|
|
8005526: 3301 adds r3, #1
|
|
8005528: 005b lsls r3, r3, #1
|
|
800552a: 643b str r3, [r7, #64] @ 0x40
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
800552c: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
800552e: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8005530: fbb2 f3f3 udiv r3, r2, r3
|
|
8005534: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8005536: e002 b.n 800553e <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8005538: 4b05 ldr r3, [pc, #20] @ (8005550 <HAL_RCC_GetSysClockFreq+0x204>)
|
|
800553a: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
800553c: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
800553e: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
}
|
|
8005540: 4618 mov r0, r3
|
|
8005542: 3750 adds r7, #80 @ 0x50
|
|
8005544: 46bd mov sp, r7
|
|
8005546: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
800554a: bf00 nop
|
|
800554c: 40023800 .word 0x40023800
|
|
8005550: 00f42400 .word 0x00f42400
|
|
8005554: 007a1200 .word 0x007a1200
|
|
|
|
08005558 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8005558: b480 push {r7}
|
|
800555a: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
800555c: 4b03 ldr r3, [pc, #12] @ (800556c <HAL_RCC_GetHCLKFreq+0x14>)
|
|
800555e: 681b ldr r3, [r3, #0]
|
|
}
|
|
8005560: 4618 mov r0, r3
|
|
8005562: 46bd mov sp, r7
|
|
8005564: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005568: 4770 bx lr
|
|
800556a: bf00 nop
|
|
800556c: 20000000 .word 0x20000000
|
|
|
|
08005570 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8005570: b580 push {r7, lr}
|
|
8005572: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
8005574: f7ff fff0 bl 8005558 <HAL_RCC_GetHCLKFreq>
|
|
8005578: 4602 mov r2, r0
|
|
800557a: 4b05 ldr r3, [pc, #20] @ (8005590 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
800557c: 689b ldr r3, [r3, #8]
|
|
800557e: 0a9b lsrs r3, r3, #10
|
|
8005580: f003 0307 and.w r3, r3, #7
|
|
8005584: 4903 ldr r1, [pc, #12] @ (8005594 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8005586: 5ccb ldrb r3, [r1, r3]
|
|
8005588: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
800558c: 4618 mov r0, r3
|
|
800558e: bd80 pop {r7, pc}
|
|
8005590: 40023800 .word 0x40023800
|
|
8005594: 0800d11c .word 0x0800d11c
|
|
|
|
08005598 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8005598: b580 push {r7, lr}
|
|
800559a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
800559c: f7ff ffdc bl 8005558 <HAL_RCC_GetHCLKFreq>
|
|
80055a0: 4602 mov r2, r0
|
|
80055a2: 4b05 ldr r3, [pc, #20] @ (80055b8 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
80055a4: 689b ldr r3, [r3, #8]
|
|
80055a6: 0b5b lsrs r3, r3, #13
|
|
80055a8: f003 0307 and.w r3, r3, #7
|
|
80055ac: 4903 ldr r1, [pc, #12] @ (80055bc <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
80055ae: 5ccb ldrb r3, [r1, r3]
|
|
80055b0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80055b4: 4618 mov r0, r3
|
|
80055b6: bd80 pop {r7, pc}
|
|
80055b8: 40023800 .word 0x40023800
|
|
80055bc: 0800d11c .word 0x0800d11c
|
|
|
|
080055c0 <HAL_RCC_GetClockConfig>:
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
80055c0: b480 push {r7}
|
|
80055c2: b083 sub sp, #12
|
|
80055c4: af00 add r7, sp, #0
|
|
80055c6: 6078 str r0, [r7, #4]
|
|
80055c8: 6039 str r1, [r7, #0]
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
80055ca: 687b ldr r3, [r7, #4]
|
|
80055cc: 220f movs r2, #15
|
|
80055ce: 601a str r2, [r3, #0]
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
80055d0: 4b12 ldr r3, [pc, #72] @ (800561c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80055d2: 689b ldr r3, [r3, #8]
|
|
80055d4: f003 0203 and.w r2, r3, #3
|
|
80055d8: 687b ldr r3, [r7, #4]
|
|
80055da: 605a str r2, [r3, #4]
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
80055dc: 4b0f ldr r3, [pc, #60] @ (800561c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80055de: 689b ldr r3, [r3, #8]
|
|
80055e0: f003 02f0 and.w r2, r3, #240 @ 0xf0
|
|
80055e4: 687b ldr r3, [r7, #4]
|
|
80055e6: 609a str r2, [r3, #8]
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
80055e8: 4b0c ldr r3, [pc, #48] @ (800561c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80055ea: 689b ldr r3, [r3, #8]
|
|
80055ec: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
|
|
80055f0: 687b ldr r3, [r7, #4]
|
|
80055f2: 60da str r2, [r3, #12]
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
|
|
80055f4: 4b09 ldr r3, [pc, #36] @ (800561c <HAL_RCC_GetClockConfig+0x5c>)
|
|
80055f6: 689b ldr r3, [r3, #8]
|
|
80055f8: 08db lsrs r3, r3, #3
|
|
80055fa: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
|
|
80055fe: 687b ldr r3, [r7, #4]
|
|
8005600: 611a str r2, [r3, #16]
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
8005602: 4b07 ldr r3, [pc, #28] @ (8005620 <HAL_RCC_GetClockConfig+0x60>)
|
|
8005604: 681b ldr r3, [r3, #0]
|
|
8005606: f003 020f and.w r2, r3, #15
|
|
800560a: 683b ldr r3, [r7, #0]
|
|
800560c: 601a str r2, [r3, #0]
|
|
}
|
|
800560e: bf00 nop
|
|
8005610: 370c adds r7, #12
|
|
8005612: 46bd mov sp, r7
|
|
8005614: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005618: 4770 bx lr
|
|
800561a: bf00 nop
|
|
800561c: 40023800 .word 0x40023800
|
|
8005620: 40023c00 .word 0x40023c00
|
|
|
|
08005624 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8005624: b580 push {r7, lr}
|
|
8005626: b086 sub sp, #24
|
|
8005628: af00 add r7, sp, #0
|
|
800562a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
800562c: 2300 movs r3, #0
|
|
800562e: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg1 = 0U;
|
|
8005630: 2300 movs r3, #0
|
|
8005632: 613b str r3, [r7, #16]
|
|
|
|
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
|
|
/*----------------------- Common configuration SAI/I2S ---------------------*/
|
|
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
|
|
factor is common parameters for both peripherals */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
|
8005634: 687b ldr r3, [r7, #4]
|
|
8005636: 681b ldr r3, [r3, #0]
|
|
8005638: f003 0301 and.w r3, r3, #1
|
|
800563c: 2b00 cmp r3, #0
|
|
800563e: d10b bne.n 8005658 <HAL_RCCEx_PeriphCLKConfig+0x34>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
|
|
8005640: 687b ldr r3, [r7, #4]
|
|
8005642: 681b ldr r3, [r3, #0]
|
|
8005644: f003 0302 and.w r3, r3, #2
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
|
8005648: 2b00 cmp r3, #0
|
|
800564a: d105 bne.n 8005658 <HAL_RCCEx_PeriphCLKConfig+0x34>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
|
|
800564c: 687b ldr r3, [r7, #4]
|
|
800564e: 681b ldr r3, [r3, #0]
|
|
8005650: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
|
|
8005654: 2b00 cmp r3, #0
|
|
8005656: d075 beq.n 8005744 <HAL_RCCEx_PeriphCLKConfig+0x120>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
8005658: 4b91 ldr r3, [pc, #580] @ (80058a0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|
800565a: 2200 movs r2, #0
|
|
800565c: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800565e: f7fc f83d bl 80016dc <HAL_GetTick>
|
|
8005662: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8005664: e008 b.n 8005678 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8005666: f7fc f839 bl 80016dc <HAL_GetTick>
|
|
800566a: 4602 mov r2, r0
|
|
800566c: 697b ldr r3, [r7, #20]
|
|
800566e: 1ad3 subs r3, r2, r3
|
|
8005670: 2b02 cmp r3, #2
|
|
8005672: d901 bls.n 8005678 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8005674: 2303 movs r3, #3
|
|
8005676: e189 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8005678: 4b8a ldr r3, [pc, #552] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800567a: 681b ldr r3, [r3, #0]
|
|
800567c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8005680: 2b00 cmp r3, #0
|
|
8005682: d1f0 bne.n 8005666 <HAL_RCCEx_PeriphCLKConfig+0x42>
|
|
}
|
|
|
|
/*---------------------------- I2S configuration -------------------------*/
|
|
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
|
|
only for I2S configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
|
8005684: 687b ldr r3, [r7, #4]
|
|
8005686: 681b ldr r3, [r3, #0]
|
|
8005688: f003 0301 and.w r3, r3, #1
|
|
800568c: 2b00 cmp r3, #0
|
|
800568e: d009 beq.n 80056a4 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
8005690: 687b ldr r3, [r7, #4]
|
|
8005692: 685b ldr r3, [r3, #4]
|
|
8005694: 019a lsls r2, r3, #6
|
|
8005696: 687b ldr r3, [r7, #4]
|
|
8005698: 689b ldr r3, [r3, #8]
|
|
800569a: 071b lsls r3, r3, #28
|
|
800569c: 4981 ldr r1, [pc, #516] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800569e: 4313 orrs r3, r2
|
|
80056a0: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
}
|
|
|
|
/*---------------------------- SAI configuration -------------------------*/
|
|
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
|
|
be added only for SAI configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
|
|
80056a4: 687b ldr r3, [r7, #4]
|
|
80056a6: 681b ldr r3, [r3, #0]
|
|
80056a8: f003 0302 and.w r3, r3, #2
|
|
80056ac: 2b00 cmp r3, #0
|
|
80056ae: d01f beq.n 80056f0 <HAL_RCCEx_PeriphCLKConfig+0xcc>
|
|
/* Check the PLLI2S division factors */
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
80056b0: 4b7c ldr r3, [pc, #496] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80056b2: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80056b6: 0f1b lsrs r3, r3, #28
|
|
80056b8: f003 0307 and.w r3, r3, #7
|
|
80056bc: 613b str r3, [r7, #16]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
|
|
80056be: 687b ldr r3, [r7, #4]
|
|
80056c0: 685b ldr r3, [r3, #4]
|
|
80056c2: 019a lsls r2, r3, #6
|
|
80056c4: 687b ldr r3, [r7, #4]
|
|
80056c6: 68db ldr r3, [r3, #12]
|
|
80056c8: 061b lsls r3, r3, #24
|
|
80056ca: 431a orrs r2, r3
|
|
80056cc: 693b ldr r3, [r7, #16]
|
|
80056ce: 071b lsls r3, r3, #28
|
|
80056d0: 4974 ldr r1, [pc, #464] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80056d2: 4313 orrs r3, r2
|
|
80056d4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
80056d8: 4b72 ldr r3, [pc, #456] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80056da: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80056de: f023 021f bic.w r2, r3, #31
|
|
80056e2: 687b ldr r3, [r7, #4]
|
|
80056e4: 69db ldr r3, [r3, #28]
|
|
80056e6: 3b01 subs r3, #1
|
|
80056e8: 496e ldr r1, [pc, #440] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80056ea: 4313 orrs r3, r2
|
|
80056ec: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
80056f0: 687b ldr r3, [r7, #4]
|
|
80056f2: 681b ldr r3, [r3, #0]
|
|
80056f4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80056f8: 2b00 cmp r3, #0
|
|
80056fa: d00d beq.n 8005718 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
/* Check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Configure the PLLI2S multiplication and division factors */
|
|
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
|
|
80056fc: 687b ldr r3, [r7, #4]
|
|
80056fe: 685b ldr r3, [r3, #4]
|
|
8005700: 019a lsls r2, r3, #6
|
|
8005702: 687b ldr r3, [r7, #4]
|
|
8005704: 68db ldr r3, [r3, #12]
|
|
8005706: 061b lsls r3, r3, #24
|
|
8005708: 431a orrs r2, r3
|
|
800570a: 687b ldr r3, [r7, #4]
|
|
800570c: 689b ldr r3, [r3, #8]
|
|
800570e: 071b lsls r3, r3, #28
|
|
8005710: 4964 ldr r1, [pc, #400] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005712: 4313 orrs r3, r2
|
|
8005714: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
8005718: 4b61 ldr r3, [pc, #388] @ (80058a0 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|
800571a: 2201 movs r2, #1
|
|
800571c: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800571e: f7fb ffdd bl 80016dc <HAL_GetTick>
|
|
8005722: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8005724: e008 b.n 8005738 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8005726: f7fb ffd9 bl 80016dc <HAL_GetTick>
|
|
800572a: 4602 mov r2, r0
|
|
800572c: 697b ldr r3, [r7, #20]
|
|
800572e: 1ad3 subs r3, r2, r3
|
|
8005730: 2b02 cmp r3, #2
|
|
8005732: d901 bls.n 8005738 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8005734: 2303 movs r3, #3
|
|
8005736: e129 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8005738: 4b5a ldr r3, [pc, #360] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800573a: 681b ldr r3, [r3, #0]
|
|
800573c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8005740: 2b00 cmp r3, #0
|
|
8005742: d0f0 beq.n 8005726 <HAL_RCCEx_PeriphCLKConfig+0x102>
|
|
|
|
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
|
|
/*----------------------- Common configuration SAI/LTDC --------------------*/
|
|
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
|
|
factor is common parameters for both peripherals */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
|
8005744: 687b ldr r3, [r7, #4]
|
|
8005746: 681b ldr r3, [r3, #0]
|
|
8005748: f003 0304 and.w r3, r3, #4
|
|
800574c: 2b00 cmp r3, #0
|
|
800574e: d105 bne.n 800575c <HAL_RCCEx_PeriphCLKConfig+0x138>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
|
|
8005750: 687b ldr r3, [r7, #4]
|
|
8005752: 681b ldr r3, [r3, #0]
|
|
8005754: f003 0308 and.w r3, r3, #8
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
|
8005758: 2b00 cmp r3, #0
|
|
800575a: d079 beq.n 8005850 <HAL_RCCEx_PeriphCLKConfig+0x22c>
|
|
{
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
800575c: 4b52 ldr r3, [pc, #328] @ (80058a8 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
|
800575e: 2200 movs r2, #0
|
|
8005760: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8005762: f7fb ffbb bl 80016dc <HAL_GetTick>
|
|
8005766: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8005768: e008 b.n 800577c <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
800576a: f7fb ffb7 bl 80016dc <HAL_GetTick>
|
|
800576e: 4602 mov r2, r0
|
|
8005770: 697b ldr r3, [r7, #20]
|
|
8005772: 1ad3 subs r3, r2, r3
|
|
8005774: 2b02 cmp r3, #2
|
|
8005776: d901 bls.n 800577c <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8005778: 2303 movs r3, #3
|
|
800577a: e107 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
800577c: 4b49 ldr r3, [pc, #292] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800577e: 681b ldr r3, [r3, #0]
|
|
8005780: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8005784: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8005788: d0ef beq.n 800576a <HAL_RCCEx_PeriphCLKConfig+0x146>
|
|
}
|
|
|
|
/*---------------------------- SAI configuration -------------------------*/
|
|
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
|
|
be added only for SAI configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
|
|
800578a: 687b ldr r3, [r7, #4]
|
|
800578c: 681b ldr r3, [r3, #0]
|
|
800578e: f003 0304 and.w r3, r3, #4
|
|
8005792: 2b00 cmp r3, #0
|
|
8005794: d020 beq.n 80057d8 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
|
|
8005796: 4b43 ldr r3, [pc, #268] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005798: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800579c: 0f1b lsrs r3, r3, #28
|
|
800579e: f003 0307 and.w r3, r3, #7
|
|
80057a2: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
|
|
80057a4: 687b ldr r3, [r7, #4]
|
|
80057a6: 691b ldr r3, [r3, #16]
|
|
80057a8: 019a lsls r2, r3, #6
|
|
80057aa: 687b ldr r3, [r7, #4]
|
|
80057ac: 695b ldr r3, [r3, #20]
|
|
80057ae: 061b lsls r3, r3, #24
|
|
80057b0: 431a orrs r2, r3
|
|
80057b2: 693b ldr r3, [r7, #16]
|
|
80057b4: 071b lsls r3, r3, #28
|
|
80057b6: 493b ldr r1, [pc, #236] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80057b8: 4313 orrs r3, r2
|
|
80057ba: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
80057be: 4b39 ldr r3, [pc, #228] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80057c0: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
80057c4: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
80057c8: 687b ldr r3, [r7, #4]
|
|
80057ca: 6a1b ldr r3, [r3, #32]
|
|
80057cc: 3b01 subs r3, #1
|
|
80057ce: 021b lsls r3, r3, #8
|
|
80057d0: 4934 ldr r1, [pc, #208] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80057d2: 4313 orrs r3, r2
|
|
80057d4: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*---------------------------- LTDC configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
|
|
80057d8: 687b ldr r3, [r7, #4]
|
|
80057da: 681b ldr r3, [r3, #0]
|
|
80057dc: f003 0308 and.w r3, r3, #8
|
|
80057e0: 2b00 cmp r3, #0
|
|
80057e2: d01e beq.n 8005822 <HAL_RCCEx_PeriphCLKConfig+0x1fe>
|
|
{
|
|
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
|
|
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
|
|
|
|
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
80057e4: 4b2f ldr r3, [pc, #188] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
80057e6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80057ea: 0e1b lsrs r3, r3, #24
|
|
80057ec: f003 030f and.w r3, r3, #15
|
|
80057f0: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
|
|
80057f2: 687b ldr r3, [r7, #4]
|
|
80057f4: 691b ldr r3, [r3, #16]
|
|
80057f6: 019a lsls r2, r3, #6
|
|
80057f8: 693b ldr r3, [r7, #16]
|
|
80057fa: 061b lsls r3, r3, #24
|
|
80057fc: 431a orrs r2, r3
|
|
80057fe: 687b ldr r3, [r7, #4]
|
|
8005800: 699b ldr r3, [r3, #24]
|
|
8005802: 071b lsls r3, r3, #28
|
|
8005804: 4927 ldr r1, [pc, #156] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005806: 4313 orrs r3, r2
|
|
8005808: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
|
|
800580c: 4b25 ldr r3, [pc, #148] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800580e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8005812: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8005816: 687b ldr r3, [r7, #4]
|
|
8005818: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800581a: 4922 ldr r1, [pc, #136] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800581c: 4313 orrs r3, r2
|
|
800581e: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
8005822: 4b21 ldr r3, [pc, #132] @ (80058a8 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
|
8005824: 2201 movs r2, #1
|
|
8005826: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8005828: f7fb ff58 bl 80016dc <HAL_GetTick>
|
|
800582c: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800582e: e008 b.n 8005842 <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8005830: f7fb ff54 bl 80016dc <HAL_GetTick>
|
|
8005834: 4602 mov r2, r0
|
|
8005836: 697b ldr r3, [r7, #20]
|
|
8005838: 1ad3 subs r3, r2, r3
|
|
800583a: 2b02 cmp r3, #2
|
|
800583c: d901 bls.n 8005842 <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800583e: 2303 movs r3, #3
|
|
8005840: e0a4 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
8005842: 4b18 ldr r3, [pc, #96] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005844: 681b ldr r3, [r3, #0]
|
|
8005846: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
800584a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800584e: d1ef bne.n 8005830 <HAL_RCCEx_PeriphCLKConfig+0x20c>
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- RTC configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
8005850: 687b ldr r3, [r7, #4]
|
|
8005852: 681b ldr r3, [r3, #0]
|
|
8005854: f003 0320 and.w r3, r3, #32
|
|
8005858: 2b00 cmp r3, #0
|
|
800585a: f000 808b beq.w 8005974 <HAL_RCCEx_PeriphCLKConfig+0x350>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800585e: 2300 movs r3, #0
|
|
8005860: 60fb str r3, [r7, #12]
|
|
8005862: 4b10 ldr r3, [pc, #64] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005864: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005866: 4a0f ldr r2, [pc, #60] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005868: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
800586c: 6413 str r3, [r2, #64] @ 0x40
|
|
800586e: 4b0d ldr r3, [pc, #52] @ (80058a4 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005870: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005872: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8005876: 60fb str r3, [r7, #12]
|
|
8005878: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
800587a: 4b0c ldr r3, [pc, #48] @ (80058ac <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
|
800587c: 681b ldr r3, [r3, #0]
|
|
800587e: 4a0b ldr r2, [pc, #44] @ (80058ac <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
|
8005880: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8005884: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8005886: f7fb ff29 bl 80016dc <HAL_GetTick>
|
|
800588a: 6178 str r0, [r7, #20]
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
800588c: e010 b.n 80058b0 <HAL_RCCEx_PeriphCLKConfig+0x28c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
800588e: f7fb ff25 bl 80016dc <HAL_GetTick>
|
|
8005892: 4602 mov r2, r0
|
|
8005894: 697b ldr r3, [r7, #20]
|
|
8005896: 1ad3 subs r3, r2, r3
|
|
8005898: 2b02 cmp r3, #2
|
|
800589a: d909 bls.n 80058b0 <HAL_RCCEx_PeriphCLKConfig+0x28c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800589c: 2303 movs r3, #3
|
|
800589e: e075 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
80058a0: 42470068 .word 0x42470068
|
|
80058a4: 40023800 .word 0x40023800
|
|
80058a8: 42470070 .word 0x42470070
|
|
80058ac: 40007000 .word 0x40007000
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
80058b0: 4b38 ldr r3, [pc, #224] @ (8005994 <HAL_RCCEx_PeriphCLKConfig+0x370>)
|
|
80058b2: 681b ldr r3, [r3, #0]
|
|
80058b4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80058b8: 2b00 cmp r3, #0
|
|
80058ba: d0e8 beq.n 800588e <HAL_RCCEx_PeriphCLKConfig+0x26a>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80058bc: 4b36 ldr r3, [pc, #216] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
80058be: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80058c0: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80058c4: 613b str r3, [r7, #16]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
80058c6: 693b ldr r3, [r7, #16]
|
|
80058c8: 2b00 cmp r3, #0
|
|
80058ca: d02f beq.n 800592c <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
80058cc: 687b ldr r3, [r7, #4]
|
|
80058ce: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80058d0: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80058d4: 693a ldr r2, [r7, #16]
|
|
80058d6: 429a cmp r2, r3
|
|
80058d8: d028 beq.n 800592c <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
80058da: 4b2f ldr r3, [pc, #188] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
80058dc: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80058de: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
80058e2: 613b str r3, [r7, #16]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80058e4: 4b2d ldr r3, [pc, #180] @ (800599c <HAL_RCCEx_PeriphCLKConfig+0x378>)
|
|
80058e6: 2201 movs r2, #1
|
|
80058e8: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80058ea: 4b2c ldr r3, [pc, #176] @ (800599c <HAL_RCCEx_PeriphCLKConfig+0x378>)
|
|
80058ec: 2200 movs r2, #0
|
|
80058ee: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
80058f0: 4a29 ldr r2, [pc, #164] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
80058f2: 693b ldr r3, [r7, #16]
|
|
80058f4: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
80058f6: 4b28 ldr r3, [pc, #160] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
80058f8: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80058fa: f003 0301 and.w r3, r3, #1
|
|
80058fe: 2b01 cmp r3, #1
|
|
8005900: d114 bne.n 800592c <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8005902: f7fb feeb bl 80016dc <HAL_GetTick>
|
|
8005906: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005908: e00a b.n 8005920 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800590a: f7fb fee7 bl 80016dc <HAL_GetTick>
|
|
800590e: 4602 mov r2, r0
|
|
8005910: 697b ldr r3, [r7, #20]
|
|
8005912: 1ad3 subs r3, r2, r3
|
|
8005914: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005918: 4293 cmp r3, r2
|
|
800591a: d901 bls.n 8005920 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800591c: 2303 movs r3, #3
|
|
800591e: e035 b.n 800598c <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005920: 4b1d ldr r3, [pc, #116] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005922: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005924: f003 0302 and.w r3, r3, #2
|
|
8005928: 2b00 cmp r3, #0
|
|
800592a: d0ee beq.n 800590a <HAL_RCCEx_PeriphCLKConfig+0x2e6>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
800592c: 687b ldr r3, [r7, #4]
|
|
800592e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005930: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005934: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8005938: d10d bne.n 8005956 <HAL_RCCEx_PeriphCLKConfig+0x332>
|
|
800593a: 4b17 ldr r3, [pc, #92] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800593c: 689b ldr r3, [r3, #8]
|
|
800593e: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
8005942: 687b ldr r3, [r7, #4]
|
|
8005944: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005946: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
800594a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800594e: 4912 ldr r1, [pc, #72] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005950: 4313 orrs r3, r2
|
|
8005952: 608b str r3, [r1, #8]
|
|
8005954: e005 b.n 8005962 <HAL_RCCEx_PeriphCLKConfig+0x33e>
|
|
8005956: 4b10 ldr r3, [pc, #64] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005958: 689b ldr r3, [r3, #8]
|
|
800595a: 4a0f ldr r2, [pc, #60] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800595c: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
8005960: 6093 str r3, [r2, #8]
|
|
8005962: 4b0d ldr r3, [pc, #52] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005964: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
8005966: 687b ldr r3, [r7, #4]
|
|
8005968: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800596a: f3c3 030b ubfx r3, r3, #0, #12
|
|
800596e: 490a ldr r1, [pc, #40] @ (8005998 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005970: 4313 orrs r3, r2
|
|
8005972: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
8005974: 687b ldr r3, [r7, #4]
|
|
8005976: 681b ldr r3, [r3, #0]
|
|
8005978: f003 0310 and.w r3, r3, #16
|
|
800597c: 2b00 cmp r3, #0
|
|
800597e: d004 beq.n 800598a <HAL_RCCEx_PeriphCLKConfig+0x366>
|
|
{
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
8005980: 687b ldr r3, [r7, #4]
|
|
8005982: f893 202c ldrb.w r2, [r3, #44] @ 0x2c
|
|
8005986: 4b06 ldr r3, [pc, #24] @ (80059a0 <HAL_RCCEx_PeriphCLKConfig+0x37c>)
|
|
8005988: 601a str r2, [r3, #0]
|
|
}
|
|
return HAL_OK;
|
|
800598a: 2300 movs r3, #0
|
|
}
|
|
800598c: 4618 mov r0, r3
|
|
800598e: 3718 adds r7, #24
|
|
8005990: 46bd mov sp, r7
|
|
8005992: bd80 pop {r7, pc}
|
|
8005994: 40007000 .word 0x40007000
|
|
8005998: 40023800 .word 0x40023800
|
|
800599c: 42470e40 .word 0x42470e40
|
|
80059a0: 424711e0 .word 0x424711e0
|
|
|
|
080059a4 <HAL_SDRAM_Init>:
|
|
* the configuration information for SDRAM module.
|
|
* @param Timing Pointer to SDRAM control timing structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
|
|
{
|
|
80059a4: b580 push {r7, lr}
|
|
80059a6: b082 sub sp, #8
|
|
80059a8: af00 add r7, sp, #0
|
|
80059aa: 6078 str r0, [r7, #4]
|
|
80059ac: 6039 str r1, [r7, #0]
|
|
/* Check the SDRAM handle parameter */
|
|
if (hsdram == NULL)
|
|
80059ae: 687b ldr r3, [r7, #4]
|
|
80059b0: 2b00 cmp r3, #0
|
|
80059b2: d101 bne.n 80059b8 <HAL_SDRAM_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80059b4: 2301 movs r3, #1
|
|
80059b6: e025 b.n 8005a04 <HAL_SDRAM_Init+0x60>
|
|
}
|
|
|
|
if (hsdram->State == HAL_SDRAM_STATE_RESET)
|
|
80059b8: 687b ldr r3, [r7, #4]
|
|
80059ba: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
80059be: b2db uxtb r3, r3
|
|
80059c0: 2b00 cmp r3, #0
|
|
80059c2: d106 bne.n 80059d2 <HAL_SDRAM_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hsdram->Lock = HAL_UNLOCKED;
|
|
80059c4: 687b ldr r3, [r7, #4]
|
|
80059c6: 2200 movs r2, #0
|
|
80059c8: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Init the low level hardware */
|
|
hsdram->MspInitCallback(hsdram);
|
|
#else
|
|
/* Initialize the low level hardware (MSP) */
|
|
HAL_SDRAM_MspInit(hsdram);
|
|
80059cc: 6878 ldr r0, [r7, #4]
|
|
80059ce: f7fb fd13 bl 80013f8 <HAL_SDRAM_MspInit>
|
|
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Initialize the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
80059d2: 687b ldr r3, [r7, #4]
|
|
80059d4: 2202 movs r2, #2
|
|
80059d6: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
/* Initialize SDRAM control Interface */
|
|
(void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
|
|
80059da: 687b ldr r3, [r7, #4]
|
|
80059dc: 681a ldr r2, [r3, #0]
|
|
80059de: 687b ldr r3, [r7, #4]
|
|
80059e0: 3304 adds r3, #4
|
|
80059e2: 4619 mov r1, r3
|
|
80059e4: 4610 mov r0, r2
|
|
80059e6: f000 ffcd bl 8006984 <FMC_SDRAM_Init>
|
|
|
|
/* Initialize SDRAM timing Interface */
|
|
(void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
|
|
80059ea: 687b ldr r3, [r7, #4]
|
|
80059ec: 6818 ldr r0, [r3, #0]
|
|
80059ee: 687b ldr r3, [r7, #4]
|
|
80059f0: 685b ldr r3, [r3, #4]
|
|
80059f2: 461a mov r2, r3
|
|
80059f4: 6839 ldr r1, [r7, #0]
|
|
80059f6: f001 f822 bl 8006a3e <FMC_SDRAM_Timing_Init>
|
|
/* Update the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
80059fa: 687b ldr r3, [r7, #4]
|
|
80059fc: 2201 movs r2, #1
|
|
80059fe: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
8005a02: 2300 movs r3, #0
|
|
}
|
|
8005a04: 4618 mov r0, r3
|
|
8005a06: 3708 adds r7, #8
|
|
8005a08: 46bd mov sp, r7
|
|
8005a0a: bd80 pop {r7, pc}
|
|
|
|
08005a0c <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8005a0c: b580 push {r7, lr}
|
|
8005a0e: b082 sub sp, #8
|
|
8005a10: af00 add r7, sp, #0
|
|
8005a12: 6078 str r0, [r7, #4]
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
8005a14: 687b ldr r3, [r7, #4]
|
|
8005a16: 2b00 cmp r3, #0
|
|
8005a18: d101 bne.n 8005a1e <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005a1a: 2301 movs r3, #1
|
|
8005a1c: e07b b.n 8005b16 <HAL_SPI_Init+0x10a>
|
|
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
8005a1e: 687b ldr r3, [r7, #4]
|
|
8005a20: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005a22: 2b00 cmp r3, #0
|
|
8005a24: d108 bne.n 8005a38 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8005a26: 687b ldr r3, [r7, #4]
|
|
8005a28: 685b ldr r3, [r3, #4]
|
|
8005a2a: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
8005a2e: d009 beq.n 8005a44 <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
8005a30: 687b ldr r3, [r7, #4]
|
|
8005a32: 2200 movs r2, #0
|
|
8005a34: 61da str r2, [r3, #28]
|
|
8005a36: e005 b.n 8005a44 <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8005a38: 687b ldr r3, [r7, #4]
|
|
8005a3a: 2200 movs r2, #0
|
|
8005a3c: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8005a3e: 687b ldr r3, [r7, #4]
|
|
8005a40: 2200 movs r2, #0
|
|
8005a42: 615a str r2, [r3, #20]
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8005a44: 687b ldr r3, [r7, #4]
|
|
8005a46: 2200 movs r2, #0
|
|
8005a48: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
8005a4a: 687b ldr r3, [r7, #4]
|
|
8005a4c: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
8005a50: b2db uxtb r3, r3
|
|
8005a52: 2b00 cmp r3, #0
|
|
8005a54: d106 bne.n 8005a64 <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
8005a56: 687b ldr r3, [r7, #4]
|
|
8005a58: 2200 movs r2, #0
|
|
8005a5a: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
8005a5e: 6878 ldr r0, [r7, #4]
|
|
8005a60: f7fb fb86 bl 8001170 <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8005a64: 687b ldr r3, [r7, #4]
|
|
8005a66: 2202 movs r2, #2
|
|
8005a68: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8005a6c: 687b ldr r3, [r7, #4]
|
|
8005a6e: 681b ldr r3, [r3, #0]
|
|
8005a70: 681a ldr r2, [r3, #0]
|
|
8005a72: 687b ldr r3, [r7, #4]
|
|
8005a74: 681b ldr r3, [r3, #0]
|
|
8005a76: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
8005a7a: 601a str r2, [r3, #0]
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
8005a7c: 687b ldr r3, [r7, #4]
|
|
8005a7e: 685b ldr r3, [r3, #4]
|
|
8005a80: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
8005a84: 687b ldr r3, [r7, #4]
|
|
8005a86: 689b ldr r3, [r3, #8]
|
|
8005a88: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
8005a8c: 431a orrs r2, r3
|
|
8005a8e: 687b ldr r3, [r7, #4]
|
|
8005a90: 68db ldr r3, [r3, #12]
|
|
8005a92: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8005a96: 431a orrs r2, r3
|
|
8005a98: 687b ldr r3, [r7, #4]
|
|
8005a9a: 691b ldr r3, [r3, #16]
|
|
8005a9c: f003 0302 and.w r3, r3, #2
|
|
8005aa0: 431a orrs r2, r3
|
|
8005aa2: 687b ldr r3, [r7, #4]
|
|
8005aa4: 695b ldr r3, [r3, #20]
|
|
8005aa6: f003 0301 and.w r3, r3, #1
|
|
8005aaa: 431a orrs r2, r3
|
|
8005aac: 687b ldr r3, [r7, #4]
|
|
8005aae: 699b ldr r3, [r3, #24]
|
|
8005ab0: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8005ab4: 431a orrs r2, r3
|
|
8005ab6: 687b ldr r3, [r7, #4]
|
|
8005ab8: 69db ldr r3, [r3, #28]
|
|
8005aba: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
8005abe: 431a orrs r2, r3
|
|
8005ac0: 687b ldr r3, [r7, #4]
|
|
8005ac2: 6a1b ldr r3, [r3, #32]
|
|
8005ac4: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005ac8: ea42 0103 orr.w r1, r2, r3
|
|
8005acc: 687b ldr r3, [r7, #4]
|
|
8005ace: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005ad0: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
8005ad4: 687b ldr r3, [r7, #4]
|
|
8005ad6: 681b ldr r3, [r3, #0]
|
|
8005ad8: 430a orrs r2, r1
|
|
8005ada: 601a str r2, [r3, #0]
|
|
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
|
|
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
|
|
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
|
|
|
|
/* Configure : NSS management, TI Mode */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
|
|
8005adc: 687b ldr r3, [r7, #4]
|
|
8005ade: 699b ldr r3, [r3, #24]
|
|
8005ae0: 0c1b lsrs r3, r3, #16
|
|
8005ae2: f003 0104 and.w r1, r3, #4
|
|
8005ae6: 687b ldr r3, [r7, #4]
|
|
8005ae8: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005aea: f003 0210 and.w r2, r3, #16
|
|
8005aee: 687b ldr r3, [r7, #4]
|
|
8005af0: 681b ldr r3, [r3, #0]
|
|
8005af2: 430a orrs r2, r1
|
|
8005af4: 605a str r2, [r3, #4]
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
8005af6: 687b ldr r3, [r7, #4]
|
|
8005af8: 681b ldr r3, [r3, #0]
|
|
8005afa: 69da ldr r2, [r3, #28]
|
|
8005afc: 687b ldr r3, [r7, #4]
|
|
8005afe: 681b ldr r3, [r3, #0]
|
|
8005b00: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8005b04: 61da str r2, [r3, #28]
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8005b06: 687b ldr r3, [r7, #4]
|
|
8005b08: 2200 movs r2, #0
|
|
8005b0a: 655a str r2, [r3, #84] @ 0x54
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8005b0c: 687b ldr r3, [r7, #4]
|
|
8005b0e: 2201 movs r2, #1
|
|
8005b10: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
return HAL_OK;
|
|
8005b14: 2300 movs r3, #0
|
|
}
|
|
8005b16: 4618 mov r0, r3
|
|
8005b18: 3708 adds r7, #8
|
|
8005b1a: 46bd mov sp, r7
|
|
8005b1c: bd80 pop {r7, pc}
|
|
|
|
08005b1e <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005b1e: b580 push {r7, lr}
|
|
8005b20: b082 sub sp, #8
|
|
8005b22: af00 add r7, sp, #0
|
|
8005b24: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8005b26: 687b ldr r3, [r7, #4]
|
|
8005b28: 2b00 cmp r3, #0
|
|
8005b2a: d101 bne.n 8005b30 <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005b2c: 2301 movs r3, #1
|
|
8005b2e: e041 b.n 8005bb4 <HAL_TIM_Base_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8005b30: 687b ldr r3, [r7, #4]
|
|
8005b32: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8005b36: b2db uxtb r3, r3
|
|
8005b38: 2b00 cmp r3, #0
|
|
8005b3a: d106 bne.n 8005b4a <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8005b3c: 687b ldr r3, [r7, #4]
|
|
8005b3e: 2200 movs r2, #0
|
|
8005b40: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
8005b44: 6878 ldr r0, [r7, #4]
|
|
8005b46: f7fb fb5b bl 8001200 <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005b4a: 687b ldr r3, [r7, #4]
|
|
8005b4c: 2202 movs r2, #2
|
|
8005b4e: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8005b52: 687b ldr r3, [r7, #4]
|
|
8005b54: 681a ldr r2, [r3, #0]
|
|
8005b56: 687b ldr r3, [r7, #4]
|
|
8005b58: 3304 adds r3, #4
|
|
8005b5a: 4619 mov r1, r3
|
|
8005b5c: 4610 mov r0, r2
|
|
8005b5e: f000 fa7d bl 800605c <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8005b62: 687b ldr r3, [r7, #4]
|
|
8005b64: 2201 movs r2, #1
|
|
8005b66: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005b6a: 687b ldr r3, [r7, #4]
|
|
8005b6c: 2201 movs r2, #1
|
|
8005b6e: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
8005b72: 687b ldr r3, [r7, #4]
|
|
8005b74: 2201 movs r2, #1
|
|
8005b76: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
8005b7a: 687b ldr r3, [r7, #4]
|
|
8005b7c: 2201 movs r2, #1
|
|
8005b7e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
8005b82: 687b ldr r3, [r7, #4]
|
|
8005b84: 2201 movs r2, #1
|
|
8005b86: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005b8a: 687b ldr r3, [r7, #4]
|
|
8005b8c: 2201 movs r2, #1
|
|
8005b8e: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
8005b92: 687b ldr r3, [r7, #4]
|
|
8005b94: 2201 movs r2, #1
|
|
8005b96: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
8005b9a: 687b ldr r3, [r7, #4]
|
|
8005b9c: 2201 movs r2, #1
|
|
8005b9e: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8005ba2: 687b ldr r3, [r7, #4]
|
|
8005ba4: 2201 movs r2, #1
|
|
8005ba6: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005baa: 687b ldr r3, [r7, #4]
|
|
8005bac: 2201 movs r2, #1
|
|
8005bae: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8005bb2: 2300 movs r3, #0
|
|
}
|
|
8005bb4: 4618 mov r0, r3
|
|
8005bb6: 3708 adds r7, #8
|
|
8005bb8: 46bd mov sp, r7
|
|
8005bba: bd80 pop {r7, pc}
|
|
|
|
08005bbc <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005bbc: b480 push {r7}
|
|
8005bbe: b085 sub sp, #20
|
|
8005bc0: af00 add r7, sp, #0
|
|
8005bc2: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
8005bc4: 687b ldr r3, [r7, #4]
|
|
8005bc6: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8005bca: b2db uxtb r3, r3
|
|
8005bcc: 2b01 cmp r3, #1
|
|
8005bce: d001 beq.n 8005bd4 <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
8005bd0: 2301 movs r3, #1
|
|
8005bd2: e04e b.n 8005c72 <HAL_TIM_Base_Start_IT+0xb6>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005bd4: 687b ldr r3, [r7, #4]
|
|
8005bd6: 2202 movs r2, #2
|
|
8005bd8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
8005bdc: 687b ldr r3, [r7, #4]
|
|
8005bde: 681b ldr r3, [r3, #0]
|
|
8005be0: 68da ldr r2, [r3, #12]
|
|
8005be2: 687b ldr r3, [r7, #4]
|
|
8005be4: 681b ldr r3, [r3, #0]
|
|
8005be6: f042 0201 orr.w r2, r2, #1
|
|
8005bea: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005bec: 687b ldr r3, [r7, #4]
|
|
8005bee: 681b ldr r3, [r3, #0]
|
|
8005bf0: 4a23 ldr r2, [pc, #140] @ (8005c80 <HAL_TIM_Base_Start_IT+0xc4>)
|
|
8005bf2: 4293 cmp r3, r2
|
|
8005bf4: d022 beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005bf6: 687b ldr r3, [r7, #4]
|
|
8005bf8: 681b ldr r3, [r3, #0]
|
|
8005bfa: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005bfe: d01d beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c00: 687b ldr r3, [r7, #4]
|
|
8005c02: 681b ldr r3, [r3, #0]
|
|
8005c04: 4a1f ldr r2, [pc, #124] @ (8005c84 <HAL_TIM_Base_Start_IT+0xc8>)
|
|
8005c06: 4293 cmp r3, r2
|
|
8005c08: d018 beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c0a: 687b ldr r3, [r7, #4]
|
|
8005c0c: 681b ldr r3, [r3, #0]
|
|
8005c0e: 4a1e ldr r2, [pc, #120] @ (8005c88 <HAL_TIM_Base_Start_IT+0xcc>)
|
|
8005c10: 4293 cmp r3, r2
|
|
8005c12: d013 beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c14: 687b ldr r3, [r7, #4]
|
|
8005c16: 681b ldr r3, [r3, #0]
|
|
8005c18: 4a1c ldr r2, [pc, #112] @ (8005c8c <HAL_TIM_Base_Start_IT+0xd0>)
|
|
8005c1a: 4293 cmp r3, r2
|
|
8005c1c: d00e beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c1e: 687b ldr r3, [r7, #4]
|
|
8005c20: 681b ldr r3, [r3, #0]
|
|
8005c22: 4a1b ldr r2, [pc, #108] @ (8005c90 <HAL_TIM_Base_Start_IT+0xd4>)
|
|
8005c24: 4293 cmp r3, r2
|
|
8005c26: d009 beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c28: 687b ldr r3, [r7, #4]
|
|
8005c2a: 681b ldr r3, [r3, #0]
|
|
8005c2c: 4a19 ldr r2, [pc, #100] @ (8005c94 <HAL_TIM_Base_Start_IT+0xd8>)
|
|
8005c2e: 4293 cmp r3, r2
|
|
8005c30: d004 beq.n 8005c3c <HAL_TIM_Base_Start_IT+0x80>
|
|
8005c32: 687b ldr r3, [r7, #4]
|
|
8005c34: 681b ldr r3, [r3, #0]
|
|
8005c36: 4a18 ldr r2, [pc, #96] @ (8005c98 <HAL_TIM_Base_Start_IT+0xdc>)
|
|
8005c38: 4293 cmp r3, r2
|
|
8005c3a: d111 bne.n 8005c60 <HAL_TIM_Base_Start_IT+0xa4>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8005c3c: 687b ldr r3, [r7, #4]
|
|
8005c3e: 681b ldr r3, [r3, #0]
|
|
8005c40: 689b ldr r3, [r3, #8]
|
|
8005c42: f003 0307 and.w r3, r3, #7
|
|
8005c46: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8005c48: 68fb ldr r3, [r7, #12]
|
|
8005c4a: 2b06 cmp r3, #6
|
|
8005c4c: d010 beq.n 8005c70 <HAL_TIM_Base_Start_IT+0xb4>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8005c4e: 687b ldr r3, [r7, #4]
|
|
8005c50: 681b ldr r3, [r3, #0]
|
|
8005c52: 681a ldr r2, [r3, #0]
|
|
8005c54: 687b ldr r3, [r7, #4]
|
|
8005c56: 681b ldr r3, [r3, #0]
|
|
8005c58: f042 0201 orr.w r2, r2, #1
|
|
8005c5c: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8005c5e: e007 b.n 8005c70 <HAL_TIM_Base_Start_IT+0xb4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
8005c60: 687b ldr r3, [r7, #4]
|
|
8005c62: 681b ldr r3, [r3, #0]
|
|
8005c64: 681a ldr r2, [r3, #0]
|
|
8005c66: 687b ldr r3, [r7, #4]
|
|
8005c68: 681b ldr r3, [r3, #0]
|
|
8005c6a: f042 0201 orr.w r2, r2, #1
|
|
8005c6e: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
8005c70: 2300 movs r3, #0
|
|
}
|
|
8005c72: 4618 mov r0, r3
|
|
8005c74: 3714 adds r7, #20
|
|
8005c76: 46bd mov sp, r7
|
|
8005c78: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c7c: 4770 bx lr
|
|
8005c7e: bf00 nop
|
|
8005c80: 40010000 .word 0x40010000
|
|
8005c84: 40000400 .word 0x40000400
|
|
8005c88: 40000800 .word 0x40000800
|
|
8005c8c: 40000c00 .word 0x40000c00
|
|
8005c90: 40010400 .word 0x40010400
|
|
8005c94: 40014000 .word 0x40014000
|
|
8005c98: 40001800 .word 0x40001800
|
|
|
|
08005c9c <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005c9c: b580 push {r7, lr}
|
|
8005c9e: b084 sub sp, #16
|
|
8005ca0: af00 add r7, sp, #0
|
|
8005ca2: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
8005ca4: 687b ldr r3, [r7, #4]
|
|
8005ca6: 681b ldr r3, [r3, #0]
|
|
8005ca8: 68db ldr r3, [r3, #12]
|
|
8005caa: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
8005cac: 687b ldr r3, [r7, #4]
|
|
8005cae: 681b ldr r3, [r3, #0]
|
|
8005cb0: 691b ldr r3, [r3, #16]
|
|
8005cb2: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
8005cb4: 68bb ldr r3, [r7, #8]
|
|
8005cb6: f003 0302 and.w r3, r3, #2
|
|
8005cba: 2b00 cmp r3, #0
|
|
8005cbc: d020 beq.n 8005d00 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
8005cbe: 68fb ldr r3, [r7, #12]
|
|
8005cc0: f003 0302 and.w r3, r3, #2
|
|
8005cc4: 2b00 cmp r3, #0
|
|
8005cc6: d01b beq.n 8005d00 <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
8005cc8: 687b ldr r3, [r7, #4]
|
|
8005cca: 681b ldr r3, [r3, #0]
|
|
8005ccc: f06f 0202 mvn.w r2, #2
|
|
8005cd0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
8005cd2: 687b ldr r3, [r7, #4]
|
|
8005cd4: 2201 movs r2, #1
|
|
8005cd6: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
8005cd8: 687b ldr r3, [r7, #4]
|
|
8005cda: 681b ldr r3, [r3, #0]
|
|
8005cdc: 699b ldr r3, [r3, #24]
|
|
8005cde: f003 0303 and.w r3, r3, #3
|
|
8005ce2: 2b00 cmp r3, #0
|
|
8005ce4: d003 beq.n 8005cee <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005ce6: 6878 ldr r0, [r7, #4]
|
|
8005ce8: f000 f999 bl 800601e <HAL_TIM_IC_CaptureCallback>
|
|
8005cec: e005 b.n 8005cfa <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005cee: 6878 ldr r0, [r7, #4]
|
|
8005cf0: f000 f98b bl 800600a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005cf4: 6878 ldr r0, [r7, #4]
|
|
8005cf6: f000 f99c bl 8006032 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005cfa: 687b ldr r3, [r7, #4]
|
|
8005cfc: 2200 movs r2, #0
|
|
8005cfe: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
8005d00: 68bb ldr r3, [r7, #8]
|
|
8005d02: f003 0304 and.w r3, r3, #4
|
|
8005d06: 2b00 cmp r3, #0
|
|
8005d08: d020 beq.n 8005d4c <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8005d0a: 68fb ldr r3, [r7, #12]
|
|
8005d0c: f003 0304 and.w r3, r3, #4
|
|
8005d10: 2b00 cmp r3, #0
|
|
8005d12: d01b beq.n 8005d4c <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8005d14: 687b ldr r3, [r7, #4]
|
|
8005d16: 681b ldr r3, [r3, #0]
|
|
8005d18: f06f 0204 mvn.w r2, #4
|
|
8005d1c: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
8005d1e: 687b ldr r3, [r7, #4]
|
|
8005d20: 2202 movs r2, #2
|
|
8005d22: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8005d24: 687b ldr r3, [r7, #4]
|
|
8005d26: 681b ldr r3, [r3, #0]
|
|
8005d28: 699b ldr r3, [r3, #24]
|
|
8005d2a: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005d2e: 2b00 cmp r3, #0
|
|
8005d30: d003 beq.n 8005d3a <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005d32: 6878 ldr r0, [r7, #4]
|
|
8005d34: f000 f973 bl 800601e <HAL_TIM_IC_CaptureCallback>
|
|
8005d38: e005 b.n 8005d46 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005d3a: 6878 ldr r0, [r7, #4]
|
|
8005d3c: f000 f965 bl 800600a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005d40: 6878 ldr r0, [r7, #4]
|
|
8005d42: f000 f976 bl 8006032 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005d46: 687b ldr r3, [r7, #4]
|
|
8005d48: 2200 movs r2, #0
|
|
8005d4a: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8005d4c: 68bb ldr r3, [r7, #8]
|
|
8005d4e: f003 0308 and.w r3, r3, #8
|
|
8005d52: 2b00 cmp r3, #0
|
|
8005d54: d020 beq.n 8005d98 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8005d56: 68fb ldr r3, [r7, #12]
|
|
8005d58: f003 0308 and.w r3, r3, #8
|
|
8005d5c: 2b00 cmp r3, #0
|
|
8005d5e: d01b beq.n 8005d98 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
8005d60: 687b ldr r3, [r7, #4]
|
|
8005d62: 681b ldr r3, [r3, #0]
|
|
8005d64: f06f 0208 mvn.w r2, #8
|
|
8005d68: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8005d6a: 687b ldr r3, [r7, #4]
|
|
8005d6c: 2204 movs r2, #4
|
|
8005d6e: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
8005d70: 687b ldr r3, [r7, #4]
|
|
8005d72: 681b ldr r3, [r3, #0]
|
|
8005d74: 69db ldr r3, [r3, #28]
|
|
8005d76: f003 0303 and.w r3, r3, #3
|
|
8005d7a: 2b00 cmp r3, #0
|
|
8005d7c: d003 beq.n 8005d86 <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005d7e: 6878 ldr r0, [r7, #4]
|
|
8005d80: f000 f94d bl 800601e <HAL_TIM_IC_CaptureCallback>
|
|
8005d84: e005 b.n 8005d92 <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005d86: 6878 ldr r0, [r7, #4]
|
|
8005d88: f000 f93f bl 800600a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005d8c: 6878 ldr r0, [r7, #4]
|
|
8005d8e: f000 f950 bl 8006032 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005d92: 687b ldr r3, [r7, #4]
|
|
8005d94: 2200 movs r2, #0
|
|
8005d96: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
8005d98: 68bb ldr r3, [r7, #8]
|
|
8005d9a: f003 0310 and.w r3, r3, #16
|
|
8005d9e: 2b00 cmp r3, #0
|
|
8005da0: d020 beq.n 8005de4 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
8005da2: 68fb ldr r3, [r7, #12]
|
|
8005da4: f003 0310 and.w r3, r3, #16
|
|
8005da8: 2b00 cmp r3, #0
|
|
8005daa: d01b beq.n 8005de4 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
8005dac: 687b ldr r3, [r7, #4]
|
|
8005dae: 681b ldr r3, [r3, #0]
|
|
8005db0: f06f 0210 mvn.w r2, #16
|
|
8005db4: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
8005db6: 687b ldr r3, [r7, #4]
|
|
8005db8: 2208 movs r2, #8
|
|
8005dba: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
8005dbc: 687b ldr r3, [r7, #4]
|
|
8005dbe: 681b ldr r3, [r3, #0]
|
|
8005dc0: 69db ldr r3, [r3, #28]
|
|
8005dc2: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005dc6: 2b00 cmp r3, #0
|
|
8005dc8: d003 beq.n 8005dd2 <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005dca: 6878 ldr r0, [r7, #4]
|
|
8005dcc: f000 f927 bl 800601e <HAL_TIM_IC_CaptureCallback>
|
|
8005dd0: e005 b.n 8005dde <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005dd2: 6878 ldr r0, [r7, #4]
|
|
8005dd4: f000 f919 bl 800600a <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005dd8: 6878 ldr r0, [r7, #4]
|
|
8005dda: f000 f92a bl 8006032 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005dde: 687b ldr r3, [r7, #4]
|
|
8005de0: 2200 movs r2, #0
|
|
8005de2: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
8005de4: 68bb ldr r3, [r7, #8]
|
|
8005de6: f003 0301 and.w r3, r3, #1
|
|
8005dea: 2b00 cmp r3, #0
|
|
8005dec: d00c beq.n 8005e08 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
8005dee: 68fb ldr r3, [r7, #12]
|
|
8005df0: f003 0301 and.w r3, r3, #1
|
|
8005df4: 2b00 cmp r3, #0
|
|
8005df6: d007 beq.n 8005e08 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8005df8: 687b ldr r3, [r7, #4]
|
|
8005dfa: 681b ldr r3, [r3, #0]
|
|
8005dfc: f06f 0201 mvn.w r2, #1
|
|
8005e00: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8005e02: 6878 ldr r0, [r7, #4]
|
|
8005e04: f7fa ff8c bl 8000d20 <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
|
8005e08: 68bb ldr r3, [r7, #8]
|
|
8005e0a: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005e0e: 2b00 cmp r3, #0
|
|
8005e10: d00c beq.n 8005e2c <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8005e12: 68fb ldr r3, [r7, #12]
|
|
8005e14: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005e18: 2b00 cmp r3, #0
|
|
8005e1a: d007 beq.n 8005e2c <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
|
|
8005e1c: 687b ldr r3, [r7, #4]
|
|
8005e1e: 681b ldr r3, [r3, #0]
|
|
8005e20: f06f 0280 mvn.w r2, #128 @ 0x80
|
|
8005e24: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8005e26: 6878 ldr r0, [r7, #4]
|
|
8005e28: f000 fade bl 80063e8 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
8005e2c: 68bb ldr r3, [r7, #8]
|
|
8005e2e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005e32: 2b00 cmp r3, #0
|
|
8005e34: d00c beq.n 8005e50 <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8005e36: 68fb ldr r3, [r7, #12]
|
|
8005e38: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005e3c: 2b00 cmp r3, #0
|
|
8005e3e: d007 beq.n 8005e50 <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8005e40: 687b ldr r3, [r7, #4]
|
|
8005e42: 681b ldr r3, [r3, #0]
|
|
8005e44: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8005e48: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8005e4a: 6878 ldr r0, [r7, #4]
|
|
8005e4c: f000 f8fb bl 8006046 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8005e50: 68bb ldr r3, [r7, #8]
|
|
8005e52: f003 0320 and.w r3, r3, #32
|
|
8005e56: 2b00 cmp r3, #0
|
|
8005e58: d00c beq.n 8005e74 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
8005e5a: 68fb ldr r3, [r7, #12]
|
|
8005e5c: f003 0320 and.w r3, r3, #32
|
|
8005e60: 2b00 cmp r3, #0
|
|
8005e62: d007 beq.n 8005e74 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8005e64: 687b ldr r3, [r7, #4]
|
|
8005e66: 681b ldr r3, [r3, #0]
|
|
8005e68: f06f 0220 mvn.w r2, #32
|
|
8005e6c: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8005e6e: 6878 ldr r0, [r7, #4]
|
|
8005e70: f000 fab0 bl 80063d4 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
8005e74: bf00 nop
|
|
8005e76: 3710 adds r7, #16
|
|
8005e78: 46bd mov sp, r7
|
|
8005e7a: bd80 pop {r7, pc}
|
|
|
|
08005e7c <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
8005e7c: b580 push {r7, lr}
|
|
8005e7e: b084 sub sp, #16
|
|
8005e80: af00 add r7, sp, #0
|
|
8005e82: 6078 str r0, [r7, #4]
|
|
8005e84: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8005e86: 2300 movs r3, #0
|
|
8005e88: 73fb strb r3, [r7, #15]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
8005e8a: 687b ldr r3, [r7, #4]
|
|
8005e8c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005e90: 2b01 cmp r3, #1
|
|
8005e92: d101 bne.n 8005e98 <HAL_TIM_ConfigClockSource+0x1c>
|
|
8005e94: 2302 movs r3, #2
|
|
8005e96: e0b4 b.n 8006002 <HAL_TIM_ConfigClockSource+0x186>
|
|
8005e98: 687b ldr r3, [r7, #4]
|
|
8005e9a: 2201 movs r2, #1
|
|
8005e9c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005ea0: 687b ldr r3, [r7, #4]
|
|
8005ea2: 2202 movs r2, #2
|
|
8005ea4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005ea8: 687b ldr r3, [r7, #4]
|
|
8005eaa: 681b ldr r3, [r3, #0]
|
|
8005eac: 689b ldr r3, [r3, #8]
|
|
8005eae: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
8005eb0: 68bb ldr r3, [r7, #8]
|
|
8005eb2: f023 0377 bic.w r3, r3, #119 @ 0x77
|
|
8005eb6: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8005eb8: 68bb ldr r3, [r7, #8]
|
|
8005eba: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8005ebe: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005ec0: 687b ldr r3, [r7, #4]
|
|
8005ec2: 681b ldr r3, [r3, #0]
|
|
8005ec4: 68ba ldr r2, [r7, #8]
|
|
8005ec6: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
8005ec8: 683b ldr r3, [r7, #0]
|
|
8005eca: 681b ldr r3, [r3, #0]
|
|
8005ecc: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005ed0: d03e beq.n 8005f50 <HAL_TIM_ConfigClockSource+0xd4>
|
|
8005ed2: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005ed6: f200 8087 bhi.w 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005eda: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005ede: f000 8086 beq.w 8005fee <HAL_TIM_ConfigClockSource+0x172>
|
|
8005ee2: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005ee6: d87f bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005ee8: 2b70 cmp r3, #112 @ 0x70
|
|
8005eea: d01a beq.n 8005f22 <HAL_TIM_ConfigClockSource+0xa6>
|
|
8005eec: 2b70 cmp r3, #112 @ 0x70
|
|
8005eee: d87b bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005ef0: 2b60 cmp r3, #96 @ 0x60
|
|
8005ef2: d050 beq.n 8005f96 <HAL_TIM_ConfigClockSource+0x11a>
|
|
8005ef4: 2b60 cmp r3, #96 @ 0x60
|
|
8005ef6: d877 bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005ef8: 2b50 cmp r3, #80 @ 0x50
|
|
8005efa: d03c beq.n 8005f76 <HAL_TIM_ConfigClockSource+0xfa>
|
|
8005efc: 2b50 cmp r3, #80 @ 0x50
|
|
8005efe: d873 bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005f00: 2b40 cmp r3, #64 @ 0x40
|
|
8005f02: d058 beq.n 8005fb6 <HAL_TIM_ConfigClockSource+0x13a>
|
|
8005f04: 2b40 cmp r3, #64 @ 0x40
|
|
8005f06: d86f bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005f08: 2b30 cmp r3, #48 @ 0x30
|
|
8005f0a: d064 beq.n 8005fd6 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005f0c: 2b30 cmp r3, #48 @ 0x30
|
|
8005f0e: d86b bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005f10: 2b20 cmp r3, #32
|
|
8005f12: d060 beq.n 8005fd6 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005f14: 2b20 cmp r3, #32
|
|
8005f16: d867 bhi.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005f18: 2b00 cmp r3, #0
|
|
8005f1a: d05c beq.n 8005fd6 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005f1c: 2b10 cmp r3, #16
|
|
8005f1e: d05a beq.n 8005fd6 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005f20: e062 b.n 8005fe8 <HAL_TIM_ConfigClockSource+0x16c>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005f22: 687b ldr r3, [r7, #4]
|
|
8005f24: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005f26: 683b ldr r3, [r7, #0]
|
|
8005f28: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005f2a: 683b ldr r3, [r7, #0]
|
|
8005f2c: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005f2e: 683b ldr r3, [r7, #0]
|
|
8005f30: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005f32: f000 f9b3 bl 800629c <TIM_ETR_SetConfig>
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005f36: 687b ldr r3, [r7, #4]
|
|
8005f38: 681b ldr r3, [r3, #0]
|
|
8005f3a: 689b ldr r3, [r3, #8]
|
|
8005f3c: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
8005f3e: 68bb ldr r3, [r7, #8]
|
|
8005f40: f043 0377 orr.w r3, r3, #119 @ 0x77
|
|
8005f44: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005f46: 687b ldr r3, [r7, #4]
|
|
8005f48: 681b ldr r3, [r3, #0]
|
|
8005f4a: 68ba ldr r2, [r7, #8]
|
|
8005f4c: 609a str r2, [r3, #8]
|
|
break;
|
|
8005f4e: e04f b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005f50: 687b ldr r3, [r7, #4]
|
|
8005f52: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005f54: 683b ldr r3, [r7, #0]
|
|
8005f56: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005f58: 683b ldr r3, [r7, #0]
|
|
8005f5a: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005f5c: 683b ldr r3, [r7, #0]
|
|
8005f5e: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
8005f60: f000 f99c bl 800629c <TIM_ETR_SetConfig>
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
8005f64: 687b ldr r3, [r7, #4]
|
|
8005f66: 681b ldr r3, [r3, #0]
|
|
8005f68: 689a ldr r2, [r3, #8]
|
|
8005f6a: 687b ldr r3, [r7, #4]
|
|
8005f6c: 681b ldr r3, [r3, #0]
|
|
8005f6e: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
8005f72: 609a str r2, [r3, #8]
|
|
break;
|
|
8005f74: e03c b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005f76: 687b ldr r3, [r7, #4]
|
|
8005f78: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005f7a: 683b ldr r3, [r7, #0]
|
|
8005f7c: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005f7e: 683b ldr r3, [r7, #0]
|
|
8005f80: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005f82: 461a mov r2, r3
|
|
8005f84: f000 f910 bl 80061a8 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
8005f88: 687b ldr r3, [r7, #4]
|
|
8005f8a: 681b ldr r3, [r3, #0]
|
|
8005f8c: 2150 movs r1, #80 @ 0x50
|
|
8005f8e: 4618 mov r0, r3
|
|
8005f90: f000 f969 bl 8006266 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005f94: e02c b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
8005f96: 687b ldr r3, [r7, #4]
|
|
8005f98: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005f9a: 683b ldr r3, [r7, #0]
|
|
8005f9c: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005f9e: 683b ldr r3, [r7, #0]
|
|
8005fa0: 68db ldr r3, [r3, #12]
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
8005fa2: 461a mov r2, r3
|
|
8005fa4: f000 f92f bl 8006206 <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
8005fa8: 687b ldr r3, [r7, #4]
|
|
8005faa: 681b ldr r3, [r3, #0]
|
|
8005fac: 2160 movs r1, #96 @ 0x60
|
|
8005fae: 4618 mov r0, r3
|
|
8005fb0: f000 f959 bl 8006266 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005fb4: e01c b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005fb6: 687b ldr r3, [r7, #4]
|
|
8005fb8: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005fba: 683b ldr r3, [r7, #0]
|
|
8005fbc: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005fbe: 683b ldr r3, [r7, #0]
|
|
8005fc0: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
8005fc2: 461a mov r2, r3
|
|
8005fc4: f000 f8f0 bl 80061a8 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
8005fc8: 687b ldr r3, [r7, #4]
|
|
8005fca: 681b ldr r3, [r3, #0]
|
|
8005fcc: 2140 movs r1, #64 @ 0x40
|
|
8005fce: 4618 mov r0, r3
|
|
8005fd0: f000 f949 bl 8006266 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005fd4: e00c b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
8005fd6: 687b ldr r3, [r7, #4]
|
|
8005fd8: 681a ldr r2, [r3, #0]
|
|
8005fda: 683b ldr r3, [r7, #0]
|
|
8005fdc: 681b ldr r3, [r3, #0]
|
|
8005fde: 4619 mov r1, r3
|
|
8005fe0: 4610 mov r0, r2
|
|
8005fe2: f000 f940 bl 8006266 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005fe6: e003 b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005fe8: 2301 movs r3, #1
|
|
8005fea: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8005fec: e000 b.n 8005ff0 <HAL_TIM_ConfigClockSource+0x174>
|
|
break;
|
|
8005fee: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005ff0: 687b ldr r3, [r7, #4]
|
|
8005ff2: 2201 movs r2, #1
|
|
8005ff4: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005ff8: 687b ldr r3, [r7, #4]
|
|
8005ffa: 2200 movs r2, #0
|
|
8005ffc: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
8006000: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006002: 4618 mov r0, r3
|
|
8006004: 3710 adds r7, #16
|
|
8006006: 46bd mov sp, r7
|
|
8006008: bd80 pop {r7, pc}
|
|
|
|
0800600a <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800600a: b480 push {r7}
|
|
800600c: b083 sub sp, #12
|
|
800600e: af00 add r7, sp, #0
|
|
8006010: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006012: bf00 nop
|
|
8006014: 370c adds r7, #12
|
|
8006016: 46bd mov sp, r7
|
|
8006018: f85d 7b04 ldr.w r7, [sp], #4
|
|
800601c: 4770 bx lr
|
|
|
|
0800601e <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800601e: b480 push {r7}
|
|
8006020: b083 sub sp, #12
|
|
8006022: af00 add r7, sp, #0
|
|
8006024: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8006026: bf00 nop
|
|
8006028: 370c adds r7, #12
|
|
800602a: 46bd mov sp, r7
|
|
800602c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006030: 4770 bx lr
|
|
|
|
08006032 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8006032: b480 push {r7}
|
|
8006034: b083 sub sp, #12
|
|
8006036: af00 add r7, sp, #0
|
|
8006038: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800603a: bf00 nop
|
|
800603c: 370c adds r7, #12
|
|
800603e: 46bd mov sp, r7
|
|
8006040: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006044: 4770 bx lr
|
|
|
|
08006046 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8006046: b480 push {r7}
|
|
8006048: b083 sub sp, #12
|
|
800604a: af00 add r7, sp, #0
|
|
800604c: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800604e: bf00 nop
|
|
8006050: 370c adds r7, #12
|
|
8006052: 46bd mov sp, r7
|
|
8006054: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006058: 4770 bx lr
|
|
...
|
|
|
|
0800605c <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
800605c: b480 push {r7}
|
|
800605e: b085 sub sp, #20
|
|
8006060: af00 add r7, sp, #0
|
|
8006062: 6078 str r0, [r7, #4]
|
|
8006064: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
8006066: 687b ldr r3, [r7, #4]
|
|
8006068: 681b ldr r3, [r3, #0]
|
|
800606a: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
800606c: 687b ldr r3, [r7, #4]
|
|
800606e: 4a43 ldr r2, [pc, #268] @ (800617c <TIM_Base_SetConfig+0x120>)
|
|
8006070: 4293 cmp r3, r2
|
|
8006072: d013 beq.n 800609c <TIM_Base_SetConfig+0x40>
|
|
8006074: 687b ldr r3, [r7, #4]
|
|
8006076: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800607a: d00f beq.n 800609c <TIM_Base_SetConfig+0x40>
|
|
800607c: 687b ldr r3, [r7, #4]
|
|
800607e: 4a40 ldr r2, [pc, #256] @ (8006180 <TIM_Base_SetConfig+0x124>)
|
|
8006080: 4293 cmp r3, r2
|
|
8006082: d00b beq.n 800609c <TIM_Base_SetConfig+0x40>
|
|
8006084: 687b ldr r3, [r7, #4]
|
|
8006086: 4a3f ldr r2, [pc, #252] @ (8006184 <TIM_Base_SetConfig+0x128>)
|
|
8006088: 4293 cmp r3, r2
|
|
800608a: d007 beq.n 800609c <TIM_Base_SetConfig+0x40>
|
|
800608c: 687b ldr r3, [r7, #4]
|
|
800608e: 4a3e ldr r2, [pc, #248] @ (8006188 <TIM_Base_SetConfig+0x12c>)
|
|
8006090: 4293 cmp r3, r2
|
|
8006092: d003 beq.n 800609c <TIM_Base_SetConfig+0x40>
|
|
8006094: 687b ldr r3, [r7, #4]
|
|
8006096: 4a3d ldr r2, [pc, #244] @ (800618c <TIM_Base_SetConfig+0x130>)
|
|
8006098: 4293 cmp r3, r2
|
|
800609a: d108 bne.n 80060ae <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
800609c: 68fb ldr r3, [r7, #12]
|
|
800609e: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80060a2: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80060a4: 683b ldr r3, [r7, #0]
|
|
80060a6: 685b ldr r3, [r3, #4]
|
|
80060a8: 68fa ldr r2, [r7, #12]
|
|
80060aa: 4313 orrs r3, r2
|
|
80060ac: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80060ae: 687b ldr r3, [r7, #4]
|
|
80060b0: 4a32 ldr r2, [pc, #200] @ (800617c <TIM_Base_SetConfig+0x120>)
|
|
80060b2: 4293 cmp r3, r2
|
|
80060b4: d02b beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060b6: 687b ldr r3, [r7, #4]
|
|
80060b8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80060bc: d027 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060be: 687b ldr r3, [r7, #4]
|
|
80060c0: 4a2f ldr r2, [pc, #188] @ (8006180 <TIM_Base_SetConfig+0x124>)
|
|
80060c2: 4293 cmp r3, r2
|
|
80060c4: d023 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060c6: 687b ldr r3, [r7, #4]
|
|
80060c8: 4a2e ldr r2, [pc, #184] @ (8006184 <TIM_Base_SetConfig+0x128>)
|
|
80060ca: 4293 cmp r3, r2
|
|
80060cc: d01f beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060ce: 687b ldr r3, [r7, #4]
|
|
80060d0: 4a2d ldr r2, [pc, #180] @ (8006188 <TIM_Base_SetConfig+0x12c>)
|
|
80060d2: 4293 cmp r3, r2
|
|
80060d4: d01b beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060d6: 687b ldr r3, [r7, #4]
|
|
80060d8: 4a2c ldr r2, [pc, #176] @ (800618c <TIM_Base_SetConfig+0x130>)
|
|
80060da: 4293 cmp r3, r2
|
|
80060dc: d017 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060de: 687b ldr r3, [r7, #4]
|
|
80060e0: 4a2b ldr r2, [pc, #172] @ (8006190 <TIM_Base_SetConfig+0x134>)
|
|
80060e2: 4293 cmp r3, r2
|
|
80060e4: d013 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060e6: 687b ldr r3, [r7, #4]
|
|
80060e8: 4a2a ldr r2, [pc, #168] @ (8006194 <TIM_Base_SetConfig+0x138>)
|
|
80060ea: 4293 cmp r3, r2
|
|
80060ec: d00f beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060ee: 687b ldr r3, [r7, #4]
|
|
80060f0: 4a29 ldr r2, [pc, #164] @ (8006198 <TIM_Base_SetConfig+0x13c>)
|
|
80060f2: 4293 cmp r3, r2
|
|
80060f4: d00b beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060f6: 687b ldr r3, [r7, #4]
|
|
80060f8: 4a28 ldr r2, [pc, #160] @ (800619c <TIM_Base_SetConfig+0x140>)
|
|
80060fa: 4293 cmp r3, r2
|
|
80060fc: d007 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
80060fe: 687b ldr r3, [r7, #4]
|
|
8006100: 4a27 ldr r2, [pc, #156] @ (80061a0 <TIM_Base_SetConfig+0x144>)
|
|
8006102: 4293 cmp r3, r2
|
|
8006104: d003 beq.n 800610e <TIM_Base_SetConfig+0xb2>
|
|
8006106: 687b ldr r3, [r7, #4]
|
|
8006108: 4a26 ldr r2, [pc, #152] @ (80061a4 <TIM_Base_SetConfig+0x148>)
|
|
800610a: 4293 cmp r3, r2
|
|
800610c: d108 bne.n 8006120 <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800610e: 68fb ldr r3, [r7, #12]
|
|
8006110: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8006114: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8006116: 683b ldr r3, [r7, #0]
|
|
8006118: 68db ldr r3, [r3, #12]
|
|
800611a: 68fa ldr r2, [r7, #12]
|
|
800611c: 4313 orrs r3, r2
|
|
800611e: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8006120: 68fb ldr r3, [r7, #12]
|
|
8006122: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
8006126: 683b ldr r3, [r7, #0]
|
|
8006128: 695b ldr r3, [r3, #20]
|
|
800612a: 4313 orrs r3, r2
|
|
800612c: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800612e: 683b ldr r3, [r7, #0]
|
|
8006130: 689a ldr r2, [r3, #8]
|
|
8006132: 687b ldr r3, [r7, #4]
|
|
8006134: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8006136: 683b ldr r3, [r7, #0]
|
|
8006138: 681a ldr r2, [r3, #0]
|
|
800613a: 687b ldr r3, [r7, #4]
|
|
800613c: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800613e: 687b ldr r3, [r7, #4]
|
|
8006140: 4a0e ldr r2, [pc, #56] @ (800617c <TIM_Base_SetConfig+0x120>)
|
|
8006142: 4293 cmp r3, r2
|
|
8006144: d003 beq.n 800614e <TIM_Base_SetConfig+0xf2>
|
|
8006146: 687b ldr r3, [r7, #4]
|
|
8006148: 4a10 ldr r2, [pc, #64] @ (800618c <TIM_Base_SetConfig+0x130>)
|
|
800614a: 4293 cmp r3, r2
|
|
800614c: d103 bne.n 8006156 <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800614e: 683b ldr r3, [r7, #0]
|
|
8006150: 691a ldr r2, [r3, #16]
|
|
8006152: 687b ldr r3, [r7, #4]
|
|
8006154: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
8006156: 687b ldr r3, [r7, #4]
|
|
8006158: 681b ldr r3, [r3, #0]
|
|
800615a: f043 0204 orr.w r2, r3, #4
|
|
800615e: 687b ldr r3, [r7, #4]
|
|
8006160: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8006162: 687b ldr r3, [r7, #4]
|
|
8006164: 2201 movs r2, #1
|
|
8006166: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8006168: 687b ldr r3, [r7, #4]
|
|
800616a: 68fa ldr r2, [r7, #12]
|
|
800616c: 601a str r2, [r3, #0]
|
|
}
|
|
800616e: bf00 nop
|
|
8006170: 3714 adds r7, #20
|
|
8006172: 46bd mov sp, r7
|
|
8006174: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006178: 4770 bx lr
|
|
800617a: bf00 nop
|
|
800617c: 40010000 .word 0x40010000
|
|
8006180: 40000400 .word 0x40000400
|
|
8006184: 40000800 .word 0x40000800
|
|
8006188: 40000c00 .word 0x40000c00
|
|
800618c: 40010400 .word 0x40010400
|
|
8006190: 40014000 .word 0x40014000
|
|
8006194: 40014400 .word 0x40014400
|
|
8006198: 40014800 .word 0x40014800
|
|
800619c: 40001800 .word 0x40001800
|
|
80061a0: 40001c00 .word 0x40001c00
|
|
80061a4: 40002000 .word 0x40002000
|
|
|
|
080061a8 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
80061a8: b480 push {r7}
|
|
80061aa: b087 sub sp, #28
|
|
80061ac: af00 add r7, sp, #0
|
|
80061ae: 60f8 str r0, [r7, #12]
|
|
80061b0: 60b9 str r1, [r7, #8]
|
|
80061b2: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
80061b4: 68fb ldr r3, [r7, #12]
|
|
80061b6: 6a1b ldr r3, [r3, #32]
|
|
80061b8: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80061ba: 68fb ldr r3, [r7, #12]
|
|
80061bc: 6a1b ldr r3, [r3, #32]
|
|
80061be: f023 0201 bic.w r2, r3, #1
|
|
80061c2: 68fb ldr r3, [r7, #12]
|
|
80061c4: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
80061c6: 68fb ldr r3, [r7, #12]
|
|
80061c8: 699b ldr r3, [r3, #24]
|
|
80061ca: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
80061cc: 693b ldr r3, [r7, #16]
|
|
80061ce: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
80061d2: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
80061d4: 687b ldr r3, [r7, #4]
|
|
80061d6: 011b lsls r3, r3, #4
|
|
80061d8: 693a ldr r2, [r7, #16]
|
|
80061da: 4313 orrs r3, r2
|
|
80061dc: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
80061de: 697b ldr r3, [r7, #20]
|
|
80061e0: f023 030a bic.w r3, r3, #10
|
|
80061e4: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
80061e6: 697a ldr r2, [r7, #20]
|
|
80061e8: 68bb ldr r3, [r7, #8]
|
|
80061ea: 4313 orrs r3, r2
|
|
80061ec: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
80061ee: 68fb ldr r3, [r7, #12]
|
|
80061f0: 693a ldr r2, [r7, #16]
|
|
80061f2: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
80061f4: 68fb ldr r3, [r7, #12]
|
|
80061f6: 697a ldr r2, [r7, #20]
|
|
80061f8: 621a str r2, [r3, #32]
|
|
}
|
|
80061fa: bf00 nop
|
|
80061fc: 371c adds r7, #28
|
|
80061fe: 46bd mov sp, r7
|
|
8006200: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006204: 4770 bx lr
|
|
|
|
08006206 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8006206: b480 push {r7}
|
|
8006208: b087 sub sp, #28
|
|
800620a: af00 add r7, sp, #0
|
|
800620c: 60f8 str r0, [r7, #12]
|
|
800620e: 60b9 str r1, [r7, #8]
|
|
8006210: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8006212: 68fb ldr r3, [r7, #12]
|
|
8006214: 6a1b ldr r3, [r3, #32]
|
|
8006216: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8006218: 68fb ldr r3, [r7, #12]
|
|
800621a: 6a1b ldr r3, [r3, #32]
|
|
800621c: f023 0210 bic.w r2, r3, #16
|
|
8006220: 68fb ldr r3, [r7, #12]
|
|
8006222: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8006224: 68fb ldr r3, [r7, #12]
|
|
8006226: 699b ldr r3, [r3, #24]
|
|
8006228: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
800622a: 693b ldr r3, [r7, #16]
|
|
800622c: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8006230: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
8006232: 687b ldr r3, [r7, #4]
|
|
8006234: 031b lsls r3, r3, #12
|
|
8006236: 693a ldr r2, [r7, #16]
|
|
8006238: 4313 orrs r3, r2
|
|
800623a: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
800623c: 697b ldr r3, [r7, #20]
|
|
800623e: f023 03a0 bic.w r3, r3, #160 @ 0xa0
|
|
8006242: 617b str r3, [r7, #20]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8006244: 68bb ldr r3, [r7, #8]
|
|
8006246: 011b lsls r3, r3, #4
|
|
8006248: 697a ldr r2, [r7, #20]
|
|
800624a: 4313 orrs r3, r2
|
|
800624c: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
800624e: 68fb ldr r3, [r7, #12]
|
|
8006250: 693a ldr r2, [r7, #16]
|
|
8006252: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8006254: 68fb ldr r3, [r7, #12]
|
|
8006256: 697a ldr r2, [r7, #20]
|
|
8006258: 621a str r2, [r3, #32]
|
|
}
|
|
800625a: bf00 nop
|
|
800625c: 371c adds r7, #28
|
|
800625e: 46bd mov sp, r7
|
|
8006260: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006264: 4770 bx lr
|
|
|
|
08006266 <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
8006266: b480 push {r7}
|
|
8006268: b085 sub sp, #20
|
|
800626a: af00 add r7, sp, #0
|
|
800626c: 6078 str r0, [r7, #4]
|
|
800626e: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8006270: 687b ldr r3, [r7, #4]
|
|
8006272: 689b ldr r3, [r3, #8]
|
|
8006274: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8006276: 68fb ldr r3, [r7, #12]
|
|
8006278: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800627c: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
800627e: 683a ldr r2, [r7, #0]
|
|
8006280: 68fb ldr r3, [r7, #12]
|
|
8006282: 4313 orrs r3, r2
|
|
8006284: f043 0307 orr.w r3, r3, #7
|
|
8006288: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
800628a: 687b ldr r3, [r7, #4]
|
|
800628c: 68fa ldr r2, [r7, #12]
|
|
800628e: 609a str r2, [r3, #8]
|
|
}
|
|
8006290: bf00 nop
|
|
8006292: 3714 adds r7, #20
|
|
8006294: 46bd mov sp, r7
|
|
8006296: f85d 7b04 ldr.w r7, [sp], #4
|
|
800629a: 4770 bx lr
|
|
|
|
0800629c <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
800629c: b480 push {r7}
|
|
800629e: b087 sub sp, #28
|
|
80062a0: af00 add r7, sp, #0
|
|
80062a2: 60f8 str r0, [r7, #12]
|
|
80062a4: 60b9 str r1, [r7, #8]
|
|
80062a6: 607a str r2, [r7, #4]
|
|
80062a8: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
80062aa: 68fb ldr r3, [r7, #12]
|
|
80062ac: 689b ldr r3, [r3, #8]
|
|
80062ae: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
80062b0: 697b ldr r3, [r7, #20]
|
|
80062b2: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
80062b6: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
80062b8: 683b ldr r3, [r7, #0]
|
|
80062ba: 021a lsls r2, r3, #8
|
|
80062bc: 687b ldr r3, [r7, #4]
|
|
80062be: 431a orrs r2, r3
|
|
80062c0: 68bb ldr r3, [r7, #8]
|
|
80062c2: 4313 orrs r3, r2
|
|
80062c4: 697a ldr r2, [r7, #20]
|
|
80062c6: 4313 orrs r3, r2
|
|
80062c8: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
80062ca: 68fb ldr r3, [r7, #12]
|
|
80062cc: 697a ldr r2, [r7, #20]
|
|
80062ce: 609a str r2, [r3, #8]
|
|
}
|
|
80062d0: bf00 nop
|
|
80062d2: 371c adds r7, #28
|
|
80062d4: 46bd mov sp, r7
|
|
80062d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80062da: 4770 bx lr
|
|
|
|
080062dc <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
80062dc: b480 push {r7}
|
|
80062de: b085 sub sp, #20
|
|
80062e0: af00 add r7, sp, #0
|
|
80062e2: 6078 str r0, [r7, #4]
|
|
80062e4: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
80062e6: 687b ldr r3, [r7, #4]
|
|
80062e8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80062ec: 2b01 cmp r3, #1
|
|
80062ee: d101 bne.n 80062f4 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
80062f0: 2302 movs r3, #2
|
|
80062f2: e05a b.n 80063aa <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
80062f4: 687b ldr r3, [r7, #4]
|
|
80062f6: 2201 movs r2, #1
|
|
80062f8: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80062fc: 687b ldr r3, [r7, #4]
|
|
80062fe: 2202 movs r2, #2
|
|
8006300: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8006304: 687b ldr r3, [r7, #4]
|
|
8006306: 681b ldr r3, [r3, #0]
|
|
8006308: 685b ldr r3, [r3, #4]
|
|
800630a: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
800630c: 687b ldr r3, [r7, #4]
|
|
800630e: 681b ldr r3, [r3, #0]
|
|
8006310: 689b ldr r3, [r3, #8]
|
|
8006312: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8006314: 68fb ldr r3, [r7, #12]
|
|
8006316: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
800631a: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
800631c: 683b ldr r3, [r7, #0]
|
|
800631e: 681b ldr r3, [r3, #0]
|
|
8006320: 68fa ldr r2, [r7, #12]
|
|
8006322: 4313 orrs r3, r2
|
|
8006324: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8006326: 687b ldr r3, [r7, #4]
|
|
8006328: 681b ldr r3, [r3, #0]
|
|
800632a: 68fa ldr r2, [r7, #12]
|
|
800632c: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
800632e: 687b ldr r3, [r7, #4]
|
|
8006330: 681b ldr r3, [r3, #0]
|
|
8006332: 4a21 ldr r2, [pc, #132] @ (80063b8 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8006334: 4293 cmp r3, r2
|
|
8006336: d022 beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8006338: 687b ldr r3, [r7, #4]
|
|
800633a: 681b ldr r3, [r3, #0]
|
|
800633c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8006340: d01d beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8006342: 687b ldr r3, [r7, #4]
|
|
8006344: 681b ldr r3, [r3, #0]
|
|
8006346: 4a1d ldr r2, [pc, #116] @ (80063bc <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8006348: 4293 cmp r3, r2
|
|
800634a: d018 beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
800634c: 687b ldr r3, [r7, #4]
|
|
800634e: 681b ldr r3, [r3, #0]
|
|
8006350: 4a1b ldr r2, [pc, #108] @ (80063c0 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8006352: 4293 cmp r3, r2
|
|
8006354: d013 beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8006356: 687b ldr r3, [r7, #4]
|
|
8006358: 681b ldr r3, [r3, #0]
|
|
800635a: 4a1a ldr r2, [pc, #104] @ (80063c4 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
800635c: 4293 cmp r3, r2
|
|
800635e: d00e beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8006360: 687b ldr r3, [r7, #4]
|
|
8006362: 681b ldr r3, [r3, #0]
|
|
8006364: 4a18 ldr r2, [pc, #96] @ (80063c8 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
8006366: 4293 cmp r3, r2
|
|
8006368: d009 beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
800636a: 687b ldr r3, [r7, #4]
|
|
800636c: 681b ldr r3, [r3, #0]
|
|
800636e: 4a17 ldr r2, [pc, #92] @ (80063cc <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8006370: 4293 cmp r3, r2
|
|
8006372: d004 beq.n 800637e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8006374: 687b ldr r3, [r7, #4]
|
|
8006376: 681b ldr r3, [r3, #0]
|
|
8006378: 4a15 ldr r2, [pc, #84] @ (80063d0 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
800637a: 4293 cmp r3, r2
|
|
800637c: d10c bne.n 8006398 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
800637e: 68bb ldr r3, [r7, #8]
|
|
8006380: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8006384: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8006386: 683b ldr r3, [r7, #0]
|
|
8006388: 685b ldr r3, [r3, #4]
|
|
800638a: 68ba ldr r2, [r7, #8]
|
|
800638c: 4313 orrs r3, r2
|
|
800638e: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8006390: 687b ldr r3, [r7, #4]
|
|
8006392: 681b ldr r3, [r3, #0]
|
|
8006394: 68ba ldr r2, [r7, #8]
|
|
8006396: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8006398: 687b ldr r3, [r7, #4]
|
|
800639a: 2201 movs r2, #1
|
|
800639c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80063a0: 687b ldr r3, [r7, #4]
|
|
80063a2: 2200 movs r2, #0
|
|
80063a4: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
80063a8: 2300 movs r3, #0
|
|
}
|
|
80063aa: 4618 mov r0, r3
|
|
80063ac: 3714 adds r7, #20
|
|
80063ae: 46bd mov sp, r7
|
|
80063b0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063b4: 4770 bx lr
|
|
80063b6: bf00 nop
|
|
80063b8: 40010000 .word 0x40010000
|
|
80063bc: 40000400 .word 0x40000400
|
|
80063c0: 40000800 .word 0x40000800
|
|
80063c4: 40000c00 .word 0x40000c00
|
|
80063c8: 40010400 .word 0x40010400
|
|
80063cc: 40014000 .word 0x40014000
|
|
80063d0: 40001800 .word 0x40001800
|
|
|
|
080063d4 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80063d4: b480 push {r7}
|
|
80063d6: b083 sub sp, #12
|
|
80063d8: af00 add r7, sp, #0
|
|
80063da: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80063dc: bf00 nop
|
|
80063de: 370c adds r7, #12
|
|
80063e0: 46bd mov sp, r7
|
|
80063e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063e6: 4770 bx lr
|
|
|
|
080063e8 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
80063e8: b480 push {r7}
|
|
80063ea: b083 sub sp, #12
|
|
80063ec: af00 add r7, sp, #0
|
|
80063ee: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
80063f0: bf00 nop
|
|
80063f2: 370c adds r7, #12
|
|
80063f4: 46bd mov sp, r7
|
|
80063f6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063fa: 4770 bx lr
|
|
|
|
080063fc <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
80063fc: b580 push {r7, lr}
|
|
80063fe: b082 sub sp, #8
|
|
8006400: af00 add r7, sp, #0
|
|
8006402: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8006404: 687b ldr r3, [r7, #4]
|
|
8006406: 2b00 cmp r3, #0
|
|
8006408: d101 bne.n 800640e <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800640a: 2301 movs r3, #1
|
|
800640c: e042 b.n 8006494 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
800640e: 687b ldr r3, [r7, #4]
|
|
8006410: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8006414: b2db uxtb r3, r3
|
|
8006416: 2b00 cmp r3, #0
|
|
8006418: d106 bne.n 8006428 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
800641a: 687b ldr r3, [r7, #4]
|
|
800641c: 2200 movs r2, #0
|
|
800641e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8006422: 6878 ldr r0, [r7, #4]
|
|
8006424: f7fa ff0e bl 8001244 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8006428: 687b ldr r3, [r7, #4]
|
|
800642a: 2224 movs r2, #36 @ 0x24
|
|
800642c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8006430: 687b ldr r3, [r7, #4]
|
|
8006432: 681b ldr r3, [r3, #0]
|
|
8006434: 68da ldr r2, [r3, #12]
|
|
8006436: 687b ldr r3, [r7, #4]
|
|
8006438: 681b ldr r3, [r3, #0]
|
|
800643a: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800643e: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8006440: 6878 ldr r0, [r7, #4]
|
|
8006442: f000 f82b bl 800649c <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8006446: 687b ldr r3, [r7, #4]
|
|
8006448: 681b ldr r3, [r3, #0]
|
|
800644a: 691a ldr r2, [r3, #16]
|
|
800644c: 687b ldr r3, [r7, #4]
|
|
800644e: 681b ldr r3, [r3, #0]
|
|
8006450: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8006454: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8006456: 687b ldr r3, [r7, #4]
|
|
8006458: 681b ldr r3, [r3, #0]
|
|
800645a: 695a ldr r2, [r3, #20]
|
|
800645c: 687b ldr r3, [r7, #4]
|
|
800645e: 681b ldr r3, [r3, #0]
|
|
8006460: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8006464: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8006466: 687b ldr r3, [r7, #4]
|
|
8006468: 681b ldr r3, [r3, #0]
|
|
800646a: 68da ldr r2, [r3, #12]
|
|
800646c: 687b ldr r3, [r7, #4]
|
|
800646e: 681b ldr r3, [r3, #0]
|
|
8006470: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8006474: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006476: 687b ldr r3, [r7, #4]
|
|
8006478: 2200 movs r2, #0
|
|
800647a: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800647c: 687b ldr r3, [r7, #4]
|
|
800647e: 2220 movs r2, #32
|
|
8006480: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006484: 687b ldr r3, [r7, #4]
|
|
8006486: 2220 movs r2, #32
|
|
8006488: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800648c: 687b ldr r3, [r7, #4]
|
|
800648e: 2200 movs r2, #0
|
|
8006490: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8006492: 2300 movs r3, #0
|
|
}
|
|
8006494: 4618 mov r0, r3
|
|
8006496: 3708 adds r7, #8
|
|
8006498: 46bd mov sp, r7
|
|
800649a: bd80 pop {r7, pc}
|
|
|
|
0800649c <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800649c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
80064a0: b0c0 sub sp, #256 @ 0x100
|
|
80064a2: af00 add r7, sp, #0
|
|
80064a4: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80064a8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064ac: 681b ldr r3, [r3, #0]
|
|
80064ae: 691b ldr r3, [r3, #16]
|
|
80064b0: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
80064b4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064b8: 68d9 ldr r1, [r3, #12]
|
|
80064ba: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064be: 681a ldr r2, [r3, #0]
|
|
80064c0: ea40 0301 orr.w r3, r0, r1
|
|
80064c4: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
80064c6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064ca: 689a ldr r2, [r3, #8]
|
|
80064cc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064d0: 691b ldr r3, [r3, #16]
|
|
80064d2: 431a orrs r2, r3
|
|
80064d4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064d8: 695b ldr r3, [r3, #20]
|
|
80064da: 431a orrs r2, r3
|
|
80064dc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064e0: 69db ldr r3, [r3, #28]
|
|
80064e2: 4313 orrs r3, r2
|
|
80064e4: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
80064e8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064ec: 681b ldr r3, [r3, #0]
|
|
80064ee: 68db ldr r3, [r3, #12]
|
|
80064f0: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
80064f4: f021 010c bic.w r1, r1, #12
|
|
80064f8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80064fc: 681a ldr r2, [r3, #0]
|
|
80064fe: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
8006502: 430b orrs r3, r1
|
|
8006504: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8006506: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800650a: 681b ldr r3, [r3, #0]
|
|
800650c: 695b ldr r3, [r3, #20]
|
|
800650e: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
8006512: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006516: 6999 ldr r1, [r3, #24]
|
|
8006518: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800651c: 681a ldr r2, [r3, #0]
|
|
800651e: ea40 0301 orr.w r3, r0, r1
|
|
8006522: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
8006524: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006528: 681a ldr r2, [r3, #0]
|
|
800652a: 4b8f ldr r3, [pc, #572] @ (8006768 <UART_SetConfig+0x2cc>)
|
|
800652c: 429a cmp r2, r3
|
|
800652e: d005 beq.n 800653c <UART_SetConfig+0xa0>
|
|
8006530: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006534: 681a ldr r2, [r3, #0]
|
|
8006536: 4b8d ldr r3, [pc, #564] @ (800676c <UART_SetConfig+0x2d0>)
|
|
8006538: 429a cmp r2, r3
|
|
800653a: d104 bne.n 8006546 <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
800653c: f7ff f82c bl 8005598 <HAL_RCC_GetPCLK2Freq>
|
|
8006540: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
8006544: e003 b.n 800654e <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8006546: f7ff f813 bl 8005570 <HAL_RCC_GetPCLK1Freq>
|
|
800654a: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
800654e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006552: 69db ldr r3, [r3, #28]
|
|
8006554: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8006558: f040 810c bne.w 8006774 <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
800655c: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006560: 2200 movs r2, #0
|
|
8006562: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8006566: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
800656a: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
800656e: 4622 mov r2, r4
|
|
8006570: 462b mov r3, r5
|
|
8006572: 1891 adds r1, r2, r2
|
|
8006574: 65b9 str r1, [r7, #88] @ 0x58
|
|
8006576: 415b adcs r3, r3
|
|
8006578: 65fb str r3, [r7, #92] @ 0x5c
|
|
800657a: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
800657e: 4621 mov r1, r4
|
|
8006580: eb12 0801 adds.w r8, r2, r1
|
|
8006584: 4629 mov r1, r5
|
|
8006586: eb43 0901 adc.w r9, r3, r1
|
|
800658a: f04f 0200 mov.w r2, #0
|
|
800658e: f04f 0300 mov.w r3, #0
|
|
8006592: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8006596: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
800659a: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
800659e: 4690 mov r8, r2
|
|
80065a0: 4699 mov r9, r3
|
|
80065a2: 4623 mov r3, r4
|
|
80065a4: eb18 0303 adds.w r3, r8, r3
|
|
80065a8: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
80065ac: 462b mov r3, r5
|
|
80065ae: eb49 0303 adc.w r3, r9, r3
|
|
80065b2: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
80065b6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80065ba: 685b ldr r3, [r3, #4]
|
|
80065bc: 2200 movs r2, #0
|
|
80065be: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
80065c2: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
80065c6: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
80065ca: 460b mov r3, r1
|
|
80065cc: 18db adds r3, r3, r3
|
|
80065ce: 653b str r3, [r7, #80] @ 0x50
|
|
80065d0: 4613 mov r3, r2
|
|
80065d2: eb42 0303 adc.w r3, r2, r3
|
|
80065d6: 657b str r3, [r7, #84] @ 0x54
|
|
80065d8: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
80065dc: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
80065e0: f7f9 fe06 bl 80001f0 <__aeabi_uldivmod>
|
|
80065e4: 4602 mov r2, r0
|
|
80065e6: 460b mov r3, r1
|
|
80065e8: 4b61 ldr r3, [pc, #388] @ (8006770 <UART_SetConfig+0x2d4>)
|
|
80065ea: fba3 2302 umull r2, r3, r3, r2
|
|
80065ee: 095b lsrs r3, r3, #5
|
|
80065f0: 011c lsls r4, r3, #4
|
|
80065f2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80065f6: 2200 movs r2, #0
|
|
80065f8: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
80065fc: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
8006600: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8006604: 4642 mov r2, r8
|
|
8006606: 464b mov r3, r9
|
|
8006608: 1891 adds r1, r2, r2
|
|
800660a: 64b9 str r1, [r7, #72] @ 0x48
|
|
800660c: 415b adcs r3, r3
|
|
800660e: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006610: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8006614: 4641 mov r1, r8
|
|
8006616: eb12 0a01 adds.w sl, r2, r1
|
|
800661a: 4649 mov r1, r9
|
|
800661c: eb43 0b01 adc.w fp, r3, r1
|
|
8006620: f04f 0200 mov.w r2, #0
|
|
8006624: f04f 0300 mov.w r3, #0
|
|
8006628: ea4f 03cb mov.w r3, fp, lsl #3
|
|
800662c: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8006630: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8006634: 4692 mov sl, r2
|
|
8006636: 469b mov fp, r3
|
|
8006638: 4643 mov r3, r8
|
|
800663a: eb1a 0303 adds.w r3, sl, r3
|
|
800663e: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8006642: 464b mov r3, r9
|
|
8006644: eb4b 0303 adc.w r3, fp, r3
|
|
8006648: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
800664c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006650: 685b ldr r3, [r3, #4]
|
|
8006652: 2200 movs r2, #0
|
|
8006654: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8006658: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
800665c: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
8006660: 460b mov r3, r1
|
|
8006662: 18db adds r3, r3, r3
|
|
8006664: 643b str r3, [r7, #64] @ 0x40
|
|
8006666: 4613 mov r3, r2
|
|
8006668: eb42 0303 adc.w r3, r2, r3
|
|
800666c: 647b str r3, [r7, #68] @ 0x44
|
|
800666e: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
8006672: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8006676: f7f9 fdbb bl 80001f0 <__aeabi_uldivmod>
|
|
800667a: 4602 mov r2, r0
|
|
800667c: 460b mov r3, r1
|
|
800667e: 4611 mov r1, r2
|
|
8006680: 4b3b ldr r3, [pc, #236] @ (8006770 <UART_SetConfig+0x2d4>)
|
|
8006682: fba3 2301 umull r2, r3, r3, r1
|
|
8006686: 095b lsrs r3, r3, #5
|
|
8006688: 2264 movs r2, #100 @ 0x64
|
|
800668a: fb02 f303 mul.w r3, r2, r3
|
|
800668e: 1acb subs r3, r1, r3
|
|
8006690: 00db lsls r3, r3, #3
|
|
8006692: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8006696: 4b36 ldr r3, [pc, #216] @ (8006770 <UART_SetConfig+0x2d4>)
|
|
8006698: fba3 2302 umull r2, r3, r3, r2
|
|
800669c: 095b lsrs r3, r3, #5
|
|
800669e: 005b lsls r3, r3, #1
|
|
80066a0: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
80066a4: 441c add r4, r3
|
|
80066a6: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80066aa: 2200 movs r2, #0
|
|
80066ac: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
80066b0: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
80066b4: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
80066b8: 4642 mov r2, r8
|
|
80066ba: 464b mov r3, r9
|
|
80066bc: 1891 adds r1, r2, r2
|
|
80066be: 63b9 str r1, [r7, #56] @ 0x38
|
|
80066c0: 415b adcs r3, r3
|
|
80066c2: 63fb str r3, [r7, #60] @ 0x3c
|
|
80066c4: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
80066c8: 4641 mov r1, r8
|
|
80066ca: 1851 adds r1, r2, r1
|
|
80066cc: 6339 str r1, [r7, #48] @ 0x30
|
|
80066ce: 4649 mov r1, r9
|
|
80066d0: 414b adcs r3, r1
|
|
80066d2: 637b str r3, [r7, #52] @ 0x34
|
|
80066d4: f04f 0200 mov.w r2, #0
|
|
80066d8: f04f 0300 mov.w r3, #0
|
|
80066dc: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
80066e0: 4659 mov r1, fp
|
|
80066e2: 00cb lsls r3, r1, #3
|
|
80066e4: 4651 mov r1, sl
|
|
80066e6: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80066ea: 4651 mov r1, sl
|
|
80066ec: 00ca lsls r2, r1, #3
|
|
80066ee: 4610 mov r0, r2
|
|
80066f0: 4619 mov r1, r3
|
|
80066f2: 4603 mov r3, r0
|
|
80066f4: 4642 mov r2, r8
|
|
80066f6: 189b adds r3, r3, r2
|
|
80066f8: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80066fc: 464b mov r3, r9
|
|
80066fe: 460a mov r2, r1
|
|
8006700: eb42 0303 adc.w r3, r2, r3
|
|
8006704: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8006708: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800670c: 685b ldr r3, [r3, #4]
|
|
800670e: 2200 movs r2, #0
|
|
8006710: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8006714: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8006718: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
800671c: 460b mov r3, r1
|
|
800671e: 18db adds r3, r3, r3
|
|
8006720: 62bb str r3, [r7, #40] @ 0x28
|
|
8006722: 4613 mov r3, r2
|
|
8006724: eb42 0303 adc.w r3, r2, r3
|
|
8006728: 62fb str r3, [r7, #44] @ 0x2c
|
|
800672a: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
800672e: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
8006732: f7f9 fd5d bl 80001f0 <__aeabi_uldivmod>
|
|
8006736: 4602 mov r2, r0
|
|
8006738: 460b mov r3, r1
|
|
800673a: 4b0d ldr r3, [pc, #52] @ (8006770 <UART_SetConfig+0x2d4>)
|
|
800673c: fba3 1302 umull r1, r3, r3, r2
|
|
8006740: 095b lsrs r3, r3, #5
|
|
8006742: 2164 movs r1, #100 @ 0x64
|
|
8006744: fb01 f303 mul.w r3, r1, r3
|
|
8006748: 1ad3 subs r3, r2, r3
|
|
800674a: 00db lsls r3, r3, #3
|
|
800674c: 3332 adds r3, #50 @ 0x32
|
|
800674e: 4a08 ldr r2, [pc, #32] @ (8006770 <UART_SetConfig+0x2d4>)
|
|
8006750: fba2 2303 umull r2, r3, r2, r3
|
|
8006754: 095b lsrs r3, r3, #5
|
|
8006756: f003 0207 and.w r2, r3, #7
|
|
800675a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800675e: 681b ldr r3, [r3, #0]
|
|
8006760: 4422 add r2, r4
|
|
8006762: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8006764: e106 b.n 8006974 <UART_SetConfig+0x4d8>
|
|
8006766: bf00 nop
|
|
8006768: 40011000 .word 0x40011000
|
|
800676c: 40011400 .word 0x40011400
|
|
8006770: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8006774: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006778: 2200 movs r2, #0
|
|
800677a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
800677e: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
8006782: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8006786: 4642 mov r2, r8
|
|
8006788: 464b mov r3, r9
|
|
800678a: 1891 adds r1, r2, r2
|
|
800678c: 6239 str r1, [r7, #32]
|
|
800678e: 415b adcs r3, r3
|
|
8006790: 627b str r3, [r7, #36] @ 0x24
|
|
8006792: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8006796: 4641 mov r1, r8
|
|
8006798: 1854 adds r4, r2, r1
|
|
800679a: 4649 mov r1, r9
|
|
800679c: eb43 0501 adc.w r5, r3, r1
|
|
80067a0: f04f 0200 mov.w r2, #0
|
|
80067a4: f04f 0300 mov.w r3, #0
|
|
80067a8: 00eb lsls r3, r5, #3
|
|
80067aa: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
80067ae: 00e2 lsls r2, r4, #3
|
|
80067b0: 4614 mov r4, r2
|
|
80067b2: 461d mov r5, r3
|
|
80067b4: 4643 mov r3, r8
|
|
80067b6: 18e3 adds r3, r4, r3
|
|
80067b8: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
80067bc: 464b mov r3, r9
|
|
80067be: eb45 0303 adc.w r3, r5, r3
|
|
80067c2: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
80067c6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
80067ca: 685b ldr r3, [r3, #4]
|
|
80067cc: 2200 movs r2, #0
|
|
80067ce: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
80067d2: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
80067d6: f04f 0200 mov.w r2, #0
|
|
80067da: f04f 0300 mov.w r3, #0
|
|
80067de: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
80067e2: 4629 mov r1, r5
|
|
80067e4: 008b lsls r3, r1, #2
|
|
80067e6: 4621 mov r1, r4
|
|
80067e8: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
80067ec: 4621 mov r1, r4
|
|
80067ee: 008a lsls r2, r1, #2
|
|
80067f0: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
80067f4: f7f9 fcfc bl 80001f0 <__aeabi_uldivmod>
|
|
80067f8: 4602 mov r2, r0
|
|
80067fa: 460b mov r3, r1
|
|
80067fc: 4b60 ldr r3, [pc, #384] @ (8006980 <UART_SetConfig+0x4e4>)
|
|
80067fe: fba3 2302 umull r2, r3, r3, r2
|
|
8006802: 095b lsrs r3, r3, #5
|
|
8006804: 011c lsls r4, r3, #4
|
|
8006806: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
800680a: 2200 movs r2, #0
|
|
800680c: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
8006810: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8006814: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8006818: 4642 mov r2, r8
|
|
800681a: 464b mov r3, r9
|
|
800681c: 1891 adds r1, r2, r2
|
|
800681e: 61b9 str r1, [r7, #24]
|
|
8006820: 415b adcs r3, r3
|
|
8006822: 61fb str r3, [r7, #28]
|
|
8006824: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8006828: 4641 mov r1, r8
|
|
800682a: 1851 adds r1, r2, r1
|
|
800682c: 6139 str r1, [r7, #16]
|
|
800682e: 4649 mov r1, r9
|
|
8006830: 414b adcs r3, r1
|
|
8006832: 617b str r3, [r7, #20]
|
|
8006834: f04f 0200 mov.w r2, #0
|
|
8006838: f04f 0300 mov.w r3, #0
|
|
800683c: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
8006840: 4659 mov r1, fp
|
|
8006842: 00cb lsls r3, r1, #3
|
|
8006844: 4651 mov r1, sl
|
|
8006846: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
800684a: 4651 mov r1, sl
|
|
800684c: 00ca lsls r2, r1, #3
|
|
800684e: 4610 mov r0, r2
|
|
8006850: 4619 mov r1, r3
|
|
8006852: 4603 mov r3, r0
|
|
8006854: 4642 mov r2, r8
|
|
8006856: 189b adds r3, r3, r2
|
|
8006858: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
800685c: 464b mov r3, r9
|
|
800685e: 460a mov r2, r1
|
|
8006860: eb42 0303 adc.w r3, r2, r3
|
|
8006864: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006868: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800686c: 685b ldr r3, [r3, #4]
|
|
800686e: 2200 movs r2, #0
|
|
8006870: 67bb str r3, [r7, #120] @ 0x78
|
|
8006872: 67fa str r2, [r7, #124] @ 0x7c
|
|
8006874: f04f 0200 mov.w r2, #0
|
|
8006878: f04f 0300 mov.w r3, #0
|
|
800687c: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
8006880: 4649 mov r1, r9
|
|
8006882: 008b lsls r3, r1, #2
|
|
8006884: 4641 mov r1, r8
|
|
8006886: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
800688a: 4641 mov r1, r8
|
|
800688c: 008a lsls r2, r1, #2
|
|
800688e: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
8006892: f7f9 fcad bl 80001f0 <__aeabi_uldivmod>
|
|
8006896: 4602 mov r2, r0
|
|
8006898: 460b mov r3, r1
|
|
800689a: 4611 mov r1, r2
|
|
800689c: 4b38 ldr r3, [pc, #224] @ (8006980 <UART_SetConfig+0x4e4>)
|
|
800689e: fba3 2301 umull r2, r3, r3, r1
|
|
80068a2: 095b lsrs r3, r3, #5
|
|
80068a4: 2264 movs r2, #100 @ 0x64
|
|
80068a6: fb02 f303 mul.w r3, r2, r3
|
|
80068aa: 1acb subs r3, r1, r3
|
|
80068ac: 011b lsls r3, r3, #4
|
|
80068ae: 3332 adds r3, #50 @ 0x32
|
|
80068b0: 4a33 ldr r2, [pc, #204] @ (8006980 <UART_SetConfig+0x4e4>)
|
|
80068b2: fba2 2303 umull r2, r3, r2, r3
|
|
80068b6: 095b lsrs r3, r3, #5
|
|
80068b8: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80068bc: 441c add r4, r3
|
|
80068be: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80068c2: 2200 movs r2, #0
|
|
80068c4: 673b str r3, [r7, #112] @ 0x70
|
|
80068c6: 677a str r2, [r7, #116] @ 0x74
|
|
80068c8: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
80068cc: 4642 mov r2, r8
|
|
80068ce: 464b mov r3, r9
|
|
80068d0: 1891 adds r1, r2, r2
|
|
80068d2: 60b9 str r1, [r7, #8]
|
|
80068d4: 415b adcs r3, r3
|
|
80068d6: 60fb str r3, [r7, #12]
|
|
80068d8: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
80068dc: 4641 mov r1, r8
|
|
80068de: 1851 adds r1, r2, r1
|
|
80068e0: 6039 str r1, [r7, #0]
|
|
80068e2: 4649 mov r1, r9
|
|
80068e4: 414b adcs r3, r1
|
|
80068e6: 607b str r3, [r7, #4]
|
|
80068e8: f04f 0200 mov.w r2, #0
|
|
80068ec: f04f 0300 mov.w r3, #0
|
|
80068f0: e9d7 ab00 ldrd sl, fp, [r7]
|
|
80068f4: 4659 mov r1, fp
|
|
80068f6: 00cb lsls r3, r1, #3
|
|
80068f8: 4651 mov r1, sl
|
|
80068fa: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
80068fe: 4651 mov r1, sl
|
|
8006900: 00ca lsls r2, r1, #3
|
|
8006902: 4610 mov r0, r2
|
|
8006904: 4619 mov r1, r3
|
|
8006906: 4603 mov r3, r0
|
|
8006908: 4642 mov r2, r8
|
|
800690a: 189b adds r3, r3, r2
|
|
800690c: 66bb str r3, [r7, #104] @ 0x68
|
|
800690e: 464b mov r3, r9
|
|
8006910: 460a mov r2, r1
|
|
8006912: eb42 0303 adc.w r3, r2, r3
|
|
8006916: 66fb str r3, [r7, #108] @ 0x6c
|
|
8006918: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800691c: 685b ldr r3, [r3, #4]
|
|
800691e: 2200 movs r2, #0
|
|
8006920: 663b str r3, [r7, #96] @ 0x60
|
|
8006922: 667a str r2, [r7, #100] @ 0x64
|
|
8006924: f04f 0200 mov.w r2, #0
|
|
8006928: f04f 0300 mov.w r3, #0
|
|
800692c: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
8006930: 4649 mov r1, r9
|
|
8006932: 008b lsls r3, r1, #2
|
|
8006934: 4641 mov r1, r8
|
|
8006936: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
800693a: 4641 mov r1, r8
|
|
800693c: 008a lsls r2, r1, #2
|
|
800693e: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
8006942: f7f9 fc55 bl 80001f0 <__aeabi_uldivmod>
|
|
8006946: 4602 mov r2, r0
|
|
8006948: 460b mov r3, r1
|
|
800694a: 4b0d ldr r3, [pc, #52] @ (8006980 <UART_SetConfig+0x4e4>)
|
|
800694c: fba3 1302 umull r1, r3, r3, r2
|
|
8006950: 095b lsrs r3, r3, #5
|
|
8006952: 2164 movs r1, #100 @ 0x64
|
|
8006954: fb01 f303 mul.w r3, r1, r3
|
|
8006958: 1ad3 subs r3, r2, r3
|
|
800695a: 011b lsls r3, r3, #4
|
|
800695c: 3332 adds r3, #50 @ 0x32
|
|
800695e: 4a08 ldr r2, [pc, #32] @ (8006980 <UART_SetConfig+0x4e4>)
|
|
8006960: fba2 2303 umull r2, r3, r2, r3
|
|
8006964: 095b lsrs r3, r3, #5
|
|
8006966: f003 020f and.w r2, r3, #15
|
|
800696a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800696e: 681b ldr r3, [r3, #0]
|
|
8006970: 4422 add r2, r4
|
|
8006972: 609a str r2, [r3, #8]
|
|
}
|
|
8006974: bf00 nop
|
|
8006976: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
800697a: 46bd mov sp, r7
|
|
800697c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8006980: 51eb851f .word 0x51eb851f
|
|
|
|
08006984 <FMC_SDRAM_Init>:
|
|
* @param Device Pointer to SDRAM device instance
|
|
* @param Init Pointer to SDRAM Initialization structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
|
|
{
|
|
8006984: b480 push {r7}
|
|
8006986: b083 sub sp, #12
|
|
8006988: af00 add r7, sp, #0
|
|
800698a: 6078 str r0, [r7, #4]
|
|
800698c: 6039 str r1, [r7, #0]
|
|
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
|
|
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
|
|
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
|
|
|
|
/* Set SDRAM bank configuration parameters */
|
|
if (Init->SDBank == FMC_SDRAM_BANK1)
|
|
800698e: 683b ldr r3, [r7, #0]
|
|
8006990: 681b ldr r3, [r3, #0]
|
|
8006992: 2b00 cmp r3, #0
|
|
8006994: d123 bne.n 80069de <FMC_SDRAM_Init+0x5a>
|
|
{
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
|
|
8006996: 687b ldr r3, [r7, #4]
|
|
8006998: 681b ldr r3, [r3, #0]
|
|
800699a: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
800699e: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
80069a2: 683a ldr r2, [r7, #0]
|
|
80069a4: 6851 ldr r1, [r2, #4]
|
|
80069a6: 683a ldr r2, [r7, #0]
|
|
80069a8: 6892 ldr r2, [r2, #8]
|
|
80069aa: 4311 orrs r1, r2
|
|
80069ac: 683a ldr r2, [r7, #0]
|
|
80069ae: 68d2 ldr r2, [r2, #12]
|
|
80069b0: 4311 orrs r1, r2
|
|
80069b2: 683a ldr r2, [r7, #0]
|
|
80069b4: 6912 ldr r2, [r2, #16]
|
|
80069b6: 4311 orrs r1, r2
|
|
80069b8: 683a ldr r2, [r7, #0]
|
|
80069ba: 6952 ldr r2, [r2, #20]
|
|
80069bc: 4311 orrs r1, r2
|
|
80069be: 683a ldr r2, [r7, #0]
|
|
80069c0: 6992 ldr r2, [r2, #24]
|
|
80069c2: 4311 orrs r1, r2
|
|
80069c4: 683a ldr r2, [r7, #0]
|
|
80069c6: 69d2 ldr r2, [r2, #28]
|
|
80069c8: 4311 orrs r1, r2
|
|
80069ca: 683a ldr r2, [r7, #0]
|
|
80069cc: 6a12 ldr r2, [r2, #32]
|
|
80069ce: 4311 orrs r1, r2
|
|
80069d0: 683a ldr r2, [r7, #0]
|
|
80069d2: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
80069d4: 430a orrs r2, r1
|
|
80069d6: 431a orrs r2, r3
|
|
80069d8: 687b ldr r3, [r7, #4]
|
|
80069da: 601a str r2, [r3, #0]
|
|
80069dc: e028 b.n 8006a30 <FMC_SDRAM_Init+0xac>
|
|
Init->ReadBurst |
|
|
Init->ReadPipeDelay));
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
|
|
80069de: 687b ldr r3, [r7, #4]
|
|
80069e0: 681b ldr r3, [r3, #0]
|
|
80069e2: f423 42f8 bic.w r2, r3, #31744 @ 0x7c00
|
|
80069e6: 683b ldr r3, [r7, #0]
|
|
80069e8: 69d9 ldr r1, [r3, #28]
|
|
80069ea: 683b ldr r3, [r7, #0]
|
|
80069ec: 6a1b ldr r3, [r3, #32]
|
|
80069ee: 4319 orrs r1, r3
|
|
80069f0: 683b ldr r3, [r7, #0]
|
|
80069f2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80069f4: 430b orrs r3, r1
|
|
80069f6: 431a orrs r2, r3
|
|
80069f8: 687b ldr r3, [r7, #4]
|
|
80069fa: 601a str r2, [r3, #0]
|
|
FMC_SDCR1_RPIPE,
|
|
(Init->SDClockPeriod |
|
|
Init->ReadBurst |
|
|
Init->ReadPipeDelay));
|
|
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
|
|
80069fc: 687b ldr r3, [r7, #4]
|
|
80069fe: 685b ldr r3, [r3, #4]
|
|
8006a00: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
8006a04: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8006a08: 683a ldr r2, [r7, #0]
|
|
8006a0a: 6851 ldr r1, [r2, #4]
|
|
8006a0c: 683a ldr r2, [r7, #0]
|
|
8006a0e: 6892 ldr r2, [r2, #8]
|
|
8006a10: 4311 orrs r1, r2
|
|
8006a12: 683a ldr r2, [r7, #0]
|
|
8006a14: 68d2 ldr r2, [r2, #12]
|
|
8006a16: 4311 orrs r1, r2
|
|
8006a18: 683a ldr r2, [r7, #0]
|
|
8006a1a: 6912 ldr r2, [r2, #16]
|
|
8006a1c: 4311 orrs r1, r2
|
|
8006a1e: 683a ldr r2, [r7, #0]
|
|
8006a20: 6952 ldr r2, [r2, #20]
|
|
8006a22: 4311 orrs r1, r2
|
|
8006a24: 683a ldr r2, [r7, #0]
|
|
8006a26: 6992 ldr r2, [r2, #24]
|
|
8006a28: 430a orrs r2, r1
|
|
8006a2a: 431a orrs r2, r3
|
|
8006a2c: 687b ldr r3, [r7, #4]
|
|
8006a2e: 605a str r2, [r3, #4]
|
|
Init->InternalBankNumber |
|
|
Init->CASLatency |
|
|
Init->WriteProtection));
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006a30: 2300 movs r3, #0
|
|
}
|
|
8006a32: 4618 mov r0, r3
|
|
8006a34: 370c adds r7, #12
|
|
8006a36: 46bd mov sp, r7
|
|
8006a38: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006a3c: 4770 bx lr
|
|
|
|
08006a3e <FMC_SDRAM_Timing_Init>:
|
|
* @param Bank SDRAM bank number
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
|
|
const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
|
|
{
|
|
8006a3e: b480 push {r7}
|
|
8006a40: b085 sub sp, #20
|
|
8006a42: af00 add r7, sp, #0
|
|
8006a44: 60f8 str r0, [r7, #12]
|
|
8006a46: 60b9 str r1, [r7, #8]
|
|
8006a48: 607a str r2, [r7, #4]
|
|
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
|
|
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
|
|
assert_param(IS_FMC_SDRAM_BANK(Bank));
|
|
|
|
/* Set SDRAM device timing parameters */
|
|
if (Bank == FMC_SDRAM_BANK1)
|
|
8006a4a: 687b ldr r3, [r7, #4]
|
|
8006a4c: 2b00 cmp r3, #0
|
|
8006a4e: d128 bne.n 8006aa2 <FMC_SDRAM_Timing_Init+0x64>
|
|
{
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
|
|
8006a50: 68fb ldr r3, [r7, #12]
|
|
8006a52: 689b ldr r3, [r3, #8]
|
|
8006a54: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
|
|
8006a58: 68bb ldr r3, [r7, #8]
|
|
8006a5a: 681b ldr r3, [r3, #0]
|
|
8006a5c: 1e59 subs r1, r3, #1
|
|
8006a5e: 68bb ldr r3, [r7, #8]
|
|
8006a60: 685b ldr r3, [r3, #4]
|
|
8006a62: 3b01 subs r3, #1
|
|
8006a64: 011b lsls r3, r3, #4
|
|
8006a66: 4319 orrs r1, r3
|
|
8006a68: 68bb ldr r3, [r7, #8]
|
|
8006a6a: 689b ldr r3, [r3, #8]
|
|
8006a6c: 3b01 subs r3, #1
|
|
8006a6e: 021b lsls r3, r3, #8
|
|
8006a70: 4319 orrs r1, r3
|
|
8006a72: 68bb ldr r3, [r7, #8]
|
|
8006a74: 68db ldr r3, [r3, #12]
|
|
8006a76: 3b01 subs r3, #1
|
|
8006a78: 031b lsls r3, r3, #12
|
|
8006a7a: 4319 orrs r1, r3
|
|
8006a7c: 68bb ldr r3, [r7, #8]
|
|
8006a7e: 691b ldr r3, [r3, #16]
|
|
8006a80: 3b01 subs r3, #1
|
|
8006a82: 041b lsls r3, r3, #16
|
|
8006a84: 4319 orrs r1, r3
|
|
8006a86: 68bb ldr r3, [r7, #8]
|
|
8006a88: 695b ldr r3, [r3, #20]
|
|
8006a8a: 3b01 subs r3, #1
|
|
8006a8c: 051b lsls r3, r3, #20
|
|
8006a8e: 4319 orrs r1, r3
|
|
8006a90: 68bb ldr r3, [r7, #8]
|
|
8006a92: 699b ldr r3, [r3, #24]
|
|
8006a94: 3b01 subs r3, #1
|
|
8006a96: 061b lsls r3, r3, #24
|
|
8006a98: 430b orrs r3, r1
|
|
8006a9a: 431a orrs r2, r3
|
|
8006a9c: 68fb ldr r3, [r7, #12]
|
|
8006a9e: 609a str r2, [r3, #8]
|
|
8006aa0: e02f b.n 8006b02 <FMC_SDRAM_Timing_Init+0xc4>
|
|
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
|
|
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
|
|
8006aa2: 68fb ldr r3, [r7, #12]
|
|
8006aa4: 689b ldr r3, [r3, #8]
|
|
8006aa6: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
|
|
8006aaa: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8006aae: 68ba ldr r2, [r7, #8]
|
|
8006ab0: 68d2 ldr r2, [r2, #12]
|
|
8006ab2: 3a01 subs r2, #1
|
|
8006ab4: 0311 lsls r1, r2, #12
|
|
8006ab6: 68ba ldr r2, [r7, #8]
|
|
8006ab8: 6952 ldr r2, [r2, #20]
|
|
8006aba: 3a01 subs r2, #1
|
|
8006abc: 0512 lsls r2, r2, #20
|
|
8006abe: 430a orrs r2, r1
|
|
8006ac0: 431a orrs r2, r3
|
|
8006ac2: 68fb ldr r3, [r7, #12]
|
|
8006ac4: 609a str r2, [r3, #8]
|
|
FMC_SDTR1_TRC |
|
|
FMC_SDTR1_TRP,
|
|
(((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
|
|
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
|
|
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
|
|
8006ac6: 68fb ldr r3, [r7, #12]
|
|
8006ac8: 68db ldr r3, [r3, #12]
|
|
8006aca: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
|
|
8006ace: 68bb ldr r3, [r7, #8]
|
|
8006ad0: 681b ldr r3, [r3, #0]
|
|
8006ad2: 1e59 subs r1, r3, #1
|
|
8006ad4: 68bb ldr r3, [r7, #8]
|
|
8006ad6: 685b ldr r3, [r3, #4]
|
|
8006ad8: 3b01 subs r3, #1
|
|
8006ada: 011b lsls r3, r3, #4
|
|
8006adc: 4319 orrs r1, r3
|
|
8006ade: 68bb ldr r3, [r7, #8]
|
|
8006ae0: 689b ldr r3, [r3, #8]
|
|
8006ae2: 3b01 subs r3, #1
|
|
8006ae4: 021b lsls r3, r3, #8
|
|
8006ae6: 4319 orrs r1, r3
|
|
8006ae8: 68bb ldr r3, [r7, #8]
|
|
8006aea: 691b ldr r3, [r3, #16]
|
|
8006aec: 3b01 subs r3, #1
|
|
8006aee: 041b lsls r3, r3, #16
|
|
8006af0: 4319 orrs r1, r3
|
|
8006af2: 68bb ldr r3, [r7, #8]
|
|
8006af4: 699b ldr r3, [r3, #24]
|
|
8006af6: 3b01 subs r3, #1
|
|
8006af8: 061b lsls r3, r3, #24
|
|
8006afa: 430b orrs r3, r1
|
|
8006afc: 431a orrs r2, r3
|
|
8006afe: 68fb ldr r3, [r7, #12]
|
|
8006b00: 60da str r2, [r3, #12]
|
|
(((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
|
|
(((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
|
|
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006b02: 2300 movs r3, #0
|
|
}
|
|
8006b04: 4618 mov r0, r3
|
|
8006b06: 3714 adds r7, #20
|
|
8006b08: 46bd mov sp, r7
|
|
8006b0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b0e: 4770 bx lr
|
|
|
|
08006b10 <USB_CoreInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8006b10: b084 sub sp, #16
|
|
8006b12: b580 push {r7, lr}
|
|
8006b14: b084 sub sp, #16
|
|
8006b16: af00 add r7, sp, #0
|
|
8006b18: 6078 str r0, [r7, #4]
|
|
8006b1a: f107 001c add.w r0, r7, #28
|
|
8006b1e: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret;
|
|
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
|
|
8006b22: f897 3021 ldrb.w r3, [r7, #33] @ 0x21
|
|
8006b26: 2b01 cmp r3, #1
|
|
8006b28: d123 bne.n 8006b72 <USB_CoreInit+0x62>
|
|
{
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8006b2a: 687b ldr r3, [r7, #4]
|
|
8006b2c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006b2e: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8006b32: 687b ldr r3, [r7, #4]
|
|
8006b34: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Init The ULPI Interface */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
|
|
8006b36: 687b ldr r3, [r7, #4]
|
|
8006b38: 68db ldr r3, [r3, #12]
|
|
8006b3a: f423 0384 bic.w r3, r3, #4325376 @ 0x420000
|
|
8006b3e: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8006b42: 687a ldr r2, [r7, #4]
|
|
8006b44: 60d3 str r3, [r2, #12]
|
|
|
|
/* Select vbus source */
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
|
|
8006b46: 687b ldr r3, [r7, #4]
|
|
8006b48: 68db ldr r3, [r3, #12]
|
|
8006b4a: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
8006b4e: 687b ldr r3, [r7, #4]
|
|
8006b50: 60da str r2, [r3, #12]
|
|
if (cfg.use_external_vbus == 1U)
|
|
8006b52: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8006b56: 2b01 cmp r3, #1
|
|
8006b58: d105 bne.n 8006b66 <USB_CoreInit+0x56>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
|
|
8006b5a: 687b ldr r3, [r7, #4]
|
|
8006b5c: 68db ldr r3, [r3, #12]
|
|
8006b5e: f443 1280 orr.w r2, r3, #1048576 @ 0x100000
|
|
8006b62: 687b ldr r3, [r7, #4]
|
|
8006b64: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8006b66: 6878 ldr r0, [r7, #4]
|
|
8006b68: f000 f9dc bl 8006f24 <USB_CoreReset>
|
|
8006b6c: 4603 mov r3, r0
|
|
8006b6e: 73fb strb r3, [r7, #15]
|
|
8006b70: e01b b.n 8006baa <USB_CoreInit+0x9a>
|
|
}
|
|
else /* FS interface (embedded Phy) */
|
|
{
|
|
/* Select FS Embedded PHY */
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
|
|
8006b72: 687b ldr r3, [r7, #4]
|
|
8006b74: 68db ldr r3, [r3, #12]
|
|
8006b76: f043 0240 orr.w r2, r3, #64 @ 0x40
|
|
8006b7a: 687b ldr r3, [r7, #4]
|
|
8006b7c: 60da str r2, [r3, #12]
|
|
|
|
/* Reset after a PHY select */
|
|
ret = USB_CoreReset(USBx);
|
|
8006b7e: 6878 ldr r0, [r7, #4]
|
|
8006b80: f000 f9d0 bl 8006f24 <USB_CoreReset>
|
|
8006b84: 4603 mov r3, r0
|
|
8006b86: 73fb strb r3, [r7, #15]
|
|
|
|
if (cfg.battery_charging_enable == 0U)
|
|
8006b88: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
8006b8c: 2b00 cmp r3, #0
|
|
8006b8e: d106 bne.n 8006b9e <USB_CoreInit+0x8e>
|
|
{
|
|
/* Activate the USB Transceiver */
|
|
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
|
|
8006b90: 687b ldr r3, [r7, #4]
|
|
8006b92: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006b94: f443 3280 orr.w r2, r3, #65536 @ 0x10000
|
|
8006b98: 687b ldr r3, [r7, #4]
|
|
8006b9a: 639a str r2, [r3, #56] @ 0x38
|
|
8006b9c: e005 b.n 8006baa <USB_CoreInit+0x9a>
|
|
}
|
|
else
|
|
{
|
|
/* Deactivate the USB Transceiver */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
|
|
8006b9e: 687b ldr r3, [r7, #4]
|
|
8006ba0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006ba2: f423 3280 bic.w r2, r3, #65536 @ 0x10000
|
|
8006ba6: 687b ldr r3, [r7, #4]
|
|
8006ba8: 639a str r2, [r3, #56] @ 0x38
|
|
}
|
|
}
|
|
|
|
if (cfg.dma_enable == 1U)
|
|
8006baa: 7fbb ldrb r3, [r7, #30]
|
|
8006bac: 2b01 cmp r3, #1
|
|
8006bae: d10b bne.n 8006bc8 <USB_CoreInit+0xb8>
|
|
{
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
|
|
8006bb0: 687b ldr r3, [r7, #4]
|
|
8006bb2: 689b ldr r3, [r3, #8]
|
|
8006bb4: f043 0206 orr.w r2, r3, #6
|
|
8006bb8: 687b ldr r3, [r7, #4]
|
|
8006bba: 609a str r2, [r3, #8]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
|
|
8006bbc: 687b ldr r3, [r7, #4]
|
|
8006bbe: 689b ldr r3, [r3, #8]
|
|
8006bc0: f043 0220 orr.w r2, r3, #32
|
|
8006bc4: 687b ldr r3, [r7, #4]
|
|
8006bc6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
return ret;
|
|
8006bc8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8006bca: 4618 mov r0, r3
|
|
8006bcc: 3710 adds r7, #16
|
|
8006bce: 46bd mov sp, r7
|
|
8006bd0: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8006bd4: b004 add sp, #16
|
|
8006bd6: 4770 bx lr
|
|
|
|
08006bd8 <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006bd8: b480 push {r7}
|
|
8006bda: b083 sub sp, #12
|
|
8006bdc: af00 add r7, sp, #0
|
|
8006bde: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
8006be0: 687b ldr r3, [r7, #4]
|
|
8006be2: 689b ldr r3, [r3, #8]
|
|
8006be4: f043 0201 orr.w r2, r3, #1
|
|
8006be8: 687b ldr r3, [r7, #4]
|
|
8006bea: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8006bec: 2300 movs r3, #0
|
|
}
|
|
8006bee: 4618 mov r0, r3
|
|
8006bf0: 370c adds r7, #12
|
|
8006bf2: 46bd mov sp, r7
|
|
8006bf4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006bf8: 4770 bx lr
|
|
|
|
08006bfa <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006bfa: b480 push {r7}
|
|
8006bfc: b083 sub sp, #12
|
|
8006bfe: af00 add r7, sp, #0
|
|
8006c00: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
8006c02: 687b ldr r3, [r7, #4]
|
|
8006c04: 689b ldr r3, [r3, #8]
|
|
8006c06: f023 0201 bic.w r2, r3, #1
|
|
8006c0a: 687b ldr r3, [r7, #4]
|
|
8006c0c: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8006c0e: 2300 movs r3, #0
|
|
}
|
|
8006c10: 4618 mov r0, r3
|
|
8006c12: 370c adds r7, #12
|
|
8006c14: 46bd mov sp, r7
|
|
8006c16: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006c1a: 4770 bx lr
|
|
|
|
08006c1c <USB_SetCurrentMode>:
|
|
* @arg USB_DEVICE_MODE Peripheral mode
|
|
* @arg USB_HOST_MODE Host mode
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
|
|
{
|
|
8006c1c: b580 push {r7, lr}
|
|
8006c1e: b084 sub sp, #16
|
|
8006c20: af00 add r7, sp, #0
|
|
8006c22: 6078 str r0, [r7, #4]
|
|
8006c24: 460b mov r3, r1
|
|
8006c26: 70fb strb r3, [r7, #3]
|
|
uint32_t ms = 0U;
|
|
8006c28: 2300 movs r3, #0
|
|
8006c2a: 60fb str r3, [r7, #12]
|
|
|
|
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
|
|
8006c2c: 687b ldr r3, [r7, #4]
|
|
8006c2e: 68db ldr r3, [r3, #12]
|
|
8006c30: f023 42c0 bic.w r2, r3, #1610612736 @ 0x60000000
|
|
8006c34: 687b ldr r3, [r7, #4]
|
|
8006c36: 60da str r2, [r3, #12]
|
|
|
|
if (mode == USB_HOST_MODE)
|
|
8006c38: 78fb ldrb r3, [r7, #3]
|
|
8006c3a: 2b01 cmp r3, #1
|
|
8006c3c: d115 bne.n 8006c6a <USB_SetCurrentMode+0x4e>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
|
|
8006c3e: 687b ldr r3, [r7, #4]
|
|
8006c40: 68db ldr r3, [r3, #12]
|
|
8006c42: f043 5200 orr.w r2, r3, #536870912 @ 0x20000000
|
|
8006c46: 687b ldr r3, [r7, #4]
|
|
8006c48: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8006c4a: 200a movs r0, #10
|
|
8006c4c: f7fa fd52 bl 80016f4 <HAL_Delay>
|
|
ms += 10U;
|
|
8006c50: 68fb ldr r3, [r7, #12]
|
|
8006c52: 330a adds r3, #10
|
|
8006c54: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8006c56: 6878 ldr r0, [r7, #4]
|
|
8006c58: f000 f956 bl 8006f08 <USB_GetMode>
|
|
8006c5c: 4603 mov r3, r0
|
|
8006c5e: 2b01 cmp r3, #1
|
|
8006c60: d01e beq.n 8006ca0 <USB_SetCurrentMode+0x84>
|
|
8006c62: 68fb ldr r3, [r7, #12]
|
|
8006c64: 2bc7 cmp r3, #199 @ 0xc7
|
|
8006c66: d9f0 bls.n 8006c4a <USB_SetCurrentMode+0x2e>
|
|
8006c68: e01a b.n 8006ca0 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else if (mode == USB_DEVICE_MODE)
|
|
8006c6a: 78fb ldrb r3, [r7, #3]
|
|
8006c6c: 2b00 cmp r3, #0
|
|
8006c6e: d115 bne.n 8006c9c <USB_SetCurrentMode+0x80>
|
|
{
|
|
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
|
|
8006c70: 687b ldr r3, [r7, #4]
|
|
8006c72: 68db ldr r3, [r3, #12]
|
|
8006c74: f043 4280 orr.w r2, r3, #1073741824 @ 0x40000000
|
|
8006c78: 687b ldr r3, [r7, #4]
|
|
8006c7a: 60da str r2, [r3, #12]
|
|
|
|
do
|
|
{
|
|
HAL_Delay(10U);
|
|
8006c7c: 200a movs r0, #10
|
|
8006c7e: f7fa fd39 bl 80016f4 <HAL_Delay>
|
|
ms += 10U;
|
|
8006c82: 68fb ldr r3, [r7, #12]
|
|
8006c84: 330a adds r3, #10
|
|
8006c86: 60fb str r3, [r7, #12]
|
|
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
|
|
8006c88: 6878 ldr r0, [r7, #4]
|
|
8006c8a: f000 f93d bl 8006f08 <USB_GetMode>
|
|
8006c8e: 4603 mov r3, r0
|
|
8006c90: 2b00 cmp r3, #0
|
|
8006c92: d005 beq.n 8006ca0 <USB_SetCurrentMode+0x84>
|
|
8006c94: 68fb ldr r3, [r7, #12]
|
|
8006c96: 2bc7 cmp r3, #199 @ 0xc7
|
|
8006c98: d9f0 bls.n 8006c7c <USB_SetCurrentMode+0x60>
|
|
8006c9a: e001 b.n 8006ca0 <USB_SetCurrentMode+0x84>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8006c9c: 2301 movs r3, #1
|
|
8006c9e: e005 b.n 8006cac <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
|
|
8006ca0: 68fb ldr r3, [r7, #12]
|
|
8006ca2: 2bc8 cmp r3, #200 @ 0xc8
|
|
8006ca4: d101 bne.n 8006caa <USB_SetCurrentMode+0x8e>
|
|
{
|
|
return HAL_ERROR;
|
|
8006ca6: 2301 movs r3, #1
|
|
8006ca8: e000 b.n 8006cac <USB_SetCurrentMode+0x90>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006caa: 2300 movs r3, #0
|
|
}
|
|
8006cac: 4618 mov r0, r3
|
|
8006cae: 3710 adds r7, #16
|
|
8006cb0: 46bd mov sp, r7
|
|
8006cb2: bd80 pop {r7, pc}
|
|
|
|
08006cb4 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
8006cb4: b480 push {r7}
|
|
8006cb6: b085 sub sp, #20
|
|
8006cb8: af00 add r7, sp, #0
|
|
8006cba: 6078 str r0, [r7, #4]
|
|
8006cbc: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
8006cbe: 2300 movs r3, #0
|
|
8006cc0: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006cc2: 68fb ldr r3, [r7, #12]
|
|
8006cc4: 3301 adds r3, #1
|
|
8006cc6: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006cc8: 68fb ldr r3, [r7, #12]
|
|
8006cca: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006cce: d901 bls.n 8006cd4 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006cd0: 2303 movs r3, #3
|
|
8006cd2: e01b b.n 8006d0c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006cd4: 687b ldr r3, [r7, #4]
|
|
8006cd6: 691b ldr r3, [r3, #16]
|
|
8006cd8: 2b00 cmp r3, #0
|
|
8006cda: daf2 bge.n 8006cc2 <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
8006cdc: 2300 movs r3, #0
|
|
8006cde: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
8006ce0: 683b ldr r3, [r7, #0]
|
|
8006ce2: 019b lsls r3, r3, #6
|
|
8006ce4: f043 0220 orr.w r2, r3, #32
|
|
8006ce8: 687b ldr r3, [r7, #4]
|
|
8006cea: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006cec: 68fb ldr r3, [r7, #12]
|
|
8006cee: 3301 adds r3, #1
|
|
8006cf0: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006cf2: 68fb ldr r3, [r7, #12]
|
|
8006cf4: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006cf8: d901 bls.n 8006cfe <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006cfa: 2303 movs r3, #3
|
|
8006cfc: e006 b.n 8006d0c <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
8006cfe: 687b ldr r3, [r7, #4]
|
|
8006d00: 691b ldr r3, [r3, #16]
|
|
8006d02: f003 0320 and.w r3, r3, #32
|
|
8006d06: 2b20 cmp r3, #32
|
|
8006d08: d0f0 beq.n 8006cec <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
8006d0a: 2300 movs r3, #0
|
|
}
|
|
8006d0c: 4618 mov r0, r3
|
|
8006d0e: 3714 adds r7, #20
|
|
8006d10: 46bd mov sp, r7
|
|
8006d12: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d16: 4770 bx lr
|
|
|
|
08006d18 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006d18: b480 push {r7}
|
|
8006d1a: b085 sub sp, #20
|
|
8006d1c: af00 add r7, sp, #0
|
|
8006d1e: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8006d20: 2300 movs r3, #0
|
|
8006d22: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006d24: 68fb ldr r3, [r7, #12]
|
|
8006d26: 3301 adds r3, #1
|
|
8006d28: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006d2a: 68fb ldr r3, [r7, #12]
|
|
8006d2c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006d30: d901 bls.n 8006d36 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006d32: 2303 movs r3, #3
|
|
8006d34: e018 b.n 8006d68 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006d36: 687b ldr r3, [r7, #4]
|
|
8006d38: 691b ldr r3, [r3, #16]
|
|
8006d3a: 2b00 cmp r3, #0
|
|
8006d3c: daf2 bge.n 8006d24 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
8006d3e: 2300 movs r3, #0
|
|
8006d40: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
8006d42: 687b ldr r3, [r7, #4]
|
|
8006d44: 2210 movs r2, #16
|
|
8006d46: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006d48: 68fb ldr r3, [r7, #12]
|
|
8006d4a: 3301 adds r3, #1
|
|
8006d4c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006d4e: 68fb ldr r3, [r7, #12]
|
|
8006d50: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006d54: d901 bls.n 8006d5a <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006d56: 2303 movs r3, #3
|
|
8006d58: e006 b.n 8006d68 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
8006d5a: 687b ldr r3, [r7, #4]
|
|
8006d5c: 691b ldr r3, [r3, #16]
|
|
8006d5e: f003 0310 and.w r3, r3, #16
|
|
8006d62: 2b10 cmp r3, #16
|
|
8006d64: d0f0 beq.n 8006d48 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
8006d66: 2300 movs r3, #0
|
|
}
|
|
8006d68: 4618 mov r0, r3
|
|
8006d6a: 3714 adds r7, #20
|
|
8006d6c: 46bd mov sp, r7
|
|
8006d6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d72: 4770 bx lr
|
|
|
|
08006d74 <USB_WritePacket>:
|
|
* 1 : DMA feature used
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
|
|
uint8_t ch_ep_num, uint16_t len, uint8_t dma)
|
|
{
|
|
8006d74: b480 push {r7}
|
|
8006d76: b089 sub sp, #36 @ 0x24
|
|
8006d78: af00 add r7, sp, #0
|
|
8006d7a: 60f8 str r0, [r7, #12]
|
|
8006d7c: 60b9 str r1, [r7, #8]
|
|
8006d7e: 4611 mov r1, r2
|
|
8006d80: 461a mov r2, r3
|
|
8006d82: 460b mov r3, r1
|
|
8006d84: 71fb strb r3, [r7, #7]
|
|
8006d86: 4613 mov r3, r2
|
|
8006d88: 80bb strh r3, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006d8a: 68fb ldr r3, [r7, #12]
|
|
8006d8c: 617b str r3, [r7, #20]
|
|
uint8_t *pSrc = src;
|
|
8006d8e: 68bb ldr r3, [r7, #8]
|
|
8006d90: 61fb str r3, [r7, #28]
|
|
uint32_t count32b;
|
|
uint32_t i;
|
|
|
|
if (dma == 0U)
|
|
8006d92: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8006d96: 2b00 cmp r3, #0
|
|
8006d98: d123 bne.n 8006de2 <USB_WritePacket+0x6e>
|
|
{
|
|
count32b = ((uint32_t)len + 3U) / 4U;
|
|
8006d9a: 88bb ldrh r3, [r7, #4]
|
|
8006d9c: 3303 adds r3, #3
|
|
8006d9e: 089b lsrs r3, r3, #2
|
|
8006da0: 613b str r3, [r7, #16]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006da2: 2300 movs r3, #0
|
|
8006da4: 61bb str r3, [r7, #24]
|
|
8006da6: e018 b.n 8006dda <USB_WritePacket+0x66>
|
|
{
|
|
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
|
|
8006da8: 79fb ldrb r3, [r7, #7]
|
|
8006daa: 031a lsls r2, r3, #12
|
|
8006dac: 697b ldr r3, [r7, #20]
|
|
8006dae: 4413 add r3, r2
|
|
8006db0: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006db4: 461a mov r2, r3
|
|
8006db6: 69fb ldr r3, [r7, #28]
|
|
8006db8: 681b ldr r3, [r3, #0]
|
|
8006dba: 6013 str r3, [r2, #0]
|
|
pSrc++;
|
|
8006dbc: 69fb ldr r3, [r7, #28]
|
|
8006dbe: 3301 adds r3, #1
|
|
8006dc0: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006dc2: 69fb ldr r3, [r7, #28]
|
|
8006dc4: 3301 adds r3, #1
|
|
8006dc6: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006dc8: 69fb ldr r3, [r7, #28]
|
|
8006dca: 3301 adds r3, #1
|
|
8006dcc: 61fb str r3, [r7, #28]
|
|
pSrc++;
|
|
8006dce: 69fb ldr r3, [r7, #28]
|
|
8006dd0: 3301 adds r3, #1
|
|
8006dd2: 61fb str r3, [r7, #28]
|
|
for (i = 0U; i < count32b; i++)
|
|
8006dd4: 69bb ldr r3, [r7, #24]
|
|
8006dd6: 3301 adds r3, #1
|
|
8006dd8: 61bb str r3, [r7, #24]
|
|
8006dda: 69ba ldr r2, [r7, #24]
|
|
8006ddc: 693b ldr r3, [r7, #16]
|
|
8006dde: 429a cmp r2, r3
|
|
8006de0: d3e2 bcc.n 8006da8 <USB_WritePacket+0x34>
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006de2: 2300 movs r3, #0
|
|
}
|
|
8006de4: 4618 mov r0, r3
|
|
8006de6: 3724 adds r7, #36 @ 0x24
|
|
8006de8: 46bd mov sp, r7
|
|
8006dea: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006dee: 4770 bx lr
|
|
|
|
08006df0 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8006df0: b480 push {r7}
|
|
8006df2: b08b sub sp, #44 @ 0x2c
|
|
8006df4: af00 add r7, sp, #0
|
|
8006df6: 60f8 str r0, [r7, #12]
|
|
8006df8: 60b9 str r1, [r7, #8]
|
|
8006dfa: 4613 mov r3, r2
|
|
8006dfc: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006dfe: 68fb ldr r3, [r7, #12]
|
|
8006e00: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8006e02: 68bb ldr r3, [r7, #8]
|
|
8006e04: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8006e06: 88fb ldrh r3, [r7, #6]
|
|
8006e08: 089b lsrs r3, r3, #2
|
|
8006e0a: b29b uxth r3, r3
|
|
8006e0c: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
8006e0e: 88fb ldrh r3, [r7, #6]
|
|
8006e10: f003 0303 and.w r3, r3, #3
|
|
8006e14: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8006e16: 2300 movs r3, #0
|
|
8006e18: 623b str r3, [r7, #32]
|
|
8006e1a: e014 b.n 8006e46 <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
8006e1c: 69bb ldr r3, [r7, #24]
|
|
8006e1e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006e22: 681a ldr r2, [r3, #0]
|
|
8006e24: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e26: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8006e28: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e2a: 3301 adds r3, #1
|
|
8006e2c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006e2e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e30: 3301 adds r3, #1
|
|
8006e32: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006e34: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e36: 3301 adds r3, #1
|
|
8006e38: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006e3a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e3c: 3301 adds r3, #1
|
|
8006e3e: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8006e40: 6a3b ldr r3, [r7, #32]
|
|
8006e42: 3301 adds r3, #1
|
|
8006e44: 623b str r3, [r7, #32]
|
|
8006e46: 6a3a ldr r2, [r7, #32]
|
|
8006e48: 697b ldr r3, [r7, #20]
|
|
8006e4a: 429a cmp r2, r3
|
|
8006e4c: d3e6 bcc.n 8006e1c <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
8006e4e: 8bfb ldrh r3, [r7, #30]
|
|
8006e50: 2b00 cmp r3, #0
|
|
8006e52: d01e beq.n 8006e92 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
8006e54: 2300 movs r3, #0
|
|
8006e56: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
8006e58: 69bb ldr r3, [r7, #24]
|
|
8006e5a: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006e5e: 461a mov r2, r3
|
|
8006e60: f107 0310 add.w r3, r7, #16
|
|
8006e64: 6812 ldr r2, [r2, #0]
|
|
8006e66: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
8006e68: 693a ldr r2, [r7, #16]
|
|
8006e6a: 6a3b ldr r3, [r7, #32]
|
|
8006e6c: b2db uxtb r3, r3
|
|
8006e6e: 00db lsls r3, r3, #3
|
|
8006e70: fa22 f303 lsr.w r3, r2, r3
|
|
8006e74: b2da uxtb r2, r3
|
|
8006e76: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e78: 701a strb r2, [r3, #0]
|
|
i++;
|
|
8006e7a: 6a3b ldr r3, [r7, #32]
|
|
8006e7c: 3301 adds r3, #1
|
|
8006e7e: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
8006e80: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006e82: 3301 adds r3, #1
|
|
8006e84: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
8006e86: 8bfb ldrh r3, [r7, #30]
|
|
8006e88: 3b01 subs r3, #1
|
|
8006e8a: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
8006e8c: 8bfb ldrh r3, [r7, #30]
|
|
8006e8e: 2b00 cmp r3, #0
|
|
8006e90: d1ea bne.n 8006e68 <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
8006e92: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
8006e94: 4618 mov r0, r3
|
|
8006e96: 372c adds r7, #44 @ 0x2c
|
|
8006e98: 46bd mov sp, r7
|
|
8006e9a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006e9e: 4770 bx lr
|
|
|
|
08006ea0 <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
8006ea0: b480 push {r7}
|
|
8006ea2: b085 sub sp, #20
|
|
8006ea4: af00 add r7, sp, #0
|
|
8006ea6: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
8006ea8: 687b ldr r3, [r7, #4]
|
|
8006eaa: 695b ldr r3, [r3, #20]
|
|
8006eac: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
8006eae: 687b ldr r3, [r7, #4]
|
|
8006eb0: 699b ldr r3, [r3, #24]
|
|
8006eb2: 68fa ldr r2, [r7, #12]
|
|
8006eb4: 4013 ands r3, r2
|
|
8006eb6: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8006eb8: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8006eba: 4618 mov r0, r3
|
|
8006ebc: 3714 adds r7, #20
|
|
8006ebe: 46bd mov sp, r7
|
|
8006ec0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ec4: 4770 bx lr
|
|
|
|
08006ec6 <USB_ReadChInterrupts>:
|
|
* @param USBx Selected device
|
|
* @param chnum Channel number
|
|
* @retval USB Channel Interrupt status
|
|
*/
|
|
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
|
|
{
|
|
8006ec6: b480 push {r7}
|
|
8006ec8: b085 sub sp, #20
|
|
8006eca: af00 add r7, sp, #0
|
|
8006ecc: 6078 str r0, [r7, #4]
|
|
8006ece: 460b mov r3, r1
|
|
8006ed0: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006ed2: 687b ldr r3, [r7, #4]
|
|
8006ed4: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_HC(chnum)->HCINT;
|
|
8006ed6: 78fb ldrb r3, [r7, #3]
|
|
8006ed8: 015a lsls r2, r3, #5
|
|
8006eda: 68fb ldr r3, [r7, #12]
|
|
8006edc: 4413 add r3, r2
|
|
8006ede: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006ee2: 689b ldr r3, [r3, #8]
|
|
8006ee4: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_HC(chnum)->HCINTMSK;
|
|
8006ee6: 78fb ldrb r3, [r7, #3]
|
|
8006ee8: 015a lsls r2, r3, #5
|
|
8006eea: 68fb ldr r3, [r7, #12]
|
|
8006eec: 4413 add r3, r2
|
|
8006eee: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006ef2: 68db ldr r3, [r3, #12]
|
|
8006ef4: 68ba ldr r2, [r7, #8]
|
|
8006ef6: 4013 ands r3, r2
|
|
8006ef8: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
8006efa: 68bb ldr r3, [r7, #8]
|
|
}
|
|
8006efc: 4618 mov r0, r3
|
|
8006efe: 3714 adds r7, #20
|
|
8006f00: 46bd mov sp, r7
|
|
8006f02: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f06: 4770 bx lr
|
|
|
|
08006f08 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f08: b480 push {r7}
|
|
8006f0a: b083 sub sp, #12
|
|
8006f0c: af00 add r7, sp, #0
|
|
8006f0e: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
8006f10: 687b ldr r3, [r7, #4]
|
|
8006f12: 695b ldr r3, [r3, #20]
|
|
8006f14: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8006f18: 4618 mov r0, r3
|
|
8006f1a: 370c adds r7, #12
|
|
8006f1c: 46bd mov sp, r7
|
|
8006f1e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f22: 4770 bx lr
|
|
|
|
08006f24 <USB_CoreReset>:
|
|
* @brief Reset the USB Core (needed after USB clock settings change)
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006f24: b480 push {r7}
|
|
8006f26: b085 sub sp, #20
|
|
8006f28: af00 add r7, sp, #0
|
|
8006f2a: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
8006f2c: 2300 movs r3, #0
|
|
8006f2e: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
8006f30: 68fb ldr r3, [r7, #12]
|
|
8006f32: 3301 adds r3, #1
|
|
8006f34: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006f36: 68fb ldr r3, [r7, #12]
|
|
8006f38: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006f3c: d901 bls.n 8006f42 <USB_CoreReset+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006f3e: 2303 movs r3, #3
|
|
8006f40: e022 b.n 8006f88 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006f42: 687b ldr r3, [r7, #4]
|
|
8006f44: 691b ldr r3, [r3, #16]
|
|
8006f46: 2b00 cmp r3, #0
|
|
8006f48: daf2 bge.n 8006f30 <USB_CoreReset+0xc>
|
|
|
|
count = 10U;
|
|
8006f4a: 230a movs r3, #10
|
|
8006f4c: 60fb str r3, [r7, #12]
|
|
|
|
/* few cycles before setting core reset */
|
|
while (count > 0U)
|
|
8006f4e: e002 b.n 8006f56 <USB_CoreReset+0x32>
|
|
{
|
|
count--;
|
|
8006f50: 68fb ldr r3, [r7, #12]
|
|
8006f52: 3b01 subs r3, #1
|
|
8006f54: 60fb str r3, [r7, #12]
|
|
while (count > 0U)
|
|
8006f56: 68fb ldr r3, [r7, #12]
|
|
8006f58: 2b00 cmp r3, #0
|
|
8006f5a: d1f9 bne.n 8006f50 <USB_CoreReset+0x2c>
|
|
}
|
|
|
|
/* Core Soft Reset */
|
|
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
|
|
8006f5c: 687b ldr r3, [r7, #4]
|
|
8006f5e: 691b ldr r3, [r3, #16]
|
|
8006f60: f043 0201 orr.w r2, r3, #1
|
|
8006f64: 687b ldr r3, [r7, #4]
|
|
8006f66: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006f68: 68fb ldr r3, [r7, #12]
|
|
8006f6a: 3301 adds r3, #1
|
|
8006f6c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006f6e: 68fb ldr r3, [r7, #12]
|
|
8006f70: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006f74: d901 bls.n 8006f7a <USB_CoreReset+0x56>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006f76: 2303 movs r3, #3
|
|
8006f78: e006 b.n 8006f88 <USB_CoreReset+0x64>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
|
|
8006f7a: 687b ldr r3, [r7, #4]
|
|
8006f7c: 691b ldr r3, [r3, #16]
|
|
8006f7e: f003 0301 and.w r3, r3, #1
|
|
8006f82: 2b01 cmp r3, #1
|
|
8006f84: d0f0 beq.n 8006f68 <USB_CoreReset+0x44>
|
|
|
|
return HAL_OK;
|
|
8006f86: 2300 movs r3, #0
|
|
}
|
|
8006f88: 4618 mov r0, r3
|
|
8006f8a: 3714 adds r7, #20
|
|
8006f8c: 46bd mov sp, r7
|
|
8006f8e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006f92: 4770 bx lr
|
|
|
|
08006f94 <USB_HostInit>:
|
|
* @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
|
|
* the configuration information for the specified USBx peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
|
|
{
|
|
8006f94: b084 sub sp, #16
|
|
8006f96: b580 push {r7, lr}
|
|
8006f98: b086 sub sp, #24
|
|
8006f9a: af00 add r7, sp, #0
|
|
8006f9c: 6078 str r0, [r7, #4]
|
|
8006f9e: f107 0024 add.w r0, r7, #36 @ 0x24
|
|
8006fa2: e880 000e stmia.w r0, {r1, r2, r3}
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8006fa6: 2300 movs r3, #0
|
|
8006fa8: 75fb strb r3, [r7, #23]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006faa: 687b ldr r3, [r7, #4]
|
|
8006fac: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
|
|
/* Restart the Phy Clock */
|
|
USBx_PCGCCTL = 0U;
|
|
8006fae: 68fb ldr r3, [r7, #12]
|
|
8006fb0: f503 6360 add.w r3, r3, #3584 @ 0xe00
|
|
8006fb4: 461a mov r2, r3
|
|
8006fb6: 2300 movs r3, #0
|
|
8006fb8: 6013 str r3, [r2, #0]
|
|
#else
|
|
/*
|
|
* Disable HW VBUS sensing. VBUS is internally considered to be always
|
|
* at VBUS-Valid level (5V).
|
|
*/
|
|
USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
|
8006fba: 687b ldr r3, [r7, #4]
|
|
8006fbc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006fbe: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
|
|
8006fc2: 687b ldr r3, [r7, #4]
|
|
8006fc4: 639a str r2, [r3, #56] @ 0x38
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
|
|
8006fc6: 687b ldr r3, [r7, #4]
|
|
8006fc8: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006fca: f423 2200 bic.w r2, r3, #524288 @ 0x80000
|
|
8006fce: 687b ldr r3, [r7, #4]
|
|
8006fd0: 639a str r2, [r3, #56] @ 0x38
|
|
USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
|
|
8006fd2: 687b ldr r3, [r7, #4]
|
|
8006fd4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006fd6: f423 2280 bic.w r2, r3, #262144 @ 0x40000
|
|
8006fda: 687b ldr r3, [r7, #4]
|
|
8006fdc: 639a str r2, [r3, #56] @ 0x38
|
|
/* Disable Battery chargin detector */
|
|
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
|
|
#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||
|
|
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */
|
|
|
|
if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
|
|
8006fde: 687b ldr r3, [r7, #4]
|
|
8006fe0: 68db ldr r3, [r3, #12]
|
|
8006fe2: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8006fe6: 2b00 cmp r3, #0
|
|
8006fe8: d119 bne.n 800701e <USB_HostInit+0x8a>
|
|
{
|
|
if (cfg.speed == USBH_FSLS_SPEED)
|
|
8006fea: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8006fee: 2b01 cmp r3, #1
|
|
8006ff0: d10a bne.n 8007008 <USB_HostInit+0x74>
|
|
{
|
|
/* Force Device Enumeration to FS/LS mode only */
|
|
USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
|
|
8006ff2: 68fb ldr r3, [r7, #12]
|
|
8006ff4: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8006ff8: 681b ldr r3, [r3, #0]
|
|
8006ffa: 68fa ldr r2, [r7, #12]
|
|
8006ffc: f502 6280 add.w r2, r2, #1024 @ 0x400
|
|
8007000: f043 0304 orr.w r3, r3, #4
|
|
8007004: 6013 str r3, [r2, #0]
|
|
8007006: e014 b.n 8007032 <USB_HostInit+0x9e>
|
|
}
|
|
else
|
|
{
|
|
/* Set default Max speed support */
|
|
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
|
|
8007008: 68fb ldr r3, [r7, #12]
|
|
800700a: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800700e: 681b ldr r3, [r3, #0]
|
|
8007010: 68fa ldr r2, [r7, #12]
|
|
8007012: f502 6280 add.w r2, r2, #1024 @ 0x400
|
|
8007016: f023 0304 bic.w r3, r3, #4
|
|
800701a: 6013 str r3, [r2, #0]
|
|
800701c: e009 b.n 8007032 <USB_HostInit+0x9e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set default Max speed support */
|
|
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
|
|
800701e: 68fb ldr r3, [r7, #12]
|
|
8007020: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007024: 681b ldr r3, [r3, #0]
|
|
8007026: 68fa ldr r2, [r7, #12]
|
|
8007028: f502 6280 add.w r2, r2, #1024 @ 0x400
|
|
800702c: f023 0304 bic.w r3, r3, #4
|
|
8007030: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Make sure the FIFOs are flushed. */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
8007032: 2110 movs r1, #16
|
|
8007034: 6878 ldr r0, [r7, #4]
|
|
8007036: f7ff fe3d bl 8006cb4 <USB_FlushTxFifo>
|
|
800703a: 4603 mov r3, r0
|
|
800703c: 2b00 cmp r3, #0
|
|
800703e: d001 beq.n 8007044 <USB_HostInit+0xb0>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007040: 2301 movs r3, #1
|
|
8007042: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
8007044: 6878 ldr r0, [r7, #4]
|
|
8007046: f7ff fe67 bl 8006d18 <USB_FlushRxFifo>
|
|
800704a: 4603 mov r3, r0
|
|
800704c: 2b00 cmp r3, #0
|
|
800704e: d001 beq.n 8007054 <USB_HostInit+0xc0>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007050: 2301 movs r3, #1
|
|
8007052: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
/* Clear all pending HC Interrupts */
|
|
for (i = 0U; i < cfg.Host_channels; i++)
|
|
8007054: 2300 movs r3, #0
|
|
8007056: 613b str r3, [r7, #16]
|
|
8007058: e015 b.n 8007086 <USB_HostInit+0xf2>
|
|
{
|
|
USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK;
|
|
800705a: 693b ldr r3, [r7, #16]
|
|
800705c: 015a lsls r2, r3, #5
|
|
800705e: 68fb ldr r3, [r7, #12]
|
|
8007060: 4413 add r3, r2
|
|
8007062: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007066: 461a mov r2, r3
|
|
8007068: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800706c: 6093 str r3, [r2, #8]
|
|
USBx_HC(i)->HCINTMSK = 0U;
|
|
800706e: 693b ldr r3, [r7, #16]
|
|
8007070: 015a lsls r2, r3, #5
|
|
8007072: 68fb ldr r3, [r7, #12]
|
|
8007074: 4413 add r3, r2
|
|
8007076: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800707a: 461a mov r2, r3
|
|
800707c: 2300 movs r3, #0
|
|
800707e: 60d3 str r3, [r2, #12]
|
|
for (i = 0U; i < cfg.Host_channels; i++)
|
|
8007080: 693b ldr r3, [r7, #16]
|
|
8007082: 3301 adds r3, #1
|
|
8007084: 613b str r3, [r7, #16]
|
|
8007086: f897 3025 ldrb.w r3, [r7, #37] @ 0x25
|
|
800708a: 461a mov r2, r3
|
|
800708c: 693b ldr r3, [r7, #16]
|
|
800708e: 4293 cmp r3, r2
|
|
8007090: d3e3 bcc.n 800705a <USB_HostInit+0xc6>
|
|
}
|
|
|
|
/* Disable all interrupts. */
|
|
USBx->GINTMSK = 0U;
|
|
8007092: 687b ldr r3, [r7, #4]
|
|
8007094: 2200 movs r2, #0
|
|
8007096: 619a str r2, [r3, #24]
|
|
|
|
/* Clear any pending interrupts */
|
|
USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
|
|
8007098: 687b ldr r3, [r7, #4]
|
|
800709a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800709e: 615a str r2, [r3, #20]
|
|
#if defined (USB_OTG_HS)
|
|
if (USBx == USB_OTG_HS)
|
|
80070a0: 687b ldr r3, [r7, #4]
|
|
80070a2: 4a18 ldr r2, [pc, #96] @ (8007104 <USB_HostInit+0x170>)
|
|
80070a4: 4293 cmp r3, r2
|
|
80070a6: d10b bne.n 80070c0 <USB_HostInit+0x12c>
|
|
{
|
|
/* set Rx FIFO size */
|
|
USBx->GRXFSIZ = 0x200U;
|
|
80070a8: 687b ldr r3, [r7, #4]
|
|
80070aa: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80070ae: 625a str r2, [r3, #36] @ 0x24
|
|
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
|
|
80070b0: 687b ldr r3, [r7, #4]
|
|
80070b2: 4a15 ldr r2, [pc, #84] @ (8007108 <USB_HostInit+0x174>)
|
|
80070b4: 629a str r2, [r3, #40] @ 0x28
|
|
USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
|
|
80070b6: 687b ldr r3, [r7, #4]
|
|
80070b8: 4a14 ldr r2, [pc, #80] @ (800710c <USB_HostInit+0x178>)
|
|
80070ba: f8c3 2100 str.w r2, [r3, #256] @ 0x100
|
|
80070be: e009 b.n 80070d4 <USB_HostInit+0x140>
|
|
}
|
|
else
|
|
#endif /* defined (USB_OTG_HS) */
|
|
{
|
|
/* set Rx FIFO size */
|
|
USBx->GRXFSIZ = 0x80U;
|
|
80070c0: 687b ldr r3, [r7, #4]
|
|
80070c2: 2280 movs r2, #128 @ 0x80
|
|
80070c4: 625a str r2, [r3, #36] @ 0x24
|
|
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
|
|
80070c6: 687b ldr r3, [r7, #4]
|
|
80070c8: 4a11 ldr r2, [pc, #68] @ (8007110 <USB_HostInit+0x17c>)
|
|
80070ca: 629a str r2, [r3, #40] @ 0x28
|
|
USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
|
|
80070cc: 687b ldr r3, [r7, #4]
|
|
80070ce: 4a11 ldr r2, [pc, #68] @ (8007114 <USB_HostInit+0x180>)
|
|
80070d0: f8c3 2100 str.w r2, [r3, #256] @ 0x100
|
|
}
|
|
|
|
/* Enable the common interrupts */
|
|
if (cfg.dma_enable == 0U)
|
|
80070d4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
80070d8: 2b00 cmp r3, #0
|
|
80070da: d105 bne.n 80070e8 <USB_HostInit+0x154>
|
|
{
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
|
|
80070dc: 687b ldr r3, [r7, #4]
|
|
80070de: 699b ldr r3, [r3, #24]
|
|
80070e0: f043 0210 orr.w r2, r3, #16
|
|
80070e4: 687b ldr r3, [r7, #4]
|
|
80070e6: 619a str r2, [r3, #24]
|
|
}
|
|
|
|
/* Enable interrupts matching to the Host mode ONLY */
|
|
USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \
|
|
80070e8: 687b ldr r3, [r7, #4]
|
|
80070ea: 699a ldr r2, [r3, #24]
|
|
80070ec: 4b0a ldr r3, [pc, #40] @ (8007118 <USB_HostInit+0x184>)
|
|
80070ee: 4313 orrs r3, r2
|
|
80070f0: 687a ldr r2, [r7, #4]
|
|
80070f2: 6193 str r3, [r2, #24]
|
|
USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \
|
|
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
|
|
|
|
return ret;
|
|
80070f4: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
80070f6: 4618 mov r0, r3
|
|
80070f8: 3718 adds r7, #24
|
|
80070fa: 46bd mov sp, r7
|
|
80070fc: e8bd 4080 ldmia.w sp!, {r7, lr}
|
|
8007100: b004 add sp, #16
|
|
8007102: 4770 bx lr
|
|
8007104: 40040000 .word 0x40040000
|
|
8007108: 01000200 .word 0x01000200
|
|
800710c: 00e00300 .word 0x00e00300
|
|
8007110: 00600080 .word 0x00600080
|
|
8007114: 004000e0 .word 0x004000e0
|
|
8007118: a3200008 .word 0xa3200008
|
|
|
|
0800711c <USB_InitFSLSPClkSel>:
|
|
* HCFG_48_MHZ : Full Speed 48 MHz Clock
|
|
* HCFG_6_MHZ : Low Speed 6 MHz Clock
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
|
|
{
|
|
800711c: b480 push {r7}
|
|
800711e: b085 sub sp, #20
|
|
8007120: af00 add r7, sp, #0
|
|
8007122: 6078 str r0, [r7, #4]
|
|
8007124: 460b mov r3, r1
|
|
8007126: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007128: 687b ldr r3, [r7, #4]
|
|
800712a: 60fb str r3, [r7, #12]
|
|
|
|
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
|
|
800712c: 68fb ldr r3, [r7, #12]
|
|
800712e: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007132: 681b ldr r3, [r3, #0]
|
|
8007134: 68fa ldr r2, [r7, #12]
|
|
8007136: f502 6280 add.w r2, r2, #1024 @ 0x400
|
|
800713a: f023 0303 bic.w r3, r3, #3
|
|
800713e: 6013 str r3, [r2, #0]
|
|
USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
|
|
8007140: 68fb ldr r3, [r7, #12]
|
|
8007142: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007146: 681a ldr r2, [r3, #0]
|
|
8007148: 78fb ldrb r3, [r7, #3]
|
|
800714a: f003 0303 and.w r3, r3, #3
|
|
800714e: 68f9 ldr r1, [r7, #12]
|
|
8007150: f501 6180 add.w r1, r1, #1024 @ 0x400
|
|
8007154: 4313 orrs r3, r2
|
|
8007156: 600b str r3, [r1, #0]
|
|
|
|
if (freq == HCFG_48_MHZ)
|
|
8007158: 78fb ldrb r3, [r7, #3]
|
|
800715a: 2b01 cmp r3, #1
|
|
800715c: d107 bne.n 800716e <USB_InitFSLSPClkSel+0x52>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_48_MHZ;
|
|
800715e: 68fb ldr r3, [r7, #12]
|
|
8007160: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007164: 461a mov r2, r3
|
|
8007166: f64b 3380 movw r3, #48000 @ 0xbb80
|
|
800716a: 6053 str r3, [r2, #4]
|
|
800716c: e00c b.n 8007188 <USB_InitFSLSPClkSel+0x6c>
|
|
}
|
|
else if (freq == HCFG_6_MHZ)
|
|
800716e: 78fb ldrb r3, [r7, #3]
|
|
8007170: 2b02 cmp r3, #2
|
|
8007172: d107 bne.n 8007184 <USB_InitFSLSPClkSel+0x68>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_6_MHZ;
|
|
8007174: 68fb ldr r3, [r7, #12]
|
|
8007176: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800717a: 461a mov r2, r3
|
|
800717c: f241 7370 movw r3, #6000 @ 0x1770
|
|
8007180: 6053 str r3, [r2, #4]
|
|
8007182: e001 b.n 8007188 <USB_InitFSLSPClkSel+0x6c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
8007184: 2301 movs r3, #1
|
|
8007186: e000 b.n 800718a <USB_InitFSLSPClkSel+0x6e>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007188: 2300 movs r3, #0
|
|
}
|
|
800718a: 4618 mov r0, r3
|
|
800718c: 3714 adds r7, #20
|
|
800718e: 46bd mov sp, r7
|
|
8007190: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007194: 4770 bx lr
|
|
|
|
08007196 <USB_ResetPort>:
|
|
* @retval HAL status
|
|
* @note (1)The application must wait at least 10 ms
|
|
* before clearing the reset bit.
|
|
*/
|
|
HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007196: b580 push {r7, lr}
|
|
8007198: b084 sub sp, #16
|
|
800719a: af00 add r7, sp, #0
|
|
800719c: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800719e: 687b ldr r3, [r7, #4]
|
|
80071a0: 60fb str r3, [r7, #12]
|
|
|
|
__IO uint32_t hprt0 = 0U;
|
|
80071a2: 2300 movs r3, #0
|
|
80071a4: 60bb str r3, [r7, #8]
|
|
|
|
hprt0 = USBx_HPRT0;
|
|
80071a6: 68fb ldr r3, [r7, #12]
|
|
80071a8: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
80071ac: 681b ldr r3, [r3, #0]
|
|
80071ae: 60bb str r3, [r7, #8]
|
|
|
|
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
|
|
80071b0: 68bb ldr r3, [r7, #8]
|
|
80071b2: f023 032e bic.w r3, r3, #46 @ 0x2e
|
|
80071b6: 60bb str r3, [r7, #8]
|
|
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
|
|
|
|
USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
|
|
80071b8: 68bb ldr r3, [r7, #8]
|
|
80071ba: 68fa ldr r2, [r7, #12]
|
|
80071bc: f502 6288 add.w r2, r2, #1088 @ 0x440
|
|
80071c0: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80071c4: 6013 str r3, [r2, #0]
|
|
HAL_Delay(100U); /* See Note #1 */
|
|
80071c6: 2064 movs r0, #100 @ 0x64
|
|
80071c8: f7fa fa94 bl 80016f4 <HAL_Delay>
|
|
USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
|
|
80071cc: 68bb ldr r3, [r7, #8]
|
|
80071ce: 68fa ldr r2, [r7, #12]
|
|
80071d0: f502 6288 add.w r2, r2, #1088 @ 0x440
|
|
80071d4: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
80071d8: 6013 str r3, [r2, #0]
|
|
HAL_Delay(10U);
|
|
80071da: 200a movs r0, #10
|
|
80071dc: f7fa fa8a bl 80016f4 <HAL_Delay>
|
|
|
|
return HAL_OK;
|
|
80071e0: 2300 movs r3, #0
|
|
}
|
|
80071e2: 4618 mov r0, r3
|
|
80071e4: 3710 adds r7, #16
|
|
80071e6: 46bd mov sp, r7
|
|
80071e8: bd80 pop {r7, pc}
|
|
|
|
080071ea <USB_DriveVbus>:
|
|
* 0 : Deactivate VBUS
|
|
* 1 : Activate VBUS
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
|
|
{
|
|
80071ea: b480 push {r7}
|
|
80071ec: b085 sub sp, #20
|
|
80071ee: af00 add r7, sp, #0
|
|
80071f0: 6078 str r0, [r7, #4]
|
|
80071f2: 460b mov r3, r1
|
|
80071f4: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80071f6: 687b ldr r3, [r7, #4]
|
|
80071f8: 60fb str r3, [r7, #12]
|
|
__IO uint32_t hprt0 = 0U;
|
|
80071fa: 2300 movs r3, #0
|
|
80071fc: 60bb str r3, [r7, #8]
|
|
|
|
hprt0 = USBx_HPRT0;
|
|
80071fe: 68fb ldr r3, [r7, #12]
|
|
8007200: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8007204: 681b ldr r3, [r3, #0]
|
|
8007206: 60bb str r3, [r7, #8]
|
|
|
|
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
|
|
8007208: 68bb ldr r3, [r7, #8]
|
|
800720a: f023 032e bic.w r3, r3, #46 @ 0x2e
|
|
800720e: 60bb str r3, [r7, #8]
|
|
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
|
|
|
|
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))
|
|
8007210: 68bb ldr r3, [r7, #8]
|
|
8007212: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8007216: 2b00 cmp r3, #0
|
|
8007218: d109 bne.n 800722e <USB_DriveVbus+0x44>
|
|
800721a: 78fb ldrb r3, [r7, #3]
|
|
800721c: 2b01 cmp r3, #1
|
|
800721e: d106 bne.n 800722e <USB_DriveVbus+0x44>
|
|
{
|
|
USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
|
|
8007220: 68bb ldr r3, [r7, #8]
|
|
8007222: 68fa ldr r2, [r7, #12]
|
|
8007224: f502 6288 add.w r2, r2, #1088 @ 0x440
|
|
8007228: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
800722c: 6013 str r3, [r2, #0]
|
|
}
|
|
if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))
|
|
800722e: 68bb ldr r3, [r7, #8]
|
|
8007230: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8007234: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8007238: d109 bne.n 800724e <USB_DriveVbus+0x64>
|
|
800723a: 78fb ldrb r3, [r7, #3]
|
|
800723c: 2b00 cmp r3, #0
|
|
800723e: d106 bne.n 800724e <USB_DriveVbus+0x64>
|
|
{
|
|
USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
|
|
8007240: 68bb ldr r3, [r7, #8]
|
|
8007242: 68fa ldr r2, [r7, #12]
|
|
8007244: f502 6288 add.w r2, r2, #1088 @ 0x440
|
|
8007248: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
800724c: 6013 str r3, [r2, #0]
|
|
}
|
|
return HAL_OK;
|
|
800724e: 2300 movs r3, #0
|
|
}
|
|
8007250: 4618 mov r0, r3
|
|
8007252: 3714 adds r7, #20
|
|
8007254: 46bd mov sp, r7
|
|
8007256: f85d 7b04 ldr.w r7, [sp], #4
|
|
800725a: 4770 bx lr
|
|
|
|
0800725c <USB_GetHostSpeed>:
|
|
* @arg HCD_DEVICE_SPEED_HIGH: High speed mode
|
|
* @arg HCD_DEVICE_SPEED_FULL: Full speed mode
|
|
* @arg HCD_DEVICE_SPEED_LOW: Low speed mode
|
|
*/
|
|
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
800725c: b480 push {r7}
|
|
800725e: b085 sub sp, #20
|
|
8007260: af00 add r7, sp, #0
|
|
8007262: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007264: 687b ldr r3, [r7, #4]
|
|
8007266: 60fb str r3, [r7, #12]
|
|
__IO uint32_t hprt0 = 0U;
|
|
8007268: 2300 movs r3, #0
|
|
800726a: 60bb str r3, [r7, #8]
|
|
|
|
hprt0 = USBx_HPRT0;
|
|
800726c: 68fb ldr r3, [r7, #12]
|
|
800726e: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8007272: 681b ldr r3, [r3, #0]
|
|
8007274: 60bb str r3, [r7, #8]
|
|
return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
|
|
8007276: 68bb ldr r3, [r7, #8]
|
|
8007278: 0c5b lsrs r3, r3, #17
|
|
800727a: f003 0303 and.w r3, r3, #3
|
|
}
|
|
800727e: 4618 mov r0, r3
|
|
8007280: 3714 adds r7, #20
|
|
8007282: 46bd mov sp, r7
|
|
8007284: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007288: 4770 bx lr
|
|
|
|
0800728a <USB_GetCurrentFrame>:
|
|
* @brief Return Host Current Frame number
|
|
* @param USBx Selected device
|
|
* @retval current frame number
|
|
*/
|
|
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
800728a: b480 push {r7}
|
|
800728c: b085 sub sp, #20
|
|
800728e: af00 add r7, sp, #0
|
|
8007290: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007292: 687b ldr r3, [r7, #4]
|
|
8007294: 60fb str r3, [r7, #12]
|
|
|
|
return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
|
|
8007296: 68fb ldr r3, [r7, #12]
|
|
8007298: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800729c: 689b ldr r3, [r3, #8]
|
|
800729e: b29b uxth r3, r3
|
|
}
|
|
80072a0: 4618 mov r0, r3
|
|
80072a2: 3714 adds r7, #20
|
|
80072a4: 46bd mov sp, r7
|
|
80072a6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80072aa: 4770 bx lr
|
|
|
|
080072ac <USB_HC_Init>:
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
|
|
uint8_t epnum, uint8_t dev_address, uint8_t speed,
|
|
uint8_t ep_type, uint16_t mps)
|
|
{
|
|
80072ac: b580 push {r7, lr}
|
|
80072ae: b088 sub sp, #32
|
|
80072b0: af00 add r7, sp, #0
|
|
80072b2: 6078 str r0, [r7, #4]
|
|
80072b4: 4608 mov r0, r1
|
|
80072b6: 4611 mov r1, r2
|
|
80072b8: 461a mov r2, r3
|
|
80072ba: 4603 mov r3, r0
|
|
80072bc: 70fb strb r3, [r7, #3]
|
|
80072be: 460b mov r3, r1
|
|
80072c0: 70bb strb r3, [r7, #2]
|
|
80072c2: 4613 mov r3, r2
|
|
80072c4: 707b strb r3, [r7, #1]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
80072c6: 2300 movs r3, #0
|
|
80072c8: 77fb strb r3, [r7, #31]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80072ca: 687b ldr r3, [r7, #4]
|
|
80072cc: 613b str r3, [r7, #16]
|
|
uint32_t HCcharEpDir;
|
|
uint32_t HCcharLowSpeed;
|
|
uint32_t HostCoreSpeed;
|
|
|
|
/* Clear old interrupt conditions for this host channel. */
|
|
USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK;
|
|
80072ce: 78fb ldrb r3, [r7, #3]
|
|
80072d0: 015a lsls r2, r3, #5
|
|
80072d2: 693b ldr r3, [r7, #16]
|
|
80072d4: 4413 add r3, r2
|
|
80072d6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80072da: 461a mov r2, r3
|
|
80072dc: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80072e0: 6093 str r3, [r2, #8]
|
|
|
|
/* Enable channel interrupts required for this transfer. */
|
|
switch (ep_type)
|
|
80072e2: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
80072e6: 2b03 cmp r3, #3
|
|
80072e8: d87c bhi.n 80073e4 <USB_HC_Init+0x138>
|
|
80072ea: a201 add r2, pc, #4 @ (adr r2, 80072f0 <USB_HC_Init+0x44>)
|
|
80072ec: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80072f0: 08007301 .word 0x08007301
|
|
80072f4: 080073a7 .word 0x080073a7
|
|
80072f8: 08007301 .word 0x08007301
|
|
80072fc: 08007369 .word 0x08007369
|
|
{
|
|
case EP_TYPE_CTRL:
|
|
case EP_TYPE_BULK:
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
|
|
8007300: 78fb ldrb r3, [r7, #3]
|
|
8007302: 015a lsls r2, r3, #5
|
|
8007304: 693b ldr r3, [r7, #16]
|
|
8007306: 4413 add r3, r2
|
|
8007308: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800730c: 461a mov r2, r3
|
|
800730e: f240 439d movw r3, #1181 @ 0x49d
|
|
8007312: 60d3 str r3, [r2, #12]
|
|
USB_OTG_HCINTMSK_TXERRM |
|
|
USB_OTG_HCINTMSK_DTERRM |
|
|
USB_OTG_HCINTMSK_AHBERR |
|
|
USB_OTG_HCINTMSK_NAKM;
|
|
|
|
if ((epnum & 0x80U) == 0x80U)
|
|
8007314: f997 3002 ldrsb.w r3, [r7, #2]
|
|
8007318: 2b00 cmp r3, #0
|
|
800731a: da10 bge.n 800733e <USB_HC_Init+0x92>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
|
|
800731c: 78fb ldrb r3, [r7, #3]
|
|
800731e: 015a lsls r2, r3, #5
|
|
8007320: 693b ldr r3, [r7, #16]
|
|
8007322: 4413 add r3, r2
|
|
8007324: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007328: 68db ldr r3, [r3, #12]
|
|
800732a: 78fa ldrb r2, [r7, #3]
|
|
800732c: 0151 lsls r1, r2, #5
|
|
800732e: 693a ldr r2, [r7, #16]
|
|
8007330: 440a add r2, r1
|
|
8007332: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007336: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
800733a: 60d3 str r3, [r2, #12]
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
|
|
USB_OTG_HCINTMSK_ACKM;
|
|
}
|
|
#endif /* defined (USB_OTG_HS) */
|
|
}
|
|
break;
|
|
800733c: e055 b.n 80073ea <USB_HC_Init+0x13e>
|
|
if (USBx == USB_OTG_HS)
|
|
800733e: 687b ldr r3, [r7, #4]
|
|
8007340: 4a6f ldr r2, [pc, #444] @ (8007500 <USB_HC_Init+0x254>)
|
|
8007342: 4293 cmp r3, r2
|
|
8007344: d151 bne.n 80073ea <USB_HC_Init+0x13e>
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
|
|
8007346: 78fb ldrb r3, [r7, #3]
|
|
8007348: 015a lsls r2, r3, #5
|
|
800734a: 693b ldr r3, [r7, #16]
|
|
800734c: 4413 add r3, r2
|
|
800734e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007352: 68db ldr r3, [r3, #12]
|
|
8007354: 78fa ldrb r2, [r7, #3]
|
|
8007356: 0151 lsls r1, r2, #5
|
|
8007358: 693a ldr r2, [r7, #16]
|
|
800735a: 440a add r2, r1
|
|
800735c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007360: f043 0360 orr.w r3, r3, #96 @ 0x60
|
|
8007364: 60d3 str r3, [r2, #12]
|
|
break;
|
|
8007366: e040 b.n 80073ea <USB_HC_Init+0x13e>
|
|
|
|
case EP_TYPE_INTR:
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
|
|
8007368: 78fb ldrb r3, [r7, #3]
|
|
800736a: 015a lsls r2, r3, #5
|
|
800736c: 693b ldr r3, [r7, #16]
|
|
800736e: 4413 add r3, r2
|
|
8007370: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007374: 461a mov r2, r3
|
|
8007376: f240 639d movw r3, #1693 @ 0x69d
|
|
800737a: 60d3 str r3, [r2, #12]
|
|
USB_OTG_HCINTMSK_DTERRM |
|
|
USB_OTG_HCINTMSK_NAKM |
|
|
USB_OTG_HCINTMSK_AHBERR |
|
|
USB_OTG_HCINTMSK_FRMORM;
|
|
|
|
if ((epnum & 0x80U) == 0x80U)
|
|
800737c: f997 3002 ldrsb.w r3, [r7, #2]
|
|
8007380: 2b00 cmp r3, #0
|
|
8007382: da34 bge.n 80073ee <USB_HC_Init+0x142>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
|
|
8007384: 78fb ldrb r3, [r7, #3]
|
|
8007386: 015a lsls r2, r3, #5
|
|
8007388: 693b ldr r3, [r7, #16]
|
|
800738a: 4413 add r3, r2
|
|
800738c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007390: 68db ldr r3, [r3, #12]
|
|
8007392: 78fa ldrb r2, [r7, #3]
|
|
8007394: 0151 lsls r1, r2, #5
|
|
8007396: 693a ldr r2, [r7, #16]
|
|
8007398: 440a add r2, r1
|
|
800739a: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800739e: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80073a2: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
break;
|
|
80073a4: e023 b.n 80073ee <USB_HC_Init+0x142>
|
|
|
|
case EP_TYPE_ISOC:
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |
|
|
80073a6: 78fb ldrb r3, [r7, #3]
|
|
80073a8: 015a lsls r2, r3, #5
|
|
80073aa: 693b ldr r3, [r7, #16]
|
|
80073ac: 4413 add r3, r2
|
|
80073ae: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80073b2: 461a mov r2, r3
|
|
80073b4: f240 2325 movw r3, #549 @ 0x225
|
|
80073b8: 60d3 str r3, [r2, #12]
|
|
USB_OTG_HCINTMSK_ACKM |
|
|
USB_OTG_HCINTMSK_AHBERR |
|
|
USB_OTG_HCINTMSK_FRMORM;
|
|
|
|
if ((epnum & 0x80U) == 0x80U)
|
|
80073ba: f997 3002 ldrsb.w r3, [r7, #2]
|
|
80073be: 2b00 cmp r3, #0
|
|
80073c0: da17 bge.n 80073f2 <USB_HC_Init+0x146>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
|
|
80073c2: 78fb ldrb r3, [r7, #3]
|
|
80073c4: 015a lsls r2, r3, #5
|
|
80073c6: 693b ldr r3, [r7, #16]
|
|
80073c8: 4413 add r3, r2
|
|
80073ca: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80073ce: 68db ldr r3, [r3, #12]
|
|
80073d0: 78fa ldrb r2, [r7, #3]
|
|
80073d2: 0151 lsls r1, r2, #5
|
|
80073d4: 693a ldr r2, [r7, #16]
|
|
80073d6: 440a add r2, r1
|
|
80073d8: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80073dc: f443 73c0 orr.w r3, r3, #384 @ 0x180
|
|
80073e0: 60d3 str r3, [r2, #12]
|
|
}
|
|
break;
|
|
80073e2: e006 b.n 80073f2 <USB_HC_Init+0x146>
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
80073e4: 2301 movs r3, #1
|
|
80073e6: 77fb strb r3, [r7, #31]
|
|
break;
|
|
80073e8: e004 b.n 80073f4 <USB_HC_Init+0x148>
|
|
break;
|
|
80073ea: bf00 nop
|
|
80073ec: e002 b.n 80073f4 <USB_HC_Init+0x148>
|
|
break;
|
|
80073ee: bf00 nop
|
|
80073f0: e000 b.n 80073f4 <USB_HC_Init+0x148>
|
|
break;
|
|
80073f2: bf00 nop
|
|
}
|
|
|
|
/* Clear Hub Start Split transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
|
|
80073f4: 78fb ldrb r3, [r7, #3]
|
|
80073f6: 015a lsls r2, r3, #5
|
|
80073f8: 693b ldr r3, [r7, #16]
|
|
80073fa: 4413 add r3, r2
|
|
80073fc: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007400: 461a mov r2, r3
|
|
8007402: 2300 movs r3, #0
|
|
8007404: 6053 str r3, [r2, #4]
|
|
|
|
/* Enable host channel Halt interrupt */
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
|
|
8007406: 78fb ldrb r3, [r7, #3]
|
|
8007408: 015a lsls r2, r3, #5
|
|
800740a: 693b ldr r3, [r7, #16]
|
|
800740c: 4413 add r3, r2
|
|
800740e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007412: 68db ldr r3, [r3, #12]
|
|
8007414: 78fa ldrb r2, [r7, #3]
|
|
8007416: 0151 lsls r1, r2, #5
|
|
8007418: 693a ldr r2, [r7, #16]
|
|
800741a: 440a add r2, r1
|
|
800741c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007420: f043 0302 orr.w r3, r3, #2
|
|
8007424: 60d3 str r3, [r2, #12]
|
|
|
|
/* Enable the top level host channel interrupt. */
|
|
USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
|
|
8007426: 693b ldr r3, [r7, #16]
|
|
8007428: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800742c: 699a ldr r2, [r3, #24]
|
|
800742e: 78fb ldrb r3, [r7, #3]
|
|
8007430: f003 030f and.w r3, r3, #15
|
|
8007434: 2101 movs r1, #1
|
|
8007436: fa01 f303 lsl.w r3, r1, r3
|
|
800743a: 6939 ldr r1, [r7, #16]
|
|
800743c: f501 6180 add.w r1, r1, #1024 @ 0x400
|
|
8007440: 4313 orrs r3, r2
|
|
8007442: 618b str r3, [r1, #24]
|
|
|
|
/* Make sure host channel interrupts are enabled. */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
|
|
8007444: 687b ldr r3, [r7, #4]
|
|
8007446: 699b ldr r3, [r3, #24]
|
|
8007448: f043 7200 orr.w r2, r3, #33554432 @ 0x2000000
|
|
800744c: 687b ldr r3, [r7, #4]
|
|
800744e: 619a str r2, [r3, #24]
|
|
|
|
/* Program the HCCHAR register */
|
|
if ((epnum & 0x80U) == 0x80U)
|
|
8007450: f997 3002 ldrsb.w r3, [r7, #2]
|
|
8007454: 2b00 cmp r3, #0
|
|
8007456: da03 bge.n 8007460 <USB_HC_Init+0x1b4>
|
|
{
|
|
HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;
|
|
8007458: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800745c: 61bb str r3, [r7, #24]
|
|
800745e: e001 b.n 8007464 <USB_HC_Init+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
HCcharEpDir = 0U;
|
|
8007460: 2300 movs r3, #0
|
|
8007462: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
HostCoreSpeed = USB_GetHostSpeed(USBx);
|
|
8007464: 6878 ldr r0, [r7, #4]
|
|
8007466: f7ff fef9 bl 800725c <USB_GetHostSpeed>
|
|
800746a: 60f8 str r0, [r7, #12]
|
|
|
|
/* LS device plugged to HUB */
|
|
if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
|
|
800746c: f897 3028 ldrb.w r3, [r7, #40] @ 0x28
|
|
8007470: 2b02 cmp r3, #2
|
|
8007472: d106 bne.n 8007482 <USB_HC_Init+0x1d6>
|
|
8007474: 68fb ldr r3, [r7, #12]
|
|
8007476: 2b02 cmp r3, #2
|
|
8007478: d003 beq.n 8007482 <USB_HC_Init+0x1d6>
|
|
{
|
|
HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
|
|
800747a: f44f 3300 mov.w r3, #131072 @ 0x20000
|
|
800747e: 617b str r3, [r7, #20]
|
|
8007480: e001 b.n 8007486 <USB_HC_Init+0x1da>
|
|
}
|
|
else
|
|
{
|
|
HCcharLowSpeed = 0U;
|
|
8007482: 2300 movs r3, #0
|
|
8007484: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
|
|
8007486: 787b ldrb r3, [r7, #1]
|
|
8007488: 059b lsls r3, r3, #22
|
|
800748a: f003 52fe and.w r2, r3, #532676608 @ 0x1fc00000
|
|
((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
|
|
800748e: 78bb ldrb r3, [r7, #2]
|
|
8007490: 02db lsls r3, r3, #11
|
|
8007492: f403 43f0 and.w r3, r3, #30720 @ 0x7800
|
|
USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
|
|
8007496: 431a orrs r2, r3
|
|
(((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
|
|
8007498: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
800749c: 049b lsls r3, r3, #18
|
|
800749e: f403 2340 and.w r3, r3, #786432 @ 0xc0000
|
|
((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
|
|
80074a2: 431a orrs r2, r3
|
|
((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) |
|
|
80074a4: 8e3b ldrh r3, [r7, #48] @ 0x30
|
|
80074a6: f3c3 030a ubfx r3, r3, #0, #11
|
|
(((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
|
|
80074aa: 431a orrs r2, r3
|
|
USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed;
|
|
80074ac: 69bb ldr r3, [r7, #24]
|
|
80074ae: 431a orrs r2, r3
|
|
80074b0: 697b ldr r3, [r7, #20]
|
|
80074b2: 4313 orrs r3, r2
|
|
USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
|
|
80074b4: 78fa ldrb r2, [r7, #3]
|
|
80074b6: 0151 lsls r1, r2, #5
|
|
80074b8: 693a ldr r2, [r7, #16]
|
|
80074ba: 440a add r2, r1
|
|
80074bc: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed;
|
|
80074c0: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
|
|
80074c4: 6013 str r3, [r2, #0]
|
|
|
|
if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
|
|
80074c6: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
80074ca: 2b03 cmp r3, #3
|
|
80074cc: d003 beq.n 80074d6 <USB_HC_Init+0x22a>
|
|
80074ce: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
80074d2: 2b01 cmp r3, #1
|
|
80074d4: d10f bne.n 80074f6 <USB_HC_Init+0x24a>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
|
|
80074d6: 78fb ldrb r3, [r7, #3]
|
|
80074d8: 015a lsls r2, r3, #5
|
|
80074da: 693b ldr r3, [r7, #16]
|
|
80074dc: 4413 add r3, r2
|
|
80074de: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80074e2: 681b ldr r3, [r3, #0]
|
|
80074e4: 78fa ldrb r2, [r7, #3]
|
|
80074e6: 0151 lsls r1, r2, #5
|
|
80074e8: 693a ldr r2, [r7, #16]
|
|
80074ea: 440a add r2, r1
|
|
80074ec: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80074f0: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
80074f4: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
return ret;
|
|
80074f6: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
80074f8: 4618 mov r0, r3
|
|
80074fa: 3720 adds r7, #32
|
|
80074fc: 46bd mov sp, r7
|
|
80074fe: bd80 pop {r7, pc}
|
|
8007500: 40040000 .word 0x40040000
|
|
|
|
08007504 <USB_HC_StartXfer>:
|
|
* 0 : DMA feature not used
|
|
* 1 : DMA feature used
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
|
|
{
|
|
8007504: b580 push {r7, lr}
|
|
8007506: b08c sub sp, #48 @ 0x30
|
|
8007508: af02 add r7, sp, #8
|
|
800750a: 60f8 str r0, [r7, #12]
|
|
800750c: 60b9 str r1, [r7, #8]
|
|
800750e: 4613 mov r3, r2
|
|
8007510: 71fb strb r3, [r7, #7]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007512: 68fb ldr r3, [r7, #12]
|
|
8007514: 623b str r3, [r7, #32]
|
|
uint32_t ch_num = (uint32_t)hc->ch_num;
|
|
8007516: 68bb ldr r3, [r7, #8]
|
|
8007518: 785b ldrb r3, [r3, #1]
|
|
800751a: 61fb str r3, [r7, #28]
|
|
__IO uint32_t tmpreg;
|
|
uint8_t is_oddframe;
|
|
uint16_t len_words;
|
|
uint16_t num_packets;
|
|
uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT;
|
|
800751c: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8007520: 837b strh r3, [r7, #26]
|
|
|
|
#if defined (USB_OTG_HS)
|
|
if (USBx == USB_OTG_HS)
|
|
8007522: 68fb ldr r3, [r7, #12]
|
|
8007524: 4a5d ldr r2, [pc, #372] @ (800769c <USB_HC_StartXfer+0x198>)
|
|
8007526: 4293 cmp r3, r2
|
|
8007528: d12f bne.n 800758a <USB_HC_StartXfer+0x86>
|
|
{
|
|
/* in DMA mode host Core automatically issues ping in case of NYET/NAK */
|
|
if (dma == 1U)
|
|
800752a: 79fb ldrb r3, [r7, #7]
|
|
800752c: 2b01 cmp r3, #1
|
|
800752e: d11c bne.n 800756a <USB_HC_StartXfer+0x66>
|
|
{
|
|
if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U))
|
|
8007530: 68bb ldr r3, [r7, #8]
|
|
8007532: 7c9b ldrb r3, [r3, #18]
|
|
8007534: 2b00 cmp r3, #0
|
|
8007536: d003 beq.n 8007540 <USB_HC_StartXfer+0x3c>
|
|
8007538: 68bb ldr r3, [r7, #8]
|
|
800753a: 7c9b ldrb r3, [r3, #18]
|
|
800753c: 2b02 cmp r3, #2
|
|
800753e: d124 bne.n 800758a <USB_HC_StartXfer+0x86>
|
|
8007540: 68bb ldr r3, [r7, #8]
|
|
8007542: 799b ldrb r3, [r3, #6]
|
|
8007544: 2b00 cmp r3, #0
|
|
8007546: d120 bne.n 800758a <USB_HC_StartXfer+0x86>
|
|
{
|
|
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
|
|
8007548: 69fb ldr r3, [r7, #28]
|
|
800754a: 015a lsls r2, r3, #5
|
|
800754c: 6a3b ldr r3, [r7, #32]
|
|
800754e: 4413 add r3, r2
|
|
8007550: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007554: 68db ldr r3, [r3, #12]
|
|
8007556: 69fa ldr r2, [r7, #28]
|
|
8007558: 0151 lsls r1, r2, #5
|
|
800755a: 6a3a ldr r2, [r7, #32]
|
|
800755c: 440a add r2, r1
|
|
800755e: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007562: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8007566: 60d3 str r3, [r2, #12]
|
|
8007568: e00f b.n 800758a <USB_HC_StartXfer+0x86>
|
|
USB_OTG_HCINTMSK_NAKM);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U))
|
|
800756a: 68bb ldr r3, [r7, #8]
|
|
800756c: 791b ldrb r3, [r3, #4]
|
|
800756e: 2b00 cmp r3, #0
|
|
8007570: d10b bne.n 800758a <USB_HC_StartXfer+0x86>
|
|
8007572: 68bb ldr r3, [r7, #8]
|
|
8007574: 795b ldrb r3, [r3, #5]
|
|
8007576: 2b01 cmp r3, #1
|
|
8007578: d107 bne.n 800758a <USB_HC_StartXfer+0x86>
|
|
{
|
|
(void)USB_DoPing(USBx, hc->ch_num);
|
|
800757a: 68bb ldr r3, [r7, #8]
|
|
800757c: 785b ldrb r3, [r3, #1]
|
|
800757e: 4619 mov r1, r3
|
|
8007580: 68f8 ldr r0, [r7, #12]
|
|
8007582: f000 fb6b bl 8007c5c <USB_DoPing>
|
|
return HAL_OK;
|
|
8007586: 2300 movs r3, #0
|
|
8007588: e232 b.n 80079f0 <USB_HC_StartXfer+0x4ec>
|
|
}
|
|
}
|
|
}
|
|
#endif /* defined (USB_OTG_HS) */
|
|
|
|
if (hc->do_ssplit == 1U)
|
|
800758a: 68bb ldr r3, [r7, #8]
|
|
800758c: 799b ldrb r3, [r3, #6]
|
|
800758e: 2b01 cmp r3, #1
|
|
8007590: d158 bne.n 8007644 <USB_HC_StartXfer+0x140>
|
|
{
|
|
/* Set number of packet to 1 for Split transaction */
|
|
num_packets = 1U;
|
|
8007592: 2301 movs r3, #1
|
|
8007594: 84fb strh r3, [r7, #38] @ 0x26
|
|
|
|
if (hc->ep_is_in != 0U)
|
|
8007596: 68bb ldr r3, [r7, #8]
|
|
8007598: 78db ldrb r3, [r3, #3]
|
|
800759a: 2b00 cmp r3, #0
|
|
800759c: d007 beq.n 80075ae <USB_HC_StartXfer+0xaa>
|
|
{
|
|
hc->XferSize = (uint32_t)num_packets * hc->max_packet;
|
|
800759e: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
80075a0: 68ba ldr r2, [r7, #8]
|
|
80075a2: 8a92 ldrh r2, [r2, #20]
|
|
80075a4: fb03 f202 mul.w r2, r3, r2
|
|
80075a8: 68bb ldr r3, [r7, #8]
|
|
80075aa: 61da str r2, [r3, #28]
|
|
80075ac: e07c b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
else
|
|
{
|
|
if (hc->ep_type == EP_TYPE_ISOC)
|
|
80075ae: 68bb ldr r3, [r7, #8]
|
|
80075b0: 7c9b ldrb r3, [r3, #18]
|
|
80075b2: 2b01 cmp r3, #1
|
|
80075b4: d130 bne.n 8007618 <USB_HC_StartXfer+0x114>
|
|
{
|
|
if (hc->xfer_len > ISO_SPLT_MPS)
|
|
80075b6: 68bb ldr r3, [r7, #8]
|
|
80075b8: 6a1b ldr r3, [r3, #32]
|
|
80075ba: 2bbc cmp r3, #188 @ 0xbc
|
|
80075bc: d918 bls.n 80075f0 <USB_HC_StartXfer+0xec>
|
|
{
|
|
/* Isochrone Max Packet Size for Split mode */
|
|
hc->XferSize = hc->max_packet;
|
|
80075be: 68bb ldr r3, [r7, #8]
|
|
80075c0: 8a9b ldrh r3, [r3, #20]
|
|
80075c2: 461a mov r2, r3
|
|
80075c4: 68bb ldr r3, [r7, #8]
|
|
80075c6: 61da str r2, [r3, #28]
|
|
hc->xfer_len = hc->XferSize;
|
|
80075c8: 68bb ldr r3, [r7, #8]
|
|
80075ca: 69da ldr r2, [r3, #28]
|
|
80075cc: 68bb ldr r3, [r7, #8]
|
|
80075ce: 621a str r2, [r3, #32]
|
|
|
|
if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE))
|
|
80075d0: 68bb ldr r3, [r7, #8]
|
|
80075d2: 68db ldr r3, [r3, #12]
|
|
80075d4: 2b01 cmp r3, #1
|
|
80075d6: d003 beq.n 80075e0 <USB_HC_StartXfer+0xdc>
|
|
80075d8: 68bb ldr r3, [r7, #8]
|
|
80075da: 68db ldr r3, [r3, #12]
|
|
80075dc: 2b02 cmp r3, #2
|
|
80075de: d103 bne.n 80075e8 <USB_HC_StartXfer+0xe4>
|
|
{
|
|
hc->iso_splt_xactPos = HCSPLT_MIDDLE;
|
|
80075e0: 68bb ldr r3, [r7, #8]
|
|
80075e2: 2202 movs r2, #2
|
|
80075e4: 60da str r2, [r3, #12]
|
|
80075e6: e05f b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
else
|
|
{
|
|
hc->iso_splt_xactPos = HCSPLT_BEGIN;
|
|
80075e8: 68bb ldr r3, [r7, #8]
|
|
80075ea: 2201 movs r2, #1
|
|
80075ec: 60da str r2, [r3, #12]
|
|
80075ee: e05b b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
hc->XferSize = hc->xfer_len;
|
|
80075f0: 68bb ldr r3, [r7, #8]
|
|
80075f2: 6a1a ldr r2, [r3, #32]
|
|
80075f4: 68bb ldr r3, [r7, #8]
|
|
80075f6: 61da str r2, [r3, #28]
|
|
|
|
if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE))
|
|
80075f8: 68bb ldr r3, [r7, #8]
|
|
80075fa: 68db ldr r3, [r3, #12]
|
|
80075fc: 2b01 cmp r3, #1
|
|
80075fe: d007 beq.n 8007610 <USB_HC_StartXfer+0x10c>
|
|
8007600: 68bb ldr r3, [r7, #8]
|
|
8007602: 68db ldr r3, [r3, #12]
|
|
8007604: 2b02 cmp r3, #2
|
|
8007606: d003 beq.n 8007610 <USB_HC_StartXfer+0x10c>
|
|
{
|
|
hc->iso_splt_xactPos = HCSPLT_FULL;
|
|
8007608: 68bb ldr r3, [r7, #8]
|
|
800760a: 2204 movs r2, #4
|
|
800760c: 60da str r2, [r3, #12]
|
|
800760e: e04b b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
else
|
|
{
|
|
hc->iso_splt_xactPos = HCSPLT_END;
|
|
8007610: 68bb ldr r3, [r7, #8]
|
|
8007612: 2203 movs r2, #3
|
|
8007614: 60da str r2, [r3, #12]
|
|
8007616: e047 b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((dma == 1U) && (hc->xfer_len > hc->max_packet))
|
|
8007618: 79fb ldrb r3, [r7, #7]
|
|
800761a: 2b01 cmp r3, #1
|
|
800761c: d10d bne.n 800763a <USB_HC_StartXfer+0x136>
|
|
800761e: 68bb ldr r3, [r7, #8]
|
|
8007620: 6a1b ldr r3, [r3, #32]
|
|
8007622: 68ba ldr r2, [r7, #8]
|
|
8007624: 8a92 ldrh r2, [r2, #20]
|
|
8007626: 4293 cmp r3, r2
|
|
8007628: d907 bls.n 800763a <USB_HC_StartXfer+0x136>
|
|
{
|
|
hc->XferSize = (uint32_t)num_packets * hc->max_packet;
|
|
800762a: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
800762c: 68ba ldr r2, [r7, #8]
|
|
800762e: 8a92 ldrh r2, [r2, #20]
|
|
8007630: fb03 f202 mul.w r2, r3, r2
|
|
8007634: 68bb ldr r3, [r7, #8]
|
|
8007636: 61da str r2, [r3, #28]
|
|
8007638: e036 b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
else
|
|
{
|
|
hc->XferSize = hc->xfer_len;
|
|
800763a: 68bb ldr r3, [r7, #8]
|
|
800763c: 6a1a ldr r2, [r3, #32]
|
|
800763e: 68bb ldr r3, [r7, #8]
|
|
8007640: 61da str r2, [r3, #28]
|
|
8007642: e031 b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Compute the expected number of packets associated to the transfer */
|
|
if (hc->xfer_len > 0U)
|
|
8007644: 68bb ldr r3, [r7, #8]
|
|
8007646: 6a1b ldr r3, [r3, #32]
|
|
8007648: 2b00 cmp r3, #0
|
|
800764a: d018 beq.n 800767e <USB_HC_StartXfer+0x17a>
|
|
{
|
|
num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
|
|
800764c: 68bb ldr r3, [r7, #8]
|
|
800764e: 6a1b ldr r3, [r3, #32]
|
|
8007650: 68ba ldr r2, [r7, #8]
|
|
8007652: 8a92 ldrh r2, [r2, #20]
|
|
8007654: 4413 add r3, r2
|
|
8007656: 3b01 subs r3, #1
|
|
8007658: 68ba ldr r2, [r7, #8]
|
|
800765a: 8a92 ldrh r2, [r2, #20]
|
|
800765c: fbb3 f3f2 udiv r3, r3, r2
|
|
8007660: 84fb strh r3, [r7, #38] @ 0x26
|
|
|
|
if (num_packets > max_hc_pkt_count)
|
|
8007662: 8cfa ldrh r2, [r7, #38] @ 0x26
|
|
8007664: 8b7b ldrh r3, [r7, #26]
|
|
8007666: 429a cmp r2, r3
|
|
8007668: d90b bls.n 8007682 <USB_HC_StartXfer+0x17e>
|
|
{
|
|
num_packets = max_hc_pkt_count;
|
|
800766a: 8b7b ldrh r3, [r7, #26]
|
|
800766c: 84fb strh r3, [r7, #38] @ 0x26
|
|
hc->XferSize = (uint32_t)num_packets * hc->max_packet;
|
|
800766e: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
8007670: 68ba ldr r2, [r7, #8]
|
|
8007672: 8a92 ldrh r2, [r2, #20]
|
|
8007674: fb03 f202 mul.w r2, r3, r2
|
|
8007678: 68bb ldr r3, [r7, #8]
|
|
800767a: 61da str r2, [r3, #28]
|
|
800767c: e001 b.n 8007682 <USB_HC_StartXfer+0x17e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
num_packets = 1U;
|
|
800767e: 2301 movs r3, #1
|
|
8007680: 84fb strh r3, [r7, #38] @ 0x26
|
|
|
|
/*
|
|
* For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
|
|
* max_packet size.
|
|
*/
|
|
if (hc->ep_is_in != 0U)
|
|
8007682: 68bb ldr r3, [r7, #8]
|
|
8007684: 78db ldrb r3, [r3, #3]
|
|
8007686: 2b00 cmp r3, #0
|
|
8007688: d00a beq.n 80076a0 <USB_HC_StartXfer+0x19c>
|
|
{
|
|
hc->XferSize = (uint32_t)num_packets * hc->max_packet;
|
|
800768a: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
800768c: 68ba ldr r2, [r7, #8]
|
|
800768e: 8a92 ldrh r2, [r2, #20]
|
|
8007690: fb03 f202 mul.w r2, r3, r2
|
|
8007694: 68bb ldr r3, [r7, #8]
|
|
8007696: 61da str r2, [r3, #28]
|
|
8007698: e006 b.n 80076a8 <USB_HC_StartXfer+0x1a4>
|
|
800769a: bf00 nop
|
|
800769c: 40040000 .word 0x40040000
|
|
}
|
|
else
|
|
{
|
|
hc->XferSize = hc->xfer_len;
|
|
80076a0: 68bb ldr r3, [r7, #8]
|
|
80076a2: 6a1a ldr r2, [r3, #32]
|
|
80076a4: 68bb ldr r3, [r7, #8]
|
|
80076a6: 61da str r2, [r3, #28]
|
|
}
|
|
}
|
|
|
|
/* Initialize the HCTSIZn register */
|
|
USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
|
|
80076a8: 68bb ldr r3, [r7, #8]
|
|
80076aa: 69db ldr r3, [r3, #28]
|
|
80076ac: f3c3 0212 ubfx r2, r3, #0, #19
|
|
(((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
|
|
80076b0: 8cfb ldrh r3, [r7, #38] @ 0x26
|
|
80076b2: 04d9 lsls r1, r3, #19
|
|
80076b4: 4ba3 ldr r3, [pc, #652] @ (8007944 <USB_HC_StartXfer+0x440>)
|
|
80076b6: 400b ands r3, r1
|
|
USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
|
|
80076b8: 431a orrs r2, r3
|
|
(((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
|
|
80076ba: 68bb ldr r3, [r7, #8]
|
|
80076bc: 7d9b ldrb r3, [r3, #22]
|
|
80076be: 075b lsls r3, r3, #29
|
|
80076c0: f003 43c0 and.w r3, r3, #1610612736 @ 0x60000000
|
|
USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
|
|
80076c4: 69f9 ldr r1, [r7, #28]
|
|
80076c6: 0148 lsls r0, r1, #5
|
|
80076c8: 6a39 ldr r1, [r7, #32]
|
|
80076ca: 4401 add r1, r0
|
|
80076cc: f501 61a0 add.w r1, r1, #1280 @ 0x500
|
|
(((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
|
|
80076d0: 4313 orrs r3, r2
|
|
USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
|
|
80076d2: 610b str r3, [r1, #16]
|
|
|
|
if (dma != 0U)
|
|
80076d4: 79fb ldrb r3, [r7, #7]
|
|
80076d6: 2b00 cmp r3, #0
|
|
80076d8: d009 beq.n 80076ee <USB_HC_StartXfer+0x1ea>
|
|
{
|
|
/* xfer_buff MUST be 32-bits aligned */
|
|
USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
|
|
80076da: 68bb ldr r3, [r7, #8]
|
|
80076dc: 6999 ldr r1, [r3, #24]
|
|
80076de: 69fb ldr r3, [r7, #28]
|
|
80076e0: 015a lsls r2, r3, #5
|
|
80076e2: 6a3b ldr r3, [r7, #32]
|
|
80076e4: 4413 add r3, r2
|
|
80076e6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80076ea: 460a mov r2, r1
|
|
80076ec: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;
|
|
80076ee: 6a3b ldr r3, [r7, #32]
|
|
80076f0: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80076f4: 689b ldr r3, [r3, #8]
|
|
80076f6: f003 0301 and.w r3, r3, #1
|
|
80076fa: 2b00 cmp r3, #0
|
|
80076fc: bf0c ite eq
|
|
80076fe: 2301 moveq r3, #1
|
|
8007700: 2300 movne r3, #0
|
|
8007702: b2db uxtb r3, r3
|
|
8007704: 767b strb r3, [r7, #25]
|
|
USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
|
|
8007706: 69fb ldr r3, [r7, #28]
|
|
8007708: 015a lsls r2, r3, #5
|
|
800770a: 6a3b ldr r3, [r7, #32]
|
|
800770c: 4413 add r3, r2
|
|
800770e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007712: 681b ldr r3, [r3, #0]
|
|
8007714: 69fa ldr r2, [r7, #28]
|
|
8007716: 0151 lsls r1, r2, #5
|
|
8007718: 6a3a ldr r2, [r7, #32]
|
|
800771a: 440a add r2, r1
|
|
800771c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007720: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
|
|
8007724: 6013 str r3, [r2, #0]
|
|
USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
|
|
8007726: 69fb ldr r3, [r7, #28]
|
|
8007728: 015a lsls r2, r3, #5
|
|
800772a: 6a3b ldr r3, [r7, #32]
|
|
800772c: 4413 add r3, r2
|
|
800772e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007732: 681a ldr r2, [r3, #0]
|
|
8007734: 7e7b ldrb r3, [r7, #25]
|
|
8007736: 075b lsls r3, r3, #29
|
|
8007738: 69f9 ldr r1, [r7, #28]
|
|
800773a: 0148 lsls r0, r1, #5
|
|
800773c: 6a39 ldr r1, [r7, #32]
|
|
800773e: 4401 add r1, r0
|
|
8007740: f501 61a0 add.w r1, r1, #1280 @ 0x500
|
|
8007744: 4313 orrs r3, r2
|
|
8007746: 600b str r3, [r1, #0]
|
|
|
|
if (hc->do_ssplit == 1U)
|
|
8007748: 68bb ldr r3, [r7, #8]
|
|
800774a: 799b ldrb r3, [r3, #6]
|
|
800774c: 2b01 cmp r3, #1
|
|
800774e: f040 80c3 bne.w 80078d8 <USB_HC_StartXfer+0x3d4>
|
|
{
|
|
/* Set Hub start Split transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
|
|
8007752: 68bb ldr r3, [r7, #8]
|
|
8007754: 7c5b ldrb r3, [r3, #17]
|
|
8007756: 01db lsls r3, r3, #7
|
|
(uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN;
|
|
8007758: 68ba ldr r2, [r7, #8]
|
|
800775a: 7c12 ldrb r2, [r2, #16]
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
|
|
800775c: 4313 orrs r3, r2
|
|
800775e: 69fa ldr r2, [r7, #28]
|
|
8007760: 0151 lsls r1, r2, #5
|
|
8007762: 6a3a ldr r2, [r7, #32]
|
|
8007764: 440a add r2, r1
|
|
8007766: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
(uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN;
|
|
800776a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
|
|
800776e: 6053 str r3, [r2, #4]
|
|
|
|
/* unmask ack & nyet for IN/OUT transactions */
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM |
|
|
8007770: 69fb ldr r3, [r7, #28]
|
|
8007772: 015a lsls r2, r3, #5
|
|
8007774: 6a3b ldr r3, [r7, #32]
|
|
8007776: 4413 add r3, r2
|
|
8007778: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800777c: 68db ldr r3, [r3, #12]
|
|
800777e: 69fa ldr r2, [r7, #28]
|
|
8007780: 0151 lsls r1, r2, #5
|
|
8007782: 6a3a ldr r2, [r7, #32]
|
|
8007784: 440a add r2, r1
|
|
8007786: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800778a: f043 0360 orr.w r3, r3, #96 @ 0x60
|
|
800778e: 60d3 str r3, [r2, #12]
|
|
USB_OTG_HCINTMSK_NYET);
|
|
|
|
if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U))
|
|
8007790: 68bb ldr r3, [r7, #8]
|
|
8007792: 79db ldrb r3, [r3, #7]
|
|
8007794: 2b01 cmp r3, #1
|
|
8007796: d123 bne.n 80077e0 <USB_HC_StartXfer+0x2dc>
|
|
8007798: 68bb ldr r3, [r7, #8]
|
|
800779a: 78db ldrb r3, [r3, #3]
|
|
800779c: 2b00 cmp r3, #0
|
|
800779e: d11f bne.n 80077e0 <USB_HC_StartXfer+0x2dc>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
|
|
80077a0: 69fb ldr r3, [r7, #28]
|
|
80077a2: 015a lsls r2, r3, #5
|
|
80077a4: 6a3b ldr r3, [r7, #32]
|
|
80077a6: 4413 add r3, r2
|
|
80077a8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80077ac: 685b ldr r3, [r3, #4]
|
|
80077ae: 69fa ldr r2, [r7, #28]
|
|
80077b0: 0151 lsls r1, r2, #5
|
|
80077b2: 6a3a ldr r2, [r7, #32]
|
|
80077b4: 440a add r2, r1
|
|
80077b6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80077ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80077be: 6053 str r3, [r2, #4]
|
|
USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
|
|
80077c0: 69fb ldr r3, [r7, #28]
|
|
80077c2: 015a lsls r2, r3, #5
|
|
80077c4: 6a3b ldr r3, [r7, #32]
|
|
80077c6: 4413 add r3, r2
|
|
80077c8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80077cc: 68db ldr r3, [r3, #12]
|
|
80077ce: 69fa ldr r2, [r7, #28]
|
|
80077d0: 0151 lsls r1, r2, #5
|
|
80077d2: 6a3a ldr r2, [r7, #32]
|
|
80077d4: 440a add r2, r1
|
|
80077d6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80077da: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
80077de: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) &&
|
|
80077e0: 68bb ldr r3, [r7, #8]
|
|
80077e2: 7c9b ldrb r3, [r3, #18]
|
|
80077e4: 2b01 cmp r3, #1
|
|
80077e6: d003 beq.n 80077f0 <USB_HC_StartXfer+0x2ec>
|
|
80077e8: 68bb ldr r3, [r7, #8]
|
|
80077ea: 7c9b ldrb r3, [r3, #18]
|
|
80077ec: 2b03 cmp r3, #3
|
|
80077ee: d117 bne.n 8007820 <USB_HC_StartXfer+0x31c>
|
|
(hc->do_csplit == 1U) && (hc->ep_is_in == 1U))
|
|
80077f0: 68bb ldr r3, [r7, #8]
|
|
80077f2: 79db ldrb r3, [r3, #7]
|
|
if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) &&
|
|
80077f4: 2b01 cmp r3, #1
|
|
80077f6: d113 bne.n 8007820 <USB_HC_StartXfer+0x31c>
|
|
(hc->do_csplit == 1U) && (hc->ep_is_in == 1U))
|
|
80077f8: 68bb ldr r3, [r7, #8]
|
|
80077fa: 78db ldrb r3, [r3, #3]
|
|
80077fc: 2b01 cmp r3, #1
|
|
80077fe: d10f bne.n 8007820 <USB_HC_StartXfer+0x31c>
|
|
{
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
|
|
8007800: 69fb ldr r3, [r7, #28]
|
|
8007802: 015a lsls r2, r3, #5
|
|
8007804: 6a3b ldr r3, [r7, #32]
|
|
8007806: 4413 add r3, r2
|
|
8007808: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800780c: 685b ldr r3, [r3, #4]
|
|
800780e: 69fa ldr r2, [r7, #28]
|
|
8007810: 0151 lsls r1, r2, #5
|
|
8007812: 6a3a ldr r2, [r7, #32]
|
|
8007814: 440a add r2, r1
|
|
8007816: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800781a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800781e: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
/* Position management for iso out transaction on split mode */
|
|
if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U))
|
|
8007820: 68bb ldr r3, [r7, #8]
|
|
8007822: 7c9b ldrb r3, [r3, #18]
|
|
8007824: 2b01 cmp r3, #1
|
|
8007826: d162 bne.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
8007828: 68bb ldr r3, [r7, #8]
|
|
800782a: 78db ldrb r3, [r3, #3]
|
|
800782c: 2b00 cmp r3, #0
|
|
800782e: d15e bne.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
{
|
|
/* Set data payload position */
|
|
switch (hc->iso_splt_xactPos)
|
|
8007830: 68bb ldr r3, [r7, #8]
|
|
8007832: 68db ldr r3, [r3, #12]
|
|
8007834: 3b01 subs r3, #1
|
|
8007836: 2b03 cmp r3, #3
|
|
8007838: d858 bhi.n 80078ec <USB_HC_StartXfer+0x3e8>
|
|
800783a: a201 add r2, pc, #4 @ (adr r2, 8007840 <USB_HC_StartXfer+0x33c>)
|
|
800783c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007840: 08007851 .word 0x08007851
|
|
8007844: 08007873 .word 0x08007873
|
|
8007848: 08007895 .word 0x08007895
|
|
800784c: 080078b7 .word 0x080078b7
|
|
{
|
|
case HCSPLT_BEGIN:
|
|
/* First data payload for OUT Transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1;
|
|
8007850: 69fb ldr r3, [r7, #28]
|
|
8007852: 015a lsls r2, r3, #5
|
|
8007854: 6a3b ldr r3, [r7, #32]
|
|
8007856: 4413 add r3, r2
|
|
8007858: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800785c: 685b ldr r3, [r3, #4]
|
|
800785e: 69fa ldr r2, [r7, #28]
|
|
8007860: 0151 lsls r1, r2, #5
|
|
8007862: 6a3a ldr r2, [r7, #32]
|
|
8007864: 440a add r2, r1
|
|
8007866: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800786a: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
800786e: 6053 str r3, [r2, #4]
|
|
break;
|
|
8007870: e03d b.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
|
|
case HCSPLT_MIDDLE:
|
|
/* Middle data payload for OUT Transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos;
|
|
8007872: 69fb ldr r3, [r7, #28]
|
|
8007874: 015a lsls r2, r3, #5
|
|
8007876: 6a3b ldr r3, [r7, #32]
|
|
8007878: 4413 add r3, r2
|
|
800787a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800787e: 685b ldr r3, [r3, #4]
|
|
8007880: 69fa ldr r2, [r7, #28]
|
|
8007882: 0151 lsls r1, r2, #5
|
|
8007884: 6a3a ldr r2, [r7, #32]
|
|
8007886: 440a add r2, r1
|
|
8007888: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800788c: f043 030e orr.w r3, r3, #14
|
|
8007890: 6053 str r3, [r2, #4]
|
|
break;
|
|
8007892: e02c b.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
|
|
case HCSPLT_END:
|
|
/* End data payload for OUT Transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0;
|
|
8007894: 69fb ldr r3, [r7, #28]
|
|
8007896: 015a lsls r2, r3, #5
|
|
8007898: 6a3b ldr r3, [r7, #32]
|
|
800789a: 4413 add r3, r2
|
|
800789c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80078a0: 685b ldr r3, [r3, #4]
|
|
80078a2: 69fa ldr r2, [r7, #28]
|
|
80078a4: 0151 lsls r1, r2, #5
|
|
80078a6: 6a3a ldr r2, [r7, #32]
|
|
80078a8: 440a add r2, r1
|
|
80078aa: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80078ae: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80078b2: 6053 str r3, [r2, #4]
|
|
break;
|
|
80078b4: e01b b.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
|
|
case HCSPLT_FULL:
|
|
/* Entire data payload for OUT Transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS;
|
|
80078b6: 69fb ldr r3, [r7, #28]
|
|
80078b8: 015a lsls r2, r3, #5
|
|
80078ba: 6a3b ldr r3, [r7, #32]
|
|
80078bc: 4413 add r3, r2
|
|
80078be: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80078c2: 685b ldr r3, [r3, #4]
|
|
80078c4: 69fa ldr r2, [r7, #28]
|
|
80078c6: 0151 lsls r1, r2, #5
|
|
80078c8: 6a3a ldr r2, [r7, #32]
|
|
80078ca: 440a add r2, r1
|
|
80078cc: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80078d0: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
80078d4: 6053 str r3, [r2, #4]
|
|
break;
|
|
80078d6: e00a b.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Clear Hub Start Split transaction */
|
|
USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
|
|
80078d8: 69fb ldr r3, [r7, #28]
|
|
80078da: 015a lsls r2, r3, #5
|
|
80078dc: 6a3b ldr r3, [r7, #32]
|
|
80078de: 4413 add r3, r2
|
|
80078e0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80078e4: 461a mov r2, r3
|
|
80078e6: 2300 movs r3, #0
|
|
80078e8: 6053 str r3, [r2, #4]
|
|
80078ea: e000 b.n 80078ee <USB_HC_StartXfer+0x3ea>
|
|
break;
|
|
80078ec: bf00 nop
|
|
}
|
|
|
|
/* Set host channel enable */
|
|
tmpreg = USBx_HC(ch_num)->HCCHAR;
|
|
80078ee: 69fb ldr r3, [r7, #28]
|
|
80078f0: 015a lsls r2, r3, #5
|
|
80078f2: 6a3b ldr r3, [r7, #32]
|
|
80078f4: 4413 add r3, r2
|
|
80078f6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80078fa: 681b ldr r3, [r3, #0]
|
|
80078fc: 613b str r3, [r7, #16]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
80078fe: 693b ldr r3, [r7, #16]
|
|
8007900: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8007904: 613b str r3, [r7, #16]
|
|
|
|
/* make sure to set the correct ep direction */
|
|
if (hc->ep_is_in != 0U)
|
|
8007906: 68bb ldr r3, [r7, #8]
|
|
8007908: 78db ldrb r3, [r3, #3]
|
|
800790a: 2b00 cmp r3, #0
|
|
800790c: d004 beq.n 8007918 <USB_HC_StartXfer+0x414>
|
|
{
|
|
tmpreg |= USB_OTG_HCCHAR_EPDIR;
|
|
800790e: 693b ldr r3, [r7, #16]
|
|
8007910: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8007914: 613b str r3, [r7, #16]
|
|
8007916: e003 b.n 8007920 <USB_HC_StartXfer+0x41c>
|
|
}
|
|
else
|
|
{
|
|
tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
|
|
8007918: 693b ldr r3, [r7, #16]
|
|
800791a: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
800791e: 613b str r3, [r7, #16]
|
|
}
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8007920: 693b ldr r3, [r7, #16]
|
|
8007922: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007926: 613b str r3, [r7, #16]
|
|
USBx_HC(ch_num)->HCCHAR = tmpreg;
|
|
8007928: 69fb ldr r3, [r7, #28]
|
|
800792a: 015a lsls r2, r3, #5
|
|
800792c: 6a3b ldr r3, [r7, #32]
|
|
800792e: 4413 add r3, r2
|
|
8007930: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007934: 461a mov r2, r3
|
|
8007936: 693b ldr r3, [r7, #16]
|
|
8007938: 6013 str r3, [r2, #0]
|
|
|
|
if (dma != 0U) /* dma mode */
|
|
800793a: 79fb ldrb r3, [r7, #7]
|
|
800793c: 2b00 cmp r3, #0
|
|
800793e: d003 beq.n 8007948 <USB_HC_StartXfer+0x444>
|
|
{
|
|
return HAL_OK;
|
|
8007940: 2300 movs r3, #0
|
|
8007942: e055 b.n 80079f0 <USB_HC_StartXfer+0x4ec>
|
|
8007944: 1ff80000 .word 0x1ff80000
|
|
}
|
|
|
|
if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U))
|
|
8007948: 68bb ldr r3, [r7, #8]
|
|
800794a: 78db ldrb r3, [r3, #3]
|
|
800794c: 2b00 cmp r3, #0
|
|
800794e: d14e bne.n 80079ee <USB_HC_StartXfer+0x4ea>
|
|
8007950: 68bb ldr r3, [r7, #8]
|
|
8007952: 6a1b ldr r3, [r3, #32]
|
|
8007954: 2b00 cmp r3, #0
|
|
8007956: d04a beq.n 80079ee <USB_HC_StartXfer+0x4ea>
|
|
8007958: 68bb ldr r3, [r7, #8]
|
|
800795a: 79db ldrb r3, [r3, #7]
|
|
800795c: 2b00 cmp r3, #0
|
|
800795e: d146 bne.n 80079ee <USB_HC_StartXfer+0x4ea>
|
|
{
|
|
switch (hc->ep_type)
|
|
8007960: 68bb ldr r3, [r7, #8]
|
|
8007962: 7c9b ldrb r3, [r3, #18]
|
|
8007964: 2b03 cmp r3, #3
|
|
8007966: d831 bhi.n 80079cc <USB_HC_StartXfer+0x4c8>
|
|
8007968: a201 add r2, pc, #4 @ (adr r2, 8007970 <USB_HC_StartXfer+0x46c>)
|
|
800796a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800796e: bf00 nop
|
|
8007970: 08007981 .word 0x08007981
|
|
8007974: 080079a5 .word 0x080079a5
|
|
8007978: 08007981 .word 0x08007981
|
|
800797c: 080079a5 .word 0x080079a5
|
|
{
|
|
/* Non periodic transfer */
|
|
case EP_TYPE_CTRL:
|
|
case EP_TYPE_BULK:
|
|
|
|
len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
|
|
8007980: 68bb ldr r3, [r7, #8]
|
|
8007982: 6a1b ldr r3, [r3, #32]
|
|
8007984: 3303 adds r3, #3
|
|
8007986: 089b lsrs r3, r3, #2
|
|
8007988: 82fb strh r3, [r7, #22]
|
|
|
|
/* check if there is enough space in FIFO space */
|
|
if (len_words > (USBx->HNPTXSTS & 0xFFFFU))
|
|
800798a: 8afa ldrh r2, [r7, #22]
|
|
800798c: 68fb ldr r3, [r7, #12]
|
|
800798e: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007990: b29b uxth r3, r3
|
|
8007992: 429a cmp r2, r3
|
|
8007994: d91c bls.n 80079d0 <USB_HC_StartXfer+0x4cc>
|
|
{
|
|
/* need to process data in nptxfempty interrupt */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
|
|
8007996: 68fb ldr r3, [r7, #12]
|
|
8007998: 699b ldr r3, [r3, #24]
|
|
800799a: f043 0220 orr.w r2, r3, #32
|
|
800799e: 68fb ldr r3, [r7, #12]
|
|
80079a0: 619a str r2, [r3, #24]
|
|
}
|
|
break;
|
|
80079a2: e015 b.n 80079d0 <USB_HC_StartXfer+0x4cc>
|
|
|
|
/* Periodic transfer */
|
|
case EP_TYPE_INTR:
|
|
case EP_TYPE_ISOC:
|
|
len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);
|
|
80079a4: 68bb ldr r3, [r7, #8]
|
|
80079a6: 6a1b ldr r3, [r3, #32]
|
|
80079a8: 3303 adds r3, #3
|
|
80079aa: 089b lsrs r3, r3, #2
|
|
80079ac: 82fb strh r3, [r7, #22]
|
|
/* check if there is enough space in FIFO space */
|
|
if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */
|
|
80079ae: 8afa ldrh r2, [r7, #22]
|
|
80079b0: 6a3b ldr r3, [r7, #32]
|
|
80079b2: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80079b6: 691b ldr r3, [r3, #16]
|
|
80079b8: b29b uxth r3, r3
|
|
80079ba: 429a cmp r2, r3
|
|
80079bc: d90a bls.n 80079d4 <USB_HC_StartXfer+0x4d0>
|
|
{
|
|
/* need to process data in ptxfempty interrupt */
|
|
USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
|
|
80079be: 68fb ldr r3, [r7, #12]
|
|
80079c0: 699b ldr r3, [r3, #24]
|
|
80079c2: f043 6280 orr.w r2, r3, #67108864 @ 0x4000000
|
|
80079c6: 68fb ldr r3, [r7, #12]
|
|
80079c8: 619a str r2, [r3, #24]
|
|
}
|
|
break;
|
|
80079ca: e003 b.n 80079d4 <USB_HC_StartXfer+0x4d0>
|
|
|
|
default:
|
|
break;
|
|
80079cc: bf00 nop
|
|
80079ce: e002 b.n 80079d6 <USB_HC_StartXfer+0x4d2>
|
|
break;
|
|
80079d0: bf00 nop
|
|
80079d2: e000 b.n 80079d6 <USB_HC_StartXfer+0x4d2>
|
|
break;
|
|
80079d4: bf00 nop
|
|
}
|
|
|
|
/* Write packet into the Tx FIFO. */
|
|
(void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);
|
|
80079d6: 68bb ldr r3, [r7, #8]
|
|
80079d8: 6999 ldr r1, [r3, #24]
|
|
80079da: 68bb ldr r3, [r7, #8]
|
|
80079dc: 785a ldrb r2, [r3, #1]
|
|
80079de: 68bb ldr r3, [r7, #8]
|
|
80079e0: 6a1b ldr r3, [r3, #32]
|
|
80079e2: b29b uxth r3, r3
|
|
80079e4: 2000 movs r0, #0
|
|
80079e6: 9000 str r0, [sp, #0]
|
|
80079e8: 68f8 ldr r0, [r7, #12]
|
|
80079ea: f7ff f9c3 bl 8006d74 <USB_WritePacket>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80079ee: 2300 movs r3, #0
|
|
}
|
|
80079f0: 4618 mov r0, r3
|
|
80079f2: 3728 adds r7, #40 @ 0x28
|
|
80079f4: 46bd mov sp, r7
|
|
80079f6: bd80 pop {r7, pc}
|
|
|
|
080079f8 <USB_HC_ReadInterrupt>:
|
|
* @brief Read all host channel interrupts status
|
|
* @param USBx Selected device
|
|
* @retval HAL state
|
|
*/
|
|
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80079f8: b480 push {r7}
|
|
80079fa: b085 sub sp, #20
|
|
80079fc: af00 add r7, sp, #0
|
|
80079fe: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007a00: 687b ldr r3, [r7, #4]
|
|
8007a02: 60fb str r3, [r7, #12]
|
|
|
|
return ((USBx_HOST->HAINT) & 0xFFFFU);
|
|
8007a04: 68fb ldr r3, [r7, #12]
|
|
8007a06: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007a0a: 695b ldr r3, [r3, #20]
|
|
8007a0c: b29b uxth r3, r3
|
|
}
|
|
8007a0e: 4618 mov r0, r3
|
|
8007a10: 3714 adds r7, #20
|
|
8007a12: 46bd mov sp, r7
|
|
8007a14: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007a18: 4770 bx lr
|
|
|
|
08007a1a <USB_HC_Halt>:
|
|
* @param hc_num Host Channel number
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
|
|
{
|
|
8007a1a: b480 push {r7}
|
|
8007a1c: b089 sub sp, #36 @ 0x24
|
|
8007a1e: af00 add r7, sp, #0
|
|
8007a20: 6078 str r0, [r7, #4]
|
|
8007a22: 460b mov r3, r1
|
|
8007a24: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007a26: 687b ldr r3, [r7, #4]
|
|
8007a28: 61fb str r3, [r7, #28]
|
|
uint32_t hcnum = (uint32_t)hc_num;
|
|
8007a2a: 78fb ldrb r3, [r7, #3]
|
|
8007a2c: 61bb str r3, [r7, #24]
|
|
__IO uint32_t count = 0U;
|
|
8007a2e: 2300 movs r3, #0
|
|
8007a30: 60bb str r3, [r7, #8]
|
|
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
|
|
8007a32: 69bb ldr r3, [r7, #24]
|
|
8007a34: 015a lsls r2, r3, #5
|
|
8007a36: 69fb ldr r3, [r7, #28]
|
|
8007a38: 4413 add r3, r2
|
|
8007a3a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007a3e: 681b ldr r3, [r3, #0]
|
|
8007a40: 0c9b lsrs r3, r3, #18
|
|
8007a42: f003 0303 and.w r3, r3, #3
|
|
8007a46: 617b str r3, [r7, #20]
|
|
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
|
|
8007a48: 69bb ldr r3, [r7, #24]
|
|
8007a4a: 015a lsls r2, r3, #5
|
|
8007a4c: 69fb ldr r3, [r7, #28]
|
|
8007a4e: 4413 add r3, r2
|
|
8007a50: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007a54: 681b ldr r3, [r3, #0]
|
|
8007a56: 0fdb lsrs r3, r3, #31
|
|
8007a58: f003 0301 and.w r3, r3, #1
|
|
8007a5c: 613b str r3, [r7, #16]
|
|
uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
|
|
8007a5e: 69bb ldr r3, [r7, #24]
|
|
8007a60: 015a lsls r2, r3, #5
|
|
8007a62: 69fb ldr r3, [r7, #28]
|
|
8007a64: 4413 add r3, r2
|
|
8007a66: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007a6a: 685b ldr r3, [r3, #4]
|
|
8007a6c: 0fdb lsrs r3, r3, #31
|
|
8007a6e: f003 0301 and.w r3, r3, #1
|
|
8007a72: 60fb str r3, [r7, #12]
|
|
|
|
/* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
|
|
At the end of the next uframe/frame (in the worst case), the core generates a channel halted
|
|
and disables the channel automatically. */
|
|
|
|
if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
|
|
8007a74: 687b ldr r3, [r7, #4]
|
|
8007a76: 689b ldr r3, [r3, #8]
|
|
8007a78: f003 0320 and.w r3, r3, #32
|
|
8007a7c: 2b20 cmp r3, #32
|
|
8007a7e: d10d bne.n 8007a9c <USB_HC_Halt+0x82>
|
|
8007a80: 68fb ldr r3, [r7, #12]
|
|
8007a82: 2b00 cmp r3, #0
|
|
8007a84: d10a bne.n 8007a9c <USB_HC_Halt+0x82>
|
|
8007a86: 693b ldr r3, [r7, #16]
|
|
8007a88: 2b00 cmp r3, #0
|
|
8007a8a: d005 beq.n 8007a98 <USB_HC_Halt+0x7e>
|
|
((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
|
|
8007a8c: 697b ldr r3, [r7, #20]
|
|
8007a8e: 2b01 cmp r3, #1
|
|
8007a90: d002 beq.n 8007a98 <USB_HC_Halt+0x7e>
|
|
8007a92: 697b ldr r3, [r7, #20]
|
|
8007a94: 2b03 cmp r3, #3
|
|
8007a96: d101 bne.n 8007a9c <USB_HC_Halt+0x82>
|
|
{
|
|
return HAL_OK;
|
|
8007a98: 2300 movs r3, #0
|
|
8007a9a: e0d8 b.n 8007c4e <USB_HC_Halt+0x234>
|
|
}
|
|
|
|
/* Check for space in the request queue to issue the halt. */
|
|
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
|
|
8007a9c: 697b ldr r3, [r7, #20]
|
|
8007a9e: 2b00 cmp r3, #0
|
|
8007aa0: d002 beq.n 8007aa8 <USB_HC_Halt+0x8e>
|
|
8007aa2: 697b ldr r3, [r7, #20]
|
|
8007aa4: 2b02 cmp r3, #2
|
|
8007aa6: d173 bne.n 8007b90 <USB_HC_Halt+0x176>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
|
8007aa8: 69bb ldr r3, [r7, #24]
|
|
8007aaa: 015a lsls r2, r3, #5
|
|
8007aac: 69fb ldr r3, [r7, #28]
|
|
8007aae: 4413 add r3, r2
|
|
8007ab0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007ab4: 681b ldr r3, [r3, #0]
|
|
8007ab6: 69ba ldr r2, [r7, #24]
|
|
8007ab8: 0151 lsls r1, r2, #5
|
|
8007aba: 69fa ldr r2, [r7, #28]
|
|
8007abc: 440a add r2, r1
|
|
8007abe: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007ac2: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007ac6: 6013 str r3, [r2, #0]
|
|
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8007ac8: 687b ldr r3, [r7, #4]
|
|
8007aca: 689b ldr r3, [r3, #8]
|
|
8007acc: f003 0320 and.w r3, r3, #32
|
|
8007ad0: 2b00 cmp r3, #0
|
|
8007ad2: d14a bne.n 8007b6a <USB_HC_Halt+0x150>
|
|
{
|
|
if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
|
|
8007ad4: 687b ldr r3, [r7, #4]
|
|
8007ad6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007ad8: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
8007adc: 2b00 cmp r3, #0
|
|
8007ade: d133 bne.n 8007b48 <USB_HC_Halt+0x12e>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
|
8007ae0: 69bb ldr r3, [r7, #24]
|
|
8007ae2: 015a lsls r2, r3, #5
|
|
8007ae4: 69fb ldr r3, [r7, #28]
|
|
8007ae6: 4413 add r3, r2
|
|
8007ae8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007aec: 681b ldr r3, [r3, #0]
|
|
8007aee: 69ba ldr r2, [r7, #24]
|
|
8007af0: 0151 lsls r1, r2, #5
|
|
8007af2: 69fa ldr r2, [r7, #28]
|
|
8007af4: 440a add r2, r1
|
|
8007af6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007afa: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8007afe: 6013 str r3, [r2, #0]
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8007b00: 69bb ldr r3, [r7, #24]
|
|
8007b02: 015a lsls r2, r3, #5
|
|
8007b04: 69fb ldr r3, [r7, #28]
|
|
8007b06: 4413 add r3, r2
|
|
8007b08: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007b0c: 681b ldr r3, [r3, #0]
|
|
8007b0e: 69ba ldr r2, [r7, #24]
|
|
8007b10: 0151 lsls r1, r2, #5
|
|
8007b12: 69fa ldr r2, [r7, #28]
|
|
8007b14: 440a add r2, r1
|
|
8007b16: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007b1a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007b1e: 6013 str r3, [r2, #0]
|
|
do
|
|
{
|
|
count++;
|
|
8007b20: 68bb ldr r3, [r7, #8]
|
|
8007b22: 3301 adds r3, #1
|
|
8007b24: 60bb str r3, [r7, #8]
|
|
|
|
if (count > 1000U)
|
|
8007b26: 68bb ldr r3, [r7, #8]
|
|
8007b28: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8007b2c: d82e bhi.n 8007b8c <USB_HC_Halt+0x172>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8007b2e: 69bb ldr r3, [r7, #24]
|
|
8007b30: 015a lsls r2, r3, #5
|
|
8007b32: 69fb ldr r3, [r7, #28]
|
|
8007b34: 4413 add r3, r2
|
|
8007b36: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007b3a: 681b ldr r3, [r3, #0]
|
|
8007b3c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007b40: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007b44: d0ec beq.n 8007b20 <USB_HC_Halt+0x106>
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8007b46: e081 b.n 8007c4c <USB_HC_Halt+0x232>
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8007b48: 69bb ldr r3, [r7, #24]
|
|
8007b4a: 015a lsls r2, r3, #5
|
|
8007b4c: 69fb ldr r3, [r7, #28]
|
|
8007b4e: 4413 add r3, r2
|
|
8007b50: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007b54: 681b ldr r3, [r3, #0]
|
|
8007b56: 69ba ldr r2, [r7, #24]
|
|
8007b58: 0151 lsls r1, r2, #5
|
|
8007b5a: 69fa ldr r2, [r7, #28]
|
|
8007b5c: 440a add r2, r1
|
|
8007b5e: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007b62: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007b66: 6013 str r3, [r2, #0]
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8007b68: e070 b.n 8007c4c <USB_HC_Halt+0x232>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8007b6a: 69bb ldr r3, [r7, #24]
|
|
8007b6c: 015a lsls r2, r3, #5
|
|
8007b6e: 69fb ldr r3, [r7, #28]
|
|
8007b70: 4413 add r3, r2
|
|
8007b72: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007b76: 681b ldr r3, [r3, #0]
|
|
8007b78: 69ba ldr r2, [r7, #24]
|
|
8007b7a: 0151 lsls r1, r2, #5
|
|
8007b7c: 69fa ldr r2, [r7, #28]
|
|
8007b7e: 440a add r2, r1
|
|
8007b80: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007b84: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007b88: 6013 str r3, [r2, #0]
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8007b8a: e05f b.n 8007c4c <USB_HC_Halt+0x232>
|
|
break;
|
|
8007b8c: bf00 nop
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8007b8e: e05d b.n 8007c4c <USB_HC_Halt+0x232>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
|
8007b90: 69bb ldr r3, [r7, #24]
|
|
8007b92: 015a lsls r2, r3, #5
|
|
8007b94: 69fb ldr r3, [r7, #28]
|
|
8007b96: 4413 add r3, r2
|
|
8007b98: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007b9c: 681b ldr r3, [r3, #0]
|
|
8007b9e: 69ba ldr r2, [r7, #24]
|
|
8007ba0: 0151 lsls r1, r2, #5
|
|
8007ba2: 69fa ldr r2, [r7, #28]
|
|
8007ba4: 440a add r2, r1
|
|
8007ba6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007baa: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007bae: 6013 str r3, [r2, #0]
|
|
|
|
if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
|
|
8007bb0: 69fb ldr r3, [r7, #28]
|
|
8007bb2: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007bb6: 691b ldr r3, [r3, #16]
|
|
8007bb8: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
8007bbc: 2b00 cmp r3, #0
|
|
8007bbe: d133 bne.n 8007c28 <USB_HC_Halt+0x20e>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
|
8007bc0: 69bb ldr r3, [r7, #24]
|
|
8007bc2: 015a lsls r2, r3, #5
|
|
8007bc4: 69fb ldr r3, [r7, #28]
|
|
8007bc6: 4413 add r3, r2
|
|
8007bc8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007bcc: 681b ldr r3, [r3, #0]
|
|
8007bce: 69ba ldr r2, [r7, #24]
|
|
8007bd0: 0151 lsls r1, r2, #5
|
|
8007bd2: 69fa ldr r2, [r7, #28]
|
|
8007bd4: 440a add r2, r1
|
|
8007bd6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007bda: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8007bde: 6013 str r3, [r2, #0]
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8007be0: 69bb ldr r3, [r7, #24]
|
|
8007be2: 015a lsls r2, r3, #5
|
|
8007be4: 69fb ldr r3, [r7, #28]
|
|
8007be6: 4413 add r3, r2
|
|
8007be8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007bec: 681b ldr r3, [r3, #0]
|
|
8007bee: 69ba ldr r2, [r7, #24]
|
|
8007bf0: 0151 lsls r1, r2, #5
|
|
8007bf2: 69fa ldr r2, [r7, #28]
|
|
8007bf4: 440a add r2, r1
|
|
8007bf6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007bfa: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007bfe: 6013 str r3, [r2, #0]
|
|
do
|
|
{
|
|
count++;
|
|
8007c00: 68bb ldr r3, [r7, #8]
|
|
8007c02: 3301 adds r3, #1
|
|
8007c04: 60bb str r3, [r7, #8]
|
|
|
|
if (count > 1000U)
|
|
8007c06: 68bb ldr r3, [r7, #8]
|
|
8007c08: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8007c0c: d81d bhi.n 8007c4a <USB_HC_Halt+0x230>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8007c0e: 69bb ldr r3, [r7, #24]
|
|
8007c10: 015a lsls r2, r3, #5
|
|
8007c12: 69fb ldr r3, [r7, #28]
|
|
8007c14: 4413 add r3, r2
|
|
8007c16: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007c1a: 681b ldr r3, [r3, #0]
|
|
8007c1c: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007c20: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007c24: d0ec beq.n 8007c00 <USB_HC_Halt+0x1e6>
|
|
8007c26: e011 b.n 8007c4c <USB_HC_Halt+0x232>
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8007c28: 69bb ldr r3, [r7, #24]
|
|
8007c2a: 015a lsls r2, r3, #5
|
|
8007c2c: 69fb ldr r3, [r7, #28]
|
|
8007c2e: 4413 add r3, r2
|
|
8007c30: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007c34: 681b ldr r3, [r3, #0]
|
|
8007c36: 69ba ldr r2, [r7, #24]
|
|
8007c38: 0151 lsls r1, r2, #5
|
|
8007c3a: 69fa ldr r2, [r7, #28]
|
|
8007c3c: 440a add r2, r1
|
|
8007c3e: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007c42: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007c46: 6013 str r3, [r2, #0]
|
|
8007c48: e000 b.n 8007c4c <USB_HC_Halt+0x232>
|
|
break;
|
|
8007c4a: bf00 nop
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8007c4c: 2300 movs r3, #0
|
|
}
|
|
8007c4e: 4618 mov r0, r3
|
|
8007c50: 3724 adds r7, #36 @ 0x24
|
|
8007c52: 46bd mov sp, r7
|
|
8007c54: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007c58: 4770 bx lr
|
|
...
|
|
|
|
08007c5c <USB_DoPing>:
|
|
* @param hc_num Host Channel number
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
|
|
{
|
|
8007c5c: b480 push {r7}
|
|
8007c5e: b087 sub sp, #28
|
|
8007c60: af00 add r7, sp, #0
|
|
8007c62: 6078 str r0, [r7, #4]
|
|
8007c64: 460b mov r3, r1
|
|
8007c66: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007c68: 687b ldr r3, [r7, #4]
|
|
8007c6a: 617b str r3, [r7, #20]
|
|
uint32_t chnum = (uint32_t)ch_num;
|
|
8007c6c: 78fb ldrb r3, [r7, #3]
|
|
8007c6e: 613b str r3, [r7, #16]
|
|
uint32_t num_packets = 1U;
|
|
8007c70: 2301 movs r3, #1
|
|
8007c72: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
|
|
8007c74: 68fb ldr r3, [r7, #12]
|
|
8007c76: 04da lsls r2, r3, #19
|
|
8007c78: 4b15 ldr r3, [pc, #84] @ (8007cd0 <USB_DoPing+0x74>)
|
|
8007c7a: 4013 ands r3, r2
|
|
8007c7c: 693a ldr r2, [r7, #16]
|
|
8007c7e: 0151 lsls r1, r2, #5
|
|
8007c80: 697a ldr r2, [r7, #20]
|
|
8007c82: 440a add r2, r1
|
|
8007c84: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8007c88: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007c8c: 6113 str r3, [r2, #16]
|
|
USB_OTG_HCTSIZ_DOPING;
|
|
|
|
/* Set host channel enable */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8007c8e: 693b ldr r3, [r7, #16]
|
|
8007c90: 015a lsls r2, r3, #5
|
|
8007c92: 697b ldr r3, [r7, #20]
|
|
8007c94: 4413 add r3, r2
|
|
8007c96: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007c9a: 681b ldr r3, [r3, #0]
|
|
8007c9c: 60bb str r3, [r7, #8]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8007c9e: 68bb ldr r3, [r7, #8]
|
|
8007ca0: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8007ca4: 60bb str r3, [r7, #8]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8007ca6: 68bb ldr r3, [r7, #8]
|
|
8007ca8: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007cac: 60bb str r3, [r7, #8]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8007cae: 693b ldr r3, [r7, #16]
|
|
8007cb0: 015a lsls r2, r3, #5
|
|
8007cb2: 697b ldr r3, [r7, #20]
|
|
8007cb4: 4413 add r3, r2
|
|
8007cb6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007cba: 461a mov r2, r3
|
|
8007cbc: 68bb ldr r3, [r7, #8]
|
|
8007cbe: 6013 str r3, [r2, #0]
|
|
|
|
return HAL_OK;
|
|
8007cc0: 2300 movs r3, #0
|
|
}
|
|
8007cc2: 4618 mov r0, r3
|
|
8007cc4: 371c adds r7, #28
|
|
8007cc6: 46bd mov sp, r7
|
|
8007cc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ccc: 4770 bx lr
|
|
8007cce: bf00 nop
|
|
8007cd0: 1ff80000 .word 0x1ff80000
|
|
|
|
08007cd4 <USB_StopHost>:
|
|
* @brief Stop Host Core
|
|
* @param USBx Selected device
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8007cd4: b580 push {r7, lr}
|
|
8007cd6: b088 sub sp, #32
|
|
8007cd8: af00 add r7, sp, #0
|
|
8007cda: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8007cdc: 2300 movs r3, #0
|
|
8007cde: 77fb strb r3, [r7, #31]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8007ce0: 687b ldr r3, [r7, #4]
|
|
8007ce2: 617b str r3, [r7, #20]
|
|
__IO uint32_t count = 0U;
|
|
8007ce4: 2300 movs r3, #0
|
|
8007ce6: 60fb str r3, [r7, #12]
|
|
uint32_t value;
|
|
uint32_t i;
|
|
|
|
(void)USB_DisableGlobalInt(USBx);
|
|
8007ce8: 6878 ldr r0, [r7, #4]
|
|
8007cea: f7fe ff86 bl 8006bfa <USB_DisableGlobalInt>
|
|
|
|
/* Flush USB FIFO */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
8007cee: 2110 movs r1, #16
|
|
8007cf0: 6878 ldr r0, [r7, #4]
|
|
8007cf2: f7fe ffdf bl 8006cb4 <USB_FlushTxFifo>
|
|
8007cf6: 4603 mov r3, r0
|
|
8007cf8: 2b00 cmp r3, #0
|
|
8007cfa: d001 beq.n 8007d00 <USB_StopHost+0x2c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007cfc: 2301 movs r3, #1
|
|
8007cfe: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
8007d00: 6878 ldr r0, [r7, #4]
|
|
8007d02: f7ff f809 bl 8006d18 <USB_FlushRxFifo>
|
|
8007d06: 4603 mov r3, r0
|
|
8007d08: 2b00 cmp r3, #0
|
|
8007d0a: d001 beq.n 8007d10 <USB_StopHost+0x3c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8007d0c: 2301 movs r3, #1
|
|
8007d0e: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
/* Flush out any leftover queued requests. */
|
|
for (i = 0U; i <= 15U; i++)
|
|
8007d10: 2300 movs r3, #0
|
|
8007d12: 61bb str r3, [r7, #24]
|
|
8007d14: e01f b.n 8007d56 <USB_StopHost+0x82>
|
|
{
|
|
value = USBx_HC(i)->HCCHAR;
|
|
8007d16: 69bb ldr r3, [r7, #24]
|
|
8007d18: 015a lsls r2, r3, #5
|
|
8007d1a: 697b ldr r3, [r7, #20]
|
|
8007d1c: 4413 add r3, r2
|
|
8007d1e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007d22: 681b ldr r3, [r3, #0]
|
|
8007d24: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHDIS;
|
|
8007d26: 693b ldr r3, [r7, #16]
|
|
8007d28: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007d2c: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_CHENA;
|
|
8007d2e: 693b ldr r3, [r7, #16]
|
|
8007d30: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8007d34: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_EPDIR;
|
|
8007d36: 693b ldr r3, [r7, #16]
|
|
8007d38: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
8007d3c: 613b str r3, [r7, #16]
|
|
USBx_HC(i)->HCCHAR = value;
|
|
8007d3e: 69bb ldr r3, [r7, #24]
|
|
8007d40: 015a lsls r2, r3, #5
|
|
8007d42: 697b ldr r3, [r7, #20]
|
|
8007d44: 4413 add r3, r2
|
|
8007d46: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007d4a: 461a mov r2, r3
|
|
8007d4c: 693b ldr r3, [r7, #16]
|
|
8007d4e: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i <= 15U; i++)
|
|
8007d50: 69bb ldr r3, [r7, #24]
|
|
8007d52: 3301 adds r3, #1
|
|
8007d54: 61bb str r3, [r7, #24]
|
|
8007d56: 69bb ldr r3, [r7, #24]
|
|
8007d58: 2b0f cmp r3, #15
|
|
8007d5a: d9dc bls.n 8007d16 <USB_StopHost+0x42>
|
|
}
|
|
|
|
/* Halt all channels to put them into a known state. */
|
|
for (i = 0U; i <= 15U; i++)
|
|
8007d5c: 2300 movs r3, #0
|
|
8007d5e: 61bb str r3, [r7, #24]
|
|
8007d60: e034 b.n 8007dcc <USB_StopHost+0xf8>
|
|
{
|
|
value = USBx_HC(i)->HCCHAR;
|
|
8007d62: 69bb ldr r3, [r7, #24]
|
|
8007d64: 015a lsls r2, r3, #5
|
|
8007d66: 697b ldr r3, [r7, #20]
|
|
8007d68: 4413 add r3, r2
|
|
8007d6a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007d6e: 681b ldr r3, [r3, #0]
|
|
8007d70: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHDIS;
|
|
8007d72: 693b ldr r3, [r7, #16]
|
|
8007d74: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
8007d78: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHENA;
|
|
8007d7a: 693b ldr r3, [r7, #16]
|
|
8007d7c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8007d80: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_EPDIR;
|
|
8007d82: 693b ldr r3, [r7, #16]
|
|
8007d84: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
8007d88: 613b str r3, [r7, #16]
|
|
USBx_HC(i)->HCCHAR = value;
|
|
8007d8a: 69bb ldr r3, [r7, #24]
|
|
8007d8c: 015a lsls r2, r3, #5
|
|
8007d8e: 697b ldr r3, [r7, #20]
|
|
8007d90: 4413 add r3, r2
|
|
8007d92: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007d96: 461a mov r2, r3
|
|
8007d98: 693b ldr r3, [r7, #16]
|
|
8007d9a: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8007d9c: 68fb ldr r3, [r7, #12]
|
|
8007d9e: 3301 adds r3, #1
|
|
8007da0: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 1000U)
|
|
8007da2: 68fb ldr r3, [r7, #12]
|
|
8007da4: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8007da8: d80c bhi.n 8007dc4 <USB_StopHost+0xf0>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8007daa: 69bb ldr r3, [r7, #24]
|
|
8007dac: 015a lsls r2, r3, #5
|
|
8007dae: 697b ldr r3, [r7, #20]
|
|
8007db0: 4413 add r3, r2
|
|
8007db2: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8007db6: 681b ldr r3, [r3, #0]
|
|
8007db8: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8007dbc: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
8007dc0: d0ec beq.n 8007d9c <USB_StopHost+0xc8>
|
|
8007dc2: e000 b.n 8007dc6 <USB_StopHost+0xf2>
|
|
break;
|
|
8007dc4: bf00 nop
|
|
for (i = 0U; i <= 15U; i++)
|
|
8007dc6: 69bb ldr r3, [r7, #24]
|
|
8007dc8: 3301 adds r3, #1
|
|
8007dca: 61bb str r3, [r7, #24]
|
|
8007dcc: 69bb ldr r3, [r7, #24]
|
|
8007dce: 2b0f cmp r3, #15
|
|
8007dd0: d9c7 bls.n 8007d62 <USB_StopHost+0x8e>
|
|
}
|
|
|
|
/* Clear any pending Host interrupts */
|
|
USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK;
|
|
8007dd2: 697b ldr r3, [r7, #20]
|
|
8007dd4: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8007dd8: 461a mov r2, r3
|
|
8007dda: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
8007dde: 6153 str r3, [r2, #20]
|
|
USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
|
|
8007de0: 687b ldr r3, [r7, #4]
|
|
8007de2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8007de6: 615a str r2, [r3, #20]
|
|
|
|
(void)USB_EnableGlobalInt(USBx);
|
|
8007de8: 6878 ldr r0, [r7, #4]
|
|
8007dea: f7fe fef5 bl 8006bd8 <USB_EnableGlobalInt>
|
|
|
|
return ret;
|
|
8007dee: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
8007df0: 4618 mov r0, r3
|
|
8007df2: 3720 adds r7, #32
|
|
8007df4: 46bd mov sp, r7
|
|
8007df6: bd80 pop {r7, pc}
|
|
|
|
08007df8 <USBH_CDC_InterfaceInit>:
|
|
* The function init the CDC class.
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_CDC_InterfaceInit(USBH_HandleTypeDef *phost)
|
|
{
|
|
8007df8: b590 push {r4, r7, lr}
|
|
8007dfa: b089 sub sp, #36 @ 0x24
|
|
8007dfc: af04 add r7, sp, #16
|
|
8007dfe: 6078 str r0, [r7, #4]
|
|
|
|
USBH_StatusTypeDef status;
|
|
uint8_t interface;
|
|
CDC_HandleTypeDef *CDC_Handle;
|
|
|
|
interface = USBH_FindInterface(phost, COMMUNICATION_INTERFACE_CLASS_CODE,
|
|
8007e00: 2301 movs r3, #1
|
|
8007e02: 2202 movs r2, #2
|
|
8007e04: 2102 movs r1, #2
|
|
8007e06: 6878 ldr r0, [r7, #4]
|
|
8007e08: f000 fcbd bl 8008786 <USBH_FindInterface>
|
|
8007e0c: 4603 mov r3, r0
|
|
8007e0e: 73fb strb r3, [r7, #15]
|
|
ABSTRACT_CONTROL_MODEL, COMMON_AT_COMMAND);
|
|
|
|
if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */
|
|
8007e10: 7bfb ldrb r3, [r7, #15]
|
|
8007e12: 2bff cmp r3, #255 @ 0xff
|
|
8007e14: d002 beq.n 8007e1c <USBH_CDC_InterfaceInit+0x24>
|
|
8007e16: 7bfb ldrb r3, [r7, #15]
|
|
8007e18: 2b01 cmp r3, #1
|
|
8007e1a: d901 bls.n 8007e20 <USBH_CDC_InterfaceInit+0x28>
|
|
{
|
|
USBH_DbgLog("Cannot Find the interface for Communication Interface Class.", phost->pActiveClass->Name);
|
|
return USBH_FAIL;
|
|
8007e1c: 2302 movs r3, #2
|
|
8007e1e: e13d b.n 800809c <USBH_CDC_InterfaceInit+0x2a4>
|
|
}
|
|
|
|
status = USBH_SelectInterface(phost, interface);
|
|
8007e20: 7bfb ldrb r3, [r7, #15]
|
|
8007e22: 4619 mov r1, r3
|
|
8007e24: 6878 ldr r0, [r7, #4]
|
|
8007e26: f000 fc92 bl 800874e <USBH_SelectInterface>
|
|
8007e2a: 4603 mov r3, r0
|
|
8007e2c: 73bb strb r3, [r7, #14]
|
|
|
|
if (status != USBH_OK)
|
|
8007e2e: 7bbb ldrb r3, [r7, #14]
|
|
8007e30: 2b00 cmp r3, #0
|
|
8007e32: d001 beq.n 8007e38 <USBH_CDC_InterfaceInit+0x40>
|
|
{
|
|
return USBH_FAIL;
|
|
8007e34: 2302 movs r3, #2
|
|
8007e36: e131 b.n 800809c <USBH_CDC_InterfaceInit+0x2a4>
|
|
}
|
|
|
|
phost->pActiveClass->pData = (CDC_HandleTypeDef *)USBH_malloc(sizeof(CDC_HandleTypeDef));
|
|
8007e38: 687b ldr r3, [r7, #4]
|
|
8007e3a: f8d3 437c ldr.w r4, [r3, #892] @ 0x37c
|
|
8007e3e: 2050 movs r0, #80 @ 0x50
|
|
8007e40: f004 ffc8 bl 800cdd4 <malloc>
|
|
8007e44: 4603 mov r3, r0
|
|
8007e46: 61e3 str r3, [r4, #28]
|
|
CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
8007e48: 687b ldr r3, [r7, #4]
|
|
8007e4a: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8007e4e: 69db ldr r3, [r3, #28]
|
|
8007e50: 60bb str r3, [r7, #8]
|
|
|
|
if (CDC_Handle == NULL)
|
|
8007e52: 68bb ldr r3, [r7, #8]
|
|
8007e54: 2b00 cmp r3, #0
|
|
8007e56: d101 bne.n 8007e5c <USBH_CDC_InterfaceInit+0x64>
|
|
{
|
|
USBH_DbgLog("Cannot allocate memory for CDC Handle");
|
|
return USBH_FAIL;
|
|
8007e58: 2302 movs r3, #2
|
|
8007e5a: e11f b.n 800809c <USBH_CDC_InterfaceInit+0x2a4>
|
|
}
|
|
|
|
/* Initialize cdc handler */
|
|
(void)USBH_memset(CDC_Handle, 0, sizeof(CDC_HandleTypeDef));
|
|
8007e5c: 2250 movs r2, #80 @ 0x50
|
|
8007e5e: 2100 movs r1, #0
|
|
8007e60: 68b8 ldr r0, [r7, #8]
|
|
8007e62: f005 f875 bl 800cf50 <memset>
|
|
|
|
/*Collect the notification endpoint address and length*/
|
|
if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) != 0U)
|
|
8007e66: 7bfb ldrb r3, [r7, #15]
|
|
8007e68: 687a ldr r2, [r7, #4]
|
|
8007e6a: 211a movs r1, #26
|
|
8007e6c: fb01 f303 mul.w r3, r1, r3
|
|
8007e70: 4413 add r3, r2
|
|
8007e72: f203 334e addw r3, r3, #846 @ 0x34e
|
|
8007e76: 781b ldrb r3, [r3, #0]
|
|
8007e78: b25b sxtb r3, r3
|
|
8007e7a: 2b00 cmp r3, #0
|
|
8007e7c: da15 bge.n 8007eaa <USBH_CDC_InterfaceInit+0xb2>
|
|
{
|
|
CDC_Handle->CommItf.NotifEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
|
|
8007e7e: 7bfb ldrb r3, [r7, #15]
|
|
8007e80: 687a ldr r2, [r7, #4]
|
|
8007e82: 211a movs r1, #26
|
|
8007e84: fb01 f303 mul.w r3, r1, r3
|
|
8007e88: 4413 add r3, r2
|
|
8007e8a: f203 334e addw r3, r3, #846 @ 0x34e
|
|
8007e8e: 781a ldrb r2, [r3, #0]
|
|
8007e90: 68bb ldr r3, [r7, #8]
|
|
8007e92: 705a strb r2, [r3, #1]
|
|
CDC_Handle->CommItf.NotifEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
|
|
8007e94: 7bfb ldrb r3, [r7, #15]
|
|
8007e96: 687a ldr r2, [r7, #4]
|
|
8007e98: 211a movs r1, #26
|
|
8007e9a: fb01 f303 mul.w r3, r1, r3
|
|
8007e9e: 4413 add r3, r2
|
|
8007ea0: f503 7354 add.w r3, r3, #848 @ 0x350
|
|
8007ea4: 881a ldrh r2, [r3, #0]
|
|
8007ea6: 68bb ldr r3, [r7, #8]
|
|
8007ea8: 815a strh r2, [r3, #10]
|
|
}
|
|
|
|
/*Allocate the length for host channel number in*/
|
|
CDC_Handle->CommItf.NotifPipe = USBH_AllocPipe(phost, CDC_Handle->CommItf.NotifEp);
|
|
8007eaa: 68bb ldr r3, [r7, #8]
|
|
8007eac: 785b ldrb r3, [r3, #1]
|
|
8007eae: 4619 mov r1, r3
|
|
8007eb0: 6878 ldr r0, [r7, #4]
|
|
8007eb2: f002 f90c bl 800a0ce <USBH_AllocPipe>
|
|
8007eb6: 4603 mov r3, r0
|
|
8007eb8: 461a mov r2, r3
|
|
8007eba: 68bb ldr r3, [r7, #8]
|
|
8007ebc: 701a strb r2, [r3, #0]
|
|
|
|
/* Open pipe for Notification endpoint */
|
|
(void)USBH_OpenPipe(phost, CDC_Handle->CommItf.NotifPipe, CDC_Handle->CommItf.NotifEp,
|
|
8007ebe: 68bb ldr r3, [r7, #8]
|
|
8007ec0: 7819 ldrb r1, [r3, #0]
|
|
8007ec2: 68bb ldr r3, [r7, #8]
|
|
8007ec4: 7858 ldrb r0, [r3, #1]
|
|
8007ec6: 687b ldr r3, [r7, #4]
|
|
8007ec8: f893 431c ldrb.w r4, [r3, #796] @ 0x31c
|
|
8007ecc: 687b ldr r3, [r7, #4]
|
|
8007ece: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8007ed2: 68ba ldr r2, [r7, #8]
|
|
8007ed4: 8952 ldrh r2, [r2, #10]
|
|
8007ed6: 9202 str r2, [sp, #8]
|
|
8007ed8: 2203 movs r2, #3
|
|
8007eda: 9201 str r2, [sp, #4]
|
|
8007edc: 9300 str r3, [sp, #0]
|
|
8007ede: 4623 mov r3, r4
|
|
8007ee0: 4602 mov r2, r0
|
|
8007ee2: 6878 ldr r0, [r7, #4]
|
|
8007ee4: f002 f8c4 bl 800a070 <USBH_OpenPipe>
|
|
phost->device.address, phost->device.speed, USB_EP_TYPE_INTR,
|
|
CDC_Handle->CommItf.NotifEpSize);
|
|
|
|
(void)USBH_LL_SetToggle(phost, CDC_Handle->CommItf.NotifPipe, 0U);
|
|
8007ee8: 68bb ldr r3, [r7, #8]
|
|
8007eea: 781b ldrb r3, [r3, #0]
|
|
8007eec: 2200 movs r2, #0
|
|
8007eee: 4619 mov r1, r3
|
|
8007ef0: 6878 ldr r0, [r7, #4]
|
|
8007ef2: f004 fee9 bl 800ccc8 <USBH_LL_SetToggle>
|
|
|
|
interface = USBH_FindInterface(phost, DATA_INTERFACE_CLASS_CODE,
|
|
8007ef6: 2300 movs r3, #0
|
|
8007ef8: 2200 movs r2, #0
|
|
8007efa: 210a movs r1, #10
|
|
8007efc: 6878 ldr r0, [r7, #4]
|
|
8007efe: f000 fc42 bl 8008786 <USBH_FindInterface>
|
|
8007f02: 4603 mov r3, r0
|
|
8007f04: 73fb strb r3, [r7, #15]
|
|
RESERVED, NO_CLASS_SPECIFIC_PROTOCOL_CODE);
|
|
|
|
if ((interface == 0xFFU) || (interface >= USBH_MAX_NUM_INTERFACES)) /* No Valid Interface */
|
|
8007f06: 7bfb ldrb r3, [r7, #15]
|
|
8007f08: 2bff cmp r3, #255 @ 0xff
|
|
8007f0a: d002 beq.n 8007f12 <USBH_CDC_InterfaceInit+0x11a>
|
|
8007f0c: 7bfb ldrb r3, [r7, #15]
|
|
8007f0e: 2b01 cmp r3, #1
|
|
8007f10: d901 bls.n 8007f16 <USBH_CDC_InterfaceInit+0x11e>
|
|
{
|
|
USBH_DbgLog("Cannot Find the interface for Data Interface Class.", phost->pActiveClass->Name);
|
|
return USBH_FAIL;
|
|
8007f12: 2302 movs r3, #2
|
|
8007f14: e0c2 b.n 800809c <USBH_CDC_InterfaceInit+0x2a4>
|
|
}
|
|
|
|
/*Collect the class specific endpoint address and length*/
|
|
if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress & 0x80U) != 0U)
|
|
8007f16: 7bfb ldrb r3, [r7, #15]
|
|
8007f18: 687a ldr r2, [r7, #4]
|
|
8007f1a: 211a movs r1, #26
|
|
8007f1c: fb01 f303 mul.w r3, r1, r3
|
|
8007f20: 4413 add r3, r2
|
|
8007f22: f203 334e addw r3, r3, #846 @ 0x34e
|
|
8007f26: 781b ldrb r3, [r3, #0]
|
|
8007f28: b25b sxtb r3, r3
|
|
8007f2a: 2b00 cmp r3, #0
|
|
8007f2c: da16 bge.n 8007f5c <USBH_CDC_InterfaceInit+0x164>
|
|
{
|
|
CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
|
|
8007f2e: 7bfb ldrb r3, [r7, #15]
|
|
8007f30: 687a ldr r2, [r7, #4]
|
|
8007f32: 211a movs r1, #26
|
|
8007f34: fb01 f303 mul.w r3, r1, r3
|
|
8007f38: 4413 add r3, r2
|
|
8007f3a: f203 334e addw r3, r3, #846 @ 0x34e
|
|
8007f3e: 781a ldrb r2, [r3, #0]
|
|
8007f40: 68bb ldr r3, [r7, #8]
|
|
8007f42: 73da strb r2, [r3, #15]
|
|
CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
|
|
8007f44: 7bfb ldrb r3, [r7, #15]
|
|
8007f46: 687a ldr r2, [r7, #4]
|
|
8007f48: 211a movs r1, #26
|
|
8007f4a: fb01 f303 mul.w r3, r1, r3
|
|
8007f4e: 4413 add r3, r2
|
|
8007f50: f503 7354 add.w r3, r3, #848 @ 0x350
|
|
8007f54: 881a ldrh r2, [r3, #0]
|
|
8007f56: 68bb ldr r3, [r7, #8]
|
|
8007f58: 835a strh r2, [r3, #26]
|
|
8007f5a: e015 b.n 8007f88 <USBH_CDC_InterfaceInit+0x190>
|
|
}
|
|
else
|
|
{
|
|
CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].bEndpointAddress;
|
|
8007f5c: 7bfb ldrb r3, [r7, #15]
|
|
8007f5e: 687a ldr r2, [r7, #4]
|
|
8007f60: 211a movs r1, #26
|
|
8007f62: fb01 f303 mul.w r3, r1, r3
|
|
8007f66: 4413 add r3, r2
|
|
8007f68: f203 334e addw r3, r3, #846 @ 0x34e
|
|
8007f6c: 781a ldrb r2, [r3, #0]
|
|
8007f6e: 68bb ldr r3, [r7, #8]
|
|
8007f70: 739a strb r2, [r3, #14]
|
|
CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[0].wMaxPacketSize;
|
|
8007f72: 7bfb ldrb r3, [r7, #15]
|
|
8007f74: 687a ldr r2, [r7, #4]
|
|
8007f76: 211a movs r1, #26
|
|
8007f78: fb01 f303 mul.w r3, r1, r3
|
|
8007f7c: 4413 add r3, r2
|
|
8007f7e: f503 7354 add.w r3, r3, #848 @ 0x350
|
|
8007f82: 881a ldrh r2, [r3, #0]
|
|
8007f84: 68bb ldr r3, [r7, #8]
|
|
8007f86: 831a strh r2, [r3, #24]
|
|
}
|
|
|
|
if ((phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress & 0x80U) != 0U)
|
|
8007f88: 7bfb ldrb r3, [r7, #15]
|
|
8007f8a: 687a ldr r2, [r7, #4]
|
|
8007f8c: 211a movs r1, #26
|
|
8007f8e: fb01 f303 mul.w r3, r1, r3
|
|
8007f92: 4413 add r3, r2
|
|
8007f94: f203 3356 addw r3, r3, #854 @ 0x356
|
|
8007f98: 781b ldrb r3, [r3, #0]
|
|
8007f9a: b25b sxtb r3, r3
|
|
8007f9c: 2b00 cmp r3, #0
|
|
8007f9e: da16 bge.n 8007fce <USBH_CDC_InterfaceInit+0x1d6>
|
|
{
|
|
CDC_Handle->DataItf.InEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress;
|
|
8007fa0: 7bfb ldrb r3, [r7, #15]
|
|
8007fa2: 687a ldr r2, [r7, #4]
|
|
8007fa4: 211a movs r1, #26
|
|
8007fa6: fb01 f303 mul.w r3, r1, r3
|
|
8007faa: 4413 add r3, r2
|
|
8007fac: f203 3356 addw r3, r3, #854 @ 0x356
|
|
8007fb0: 781a ldrb r2, [r3, #0]
|
|
8007fb2: 68bb ldr r3, [r7, #8]
|
|
8007fb4: 73da strb r2, [r3, #15]
|
|
CDC_Handle->DataItf.InEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize;
|
|
8007fb6: 7bfb ldrb r3, [r7, #15]
|
|
8007fb8: 687a ldr r2, [r7, #4]
|
|
8007fba: 211a movs r1, #26
|
|
8007fbc: fb01 f303 mul.w r3, r1, r3
|
|
8007fc0: 4413 add r3, r2
|
|
8007fc2: f503 7356 add.w r3, r3, #856 @ 0x358
|
|
8007fc6: 881a ldrh r2, [r3, #0]
|
|
8007fc8: 68bb ldr r3, [r7, #8]
|
|
8007fca: 835a strh r2, [r3, #26]
|
|
8007fcc: e015 b.n 8007ffa <USBH_CDC_InterfaceInit+0x202>
|
|
}
|
|
else
|
|
{
|
|
CDC_Handle->DataItf.OutEp = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].bEndpointAddress;
|
|
8007fce: 7bfb ldrb r3, [r7, #15]
|
|
8007fd0: 687a ldr r2, [r7, #4]
|
|
8007fd2: 211a movs r1, #26
|
|
8007fd4: fb01 f303 mul.w r3, r1, r3
|
|
8007fd8: 4413 add r3, r2
|
|
8007fda: f203 3356 addw r3, r3, #854 @ 0x356
|
|
8007fde: 781a ldrb r2, [r3, #0]
|
|
8007fe0: 68bb ldr r3, [r7, #8]
|
|
8007fe2: 739a strb r2, [r3, #14]
|
|
CDC_Handle->DataItf.OutEpSize = phost->device.CfgDesc.Itf_Desc[interface].Ep_Desc[1].wMaxPacketSize;
|
|
8007fe4: 7bfb ldrb r3, [r7, #15]
|
|
8007fe6: 687a ldr r2, [r7, #4]
|
|
8007fe8: 211a movs r1, #26
|
|
8007fea: fb01 f303 mul.w r3, r1, r3
|
|
8007fee: 4413 add r3, r2
|
|
8007ff0: f503 7356 add.w r3, r3, #856 @ 0x358
|
|
8007ff4: 881a ldrh r2, [r3, #0]
|
|
8007ff6: 68bb ldr r3, [r7, #8]
|
|
8007ff8: 831a strh r2, [r3, #24]
|
|
}
|
|
|
|
/*Allocate the length for host channel number out*/
|
|
CDC_Handle->DataItf.OutPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.OutEp);
|
|
8007ffa: 68bb ldr r3, [r7, #8]
|
|
8007ffc: 7b9b ldrb r3, [r3, #14]
|
|
8007ffe: 4619 mov r1, r3
|
|
8008000: 6878 ldr r0, [r7, #4]
|
|
8008002: f002 f864 bl 800a0ce <USBH_AllocPipe>
|
|
8008006: 4603 mov r3, r0
|
|
8008008: 461a mov r2, r3
|
|
800800a: 68bb ldr r3, [r7, #8]
|
|
800800c: 735a strb r2, [r3, #13]
|
|
|
|
/*Allocate the length for host channel number in*/
|
|
CDC_Handle->DataItf.InPipe = USBH_AllocPipe(phost, CDC_Handle->DataItf.InEp);
|
|
800800e: 68bb ldr r3, [r7, #8]
|
|
8008010: 7bdb ldrb r3, [r3, #15]
|
|
8008012: 4619 mov r1, r3
|
|
8008014: 6878 ldr r0, [r7, #4]
|
|
8008016: f002 f85a bl 800a0ce <USBH_AllocPipe>
|
|
800801a: 4603 mov r3, r0
|
|
800801c: 461a mov r2, r3
|
|
800801e: 68bb ldr r3, [r7, #8]
|
|
8008020: 731a strb r2, [r3, #12]
|
|
|
|
/* Open channel for OUT endpoint */
|
|
(void)USBH_OpenPipe(phost, CDC_Handle->DataItf.OutPipe, CDC_Handle->DataItf.OutEp,
|
|
8008022: 68bb ldr r3, [r7, #8]
|
|
8008024: 7b59 ldrb r1, [r3, #13]
|
|
8008026: 68bb ldr r3, [r7, #8]
|
|
8008028: 7b98 ldrb r0, [r3, #14]
|
|
800802a: 687b ldr r3, [r7, #4]
|
|
800802c: f893 431c ldrb.w r4, [r3, #796] @ 0x31c
|
|
8008030: 687b ldr r3, [r7, #4]
|
|
8008032: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8008036: 68ba ldr r2, [r7, #8]
|
|
8008038: 8b12 ldrh r2, [r2, #24]
|
|
800803a: 9202 str r2, [sp, #8]
|
|
800803c: 2202 movs r2, #2
|
|
800803e: 9201 str r2, [sp, #4]
|
|
8008040: 9300 str r3, [sp, #0]
|
|
8008042: 4623 mov r3, r4
|
|
8008044: 4602 mov r2, r0
|
|
8008046: 6878 ldr r0, [r7, #4]
|
|
8008048: f002 f812 bl 800a070 <USBH_OpenPipe>
|
|
phost->device.address, phost->device.speed, USB_EP_TYPE_BULK,
|
|
CDC_Handle->DataItf.OutEpSize);
|
|
|
|
/* Open channel for IN endpoint */
|
|
(void)USBH_OpenPipe(phost, CDC_Handle->DataItf.InPipe, CDC_Handle->DataItf.InEp,
|
|
800804c: 68bb ldr r3, [r7, #8]
|
|
800804e: 7b19 ldrb r1, [r3, #12]
|
|
8008050: 68bb ldr r3, [r7, #8]
|
|
8008052: 7bd8 ldrb r0, [r3, #15]
|
|
8008054: 687b ldr r3, [r7, #4]
|
|
8008056: f893 431c ldrb.w r4, [r3, #796] @ 0x31c
|
|
800805a: 687b ldr r3, [r7, #4]
|
|
800805c: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8008060: 68ba ldr r2, [r7, #8]
|
|
8008062: 8b52 ldrh r2, [r2, #26]
|
|
8008064: 9202 str r2, [sp, #8]
|
|
8008066: 2202 movs r2, #2
|
|
8008068: 9201 str r2, [sp, #4]
|
|
800806a: 9300 str r3, [sp, #0]
|
|
800806c: 4623 mov r3, r4
|
|
800806e: 4602 mov r2, r0
|
|
8008070: 6878 ldr r0, [r7, #4]
|
|
8008072: f001 fffd bl 800a070 <USBH_OpenPipe>
|
|
phost->device.address, phost->device.speed, USB_EP_TYPE_BULK,
|
|
CDC_Handle->DataItf.InEpSize);
|
|
|
|
CDC_Handle->state = CDC_IDLE_STATE;
|
|
8008076: 68bb ldr r3, [r7, #8]
|
|
8008078: 2200 movs r2, #0
|
|
800807a: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
|
|
(void)USBH_LL_SetToggle(phost, CDC_Handle->DataItf.OutPipe, 0U);
|
|
800807e: 68bb ldr r3, [r7, #8]
|
|
8008080: 7b5b ldrb r3, [r3, #13]
|
|
8008082: 2200 movs r2, #0
|
|
8008084: 4619 mov r1, r3
|
|
8008086: 6878 ldr r0, [r7, #4]
|
|
8008088: f004 fe1e bl 800ccc8 <USBH_LL_SetToggle>
|
|
(void)USBH_LL_SetToggle(phost, CDC_Handle->DataItf.InPipe, 0U);
|
|
800808c: 68bb ldr r3, [r7, #8]
|
|
800808e: 7b1b ldrb r3, [r3, #12]
|
|
8008090: 2200 movs r2, #0
|
|
8008092: 4619 mov r1, r3
|
|
8008094: 6878 ldr r0, [r7, #4]
|
|
8008096: f004 fe17 bl 800ccc8 <USBH_LL_SetToggle>
|
|
|
|
return USBH_OK;
|
|
800809a: 2300 movs r3, #0
|
|
}
|
|
800809c: 4618 mov r0, r3
|
|
800809e: 3714 adds r7, #20
|
|
80080a0: 46bd mov sp, r7
|
|
80080a2: bd90 pop {r4, r7, pc}
|
|
|
|
080080a4 <USBH_CDC_InterfaceDeInit>:
|
|
* The function DeInit the Pipes used for the CDC class.
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_CDC_InterfaceDeInit(USBH_HandleTypeDef *phost)
|
|
{
|
|
80080a4: b580 push {r7, lr}
|
|
80080a6: b084 sub sp, #16
|
|
80080a8: af00 add r7, sp, #0
|
|
80080aa: 6078 str r0, [r7, #4]
|
|
CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
80080ac: 687b ldr r3, [r7, #4]
|
|
80080ae: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80080b2: 69db ldr r3, [r3, #28]
|
|
80080b4: 60fb str r3, [r7, #12]
|
|
|
|
if ((CDC_Handle->CommItf.NotifPipe) != 0U)
|
|
80080b6: 68fb ldr r3, [r7, #12]
|
|
80080b8: 781b ldrb r3, [r3, #0]
|
|
80080ba: 2b00 cmp r3, #0
|
|
80080bc: d00e beq.n 80080dc <USBH_CDC_InterfaceDeInit+0x38>
|
|
{
|
|
(void)USBH_ClosePipe(phost, CDC_Handle->CommItf.NotifPipe);
|
|
80080be: 68fb ldr r3, [r7, #12]
|
|
80080c0: 781b ldrb r3, [r3, #0]
|
|
80080c2: 4619 mov r1, r3
|
|
80080c4: 6878 ldr r0, [r7, #4]
|
|
80080c6: f001 fff2 bl 800a0ae <USBH_ClosePipe>
|
|
(void)USBH_FreePipe(phost, CDC_Handle->CommItf.NotifPipe);
|
|
80080ca: 68fb ldr r3, [r7, #12]
|
|
80080cc: 781b ldrb r3, [r3, #0]
|
|
80080ce: 4619 mov r1, r3
|
|
80080d0: 6878 ldr r0, [r7, #4]
|
|
80080d2: f002 f81d bl 800a110 <USBH_FreePipe>
|
|
CDC_Handle->CommItf.NotifPipe = 0U; /* Reset the Channel as Free */
|
|
80080d6: 68fb ldr r3, [r7, #12]
|
|
80080d8: 2200 movs r2, #0
|
|
80080da: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if ((CDC_Handle->DataItf.InPipe) != 0U)
|
|
80080dc: 68fb ldr r3, [r7, #12]
|
|
80080de: 7b1b ldrb r3, [r3, #12]
|
|
80080e0: 2b00 cmp r3, #0
|
|
80080e2: d00e beq.n 8008102 <USBH_CDC_InterfaceDeInit+0x5e>
|
|
{
|
|
(void)USBH_ClosePipe(phost, CDC_Handle->DataItf.InPipe);
|
|
80080e4: 68fb ldr r3, [r7, #12]
|
|
80080e6: 7b1b ldrb r3, [r3, #12]
|
|
80080e8: 4619 mov r1, r3
|
|
80080ea: 6878 ldr r0, [r7, #4]
|
|
80080ec: f001 ffdf bl 800a0ae <USBH_ClosePipe>
|
|
(void)USBH_FreePipe(phost, CDC_Handle->DataItf.InPipe);
|
|
80080f0: 68fb ldr r3, [r7, #12]
|
|
80080f2: 7b1b ldrb r3, [r3, #12]
|
|
80080f4: 4619 mov r1, r3
|
|
80080f6: 6878 ldr r0, [r7, #4]
|
|
80080f8: f002 f80a bl 800a110 <USBH_FreePipe>
|
|
CDC_Handle->DataItf.InPipe = 0U; /* Reset the Channel as Free */
|
|
80080fc: 68fb ldr r3, [r7, #12]
|
|
80080fe: 2200 movs r2, #0
|
|
8008100: 731a strb r2, [r3, #12]
|
|
}
|
|
|
|
if ((CDC_Handle->DataItf.OutPipe) != 0U)
|
|
8008102: 68fb ldr r3, [r7, #12]
|
|
8008104: 7b5b ldrb r3, [r3, #13]
|
|
8008106: 2b00 cmp r3, #0
|
|
8008108: d00e beq.n 8008128 <USBH_CDC_InterfaceDeInit+0x84>
|
|
{
|
|
(void)USBH_ClosePipe(phost, CDC_Handle->DataItf.OutPipe);
|
|
800810a: 68fb ldr r3, [r7, #12]
|
|
800810c: 7b5b ldrb r3, [r3, #13]
|
|
800810e: 4619 mov r1, r3
|
|
8008110: 6878 ldr r0, [r7, #4]
|
|
8008112: f001 ffcc bl 800a0ae <USBH_ClosePipe>
|
|
(void)USBH_FreePipe(phost, CDC_Handle->DataItf.OutPipe);
|
|
8008116: 68fb ldr r3, [r7, #12]
|
|
8008118: 7b5b ldrb r3, [r3, #13]
|
|
800811a: 4619 mov r1, r3
|
|
800811c: 6878 ldr r0, [r7, #4]
|
|
800811e: f001 fff7 bl 800a110 <USBH_FreePipe>
|
|
CDC_Handle->DataItf.OutPipe = 0U; /* Reset the Channel as Free */
|
|
8008122: 68fb ldr r3, [r7, #12]
|
|
8008124: 2200 movs r2, #0
|
|
8008126: 735a strb r2, [r3, #13]
|
|
}
|
|
|
|
if ((phost->pActiveClass->pData) != NULL)
|
|
8008128: 687b ldr r3, [r7, #4]
|
|
800812a: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
800812e: 69db ldr r3, [r3, #28]
|
|
8008130: 2b00 cmp r3, #0
|
|
8008132: d00b beq.n 800814c <USBH_CDC_InterfaceDeInit+0xa8>
|
|
{
|
|
USBH_free(phost->pActiveClass->pData);
|
|
8008134: 687b ldr r3, [r7, #4]
|
|
8008136: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
800813a: 69db ldr r3, [r3, #28]
|
|
800813c: 4618 mov r0, r3
|
|
800813e: f004 fe51 bl 800cde4 <free>
|
|
phost->pActiveClass->pData = 0U;
|
|
8008142: 687b ldr r3, [r7, #4]
|
|
8008144: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008148: 2200 movs r2, #0
|
|
800814a: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
return USBH_OK;
|
|
800814c: 2300 movs r3, #0
|
|
}
|
|
800814e: 4618 mov r0, r3
|
|
8008150: 3710 adds r7, #16
|
|
8008152: 46bd mov sp, r7
|
|
8008154: bd80 pop {r7, pc}
|
|
|
|
08008156 <USBH_CDC_ClassRequest>:
|
|
* for CDC class.
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_CDC_ClassRequest(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008156: b580 push {r7, lr}
|
|
8008158: b084 sub sp, #16
|
|
800815a: af00 add r7, sp, #0
|
|
800815c: 6078 str r0, [r7, #4]
|
|
USBH_StatusTypeDef status;
|
|
CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
800815e: 687b ldr r3, [r7, #4]
|
|
8008160: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008164: 69db ldr r3, [r3, #28]
|
|
8008166: 60fb str r3, [r7, #12]
|
|
|
|
/* Issue the get line coding request */
|
|
status = GetLineCoding(phost, &CDC_Handle->LineCoding);
|
|
8008168: 68fb ldr r3, [r7, #12]
|
|
800816a: 3340 adds r3, #64 @ 0x40
|
|
800816c: 4619 mov r1, r3
|
|
800816e: 6878 ldr r0, [r7, #4]
|
|
8008170: f000 f8b1 bl 80082d6 <GetLineCoding>
|
|
8008174: 4603 mov r3, r0
|
|
8008176: 72fb strb r3, [r7, #11]
|
|
if (status == USBH_OK)
|
|
8008178: 7afb ldrb r3, [r7, #11]
|
|
800817a: 2b00 cmp r3, #0
|
|
800817c: d105 bne.n 800818a <USBH_CDC_ClassRequest+0x34>
|
|
{
|
|
phost->pUser(phost, HOST_USER_CLASS_ACTIVE);
|
|
800817e: 687b ldr r3, [r7, #4]
|
|
8008180: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008184: 2102 movs r1, #2
|
|
8008186: 6878 ldr r0, [r7, #4]
|
|
8008188: 4798 blx r3
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
|
|
return status;
|
|
800818a: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
800818c: 4618 mov r0, r3
|
|
800818e: 3710 adds r7, #16
|
|
8008190: 46bd mov sp, r7
|
|
8008192: bd80 pop {r7, pc}
|
|
|
|
08008194 <USBH_CDC_Process>:
|
|
* The function is for managing state machine for CDC data transfers
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_CDC_Process(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008194: b580 push {r7, lr}
|
|
8008196: b084 sub sp, #16
|
|
8008198: af00 add r7, sp, #0
|
|
800819a: 6078 str r0, [r7, #4]
|
|
USBH_StatusTypeDef status = USBH_BUSY;
|
|
800819c: 2301 movs r3, #1
|
|
800819e: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef req_status = USBH_OK;
|
|
80081a0: 2300 movs r3, #0
|
|
80081a2: 73bb strb r3, [r7, #14]
|
|
CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
80081a4: 687b ldr r3, [r7, #4]
|
|
80081a6: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80081aa: 69db ldr r3, [r3, #28]
|
|
80081ac: 60bb str r3, [r7, #8]
|
|
|
|
switch (CDC_Handle->state)
|
|
80081ae: 68bb ldr r3, [r7, #8]
|
|
80081b0: f893 304c ldrb.w r3, [r3, #76] @ 0x4c
|
|
80081b4: 2b04 cmp r3, #4
|
|
80081b6: d877 bhi.n 80082a8 <USBH_CDC_Process+0x114>
|
|
80081b8: a201 add r2, pc, #4 @ (adr r2, 80081c0 <USBH_CDC_Process+0x2c>)
|
|
80081ba: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
80081be: bf00 nop
|
|
80081c0: 080081d5 .word 0x080081d5
|
|
80081c4: 080081db .word 0x080081db
|
|
80081c8: 0800820b .word 0x0800820b
|
|
80081cc: 0800827f .word 0x0800827f
|
|
80081d0: 0800828d .word 0x0800828d
|
|
{
|
|
|
|
case CDC_IDLE_STATE:
|
|
status = USBH_OK;
|
|
80081d4: 2300 movs r3, #0
|
|
80081d6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
80081d8: e06d b.n 80082b6 <USBH_CDC_Process+0x122>
|
|
|
|
case CDC_SET_LINE_CODING_STATE:
|
|
req_status = SetLineCoding(phost, CDC_Handle->pUserLineCoding);
|
|
80081da: 68bb ldr r3, [r7, #8]
|
|
80081dc: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
80081de: 4619 mov r1, r3
|
|
80081e0: 6878 ldr r0, [r7, #4]
|
|
80081e2: f000 f897 bl 8008314 <SetLineCoding>
|
|
80081e6: 4603 mov r3, r0
|
|
80081e8: 73bb strb r3, [r7, #14]
|
|
|
|
if (req_status == USBH_OK)
|
|
80081ea: 7bbb ldrb r3, [r7, #14]
|
|
80081ec: 2b00 cmp r3, #0
|
|
80081ee: d104 bne.n 80081fa <USBH_CDC_Process+0x66>
|
|
{
|
|
CDC_Handle->state = CDC_GET_LAST_LINE_CODING_STATE;
|
|
80081f0: 68bb ldr r3, [r7, #8]
|
|
80081f2: 2202 movs r2, #2
|
|
80081f4: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
if (req_status != USBH_BUSY)
|
|
{
|
|
CDC_Handle->state = CDC_ERROR_STATE;
|
|
}
|
|
}
|
|
break;
|
|
80081f8: e058 b.n 80082ac <USBH_CDC_Process+0x118>
|
|
if (req_status != USBH_BUSY)
|
|
80081fa: 7bbb ldrb r3, [r7, #14]
|
|
80081fc: 2b01 cmp r3, #1
|
|
80081fe: d055 beq.n 80082ac <USBH_CDC_Process+0x118>
|
|
CDC_Handle->state = CDC_ERROR_STATE;
|
|
8008200: 68bb ldr r3, [r7, #8]
|
|
8008202: 2204 movs r2, #4
|
|
8008204: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
break;
|
|
8008208: e050 b.n 80082ac <USBH_CDC_Process+0x118>
|
|
|
|
|
|
case CDC_GET_LAST_LINE_CODING_STATE:
|
|
req_status = GetLineCoding(phost, &(CDC_Handle->LineCoding));
|
|
800820a: 68bb ldr r3, [r7, #8]
|
|
800820c: 3340 adds r3, #64 @ 0x40
|
|
800820e: 4619 mov r1, r3
|
|
8008210: 6878 ldr r0, [r7, #4]
|
|
8008212: f000 f860 bl 80082d6 <GetLineCoding>
|
|
8008216: 4603 mov r3, r0
|
|
8008218: 73bb strb r3, [r7, #14]
|
|
|
|
if (req_status == USBH_OK)
|
|
800821a: 7bbb ldrb r3, [r7, #14]
|
|
800821c: 2b00 cmp r3, #0
|
|
800821e: d126 bne.n 800826e <USBH_CDC_Process+0xda>
|
|
{
|
|
CDC_Handle->state = CDC_IDLE_STATE;
|
|
8008220: 68bb ldr r3, [r7, #8]
|
|
8008222: 2200 movs r2, #0
|
|
8008224: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
|
|
if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) &&
|
|
8008228: 68bb ldr r3, [r7, #8]
|
|
800822a: f893 2044 ldrb.w r2, [r3, #68] @ 0x44
|
|
800822e: 68bb ldr r3, [r7, #8]
|
|
8008230: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8008232: 791b ldrb r3, [r3, #4]
|
|
8008234: 429a cmp r2, r3
|
|
8008236: d13b bne.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
(CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) &&
|
|
8008238: 68bb ldr r3, [r7, #8]
|
|
800823a: f893 2046 ldrb.w r2, [r3, #70] @ 0x46
|
|
800823e: 68bb ldr r3, [r7, #8]
|
|
8008240: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8008242: 799b ldrb r3, [r3, #6]
|
|
if ((CDC_Handle->LineCoding.b.bCharFormat == CDC_Handle->pUserLineCoding->b.bCharFormat) &&
|
|
8008244: 429a cmp r2, r3
|
|
8008246: d133 bne.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
(CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) &&
|
|
8008248: 68bb ldr r3, [r7, #8]
|
|
800824a: f893 2045 ldrb.w r2, [r3, #69] @ 0x45
|
|
800824e: 68bb ldr r3, [r7, #8]
|
|
8008250: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8008252: 795b ldrb r3, [r3, #5]
|
|
(CDC_Handle->LineCoding.b.bDataBits == CDC_Handle->pUserLineCoding->b.bDataBits) &&
|
|
8008254: 429a cmp r2, r3
|
|
8008256: d12b bne.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
(CDC_Handle->LineCoding.b.dwDTERate == CDC_Handle->pUserLineCoding->b.dwDTERate))
|
|
8008258: 68bb ldr r3, [r7, #8]
|
|
800825a: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800825c: 68bb ldr r3, [r7, #8]
|
|
800825e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8008260: 681b ldr r3, [r3, #0]
|
|
(CDC_Handle->LineCoding.b.bParityType == CDC_Handle->pUserLineCoding->b.bParityType) &&
|
|
8008262: 429a cmp r2, r3
|
|
8008264: d124 bne.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
{
|
|
USBH_CDC_LineCodingChanged(phost);
|
|
8008266: 6878 ldr r0, [r7, #4]
|
|
8008268: f000 f96a bl 8008540 <USBH_CDC_LineCodingChanged>
|
|
if (req_status != USBH_BUSY)
|
|
{
|
|
CDC_Handle->state = CDC_ERROR_STATE;
|
|
}
|
|
}
|
|
break;
|
|
800826c: e020 b.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
if (req_status != USBH_BUSY)
|
|
800826e: 7bbb ldrb r3, [r7, #14]
|
|
8008270: 2b01 cmp r3, #1
|
|
8008272: d01d beq.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
CDC_Handle->state = CDC_ERROR_STATE;
|
|
8008274: 68bb ldr r3, [r7, #8]
|
|
8008276: 2204 movs r2, #4
|
|
8008278: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
break;
|
|
800827c: e018 b.n 80082b0 <USBH_CDC_Process+0x11c>
|
|
|
|
case CDC_TRANSFER_DATA:
|
|
CDC_ProcessTransmission(phost);
|
|
800827e: 6878 ldr r0, [r7, #4]
|
|
8008280: f000 f867 bl 8008352 <CDC_ProcessTransmission>
|
|
CDC_ProcessReception(phost);
|
|
8008284: 6878 ldr r0, [r7, #4]
|
|
8008286: f000 f8e6 bl 8008456 <CDC_ProcessReception>
|
|
break;
|
|
800828a: e014 b.n 80082b6 <USBH_CDC_Process+0x122>
|
|
|
|
case CDC_ERROR_STATE:
|
|
req_status = USBH_ClrFeature(phost, 0x00U);
|
|
800828c: 2100 movs r1, #0
|
|
800828e: 6878 ldr r0, [r7, #4]
|
|
8008290: f001 f8ff bl 8009492 <USBH_ClrFeature>
|
|
8008294: 4603 mov r3, r0
|
|
8008296: 73bb strb r3, [r7, #14]
|
|
|
|
if (req_status == USBH_OK)
|
|
8008298: 7bbb ldrb r3, [r7, #14]
|
|
800829a: 2b00 cmp r3, #0
|
|
800829c: d10a bne.n 80082b4 <USBH_CDC_Process+0x120>
|
|
{
|
|
/*Change the state to waiting*/
|
|
CDC_Handle->state = CDC_IDLE_STATE;
|
|
800829e: 68bb ldr r3, [r7, #8]
|
|
80082a0: 2200 movs r2, #0
|
|
80082a2: f883 204c strb.w r2, [r3, #76] @ 0x4c
|
|
}
|
|
break;
|
|
80082a6: e005 b.n 80082b4 <USBH_CDC_Process+0x120>
|
|
|
|
default:
|
|
break;
|
|
80082a8: bf00 nop
|
|
80082aa: e004 b.n 80082b6 <USBH_CDC_Process+0x122>
|
|
break;
|
|
80082ac: bf00 nop
|
|
80082ae: e002 b.n 80082b6 <USBH_CDC_Process+0x122>
|
|
break;
|
|
80082b0: bf00 nop
|
|
80082b2: e000 b.n 80082b6 <USBH_CDC_Process+0x122>
|
|
break;
|
|
80082b4: bf00 nop
|
|
|
|
}
|
|
|
|
return status;
|
|
80082b6: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80082b8: 4618 mov r0, r3
|
|
80082ba: 3710 adds r7, #16
|
|
80082bc: 46bd mov sp, r7
|
|
80082be: bd80 pop {r7, pc}
|
|
|
|
080082c0 <USBH_CDC_SOFProcess>:
|
|
* The function is for managing SOF callback
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_CDC_SOFProcess(USBH_HandleTypeDef *phost)
|
|
{
|
|
80082c0: b480 push {r7}
|
|
80082c2: b083 sub sp, #12
|
|
80082c4: af00 add r7, sp, #0
|
|
80082c6: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(phost);
|
|
|
|
return USBH_OK;
|
|
80082c8: 2300 movs r3, #0
|
|
}
|
|
80082ca: 4618 mov r0, r3
|
|
80082cc: 370c adds r7, #12
|
|
80082ce: 46bd mov sp, r7
|
|
80082d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80082d4: 4770 bx lr
|
|
|
|
080082d6 <GetLineCoding>:
|
|
* configured line coding.
|
|
* @param pdev: Selected device
|
|
* @retval USBH_StatusTypeDef : USB ctl xfer status
|
|
*/
|
|
static USBH_StatusTypeDef GetLineCoding(USBH_HandleTypeDef *phost, CDC_LineCodingTypeDef *linecoding)
|
|
{
|
|
80082d6: b580 push {r7, lr}
|
|
80082d8: b082 sub sp, #8
|
|
80082da: af00 add r7, sp, #0
|
|
80082dc: 6078 str r0, [r7, #4]
|
|
80082de: 6039 str r1, [r7, #0]
|
|
|
|
phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \
|
|
80082e0: 687b ldr r3, [r7, #4]
|
|
80082e2: 22a1 movs r2, #161 @ 0xa1
|
|
80082e4: 741a strb r2, [r3, #16]
|
|
USB_REQ_RECIPIENT_INTERFACE;
|
|
|
|
phost->Control.setup.b.bRequest = CDC_GET_LINE_CODING;
|
|
80082e6: 687b ldr r3, [r7, #4]
|
|
80082e8: 2221 movs r2, #33 @ 0x21
|
|
80082ea: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = 0U;
|
|
80082ec: 687b ldr r3, [r7, #4]
|
|
80082ee: 2200 movs r2, #0
|
|
80082f0: 825a strh r2, [r3, #18]
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
80082f2: 687b ldr r3, [r7, #4]
|
|
80082f4: 2200 movs r2, #0
|
|
80082f6: 829a strh r2, [r3, #20]
|
|
phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
|
|
80082f8: 687b ldr r3, [r7, #4]
|
|
80082fa: 2207 movs r2, #7
|
|
80082fc: 82da strh r2, [r3, #22]
|
|
|
|
return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE);
|
|
80082fe: 683b ldr r3, [r7, #0]
|
|
8008300: 2207 movs r2, #7
|
|
8008302: 4619 mov r1, r3
|
|
8008304: 6878 ldr r0, [r7, #4]
|
|
8008306: f001 fbf9 bl 8009afc <USBH_CtlReq>
|
|
800830a: 4603 mov r3, r0
|
|
}
|
|
800830c: 4618 mov r0, r3
|
|
800830e: 3708 adds r7, #8
|
|
8008310: 46bd mov sp, r7
|
|
8008312: bd80 pop {r7, pc}
|
|
|
|
08008314 <SetLineCoding>:
|
|
* @param pdev: Selected device
|
|
* @retval USBH_StatusTypeDef : USB ctl xfer status
|
|
*/
|
|
static USBH_StatusTypeDef SetLineCoding(USBH_HandleTypeDef *phost,
|
|
CDC_LineCodingTypeDef *linecoding)
|
|
{
|
|
8008314: b580 push {r7, lr}
|
|
8008316: b082 sub sp, #8
|
|
8008318: af00 add r7, sp, #0
|
|
800831a: 6078 str r0, [r7, #4]
|
|
800831c: 6039 str r1, [r7, #0]
|
|
phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS |
|
|
800831e: 687b ldr r3, [r7, #4]
|
|
8008320: 2221 movs r2, #33 @ 0x21
|
|
8008322: 741a strb r2, [r3, #16]
|
|
USB_REQ_RECIPIENT_INTERFACE;
|
|
|
|
phost->Control.setup.b.bRequest = CDC_SET_LINE_CODING;
|
|
8008324: 687b ldr r3, [r7, #4]
|
|
8008326: 2220 movs r2, #32
|
|
8008328: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = 0U;
|
|
800832a: 687b ldr r3, [r7, #4]
|
|
800832c: 2200 movs r2, #0
|
|
800832e: 825a strh r2, [r3, #18]
|
|
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
8008330: 687b ldr r3, [r7, #4]
|
|
8008332: 2200 movs r2, #0
|
|
8008334: 829a strh r2, [r3, #20]
|
|
|
|
phost->Control.setup.b.wLength.w = LINE_CODING_STRUCTURE_SIZE;
|
|
8008336: 687b ldr r3, [r7, #4]
|
|
8008338: 2207 movs r2, #7
|
|
800833a: 82da strh r2, [r3, #22]
|
|
|
|
return USBH_CtlReq(phost, linecoding->Array, LINE_CODING_STRUCTURE_SIZE);
|
|
800833c: 683b ldr r3, [r7, #0]
|
|
800833e: 2207 movs r2, #7
|
|
8008340: 4619 mov r1, r3
|
|
8008342: 6878 ldr r0, [r7, #4]
|
|
8008344: f001 fbda bl 8009afc <USBH_CtlReq>
|
|
8008348: 4603 mov r3, r0
|
|
}
|
|
800834a: 4618 mov r0, r3
|
|
800834c: 3708 adds r7, #8
|
|
800834e: 46bd mov sp, r7
|
|
8008350: bd80 pop {r7, pc}
|
|
|
|
08008352 <CDC_ProcessTransmission>:
|
|
* @brief The function is responsible for sending data to the device
|
|
* @param pdev: Selected device
|
|
* @retval None
|
|
*/
|
|
static void CDC_ProcessTransmission(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008352: b580 push {r7, lr}
|
|
8008354: b086 sub sp, #24
|
|
8008356: af02 add r7, sp, #8
|
|
8008358: 6078 str r0, [r7, #4]
|
|
CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
800835a: 687b ldr r3, [r7, #4]
|
|
800835c: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008360: 69db ldr r3, [r3, #28]
|
|
8008362: 60fb str r3, [r7, #12]
|
|
USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
|
|
8008364: 2300 movs r3, #0
|
|
8008366: 72fb strb r3, [r7, #11]
|
|
|
|
switch (CDC_Handle->data_tx_state)
|
|
8008368: 68fb ldr r3, [r7, #12]
|
|
800836a: f893 304d ldrb.w r3, [r3, #77] @ 0x4d
|
|
800836e: 2b01 cmp r3, #1
|
|
8008370: d002 beq.n 8008378 <CDC_ProcessTransmission+0x26>
|
|
8008372: 2b02 cmp r3, #2
|
|
8008374: d023 beq.n 80083be <CDC_ProcessTransmission+0x6c>
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8008376: e06a b.n 800844e <CDC_ProcessTransmission+0xfc>
|
|
if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize)
|
|
8008378: 68fb ldr r3, [r7, #12]
|
|
800837a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800837c: 68fa ldr r2, [r7, #12]
|
|
800837e: 8b12 ldrh r2, [r2, #24]
|
|
8008380: 4293 cmp r3, r2
|
|
8008382: d90b bls.n 800839c <CDC_ProcessTransmission+0x4a>
|
|
(void)USBH_BulkSendData(phost,
|
|
8008384: 68fb ldr r3, [r7, #12]
|
|
8008386: 69d9 ldr r1, [r3, #28]
|
|
8008388: 68fb ldr r3, [r7, #12]
|
|
800838a: 8b1a ldrh r2, [r3, #24]
|
|
800838c: 68fb ldr r3, [r7, #12]
|
|
800838e: 7b5b ldrb r3, [r3, #13]
|
|
8008390: 2001 movs r0, #1
|
|
8008392: 9000 str r0, [sp, #0]
|
|
8008394: 6878 ldr r0, [r7, #4]
|
|
8008396: f001 fe28 bl 8009fea <USBH_BulkSendData>
|
|
800839a: e00b b.n 80083b4 <CDC_ProcessTransmission+0x62>
|
|
(void)USBH_BulkSendData(phost,
|
|
800839c: 68fb ldr r3, [r7, #12]
|
|
800839e: 69d9 ldr r1, [r3, #28]
|
|
(uint16_t)CDC_Handle->TxDataLength,
|
|
80083a0: 68fb ldr r3, [r7, #12]
|
|
80083a2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
(void)USBH_BulkSendData(phost,
|
|
80083a4: b29a uxth r2, r3
|
|
80083a6: 68fb ldr r3, [r7, #12]
|
|
80083a8: 7b5b ldrb r3, [r3, #13]
|
|
80083aa: 2001 movs r0, #1
|
|
80083ac: 9000 str r0, [sp, #0]
|
|
80083ae: 6878 ldr r0, [r7, #4]
|
|
80083b0: f001 fe1b bl 8009fea <USBH_BulkSendData>
|
|
CDC_Handle->data_tx_state = CDC_SEND_DATA_WAIT;
|
|
80083b4: 68fb ldr r3, [r7, #12]
|
|
80083b6: 2202 movs r2, #2
|
|
80083b8: f883 204d strb.w r2, [r3, #77] @ 0x4d
|
|
break;
|
|
80083bc: e047 b.n 800844e <CDC_ProcessTransmission+0xfc>
|
|
URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.OutPipe);
|
|
80083be: 68fb ldr r3, [r7, #12]
|
|
80083c0: 7b5b ldrb r3, [r3, #13]
|
|
80083c2: 4619 mov r1, r3
|
|
80083c4: 6878 ldr r0, [r7, #4]
|
|
80083c6: f004 fc55 bl 800cc74 <USBH_LL_GetURBState>
|
|
80083ca: 4603 mov r3, r0
|
|
80083cc: 72fb strb r3, [r7, #11]
|
|
if (URB_Status == USBH_URB_DONE)
|
|
80083ce: 7afb ldrb r3, [r7, #11]
|
|
80083d0: 2b01 cmp r3, #1
|
|
80083d2: d12e bne.n 8008432 <CDC_ProcessTransmission+0xe0>
|
|
if (CDC_Handle->TxDataLength > CDC_Handle->DataItf.OutEpSize)
|
|
80083d4: 68fb ldr r3, [r7, #12]
|
|
80083d6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80083d8: 68fa ldr r2, [r7, #12]
|
|
80083da: 8b12 ldrh r2, [r2, #24]
|
|
80083dc: 4293 cmp r3, r2
|
|
80083de: d90e bls.n 80083fe <CDC_ProcessTransmission+0xac>
|
|
CDC_Handle->TxDataLength -= CDC_Handle->DataItf.OutEpSize;
|
|
80083e0: 68fb ldr r3, [r7, #12]
|
|
80083e2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80083e4: 68fa ldr r2, [r7, #12]
|
|
80083e6: 8b12 ldrh r2, [r2, #24]
|
|
80083e8: 1a9a subs r2, r3, r2
|
|
80083ea: 68fb ldr r3, [r7, #12]
|
|
80083ec: 625a str r2, [r3, #36] @ 0x24
|
|
CDC_Handle->pTxData += CDC_Handle->DataItf.OutEpSize;
|
|
80083ee: 68fb ldr r3, [r7, #12]
|
|
80083f0: 69db ldr r3, [r3, #28]
|
|
80083f2: 68fa ldr r2, [r7, #12]
|
|
80083f4: 8b12 ldrh r2, [r2, #24]
|
|
80083f6: 441a add r2, r3
|
|
80083f8: 68fb ldr r3, [r7, #12]
|
|
80083fa: 61da str r2, [r3, #28]
|
|
80083fc: e002 b.n 8008404 <CDC_ProcessTransmission+0xb2>
|
|
CDC_Handle->TxDataLength = 0U;
|
|
80083fe: 68fb ldr r3, [r7, #12]
|
|
8008400: 2200 movs r2, #0
|
|
8008402: 625a str r2, [r3, #36] @ 0x24
|
|
if (CDC_Handle->TxDataLength > 0U)
|
|
8008404: 68fb ldr r3, [r7, #12]
|
|
8008406: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8008408: 2b00 cmp r3, #0
|
|
800840a: d004 beq.n 8008416 <CDC_ProcessTransmission+0xc4>
|
|
CDC_Handle->data_tx_state = CDC_SEND_DATA;
|
|
800840c: 68fb ldr r3, [r7, #12]
|
|
800840e: 2201 movs r2, #1
|
|
8008410: f883 204d strb.w r2, [r3, #77] @ 0x4d
|
|
8008414: e006 b.n 8008424 <CDC_ProcessTransmission+0xd2>
|
|
CDC_Handle->data_tx_state = CDC_IDLE;
|
|
8008416: 68fb ldr r3, [r7, #12]
|
|
8008418: 2200 movs r2, #0
|
|
800841a: f883 204d strb.w r2, [r3, #77] @ 0x4d
|
|
USBH_CDC_TransmitCallback(phost);
|
|
800841e: 6878 ldr r0, [r7, #4]
|
|
8008420: f000 f87a bl 8008518 <USBH_CDC_TransmitCallback>
|
|
USBH_OS_PutMessage(phost, USBH_CLASS_EVENT, 0U, 0U);
|
|
8008424: 2300 movs r3, #0
|
|
8008426: 2200 movs r2, #0
|
|
8008428: 2104 movs r1, #4
|
|
800842a: 6878 ldr r0, [r7, #4]
|
|
800842c: f000 febc bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8008430: e00c b.n 800844c <CDC_ProcessTransmission+0xfa>
|
|
if (URB_Status == USBH_URB_NOTREADY)
|
|
8008432: 7afb ldrb r3, [r7, #11]
|
|
8008434: 2b02 cmp r3, #2
|
|
8008436: d109 bne.n 800844c <CDC_ProcessTransmission+0xfa>
|
|
CDC_Handle->data_tx_state = CDC_SEND_DATA;
|
|
8008438: 68fb ldr r3, [r7, #12]
|
|
800843a: 2201 movs r2, #1
|
|
800843c: f883 204d strb.w r2, [r3, #77] @ 0x4d
|
|
USBH_OS_PutMessage(phost, USBH_CLASS_EVENT, 0U, 0U);
|
|
8008440: 2300 movs r3, #0
|
|
8008442: 2200 movs r2, #0
|
|
8008444: 2104 movs r1, #4
|
|
8008446: 6878 ldr r0, [r7, #4]
|
|
8008448: f000 feae bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
800844c: bf00 nop
|
|
}
|
|
}
|
|
800844e: bf00 nop
|
|
8008450: 3710 adds r7, #16
|
|
8008452: 46bd mov sp, r7
|
|
8008454: bd80 pop {r7, pc}
|
|
|
|
08008456 <CDC_ProcessReception>:
|
|
* @param pdev: Selected device
|
|
* @retval None
|
|
*/
|
|
|
|
static void CDC_ProcessReception(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008456: b580 push {r7, lr}
|
|
8008458: b086 sub sp, #24
|
|
800845a: af00 add r7, sp, #0
|
|
800845c: 6078 str r0, [r7, #4]
|
|
CDC_HandleTypeDef *CDC_Handle = (CDC_HandleTypeDef *) phost->pActiveClass->pData;
|
|
800845e: 687b ldr r3, [r7, #4]
|
|
8008460: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008464: 69db ldr r3, [r3, #28]
|
|
8008466: 617b str r3, [r7, #20]
|
|
USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
|
|
8008468: 2300 movs r3, #0
|
|
800846a: 74fb strb r3, [r7, #19]
|
|
uint32_t length;
|
|
|
|
switch (CDC_Handle->data_rx_state)
|
|
800846c: 697b ldr r3, [r7, #20]
|
|
800846e: f893 304e ldrb.w r3, [r3, #78] @ 0x4e
|
|
8008472: 2b03 cmp r3, #3
|
|
8008474: d002 beq.n 800847c <CDC_ProcessReception+0x26>
|
|
8008476: 2b04 cmp r3, #4
|
|
8008478: d00e beq.n 8008498 <CDC_ProcessReception+0x42>
|
|
/* .. */
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
800847a: e049 b.n 8008510 <CDC_ProcessReception+0xba>
|
|
(void)USBH_BulkReceiveData(phost,
|
|
800847c: 697b ldr r3, [r7, #20]
|
|
800847e: 6a19 ldr r1, [r3, #32]
|
|
8008480: 697b ldr r3, [r7, #20]
|
|
8008482: 8b5a ldrh r2, [r3, #26]
|
|
8008484: 697b ldr r3, [r7, #20]
|
|
8008486: 7b1b ldrb r3, [r3, #12]
|
|
8008488: 6878 ldr r0, [r7, #4]
|
|
800848a: f001 fdd3 bl 800a034 <USBH_BulkReceiveData>
|
|
CDC_Handle->data_rx_state = CDC_RECEIVE_DATA_WAIT;
|
|
800848e: 697b ldr r3, [r7, #20]
|
|
8008490: 2204 movs r2, #4
|
|
8008492: f883 204e strb.w r2, [r3, #78] @ 0x4e
|
|
break;
|
|
8008496: e03b b.n 8008510 <CDC_ProcessReception+0xba>
|
|
URB_Status = USBH_LL_GetURBState(phost, CDC_Handle->DataItf.InPipe);
|
|
8008498: 697b ldr r3, [r7, #20]
|
|
800849a: 7b1b ldrb r3, [r3, #12]
|
|
800849c: 4619 mov r1, r3
|
|
800849e: 6878 ldr r0, [r7, #4]
|
|
80084a0: f004 fbe8 bl 800cc74 <USBH_LL_GetURBState>
|
|
80084a4: 4603 mov r3, r0
|
|
80084a6: 74fb strb r3, [r7, #19]
|
|
if (URB_Status == USBH_URB_DONE)
|
|
80084a8: 7cfb ldrb r3, [r7, #19]
|
|
80084aa: 2b01 cmp r3, #1
|
|
80084ac: d12f bne.n 800850e <CDC_ProcessReception+0xb8>
|
|
length = USBH_LL_GetLastXferSize(phost, CDC_Handle->DataItf.InPipe);
|
|
80084ae: 697b ldr r3, [r7, #20]
|
|
80084b0: 7b1b ldrb r3, [r3, #12]
|
|
80084b2: 4619 mov r1, r3
|
|
80084b4: 6878 ldr r0, [r7, #4]
|
|
80084b6: f004 fb5d bl 800cb74 <USBH_LL_GetLastXferSize>
|
|
80084ba: 60f8 str r0, [r7, #12]
|
|
if (((CDC_Handle->RxDataLength - length) > 0U) && (length == CDC_Handle->DataItf.InEpSize))
|
|
80084bc: 697b ldr r3, [r7, #20]
|
|
80084be: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80084c0: 68fa ldr r2, [r7, #12]
|
|
80084c2: 429a cmp r2, r3
|
|
80084c4: d016 beq.n 80084f4 <CDC_ProcessReception+0x9e>
|
|
80084c6: 697b ldr r3, [r7, #20]
|
|
80084c8: 8b5b ldrh r3, [r3, #26]
|
|
80084ca: 461a mov r2, r3
|
|
80084cc: 68fb ldr r3, [r7, #12]
|
|
80084ce: 4293 cmp r3, r2
|
|
80084d0: d110 bne.n 80084f4 <CDC_ProcessReception+0x9e>
|
|
CDC_Handle->RxDataLength -= length;
|
|
80084d2: 697b ldr r3, [r7, #20]
|
|
80084d4: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
80084d6: 68fb ldr r3, [r7, #12]
|
|
80084d8: 1ad2 subs r2, r2, r3
|
|
80084da: 697b ldr r3, [r7, #20]
|
|
80084dc: 629a str r2, [r3, #40] @ 0x28
|
|
CDC_Handle->pRxData += length;
|
|
80084de: 697b ldr r3, [r7, #20]
|
|
80084e0: 6a1a ldr r2, [r3, #32]
|
|
80084e2: 68fb ldr r3, [r7, #12]
|
|
80084e4: 441a add r2, r3
|
|
80084e6: 697b ldr r3, [r7, #20]
|
|
80084e8: 621a str r2, [r3, #32]
|
|
CDC_Handle->data_rx_state = CDC_RECEIVE_DATA;
|
|
80084ea: 697b ldr r3, [r7, #20]
|
|
80084ec: 2203 movs r2, #3
|
|
80084ee: f883 204e strb.w r2, [r3, #78] @ 0x4e
|
|
80084f2: e006 b.n 8008502 <CDC_ProcessReception+0xac>
|
|
CDC_Handle->data_rx_state = CDC_IDLE;
|
|
80084f4: 697b ldr r3, [r7, #20]
|
|
80084f6: 2200 movs r2, #0
|
|
80084f8: f883 204e strb.w r2, [r3, #78] @ 0x4e
|
|
USBH_CDC_ReceiveCallback(phost);
|
|
80084fc: 6878 ldr r0, [r7, #4]
|
|
80084fe: f000 f815 bl 800852c <USBH_CDC_ReceiveCallback>
|
|
USBH_OS_PutMessage(phost, USBH_CLASS_EVENT, 0U, 0U);
|
|
8008502: 2300 movs r3, #0
|
|
8008504: 2200 movs r2, #0
|
|
8008506: 2104 movs r1, #4
|
|
8008508: 6878 ldr r0, [r7, #4]
|
|
800850a: f000 fe4d bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
800850e: bf00 nop
|
|
}
|
|
}
|
|
8008510: bf00 nop
|
|
8008512: 3718 adds r7, #24
|
|
8008514: 46bd mov sp, r7
|
|
8008516: bd80 pop {r7, pc}
|
|
|
|
08008518 <USBH_CDC_TransmitCallback>:
|
|
* @brief The function informs user that data have been received
|
|
* @param pdev: Selected device
|
|
* @retval None
|
|
*/
|
|
__weak void USBH_CDC_TransmitCallback(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008518: b480 push {r7}
|
|
800851a: b083 sub sp, #12
|
|
800851c: af00 add r7, sp, #0
|
|
800851e: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(phost);
|
|
}
|
|
8008520: bf00 nop
|
|
8008522: 370c adds r7, #12
|
|
8008524: 46bd mov sp, r7
|
|
8008526: f85d 7b04 ldr.w r7, [sp], #4
|
|
800852a: 4770 bx lr
|
|
|
|
0800852c <USBH_CDC_ReceiveCallback>:
|
|
* @brief The function informs user that data have been sent
|
|
* @param pdev: Selected device
|
|
* @retval None
|
|
*/
|
|
__weak void USBH_CDC_ReceiveCallback(USBH_HandleTypeDef *phost)
|
|
{
|
|
800852c: b480 push {r7}
|
|
800852e: b083 sub sp, #12
|
|
8008530: af00 add r7, sp, #0
|
|
8008532: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(phost);
|
|
}
|
|
8008534: bf00 nop
|
|
8008536: 370c adds r7, #12
|
|
8008538: 46bd mov sp, r7
|
|
800853a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800853e: 4770 bx lr
|
|
|
|
08008540 <USBH_CDC_LineCodingChanged>:
|
|
* @brief The function informs user that Settings have been changed
|
|
* @param pdev: Selected device
|
|
* @retval None
|
|
*/
|
|
__weak void USBH_CDC_LineCodingChanged(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008540: b480 push {r7}
|
|
8008542: b083 sub sp, #12
|
|
8008544: af00 add r7, sp, #0
|
|
8008546: 6078 str r0, [r7, #4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(phost);
|
|
}
|
|
8008548: bf00 nop
|
|
800854a: 370c adds r7, #12
|
|
800854c: 46bd mov sp, r7
|
|
800854e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008552: 4770 bx lr
|
|
|
|
08008554 <USBH_Init>:
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Init(USBH_HandleTypeDef *phost,
|
|
void (*pUsrFunc)(USBH_HandleTypeDef *phost,
|
|
uint8_t id), uint8_t id)
|
|
{
|
|
8008554: b5b0 push {r4, r5, r7, lr}
|
|
8008556: b090 sub sp, #64 @ 0x40
|
|
8008558: af00 add r7, sp, #0
|
|
800855a: 60f8 str r0, [r7, #12]
|
|
800855c: 60b9 str r1, [r7, #8]
|
|
800855e: 4613 mov r3, r2
|
|
8008560: 71fb strb r3, [r7, #7]
|
|
/* Check whether the USB Host handle is valid */
|
|
if (phost == NULL)
|
|
8008562: 68fb ldr r3, [r7, #12]
|
|
8008564: 2b00 cmp r3, #0
|
|
8008566: d101 bne.n 800856c <USBH_Init+0x18>
|
|
{
|
|
USBH_ErrLog("Invalid Host handle");
|
|
return USBH_FAIL;
|
|
8008568: 2302 movs r3, #2
|
|
800856a: e04d b.n 8008608 <USBH_Init+0xb4>
|
|
}
|
|
|
|
/* Set DRiver ID */
|
|
phost->id = id;
|
|
800856c: 68fb ldr r3, [r7, #12]
|
|
800856e: 79fa ldrb r2, [r7, #7]
|
|
8008570: f883 23cc strb.w r2, [r3, #972] @ 0x3cc
|
|
|
|
/* Unlink class*/
|
|
phost->pActiveClass = NULL;
|
|
8008574: 68fb ldr r3, [r7, #12]
|
|
8008576: 2200 movs r2, #0
|
|
8008578: f8c3 237c str.w r2, [r3, #892] @ 0x37c
|
|
phost->ClassNumber = 0U;
|
|
800857c: 68fb ldr r3, [r7, #12]
|
|
800857e: 2200 movs r2, #0
|
|
8008580: f8c3 2380 str.w r2, [r3, #896] @ 0x380
|
|
|
|
/* Restore default states and prepare EP0 */
|
|
(void)DeInitStateMachine(phost);
|
|
8008584: 68f8 ldr r0, [r7, #12]
|
|
8008586: f000 f847 bl 8008618 <DeInitStateMachine>
|
|
|
|
/* Restore default Device connection states */
|
|
phost->device.PortEnabled = 0U;
|
|
800858a: 68fb ldr r3, [r7, #12]
|
|
800858c: 2200 movs r2, #0
|
|
800858e: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
phost->device.is_connected = 0U;
|
|
8008592: 68fb ldr r3, [r7, #12]
|
|
8008594: 2200 movs r2, #0
|
|
8008596: f883 2320 strb.w r2, [r3, #800] @ 0x320
|
|
phost->device.is_disconnected = 0U;
|
|
800859a: 68fb ldr r3, [r7, #12]
|
|
800859c: 2200 movs r2, #0
|
|
800859e: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
phost->device.is_ReEnumerated = 0U;
|
|
80085a2: 68fb ldr r3, [r7, #12]
|
|
80085a4: 2200 movs r2, #0
|
|
80085a6: f883 2322 strb.w r2, [r3, #802] @ 0x322
|
|
|
|
/* Assign User process */
|
|
if (pUsrFunc != NULL)
|
|
80085aa: 68bb ldr r3, [r7, #8]
|
|
80085ac: 2b00 cmp r3, #0
|
|
80085ae: d003 beq.n 80085b8 <USBH_Init+0x64>
|
|
{
|
|
phost->pUser = pUsrFunc;
|
|
80085b0: 68fb ldr r3, [r7, #12]
|
|
80085b2: 68ba ldr r2, [r7, #8]
|
|
80085b4: f8c3 23d4 str.w r2, [r3, #980] @ 0x3d4
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
#if (osCMSIS < 0x20000U)
|
|
|
|
/* Create USB Host Queue */
|
|
osMessageQDef(USBH_Queue, MSGQUEUE_OBJECTS, uint16_t);
|
|
80085b8: 4b15 ldr r3, [pc, #84] @ (8008610 <USBH_Init+0xbc>)
|
|
80085ba: f107 0430 add.w r4, r7, #48 @ 0x30
|
|
80085be: cb0f ldmia r3, {r0, r1, r2, r3}
|
|
80085c0: e884 000f stmia.w r4, {r0, r1, r2, r3}
|
|
phost->os_event = osMessageCreate(osMessageQ(USBH_Queue), NULL);
|
|
80085c4: f107 0330 add.w r3, r7, #48 @ 0x30
|
|
80085c8: 2100 movs r1, #0
|
|
80085ca: 4618 mov r0, r3
|
|
80085cc: f001 fe73 bl 800a2b6 <osMessageCreate>
|
|
80085d0: 4602 mov r2, r0
|
|
80085d2: 68fb ldr r3, [r7, #12]
|
|
80085d4: f8c3 23d8 str.w r2, [r3, #984] @ 0x3d8
|
|
|
|
/* Create USB Host Task */
|
|
#if defined (USBH_PROCESS_STACK_SIZE)
|
|
osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, USBH_PROCESS_STACK_SIZE);
|
|
80085d8: 4b0e ldr r3, [pc, #56] @ (8008614 <USBH_Init+0xc0>)
|
|
80085da: f107 0414 add.w r4, r7, #20
|
|
80085de: 461d mov r5, r3
|
|
80085e0: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
80085e2: c40f stmia r4!, {r0, r1, r2, r3}
|
|
80085e4: e895 0007 ldmia.w r5, {r0, r1, r2}
|
|
80085e8: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
#else
|
|
osThreadDef(USBH_Thread, USBH_Process_OS, USBH_PROCESS_PRIO, 0U, 8U * configMINIMAL_STACK_SIZE);
|
|
#endif /* defined (USBH_PROCESS_STACK_SIZE) */
|
|
|
|
phost->thread = osThreadCreate(osThread(USBH_Thread), phost);
|
|
80085ec: f107 0314 add.w r3, r7, #20
|
|
80085f0: 68f9 ldr r1, [r7, #12]
|
|
80085f2: 4618 mov r0, r3
|
|
80085f4: f001 fdff bl 800a1f6 <osThreadCreate>
|
|
80085f8: 4602 mov r2, r0
|
|
80085fa: 68fb ldr r3, [r7, #12]
|
|
80085fc: f8c3 23dc str.w r2, [r3, #988] @ 0x3dc
|
|
|
|
#endif /* (osCMSIS < 0x20000U) */
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
/* Initialize low level driver */
|
|
(void)USBH_LL_Init(phost);
|
|
8008600: 68f8 ldr r0, [r7, #12]
|
|
8008602: f004 f9f9 bl 800c9f8 <USBH_LL_Init>
|
|
|
|
return USBH_OK;
|
|
8008606: 2300 movs r3, #0
|
|
}
|
|
8008608: 4618 mov r0, r3
|
|
800860a: 3740 adds r7, #64 @ 0x40
|
|
800860c: 46bd mov sp, r7
|
|
800860e: bdb0 pop {r4, r5, r7, pc}
|
|
8008610: 0800d0cc .word 0x0800d0cc
|
|
8008614: 0800d0e8 .word 0x0800d0e8
|
|
|
|
08008618 <DeInitStateMachine>:
|
|
* De-Initialize the Host state machine.
|
|
* @param phost: Host Handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef DeInitStateMachine(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008618: b580 push {r7, lr}
|
|
800861a: b084 sub sp, #16
|
|
800861c: af00 add r7, sp, #0
|
|
800861e: 6078 str r0, [r7, #4]
|
|
uint32_t i;
|
|
|
|
/* Clear Pipes flags*/
|
|
for (i = 0U; i < USBH_MAX_PIPES_NBR; i++)
|
|
8008620: 2300 movs r3, #0
|
|
8008622: 60fb str r3, [r7, #12]
|
|
8008624: e009 b.n 800863a <DeInitStateMachine+0x22>
|
|
{
|
|
phost->Pipes[i] = 0U;
|
|
8008626: 687a ldr r2, [r7, #4]
|
|
8008628: 68fb ldr r3, [r7, #12]
|
|
800862a: 33e0 adds r3, #224 @ 0xe0
|
|
800862c: 009b lsls r3, r3, #2
|
|
800862e: 4413 add r3, r2
|
|
8008630: 2200 movs r2, #0
|
|
8008632: 605a str r2, [r3, #4]
|
|
for (i = 0U; i < USBH_MAX_PIPES_NBR; i++)
|
|
8008634: 68fb ldr r3, [r7, #12]
|
|
8008636: 3301 adds r3, #1
|
|
8008638: 60fb str r3, [r7, #12]
|
|
800863a: 68fb ldr r3, [r7, #12]
|
|
800863c: 2b0f cmp r3, #15
|
|
800863e: d9f2 bls.n 8008626 <DeInitStateMachine+0xe>
|
|
}
|
|
|
|
for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++)
|
|
8008640: 2300 movs r3, #0
|
|
8008642: 60fb str r3, [r7, #12]
|
|
8008644: e009 b.n 800865a <DeInitStateMachine+0x42>
|
|
{
|
|
phost->device.Data[i] = 0U;
|
|
8008646: 687a ldr r2, [r7, #4]
|
|
8008648: 68fb ldr r3, [r7, #12]
|
|
800864a: 4413 add r3, r2
|
|
800864c: f503 738e add.w r3, r3, #284 @ 0x11c
|
|
8008650: 2200 movs r2, #0
|
|
8008652: 701a strb r2, [r3, #0]
|
|
for (i = 0U; i < USBH_MAX_DATA_BUFFER; i++)
|
|
8008654: 68fb ldr r3, [r7, #12]
|
|
8008656: 3301 adds r3, #1
|
|
8008658: 60fb str r3, [r7, #12]
|
|
800865a: 68fb ldr r3, [r7, #12]
|
|
800865c: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8008660: d3f1 bcc.n 8008646 <DeInitStateMachine+0x2e>
|
|
}
|
|
|
|
phost->gState = HOST_IDLE;
|
|
8008662: 687b ldr r3, [r7, #4]
|
|
8008664: 2200 movs r2, #0
|
|
8008666: 701a strb r2, [r3, #0]
|
|
phost->EnumState = ENUM_IDLE;
|
|
8008668: 687b ldr r3, [r7, #4]
|
|
800866a: 2200 movs r2, #0
|
|
800866c: 705a strb r2, [r3, #1]
|
|
phost->RequestState = CMD_SEND;
|
|
800866e: 687b ldr r3, [r7, #4]
|
|
8008670: 2201 movs r2, #1
|
|
8008672: 709a strb r2, [r3, #2]
|
|
phost->Timer = 0U;
|
|
8008674: 687b ldr r3, [r7, #4]
|
|
8008676: 2200 movs r2, #0
|
|
8008678: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4
|
|
|
|
phost->Control.state = CTRL_SETUP;
|
|
800867c: 687b ldr r3, [r7, #4]
|
|
800867e: 2201 movs r2, #1
|
|
8008680: 761a strb r2, [r3, #24]
|
|
phost->Control.pipe_size = USBH_MPS_DEFAULT;
|
|
8008682: 687b ldr r3, [r7, #4]
|
|
8008684: 2240 movs r2, #64 @ 0x40
|
|
8008686: 719a strb r2, [r3, #6]
|
|
phost->Control.errorcount = 0U;
|
|
8008688: 687b ldr r3, [r7, #4]
|
|
800868a: 2200 movs r2, #0
|
|
800868c: 765a strb r2, [r3, #25]
|
|
|
|
phost->device.address = USBH_ADDRESS_DEFAULT;
|
|
800868e: 687b ldr r3, [r7, #4]
|
|
8008690: 2200 movs r2, #0
|
|
8008692: f883 231c strb.w r2, [r3, #796] @ 0x31c
|
|
phost->device.speed = (uint8_t)USBH_SPEED_FULL;
|
|
8008696: 687b ldr r3, [r7, #4]
|
|
8008698: 2201 movs r2, #1
|
|
800869a: f883 231d strb.w r2, [r3, #797] @ 0x31d
|
|
phost->device.RstCnt = 0U;
|
|
800869e: 687b ldr r3, [r7, #4]
|
|
80086a0: 2200 movs r2, #0
|
|
80086a2: f883 231f strb.w r2, [r3, #799] @ 0x31f
|
|
phost->device.EnumCnt = 0U;
|
|
80086a6: 687b ldr r3, [r7, #4]
|
|
80086a8: 2200 movs r2, #0
|
|
80086aa: f883 231e strb.w r2, [r3, #798] @ 0x31e
|
|
|
|
/* Reset the device struct */
|
|
USBH_memset(&phost->device.CfgDesc_Raw, 0, sizeof(phost->device.CfgDesc_Raw));
|
|
80086ae: 687b ldr r3, [r7, #4]
|
|
80086b0: 331c adds r3, #28
|
|
80086b2: f44f 7280 mov.w r2, #256 @ 0x100
|
|
80086b6: 2100 movs r1, #0
|
|
80086b8: 4618 mov r0, r3
|
|
80086ba: f004 fc49 bl 800cf50 <memset>
|
|
USBH_memset(&phost->device.Data, 0, sizeof(phost->device.Data));
|
|
80086be: 687b ldr r3, [r7, #4]
|
|
80086c0: f503 738e add.w r3, r3, #284 @ 0x11c
|
|
80086c4: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80086c8: 2100 movs r1, #0
|
|
80086ca: 4618 mov r0, r3
|
|
80086cc: f004 fc40 bl 800cf50 <memset>
|
|
USBH_memset(&phost->device.DevDesc, 0, sizeof(phost->device.DevDesc));
|
|
80086d0: 687b ldr r3, [r7, #4]
|
|
80086d2: f203 3326 addw r3, r3, #806 @ 0x326
|
|
80086d6: 2212 movs r2, #18
|
|
80086d8: 2100 movs r1, #0
|
|
80086da: 4618 mov r0, r3
|
|
80086dc: f004 fc38 bl 800cf50 <memset>
|
|
USBH_memset(&phost->device.CfgDesc, 0, sizeof(phost->device.CfgDesc));
|
|
80086e0: 687b ldr r3, [r7, #4]
|
|
80086e2: f503 734e add.w r3, r3, #824 @ 0x338
|
|
80086e6: 223e movs r2, #62 @ 0x3e
|
|
80086e8: 2100 movs r1, #0
|
|
80086ea: 4618 mov r0, r3
|
|
80086ec: f004 fc30 bl 800cf50 <memset>
|
|
|
|
return USBH_OK;
|
|
80086f0: 2300 movs r3, #0
|
|
}
|
|
80086f2: 4618 mov r0, r3
|
|
80086f4: 3710 adds r7, #16
|
|
80086f6: 46bd mov sp, r7
|
|
80086f8: bd80 pop {r7, pc}
|
|
|
|
080086fa <USBH_RegisterClass>:
|
|
* @param phost : Host Handle
|
|
* @param pclass: Class handle
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_RegisterClass(USBH_HandleTypeDef *phost, USBH_ClassTypeDef *pclass)
|
|
{
|
|
80086fa: b480 push {r7}
|
|
80086fc: b085 sub sp, #20
|
|
80086fe: af00 add r7, sp, #0
|
|
8008700: 6078 str r0, [r7, #4]
|
|
8008702: 6039 str r1, [r7, #0]
|
|
USBH_StatusTypeDef status = USBH_OK;
|
|
8008704: 2300 movs r3, #0
|
|
8008706: 73fb strb r3, [r7, #15]
|
|
|
|
if (pclass != NULL)
|
|
8008708: 683b ldr r3, [r7, #0]
|
|
800870a: 2b00 cmp r3, #0
|
|
800870c: d016 beq.n 800873c <USBH_RegisterClass+0x42>
|
|
{
|
|
if (phost->ClassNumber < USBH_MAX_NUM_SUPPORTED_CLASS)
|
|
800870e: 687b ldr r3, [r7, #4]
|
|
8008710: f8d3 3380 ldr.w r3, [r3, #896] @ 0x380
|
|
8008714: 2b00 cmp r3, #0
|
|
8008716: d10e bne.n 8008736 <USBH_RegisterClass+0x3c>
|
|
{
|
|
/* link the class to the USB Host handle */
|
|
phost->pClass[phost->ClassNumber++] = pclass;
|
|
8008718: 687b ldr r3, [r7, #4]
|
|
800871a: f8d3 3380 ldr.w r3, [r3, #896] @ 0x380
|
|
800871e: 1c59 adds r1, r3, #1
|
|
8008720: 687a ldr r2, [r7, #4]
|
|
8008722: f8c2 1380 str.w r1, [r2, #896] @ 0x380
|
|
8008726: 687a ldr r2, [r7, #4]
|
|
8008728: 33de adds r3, #222 @ 0xde
|
|
800872a: 6839 ldr r1, [r7, #0]
|
|
800872c: f842 1023 str.w r1, [r2, r3, lsl #2]
|
|
status = USBH_OK;
|
|
8008730: 2300 movs r3, #0
|
|
8008732: 73fb strb r3, [r7, #15]
|
|
8008734: e004 b.n 8008740 <USBH_RegisterClass+0x46>
|
|
}
|
|
else
|
|
{
|
|
USBH_ErrLog("Max Class Number reached");
|
|
status = USBH_FAIL;
|
|
8008736: 2302 movs r3, #2
|
|
8008738: 73fb strb r3, [r7, #15]
|
|
800873a: e001 b.n 8008740 <USBH_RegisterClass+0x46>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBH_ErrLog("Invalid Class handle");
|
|
status = USBH_FAIL;
|
|
800873c: 2302 movs r3, #2
|
|
800873e: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
8008740: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8008742: 4618 mov r0, r3
|
|
8008744: 3714 adds r7, #20
|
|
8008746: 46bd mov sp, r7
|
|
8008748: f85d 7b04 ldr.w r7, [sp], #4
|
|
800874c: 4770 bx lr
|
|
|
|
0800874e <USBH_SelectInterface>:
|
|
* @param phost: Host Handle
|
|
* @param interface: Interface number
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_SelectInterface(USBH_HandleTypeDef *phost, uint8_t interface)
|
|
{
|
|
800874e: b480 push {r7}
|
|
8008750: b085 sub sp, #20
|
|
8008752: af00 add r7, sp, #0
|
|
8008754: 6078 str r0, [r7, #4]
|
|
8008756: 460b mov r3, r1
|
|
8008758: 70fb strb r3, [r7, #3]
|
|
USBH_StatusTypeDef status = USBH_OK;
|
|
800875a: 2300 movs r3, #0
|
|
800875c: 73fb strb r3, [r7, #15]
|
|
|
|
if (interface < phost->device.CfgDesc.bNumInterfaces)
|
|
800875e: 687b ldr r3, [r7, #4]
|
|
8008760: f893 333c ldrb.w r3, [r3, #828] @ 0x33c
|
|
8008764: 78fa ldrb r2, [r7, #3]
|
|
8008766: 429a cmp r2, r3
|
|
8008768: d204 bcs.n 8008774 <USBH_SelectInterface+0x26>
|
|
{
|
|
phost->device.current_interface = interface;
|
|
800876a: 687b ldr r3, [r7, #4]
|
|
800876c: 78fa ldrb r2, [r7, #3]
|
|
800876e: f883 2324 strb.w r2, [r3, #804] @ 0x324
|
|
8008772: e001 b.n 8008778 <USBH_SelectInterface+0x2a>
|
|
USBH_UsrLog("Protocol : %xh", phost->device.CfgDesc.Itf_Desc[interface].bInterfaceProtocol);
|
|
}
|
|
else
|
|
{
|
|
USBH_ErrLog("Cannot Select This Interface.");
|
|
status = USBH_FAIL;
|
|
8008774: 2302 movs r3, #2
|
|
8008776: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
8008778: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800877a: 4618 mov r0, r3
|
|
800877c: 3714 adds r7, #20
|
|
800877e: 46bd mov sp, r7
|
|
8008780: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008784: 4770 bx lr
|
|
|
|
08008786 <USBH_FindInterface>:
|
|
* @param Protocol: Protocol code
|
|
* @retval interface index in the configuration structure
|
|
* @note : (1)interface index 0xFF means interface index not found
|
|
*/
|
|
uint8_t USBH_FindInterface(USBH_HandleTypeDef *phost, uint8_t Class, uint8_t SubClass, uint8_t Protocol)
|
|
{
|
|
8008786: b480 push {r7}
|
|
8008788: b087 sub sp, #28
|
|
800878a: af00 add r7, sp, #0
|
|
800878c: 6078 str r0, [r7, #4]
|
|
800878e: 4608 mov r0, r1
|
|
8008790: 4611 mov r1, r2
|
|
8008792: 461a mov r2, r3
|
|
8008794: 4603 mov r3, r0
|
|
8008796: 70fb strb r3, [r7, #3]
|
|
8008798: 460b mov r3, r1
|
|
800879a: 70bb strb r3, [r7, #2]
|
|
800879c: 4613 mov r3, r2
|
|
800879e: 707b strb r3, [r7, #1]
|
|
USBH_InterfaceDescTypeDef *pif;
|
|
USBH_CfgDescTypeDef *pcfg;
|
|
uint8_t if_ix = 0U;
|
|
80087a0: 2300 movs r3, #0
|
|
80087a2: 75fb strb r3, [r7, #23]
|
|
|
|
pif = (USBH_InterfaceDescTypeDef *)NULL;
|
|
80087a4: 2300 movs r3, #0
|
|
80087a6: 613b str r3, [r7, #16]
|
|
pcfg = &phost->device.CfgDesc;
|
|
80087a8: 687b ldr r3, [r7, #4]
|
|
80087aa: f503 734e add.w r3, r3, #824 @ 0x338
|
|
80087ae: 60fb str r3, [r7, #12]
|
|
|
|
while (if_ix < USBH_MAX_NUM_INTERFACES)
|
|
80087b0: e025 b.n 80087fe <USBH_FindInterface+0x78>
|
|
{
|
|
pif = &pcfg->Itf_Desc[if_ix];
|
|
80087b2: 7dfb ldrb r3, [r7, #23]
|
|
80087b4: 221a movs r2, #26
|
|
80087b6: fb02 f303 mul.w r3, r2, r3
|
|
80087ba: 3308 adds r3, #8
|
|
80087bc: 68fa ldr r2, [r7, #12]
|
|
80087be: 4413 add r3, r2
|
|
80087c0: 3302 adds r3, #2
|
|
80087c2: 613b str r3, [r7, #16]
|
|
if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) &&
|
|
80087c4: 693b ldr r3, [r7, #16]
|
|
80087c6: 795b ldrb r3, [r3, #5]
|
|
80087c8: 78fa ldrb r2, [r7, #3]
|
|
80087ca: 429a cmp r2, r3
|
|
80087cc: d002 beq.n 80087d4 <USBH_FindInterface+0x4e>
|
|
80087ce: 78fb ldrb r3, [r7, #3]
|
|
80087d0: 2bff cmp r3, #255 @ 0xff
|
|
80087d2: d111 bne.n 80087f8 <USBH_FindInterface+0x72>
|
|
((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) &&
|
|
80087d4: 693b ldr r3, [r7, #16]
|
|
80087d6: 799b ldrb r3, [r3, #6]
|
|
if (((pif->bInterfaceClass == Class) || (Class == 0xFFU)) &&
|
|
80087d8: 78ba ldrb r2, [r7, #2]
|
|
80087da: 429a cmp r2, r3
|
|
80087dc: d002 beq.n 80087e4 <USBH_FindInterface+0x5e>
|
|
((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) &&
|
|
80087de: 78bb ldrb r3, [r7, #2]
|
|
80087e0: 2bff cmp r3, #255 @ 0xff
|
|
80087e2: d109 bne.n 80087f8 <USBH_FindInterface+0x72>
|
|
((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU)))
|
|
80087e4: 693b ldr r3, [r7, #16]
|
|
80087e6: 79db ldrb r3, [r3, #7]
|
|
((pif->bInterfaceSubClass == SubClass) || (SubClass == 0xFFU)) &&
|
|
80087e8: 787a ldrb r2, [r7, #1]
|
|
80087ea: 429a cmp r2, r3
|
|
80087ec: d002 beq.n 80087f4 <USBH_FindInterface+0x6e>
|
|
((pif->bInterfaceProtocol == Protocol) || (Protocol == 0xFFU)))
|
|
80087ee: 787b ldrb r3, [r7, #1]
|
|
80087f0: 2bff cmp r3, #255 @ 0xff
|
|
80087f2: d101 bne.n 80087f8 <USBH_FindInterface+0x72>
|
|
{
|
|
return if_ix;
|
|
80087f4: 7dfb ldrb r3, [r7, #23]
|
|
80087f6: e006 b.n 8008806 <USBH_FindInterface+0x80>
|
|
}
|
|
if_ix++;
|
|
80087f8: 7dfb ldrb r3, [r7, #23]
|
|
80087fa: 3301 adds r3, #1
|
|
80087fc: 75fb strb r3, [r7, #23]
|
|
while (if_ix < USBH_MAX_NUM_INTERFACES)
|
|
80087fe: 7dfb ldrb r3, [r7, #23]
|
|
8008800: 2b01 cmp r3, #1
|
|
8008802: d9d6 bls.n 80087b2 <USBH_FindInterface+0x2c>
|
|
}
|
|
return 0xFFU;
|
|
8008804: 23ff movs r3, #255 @ 0xff
|
|
}
|
|
8008806: 4618 mov r0, r3
|
|
8008808: 371c adds r7, #28
|
|
800880a: 46bd mov sp, r7
|
|
800880c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8008810: 4770 bx lr
|
|
|
|
08008812 <USBH_Start>:
|
|
* Start the USB Host Core.
|
|
* @param phost: Host Handle
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Start(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008812: b580 push {r7, lr}
|
|
8008814: b082 sub sp, #8
|
|
8008816: af00 add r7, sp, #0
|
|
8008818: 6078 str r0, [r7, #4]
|
|
/* Start the low level driver */
|
|
(void)USBH_LL_Start(phost);
|
|
800881a: 6878 ldr r0, [r7, #4]
|
|
800881c: f004 f932 bl 800ca84 <USBH_LL_Start>
|
|
|
|
/* Activate VBUS on the port */
|
|
(void)USBH_LL_DriverVBUS(phost, TRUE);
|
|
8008820: 2101 movs r1, #1
|
|
8008822: 6878 ldr r0, [r7, #4]
|
|
8008824: f004 fa39 bl 800cc9a <USBH_LL_DriverVBUS>
|
|
|
|
return USBH_OK;
|
|
8008828: 2300 movs r3, #0
|
|
}
|
|
800882a: 4618 mov r0, r3
|
|
800882c: 3708 adds r7, #8
|
|
800882e: 46bd mov sp, r7
|
|
8008830: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08008834 <USBH_Process>:
|
|
* Background process of the USB Core.
|
|
* @param phost: Host Handle
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Process(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008834: b580 push {r7, lr}
|
|
8008836: b088 sub sp, #32
|
|
8008838: af04 add r7, sp, #16
|
|
800883a: 6078 str r0, [r7, #4]
|
|
__IO USBH_StatusTypeDef status = USBH_FAIL;
|
|
800883c: 2302 movs r3, #2
|
|
800883e: 73bb strb r3, [r7, #14]
|
|
uint8_t idx = 0U;
|
|
8008840: 2300 movs r3, #0
|
|
8008842: 73fb strb r3, [r7, #15]
|
|
|
|
/* check for Host pending port disconnect event */
|
|
if (phost->device.is_disconnected == 1U)
|
|
8008844: 687b ldr r3, [r7, #4]
|
|
8008846: f893 3321 ldrb.w r3, [r3, #801] @ 0x321
|
|
800884a: b2db uxtb r3, r3
|
|
800884c: 2b01 cmp r3, #1
|
|
800884e: d102 bne.n 8008856 <USBH_Process+0x22>
|
|
{
|
|
phost->gState = HOST_DEV_DISCONNECTED;
|
|
8008850: 687b ldr r3, [r7, #4]
|
|
8008852: 2203 movs r2, #3
|
|
8008854: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
switch (phost->gState)
|
|
8008856: 687b ldr r3, [r7, #4]
|
|
8008858: 781b ldrb r3, [r3, #0]
|
|
800885a: b2db uxtb r3, r3
|
|
800885c: 2b0b cmp r3, #11
|
|
800885e: f200 81f5 bhi.w 8008c4c <USBH_Process+0x418>
|
|
8008862: a201 add r2, pc, #4 @ (adr r2, 8008868 <USBH_Process+0x34>)
|
|
8008864: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008868: 08008899 .word 0x08008899
|
|
800886c: 080088d7 .word 0x080088d7
|
|
8008870: 0800894d .word 0x0800894d
|
|
8008874: 08008bdb .word 0x08008bdb
|
|
8008878: 08008c4d .word 0x08008c4d
|
|
800887c: 080089f9 .word 0x080089f9
|
|
8008880: 08008b75 .word 0x08008b75
|
|
8008884: 08008a3b .word 0x08008a3b
|
|
8008888: 08008a67 .word 0x08008a67
|
|
800888c: 08008a8f .word 0x08008a8f
|
|
8008890: 08008add .word 0x08008add
|
|
8008894: 08008bc3 .word 0x08008bc3
|
|
{
|
|
case HOST_IDLE :
|
|
|
|
if ((phost->device.is_connected) != 0U)
|
|
8008898: 687b ldr r3, [r7, #4]
|
|
800889a: f893 3320 ldrb.w r3, [r3, #800] @ 0x320
|
|
800889e: b2db uxtb r3, r3
|
|
80088a0: 2b00 cmp r3, #0
|
|
80088a2: f000 81d5 beq.w 8008c50 <USBH_Process+0x41c>
|
|
{
|
|
USBH_UsrLog("USB Device Connected");
|
|
|
|
/* Wait for 200 ms after connection */
|
|
phost->gState = HOST_DEV_WAIT_FOR_ATTACHMENT;
|
|
80088a6: 687b ldr r3, [r7, #4]
|
|
80088a8: 2201 movs r2, #1
|
|
80088aa: 701a strb r2, [r3, #0]
|
|
USBH_Delay(200U);
|
|
80088ac: 20c8 movs r0, #200 @ 0xc8
|
|
80088ae: f004 fa3e bl 800cd2e <USBH_Delay>
|
|
(void)USBH_LL_ResetPort(phost);
|
|
80088b2: 6878 ldr r0, [r7, #4]
|
|
80088b4: f004 f943 bl 800cb3e <USBH_LL_ResetPort>
|
|
|
|
/* Make sure to start with Default address */
|
|
phost->device.address = USBH_ADDRESS_DEFAULT;
|
|
80088b8: 687b ldr r3, [r7, #4]
|
|
80088ba: 2200 movs r2, #0
|
|
80088bc: f883 231c strb.w r2, [r3, #796] @ 0x31c
|
|
phost->Timeout = 0U;
|
|
80088c0: 687b ldr r3, [r7, #4]
|
|
80088c2: 2200 movs r2, #0
|
|
80088c4: f8c3 23c8 str.w r2, [r3, #968] @ 0x3c8
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
80088c8: 2300 movs r3, #0
|
|
80088ca: 2200 movs r2, #0
|
|
80088cc: 2101 movs r1, #1
|
|
80088ce: 6878 ldr r0, [r7, #4]
|
|
80088d0: f000 fc6a bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
break;
|
|
80088d4: e1bc b.n 8008c50 <USBH_Process+0x41c>
|
|
|
|
case HOST_DEV_WAIT_FOR_ATTACHMENT: /* Wait for Port Enabled */
|
|
|
|
if (phost->device.PortEnabled == 1U)
|
|
80088d6: 687b ldr r3, [r7, #4]
|
|
80088d8: f893 3323 ldrb.w r3, [r3, #803] @ 0x323
|
|
80088dc: b2db uxtb r3, r3
|
|
80088de: 2b01 cmp r3, #1
|
|
80088e0: d107 bne.n 80088f2 <USBH_Process+0xbe>
|
|
{
|
|
USBH_UsrLog("USB Device Reset Completed");
|
|
phost->device.RstCnt = 0U;
|
|
80088e2: 687b ldr r3, [r7, #4]
|
|
80088e4: 2200 movs r2, #0
|
|
80088e6: f883 231f strb.w r2, [r3, #799] @ 0x31f
|
|
phost->gState = HOST_DEV_ATTACHED;
|
|
80088ea: 687b ldr r3, [r7, #4]
|
|
80088ec: 2202 movs r2, #2
|
|
80088ee: 701a strb r2, [r3, #0]
|
|
80088f0: e025 b.n 800893e <USBH_Process+0x10a>
|
|
}
|
|
else
|
|
{
|
|
if (phost->Timeout > USBH_DEV_RESET_TIMEOUT)
|
|
80088f2: 687b ldr r3, [r7, #4]
|
|
80088f4: f8d3 33c8 ldr.w r3, [r3, #968] @ 0x3c8
|
|
80088f8: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
80088fc: d914 bls.n 8008928 <USBH_Process+0xf4>
|
|
{
|
|
phost->device.RstCnt++;
|
|
80088fe: 687b ldr r3, [r7, #4]
|
|
8008900: f893 331f ldrb.w r3, [r3, #799] @ 0x31f
|
|
8008904: 3301 adds r3, #1
|
|
8008906: b2da uxtb r2, r3
|
|
8008908: 687b ldr r3, [r7, #4]
|
|
800890a: f883 231f strb.w r2, [r3, #799] @ 0x31f
|
|
if (phost->device.RstCnt > 3U)
|
|
800890e: 687b ldr r3, [r7, #4]
|
|
8008910: f893 331f ldrb.w r3, [r3, #799] @ 0x31f
|
|
8008914: 2b03 cmp r3, #3
|
|
8008916: d903 bls.n 8008920 <USBH_Process+0xec>
|
|
{
|
|
/* Buggy Device can't complete reset */
|
|
USBH_UsrLog("USB Reset Failed, Please unplug the Device.");
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008918: 687b ldr r3, [r7, #4]
|
|
800891a: 220d movs r2, #13
|
|
800891c: 701a strb r2, [r3, #0]
|
|
800891e: e00e b.n 800893e <USBH_Process+0x10a>
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_IDLE;
|
|
8008920: 687b ldr r3, [r7, #4]
|
|
8008922: 2200 movs r2, #0
|
|
8008924: 701a strb r2, [r3, #0]
|
|
8008926: e00a b.n 800893e <USBH_Process+0x10a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
phost->Timeout += 10U;
|
|
8008928: 687b ldr r3, [r7, #4]
|
|
800892a: f8d3 33c8 ldr.w r3, [r3, #968] @ 0x3c8
|
|
800892e: f103 020a add.w r2, r3, #10
|
|
8008932: 687b ldr r3, [r7, #4]
|
|
8008934: f8c3 23c8 str.w r2, [r3, #968] @ 0x3c8
|
|
USBH_Delay(10U);
|
|
8008938: 200a movs r0, #10
|
|
800893a: f004 f9f8 bl 800cd2e <USBH_Delay>
|
|
}
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
800893e: 2300 movs r3, #0
|
|
8008940: 2200 movs r2, #0
|
|
8008942: 2101 movs r1, #1
|
|
8008944: 6878 ldr r0, [r7, #4]
|
|
8008946: f000 fc2f bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
800894a: e188 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_DEV_ATTACHED :
|
|
|
|
if (phost->pUser != NULL)
|
|
800894c: 687b ldr r3, [r7, #4]
|
|
800894e: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008952: 2b00 cmp r3, #0
|
|
8008954: d005 beq.n 8008962 <USBH_Process+0x12e>
|
|
{
|
|
phost->pUser(phost, HOST_USER_CONNECTION);
|
|
8008956: 687b ldr r3, [r7, #4]
|
|
8008958: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
800895c: 2104 movs r1, #4
|
|
800895e: 6878 ldr r0, [r7, #4]
|
|
8008960: 4798 blx r3
|
|
}
|
|
|
|
/* Wait for 100 ms after Reset */
|
|
USBH_Delay(100U);
|
|
8008962: 2064 movs r0, #100 @ 0x64
|
|
8008964: f004 f9e3 bl 800cd2e <USBH_Delay>
|
|
|
|
phost->device.speed = (uint8_t)USBH_LL_GetSpeed(phost);
|
|
8008968: 6878 ldr r0, [r7, #4]
|
|
800896a: f004 f8c1 bl 800caf0 <USBH_LL_GetSpeed>
|
|
800896e: 4603 mov r3, r0
|
|
8008970: 461a mov r2, r3
|
|
8008972: 687b ldr r3, [r7, #4]
|
|
8008974: f883 231d strb.w r2, [r3, #797] @ 0x31d
|
|
|
|
#if defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U)
|
|
phost->NakTimeout = USBH_NAK_SOF_COUNT;
|
|
#endif /* defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U) */
|
|
|
|
phost->gState = HOST_ENUMERATION;
|
|
8008978: 687b ldr r3, [r7, #4]
|
|
800897a: 2205 movs r2, #5
|
|
800897c: 701a strb r2, [r3, #0]
|
|
|
|
phost->Control.pipe_out = USBH_AllocPipe(phost, 0x00U);
|
|
800897e: 2100 movs r1, #0
|
|
8008980: 6878 ldr r0, [r7, #4]
|
|
8008982: f001 fba4 bl 800a0ce <USBH_AllocPipe>
|
|
8008986: 4603 mov r3, r0
|
|
8008988: 461a mov r2, r3
|
|
800898a: 687b ldr r3, [r7, #4]
|
|
800898c: 715a strb r2, [r3, #5]
|
|
phost->Control.pipe_in = USBH_AllocPipe(phost, 0x80U);
|
|
800898e: 2180 movs r1, #128 @ 0x80
|
|
8008990: 6878 ldr r0, [r7, #4]
|
|
8008992: f001 fb9c bl 800a0ce <USBH_AllocPipe>
|
|
8008996: 4603 mov r3, r0
|
|
8008998: 461a mov r2, r3
|
|
800899a: 687b ldr r3, [r7, #4]
|
|
800899c: 711a strb r2, [r3, #4]
|
|
|
|
/* Open Control pipes */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U,
|
|
800899e: 687b ldr r3, [r7, #4]
|
|
80089a0: 7919 ldrb r1, [r3, #4]
|
|
80089a2: 687b ldr r3, [r7, #4]
|
|
80089a4: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
80089a8: 687b ldr r3, [r7, #4]
|
|
80089aa: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.address, phost->device.speed,
|
|
USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size);
|
|
80089ae: 687a ldr r2, [r7, #4]
|
|
80089b0: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U,
|
|
80089b2: 9202 str r2, [sp, #8]
|
|
80089b4: 2200 movs r2, #0
|
|
80089b6: 9201 str r2, [sp, #4]
|
|
80089b8: 9300 str r3, [sp, #0]
|
|
80089ba: 4603 mov r3, r0
|
|
80089bc: 2280 movs r2, #128 @ 0x80
|
|
80089be: 6878 ldr r0, [r7, #4]
|
|
80089c0: f001 fb56 bl 800a070 <USBH_OpenPipe>
|
|
|
|
/* Open Control pipes */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U,
|
|
80089c4: 687b ldr r3, [r7, #4]
|
|
80089c6: 7959 ldrb r1, [r3, #5]
|
|
80089c8: 687b ldr r3, [r7, #4]
|
|
80089ca: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
80089ce: 687b ldr r3, [r7, #4]
|
|
80089d0: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.address, phost->device.speed,
|
|
USBH_EP_CONTROL, (uint16_t)phost->Control.pipe_size);
|
|
80089d4: 687a ldr r2, [r7, #4]
|
|
80089d6: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U,
|
|
80089d8: 9202 str r2, [sp, #8]
|
|
80089da: 2200 movs r2, #0
|
|
80089dc: 9201 str r2, [sp, #4]
|
|
80089de: 9300 str r3, [sp, #0]
|
|
80089e0: 4603 mov r3, r0
|
|
80089e2: 2200 movs r2, #0
|
|
80089e4: 6878 ldr r0, [r7, #4]
|
|
80089e6: f001 fb43 bl 800a070 <USBH_OpenPipe>
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
80089ea: 2300 movs r3, #0
|
|
80089ec: 2200 movs r2, #0
|
|
80089ee: 2101 movs r1, #1
|
|
80089f0: 6878 ldr r0, [r7, #4]
|
|
80089f2: f000 fbd9 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
80089f6: e132 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_ENUMERATION:
|
|
/* Check for enumeration status */
|
|
status = USBH_HandleEnum(phost);
|
|
80089f8: 6878 ldr r0, [r7, #4]
|
|
80089fa: f000 f935 bl 8008c68 <USBH_HandleEnum>
|
|
80089fe: 4603 mov r3, r0
|
|
8008a00: 73bb strb r3, [r7, #14]
|
|
if (status == USBH_OK)
|
|
8008a02: 7bbb ldrb r3, [r7, #14]
|
|
8008a04: b2db uxtb r3, r3
|
|
8008a06: 2b00 cmp r3, #0
|
|
8008a08: f040 8124 bne.w 8008c54 <USBH_Process+0x420>
|
|
{
|
|
/* The function shall return USBH_OK when full enumeration is complete */
|
|
USBH_UsrLog("Enumeration done.");
|
|
|
|
phost->device.current_interface = 0U;
|
|
8008a0c: 687b ldr r3, [r7, #4]
|
|
8008a0e: 2200 movs r2, #0
|
|
8008a10: f883 2324 strb.w r2, [r3, #804] @ 0x324
|
|
|
|
if (phost->device.DevDesc.bNumConfigurations == 1U)
|
|
8008a14: 687b ldr r3, [r7, #4]
|
|
8008a16: f893 3337 ldrb.w r3, [r3, #823] @ 0x337
|
|
8008a1a: 2b01 cmp r3, #1
|
|
8008a1c: d103 bne.n 8008a26 <USBH_Process+0x1f2>
|
|
{
|
|
USBH_UsrLog("This device has only 1 configuration.");
|
|
phost->gState = HOST_SET_CONFIGURATION;
|
|
8008a1e: 687b ldr r3, [r7, #4]
|
|
8008a20: 2208 movs r2, #8
|
|
8008a22: 701a strb r2, [r3, #0]
|
|
8008a24: e002 b.n 8008a2c <USBH_Process+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_INPUT;
|
|
8008a26: 687b ldr r3, [r7, #4]
|
|
8008a28: 2207 movs r2, #7
|
|
8008a2a: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008a2c: 2300 movs r3, #0
|
|
8008a2e: 2200 movs r2, #0
|
|
8008a30: 2105 movs r1, #5
|
|
8008a32: 6878 ldr r0, [r7, #4]
|
|
8008a34: f000 fbb8 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
break;
|
|
8008a38: e10c b.n 8008c54 <USBH_Process+0x420>
|
|
|
|
case HOST_INPUT:
|
|
{
|
|
/* user callback for end of device basic enumeration */
|
|
if (phost->pUser != NULL)
|
|
8008a3a: 687b ldr r3, [r7, #4]
|
|
8008a3c: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008a40: 2b00 cmp r3, #0
|
|
8008a42: f000 8109 beq.w 8008c58 <USBH_Process+0x424>
|
|
{
|
|
phost->pUser(phost, HOST_USER_SELECT_CONFIGURATION);
|
|
8008a46: 687b ldr r3, [r7, #4]
|
|
8008a48: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008a4c: 2101 movs r1, #1
|
|
8008a4e: 6878 ldr r0, [r7, #4]
|
|
8008a50: 4798 blx r3
|
|
phost->gState = HOST_SET_CONFIGURATION;
|
|
8008a52: 687b ldr r3, [r7, #4]
|
|
8008a54: 2208 movs r2, #8
|
|
8008a56: 701a strb r2, [r3, #0]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008a58: 2300 movs r3, #0
|
|
8008a5a: 2200 movs r2, #0
|
|
8008a5c: 2105 movs r1, #5
|
|
8008a5e: 6878 ldr r0, [r7, #4]
|
|
8008a60: f000 fba2 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8008a64: e0f8 b.n 8008c58 <USBH_Process+0x424>
|
|
|
|
case HOST_SET_CONFIGURATION:
|
|
/* set configuration */
|
|
if (USBH_SetCfg(phost, (uint16_t)phost->device.CfgDesc.bConfigurationValue) == USBH_OK)
|
|
8008a66: 687b ldr r3, [r7, #4]
|
|
8008a68: f893 333d ldrb.w r3, [r3, #829] @ 0x33d
|
|
8008a6c: 4619 mov r1, r3
|
|
8008a6e: 6878 ldr r0, [r7, #4]
|
|
8008a70: f000 fcc8 bl 8009404 <USBH_SetCfg>
|
|
8008a74: 4603 mov r3, r0
|
|
8008a76: 2b00 cmp r3, #0
|
|
8008a78: d102 bne.n 8008a80 <USBH_Process+0x24c>
|
|
{
|
|
phost->gState = HOST_SET_WAKEUP_FEATURE;
|
|
8008a7a: 687b ldr r3, [r7, #4]
|
|
8008a7c: 2209 movs r2, #9
|
|
8008a7e: 701a strb r2, [r3, #0]
|
|
USBH_UsrLog("Default configuration set.");
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8008a80: 2300 movs r3, #0
|
|
8008a82: 2200 movs r2, #0
|
|
8008a84: 2101 movs r1, #1
|
|
8008a86: 6878 ldr r0, [r7, #4]
|
|
8008a88: f000 fb8e bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
8008a8c: e0e7 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_SET_WAKEUP_FEATURE:
|
|
|
|
if (((phost->device.CfgDesc.bmAttributes) & (1U << 5)) != 0U)
|
|
8008a8e: 687b ldr r3, [r7, #4]
|
|
8008a90: f893 333f ldrb.w r3, [r3, #831] @ 0x33f
|
|
8008a94: f003 0320 and.w r3, r3, #32
|
|
8008a98: 2b00 cmp r3, #0
|
|
8008a9a: d015 beq.n 8008ac8 <USBH_Process+0x294>
|
|
{
|
|
status = USBH_SetFeature(phost, FEATURE_SELECTOR_REMOTEWAKEUP);
|
|
8008a9c: 2101 movs r1, #1
|
|
8008a9e: 6878 ldr r0, [r7, #4]
|
|
8008aa0: f000 fcd3 bl 800944a <USBH_SetFeature>
|
|
8008aa4: 4603 mov r3, r0
|
|
8008aa6: 73bb strb r3, [r7, #14]
|
|
|
|
if (status == USBH_OK)
|
|
8008aa8: 7bbb ldrb r3, [r7, #14]
|
|
8008aaa: b2db uxtb r3, r3
|
|
8008aac: 2b00 cmp r3, #0
|
|
8008aae: d103 bne.n 8008ab8 <USBH_Process+0x284>
|
|
{
|
|
USBH_UsrLog("Device remote wakeup enabled");
|
|
phost->gState = HOST_CHECK_CLASS;
|
|
8008ab0: 687b ldr r3, [r7, #4]
|
|
8008ab2: 220a movs r2, #10
|
|
8008ab4: 701a strb r2, [r3, #0]
|
|
8008ab6: e00a b.n 8008ace <USBH_Process+0x29a>
|
|
}
|
|
else if (status == USBH_NOT_SUPPORTED)
|
|
8008ab8: 7bbb ldrb r3, [r7, #14]
|
|
8008aba: b2db uxtb r3, r3
|
|
8008abc: 2b03 cmp r3, #3
|
|
8008abe: d106 bne.n 8008ace <USBH_Process+0x29a>
|
|
{
|
|
USBH_UsrLog("Remote wakeup not supported by the device");
|
|
phost->gState = HOST_CHECK_CLASS;
|
|
8008ac0: 687b ldr r3, [r7, #4]
|
|
8008ac2: 220a movs r2, #10
|
|
8008ac4: 701a strb r2, [r3, #0]
|
|
8008ac6: e002 b.n 8008ace <USBH_Process+0x29a>
|
|
/* .. */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_CHECK_CLASS;
|
|
8008ac8: 687b ldr r3, [r7, #4]
|
|
8008aca: 220a movs r2, #10
|
|
8008acc: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8008ace: 2300 movs r3, #0
|
|
8008ad0: 2200 movs r2, #0
|
|
8008ad2: 2101 movs r1, #1
|
|
8008ad4: 6878 ldr r0, [r7, #4]
|
|
8008ad6: f000 fb67 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
8008ada: e0c0 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_CHECK_CLASS:
|
|
|
|
if (phost->ClassNumber == 0U)
|
|
8008adc: 687b ldr r3, [r7, #4]
|
|
8008ade: f8d3 3380 ldr.w r3, [r3, #896] @ 0x380
|
|
8008ae2: 2b00 cmp r3, #0
|
|
8008ae4: d03f beq.n 8008b66 <USBH_Process+0x332>
|
|
{
|
|
USBH_UsrLog("No Class has been registered.");
|
|
}
|
|
else
|
|
{
|
|
phost->pActiveClass = NULL;
|
|
8008ae6: 687b ldr r3, [r7, #4]
|
|
8008ae8: 2200 movs r2, #0
|
|
8008aea: f8c3 237c str.w r2, [r3, #892] @ 0x37c
|
|
|
|
for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++)
|
|
8008aee: 2300 movs r3, #0
|
|
8008af0: 73fb strb r3, [r7, #15]
|
|
8008af2: e016 b.n 8008b22 <USBH_Process+0x2ee>
|
|
{
|
|
if (phost->pClass[idx]->ClassCode == phost->device.CfgDesc.Itf_Desc[0].bInterfaceClass)
|
|
8008af4: 7bfa ldrb r2, [r7, #15]
|
|
8008af6: 687b ldr r3, [r7, #4]
|
|
8008af8: 32de adds r2, #222 @ 0xde
|
|
8008afa: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8008afe: 791a ldrb r2, [r3, #4]
|
|
8008b00: 687b ldr r3, [r7, #4]
|
|
8008b02: f893 3347 ldrb.w r3, [r3, #839] @ 0x347
|
|
8008b06: 429a cmp r2, r3
|
|
8008b08: d108 bne.n 8008b1c <USBH_Process+0x2e8>
|
|
{
|
|
phost->pActiveClass = phost->pClass[idx];
|
|
8008b0a: 7bfa ldrb r2, [r7, #15]
|
|
8008b0c: 687b ldr r3, [r7, #4]
|
|
8008b0e: 32de adds r2, #222 @ 0xde
|
|
8008b10: f853 2022 ldr.w r2, [r3, r2, lsl #2]
|
|
8008b14: 687b ldr r3, [r7, #4]
|
|
8008b16: f8c3 237c str.w r2, [r3, #892] @ 0x37c
|
|
break;
|
|
8008b1a: e005 b.n 8008b28 <USBH_Process+0x2f4>
|
|
for (idx = 0U; idx < USBH_MAX_NUM_SUPPORTED_CLASS; idx++)
|
|
8008b1c: 7bfb ldrb r3, [r7, #15]
|
|
8008b1e: 3301 adds r3, #1
|
|
8008b20: 73fb strb r3, [r7, #15]
|
|
8008b22: 7bfb ldrb r3, [r7, #15]
|
|
8008b24: 2b00 cmp r3, #0
|
|
8008b26: d0e5 beq.n 8008af4 <USBH_Process+0x2c0>
|
|
}
|
|
}
|
|
|
|
if (phost->pActiveClass != NULL)
|
|
8008b28: 687b ldr r3, [r7, #4]
|
|
8008b2a: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008b2e: 2b00 cmp r3, #0
|
|
8008b30: d016 beq.n 8008b60 <USBH_Process+0x32c>
|
|
{
|
|
if (phost->pActiveClass->Init(phost) == USBH_OK)
|
|
8008b32: 687b ldr r3, [r7, #4]
|
|
8008b34: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008b38: 689b ldr r3, [r3, #8]
|
|
8008b3a: 6878 ldr r0, [r7, #4]
|
|
8008b3c: 4798 blx r3
|
|
8008b3e: 4603 mov r3, r0
|
|
8008b40: 2b00 cmp r3, #0
|
|
8008b42: d109 bne.n 8008b58 <USBH_Process+0x324>
|
|
{
|
|
phost->gState = HOST_CLASS_REQUEST;
|
|
8008b44: 687b ldr r3, [r7, #4]
|
|
8008b46: 2206 movs r2, #6
|
|
8008b48: 701a strb r2, [r3, #0]
|
|
USBH_UsrLog("%s class started.", phost->pActiveClass->Name);
|
|
|
|
/* Inform user that a class has been activated */
|
|
phost->pUser(phost, HOST_USER_CLASS_SELECTED);
|
|
8008b4a: 687b ldr r3, [r7, #4]
|
|
8008b4c: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008b50: 2103 movs r1, #3
|
|
8008b52: 6878 ldr r0, [r7, #4]
|
|
8008b54: 4798 blx r3
|
|
8008b56: e006 b.n 8008b66 <USBH_Process+0x332>
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008b58: 687b ldr r3, [r7, #4]
|
|
8008b5a: 220d movs r2, #13
|
|
8008b5c: 701a strb r2, [r3, #0]
|
|
8008b5e: e002 b.n 8008b66 <USBH_Process+0x332>
|
|
USBH_UsrLog("Device not supporting %s class.", phost->pActiveClass->Name);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008b60: 687b ldr r3, [r7, #4]
|
|
8008b62: 220d movs r2, #13
|
|
8008b64: 701a strb r2, [r3, #0]
|
|
USBH_UsrLog("No registered class for this device.");
|
|
}
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008b66: 2300 movs r3, #0
|
|
8008b68: 2200 movs r2, #0
|
|
8008b6a: 2105 movs r1, #5
|
|
8008b6c: 6878 ldr r0, [r7, #4]
|
|
8008b6e: f000 fb1b bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
8008b72: e074 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_CLASS_REQUEST:
|
|
/* process class standard control requests state machine */
|
|
if (phost->pActiveClass != NULL)
|
|
8008b74: 687b ldr r3, [r7, #4]
|
|
8008b76: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008b7a: 2b00 cmp r3, #0
|
|
8008b7c: d017 beq.n 8008bae <USBH_Process+0x37a>
|
|
{
|
|
status = phost->pActiveClass->Requests(phost);
|
|
8008b7e: 687b ldr r3, [r7, #4]
|
|
8008b80: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008b84: 691b ldr r3, [r3, #16]
|
|
8008b86: 6878 ldr r0, [r7, #4]
|
|
8008b88: 4798 blx r3
|
|
8008b8a: 4603 mov r3, r0
|
|
8008b8c: 73bb strb r3, [r7, #14]
|
|
|
|
if (status == USBH_OK)
|
|
8008b8e: 7bbb ldrb r3, [r7, #14]
|
|
8008b90: b2db uxtb r3, r3
|
|
8008b92: 2b00 cmp r3, #0
|
|
8008b94: d103 bne.n 8008b9e <USBH_Process+0x36a>
|
|
{
|
|
phost->gState = HOST_CLASS;
|
|
8008b96: 687b ldr r3, [r7, #4]
|
|
8008b98: 220b movs r2, #11
|
|
8008b9a: 701a strb r2, [r3, #0]
|
|
8008b9c: e00a b.n 8008bb4 <USBH_Process+0x380>
|
|
}
|
|
else if (status == USBH_FAIL)
|
|
8008b9e: 7bbb ldrb r3, [r7, #14]
|
|
8008ba0: b2db uxtb r3, r3
|
|
8008ba2: 2b02 cmp r3, #2
|
|
8008ba4: d106 bne.n 8008bb4 <USBH_Process+0x380>
|
|
{
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008ba6: 687b ldr r3, [r7, #4]
|
|
8008ba8: 220d movs r2, #13
|
|
8008baa: 701a strb r2, [r3, #0]
|
|
8008bac: e002 b.n 8008bb4 <USBH_Process+0x380>
|
|
/* .. */
|
|
}
|
|
}
|
|
else
|
|
{
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008bae: 687b ldr r3, [r7, #4]
|
|
8008bb0: 220d movs r2, #13
|
|
8008bb2: 701a strb r2, [r3, #0]
|
|
USBH_ErrLog("Invalid Class Driver.");
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008bb4: 2300 movs r3, #0
|
|
8008bb6: 2200 movs r2, #0
|
|
8008bb8: 2105 movs r1, #5
|
|
8008bba: 6878 ldr r0, [r7, #4]
|
|
8008bbc: f000 faf4 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
8008bc0: e04d b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_CLASS:
|
|
/* process class state machine */
|
|
if (phost->pActiveClass != NULL)
|
|
8008bc2: 687b ldr r3, [r7, #4]
|
|
8008bc4: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008bc8: 2b00 cmp r3, #0
|
|
8008bca: d047 beq.n 8008c5c <USBH_Process+0x428>
|
|
{
|
|
phost->pActiveClass->BgndProcess(phost);
|
|
8008bcc: 687b ldr r3, [r7, #4]
|
|
8008bce: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008bd2: 695b ldr r3, [r3, #20]
|
|
8008bd4: 6878 ldr r0, [r7, #4]
|
|
8008bd6: 4798 blx r3
|
|
}
|
|
break;
|
|
8008bd8: e040 b.n 8008c5c <USBH_Process+0x428>
|
|
|
|
case HOST_DEV_DISCONNECTED :
|
|
phost->device.is_disconnected = 0U;
|
|
8008bda: 687b ldr r3, [r7, #4]
|
|
8008bdc: 2200 movs r2, #0
|
|
8008bde: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
|
|
(void)DeInitStateMachine(phost);
|
|
8008be2: 6878 ldr r0, [r7, #4]
|
|
8008be4: f7ff fd18 bl 8008618 <DeInitStateMachine>
|
|
|
|
/* Re-Initilaize Host for new Enumeration */
|
|
if (phost->pActiveClass != NULL)
|
|
8008be8: 687b ldr r3, [r7, #4]
|
|
8008bea: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008bee: 2b00 cmp r3, #0
|
|
8008bf0: d009 beq.n 8008c06 <USBH_Process+0x3d2>
|
|
{
|
|
phost->pActiveClass->DeInit(phost);
|
|
8008bf2: 687b ldr r3, [r7, #4]
|
|
8008bf4: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
8008bf8: 68db ldr r3, [r3, #12]
|
|
8008bfa: 6878 ldr r0, [r7, #4]
|
|
8008bfc: 4798 blx r3
|
|
phost->pActiveClass = NULL;
|
|
8008bfe: 687b ldr r3, [r7, #4]
|
|
8008c00: 2200 movs r2, #0
|
|
8008c02: f8c3 237c str.w r2, [r3, #892] @ 0x37c
|
|
}
|
|
|
|
if (phost->pUser != NULL)
|
|
8008c06: 687b ldr r3, [r7, #4]
|
|
8008c08: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008c0c: 2b00 cmp r3, #0
|
|
8008c0e: d005 beq.n 8008c1c <USBH_Process+0x3e8>
|
|
{
|
|
phost->pUser(phost, HOST_USER_DISCONNECTION);
|
|
8008c10: 687b ldr r3, [r7, #4]
|
|
8008c12: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8008c16: 2105 movs r1, #5
|
|
8008c18: 6878 ldr r0, [r7, #4]
|
|
8008c1a: 4798 blx r3
|
|
}
|
|
USBH_UsrLog("USB Device disconnected");
|
|
|
|
if (phost->device.is_ReEnumerated == 1U)
|
|
8008c1c: 687b ldr r3, [r7, #4]
|
|
8008c1e: f893 3322 ldrb.w r3, [r3, #802] @ 0x322
|
|
8008c22: b2db uxtb r3, r3
|
|
8008c24: 2b01 cmp r3, #1
|
|
8008c26: d107 bne.n 8008c38 <USBH_Process+0x404>
|
|
{
|
|
phost->device.is_ReEnumerated = 0U;
|
|
8008c28: 687b ldr r3, [r7, #4]
|
|
8008c2a: 2200 movs r2, #0
|
|
8008c2c: f883 2322 strb.w r2, [r3, #802] @ 0x322
|
|
|
|
/* Start the host and re-enable Vbus */
|
|
(void)USBH_Start(phost);
|
|
8008c30: 6878 ldr r0, [r7, #4]
|
|
8008c32: f7ff fdee bl 8008812 <USBH_Start>
|
|
8008c36: e002 b.n 8008c3e <USBH_Process+0x40a>
|
|
}
|
|
else
|
|
{
|
|
/* Device Disconnection Completed, start USB Driver */
|
|
(void)USBH_LL_Start(phost);
|
|
8008c38: 6878 ldr r0, [r7, #4]
|
|
8008c3a: f003 ff23 bl 800ca84 <USBH_LL_Start>
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8008c3e: 2300 movs r3, #0
|
|
8008c40: 2200 movs r2, #0
|
|
8008c42: 2101 movs r1, #1
|
|
8008c44: 6878 ldr r0, [r7, #4]
|
|
8008c46: f000 faaf bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
8008c4a: e008 b.n 8008c5e <USBH_Process+0x42a>
|
|
|
|
case HOST_ABORT_STATE:
|
|
default :
|
|
break;
|
|
8008c4c: bf00 nop
|
|
8008c4e: e006 b.n 8008c5e <USBH_Process+0x42a>
|
|
break;
|
|
8008c50: bf00 nop
|
|
8008c52: e004 b.n 8008c5e <USBH_Process+0x42a>
|
|
break;
|
|
8008c54: bf00 nop
|
|
8008c56: e002 b.n 8008c5e <USBH_Process+0x42a>
|
|
break;
|
|
8008c58: bf00 nop
|
|
8008c5a: e000 b.n 8008c5e <USBH_Process+0x42a>
|
|
break;
|
|
8008c5c: bf00 nop
|
|
}
|
|
return USBH_OK;
|
|
8008c5e: 2300 movs r3, #0
|
|
}
|
|
8008c60: 4618 mov r0, r3
|
|
8008c62: 3710 adds r7, #16
|
|
8008c64: 46bd mov sp, r7
|
|
8008c66: bd80 pop {r7, pc}
|
|
|
|
08008c68 <USBH_HandleEnum>:
|
|
* This function includes the complete enumeration process
|
|
* @param phost: Host Handle
|
|
* @retval USBH_Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_HandleEnum(USBH_HandleTypeDef *phost)
|
|
{
|
|
8008c68: b580 push {r7, lr}
|
|
8008c6a: b088 sub sp, #32
|
|
8008c6c: af04 add r7, sp, #16
|
|
8008c6e: 6078 str r0, [r7, #4]
|
|
USBH_StatusTypeDef Status = USBH_BUSY;
|
|
8008c70: 2301 movs r3, #1
|
|
8008c72: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef ReqStatus = USBH_BUSY;
|
|
8008c74: 2301 movs r3, #1
|
|
8008c76: 73bb strb r3, [r7, #14]
|
|
|
|
switch (phost->EnumState)
|
|
8008c78: 687b ldr r3, [r7, #4]
|
|
8008c7a: 785b ldrb r3, [r3, #1]
|
|
8008c7c: 2b07 cmp r3, #7
|
|
8008c7e: f200 81db bhi.w 8009038 <USBH_HandleEnum+0x3d0>
|
|
8008c82: a201 add r2, pc, #4 @ (adr r2, 8008c88 <USBH_HandleEnum+0x20>)
|
|
8008c84: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8008c88: 08008ca9 .word 0x08008ca9
|
|
8008c8c: 08008d63 .word 0x08008d63
|
|
8008c90: 08008dcd .word 0x08008dcd
|
|
8008c94: 08008e57 .word 0x08008e57
|
|
8008c98: 08008ec1 .word 0x08008ec1
|
|
8008c9c: 08008f31 .word 0x08008f31
|
|
8008ca0: 08008f9b .word 0x08008f9b
|
|
8008ca4: 08008ff9 .word 0x08008ff9
|
|
{
|
|
case ENUM_IDLE:
|
|
/* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */
|
|
ReqStatus = USBH_Get_DevDesc(phost, 8U);
|
|
8008ca8: 2108 movs r1, #8
|
|
8008caa: 6878 ldr r0, [r7, #4]
|
|
8008cac: f000 fac7 bl 800923e <USBH_Get_DevDesc>
|
|
8008cb0: 4603 mov r3, r0
|
|
8008cb2: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008cb4: 7bbb ldrb r3, [r7, #14]
|
|
8008cb6: 2b00 cmp r3, #0
|
|
8008cb8: d12e bne.n 8008d18 <USBH_HandleEnum+0xb0>
|
|
{
|
|
phost->Control.pipe_size = phost->device.DevDesc.bMaxPacketSize;
|
|
8008cba: 687b ldr r3, [r7, #4]
|
|
8008cbc: f893 232d ldrb.w r2, [r3, #813] @ 0x32d
|
|
8008cc0: 687b ldr r3, [r7, #4]
|
|
8008cc2: 719a strb r2, [r3, #6]
|
|
|
|
phost->EnumState = ENUM_GET_FULL_DEV_DESC;
|
|
8008cc4: 687b ldr r3, [r7, #4]
|
|
8008cc6: 2201 movs r2, #1
|
|
8008cc8: 705a strb r2, [r3, #1]
|
|
|
|
/* modify control channels configuration for MaxPacket size */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address,
|
|
8008cca: 687b ldr r3, [r7, #4]
|
|
8008ccc: 7919 ldrb r1, [r3, #4]
|
|
8008cce: 687b ldr r3, [r7, #4]
|
|
8008cd0: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
8008cd4: 687b ldr r3, [r7, #4]
|
|
8008cd6: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.speed, USBH_EP_CONTROL,
|
|
(uint16_t)phost->Control.pipe_size);
|
|
8008cda: 687a ldr r2, [r7, #4]
|
|
8008cdc: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address,
|
|
8008cde: 9202 str r2, [sp, #8]
|
|
8008ce0: 2200 movs r2, #0
|
|
8008ce2: 9201 str r2, [sp, #4]
|
|
8008ce4: 9300 str r3, [sp, #0]
|
|
8008ce6: 4603 mov r3, r0
|
|
8008ce8: 2280 movs r2, #128 @ 0x80
|
|
8008cea: 6878 ldr r0, [r7, #4]
|
|
8008cec: f001 f9c0 bl 800a070 <USBH_OpenPipe>
|
|
|
|
/* Open Control pipes */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
|
|
8008cf0: 687b ldr r3, [r7, #4]
|
|
8008cf2: 7959 ldrb r1, [r3, #5]
|
|
8008cf4: 687b ldr r3, [r7, #4]
|
|
8008cf6: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
8008cfa: 687b ldr r3, [r7, #4]
|
|
8008cfc: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.speed, USBH_EP_CONTROL,
|
|
(uint16_t)phost->Control.pipe_size);
|
|
8008d00: 687a ldr r2, [r7, #4]
|
|
8008d02: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
|
|
8008d04: 9202 str r2, [sp, #8]
|
|
8008d06: 2200 movs r2, #0
|
|
8008d08: 9201 str r2, [sp, #4]
|
|
8008d0a: 9300 str r3, [sp, #0]
|
|
8008d0c: 4603 mov r3, r0
|
|
8008d0e: 2200 movs r2, #0
|
|
8008d10: 6878 ldr r0, [r7, #4]
|
|
8008d12: f001 f9ad bl 800a070 <USBH_OpenPipe>
|
|
}
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
break;
|
|
8008d16: e191 b.n 800903c <USBH_HandleEnum+0x3d4>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008d18: 7bbb ldrb r3, [r7, #14]
|
|
8008d1a: 2b03 cmp r3, #3
|
|
8008d1c: f040 818e bne.w 800903c <USBH_HandleEnum+0x3d4>
|
|
phost->device.EnumCnt++;
|
|
8008d20: 687b ldr r3, [r7, #4]
|
|
8008d22: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008d26: 3301 adds r3, #1
|
|
8008d28: b2da uxtb r2, r3
|
|
8008d2a: 687b ldr r3, [r7, #4]
|
|
8008d2c: f883 231e strb.w r2, [r3, #798] @ 0x31e
|
|
if (phost->device.EnumCnt > 3U)
|
|
8008d30: 687b ldr r3, [r7, #4]
|
|
8008d32: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008d36: 2b03 cmp r3, #3
|
|
8008d38: d903 bls.n 8008d42 <USBH_HandleEnum+0xda>
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008d3a: 687b ldr r3, [r7, #4]
|
|
8008d3c: 220d movs r2, #13
|
|
8008d3e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008d40: e17c b.n 800903c <USBH_HandleEnum+0x3d4>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8008d42: 687b ldr r3, [r7, #4]
|
|
8008d44: 795b ldrb r3, [r3, #5]
|
|
8008d46: 4619 mov r1, r3
|
|
8008d48: 6878 ldr r0, [r7, #4]
|
|
8008d4a: f001 f9e1 bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8008d4e: 687b ldr r3, [r7, #4]
|
|
8008d50: 791b ldrb r3, [r3, #4]
|
|
8008d52: 4619 mov r1, r3
|
|
8008d54: 6878 ldr r0, [r7, #4]
|
|
8008d56: f001 f9db bl 800a110 <USBH_FreePipe>
|
|
phost->gState = HOST_IDLE;
|
|
8008d5a: 687b ldr r3, [r7, #4]
|
|
8008d5c: 2200 movs r2, #0
|
|
8008d5e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008d60: e16c b.n 800903c <USBH_HandleEnum+0x3d4>
|
|
|
|
case ENUM_GET_FULL_DEV_DESC:
|
|
/* Get FULL Device Desc */
|
|
ReqStatus = USBH_Get_DevDesc(phost, USB_DEVICE_DESC_SIZE);
|
|
8008d62: 2112 movs r1, #18
|
|
8008d64: 6878 ldr r0, [r7, #4]
|
|
8008d66: f000 fa6a bl 800923e <USBH_Get_DevDesc>
|
|
8008d6a: 4603 mov r3, r0
|
|
8008d6c: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008d6e: 7bbb ldrb r3, [r7, #14]
|
|
8008d70: 2b00 cmp r3, #0
|
|
8008d72: d103 bne.n 8008d7c <USBH_HandleEnum+0x114>
|
|
{
|
|
USBH_UsrLog("PID: %xh", phost->device.DevDesc.idProduct);
|
|
USBH_UsrLog("VID: %xh", phost->device.DevDesc.idVendor);
|
|
|
|
phost->EnumState = ENUM_SET_ADDR;
|
|
8008d74: 687b ldr r3, [r7, #4]
|
|
8008d76: 2202 movs r2, #2
|
|
8008d78: 705a strb r2, [r3, #1]
|
|
}
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
break;
|
|
8008d7a: e161 b.n 8009040 <USBH_HandleEnum+0x3d8>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008d7c: 7bbb ldrb r3, [r7, #14]
|
|
8008d7e: 2b03 cmp r3, #3
|
|
8008d80: f040 815e bne.w 8009040 <USBH_HandleEnum+0x3d8>
|
|
phost->device.EnumCnt++;
|
|
8008d84: 687b ldr r3, [r7, #4]
|
|
8008d86: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008d8a: 3301 adds r3, #1
|
|
8008d8c: b2da uxtb r2, r3
|
|
8008d8e: 687b ldr r3, [r7, #4]
|
|
8008d90: f883 231e strb.w r2, [r3, #798] @ 0x31e
|
|
if (phost->device.EnumCnt > 3U)
|
|
8008d94: 687b ldr r3, [r7, #4]
|
|
8008d96: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008d9a: 2b03 cmp r3, #3
|
|
8008d9c: d903 bls.n 8008da6 <USBH_HandleEnum+0x13e>
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008d9e: 687b ldr r3, [r7, #4]
|
|
8008da0: 220d movs r2, #13
|
|
8008da2: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008da4: e14c b.n 8009040 <USBH_HandleEnum+0x3d8>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8008da6: 687b ldr r3, [r7, #4]
|
|
8008da8: 795b ldrb r3, [r3, #5]
|
|
8008daa: 4619 mov r1, r3
|
|
8008dac: 6878 ldr r0, [r7, #4]
|
|
8008dae: f001 f9af bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8008db2: 687b ldr r3, [r7, #4]
|
|
8008db4: 791b ldrb r3, [r3, #4]
|
|
8008db6: 4619 mov r1, r3
|
|
8008db8: 6878 ldr r0, [r7, #4]
|
|
8008dba: f001 f9a9 bl 800a110 <USBH_FreePipe>
|
|
phost->EnumState = ENUM_IDLE;
|
|
8008dbe: 687b ldr r3, [r7, #4]
|
|
8008dc0: 2200 movs r2, #0
|
|
8008dc2: 705a strb r2, [r3, #1]
|
|
phost->gState = HOST_IDLE;
|
|
8008dc4: 687b ldr r3, [r7, #4]
|
|
8008dc6: 2200 movs r2, #0
|
|
8008dc8: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008dca: e139 b.n 8009040 <USBH_HandleEnum+0x3d8>
|
|
|
|
case ENUM_SET_ADDR:
|
|
/* set address */
|
|
ReqStatus = USBH_SetAddress(phost, USBH_DEVICE_ADDRESS);
|
|
8008dcc: 2101 movs r1, #1
|
|
8008dce: 6878 ldr r0, [r7, #4]
|
|
8008dd0: f000 faf4 bl 80093bc <USBH_SetAddress>
|
|
8008dd4: 4603 mov r3, r0
|
|
8008dd6: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008dd8: 7bbb ldrb r3, [r7, #14]
|
|
8008dda: 2b00 cmp r3, #0
|
|
8008ddc: d130 bne.n 8008e40 <USBH_HandleEnum+0x1d8>
|
|
{
|
|
USBH_Delay(2U);
|
|
8008dde: 2002 movs r0, #2
|
|
8008de0: f003 ffa5 bl 800cd2e <USBH_Delay>
|
|
phost->device.address = USBH_DEVICE_ADDRESS;
|
|
8008de4: 687b ldr r3, [r7, #4]
|
|
8008de6: 2201 movs r2, #1
|
|
8008de8: f883 231c strb.w r2, [r3, #796] @ 0x31c
|
|
|
|
/* user callback for device address assigned */
|
|
USBH_UsrLog("Address (#%d) assigned.", phost->device.address);
|
|
phost->EnumState = ENUM_GET_CFG_DESC;
|
|
8008dec: 687b ldr r3, [r7, #4]
|
|
8008dee: 2203 movs r2, #3
|
|
8008df0: 705a strb r2, [r3, #1]
|
|
|
|
/* modify control channels to update device address */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address,
|
|
8008df2: 687b ldr r3, [r7, #4]
|
|
8008df4: 7919 ldrb r1, [r3, #4]
|
|
8008df6: 687b ldr r3, [r7, #4]
|
|
8008df8: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
8008dfc: 687b ldr r3, [r7, #4]
|
|
8008dfe: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.speed, USBH_EP_CONTROL,
|
|
(uint16_t)phost->Control.pipe_size);
|
|
8008e02: 687a ldr r2, [r7, #4]
|
|
8008e04: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_in, 0x80U, phost->device.address,
|
|
8008e06: 9202 str r2, [sp, #8]
|
|
8008e08: 2200 movs r2, #0
|
|
8008e0a: 9201 str r2, [sp, #4]
|
|
8008e0c: 9300 str r3, [sp, #0]
|
|
8008e0e: 4603 mov r3, r0
|
|
8008e10: 2280 movs r2, #128 @ 0x80
|
|
8008e12: 6878 ldr r0, [r7, #4]
|
|
8008e14: f001 f92c bl 800a070 <USBH_OpenPipe>
|
|
|
|
/* Open Control pipes */
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
|
|
8008e18: 687b ldr r3, [r7, #4]
|
|
8008e1a: 7959 ldrb r1, [r3, #5]
|
|
8008e1c: 687b ldr r3, [r7, #4]
|
|
8008e1e: f893 031c ldrb.w r0, [r3, #796] @ 0x31c
|
|
8008e22: 687b ldr r3, [r7, #4]
|
|
8008e24: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
phost->device.speed, USBH_EP_CONTROL,
|
|
(uint16_t)phost->Control.pipe_size);
|
|
8008e28: 687a ldr r2, [r7, #4]
|
|
8008e2a: 7992 ldrb r2, [r2, #6]
|
|
(void)USBH_OpenPipe(phost, phost->Control.pipe_out, 0x00U, phost->device.address,
|
|
8008e2c: 9202 str r2, [sp, #8]
|
|
8008e2e: 2200 movs r2, #0
|
|
8008e30: 9201 str r2, [sp, #4]
|
|
8008e32: 9300 str r3, [sp, #0]
|
|
8008e34: 4603 mov r3, r0
|
|
8008e36: 2200 movs r2, #0
|
|
8008e38: 6878 ldr r0, [r7, #4]
|
|
8008e3a: f001 f919 bl 800a070 <USBH_OpenPipe>
|
|
}
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
break;
|
|
8008e3e: e101 b.n 8009044 <USBH_HandleEnum+0x3dc>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008e40: 7bbb ldrb r3, [r7, #14]
|
|
8008e42: 2b03 cmp r3, #3
|
|
8008e44: f040 80fe bne.w 8009044 <USBH_HandleEnum+0x3dc>
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008e48: 687b ldr r3, [r7, #4]
|
|
8008e4a: 220d movs r2, #13
|
|
8008e4c: 701a strb r2, [r3, #0]
|
|
phost->EnumState = ENUM_IDLE;
|
|
8008e4e: 687b ldr r3, [r7, #4]
|
|
8008e50: 2200 movs r2, #0
|
|
8008e52: 705a strb r2, [r3, #1]
|
|
break;
|
|
8008e54: e0f6 b.n 8009044 <USBH_HandleEnum+0x3dc>
|
|
|
|
case ENUM_GET_CFG_DESC:
|
|
/* get standard configuration descriptor */
|
|
ReqStatus = USBH_Get_CfgDesc(phost, USB_CONFIGURATION_DESC_SIZE);
|
|
8008e56: 2109 movs r1, #9
|
|
8008e58: 6878 ldr r0, [r7, #4]
|
|
8008e5a: f000 fa1c bl 8009296 <USBH_Get_CfgDesc>
|
|
8008e5e: 4603 mov r3, r0
|
|
8008e60: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008e62: 7bbb ldrb r3, [r7, #14]
|
|
8008e64: 2b00 cmp r3, #0
|
|
8008e66: d103 bne.n 8008e70 <USBH_HandleEnum+0x208>
|
|
{
|
|
phost->EnumState = ENUM_GET_FULL_CFG_DESC;
|
|
8008e68: 687b ldr r3, [r7, #4]
|
|
8008e6a: 2204 movs r2, #4
|
|
8008e6c: 705a strb r2, [r3, #1]
|
|
}
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
break;
|
|
8008e6e: e0eb b.n 8009048 <USBH_HandleEnum+0x3e0>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008e70: 7bbb ldrb r3, [r7, #14]
|
|
8008e72: 2b03 cmp r3, #3
|
|
8008e74: f040 80e8 bne.w 8009048 <USBH_HandleEnum+0x3e0>
|
|
phost->device.EnumCnt++;
|
|
8008e78: 687b ldr r3, [r7, #4]
|
|
8008e7a: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008e7e: 3301 adds r3, #1
|
|
8008e80: b2da uxtb r2, r3
|
|
8008e82: 687b ldr r3, [r7, #4]
|
|
8008e84: f883 231e strb.w r2, [r3, #798] @ 0x31e
|
|
if (phost->device.EnumCnt > 3U)
|
|
8008e88: 687b ldr r3, [r7, #4]
|
|
8008e8a: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008e8e: 2b03 cmp r3, #3
|
|
8008e90: d903 bls.n 8008e9a <USBH_HandleEnum+0x232>
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008e92: 687b ldr r3, [r7, #4]
|
|
8008e94: 220d movs r2, #13
|
|
8008e96: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008e98: e0d6 b.n 8009048 <USBH_HandleEnum+0x3e0>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8008e9a: 687b ldr r3, [r7, #4]
|
|
8008e9c: 795b ldrb r3, [r3, #5]
|
|
8008e9e: 4619 mov r1, r3
|
|
8008ea0: 6878 ldr r0, [r7, #4]
|
|
8008ea2: f001 f935 bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8008ea6: 687b ldr r3, [r7, #4]
|
|
8008ea8: 791b ldrb r3, [r3, #4]
|
|
8008eaa: 4619 mov r1, r3
|
|
8008eac: 6878 ldr r0, [r7, #4]
|
|
8008eae: f001 f92f bl 800a110 <USBH_FreePipe>
|
|
phost->EnumState = ENUM_IDLE;
|
|
8008eb2: 687b ldr r3, [r7, #4]
|
|
8008eb4: 2200 movs r2, #0
|
|
8008eb6: 705a strb r2, [r3, #1]
|
|
phost->gState = HOST_IDLE;
|
|
8008eb8: 687b ldr r3, [r7, #4]
|
|
8008eba: 2200 movs r2, #0
|
|
8008ebc: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008ebe: e0c3 b.n 8009048 <USBH_HandleEnum+0x3e0>
|
|
|
|
case ENUM_GET_FULL_CFG_DESC:
|
|
/* get FULL config descriptor (config, interface, endpoints) */
|
|
ReqStatus = USBH_Get_CfgDesc(phost, phost->device.CfgDesc.wTotalLength);
|
|
8008ec0: 687b ldr r3, [r7, #4]
|
|
8008ec2: f8b3 333a ldrh.w r3, [r3, #826] @ 0x33a
|
|
8008ec6: 4619 mov r1, r3
|
|
8008ec8: 6878 ldr r0, [r7, #4]
|
|
8008eca: f000 f9e4 bl 8009296 <USBH_Get_CfgDesc>
|
|
8008ece: 4603 mov r3, r0
|
|
8008ed0: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008ed2: 7bbb ldrb r3, [r7, #14]
|
|
8008ed4: 2b00 cmp r3, #0
|
|
8008ed6: d103 bne.n 8008ee0 <USBH_HandleEnum+0x278>
|
|
{
|
|
phost->EnumState = ENUM_GET_MFC_STRING_DESC;
|
|
8008ed8: 687b ldr r3, [r7, #4]
|
|
8008eda: 2205 movs r2, #5
|
|
8008edc: 705a strb r2, [r3, #1]
|
|
}
|
|
else
|
|
{
|
|
/* .. */
|
|
}
|
|
break;
|
|
8008ede: e0b5 b.n 800904c <USBH_HandleEnum+0x3e4>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008ee0: 7bbb ldrb r3, [r7, #14]
|
|
8008ee2: 2b03 cmp r3, #3
|
|
8008ee4: f040 80b2 bne.w 800904c <USBH_HandleEnum+0x3e4>
|
|
phost->device.EnumCnt++;
|
|
8008ee8: 687b ldr r3, [r7, #4]
|
|
8008eea: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008eee: 3301 adds r3, #1
|
|
8008ef0: b2da uxtb r2, r3
|
|
8008ef2: 687b ldr r3, [r7, #4]
|
|
8008ef4: f883 231e strb.w r2, [r3, #798] @ 0x31e
|
|
if (phost->device.EnumCnt > 3U)
|
|
8008ef8: 687b ldr r3, [r7, #4]
|
|
8008efa: f893 331e ldrb.w r3, [r3, #798] @ 0x31e
|
|
8008efe: 2b03 cmp r3, #3
|
|
8008f00: d903 bls.n 8008f0a <USBH_HandleEnum+0x2a2>
|
|
phost->gState = HOST_ABORT_STATE;
|
|
8008f02: 687b ldr r3, [r7, #4]
|
|
8008f04: 220d movs r2, #13
|
|
8008f06: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008f08: e0a0 b.n 800904c <USBH_HandleEnum+0x3e4>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8008f0a: 687b ldr r3, [r7, #4]
|
|
8008f0c: 795b ldrb r3, [r3, #5]
|
|
8008f0e: 4619 mov r1, r3
|
|
8008f10: 6878 ldr r0, [r7, #4]
|
|
8008f12: f001 f8fd bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8008f16: 687b ldr r3, [r7, #4]
|
|
8008f18: 791b ldrb r3, [r3, #4]
|
|
8008f1a: 4619 mov r1, r3
|
|
8008f1c: 6878 ldr r0, [r7, #4]
|
|
8008f1e: f001 f8f7 bl 800a110 <USBH_FreePipe>
|
|
phost->EnumState = ENUM_IDLE;
|
|
8008f22: 687b ldr r3, [r7, #4]
|
|
8008f24: 2200 movs r2, #0
|
|
8008f26: 705a strb r2, [r3, #1]
|
|
phost->gState = HOST_IDLE;
|
|
8008f28: 687b ldr r3, [r7, #4]
|
|
8008f2a: 2200 movs r2, #0
|
|
8008f2c: 701a strb r2, [r3, #0]
|
|
break;
|
|
8008f2e: e08d b.n 800904c <USBH_HandleEnum+0x3e4>
|
|
|
|
case ENUM_GET_MFC_STRING_DESC:
|
|
if (phost->device.DevDesc.iManufacturer != 0U)
|
|
8008f30: 687b ldr r3, [r7, #4]
|
|
8008f32: f893 3334 ldrb.w r3, [r3, #820] @ 0x334
|
|
8008f36: 2b00 cmp r3, #0
|
|
8008f38: d025 beq.n 8008f86 <USBH_HandleEnum+0x31e>
|
|
{
|
|
/* Check that Manufacturer String is available */
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer,
|
|
8008f3a: 687b ldr r3, [r7, #4]
|
|
8008f3c: f893 1334 ldrb.w r1, [r3, #820] @ 0x334
|
|
phost->device.Data, 0xFFU);
|
|
8008f40: 687b ldr r3, [r7, #4]
|
|
8008f42: f503 728e add.w r2, r3, #284 @ 0x11c
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iManufacturer,
|
|
8008f46: 23ff movs r3, #255 @ 0xff
|
|
8008f48: 6878 ldr r0, [r7, #4]
|
|
8008f4a: f000 f9ce bl 80092ea <USBH_Get_StringDesc>
|
|
8008f4e: 4603 mov r3, r0
|
|
8008f50: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008f52: 7bbb ldrb r3, [r7, #14]
|
|
8008f54: 2b00 cmp r3, #0
|
|
8008f56: d109 bne.n 8008f6c <USBH_HandleEnum+0x304>
|
|
{
|
|
/* User callback for Manufacturing string */
|
|
USBH_UsrLog("Manufacturer : %s", (char *)(void *)phost->device.Data);
|
|
phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
|
|
8008f58: 687b ldr r3, [r7, #4]
|
|
8008f5a: 2206 movs r2, #6
|
|
8008f5c: 705a strb r2, [r3, #1]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008f5e: 2300 movs r3, #0
|
|
8008f60: 2200 movs r2, #0
|
|
8008f62: 2105 movs r1, #5
|
|
8008f64: 6878 ldr r0, [r7, #4]
|
|
8008f66: f000 f91f bl 80091a8 <USBH_OS_PutMessage>
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
break;
|
|
8008f6a: e071 b.n 8009050 <USBH_HandleEnum+0x3e8>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008f6c: 7bbb ldrb r3, [r7, #14]
|
|
8008f6e: 2b03 cmp r3, #3
|
|
8008f70: d16e bne.n 8009050 <USBH_HandleEnum+0x3e8>
|
|
phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
|
|
8008f72: 687b ldr r3, [r7, #4]
|
|
8008f74: 2206 movs r2, #6
|
|
8008f76: 705a strb r2, [r3, #1]
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008f78: 2300 movs r3, #0
|
|
8008f7a: 2200 movs r2, #0
|
|
8008f7c: 2105 movs r1, #5
|
|
8008f7e: 6878 ldr r0, [r7, #4]
|
|
8008f80: f000 f912 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8008f84: e064 b.n 8009050 <USBH_HandleEnum+0x3e8>
|
|
phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC;
|
|
8008f86: 687b ldr r3, [r7, #4]
|
|
8008f88: 2206 movs r2, #6
|
|
8008f8a: 705a strb r2, [r3, #1]
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008f8c: 2300 movs r3, #0
|
|
8008f8e: 2200 movs r2, #0
|
|
8008f90: 2105 movs r1, #5
|
|
8008f92: 6878 ldr r0, [r7, #4]
|
|
8008f94: f000 f908 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8008f98: e05a b.n 8009050 <USBH_HandleEnum+0x3e8>
|
|
|
|
case ENUM_GET_PRODUCT_STRING_DESC:
|
|
if (phost->device.DevDesc.iProduct != 0U)
|
|
8008f9a: 687b ldr r3, [r7, #4]
|
|
8008f9c: f893 3335 ldrb.w r3, [r3, #821] @ 0x335
|
|
8008fa0: 2b00 cmp r3, #0
|
|
8008fa2: d01f beq.n 8008fe4 <USBH_HandleEnum+0x37c>
|
|
{
|
|
/* Check that Product string is available */
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct,
|
|
8008fa4: 687b ldr r3, [r7, #4]
|
|
8008fa6: f893 1335 ldrb.w r1, [r3, #821] @ 0x335
|
|
phost->device.Data, 0xFFU);
|
|
8008faa: 687b ldr r3, [r7, #4]
|
|
8008fac: f503 728e add.w r2, r3, #284 @ 0x11c
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iProduct,
|
|
8008fb0: 23ff movs r3, #255 @ 0xff
|
|
8008fb2: 6878 ldr r0, [r7, #4]
|
|
8008fb4: f000 f999 bl 80092ea <USBH_Get_StringDesc>
|
|
8008fb8: 4603 mov r3, r0
|
|
8008fba: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
8008fbc: 7bbb ldrb r3, [r7, #14]
|
|
8008fbe: 2b00 cmp r3, #0
|
|
8008fc0: d103 bne.n 8008fca <USBH_HandleEnum+0x362>
|
|
{
|
|
/* User callback for Product string */
|
|
USBH_UsrLog("Product : %s", (char *)(void *)phost->device.Data);
|
|
phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
|
|
8008fc2: 687b ldr r3, [r7, #4]
|
|
8008fc4: 2207 movs r2, #7
|
|
8008fc6: 705a strb r2, [r3, #1]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
break;
|
|
8008fc8: e044 b.n 8009054 <USBH_HandleEnum+0x3ec>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8008fca: 7bbb ldrb r3, [r7, #14]
|
|
8008fcc: 2b03 cmp r3, #3
|
|
8008fce: d141 bne.n 8009054 <USBH_HandleEnum+0x3ec>
|
|
phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
|
|
8008fd0: 687b ldr r3, [r7, #4]
|
|
8008fd2: 2207 movs r2, #7
|
|
8008fd4: 705a strb r2, [r3, #1]
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008fd6: 2300 movs r3, #0
|
|
8008fd8: 2200 movs r2, #0
|
|
8008fda: 2105 movs r1, #5
|
|
8008fdc: 6878 ldr r0, [r7, #4]
|
|
8008fde: f000 f8e3 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8008fe2: e037 b.n 8009054 <USBH_HandleEnum+0x3ec>
|
|
phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC;
|
|
8008fe4: 687b ldr r3, [r7, #4]
|
|
8008fe6: 2207 movs r2, #7
|
|
8008fe8: 705a strb r2, [r3, #1]
|
|
USBH_OS_PutMessage(phost, USBH_STATE_CHANGED_EVENT, 0U, 0U);
|
|
8008fea: 2300 movs r3, #0
|
|
8008fec: 2200 movs r2, #0
|
|
8008fee: 2105 movs r1, #5
|
|
8008ff0: 6878 ldr r0, [r7, #4]
|
|
8008ff2: f000 f8d9 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8008ff6: e02d b.n 8009054 <USBH_HandleEnum+0x3ec>
|
|
|
|
case ENUM_GET_SERIALNUM_STRING_DESC:
|
|
if (phost->device.DevDesc.iSerialNumber != 0U)
|
|
8008ff8: 687b ldr r3, [r7, #4]
|
|
8008ffa: f893 3336 ldrb.w r3, [r3, #822] @ 0x336
|
|
8008ffe: 2b00 cmp r3, #0
|
|
8009000: d017 beq.n 8009032 <USBH_HandleEnum+0x3ca>
|
|
{
|
|
/* Check that Serial number string is available */
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber,
|
|
8009002: 687b ldr r3, [r7, #4]
|
|
8009004: f893 1336 ldrb.w r1, [r3, #822] @ 0x336
|
|
phost->device.Data, 0xFFU);
|
|
8009008: 687b ldr r3, [r7, #4]
|
|
800900a: f503 728e add.w r2, r3, #284 @ 0x11c
|
|
ReqStatus = USBH_Get_StringDesc(phost, phost->device.DevDesc.iSerialNumber,
|
|
800900e: 23ff movs r3, #255 @ 0xff
|
|
8009010: 6878 ldr r0, [r7, #4]
|
|
8009012: f000 f96a bl 80092ea <USBH_Get_StringDesc>
|
|
8009016: 4603 mov r3, r0
|
|
8009018: 73bb strb r3, [r7, #14]
|
|
if (ReqStatus == USBH_OK)
|
|
800901a: 7bbb ldrb r3, [r7, #14]
|
|
800901c: 2b00 cmp r3, #0
|
|
800901e: d102 bne.n 8009026 <USBH_HandleEnum+0x3be>
|
|
{
|
|
/* User callback for Serial number string */
|
|
USBH_UsrLog("Serial Number : %s", (char *)(void *)phost->device.Data);
|
|
Status = USBH_OK;
|
|
8009020: 2300 movs r3, #0
|
|
8009022: 73fb strb r3, [r7, #15]
|
|
else
|
|
{
|
|
USBH_UsrLog("Serial Number : N/A");
|
|
Status = USBH_OK;
|
|
}
|
|
break;
|
|
8009024: e018 b.n 8009058 <USBH_HandleEnum+0x3f0>
|
|
else if (ReqStatus == USBH_NOT_SUPPORTED)
|
|
8009026: 7bbb ldrb r3, [r7, #14]
|
|
8009028: 2b03 cmp r3, #3
|
|
800902a: d115 bne.n 8009058 <USBH_HandleEnum+0x3f0>
|
|
Status = USBH_OK;
|
|
800902c: 2300 movs r3, #0
|
|
800902e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009030: e012 b.n 8009058 <USBH_HandleEnum+0x3f0>
|
|
Status = USBH_OK;
|
|
8009032: 2300 movs r3, #0
|
|
8009034: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009036: e00f b.n 8009058 <USBH_HandleEnum+0x3f0>
|
|
|
|
default:
|
|
break;
|
|
8009038: bf00 nop
|
|
800903a: e00e b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
800903c: bf00 nop
|
|
800903e: e00c b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009040: bf00 nop
|
|
8009042: e00a b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009044: bf00 nop
|
|
8009046: e008 b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009048: bf00 nop
|
|
800904a: e006 b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
800904c: bf00 nop
|
|
800904e: e004 b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009050: bf00 nop
|
|
8009052: e002 b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009054: bf00 nop
|
|
8009056: e000 b.n 800905a <USBH_HandleEnum+0x3f2>
|
|
break;
|
|
8009058: bf00 nop
|
|
}
|
|
return Status;
|
|
800905a: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800905c: 4618 mov r0, r3
|
|
800905e: 3710 adds r7, #16
|
|
8009060: 46bd mov sp, r7
|
|
8009062: bd80 pop {r7, pc}
|
|
|
|
08009064 <USBH_LL_SetTimer>:
|
|
* Set the initial Host Timer tick
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_SetTimer(USBH_HandleTypeDef *phost, uint32_t time)
|
|
{
|
|
8009064: b480 push {r7}
|
|
8009066: b083 sub sp, #12
|
|
8009068: af00 add r7, sp, #0
|
|
800906a: 6078 str r0, [r7, #4]
|
|
800906c: 6039 str r1, [r7, #0]
|
|
phost->Timer = time;
|
|
800906e: 687b ldr r3, [r7, #4]
|
|
8009070: 683a ldr r2, [r7, #0]
|
|
8009072: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4
|
|
}
|
|
8009076: bf00 nop
|
|
8009078: 370c adds r7, #12
|
|
800907a: 46bd mov sp, r7
|
|
800907c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009080: 4770 bx lr
|
|
|
|
08009082 <USBH_LL_IncTimer>:
|
|
* Increment Host Timer tick
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_IncTimer(USBH_HandleTypeDef *phost)
|
|
{
|
|
8009082: b580 push {r7, lr}
|
|
8009084: b082 sub sp, #8
|
|
8009086: af00 add r7, sp, #0
|
|
8009088: 6078 str r0, [r7, #4]
|
|
phost->Timer++;
|
|
800908a: 687b ldr r3, [r7, #4]
|
|
800908c: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8009090: 1c5a adds r2, r3, #1
|
|
8009092: 687b ldr r3, [r7, #4]
|
|
8009094: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4
|
|
USBH_HandleSof(phost);
|
|
8009098: 6878 ldr r0, [r7, #4]
|
|
800909a: f000 f804 bl 80090a6 <USBH_HandleSof>
|
|
}
|
|
800909e: bf00 nop
|
|
80090a0: 3708 adds r7, #8
|
|
80090a2: 46bd mov sp, r7
|
|
80090a4: bd80 pop {r7, pc}
|
|
|
|
080090a6 <USBH_HandleSof>:
|
|
* Call SOF process
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
static void USBH_HandleSof(USBH_HandleTypeDef *phost)
|
|
{
|
|
80090a6: b580 push {r7, lr}
|
|
80090a8: b082 sub sp, #8
|
|
80090aa: af00 add r7, sp, #0
|
|
80090ac: 6078 str r0, [r7, #4]
|
|
if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL))
|
|
80090ae: 687b ldr r3, [r7, #4]
|
|
80090b0: 781b ldrb r3, [r3, #0]
|
|
80090b2: b2db uxtb r3, r3
|
|
80090b4: 2b0b cmp r3, #11
|
|
80090b6: d10a bne.n 80090ce <USBH_HandleSof+0x28>
|
|
80090b8: 687b ldr r3, [r7, #4]
|
|
80090ba: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80090be: 2b00 cmp r3, #0
|
|
80090c0: d005 beq.n 80090ce <USBH_HandleSof+0x28>
|
|
{
|
|
phost->pActiveClass->SOFProcess(phost);
|
|
80090c2: 687b ldr r3, [r7, #4]
|
|
80090c4: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80090c8: 699b ldr r3, [r3, #24]
|
|
80090ca: 6878 ldr r0, [r7, #4]
|
|
80090cc: 4798 blx r3
|
|
}
|
|
}
|
|
80090ce: bf00 nop
|
|
80090d0: 3708 adds r7, #8
|
|
80090d2: 46bd mov sp, r7
|
|
80090d4: bd80 pop {r7, pc}
|
|
|
|
080090d6 <USBH_LL_PortEnabled>:
|
|
* Port Enabled
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost)
|
|
{
|
|
80090d6: b580 push {r7, lr}
|
|
80090d8: b082 sub sp, #8
|
|
80090da: af00 add r7, sp, #0
|
|
80090dc: 6078 str r0, [r7, #4]
|
|
phost->device.PortEnabled = 1U;
|
|
80090de: 687b ldr r3, [r7, #4]
|
|
80090e0: 2201 movs r2, #1
|
|
80090e2: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
80090e6: 2300 movs r3, #0
|
|
80090e8: 2200 movs r2, #0
|
|
80090ea: 2101 movs r1, #1
|
|
80090ec: 6878 ldr r0, [r7, #4]
|
|
80090ee: f000 f85b bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return;
|
|
80090f2: bf00 nop
|
|
}
|
|
80090f4: 3708 adds r7, #8
|
|
80090f6: 46bd mov sp, r7
|
|
80090f8: bd80 pop {r7, pc}
|
|
|
|
080090fa <USBH_LL_PortDisabled>:
|
|
* Port Disabled
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost)
|
|
{
|
|
80090fa: b480 push {r7}
|
|
80090fc: b083 sub sp, #12
|
|
80090fe: af00 add r7, sp, #0
|
|
8009100: 6078 str r0, [r7, #4]
|
|
phost->device.PortEnabled = 0U;
|
|
8009102: 687b ldr r3, [r7, #4]
|
|
8009104: 2200 movs r2, #0
|
|
8009106: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
phost->device.is_disconnected = 1U;
|
|
800910a: 687b ldr r3, [r7, #4]
|
|
800910c: 2201 movs r2, #1
|
|
800910e: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
|
|
return;
|
|
8009112: bf00 nop
|
|
}
|
|
8009114: 370c adds r7, #12
|
|
8009116: 46bd mov sp, r7
|
|
8009118: f85d 7b04 ldr.w r7, [sp], #4
|
|
800911c: 4770 bx lr
|
|
|
|
0800911e <USBH_LL_Connect>:
|
|
* Handle USB Host connection event
|
|
* @param phost: Host Handle
|
|
* @retval USBH_Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost)
|
|
{
|
|
800911e: b580 push {r7, lr}
|
|
8009120: b082 sub sp, #8
|
|
8009122: af00 add r7, sp, #0
|
|
8009124: 6078 str r0, [r7, #4]
|
|
phost->device.is_connected = 1U;
|
|
8009126: 687b ldr r3, [r7, #4]
|
|
8009128: 2201 movs r2, #1
|
|
800912a: f883 2320 strb.w r2, [r3, #800] @ 0x320
|
|
phost->device.is_disconnected = 0U;
|
|
800912e: 687b ldr r3, [r7, #4]
|
|
8009130: 2200 movs r2, #0
|
|
8009132: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
phost->device.is_ReEnumerated = 0U;
|
|
8009136: 687b ldr r3, [r7, #4]
|
|
8009138: 2200 movs r2, #0
|
|
800913a: f883 2322 strb.w r2, [r3, #802] @ 0x322
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
800913e: 2300 movs r3, #0
|
|
8009140: 2200 movs r2, #0
|
|
8009142: 2101 movs r1, #1
|
|
8009144: 6878 ldr r0, [r7, #4]
|
|
8009146: f000 f82f bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
800914a: 2300 movs r3, #0
|
|
}
|
|
800914c: 4618 mov r0, r3
|
|
800914e: 3708 adds r7, #8
|
|
8009150: 46bd mov sp, r7
|
|
8009152: bd80 pop {r7, pc}
|
|
|
|
08009154 <USBH_LL_Disconnect>:
|
|
* Handle USB Host disconnection event
|
|
* @param phost: Host Handle
|
|
* @retval USBH_Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost)
|
|
{
|
|
8009154: b580 push {r7, lr}
|
|
8009156: b082 sub sp, #8
|
|
8009158: af00 add r7, sp, #0
|
|
800915a: 6078 str r0, [r7, #4]
|
|
/* update device connection states */
|
|
phost->device.is_disconnected = 1U;
|
|
800915c: 687b ldr r3, [r7, #4]
|
|
800915e: 2201 movs r2, #1
|
|
8009160: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
phost->device.is_connected = 0U;
|
|
8009164: 687b ldr r3, [r7, #4]
|
|
8009166: 2200 movs r2, #0
|
|
8009168: f883 2320 strb.w r2, [r3, #800] @ 0x320
|
|
phost->device.PortEnabled = 0U;
|
|
800916c: 687b ldr r3, [r7, #4]
|
|
800916e: 2200 movs r2, #0
|
|
8009170: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
|
|
/* Stop Host */
|
|
(void)USBH_LL_Stop(phost);
|
|
8009174: 6878 ldr r0, [r7, #4]
|
|
8009176: f003 fca0 bl 800caba <USBH_LL_Stop>
|
|
|
|
/* FRee Control Pipes */
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
800917a: 687b ldr r3, [r7, #4]
|
|
800917c: 791b ldrb r3, [r3, #4]
|
|
800917e: 4619 mov r1, r3
|
|
8009180: 6878 ldr r0, [r7, #4]
|
|
8009182: f000 ffc5 bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8009186: 687b ldr r3, [r7, #4]
|
|
8009188: 795b ldrb r3, [r3, #5]
|
|
800918a: 4619 mov r1, r3
|
|
800918c: 6878 ldr r0, [r7, #4]
|
|
800918e: f000 ffbf bl 800a110 <USBH_FreePipe>
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8009192: 2300 movs r3, #0
|
|
8009194: 2200 movs r2, #0
|
|
8009196: 2101 movs r1, #1
|
|
8009198: 6878 ldr r0, [r7, #4]
|
|
800919a: f000 f805 bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
800919e: 2300 movs r3, #0
|
|
}
|
|
80091a0: 4618 mov r0, r3
|
|
80091a2: 3708 adds r7, #8
|
|
80091a4: 46bd mov sp, r7
|
|
80091a6: bd80 pop {r7, pc}
|
|
|
|
080091a8 <USBH_OS_PutMessage>:
|
|
* @param timeout message event timeout
|
|
* @param priority message event priority
|
|
* @retval None
|
|
*/
|
|
void USBH_OS_PutMessage(USBH_HandleTypeDef *phost, USBH_OSEventTypeDef message, uint32_t timeout, uint32_t priority)
|
|
{
|
|
80091a8: b580 push {r7, lr}
|
|
80091aa: b086 sub sp, #24
|
|
80091ac: af00 add r7, sp, #0
|
|
80091ae: 60f8 str r0, [r7, #12]
|
|
80091b0: 607a str r2, [r7, #4]
|
|
80091b2: 603b str r3, [r7, #0]
|
|
80091b4: 460b mov r3, r1
|
|
80091b6: 72fb strb r3, [r7, #11]
|
|
phost->os_msg = (uint32_t)message;
|
|
80091b8: 7afa ldrb r2, [r7, #11]
|
|
80091ba: 68fb ldr r3, [r7, #12]
|
|
80091bc: f8c3 23e0 str.w r2, [r3, #992] @ 0x3e0
|
|
|
|
#if (osCMSIS < 0x20000U)
|
|
UNUSED(priority);
|
|
|
|
/* Calculate the number of available spaces */
|
|
uint32_t available_spaces = MSGQUEUE_OBJECTS - osMessageWaiting(phost->os_event);
|
|
80091c0: 68fb ldr r3, [r7, #12]
|
|
80091c2: f8d3 33d8 ldr.w r3, [r3, #984] @ 0x3d8
|
|
80091c6: 4618 mov r0, r3
|
|
80091c8: f001 f952 bl 800a470 <osMessageWaiting>
|
|
80091cc: 4603 mov r3, r0
|
|
80091ce: f1c3 0310 rsb r3, r3, #16
|
|
80091d2: 617b str r3, [r7, #20]
|
|
|
|
if (available_spaces != 0U)
|
|
80091d4: 697b ldr r3, [r7, #20]
|
|
80091d6: 2b00 cmp r3, #0
|
|
80091d8: d009 beq.n 80091ee <USBH_OS_PutMessage+0x46>
|
|
{
|
|
(void)osMessagePut(phost->os_event, phost->os_msg, timeout);
|
|
80091da: 68fb ldr r3, [r7, #12]
|
|
80091dc: f8d3 03d8 ldr.w r0, [r3, #984] @ 0x3d8
|
|
80091e0: 68fb ldr r3, [r7, #12]
|
|
80091e2: f8d3 33e0 ldr.w r3, [r3, #992] @ 0x3e0
|
|
80091e6: 687a ldr r2, [r7, #4]
|
|
80091e8: 4619 mov r1, r3
|
|
80091ea: f001 f88d bl 800a308 <osMessagePut>
|
|
if (osMessageQueueGetSpace(phost->os_event) != 0U)
|
|
{
|
|
(void)osMessageQueuePut(phost->os_event, &phost->os_msg, priority, timeout);
|
|
}
|
|
#endif /* (osCMSIS < 0x20000U) */
|
|
}
|
|
80091ee: bf00 nop
|
|
80091f0: 3718 adds r7, #24
|
|
80091f2: 46bd mov sp, r7
|
|
80091f4: bd80 pop {r7, pc}
|
|
|
|
080091f6 <USBH_Process_OS>:
|
|
* @param pvParameters not used
|
|
* @retval None
|
|
*/
|
|
#if (osCMSIS < 0x20000U)
|
|
static void USBH_Process_OS(void const *argument)
|
|
{
|
|
80091f6: b580 push {r7, lr}
|
|
80091f8: b086 sub sp, #24
|
|
80091fa: af00 add r7, sp, #0
|
|
80091fc: 6078 str r0, [r7, #4]
|
|
osEvent event;
|
|
|
|
for (;;)
|
|
{
|
|
event = osMessageGet(((USBH_HandleTypeDef *)argument)->os_event, osWaitForever);
|
|
80091fe: 687b ldr r3, [r7, #4]
|
|
8009200: f8d3 13d8 ldr.w r1, [r3, #984] @ 0x3d8
|
|
8009204: f107 030c add.w r3, r7, #12
|
|
8009208: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800920c: 4618 mov r0, r3
|
|
800920e: f001 f8bb bl 800a388 <osMessageGet>
|
|
if (event.status == osEventMessage)
|
|
8009212: 68fb ldr r3, [r7, #12]
|
|
8009214: 2b10 cmp r3, #16
|
|
8009216: d1f2 bne.n 80091fe <USBH_Process_OS+0x8>
|
|
{
|
|
USBH_Process((USBH_HandleTypeDef *)argument);
|
|
8009218: 6878 ldr r0, [r7, #4]
|
|
800921a: f7ff fb0b bl 8008834 <USBH_Process>
|
|
event = osMessageGet(((USBH_HandleTypeDef *)argument)->os_event, osWaitForever);
|
|
800921e: e7ee b.n 80091fe <USBH_Process_OS+0x8>
|
|
|
|
08009220 <USBH_LL_NotifyURBChange>:
|
|
* Notify URB state Change
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost)
|
|
{
|
|
8009220: b580 push {r7, lr}
|
|
8009222: b082 sub sp, #8
|
|
8009224: af00 add r7, sp, #0
|
|
8009226: 6078 str r0, [r7, #4]
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8009228: 2300 movs r3, #0
|
|
800922a: 2200 movs r2, #0
|
|
800922c: 2101 movs r1, #1
|
|
800922e: 6878 ldr r0, [r7, #4]
|
|
8009230: f7ff ffba bl 80091a8 <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
8009234: 2300 movs r3, #0
|
|
}
|
|
8009236: 4618 mov r0, r3
|
|
8009238: 3708 adds r7, #8
|
|
800923a: 46bd mov sp, r7
|
|
800923c: bd80 pop {r7, pc}
|
|
|
|
0800923e <USBH_Get_DevDesc>:
|
|
* @param phost: Host Handle
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Get_DevDesc(USBH_HandleTypeDef *phost, uint16_t length)
|
|
{
|
|
800923e: b580 push {r7, lr}
|
|
8009240: b086 sub sp, #24
|
|
8009242: af02 add r7, sp, #8
|
|
8009244: 6078 str r0, [r7, #4]
|
|
8009246: 460b mov r3, r1
|
|
8009248: 807b strh r3, [r7, #2]
|
|
USBH_StatusTypeDef status;
|
|
|
|
if (length > sizeof(phost->device.Data))
|
|
800924a: 887b ldrh r3, [r7, #2]
|
|
800924c: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8009250: d901 bls.n 8009256 <USBH_Get_DevDesc+0x18>
|
|
{
|
|
USBH_ErrLog("Control error: Get Device Descriptor failed, data buffer size issue");
|
|
return USBH_NOT_SUPPORTED;
|
|
8009252: 2303 movs r3, #3
|
|
8009254: e01b b.n 800928e <USBH_Get_DevDesc+0x50>
|
|
}
|
|
|
|
status = USBH_GetDescriptor(phost,
|
|
USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
|
|
USB_DESC_DEVICE, phost->device.Data, length);
|
|
8009256: 687b ldr r3, [r7, #4]
|
|
8009258: f503 728e add.w r2, r3, #284 @ 0x11c
|
|
status = USBH_GetDescriptor(phost,
|
|
800925c: 887b ldrh r3, [r7, #2]
|
|
800925e: 9300 str r3, [sp, #0]
|
|
8009260: 4613 mov r3, r2
|
|
8009262: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8009266: 2100 movs r1, #0
|
|
8009268: 6878 ldr r0, [r7, #4]
|
|
800926a: f000 f872 bl 8009352 <USBH_GetDescriptor>
|
|
800926e: 4603 mov r3, r0
|
|
8009270: 73fb strb r3, [r7, #15]
|
|
|
|
if (status == USBH_OK)
|
|
8009272: 7bfb ldrb r3, [r7, #15]
|
|
8009274: 2b00 cmp r3, #0
|
|
8009276: d109 bne.n 800928c <USBH_Get_DevDesc+0x4e>
|
|
{
|
|
/* Commands successfully sent and Response Received */
|
|
status = USBH_ParseDevDesc(phost, phost->device.Data, length);
|
|
8009278: 687b ldr r3, [r7, #4]
|
|
800927a: f503 738e add.w r3, r3, #284 @ 0x11c
|
|
800927e: 887a ldrh r2, [r7, #2]
|
|
8009280: 4619 mov r1, r3
|
|
8009282: 6878 ldr r0, [r7, #4]
|
|
8009284: f000 f92a bl 80094dc <USBH_ParseDevDesc>
|
|
8009288: 4603 mov r3, r0
|
|
800928a: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
800928c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800928e: 4618 mov r0, r3
|
|
8009290: 3710 adds r7, #16
|
|
8009292: 46bd mov sp, r7
|
|
8009294: bd80 pop {r7, pc}
|
|
|
|
08009296 <USBH_Get_CfgDesc>:
|
|
* @param phost: Host Handle
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Get_CfgDesc(USBH_HandleTypeDef *phost, uint16_t length)
|
|
{
|
|
8009296: b580 push {r7, lr}
|
|
8009298: b086 sub sp, #24
|
|
800929a: af02 add r7, sp, #8
|
|
800929c: 6078 str r0, [r7, #4]
|
|
800929e: 460b mov r3, r1
|
|
80092a0: 807b strh r3, [r7, #2]
|
|
USBH_StatusTypeDef status;
|
|
uint8_t *pData = phost->device.CfgDesc_Raw;
|
|
80092a2: 687b ldr r3, [r7, #4]
|
|
80092a4: 331c adds r3, #28
|
|
80092a6: 60bb str r3, [r7, #8]
|
|
|
|
if (length > sizeof(phost->device.CfgDesc_Raw))
|
|
80092a8: 887b ldrh r3, [r7, #2]
|
|
80092aa: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80092ae: d901 bls.n 80092b4 <USBH_Get_CfgDesc+0x1e>
|
|
{
|
|
USBH_ErrLog("Control error: Get configuration Descriptor failed, data buffer size issue");
|
|
return USBH_NOT_SUPPORTED;
|
|
80092b0: 2303 movs r3, #3
|
|
80092b2: e016 b.n 80092e2 <USBH_Get_CfgDesc+0x4c>
|
|
}
|
|
|
|
status = USBH_GetDescriptor(phost, (USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD),
|
|
80092b4: 887b ldrh r3, [r7, #2]
|
|
80092b6: 9300 str r3, [sp, #0]
|
|
80092b8: 68bb ldr r3, [r7, #8]
|
|
80092ba: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80092be: 2100 movs r1, #0
|
|
80092c0: 6878 ldr r0, [r7, #4]
|
|
80092c2: f000 f846 bl 8009352 <USBH_GetDescriptor>
|
|
80092c6: 4603 mov r3, r0
|
|
80092c8: 73fb strb r3, [r7, #15]
|
|
USB_DESC_CONFIGURATION, pData, length);
|
|
|
|
if (status == USBH_OK)
|
|
80092ca: 7bfb ldrb r3, [r7, #15]
|
|
80092cc: 2b00 cmp r3, #0
|
|
80092ce: d107 bne.n 80092e0 <USBH_Get_CfgDesc+0x4a>
|
|
{
|
|
/* Commands successfully sent and Response Received */
|
|
status = USBH_ParseCfgDesc(phost, pData, length);
|
|
80092d0: 887b ldrh r3, [r7, #2]
|
|
80092d2: 461a mov r2, r3
|
|
80092d4: 68b9 ldr r1, [r7, #8]
|
|
80092d6: 6878 ldr r0, [r7, #4]
|
|
80092d8: f000 f9b0 bl 800963c <USBH_ParseCfgDesc>
|
|
80092dc: 4603 mov r3, r0
|
|
80092de: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
return status;
|
|
80092e0: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80092e2: 4618 mov r0, r3
|
|
80092e4: 3710 adds r7, #16
|
|
80092e6: 46bd mov sp, r7
|
|
80092e8: bd80 pop {r7, pc}
|
|
|
|
080092ea <USBH_Get_StringDesc>:
|
|
* @param buff: Buffer address for the descriptor
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Get_StringDesc(USBH_HandleTypeDef *phost, uint8_t string_index, uint8_t *buff, uint16_t length)
|
|
{
|
|
80092ea: b580 push {r7, lr}
|
|
80092ec: b088 sub sp, #32
|
|
80092ee: af02 add r7, sp, #8
|
|
80092f0: 60f8 str r0, [r7, #12]
|
|
80092f2: 607a str r2, [r7, #4]
|
|
80092f4: 461a mov r2, r3
|
|
80092f6: 460b mov r3, r1
|
|
80092f8: 72fb strb r3, [r7, #11]
|
|
80092fa: 4613 mov r3, r2
|
|
80092fc: 813b strh r3, [r7, #8]
|
|
USBH_StatusTypeDef status;
|
|
|
|
if ((length > sizeof(phost->device.Data)) || (buff == NULL))
|
|
80092fe: 893b ldrh r3, [r7, #8]
|
|
8009300: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8009304: d802 bhi.n 800930c <USBH_Get_StringDesc+0x22>
|
|
8009306: 687b ldr r3, [r7, #4]
|
|
8009308: 2b00 cmp r3, #0
|
|
800930a: d101 bne.n 8009310 <USBH_Get_StringDesc+0x26>
|
|
{
|
|
USBH_ErrLog("Control error: Get String Descriptor failed, data buffer size issue");
|
|
return USBH_NOT_SUPPORTED;
|
|
800930c: 2303 movs r3, #3
|
|
800930e: e01c b.n 800934a <USBH_Get_StringDesc+0x60>
|
|
}
|
|
|
|
status = USBH_GetDescriptor(phost,
|
|
8009310: 7afb ldrb r3, [r7, #11]
|
|
8009312: b29b uxth r3, r3
|
|
8009314: f443 7340 orr.w r3, r3, #768 @ 0x300
|
|
8009318: b29a uxth r2, r3
|
|
USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD,
|
|
USB_DESC_STRING | string_index,
|
|
phost->device.Data, length);
|
|
800931a: 68fb ldr r3, [r7, #12]
|
|
800931c: f503 718e add.w r1, r3, #284 @ 0x11c
|
|
status = USBH_GetDescriptor(phost,
|
|
8009320: 893b ldrh r3, [r7, #8]
|
|
8009322: 9300 str r3, [sp, #0]
|
|
8009324: 460b mov r3, r1
|
|
8009326: 2100 movs r1, #0
|
|
8009328: 68f8 ldr r0, [r7, #12]
|
|
800932a: f000 f812 bl 8009352 <USBH_GetDescriptor>
|
|
800932e: 4603 mov r3, r0
|
|
8009330: 75fb strb r3, [r7, #23]
|
|
|
|
if (status == USBH_OK)
|
|
8009332: 7dfb ldrb r3, [r7, #23]
|
|
8009334: 2b00 cmp r3, #0
|
|
8009336: d107 bne.n 8009348 <USBH_Get_StringDesc+0x5e>
|
|
{
|
|
/* Commands successfully sent and Response Received */
|
|
USBH_ParseStringDesc(phost->device.Data, buff, length);
|
|
8009338: 68fb ldr r3, [r7, #12]
|
|
800933a: f503 738e add.w r3, r3, #284 @ 0x11c
|
|
800933e: 893a ldrh r2, [r7, #8]
|
|
8009340: 6879 ldr r1, [r7, #4]
|
|
8009342: 4618 mov r0, r3
|
|
8009344: f000 fb8d bl 8009a62 <USBH_ParseStringDesc>
|
|
}
|
|
|
|
return status;
|
|
8009348: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800934a: 4618 mov r0, r3
|
|
800934c: 3718 adds r7, #24
|
|
800934e: 46bd mov sp, r7
|
|
8009350: bd80 pop {r7, pc}
|
|
|
|
08009352 <USBH_GetDescriptor>:
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_GetDescriptor(USBH_HandleTypeDef *phost, uint8_t req_type, uint16_t value_idx,
|
|
uint8_t *buff, uint16_t length)
|
|
{
|
|
8009352: b580 push {r7, lr}
|
|
8009354: b084 sub sp, #16
|
|
8009356: af00 add r7, sp, #0
|
|
8009358: 60f8 str r0, [r7, #12]
|
|
800935a: 607b str r3, [r7, #4]
|
|
800935c: 460b mov r3, r1
|
|
800935e: 72fb strb r3, [r7, #11]
|
|
8009360: 4613 mov r3, r2
|
|
8009362: 813b strh r3, [r7, #8]
|
|
if (phost->RequestState == CMD_SEND)
|
|
8009364: 68fb ldr r3, [r7, #12]
|
|
8009366: 789b ldrb r3, [r3, #2]
|
|
8009368: 2b01 cmp r3, #1
|
|
800936a: d11c bne.n 80093a6 <USBH_GetDescriptor+0x54>
|
|
{
|
|
phost->Control.setup.b.bmRequestType = USB_D2H | req_type;
|
|
800936c: 7afb ldrb r3, [r7, #11]
|
|
800936e: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8009372: b2da uxtb r2, r3
|
|
8009374: 68fb ldr r3, [r7, #12]
|
|
8009376: 741a strb r2, [r3, #16]
|
|
phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR;
|
|
8009378: 68fb ldr r3, [r7, #12]
|
|
800937a: 2206 movs r2, #6
|
|
800937c: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = value_idx;
|
|
800937e: 68fb ldr r3, [r7, #12]
|
|
8009380: 893a ldrh r2, [r7, #8]
|
|
8009382: 825a strh r2, [r3, #18]
|
|
|
|
if ((value_idx & 0xff00U) == USB_DESC_STRING)
|
|
8009384: 893b ldrh r3, [r7, #8]
|
|
8009386: f403 437f and.w r3, r3, #65280 @ 0xff00
|
|
800938a: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
800938e: d104 bne.n 800939a <USBH_GetDescriptor+0x48>
|
|
{
|
|
phost->Control.setup.b.wIndex.w = 0x0409U;
|
|
8009390: 68fb ldr r3, [r7, #12]
|
|
8009392: f240 4209 movw r2, #1033 @ 0x409
|
|
8009396: 829a strh r2, [r3, #20]
|
|
8009398: e002 b.n 80093a0 <USBH_GetDescriptor+0x4e>
|
|
}
|
|
else
|
|
{
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
800939a: 68fb ldr r3, [r7, #12]
|
|
800939c: 2200 movs r2, #0
|
|
800939e: 829a strh r2, [r3, #20]
|
|
}
|
|
phost->Control.setup.b.wLength.w = length;
|
|
80093a0: 68fb ldr r3, [r7, #12]
|
|
80093a2: 8b3a ldrh r2, [r7, #24]
|
|
80093a4: 82da strh r2, [r3, #22]
|
|
}
|
|
|
|
return USBH_CtlReq(phost, buff, length);
|
|
80093a6: 8b3b ldrh r3, [r7, #24]
|
|
80093a8: 461a mov r2, r3
|
|
80093aa: 6879 ldr r1, [r7, #4]
|
|
80093ac: 68f8 ldr r0, [r7, #12]
|
|
80093ae: f000 fba5 bl 8009afc <USBH_CtlReq>
|
|
80093b2: 4603 mov r3, r0
|
|
}
|
|
80093b4: 4618 mov r0, r3
|
|
80093b6: 3710 adds r7, #16
|
|
80093b8: 46bd mov sp, r7
|
|
80093ba: bd80 pop {r7, pc}
|
|
|
|
080093bc <USBH_SetAddress>:
|
|
* @param DeviceAddress: Device address to assign
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_SetAddress(USBH_HandleTypeDef *phost,
|
|
uint8_t DeviceAddress)
|
|
{
|
|
80093bc: b580 push {r7, lr}
|
|
80093be: b082 sub sp, #8
|
|
80093c0: af00 add r7, sp, #0
|
|
80093c2: 6078 str r0, [r7, #4]
|
|
80093c4: 460b mov r3, r1
|
|
80093c6: 70fb strb r3, [r7, #3]
|
|
if (phost->RequestState == CMD_SEND)
|
|
80093c8: 687b ldr r3, [r7, #4]
|
|
80093ca: 789b ldrb r3, [r3, #2]
|
|
80093cc: 2b01 cmp r3, #1
|
|
80093ce: d10f bne.n 80093f0 <USBH_SetAddress+0x34>
|
|
{
|
|
phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \
|
|
80093d0: 687b ldr r3, [r7, #4]
|
|
80093d2: 2200 movs r2, #0
|
|
80093d4: 741a strb r2, [r3, #16]
|
|
USB_REQ_TYPE_STANDARD;
|
|
|
|
phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS;
|
|
80093d6: 687b ldr r3, [r7, #4]
|
|
80093d8: 2205 movs r2, #5
|
|
80093da: 745a strb r2, [r3, #17]
|
|
|
|
phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress;
|
|
80093dc: 78fb ldrb r3, [r7, #3]
|
|
80093de: b29a uxth r2, r3
|
|
80093e0: 687b ldr r3, [r7, #4]
|
|
80093e2: 825a strh r2, [r3, #18]
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
80093e4: 687b ldr r3, [r7, #4]
|
|
80093e6: 2200 movs r2, #0
|
|
80093e8: 829a strh r2, [r3, #20]
|
|
phost->Control.setup.b.wLength.w = 0U;
|
|
80093ea: 687b ldr r3, [r7, #4]
|
|
80093ec: 2200 movs r2, #0
|
|
80093ee: 82da strh r2, [r3, #22]
|
|
}
|
|
|
|
return USBH_CtlReq(phost, NULL, 0U);
|
|
80093f0: 2200 movs r2, #0
|
|
80093f2: 2100 movs r1, #0
|
|
80093f4: 6878 ldr r0, [r7, #4]
|
|
80093f6: f000 fb81 bl 8009afc <USBH_CtlReq>
|
|
80093fa: 4603 mov r3, r0
|
|
}
|
|
80093fc: 4618 mov r0, r3
|
|
80093fe: 3708 adds r7, #8
|
|
8009400: 46bd mov sp, r7
|
|
8009402: bd80 pop {r7, pc}
|
|
|
|
08009404 <USBH_SetCfg>:
|
|
* @param phost: Host Handle
|
|
* @param cfg_idx: Configuration value
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_SetCfg(USBH_HandleTypeDef *phost, uint16_t cfg_idx)
|
|
{
|
|
8009404: b580 push {r7, lr}
|
|
8009406: b082 sub sp, #8
|
|
8009408: af00 add r7, sp, #0
|
|
800940a: 6078 str r0, [r7, #4]
|
|
800940c: 460b mov r3, r1
|
|
800940e: 807b strh r3, [r7, #2]
|
|
if (phost->RequestState == CMD_SEND)
|
|
8009410: 687b ldr r3, [r7, #4]
|
|
8009412: 789b ldrb r3, [r3, #2]
|
|
8009414: 2b01 cmp r3, #1
|
|
8009416: d10e bne.n 8009436 <USBH_SetCfg+0x32>
|
|
{
|
|
phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE
|
|
8009418: 687b ldr r3, [r7, #4]
|
|
800941a: 2200 movs r2, #0
|
|
800941c: 741a strb r2, [r3, #16]
|
|
| USB_REQ_TYPE_STANDARD;
|
|
|
|
phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION;
|
|
800941e: 687b ldr r3, [r7, #4]
|
|
8009420: 2209 movs r2, #9
|
|
8009422: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = cfg_idx;
|
|
8009424: 687b ldr r3, [r7, #4]
|
|
8009426: 887a ldrh r2, [r7, #2]
|
|
8009428: 825a strh r2, [r3, #18]
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
800942a: 687b ldr r3, [r7, #4]
|
|
800942c: 2200 movs r2, #0
|
|
800942e: 829a strh r2, [r3, #20]
|
|
phost->Control.setup.b.wLength.w = 0U;
|
|
8009430: 687b ldr r3, [r7, #4]
|
|
8009432: 2200 movs r2, #0
|
|
8009434: 82da strh r2, [r3, #22]
|
|
}
|
|
|
|
return USBH_CtlReq(phost, NULL, 0U);
|
|
8009436: 2200 movs r2, #0
|
|
8009438: 2100 movs r1, #0
|
|
800943a: 6878 ldr r0, [r7, #4]
|
|
800943c: f000 fb5e bl 8009afc <USBH_CtlReq>
|
|
8009440: 4603 mov r3, r0
|
|
}
|
|
8009442: 4618 mov r0, r3
|
|
8009444: 3708 adds r7, #8
|
|
8009446: 46bd mov sp, r7
|
|
8009448: bd80 pop {r7, pc}
|
|
|
|
0800944a <USBH_SetFeature>:
|
|
* @param pdev: Selected device
|
|
* @param itf_idx
|
|
* @retval Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_SetFeature(USBH_HandleTypeDef *phost, uint8_t wValue)
|
|
{
|
|
800944a: b580 push {r7, lr}
|
|
800944c: b082 sub sp, #8
|
|
800944e: af00 add r7, sp, #0
|
|
8009450: 6078 str r0, [r7, #4]
|
|
8009452: 460b mov r3, r1
|
|
8009454: 70fb strb r3, [r7, #3]
|
|
if (phost->RequestState == CMD_SEND)
|
|
8009456: 687b ldr r3, [r7, #4]
|
|
8009458: 789b ldrb r3, [r3, #2]
|
|
800945a: 2b01 cmp r3, #1
|
|
800945c: d10f bne.n 800947e <USBH_SetFeature+0x34>
|
|
{
|
|
phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE
|
|
800945e: 687b ldr r3, [r7, #4]
|
|
8009460: 2200 movs r2, #0
|
|
8009462: 741a strb r2, [r3, #16]
|
|
| USB_REQ_TYPE_STANDARD;
|
|
|
|
phost->Control.setup.b.bRequest = USB_REQ_SET_FEATURE;
|
|
8009464: 687b ldr r3, [r7, #4]
|
|
8009466: 2203 movs r2, #3
|
|
8009468: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = wValue;
|
|
800946a: 78fb ldrb r3, [r7, #3]
|
|
800946c: b29a uxth r2, r3
|
|
800946e: 687b ldr r3, [r7, #4]
|
|
8009470: 825a strh r2, [r3, #18]
|
|
phost->Control.setup.b.wIndex.w = 0U;
|
|
8009472: 687b ldr r3, [r7, #4]
|
|
8009474: 2200 movs r2, #0
|
|
8009476: 829a strh r2, [r3, #20]
|
|
phost->Control.setup.b.wLength.w = 0U;
|
|
8009478: 687b ldr r3, [r7, #4]
|
|
800947a: 2200 movs r2, #0
|
|
800947c: 82da strh r2, [r3, #22]
|
|
}
|
|
|
|
return USBH_CtlReq(phost, NULL, 0U);
|
|
800947e: 2200 movs r2, #0
|
|
8009480: 2100 movs r1, #0
|
|
8009482: 6878 ldr r0, [r7, #4]
|
|
8009484: f000 fb3a bl 8009afc <USBH_CtlReq>
|
|
8009488: 4603 mov r3, r0
|
|
}
|
|
800948a: 4618 mov r0, r3
|
|
800948c: 3708 adds r7, #8
|
|
800948e: 46bd mov sp, r7
|
|
8009490: bd80 pop {r7, pc}
|
|
|
|
08009492 <USBH_ClrFeature>:
|
|
* @param ep_num: endpoint number
|
|
* @param hc_num: Host channel number
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_ClrFeature(USBH_HandleTypeDef *phost, uint8_t ep_num)
|
|
{
|
|
8009492: b580 push {r7, lr}
|
|
8009494: b082 sub sp, #8
|
|
8009496: af00 add r7, sp, #0
|
|
8009498: 6078 str r0, [r7, #4]
|
|
800949a: 460b mov r3, r1
|
|
800949c: 70fb strb r3, [r7, #3]
|
|
if (phost->RequestState == CMD_SEND)
|
|
800949e: 687b ldr r3, [r7, #4]
|
|
80094a0: 789b ldrb r3, [r3, #2]
|
|
80094a2: 2b01 cmp r3, #1
|
|
80094a4: d10f bne.n 80094c6 <USBH_ClrFeature+0x34>
|
|
{
|
|
phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_ENDPOINT
|
|
80094a6: 687b ldr r3, [r7, #4]
|
|
80094a8: 2202 movs r2, #2
|
|
80094aa: 741a strb r2, [r3, #16]
|
|
| USB_REQ_TYPE_STANDARD;
|
|
|
|
phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE;
|
|
80094ac: 687b ldr r3, [r7, #4]
|
|
80094ae: 2201 movs r2, #1
|
|
80094b0: 745a strb r2, [r3, #17]
|
|
phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT;
|
|
80094b2: 687b ldr r3, [r7, #4]
|
|
80094b4: 2200 movs r2, #0
|
|
80094b6: 825a strh r2, [r3, #18]
|
|
phost->Control.setup.b.wIndex.w = ep_num;
|
|
80094b8: 78fb ldrb r3, [r7, #3]
|
|
80094ba: b29a uxth r2, r3
|
|
80094bc: 687b ldr r3, [r7, #4]
|
|
80094be: 829a strh r2, [r3, #20]
|
|
phost->Control.setup.b.wLength.w = 0U;
|
|
80094c0: 687b ldr r3, [r7, #4]
|
|
80094c2: 2200 movs r2, #0
|
|
80094c4: 82da strh r2, [r3, #22]
|
|
}
|
|
|
|
return USBH_CtlReq(phost, NULL, 0U);
|
|
80094c6: 2200 movs r2, #0
|
|
80094c8: 2100 movs r1, #0
|
|
80094ca: 6878 ldr r0, [r7, #4]
|
|
80094cc: f000 fb16 bl 8009afc <USBH_CtlReq>
|
|
80094d0: 4603 mov r3, r0
|
|
}
|
|
80094d2: 4618 mov r0, r3
|
|
80094d4: 3708 adds r7, #8
|
|
80094d6: 46bd mov sp, r7
|
|
80094d8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080094dc <USBH_ParseDevDesc>:
|
|
* @param buf: Buffer where the source descriptor is available
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_ParseDevDesc(USBH_HandleTypeDef *phost, uint8_t *buf, uint16_t length)
|
|
{
|
|
80094dc: b480 push {r7}
|
|
80094de: b087 sub sp, #28
|
|
80094e0: af00 add r7, sp, #0
|
|
80094e2: 60f8 str r0, [r7, #12]
|
|
80094e4: 60b9 str r1, [r7, #8]
|
|
80094e6: 4613 mov r3, r2
|
|
80094e8: 80fb strh r3, [r7, #6]
|
|
USBH_DevDescTypeDef *dev_desc = &phost->device.DevDesc;
|
|
80094ea: 68fb ldr r3, [r7, #12]
|
|
80094ec: f203 3326 addw r3, r3, #806 @ 0x326
|
|
80094f0: 613b str r3, [r7, #16]
|
|
USBH_StatusTypeDef status = USBH_OK;
|
|
80094f2: 2300 movs r3, #0
|
|
80094f4: 75fb strb r3, [r7, #23]
|
|
|
|
if (buf == NULL)
|
|
80094f6: 68bb ldr r3, [r7, #8]
|
|
80094f8: 2b00 cmp r3, #0
|
|
80094fa: d101 bne.n 8009500 <USBH_ParseDevDesc+0x24>
|
|
{
|
|
return USBH_FAIL;
|
|
80094fc: 2302 movs r3, #2
|
|
80094fe: e094 b.n 800962a <USBH_ParseDevDesc+0x14e>
|
|
}
|
|
|
|
dev_desc->bLength = *(uint8_t *)(buf + 0U);
|
|
8009500: 68bb ldr r3, [r7, #8]
|
|
8009502: 781a ldrb r2, [r3, #0]
|
|
8009504: 693b ldr r3, [r7, #16]
|
|
8009506: 701a strb r2, [r3, #0]
|
|
dev_desc->bDescriptorType = *(uint8_t *)(buf + 1U);
|
|
8009508: 68bb ldr r3, [r7, #8]
|
|
800950a: 785a ldrb r2, [r3, #1]
|
|
800950c: 693b ldr r3, [r7, #16]
|
|
800950e: 705a strb r2, [r3, #1]
|
|
dev_desc->bcdUSB = LE16(buf + 2U);
|
|
8009510: 68bb ldr r3, [r7, #8]
|
|
8009512: 3302 adds r3, #2
|
|
8009514: 781b ldrb r3, [r3, #0]
|
|
8009516: 461a mov r2, r3
|
|
8009518: 68bb ldr r3, [r7, #8]
|
|
800951a: 3303 adds r3, #3
|
|
800951c: 781b ldrb r3, [r3, #0]
|
|
800951e: 021b lsls r3, r3, #8
|
|
8009520: b29b uxth r3, r3
|
|
8009522: 4313 orrs r3, r2
|
|
8009524: b29a uxth r2, r3
|
|
8009526: 693b ldr r3, [r7, #16]
|
|
8009528: 805a strh r2, [r3, #2]
|
|
dev_desc->bDeviceClass = *(uint8_t *)(buf + 4U);
|
|
800952a: 68bb ldr r3, [r7, #8]
|
|
800952c: 791a ldrb r2, [r3, #4]
|
|
800952e: 693b ldr r3, [r7, #16]
|
|
8009530: 711a strb r2, [r3, #4]
|
|
dev_desc->bDeviceSubClass = *(uint8_t *)(buf + 5U);
|
|
8009532: 68bb ldr r3, [r7, #8]
|
|
8009534: 795a ldrb r2, [r3, #5]
|
|
8009536: 693b ldr r3, [r7, #16]
|
|
8009538: 715a strb r2, [r3, #5]
|
|
dev_desc->bDeviceProtocol = *(uint8_t *)(buf + 6U);
|
|
800953a: 68bb ldr r3, [r7, #8]
|
|
800953c: 799a ldrb r2, [r3, #6]
|
|
800953e: 693b ldr r3, [r7, #16]
|
|
8009540: 719a strb r2, [r3, #6]
|
|
dev_desc->bMaxPacketSize = *(uint8_t *)(buf + 7U);
|
|
8009542: 68bb ldr r3, [r7, #8]
|
|
8009544: 79da ldrb r2, [r3, #7]
|
|
8009546: 693b ldr r3, [r7, #16]
|
|
8009548: 71da strb r2, [r3, #7]
|
|
|
|
if ((phost->device.speed == (uint8_t)USBH_SPEED_HIGH) ||
|
|
800954a: 68fb ldr r3, [r7, #12]
|
|
800954c: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8009550: 2b00 cmp r3, #0
|
|
8009552: d004 beq.n 800955e <USBH_ParseDevDesc+0x82>
|
|
(phost->device.speed == (uint8_t)USBH_SPEED_FULL))
|
|
8009554: 68fb ldr r3, [r7, #12]
|
|
8009556: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
if ((phost->device.speed == (uint8_t)USBH_SPEED_HIGH) ||
|
|
800955a: 2b01 cmp r3, #1
|
|
800955c: d11b bne.n 8009596 <USBH_ParseDevDesc+0xba>
|
|
{
|
|
/* Make sure that the max packet size is either 8, 16, 32, 64 or force it to minimum allowed value */
|
|
switch (dev_desc->bMaxPacketSize)
|
|
800955e: 693b ldr r3, [r7, #16]
|
|
8009560: 79db ldrb r3, [r3, #7]
|
|
8009562: 2b20 cmp r3, #32
|
|
8009564: dc0f bgt.n 8009586 <USBH_ParseDevDesc+0xaa>
|
|
8009566: 2b08 cmp r3, #8
|
|
8009568: db0f blt.n 800958a <USBH_ParseDevDesc+0xae>
|
|
800956a: 3b08 subs r3, #8
|
|
800956c: 4a32 ldr r2, [pc, #200] @ (8009638 <USBH_ParseDevDesc+0x15c>)
|
|
800956e: fa22 f303 lsr.w r3, r2, r3
|
|
8009572: f003 0301 and.w r3, r3, #1
|
|
8009576: 2b00 cmp r3, #0
|
|
8009578: bf14 ite ne
|
|
800957a: 2301 movne r3, #1
|
|
800957c: 2300 moveq r3, #0
|
|
800957e: b2db uxtb r3, r3
|
|
8009580: 2b00 cmp r3, #0
|
|
8009582: d106 bne.n 8009592 <USBH_ParseDevDesc+0xb6>
|
|
8009584: e001 b.n 800958a <USBH_ParseDevDesc+0xae>
|
|
8009586: 2b40 cmp r3, #64 @ 0x40
|
|
8009588: d003 beq.n 8009592 <USBH_ParseDevDesc+0xb6>
|
|
case 64:
|
|
break;
|
|
|
|
default:
|
|
/* set the size to min allowed value in case the device has answered with incorrect size */
|
|
dev_desc->bMaxPacketSize = 8U;
|
|
800958a: 693b ldr r3, [r7, #16]
|
|
800958c: 2208 movs r2, #8
|
|
800958e: 71da strb r2, [r3, #7]
|
|
break;
|
|
8009590: e000 b.n 8009594 <USBH_ParseDevDesc+0xb8>
|
|
break;
|
|
8009592: bf00 nop
|
|
switch (dev_desc->bMaxPacketSize)
|
|
8009594: e00e b.n 80095b4 <USBH_ParseDevDesc+0xd8>
|
|
}
|
|
}
|
|
else if (phost->device.speed == (uint8_t)USBH_SPEED_LOW)
|
|
8009596: 68fb ldr r3, [r7, #12]
|
|
8009598: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
800959c: 2b02 cmp r3, #2
|
|
800959e: d107 bne.n 80095b0 <USBH_ParseDevDesc+0xd4>
|
|
{
|
|
if (dev_desc->bMaxPacketSize != 8U)
|
|
80095a0: 693b ldr r3, [r7, #16]
|
|
80095a2: 79db ldrb r3, [r3, #7]
|
|
80095a4: 2b08 cmp r3, #8
|
|
80095a6: d005 beq.n 80095b4 <USBH_ParseDevDesc+0xd8>
|
|
{
|
|
/* set the size to 8 in case the device has answered with incorrect size */
|
|
dev_desc->bMaxPacketSize = 8U;
|
|
80095a8: 693b ldr r3, [r7, #16]
|
|
80095aa: 2208 movs r2, #8
|
|
80095ac: 71da strb r2, [r3, #7]
|
|
80095ae: e001 b.n 80095b4 <USBH_ParseDevDesc+0xd8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
80095b0: 2303 movs r3, #3
|
|
80095b2: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (length > 8U)
|
|
80095b4: 88fb ldrh r3, [r7, #6]
|
|
80095b6: 2b08 cmp r3, #8
|
|
80095b8: d936 bls.n 8009628 <USBH_ParseDevDesc+0x14c>
|
|
{
|
|
/* For 1st time after device connection, Host may issue only 8 bytes for
|
|
Device Descriptor Length */
|
|
dev_desc->idVendor = LE16(buf + 8U);
|
|
80095ba: 68bb ldr r3, [r7, #8]
|
|
80095bc: 3308 adds r3, #8
|
|
80095be: 781b ldrb r3, [r3, #0]
|
|
80095c0: 461a mov r2, r3
|
|
80095c2: 68bb ldr r3, [r7, #8]
|
|
80095c4: 3309 adds r3, #9
|
|
80095c6: 781b ldrb r3, [r3, #0]
|
|
80095c8: 021b lsls r3, r3, #8
|
|
80095ca: b29b uxth r3, r3
|
|
80095cc: 4313 orrs r3, r2
|
|
80095ce: b29a uxth r2, r3
|
|
80095d0: 693b ldr r3, [r7, #16]
|
|
80095d2: 811a strh r2, [r3, #8]
|
|
dev_desc->idProduct = LE16(buf + 10U);
|
|
80095d4: 68bb ldr r3, [r7, #8]
|
|
80095d6: 330a adds r3, #10
|
|
80095d8: 781b ldrb r3, [r3, #0]
|
|
80095da: 461a mov r2, r3
|
|
80095dc: 68bb ldr r3, [r7, #8]
|
|
80095de: 330b adds r3, #11
|
|
80095e0: 781b ldrb r3, [r3, #0]
|
|
80095e2: 021b lsls r3, r3, #8
|
|
80095e4: b29b uxth r3, r3
|
|
80095e6: 4313 orrs r3, r2
|
|
80095e8: b29a uxth r2, r3
|
|
80095ea: 693b ldr r3, [r7, #16]
|
|
80095ec: 815a strh r2, [r3, #10]
|
|
dev_desc->bcdDevice = LE16(buf + 12U);
|
|
80095ee: 68bb ldr r3, [r7, #8]
|
|
80095f0: 330c adds r3, #12
|
|
80095f2: 781b ldrb r3, [r3, #0]
|
|
80095f4: 461a mov r2, r3
|
|
80095f6: 68bb ldr r3, [r7, #8]
|
|
80095f8: 330d adds r3, #13
|
|
80095fa: 781b ldrb r3, [r3, #0]
|
|
80095fc: 021b lsls r3, r3, #8
|
|
80095fe: b29b uxth r3, r3
|
|
8009600: 4313 orrs r3, r2
|
|
8009602: b29a uxth r2, r3
|
|
8009604: 693b ldr r3, [r7, #16]
|
|
8009606: 819a strh r2, [r3, #12]
|
|
dev_desc->iManufacturer = *(uint8_t *)(buf + 14U);
|
|
8009608: 68bb ldr r3, [r7, #8]
|
|
800960a: 7b9a ldrb r2, [r3, #14]
|
|
800960c: 693b ldr r3, [r7, #16]
|
|
800960e: 739a strb r2, [r3, #14]
|
|
dev_desc->iProduct = *(uint8_t *)(buf + 15U);
|
|
8009610: 68bb ldr r3, [r7, #8]
|
|
8009612: 7bda ldrb r2, [r3, #15]
|
|
8009614: 693b ldr r3, [r7, #16]
|
|
8009616: 73da strb r2, [r3, #15]
|
|
dev_desc->iSerialNumber = *(uint8_t *)(buf + 16U);
|
|
8009618: 68bb ldr r3, [r7, #8]
|
|
800961a: 7c1a ldrb r2, [r3, #16]
|
|
800961c: 693b ldr r3, [r7, #16]
|
|
800961e: 741a strb r2, [r3, #16]
|
|
dev_desc->bNumConfigurations = *(uint8_t *)(buf + 17U);
|
|
8009620: 68bb ldr r3, [r7, #8]
|
|
8009622: 7c5a ldrb r2, [r3, #17]
|
|
8009624: 693b ldr r3, [r7, #16]
|
|
8009626: 745a strb r2, [r3, #17]
|
|
}
|
|
|
|
return status;
|
|
8009628: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
800962a: 4618 mov r0, r3
|
|
800962c: 371c adds r7, #28
|
|
800962e: 46bd mov sp, r7
|
|
8009630: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009634: 4770 bx lr
|
|
8009636: bf00 nop
|
|
8009638: 01000101 .word 0x01000101
|
|
|
|
0800963c <USBH_ParseCfgDesc>:
|
|
* @param buf: Buffer where the source descriptor is available
|
|
* @param length: Length of the descriptor
|
|
* @retval USBH status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_ParseCfgDesc(USBH_HandleTypeDef *phost, uint8_t *buf, uint16_t length)
|
|
{
|
|
800963c: b580 push {r7, lr}
|
|
800963e: b08c sub sp, #48 @ 0x30
|
|
8009640: af00 add r7, sp, #0
|
|
8009642: 60f8 str r0, [r7, #12]
|
|
8009644: 60b9 str r1, [r7, #8]
|
|
8009646: 4613 mov r3, r2
|
|
8009648: 80fb strh r3, [r7, #6]
|
|
USBH_CfgDescTypeDef *cfg_desc = &phost->device.CfgDesc;
|
|
800964a: 68fb ldr r3, [r7, #12]
|
|
800964c: f503 734e add.w r3, r3, #824 @ 0x338
|
|
8009650: 623b str r3, [r7, #32]
|
|
USBH_StatusTypeDef status = USBH_OK;
|
|
8009652: 2300 movs r3, #0
|
|
8009654: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
USBH_InterfaceDescTypeDef *pif;
|
|
USBH_EpDescTypeDef *pep;
|
|
USBH_DescHeader_t *pdesc;
|
|
uint16_t ptr;
|
|
uint8_t if_ix = 0U;
|
|
8009658: 2300 movs r3, #0
|
|
800965a: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint8_t ep_ix = 0U;
|
|
800965e: 2300 movs r3, #0
|
|
8009660: f887 3026 strb.w r3, [r7, #38] @ 0x26
|
|
|
|
if (buf == NULL)
|
|
8009664: 68bb ldr r3, [r7, #8]
|
|
8009666: 2b00 cmp r3, #0
|
|
8009668: d101 bne.n 800966e <USBH_ParseCfgDesc+0x32>
|
|
{
|
|
return USBH_FAIL;
|
|
800966a: 2302 movs r3, #2
|
|
800966c: e0de b.n 800982c <USBH_ParseCfgDesc+0x1f0>
|
|
}
|
|
|
|
pdesc = (USBH_DescHeader_t *)(void *)buf;
|
|
800966e: 68bb ldr r3, [r7, #8]
|
|
8009670: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Make sure that the Configuration descriptor's bLength is equal to USB_CONFIGURATION_DESC_SIZE */
|
|
if (pdesc->bLength != USB_CONFIGURATION_DESC_SIZE)
|
|
8009672: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009674: 781b ldrb r3, [r3, #0]
|
|
8009676: 2b09 cmp r3, #9
|
|
8009678: d002 beq.n 8009680 <USBH_ParseCfgDesc+0x44>
|
|
{
|
|
pdesc->bLength = USB_CONFIGURATION_DESC_SIZE;
|
|
800967a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800967c: 2209 movs r2, #9
|
|
800967e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
/* Parse configuration descriptor */
|
|
cfg_desc->bLength = *(uint8_t *)(buf + 0U);
|
|
8009680: 68bb ldr r3, [r7, #8]
|
|
8009682: 781a ldrb r2, [r3, #0]
|
|
8009684: 6a3b ldr r3, [r7, #32]
|
|
8009686: 701a strb r2, [r3, #0]
|
|
cfg_desc->bDescriptorType = *(uint8_t *)(buf + 1U);
|
|
8009688: 68bb ldr r3, [r7, #8]
|
|
800968a: 785a ldrb r2, [r3, #1]
|
|
800968c: 6a3b ldr r3, [r7, #32]
|
|
800968e: 705a strb r2, [r3, #1]
|
|
cfg_desc->wTotalLength = MIN(((uint16_t) LE16(buf + 2U)), ((uint16_t)USBH_MAX_SIZE_CONFIGURATION));
|
|
8009690: 68bb ldr r3, [r7, #8]
|
|
8009692: 3302 adds r3, #2
|
|
8009694: 781b ldrb r3, [r3, #0]
|
|
8009696: 461a mov r2, r3
|
|
8009698: 68bb ldr r3, [r7, #8]
|
|
800969a: 3303 adds r3, #3
|
|
800969c: 781b ldrb r3, [r3, #0]
|
|
800969e: 021b lsls r3, r3, #8
|
|
80096a0: b29b uxth r3, r3
|
|
80096a2: 4313 orrs r3, r2
|
|
80096a4: b29b uxth r3, r3
|
|
80096a6: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80096aa: bf28 it cs
|
|
80096ac: f44f 7380 movcs.w r3, #256 @ 0x100
|
|
80096b0: b29a uxth r2, r3
|
|
80096b2: 6a3b ldr r3, [r7, #32]
|
|
80096b4: 805a strh r2, [r3, #2]
|
|
cfg_desc->bNumInterfaces = *(uint8_t *)(buf + 4U);
|
|
80096b6: 68bb ldr r3, [r7, #8]
|
|
80096b8: 791a ldrb r2, [r3, #4]
|
|
80096ba: 6a3b ldr r3, [r7, #32]
|
|
80096bc: 711a strb r2, [r3, #4]
|
|
cfg_desc->bConfigurationValue = *(uint8_t *)(buf + 5U);
|
|
80096be: 68bb ldr r3, [r7, #8]
|
|
80096c0: 795a ldrb r2, [r3, #5]
|
|
80096c2: 6a3b ldr r3, [r7, #32]
|
|
80096c4: 715a strb r2, [r3, #5]
|
|
cfg_desc->iConfiguration = *(uint8_t *)(buf + 6U);
|
|
80096c6: 68bb ldr r3, [r7, #8]
|
|
80096c8: 799a ldrb r2, [r3, #6]
|
|
80096ca: 6a3b ldr r3, [r7, #32]
|
|
80096cc: 719a strb r2, [r3, #6]
|
|
cfg_desc->bmAttributes = *(uint8_t *)(buf + 7U);
|
|
80096ce: 68bb ldr r3, [r7, #8]
|
|
80096d0: 79da ldrb r2, [r3, #7]
|
|
80096d2: 6a3b ldr r3, [r7, #32]
|
|
80096d4: 71da strb r2, [r3, #7]
|
|
cfg_desc->bMaxPower = *(uint8_t *)(buf + 8U);
|
|
80096d6: 68bb ldr r3, [r7, #8]
|
|
80096d8: 7a1a ldrb r2, [r3, #8]
|
|
80096da: 6a3b ldr r3, [r7, #32]
|
|
80096dc: 721a strb r2, [r3, #8]
|
|
|
|
if (length > USB_CONFIGURATION_DESC_SIZE)
|
|
80096de: 88fb ldrh r3, [r7, #6]
|
|
80096e0: 2b09 cmp r3, #9
|
|
80096e2: f240 80a1 bls.w 8009828 <USBH_ParseCfgDesc+0x1ec>
|
|
{
|
|
ptr = USB_LEN_CFG_DESC;
|
|
80096e6: 2309 movs r3, #9
|
|
80096e8: 82fb strh r3, [r7, #22]
|
|
pif = (USBH_InterfaceDescTypeDef *)NULL;
|
|
80096ea: 2300 movs r3, #0
|
|
80096ec: 61fb str r3, [r7, #28]
|
|
|
|
while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength))
|
|
80096ee: e085 b.n 80097fc <USBH_ParseCfgDesc+0x1c0>
|
|
{
|
|
pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr);
|
|
80096f0: f107 0316 add.w r3, r7, #22
|
|
80096f4: 4619 mov r1, r3
|
|
80096f6: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
80096f8: f000 f9e6 bl 8009ac8 <USBH_GetNextDesc>
|
|
80096fc: 62b8 str r0, [r7, #40] @ 0x28
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE)
|
|
80096fe: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009700: 785b ldrb r3, [r3, #1]
|
|
8009702: 2b04 cmp r3, #4
|
|
8009704: d17a bne.n 80097fc <USBH_ParseCfgDesc+0x1c0>
|
|
{
|
|
/* Make sure that the interface descriptor's bLength is equal to USB_INTERFACE_DESC_SIZE */
|
|
if (pdesc->bLength != USB_INTERFACE_DESC_SIZE)
|
|
8009706: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009708: 781b ldrb r3, [r3, #0]
|
|
800970a: 2b09 cmp r3, #9
|
|
800970c: d002 beq.n 8009714 <USBH_ParseCfgDesc+0xd8>
|
|
{
|
|
pdesc->bLength = USB_INTERFACE_DESC_SIZE;
|
|
800970e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009710: 2209 movs r2, #9
|
|
8009712: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
pif = &cfg_desc->Itf_Desc[if_ix];
|
|
8009714: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8009718: 221a movs r2, #26
|
|
800971a: fb02 f303 mul.w r3, r2, r3
|
|
800971e: 3308 adds r3, #8
|
|
8009720: 6a3a ldr r2, [r7, #32]
|
|
8009722: 4413 add r3, r2
|
|
8009724: 3302 adds r3, #2
|
|
8009726: 61fb str r3, [r7, #28]
|
|
USBH_ParseInterfaceDesc(pif, (uint8_t *)(void *)pdesc);
|
|
8009728: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800972a: 69f8 ldr r0, [r7, #28]
|
|
800972c: f000 f882 bl 8009834 <USBH_ParseInterfaceDesc>
|
|
|
|
ep_ix = 0U;
|
|
8009730: 2300 movs r3, #0
|
|
8009732: f887 3026 strb.w r3, [r7, #38] @ 0x26
|
|
pep = (USBH_EpDescTypeDef *)NULL;
|
|
8009736: 2300 movs r3, #0
|
|
8009738: 61bb str r3, [r7, #24]
|
|
|
|
while ((ep_ix < USBH_MAX_NUM_ENDPOINTS) && (ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength))
|
|
800973a: e043 b.n 80097c4 <USBH_ParseCfgDesc+0x188>
|
|
{
|
|
pdesc = USBH_GetNextDesc((uint8_t *)(void *)pdesc, &ptr);
|
|
800973c: f107 0316 add.w r3, r7, #22
|
|
8009740: 4619 mov r1, r3
|
|
8009742: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8009744: f000 f9c0 bl 8009ac8 <USBH_GetNextDesc>
|
|
8009748: 62b8 str r0, [r7, #40] @ 0x28
|
|
|
|
if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT)
|
|
800974a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800974c: 785b ldrb r3, [r3, #1]
|
|
800974e: 2b05 cmp r3, #5
|
|
8009750: d138 bne.n 80097c4 <USBH_ParseCfgDesc+0x188>
|
|
{
|
|
/* Check if the endpoint is appartening to an audio streaming interface */
|
|
if ((pif->bInterfaceClass == 0x01U) &&
|
|
8009752: 69fb ldr r3, [r7, #28]
|
|
8009754: 795b ldrb r3, [r3, #5]
|
|
8009756: 2b01 cmp r3, #1
|
|
8009758: d113 bne.n 8009782 <USBH_ParseCfgDesc+0x146>
|
|
((pif->bInterfaceSubClass == 0x02U) || (pif->bInterfaceSubClass == 0x03U)))
|
|
800975a: 69fb ldr r3, [r7, #28]
|
|
800975c: 799b ldrb r3, [r3, #6]
|
|
if ((pif->bInterfaceClass == 0x01U) &&
|
|
800975e: 2b02 cmp r3, #2
|
|
8009760: d003 beq.n 800976a <USBH_ParseCfgDesc+0x12e>
|
|
((pif->bInterfaceSubClass == 0x02U) || (pif->bInterfaceSubClass == 0x03U)))
|
|
8009762: 69fb ldr r3, [r7, #28]
|
|
8009764: 799b ldrb r3, [r3, #6]
|
|
8009766: 2b03 cmp r3, #3
|
|
8009768: d10b bne.n 8009782 <USBH_ParseCfgDesc+0x146>
|
|
{
|
|
/* Check if it is supporting the USB AUDIO 01 class specification */
|
|
if ((pif->bInterfaceProtocol == 0x00U) && (pdesc->bLength != 0x09U))
|
|
800976a: 69fb ldr r3, [r7, #28]
|
|
800976c: 79db ldrb r3, [r3, #7]
|
|
800976e: 2b00 cmp r3, #0
|
|
8009770: d10b bne.n 800978a <USBH_ParseCfgDesc+0x14e>
|
|
8009772: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009774: 781b ldrb r3, [r3, #0]
|
|
8009776: 2b09 cmp r3, #9
|
|
8009778: d007 beq.n 800978a <USBH_ParseCfgDesc+0x14e>
|
|
{
|
|
pdesc->bLength = 0x09U;
|
|
800977a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800977c: 2209 movs r2, #9
|
|
800977e: 701a strb r2, [r3, #0]
|
|
if ((pif->bInterfaceProtocol == 0x00U) && (pdesc->bLength != 0x09U))
|
|
8009780: e003 b.n 800978a <USBH_ParseCfgDesc+0x14e>
|
|
}
|
|
/* Make sure that the endpoint descriptor's bLength is equal to
|
|
USB_ENDPOINT_DESC_SIZE for all other endpoints types */
|
|
else
|
|
{
|
|
pdesc->bLength = USB_ENDPOINT_DESC_SIZE;
|
|
8009782: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8009784: 2207 movs r2, #7
|
|
8009786: 701a strb r2, [r3, #0]
|
|
8009788: e000 b.n 800978c <USBH_ParseCfgDesc+0x150>
|
|
if ((pif->bInterfaceProtocol == 0x00U) && (pdesc->bLength != 0x09U))
|
|
800978a: bf00 nop
|
|
}
|
|
|
|
pep = &cfg_desc->Itf_Desc[if_ix].Ep_Desc[ep_ix];
|
|
800978c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8009790: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
|
|
8009794: 3201 adds r2, #1
|
|
8009796: 00d2 lsls r2, r2, #3
|
|
8009798: 211a movs r1, #26
|
|
800979a: fb01 f303 mul.w r3, r1, r3
|
|
800979e: 4413 add r3, r2
|
|
80097a0: 3308 adds r3, #8
|
|
80097a2: 6a3a ldr r2, [r7, #32]
|
|
80097a4: 4413 add r3, r2
|
|
80097a6: 3304 adds r3, #4
|
|
80097a8: 61bb str r3, [r7, #24]
|
|
|
|
status = USBH_ParseEPDesc(phost, pep, (uint8_t *)(void *)pdesc);
|
|
80097aa: 6aba ldr r2, [r7, #40] @ 0x28
|
|
80097ac: 69b9 ldr r1, [r7, #24]
|
|
80097ae: 68f8 ldr r0, [r7, #12]
|
|
80097b0: f000 f86f bl 8009892 <USBH_ParseEPDesc>
|
|
80097b4: 4603 mov r3, r0
|
|
80097b6: f887 302f strb.w r3, [r7, #47] @ 0x2f
|
|
|
|
ep_ix++;
|
|
80097ba: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
80097be: 3301 adds r3, #1
|
|
80097c0: f887 3026 strb.w r3, [r7, #38] @ 0x26
|
|
while ((ep_ix < USBH_MAX_NUM_ENDPOINTS) && (ep_ix < pif->bNumEndpoints) && (ptr < cfg_desc->wTotalLength))
|
|
80097c4: f897 3026 ldrb.w r3, [r7, #38] @ 0x26
|
|
80097c8: 2b01 cmp r3, #1
|
|
80097ca: d80a bhi.n 80097e2 <USBH_ParseCfgDesc+0x1a6>
|
|
80097cc: 69fb ldr r3, [r7, #28]
|
|
80097ce: 791b ldrb r3, [r3, #4]
|
|
80097d0: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
|
|
80097d4: 429a cmp r2, r3
|
|
80097d6: d204 bcs.n 80097e2 <USBH_ParseCfgDesc+0x1a6>
|
|
80097d8: 6a3b ldr r3, [r7, #32]
|
|
80097da: 885a ldrh r2, [r3, #2]
|
|
80097dc: 8afb ldrh r3, [r7, #22]
|
|
80097de: 429a cmp r2, r3
|
|
80097e0: d8ac bhi.n 800973c <USBH_ParseCfgDesc+0x100>
|
|
}
|
|
}
|
|
|
|
/* Check if the required endpoint(s) data are parsed */
|
|
if (ep_ix < pif->bNumEndpoints)
|
|
80097e2: 69fb ldr r3, [r7, #28]
|
|
80097e4: 791b ldrb r3, [r3, #4]
|
|
80097e6: f897 2026 ldrb.w r2, [r7, #38] @ 0x26
|
|
80097ea: 429a cmp r2, r3
|
|
80097ec: d201 bcs.n 80097f2 <USBH_ParseCfgDesc+0x1b6>
|
|
{
|
|
return USBH_NOT_SUPPORTED;
|
|
80097ee: 2303 movs r3, #3
|
|
80097f0: e01c b.n 800982c <USBH_ParseCfgDesc+0x1f0>
|
|
}
|
|
|
|
if_ix++;
|
|
80097f2: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80097f6: 3301 adds r3, #1
|
|
80097f8: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
while ((if_ix < USBH_MAX_NUM_INTERFACES) && (ptr < cfg_desc->wTotalLength))
|
|
80097fc: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8009800: 2b01 cmp r3, #1
|
|
8009802: d805 bhi.n 8009810 <USBH_ParseCfgDesc+0x1d4>
|
|
8009804: 6a3b ldr r3, [r7, #32]
|
|
8009806: 885a ldrh r2, [r3, #2]
|
|
8009808: 8afb ldrh r3, [r7, #22]
|
|
800980a: 429a cmp r2, r3
|
|
800980c: f63f af70 bhi.w 80096f0 <USBH_ParseCfgDesc+0xb4>
|
|
}
|
|
}
|
|
|
|
/* Check if the required interface(s) data are parsed */
|
|
if (if_ix < MIN(cfg_desc->bNumInterfaces, (uint8_t)USBH_MAX_NUM_INTERFACES))
|
|
8009810: 6a3b ldr r3, [r7, #32]
|
|
8009812: 791b ldrb r3, [r3, #4]
|
|
8009814: 2b02 cmp r3, #2
|
|
8009816: bf28 it cs
|
|
8009818: 2302 movcs r3, #2
|
|
800981a: b2db uxtb r3, r3
|
|
800981c: f897 2027 ldrb.w r2, [r7, #39] @ 0x27
|
|
8009820: 429a cmp r2, r3
|
|
8009822: d201 bcs.n 8009828 <USBH_ParseCfgDesc+0x1ec>
|
|
{
|
|
return USBH_NOT_SUPPORTED;
|
|
8009824: 2303 movs r3, #3
|
|
8009826: e001 b.n 800982c <USBH_ParseCfgDesc+0x1f0>
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8009828: f897 302f ldrb.w r3, [r7, #47] @ 0x2f
|
|
}
|
|
800982c: 4618 mov r0, r3
|
|
800982e: 3730 adds r7, #48 @ 0x30
|
|
8009830: 46bd mov sp, r7
|
|
8009832: bd80 pop {r7, pc}
|
|
|
|
08009834 <USBH_ParseInterfaceDesc>:
|
|
* @param if_descriptor : Interface descriptor destination
|
|
* @param buf: Buffer where the descriptor data is available
|
|
* @retval None
|
|
*/
|
|
static void USBH_ParseInterfaceDesc(USBH_InterfaceDescTypeDef *if_descriptor, uint8_t *buf)
|
|
{
|
|
8009834: b480 push {r7}
|
|
8009836: b083 sub sp, #12
|
|
8009838: af00 add r7, sp, #0
|
|
800983a: 6078 str r0, [r7, #4]
|
|
800983c: 6039 str r1, [r7, #0]
|
|
if_descriptor->bLength = *(uint8_t *)(buf + 0U);
|
|
800983e: 683b ldr r3, [r7, #0]
|
|
8009840: 781a ldrb r2, [r3, #0]
|
|
8009842: 687b ldr r3, [r7, #4]
|
|
8009844: 701a strb r2, [r3, #0]
|
|
if_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U);
|
|
8009846: 683b ldr r3, [r7, #0]
|
|
8009848: 785a ldrb r2, [r3, #1]
|
|
800984a: 687b ldr r3, [r7, #4]
|
|
800984c: 705a strb r2, [r3, #1]
|
|
if_descriptor->bInterfaceNumber = *(uint8_t *)(buf + 2U);
|
|
800984e: 683b ldr r3, [r7, #0]
|
|
8009850: 789a ldrb r2, [r3, #2]
|
|
8009852: 687b ldr r3, [r7, #4]
|
|
8009854: 709a strb r2, [r3, #2]
|
|
if_descriptor->bAlternateSetting = *(uint8_t *)(buf + 3U);
|
|
8009856: 683b ldr r3, [r7, #0]
|
|
8009858: 78da ldrb r2, [r3, #3]
|
|
800985a: 687b ldr r3, [r7, #4]
|
|
800985c: 70da strb r2, [r3, #3]
|
|
if_descriptor->bNumEndpoints = *(uint8_t *)(buf + 4U);
|
|
800985e: 683b ldr r3, [r7, #0]
|
|
8009860: 791a ldrb r2, [r3, #4]
|
|
8009862: 687b ldr r3, [r7, #4]
|
|
8009864: 711a strb r2, [r3, #4]
|
|
if_descriptor->bInterfaceClass = *(uint8_t *)(buf + 5U);
|
|
8009866: 683b ldr r3, [r7, #0]
|
|
8009868: 795a ldrb r2, [r3, #5]
|
|
800986a: 687b ldr r3, [r7, #4]
|
|
800986c: 715a strb r2, [r3, #5]
|
|
if_descriptor->bInterfaceSubClass = *(uint8_t *)(buf + 6U);
|
|
800986e: 683b ldr r3, [r7, #0]
|
|
8009870: 799a ldrb r2, [r3, #6]
|
|
8009872: 687b ldr r3, [r7, #4]
|
|
8009874: 719a strb r2, [r3, #6]
|
|
if_descriptor->bInterfaceProtocol = *(uint8_t *)(buf + 7U);
|
|
8009876: 683b ldr r3, [r7, #0]
|
|
8009878: 79da ldrb r2, [r3, #7]
|
|
800987a: 687b ldr r3, [r7, #4]
|
|
800987c: 71da strb r2, [r3, #7]
|
|
if_descriptor->iInterface = *(uint8_t *)(buf + 8U);
|
|
800987e: 683b ldr r3, [r7, #0]
|
|
8009880: 7a1a ldrb r2, [r3, #8]
|
|
8009882: 687b ldr r3, [r7, #4]
|
|
8009884: 721a strb r2, [r3, #8]
|
|
}
|
|
8009886: bf00 nop
|
|
8009888: 370c adds r7, #12
|
|
800988a: 46bd mov sp, r7
|
|
800988c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009890: 4770 bx lr
|
|
|
|
08009892 <USBH_ParseEPDesc>:
|
|
* @param ep_descriptor: Endpoint descriptor destination address
|
|
* @param buf: Buffer where the parsed descriptor stored
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_ParseEPDesc(USBH_HandleTypeDef *phost, USBH_EpDescTypeDef *ep_descriptor, uint8_t *buf)
|
|
{
|
|
8009892: b480 push {r7}
|
|
8009894: b087 sub sp, #28
|
|
8009896: af00 add r7, sp, #0
|
|
8009898: 60f8 str r0, [r7, #12]
|
|
800989a: 60b9 str r1, [r7, #8]
|
|
800989c: 607a str r2, [r7, #4]
|
|
USBH_StatusTypeDef status = USBH_OK;
|
|
800989e: 2300 movs r3, #0
|
|
80098a0: 75fb strb r3, [r7, #23]
|
|
|
|
ep_descriptor->bLength = *(uint8_t *)(buf + 0U);
|
|
80098a2: 687b ldr r3, [r7, #4]
|
|
80098a4: 781a ldrb r2, [r3, #0]
|
|
80098a6: 68bb ldr r3, [r7, #8]
|
|
80098a8: 701a strb r2, [r3, #0]
|
|
ep_descriptor->bDescriptorType = *(uint8_t *)(buf + 1U);
|
|
80098aa: 687b ldr r3, [r7, #4]
|
|
80098ac: 785a ldrb r2, [r3, #1]
|
|
80098ae: 68bb ldr r3, [r7, #8]
|
|
80098b0: 705a strb r2, [r3, #1]
|
|
ep_descriptor->bEndpointAddress = *(uint8_t *)(buf + 2U);
|
|
80098b2: 687b ldr r3, [r7, #4]
|
|
80098b4: 789a ldrb r2, [r3, #2]
|
|
80098b6: 68bb ldr r3, [r7, #8]
|
|
80098b8: 709a strb r2, [r3, #2]
|
|
ep_descriptor->bmAttributes = *(uint8_t *)(buf + 3U);
|
|
80098ba: 687b ldr r3, [r7, #4]
|
|
80098bc: 78da ldrb r2, [r3, #3]
|
|
80098be: 68bb ldr r3, [r7, #8]
|
|
80098c0: 70da strb r2, [r3, #3]
|
|
ep_descriptor->wMaxPacketSize = LE16(buf + 4U);
|
|
80098c2: 687b ldr r3, [r7, #4]
|
|
80098c4: 3304 adds r3, #4
|
|
80098c6: 781b ldrb r3, [r3, #0]
|
|
80098c8: 461a mov r2, r3
|
|
80098ca: 687b ldr r3, [r7, #4]
|
|
80098cc: 3305 adds r3, #5
|
|
80098ce: 781b ldrb r3, [r3, #0]
|
|
80098d0: 021b lsls r3, r3, #8
|
|
80098d2: b29b uxth r3, r3
|
|
80098d4: 4313 orrs r3, r2
|
|
80098d6: b29a uxth r2, r3
|
|
80098d8: 68bb ldr r3, [r7, #8]
|
|
80098da: 809a strh r2, [r3, #4]
|
|
ep_descriptor->bInterval = *(uint8_t *)(buf + 6U);
|
|
80098dc: 687b ldr r3, [r7, #4]
|
|
80098de: 799a ldrb r2, [r3, #6]
|
|
80098e0: 68bb ldr r3, [r7, #8]
|
|
80098e2: 719a strb r2, [r3, #6]
|
|
|
|
/* Make sure that wMaxPacketSize is different from 0 */
|
|
if ((ep_descriptor->wMaxPacketSize == 0x00U) ||
|
|
80098e4: 68bb ldr r3, [r7, #8]
|
|
80098e6: 889b ldrh r3, [r3, #4]
|
|
80098e8: 2b00 cmp r3, #0
|
|
80098ea: d009 beq.n 8009900 <USBH_ParseEPDesc+0x6e>
|
|
(ep_descriptor->wMaxPacketSize > USBH_MAX_EP_PACKET_SIZE) ||
|
|
80098ec: 68bb ldr r3, [r7, #8]
|
|
80098ee: 889b ldrh r3, [r3, #4]
|
|
if ((ep_descriptor->wMaxPacketSize == 0x00U) ||
|
|
80098f0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80098f4: d804 bhi.n 8009900 <USBH_ParseEPDesc+0x6e>
|
|
(ep_descriptor->wMaxPacketSize > USBH_MAX_DATA_BUFFER))
|
|
80098f6: 68bb ldr r3, [r7, #8]
|
|
80098f8: 889b ldrh r3, [r3, #4]
|
|
(ep_descriptor->wMaxPacketSize > USBH_MAX_EP_PACKET_SIZE) ||
|
|
80098fa: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80098fe: d901 bls.n 8009904 <USBH_ParseEPDesc+0x72>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009900: 2303 movs r3, #3
|
|
8009902: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (phost->device.speed == (uint8_t)USBH_SPEED_HIGH)
|
|
8009904: 68fb ldr r3, [r7, #12]
|
|
8009906: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
800990a: 2b00 cmp r3, #0
|
|
800990c: d136 bne.n 800997c <USBH_ParseEPDesc+0xea>
|
|
{
|
|
if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK)
|
|
800990e: 68bb ldr r3, [r7, #8]
|
|
8009910: 78db ldrb r3, [r3, #3]
|
|
8009912: f003 0303 and.w r3, r3, #3
|
|
8009916: 2b02 cmp r3, #2
|
|
8009918: d108 bne.n 800992c <USBH_ParseEPDesc+0x9a>
|
|
{
|
|
if (ep_descriptor->wMaxPacketSize > 512U)
|
|
800991a: 68bb ldr r3, [r7, #8]
|
|
800991c: 889b ldrh r3, [r3, #4]
|
|
800991e: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8009922: f240 8097 bls.w 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009926: 2303 movs r3, #3
|
|
8009928: 75fb strb r3, [r7, #23]
|
|
800992a: e093 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_CTRL)
|
|
800992c: 68bb ldr r3, [r7, #8]
|
|
800992e: 78db ldrb r3, [r3, #3]
|
|
8009930: f003 0303 and.w r3, r3, #3
|
|
8009934: 2b00 cmp r3, #0
|
|
8009936: d107 bne.n 8009948 <USBH_ParseEPDesc+0xb6>
|
|
{
|
|
if (ep_descriptor->wMaxPacketSize > 64U)
|
|
8009938: 68bb ldr r3, [r7, #8]
|
|
800993a: 889b ldrh r3, [r3, #4]
|
|
800993c: 2b40 cmp r3, #64 @ 0x40
|
|
800993e: f240 8089 bls.w 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009942: 2303 movs r3, #3
|
|
8009944: 75fb strb r3, [r7, #23]
|
|
8009946: e085 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
/* For high-speed interrupt/isochronous endpoints, bInterval can vary from 1 to 16 */
|
|
else if (((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_ISOC) ||
|
|
8009948: 68bb ldr r3, [r7, #8]
|
|
800994a: 78db ldrb r3, [r3, #3]
|
|
800994c: f003 0303 and.w r3, r3, #3
|
|
8009950: 2b01 cmp r3, #1
|
|
8009952: d005 beq.n 8009960 <USBH_ParseEPDesc+0xce>
|
|
((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR))
|
|
8009954: 68bb ldr r3, [r7, #8]
|
|
8009956: 78db ldrb r3, [r3, #3]
|
|
8009958: f003 0303 and.w r3, r3, #3
|
|
else if (((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_ISOC) ||
|
|
800995c: 2b03 cmp r3, #3
|
|
800995e: d10a bne.n 8009976 <USBH_ParseEPDesc+0xe4>
|
|
{
|
|
if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->bInterval > 0x10U))
|
|
8009960: 68bb ldr r3, [r7, #8]
|
|
8009962: 799b ldrb r3, [r3, #6]
|
|
8009964: 2b00 cmp r3, #0
|
|
8009966: d003 beq.n 8009970 <USBH_ParseEPDesc+0xde>
|
|
8009968: 68bb ldr r3, [r7, #8]
|
|
800996a: 799b ldrb r3, [r3, #6]
|
|
800996c: 2b10 cmp r3, #16
|
|
800996e: d970 bls.n 8009a52 <USBH_ParseEPDesc+0x1c0>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009970: 2303 movs r3, #3
|
|
8009972: 75fb strb r3, [r7, #23]
|
|
if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->bInterval > 0x10U))
|
|
8009974: e06d b.n 8009a52 <USBH_ParseEPDesc+0x1c0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009976: 2303 movs r3, #3
|
|
8009978: 75fb strb r3, [r7, #23]
|
|
800997a: e06b b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else if (phost->device.speed == (uint8_t)USBH_SPEED_FULL)
|
|
800997c: 68fb ldr r3, [r7, #12]
|
|
800997e: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8009982: 2b01 cmp r3, #1
|
|
8009984: d13c bne.n 8009a00 <USBH_ParseEPDesc+0x16e>
|
|
{
|
|
if (((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK) ||
|
|
8009986: 68bb ldr r3, [r7, #8]
|
|
8009988: 78db ldrb r3, [r3, #3]
|
|
800998a: f003 0303 and.w r3, r3, #3
|
|
800998e: 2b02 cmp r3, #2
|
|
8009990: d005 beq.n 800999e <USBH_ParseEPDesc+0x10c>
|
|
((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_CTRL))
|
|
8009992: 68bb ldr r3, [r7, #8]
|
|
8009994: 78db ldrb r3, [r3, #3]
|
|
8009996: f003 0303 and.w r3, r3, #3
|
|
if (((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_BULK) ||
|
|
800999a: 2b00 cmp r3, #0
|
|
800999c: d106 bne.n 80099ac <USBH_ParseEPDesc+0x11a>
|
|
{
|
|
if (ep_descriptor->wMaxPacketSize > 64U)
|
|
800999e: 68bb ldr r3, [r7, #8]
|
|
80099a0: 889b ldrh r3, [r3, #4]
|
|
80099a2: 2b40 cmp r3, #64 @ 0x40
|
|
80099a4: d956 bls.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
80099a6: 2303 movs r3, #3
|
|
80099a8: 75fb strb r3, [r7, #23]
|
|
if (ep_descriptor->wMaxPacketSize > 64U)
|
|
80099aa: e053 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
/* For full-speed isochronous endpoints, the value of bInterval must be in the range from 1 to 16.*/
|
|
else if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_ISOC)
|
|
80099ac: 68bb ldr r3, [r7, #8]
|
|
80099ae: 78db ldrb r3, [r3, #3]
|
|
80099b0: f003 0303 and.w r3, r3, #3
|
|
80099b4: 2b01 cmp r3, #1
|
|
80099b6: d10e bne.n 80099d6 <USBH_ParseEPDesc+0x144>
|
|
{
|
|
if ((ep_descriptor->bInterval == 0U) ||
|
|
80099b8: 68bb ldr r3, [r7, #8]
|
|
80099ba: 799b ldrb r3, [r3, #6]
|
|
80099bc: 2b00 cmp r3, #0
|
|
80099be: d007 beq.n 80099d0 <USBH_ParseEPDesc+0x13e>
|
|
(ep_descriptor->bInterval > 0x10U) ||
|
|
80099c0: 68bb ldr r3, [r7, #8]
|
|
80099c2: 799b ldrb r3, [r3, #6]
|
|
if ((ep_descriptor->bInterval == 0U) ||
|
|
80099c4: 2b10 cmp r3, #16
|
|
80099c6: d803 bhi.n 80099d0 <USBH_ParseEPDesc+0x13e>
|
|
(ep_descriptor->wMaxPacketSize > 64U))
|
|
80099c8: 68bb ldr r3, [r7, #8]
|
|
80099ca: 889b ldrh r3, [r3, #4]
|
|
(ep_descriptor->bInterval > 0x10U) ||
|
|
80099cc: 2b40 cmp r3, #64 @ 0x40
|
|
80099ce: d941 bls.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
80099d0: 2303 movs r3, #3
|
|
80099d2: 75fb strb r3, [r7, #23]
|
|
80099d4: e03e b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
/* For full-speed interrupt endpoints, the value of bInterval may be from 1 to 255.*/
|
|
else if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR)
|
|
80099d6: 68bb ldr r3, [r7, #8]
|
|
80099d8: 78db ldrb r3, [r3, #3]
|
|
80099da: f003 0303 and.w r3, r3, #3
|
|
80099de: 2b03 cmp r3, #3
|
|
80099e0: d10b bne.n 80099fa <USBH_ParseEPDesc+0x168>
|
|
{
|
|
if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->wMaxPacketSize > 1023U))
|
|
80099e2: 68bb ldr r3, [r7, #8]
|
|
80099e4: 799b ldrb r3, [r3, #6]
|
|
80099e6: 2b00 cmp r3, #0
|
|
80099e8: d004 beq.n 80099f4 <USBH_ParseEPDesc+0x162>
|
|
80099ea: 68bb ldr r3, [r7, #8]
|
|
80099ec: 889b ldrh r3, [r3, #4]
|
|
80099ee: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
80099f2: d32f bcc.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
80099f4: 2303 movs r3, #3
|
|
80099f6: 75fb strb r3, [r7, #23]
|
|
80099f8: e02c b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
80099fa: 2303 movs r3, #3
|
|
80099fc: 75fb strb r3, [r7, #23]
|
|
80099fe: e029 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else if (phost->device.speed == (uint8_t)USBH_SPEED_LOW)
|
|
8009a00: 68fb ldr r3, [r7, #12]
|
|
8009a02: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8009a06: 2b02 cmp r3, #2
|
|
8009a08: d120 bne.n 8009a4c <USBH_ParseEPDesc+0x1ba>
|
|
{
|
|
if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_CTRL)
|
|
8009a0a: 68bb ldr r3, [r7, #8]
|
|
8009a0c: 78db ldrb r3, [r3, #3]
|
|
8009a0e: f003 0303 and.w r3, r3, #3
|
|
8009a12: 2b00 cmp r3, #0
|
|
8009a14: d106 bne.n 8009a24 <USBH_ParseEPDesc+0x192>
|
|
{
|
|
if (ep_descriptor->wMaxPacketSize != 8U)
|
|
8009a16: 68bb ldr r3, [r7, #8]
|
|
8009a18: 889b ldrh r3, [r3, #4]
|
|
8009a1a: 2b08 cmp r3, #8
|
|
8009a1c: d01a beq.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009a1e: 2303 movs r3, #3
|
|
8009a20: 75fb strb r3, [r7, #23]
|
|
8009a22: e017 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
/* For low-speed interrupt endpoints, the value of bInterval may be from 1 to 255.*/
|
|
else if ((ep_descriptor->bmAttributes & EP_TYPE_MSK) == EP_TYPE_INTR)
|
|
8009a24: 68bb ldr r3, [r7, #8]
|
|
8009a26: 78db ldrb r3, [r3, #3]
|
|
8009a28: f003 0303 and.w r3, r3, #3
|
|
8009a2c: 2b03 cmp r3, #3
|
|
8009a2e: d10a bne.n 8009a46 <USBH_ParseEPDesc+0x1b4>
|
|
{
|
|
if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->wMaxPacketSize > 8U))
|
|
8009a30: 68bb ldr r3, [r7, #8]
|
|
8009a32: 799b ldrb r3, [r3, #6]
|
|
8009a34: 2b00 cmp r3, #0
|
|
8009a36: d003 beq.n 8009a40 <USBH_ParseEPDesc+0x1ae>
|
|
8009a38: 68bb ldr r3, [r7, #8]
|
|
8009a3a: 889b ldrh r3, [r3, #4]
|
|
8009a3c: 2b08 cmp r3, #8
|
|
8009a3e: d909 bls.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009a40: 2303 movs r3, #3
|
|
8009a42: 75fb strb r3, [r7, #23]
|
|
8009a44: e006 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009a46: 2303 movs r3, #3
|
|
8009a48: 75fb strb r3, [r7, #23]
|
|
8009a4a: e003 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009a4c: 2303 movs r3, #3
|
|
8009a4e: 75fb strb r3, [r7, #23]
|
|
8009a50: e000 b.n 8009a54 <USBH_ParseEPDesc+0x1c2>
|
|
if ((ep_descriptor->bInterval == 0U) || (ep_descriptor->bInterval > 0x10U))
|
|
8009a52: bf00 nop
|
|
}
|
|
|
|
return status;
|
|
8009a54: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8009a56: 4618 mov r0, r3
|
|
8009a58: 371c adds r7, #28
|
|
8009a5a: 46bd mov sp, r7
|
|
8009a5c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009a60: 4770 bx lr
|
|
|
|
08009a62 <USBH_ParseStringDesc>:
|
|
* @param pdest: Destination address pointer
|
|
* @param length: Length of the descriptor
|
|
* @retval None
|
|
*/
|
|
static void USBH_ParseStringDesc(uint8_t *psrc, uint8_t *pdest, uint16_t length)
|
|
{
|
|
8009a62: b480 push {r7}
|
|
8009a64: b087 sub sp, #28
|
|
8009a66: af00 add r7, sp, #0
|
|
8009a68: 60f8 str r0, [r7, #12]
|
|
8009a6a: 60b9 str r1, [r7, #8]
|
|
8009a6c: 4613 mov r3, r2
|
|
8009a6e: 80fb strh r3, [r7, #6]
|
|
*/
|
|
|
|
/* Check which is lower size, the Size of string or the length of bytes read
|
|
from the device */
|
|
|
|
if (psrc[1] == USB_DESC_TYPE_STRING)
|
|
8009a70: 68fb ldr r3, [r7, #12]
|
|
8009a72: 3301 adds r3, #1
|
|
8009a74: 781b ldrb r3, [r3, #0]
|
|
8009a76: 2b03 cmp r3, #3
|
|
8009a78: d120 bne.n 8009abc <USBH_ParseStringDesc+0x5a>
|
|
{
|
|
/* Make sure the Descriptor is String Type */
|
|
|
|
/* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */
|
|
strlength = ((((uint16_t)psrc[0] - 2U) <= length) ? ((uint16_t)psrc[0] - 2U) : length);
|
|
8009a7a: 68fb ldr r3, [r7, #12]
|
|
8009a7c: 781b ldrb r3, [r3, #0]
|
|
8009a7e: 1e9a subs r2, r3, #2
|
|
8009a80: 88fb ldrh r3, [r7, #6]
|
|
8009a82: 4293 cmp r3, r2
|
|
8009a84: bf28 it cs
|
|
8009a86: 4613 movcs r3, r2
|
|
8009a88: 82bb strh r3, [r7, #20]
|
|
|
|
/* Adjust the offset ignoring the String Len and Descriptor type */
|
|
psrc += 2U;
|
|
8009a8a: 68fb ldr r3, [r7, #12]
|
|
8009a8c: 3302 adds r3, #2
|
|
8009a8e: 60fb str r3, [r7, #12]
|
|
|
|
for (idx = 0U; idx < strlength; idx += 2U)
|
|
8009a90: 2300 movs r3, #0
|
|
8009a92: 82fb strh r3, [r7, #22]
|
|
8009a94: e00b b.n 8009aae <USBH_ParseStringDesc+0x4c>
|
|
{
|
|
/* Copy Only the string and ignore the UNICODE ID, hence add the src */
|
|
*pdest = psrc[idx];
|
|
8009a96: 8afb ldrh r3, [r7, #22]
|
|
8009a98: 68fa ldr r2, [r7, #12]
|
|
8009a9a: 4413 add r3, r2
|
|
8009a9c: 781a ldrb r2, [r3, #0]
|
|
8009a9e: 68bb ldr r3, [r7, #8]
|
|
8009aa0: 701a strb r2, [r3, #0]
|
|
pdest++;
|
|
8009aa2: 68bb ldr r3, [r7, #8]
|
|
8009aa4: 3301 adds r3, #1
|
|
8009aa6: 60bb str r3, [r7, #8]
|
|
for (idx = 0U; idx < strlength; idx += 2U)
|
|
8009aa8: 8afb ldrh r3, [r7, #22]
|
|
8009aaa: 3302 adds r3, #2
|
|
8009aac: 82fb strh r3, [r7, #22]
|
|
8009aae: 8afa ldrh r2, [r7, #22]
|
|
8009ab0: 8abb ldrh r3, [r7, #20]
|
|
8009ab2: 429a cmp r2, r3
|
|
8009ab4: d3ef bcc.n 8009a96 <USBH_ParseStringDesc+0x34>
|
|
}
|
|
*pdest = 0U; /* mark end of string */
|
|
8009ab6: 68bb ldr r3, [r7, #8]
|
|
8009ab8: 2200 movs r2, #0
|
|
8009aba: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
8009abc: bf00 nop
|
|
8009abe: 371c adds r7, #28
|
|
8009ac0: 46bd mov sp, r7
|
|
8009ac2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009ac6: 4770 bx lr
|
|
|
|
08009ac8 <USBH_GetNextDesc>:
|
|
* @param buf: Buffer where the cfg descriptor is available
|
|
* @param ptr: data pointer inside the cfg descriptor
|
|
* @retval next header
|
|
*/
|
|
USBH_DescHeader_t *USBH_GetNextDesc(uint8_t *pbuf, uint16_t *ptr)
|
|
{
|
|
8009ac8: b480 push {r7}
|
|
8009aca: b085 sub sp, #20
|
|
8009acc: af00 add r7, sp, #0
|
|
8009ace: 6078 str r0, [r7, #4]
|
|
8009ad0: 6039 str r1, [r7, #0]
|
|
USBH_DescHeader_t *pnext;
|
|
|
|
*ptr += ((USBH_DescHeader_t *)(void *)pbuf)->bLength;
|
|
8009ad2: 683b ldr r3, [r7, #0]
|
|
8009ad4: 881b ldrh r3, [r3, #0]
|
|
8009ad6: 687a ldr r2, [r7, #4]
|
|
8009ad8: 7812 ldrb r2, [r2, #0]
|
|
8009ada: 4413 add r3, r2
|
|
8009adc: b29a uxth r2, r3
|
|
8009ade: 683b ldr r3, [r7, #0]
|
|
8009ae0: 801a strh r2, [r3, #0]
|
|
pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \
|
|
((USBH_DescHeader_t *)(void *)pbuf)->bLength);
|
|
8009ae2: 687b ldr r3, [r7, #4]
|
|
8009ae4: 781b ldrb r3, [r3, #0]
|
|
8009ae6: 461a mov r2, r3
|
|
pnext = (USBH_DescHeader_t *)(void *)((uint8_t *)(void *)pbuf + \
|
|
8009ae8: 687b ldr r3, [r7, #4]
|
|
8009aea: 4413 add r3, r2
|
|
8009aec: 60fb str r3, [r7, #12]
|
|
|
|
return (pnext);
|
|
8009aee: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8009af0: 4618 mov r0, r3
|
|
8009af2: 3714 adds r7, #20
|
|
8009af4: 46bd mov sp, r7
|
|
8009af6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8009afa: 4770 bx lr
|
|
|
|
08009afc <USBH_CtlReq>:
|
|
* @param length: length of the response
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_CtlReq(USBH_HandleTypeDef *phost, uint8_t *buff,
|
|
uint16_t length)
|
|
{
|
|
8009afc: b580 push {r7, lr}
|
|
8009afe: b086 sub sp, #24
|
|
8009b00: af00 add r7, sp, #0
|
|
8009b02: 60f8 str r0, [r7, #12]
|
|
8009b04: 60b9 str r1, [r7, #8]
|
|
8009b06: 4613 mov r3, r2
|
|
8009b08: 80fb strh r3, [r7, #6]
|
|
USBH_StatusTypeDef status;
|
|
status = USBH_BUSY;
|
|
8009b0a: 2301 movs r3, #1
|
|
8009b0c: 75fb strb r3, [r7, #23]
|
|
|
|
switch (phost->RequestState)
|
|
8009b0e: 68fb ldr r3, [r7, #12]
|
|
8009b10: 789b ldrb r3, [r3, #2]
|
|
8009b12: 2b01 cmp r3, #1
|
|
8009b14: d002 beq.n 8009b1c <USBH_CtlReq+0x20>
|
|
8009b16: 2b02 cmp r3, #2
|
|
8009b18: d015 beq.n 8009b46 <USBH_CtlReq+0x4a>
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
8009b1a: e033 b.n 8009b84 <USBH_CtlReq+0x88>
|
|
phost->Control.buff = buff;
|
|
8009b1c: 68fb ldr r3, [r7, #12]
|
|
8009b1e: 68ba ldr r2, [r7, #8]
|
|
8009b20: 609a str r2, [r3, #8]
|
|
phost->Control.length = length;
|
|
8009b22: 68fb ldr r3, [r7, #12]
|
|
8009b24: 88fa ldrh r2, [r7, #6]
|
|
8009b26: 819a strh r2, [r3, #12]
|
|
phost->Control.state = CTRL_SETUP;
|
|
8009b28: 68fb ldr r3, [r7, #12]
|
|
8009b2a: 2201 movs r2, #1
|
|
8009b2c: 761a strb r2, [r3, #24]
|
|
phost->RequestState = CMD_WAIT;
|
|
8009b2e: 68fb ldr r3, [r7, #12]
|
|
8009b30: 2202 movs r2, #2
|
|
8009b32: 709a strb r2, [r3, #2]
|
|
status = USBH_BUSY;
|
|
8009b34: 2301 movs r3, #1
|
|
8009b36: 75fb strb r3, [r7, #23]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009b38: 2300 movs r3, #0
|
|
8009b3a: 2200 movs r2, #0
|
|
8009b3c: 2103 movs r1, #3
|
|
8009b3e: 68f8 ldr r0, [r7, #12]
|
|
8009b40: f7ff fb32 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009b44: e01e b.n 8009b84 <USBH_CtlReq+0x88>
|
|
status = USBH_HandleControl(phost);
|
|
8009b46: 68f8 ldr r0, [r7, #12]
|
|
8009b48: f000 f822 bl 8009b90 <USBH_HandleControl>
|
|
8009b4c: 4603 mov r3, r0
|
|
8009b4e: 75fb strb r3, [r7, #23]
|
|
if ((status == USBH_OK) || (status == USBH_NOT_SUPPORTED))
|
|
8009b50: 7dfb ldrb r3, [r7, #23]
|
|
8009b52: 2b00 cmp r3, #0
|
|
8009b54: d002 beq.n 8009b5c <USBH_CtlReq+0x60>
|
|
8009b56: 7dfb ldrb r3, [r7, #23]
|
|
8009b58: 2b03 cmp r3, #3
|
|
8009b5a: d106 bne.n 8009b6a <USBH_CtlReq+0x6e>
|
|
phost->RequestState = CMD_SEND;
|
|
8009b5c: 68fb ldr r3, [r7, #12]
|
|
8009b5e: 2201 movs r2, #1
|
|
8009b60: 709a strb r2, [r3, #2]
|
|
phost->Control.state = CTRL_IDLE;
|
|
8009b62: 68fb ldr r3, [r7, #12]
|
|
8009b64: 2200 movs r2, #0
|
|
8009b66: 761a strb r2, [r3, #24]
|
|
8009b68: e005 b.n 8009b76 <USBH_CtlReq+0x7a>
|
|
else if (status == USBH_FAIL)
|
|
8009b6a: 7dfb ldrb r3, [r7, #23]
|
|
8009b6c: 2b02 cmp r3, #2
|
|
8009b6e: d102 bne.n 8009b76 <USBH_CtlReq+0x7a>
|
|
phost->RequestState = CMD_SEND;
|
|
8009b70: 68fb ldr r3, [r7, #12]
|
|
8009b72: 2201 movs r2, #1
|
|
8009b74: 709a strb r2, [r3, #2]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009b76: 2300 movs r3, #0
|
|
8009b78: 2200 movs r2, #0
|
|
8009b7a: 2103 movs r1, #3
|
|
8009b7c: 68f8 ldr r0, [r7, #12]
|
|
8009b7e: f7ff fb13 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009b82: bf00 nop
|
|
}
|
|
return status;
|
|
8009b84: 7dfb ldrb r3, [r7, #23]
|
|
}
|
|
8009b86: 4618 mov r0, r3
|
|
8009b88: 3718 adds r7, #24
|
|
8009b8a: 46bd mov sp, r7
|
|
8009b8c: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08009b90 <USBH_HandleControl>:
|
|
* Handles the USB control transfer state machine
|
|
* @param phost: Host Handle
|
|
* @retval USBH Status
|
|
*/
|
|
static USBH_StatusTypeDef USBH_HandleControl(USBH_HandleTypeDef *phost)
|
|
{
|
|
8009b90: b580 push {r7, lr}
|
|
8009b92: b086 sub sp, #24
|
|
8009b94: af02 add r7, sp, #8
|
|
8009b96: 6078 str r0, [r7, #4]
|
|
uint8_t direction;
|
|
USBH_StatusTypeDef status = USBH_BUSY;
|
|
8009b98: 2301 movs r3, #1
|
|
8009b9a: 73fb strb r3, [r7, #15]
|
|
USBH_URBStateTypeDef URB_Status = USBH_URB_IDLE;
|
|
8009b9c: 2300 movs r3, #0
|
|
8009b9e: 73bb strb r3, [r7, #14]
|
|
|
|
switch (phost->Control.state)
|
|
8009ba0: 687b ldr r3, [r7, #4]
|
|
8009ba2: 7e1b ldrb r3, [r3, #24]
|
|
8009ba4: 3b01 subs r3, #1
|
|
8009ba6: 2b0a cmp r3, #10
|
|
8009ba8: f200 81b2 bhi.w 8009f10 <USBH_HandleControl+0x380>
|
|
8009bac: a201 add r2, pc, #4 @ (adr r2, 8009bb4 <USBH_HandleControl+0x24>)
|
|
8009bae: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8009bb2: bf00 nop
|
|
8009bb4: 08009be1 .word 0x08009be1
|
|
8009bb8: 08009bfb .word 0x08009bfb
|
|
8009bbc: 08009c7d .word 0x08009c7d
|
|
8009bc0: 08009ca3 .word 0x08009ca3
|
|
8009bc4: 08009d01 .word 0x08009d01
|
|
8009bc8: 08009d2b .word 0x08009d2b
|
|
8009bcc: 08009dad .word 0x08009dad
|
|
8009bd0: 08009dcf .word 0x08009dcf
|
|
8009bd4: 08009e31 .word 0x08009e31
|
|
8009bd8: 08009e57 .word 0x08009e57
|
|
8009bdc: 08009eb9 .word 0x08009eb9
|
|
{
|
|
case CTRL_SETUP:
|
|
/* send a SETUP packet */
|
|
(void)USBH_CtlSendSetup(phost, (uint8_t *)(void *)phost->Control.setup.d8,
|
|
8009be0: 687b ldr r3, [r7, #4]
|
|
8009be2: f103 0110 add.w r1, r3, #16
|
|
8009be6: 687b ldr r3, [r7, #4]
|
|
8009be8: 795b ldrb r3, [r3, #5]
|
|
8009bea: 461a mov r2, r3
|
|
8009bec: 6878 ldr r0, [r7, #4]
|
|
8009bee: f000 f99f bl 8009f30 <USBH_CtlSendSetup>
|
|
phost->Control.pipe_out);
|
|
|
|
phost->Control.state = CTRL_SETUP_WAIT;
|
|
8009bf2: 687b ldr r3, [r7, #4]
|
|
8009bf4: 2202 movs r2, #2
|
|
8009bf6: 761a strb r2, [r3, #24]
|
|
break;
|
|
8009bf8: e195 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
case CTRL_SETUP_WAIT:
|
|
|
|
URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
|
|
8009bfa: 687b ldr r3, [r7, #4]
|
|
8009bfc: 795b ldrb r3, [r3, #5]
|
|
8009bfe: 4619 mov r1, r3
|
|
8009c00: 6878 ldr r0, [r7, #4]
|
|
8009c02: f003 f837 bl 800cc74 <USBH_LL_GetURBState>
|
|
8009c06: 4603 mov r3, r0
|
|
8009c08: 73bb strb r3, [r7, #14]
|
|
/* case SETUP packet sent successfully */
|
|
if (URB_Status == USBH_URB_DONE)
|
|
8009c0a: 7bbb ldrb r3, [r7, #14]
|
|
8009c0c: 2b01 cmp r3, #1
|
|
8009c0e: d124 bne.n 8009c5a <USBH_HandleControl+0xca>
|
|
{
|
|
direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK);
|
|
8009c10: 687b ldr r3, [r7, #4]
|
|
8009c12: 7c1b ldrb r3, [r3, #16]
|
|
8009c14: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8009c18: 737b strb r3, [r7, #13]
|
|
|
|
/* check if there is a data stage */
|
|
if (phost->Control.setup.b.wLength.w != 0U)
|
|
8009c1a: 687b ldr r3, [r7, #4]
|
|
8009c1c: 8adb ldrh r3, [r3, #22]
|
|
8009c1e: 2b00 cmp r3, #0
|
|
8009c20: d00a beq.n 8009c38 <USBH_HandleControl+0xa8>
|
|
{
|
|
if (direction == USB_D2H)
|
|
8009c22: 7b7b ldrb r3, [r7, #13]
|
|
8009c24: 2b80 cmp r3, #128 @ 0x80
|
|
8009c26: d103 bne.n 8009c30 <USBH_HandleControl+0xa0>
|
|
{
|
|
/* Data Direction is IN */
|
|
phost->Control.state = CTRL_DATA_IN;
|
|
8009c28: 687b ldr r3, [r7, #4]
|
|
8009c2a: 2203 movs r2, #3
|
|
8009c2c: 761a strb r2, [r3, #24]
|
|
8009c2e: e00d b.n 8009c4c <USBH_HandleControl+0xbc>
|
|
}
|
|
else
|
|
{
|
|
/* Data Direction is OUT */
|
|
phost->Control.state = CTRL_DATA_OUT;
|
|
8009c30: 687b ldr r3, [r7, #4]
|
|
8009c32: 2205 movs r2, #5
|
|
8009c34: 761a strb r2, [r3, #24]
|
|
8009c36: e009 b.n 8009c4c <USBH_HandleControl+0xbc>
|
|
}
|
|
/* No DATA stage */
|
|
else
|
|
{
|
|
/* If there is No Data Transfer Stage */
|
|
if (direction == USB_D2H)
|
|
8009c38: 7b7b ldrb r3, [r7, #13]
|
|
8009c3a: 2b80 cmp r3, #128 @ 0x80
|
|
8009c3c: d103 bne.n 8009c46 <USBH_HandleControl+0xb6>
|
|
{
|
|
/* Data Direction is IN */
|
|
phost->Control.state = CTRL_STATUS_OUT;
|
|
8009c3e: 687b ldr r3, [r7, #4]
|
|
8009c40: 2209 movs r2, #9
|
|
8009c42: 761a strb r2, [r3, #24]
|
|
8009c44: e002 b.n 8009c4c <USBH_HandleControl+0xbc>
|
|
}
|
|
else
|
|
{
|
|
/* Data Direction is OUT */
|
|
phost->Control.state = CTRL_STATUS_IN;
|
|
8009c46: 687b ldr r3, [r7, #4]
|
|
8009c48: 2207 movs r2, #7
|
|
8009c4a: 761a strb r2, [r3, #24]
|
|
}
|
|
}
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009c4c: 2300 movs r3, #0
|
|
8009c4e: 2200 movs r2, #0
|
|
8009c50: 2103 movs r1, #3
|
|
8009c52: 6878 ldr r0, [r7, #4]
|
|
8009c54: f7ff faa8 bl 80091a8 <USBH_OS_PutMessage>
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8009c58: e15c b.n 8009f14 <USBH_HandleControl+0x384>
|
|
if ((URB_Status == USBH_URB_ERROR) || (URB_Status == USBH_URB_NOTREADY))
|
|
8009c5a: 7bbb ldrb r3, [r7, #14]
|
|
8009c5c: 2b04 cmp r3, #4
|
|
8009c5e: d003 beq.n 8009c68 <USBH_HandleControl+0xd8>
|
|
8009c60: 7bbb ldrb r3, [r7, #14]
|
|
8009c62: 2b02 cmp r3, #2
|
|
8009c64: f040 8156 bne.w 8009f14 <USBH_HandleControl+0x384>
|
|
phost->Control.state = CTRL_ERROR;
|
|
8009c68: 687b ldr r3, [r7, #4]
|
|
8009c6a: 220b movs r2, #11
|
|
8009c6c: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009c6e: 2300 movs r3, #0
|
|
8009c70: 2200 movs r2, #0
|
|
8009c72: 2103 movs r1, #3
|
|
8009c74: 6878 ldr r0, [r7, #4]
|
|
8009c76: f7ff fa97 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009c7a: e14b b.n 8009f14 <USBH_HandleControl+0x384>
|
|
|
|
case CTRL_DATA_IN:
|
|
/* Issue an IN token */
|
|
phost->Control.timer = (uint16_t)phost->Timer;
|
|
8009c7c: 687b ldr r3, [r7, #4]
|
|
8009c7e: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8009c82: b29a uxth r2, r3
|
|
8009c84: 687b ldr r3, [r7, #4]
|
|
8009c86: 81da strh r2, [r3, #14]
|
|
|
|
#if defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U)
|
|
phost->NakTimer = phost->Timer;
|
|
#endif /* defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U) */
|
|
|
|
(void)USBH_CtlReceiveData(phost, phost->Control.buff,
|
|
8009c88: 687b ldr r3, [r7, #4]
|
|
8009c8a: 6899 ldr r1, [r3, #8]
|
|
8009c8c: 687b ldr r3, [r7, #4]
|
|
8009c8e: 899a ldrh r2, [r3, #12]
|
|
8009c90: 687b ldr r3, [r7, #4]
|
|
8009c92: 791b ldrb r3, [r3, #4]
|
|
8009c94: 6878 ldr r0, [r7, #4]
|
|
8009c96: f000 f98a bl 8009fae <USBH_CtlReceiveData>
|
|
phost->Control.length, phost->Control.pipe_in);
|
|
|
|
phost->Control.state = CTRL_DATA_IN_WAIT;
|
|
8009c9a: 687b ldr r3, [r7, #4]
|
|
8009c9c: 2204 movs r2, #4
|
|
8009c9e: 761a strb r2, [r3, #24]
|
|
break;
|
|
8009ca0: e141 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
case CTRL_DATA_IN_WAIT:
|
|
|
|
URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in);
|
|
8009ca2: 687b ldr r3, [r7, #4]
|
|
8009ca4: 791b ldrb r3, [r3, #4]
|
|
8009ca6: 4619 mov r1, r3
|
|
8009ca8: 6878 ldr r0, [r7, #4]
|
|
8009caa: f002 ffe3 bl 800cc74 <USBH_LL_GetURBState>
|
|
8009cae: 4603 mov r3, r0
|
|
8009cb0: 73bb strb r3, [r7, #14]
|
|
|
|
/* check is DATA packet transferred successfully */
|
|
if (URB_Status == USBH_URB_DONE)
|
|
8009cb2: 7bbb ldrb r3, [r7, #14]
|
|
8009cb4: 2b01 cmp r3, #1
|
|
8009cb6: d109 bne.n 8009ccc <USBH_HandleControl+0x13c>
|
|
{
|
|
phost->Control.state = CTRL_STATUS_OUT;
|
|
8009cb8: 687b ldr r3, [r7, #4]
|
|
8009cba: 2209 movs r2, #9
|
|
8009cbc: 761a strb r2, [r3, #24]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009cbe: 2300 movs r3, #0
|
|
8009cc0: 2200 movs r2, #0
|
|
8009cc2: 2103 movs r1, #3
|
|
8009cc4: 6878 ldr r0, [r7, #4]
|
|
8009cc6: f7ff fa6f bl 80091a8 <USBH_OS_PutMessage>
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8009cca: e125 b.n 8009f18 <USBH_HandleControl+0x388>
|
|
else if (URB_Status == USBH_URB_STALL)
|
|
8009ccc: 7bbb ldrb r3, [r7, #14]
|
|
8009cce: 2b05 cmp r3, #5
|
|
8009cd0: d108 bne.n 8009ce4 <USBH_HandleControl+0x154>
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009cd2: 2303 movs r3, #3
|
|
8009cd4: 73fb strb r3, [r7, #15]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009cd6: 2300 movs r3, #0
|
|
8009cd8: 2200 movs r2, #0
|
|
8009cda: 2103 movs r1, #3
|
|
8009cdc: 6878 ldr r0, [r7, #4]
|
|
8009cde: f7ff fa63 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009ce2: e119 b.n 8009f18 <USBH_HandleControl+0x388>
|
|
if (URB_Status == USBH_URB_ERROR)
|
|
8009ce4: 7bbb ldrb r3, [r7, #14]
|
|
8009ce6: 2b04 cmp r3, #4
|
|
8009ce8: f040 8116 bne.w 8009f18 <USBH_HandleControl+0x388>
|
|
phost->Control.state = CTRL_ERROR;
|
|
8009cec: 687b ldr r3, [r7, #4]
|
|
8009cee: 220b movs r2, #11
|
|
8009cf0: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009cf2: 2300 movs r3, #0
|
|
8009cf4: 2200 movs r2, #0
|
|
8009cf6: 2103 movs r1, #3
|
|
8009cf8: 6878 ldr r0, [r7, #4]
|
|
8009cfa: f7ff fa55 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009cfe: e10b b.n 8009f18 <USBH_HandleControl+0x388>
|
|
|
|
case CTRL_DATA_OUT:
|
|
|
|
(void)USBH_CtlSendData(phost, phost->Control.buff, phost->Control.length,
|
|
8009d00: 687b ldr r3, [r7, #4]
|
|
8009d02: 6899 ldr r1, [r3, #8]
|
|
8009d04: 687b ldr r3, [r7, #4]
|
|
8009d06: 899a ldrh r2, [r3, #12]
|
|
8009d08: 687b ldr r3, [r7, #4]
|
|
8009d0a: 795b ldrb r3, [r3, #5]
|
|
8009d0c: 2001 movs r0, #1
|
|
8009d0e: 9000 str r0, [sp, #0]
|
|
8009d10: 6878 ldr r0, [r7, #4]
|
|
8009d12: f000 f927 bl 8009f64 <USBH_CtlSendData>
|
|
phost->Control.pipe_out, 1U);
|
|
|
|
phost->Control.timer = (uint16_t)phost->Timer;
|
|
8009d16: 687b ldr r3, [r7, #4]
|
|
8009d18: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8009d1c: b29a uxth r2, r3
|
|
8009d1e: 687b ldr r3, [r7, #4]
|
|
8009d20: 81da strh r2, [r3, #14]
|
|
phost->Control.state = CTRL_DATA_OUT_WAIT;
|
|
8009d22: 687b ldr r3, [r7, #4]
|
|
8009d24: 2206 movs r2, #6
|
|
8009d26: 761a strb r2, [r3, #24]
|
|
break;
|
|
8009d28: e0fd b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
case CTRL_DATA_OUT_WAIT:
|
|
|
|
URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
|
|
8009d2a: 687b ldr r3, [r7, #4]
|
|
8009d2c: 795b ldrb r3, [r3, #5]
|
|
8009d2e: 4619 mov r1, r3
|
|
8009d30: 6878 ldr r0, [r7, #4]
|
|
8009d32: f002 ff9f bl 800cc74 <USBH_LL_GetURBState>
|
|
8009d36: 4603 mov r3, r0
|
|
8009d38: 73bb strb r3, [r7, #14]
|
|
|
|
if (URB_Status == USBH_URB_DONE)
|
|
8009d3a: 7bbb ldrb r3, [r7, #14]
|
|
8009d3c: 2b01 cmp r3, #1
|
|
8009d3e: d109 bne.n 8009d54 <USBH_HandleControl+0x1c4>
|
|
{
|
|
/* If the Setup Pkt is sent successful, then change the state */
|
|
phost->Control.state = CTRL_STATUS_IN;
|
|
8009d40: 687b ldr r3, [r7, #4]
|
|
8009d42: 2207 movs r2, #7
|
|
8009d44: 761a strb r2, [r3, #24]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009d46: 2300 movs r3, #0
|
|
8009d48: 2200 movs r2, #0
|
|
8009d4a: 2103 movs r1, #3
|
|
8009d4c: 6878 ldr r0, [r7, #4]
|
|
8009d4e: f7ff fa2b bl 80091a8 <USBH_OS_PutMessage>
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8009d52: e0e3 b.n 8009f1c <USBH_HandleControl+0x38c>
|
|
else if (URB_Status == USBH_URB_STALL)
|
|
8009d54: 7bbb ldrb r3, [r7, #14]
|
|
8009d56: 2b05 cmp r3, #5
|
|
8009d58: d10b bne.n 8009d72 <USBH_HandleControl+0x1e2>
|
|
phost->Control.state = CTRL_STALLED;
|
|
8009d5a: 687b ldr r3, [r7, #4]
|
|
8009d5c: 220c movs r2, #12
|
|
8009d5e: 761a strb r2, [r3, #24]
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009d60: 2303 movs r3, #3
|
|
8009d62: 73fb strb r3, [r7, #15]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009d64: 2300 movs r3, #0
|
|
8009d66: 2200 movs r2, #0
|
|
8009d68: 2103 movs r1, #3
|
|
8009d6a: 6878 ldr r0, [r7, #4]
|
|
8009d6c: f7ff fa1c bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009d70: e0d4 b.n 8009f1c <USBH_HandleControl+0x38c>
|
|
else if (URB_Status == USBH_URB_NOTREADY)
|
|
8009d72: 7bbb ldrb r3, [r7, #14]
|
|
8009d74: 2b02 cmp r3, #2
|
|
8009d76: d109 bne.n 8009d8c <USBH_HandleControl+0x1fc>
|
|
phost->Control.state = CTRL_DATA_OUT;
|
|
8009d78: 687b ldr r3, [r7, #4]
|
|
8009d7a: 2205 movs r2, #5
|
|
8009d7c: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009d7e: 2300 movs r3, #0
|
|
8009d80: 2200 movs r2, #0
|
|
8009d82: 2103 movs r1, #3
|
|
8009d84: 6878 ldr r0, [r7, #4]
|
|
8009d86: f7ff fa0f bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009d8a: e0c7 b.n 8009f1c <USBH_HandleControl+0x38c>
|
|
if (URB_Status == USBH_URB_ERROR)
|
|
8009d8c: 7bbb ldrb r3, [r7, #14]
|
|
8009d8e: 2b04 cmp r3, #4
|
|
8009d90: f040 80c4 bne.w 8009f1c <USBH_HandleControl+0x38c>
|
|
phost->Control.state = CTRL_ERROR;
|
|
8009d94: 687b ldr r3, [r7, #4]
|
|
8009d96: 220b movs r2, #11
|
|
8009d98: 761a strb r2, [r3, #24]
|
|
status = USBH_FAIL;
|
|
8009d9a: 2302 movs r3, #2
|
|
8009d9c: 73fb strb r3, [r7, #15]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009d9e: 2300 movs r3, #0
|
|
8009da0: 2200 movs r2, #0
|
|
8009da2: 2103 movs r1, #3
|
|
8009da4: 6878 ldr r0, [r7, #4]
|
|
8009da6: f7ff f9ff bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009daa: e0b7 b.n 8009f1c <USBH_HandleControl+0x38c>
|
|
|
|
case CTRL_STATUS_IN:
|
|
/* Send 0 bytes out packet */
|
|
(void)USBH_CtlReceiveData(phost, NULL, 0U, phost->Control.pipe_in);
|
|
8009dac: 687b ldr r3, [r7, #4]
|
|
8009dae: 791b ldrb r3, [r3, #4]
|
|
8009db0: 2200 movs r2, #0
|
|
8009db2: 2100 movs r1, #0
|
|
8009db4: 6878 ldr r0, [r7, #4]
|
|
8009db6: f000 f8fa bl 8009fae <USBH_CtlReceiveData>
|
|
|
|
#if defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U)
|
|
phost->NakTimer = phost->Timer;
|
|
#endif /* defined (USBH_IN_NAK_PROCESS) && (USBH_IN_NAK_PROCESS == 1U) */
|
|
|
|
phost->Control.timer = (uint16_t)phost->Timer;
|
|
8009dba: 687b ldr r3, [r7, #4]
|
|
8009dbc: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8009dc0: b29a uxth r2, r3
|
|
8009dc2: 687b ldr r3, [r7, #4]
|
|
8009dc4: 81da strh r2, [r3, #14]
|
|
phost->Control.state = CTRL_STATUS_IN_WAIT;
|
|
8009dc6: 687b ldr r3, [r7, #4]
|
|
8009dc8: 2208 movs r2, #8
|
|
8009dca: 761a strb r2, [r3, #24]
|
|
|
|
break;
|
|
8009dcc: e0ab b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
case CTRL_STATUS_IN_WAIT:
|
|
|
|
URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_in);
|
|
8009dce: 687b ldr r3, [r7, #4]
|
|
8009dd0: 791b ldrb r3, [r3, #4]
|
|
8009dd2: 4619 mov r1, r3
|
|
8009dd4: 6878 ldr r0, [r7, #4]
|
|
8009dd6: f002 ff4d bl 800cc74 <USBH_LL_GetURBState>
|
|
8009dda: 4603 mov r3, r0
|
|
8009ddc: 73bb strb r3, [r7, #14]
|
|
|
|
if (URB_Status == USBH_URB_DONE)
|
|
8009dde: 7bbb ldrb r3, [r7, #14]
|
|
8009de0: 2b01 cmp r3, #1
|
|
8009de2: d10b bne.n 8009dfc <USBH_HandleControl+0x26c>
|
|
{
|
|
/* Control transfers completed, Exit the State Machine */
|
|
phost->Control.state = CTRL_COMPLETE;
|
|
8009de4: 687b ldr r3, [r7, #4]
|
|
8009de6: 220d movs r2, #13
|
|
8009de8: 761a strb r2, [r3, #24]
|
|
status = USBH_OK;
|
|
8009dea: 2300 movs r3, #0
|
|
8009dec: 73fb strb r3, [r7, #15]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009dee: 2300 movs r3, #0
|
|
8009df0: 2200 movs r2, #0
|
|
8009df2: 2103 movs r1, #3
|
|
8009df4: 6878 ldr r0, [r7, #4]
|
|
8009df6: f7ff f9d7 bl 80091a8 <USBH_OS_PutMessage>
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8009dfa: e091 b.n 8009f20 <USBH_HandleControl+0x390>
|
|
else if (URB_Status == USBH_URB_ERROR)
|
|
8009dfc: 7bbb ldrb r3, [r7, #14]
|
|
8009dfe: 2b04 cmp r3, #4
|
|
8009e00: d109 bne.n 8009e16 <USBH_HandleControl+0x286>
|
|
phost->Control.state = CTRL_ERROR;
|
|
8009e02: 687b ldr r3, [r7, #4]
|
|
8009e04: 220b movs r2, #11
|
|
8009e06: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009e08: 2300 movs r3, #0
|
|
8009e0a: 2200 movs r2, #0
|
|
8009e0c: 2103 movs r1, #3
|
|
8009e0e: 6878 ldr r0, [r7, #4]
|
|
8009e10: f7ff f9ca bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009e14: e084 b.n 8009f20 <USBH_HandleControl+0x390>
|
|
if (URB_Status == USBH_URB_STALL)
|
|
8009e16: 7bbb ldrb r3, [r7, #14]
|
|
8009e18: 2b05 cmp r3, #5
|
|
8009e1a: f040 8081 bne.w 8009f20 <USBH_HandleControl+0x390>
|
|
status = USBH_NOT_SUPPORTED;
|
|
8009e1e: 2303 movs r3, #3
|
|
8009e20: 73fb strb r3, [r7, #15]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009e22: 2300 movs r3, #0
|
|
8009e24: 2200 movs r2, #0
|
|
8009e26: 2103 movs r1, #3
|
|
8009e28: 6878 ldr r0, [r7, #4]
|
|
8009e2a: f7ff f9bd bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009e2e: e077 b.n 8009f20 <USBH_HandleControl+0x390>
|
|
|
|
case CTRL_STATUS_OUT:
|
|
(void)USBH_CtlSendData(phost, NULL, 0U, phost->Control.pipe_out, 1U);
|
|
8009e30: 687b ldr r3, [r7, #4]
|
|
8009e32: 795b ldrb r3, [r3, #5]
|
|
8009e34: 2201 movs r2, #1
|
|
8009e36: 9200 str r2, [sp, #0]
|
|
8009e38: 2200 movs r2, #0
|
|
8009e3a: 2100 movs r1, #0
|
|
8009e3c: 6878 ldr r0, [r7, #4]
|
|
8009e3e: f000 f891 bl 8009f64 <USBH_CtlSendData>
|
|
|
|
phost->Control.timer = (uint16_t)phost->Timer;
|
|
8009e42: 687b ldr r3, [r7, #4]
|
|
8009e44: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8009e48: b29a uxth r2, r3
|
|
8009e4a: 687b ldr r3, [r7, #4]
|
|
8009e4c: 81da strh r2, [r3, #14]
|
|
phost->Control.state = CTRL_STATUS_OUT_WAIT;
|
|
8009e4e: 687b ldr r3, [r7, #4]
|
|
8009e50: 220a movs r2, #10
|
|
8009e52: 761a strb r2, [r3, #24]
|
|
break;
|
|
8009e54: e067 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
case CTRL_STATUS_OUT_WAIT:
|
|
URB_Status = USBH_LL_GetURBState(phost, phost->Control.pipe_out);
|
|
8009e56: 687b ldr r3, [r7, #4]
|
|
8009e58: 795b ldrb r3, [r3, #5]
|
|
8009e5a: 4619 mov r1, r3
|
|
8009e5c: 6878 ldr r0, [r7, #4]
|
|
8009e5e: f002 ff09 bl 800cc74 <USBH_LL_GetURBState>
|
|
8009e62: 4603 mov r3, r0
|
|
8009e64: 73bb strb r3, [r7, #14]
|
|
if (URB_Status == USBH_URB_DONE)
|
|
8009e66: 7bbb ldrb r3, [r7, #14]
|
|
8009e68: 2b01 cmp r3, #1
|
|
8009e6a: d10b bne.n 8009e84 <USBH_HandleControl+0x2f4>
|
|
{
|
|
status = USBH_OK;
|
|
8009e6c: 2300 movs r3, #0
|
|
8009e6e: 73fb strb r3, [r7, #15]
|
|
phost->Control.state = CTRL_COMPLETE;
|
|
8009e70: 687b ldr r3, [r7, #4]
|
|
8009e72: 220d movs r2, #13
|
|
8009e74: 761a strb r2, [r3, #24]
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009e76: 2300 movs r3, #0
|
|
8009e78: 2200 movs r2, #0
|
|
8009e7a: 2103 movs r1, #3
|
|
8009e7c: 6878 ldr r0, [r7, #4]
|
|
8009e7e: f7ff f993 bl 80091a8 <USBH_OS_PutMessage>
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
}
|
|
}
|
|
break;
|
|
8009e82: e04f b.n 8009f24 <USBH_HandleControl+0x394>
|
|
else if (URB_Status == USBH_URB_NOTREADY)
|
|
8009e84: 7bbb ldrb r3, [r7, #14]
|
|
8009e86: 2b02 cmp r3, #2
|
|
8009e88: d109 bne.n 8009e9e <USBH_HandleControl+0x30e>
|
|
phost->Control.state = CTRL_STATUS_OUT;
|
|
8009e8a: 687b ldr r3, [r7, #4]
|
|
8009e8c: 2209 movs r2, #9
|
|
8009e8e: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009e90: 2300 movs r3, #0
|
|
8009e92: 2200 movs r2, #0
|
|
8009e94: 2103 movs r1, #3
|
|
8009e96: 6878 ldr r0, [r7, #4]
|
|
8009e98: f7ff f986 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009e9c: e042 b.n 8009f24 <USBH_HandleControl+0x394>
|
|
if (URB_Status == USBH_URB_ERROR)
|
|
8009e9e: 7bbb ldrb r3, [r7, #14]
|
|
8009ea0: 2b04 cmp r3, #4
|
|
8009ea2: d13f bne.n 8009f24 <USBH_HandleControl+0x394>
|
|
phost->Control.state = CTRL_ERROR;
|
|
8009ea4: 687b ldr r3, [r7, #4]
|
|
8009ea6: 220b movs r2, #11
|
|
8009ea8: 761a strb r2, [r3, #24]
|
|
USBH_OS_PutMessage(phost, USBH_CONTROL_EVENT, 0U, 0U);
|
|
8009eaa: 2300 movs r3, #0
|
|
8009eac: 2200 movs r2, #0
|
|
8009eae: 2103 movs r1, #3
|
|
8009eb0: 6878 ldr r0, [r7, #4]
|
|
8009eb2: f7ff f979 bl 80091a8 <USBH_OS_PutMessage>
|
|
break;
|
|
8009eb6: e035 b.n 8009f24 <USBH_HandleControl+0x394>
|
|
PID; i.e., recovery actions via some other pipe are not required for control
|
|
endpoints. For the Default Control Pipe, a device reset will ultimately be
|
|
required to clear the halt or error condition if the next Setup PID is not
|
|
accepted.
|
|
*/
|
|
if (++phost->Control.errorcount <= USBH_MAX_ERROR_COUNT)
|
|
8009eb8: 687b ldr r3, [r7, #4]
|
|
8009eba: 7e5b ldrb r3, [r3, #25]
|
|
8009ebc: 3301 adds r3, #1
|
|
8009ebe: b2da uxtb r2, r3
|
|
8009ec0: 687b ldr r3, [r7, #4]
|
|
8009ec2: 765a strb r2, [r3, #25]
|
|
8009ec4: 687b ldr r3, [r7, #4]
|
|
8009ec6: 7e5b ldrb r3, [r3, #25]
|
|
8009ec8: 2b02 cmp r3, #2
|
|
8009eca: d806 bhi.n 8009eda <USBH_HandleControl+0x34a>
|
|
{
|
|
/* Do the transmission again, starting from SETUP Packet */
|
|
phost->Control.state = CTRL_SETUP;
|
|
8009ecc: 687b ldr r3, [r7, #4]
|
|
8009ece: 2201 movs r2, #1
|
|
8009ed0: 761a strb r2, [r3, #24]
|
|
phost->RequestState = CMD_SEND;
|
|
8009ed2: 687b ldr r3, [r7, #4]
|
|
8009ed4: 2201 movs r2, #1
|
|
8009ed6: 709a strb r2, [r3, #2]
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
|
|
phost->gState = HOST_IDLE;
|
|
status = USBH_FAIL;
|
|
}
|
|
break;
|
|
8009ed8: e025 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
phost->pUser(phost, HOST_USER_UNRECOVERED_ERROR);
|
|
8009eda: 687b ldr r3, [r7, #4]
|
|
8009edc: f8d3 33d4 ldr.w r3, [r3, #980] @ 0x3d4
|
|
8009ee0: 2106 movs r1, #6
|
|
8009ee2: 6878 ldr r0, [r7, #4]
|
|
8009ee4: 4798 blx r3
|
|
phost->Control.errorcount = 0U;
|
|
8009ee6: 687b ldr r3, [r7, #4]
|
|
8009ee8: 2200 movs r2, #0
|
|
8009eea: 765a strb r2, [r3, #25]
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8009eec: 687b ldr r3, [r7, #4]
|
|
8009eee: 795b ldrb r3, [r3, #5]
|
|
8009ef0: 4619 mov r1, r3
|
|
8009ef2: 6878 ldr r0, [r7, #4]
|
|
8009ef4: f000 f90c bl 800a110 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8009ef8: 687b ldr r3, [r7, #4]
|
|
8009efa: 791b ldrb r3, [r3, #4]
|
|
8009efc: 4619 mov r1, r3
|
|
8009efe: 6878 ldr r0, [r7, #4]
|
|
8009f00: f000 f906 bl 800a110 <USBH_FreePipe>
|
|
phost->gState = HOST_IDLE;
|
|
8009f04: 687b ldr r3, [r7, #4]
|
|
8009f06: 2200 movs r2, #0
|
|
8009f08: 701a strb r2, [r3, #0]
|
|
status = USBH_FAIL;
|
|
8009f0a: 2302 movs r3, #2
|
|
8009f0c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8009f0e: e00a b.n 8009f26 <USBH_HandleControl+0x396>
|
|
|
|
default:
|
|
break;
|
|
8009f10: bf00 nop
|
|
8009f12: e008 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
break;
|
|
8009f14: bf00 nop
|
|
8009f16: e006 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
break;
|
|
8009f18: bf00 nop
|
|
8009f1a: e004 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
break;
|
|
8009f1c: bf00 nop
|
|
8009f1e: e002 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
break;
|
|
8009f20: bf00 nop
|
|
8009f22: e000 b.n 8009f26 <USBH_HandleControl+0x396>
|
|
break;
|
|
8009f24: bf00 nop
|
|
}
|
|
|
|
return status;
|
|
8009f26: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8009f28: 4618 mov r0, r3
|
|
8009f2a: 3710 adds r7, #16
|
|
8009f2c: 46bd mov sp, r7
|
|
8009f2e: bd80 pop {r7, pc}
|
|
|
|
08009f30 <USBH_CtlSendSetup>:
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_CtlSendSetup(USBH_HandleTypeDef *phost,
|
|
uint8_t *buff,
|
|
uint8_t pipe_num)
|
|
{
|
|
8009f30: b580 push {r7, lr}
|
|
8009f32: b088 sub sp, #32
|
|
8009f34: af04 add r7, sp, #16
|
|
8009f36: 60f8 str r0, [r7, #12]
|
|
8009f38: 60b9 str r1, [r7, #8]
|
|
8009f3a: 4613 mov r3, r2
|
|
8009f3c: 71fb strb r3, [r7, #7]
|
|
|
|
(void)USBH_LL_SubmitURB(phost, /* Driver handle */
|
|
8009f3e: 79f9 ldrb r1, [r7, #7]
|
|
8009f40: 2300 movs r3, #0
|
|
8009f42: 9303 str r3, [sp, #12]
|
|
8009f44: 2308 movs r3, #8
|
|
8009f46: 9302 str r3, [sp, #8]
|
|
8009f48: 68bb ldr r3, [r7, #8]
|
|
8009f4a: 9301 str r3, [sp, #4]
|
|
8009f4c: 2300 movs r3, #0
|
|
8009f4e: 9300 str r3, [sp, #0]
|
|
8009f50: 2300 movs r3, #0
|
|
8009f52: 2200 movs r2, #0
|
|
8009f54: 68f8 ldr r0, [r7, #12]
|
|
8009f56: f002 fe5c bl 800cc12 <USBH_LL_SubmitURB>
|
|
USBH_EP_CONTROL, /* EP type */
|
|
USBH_PID_SETUP, /* Type setup */
|
|
buff, /* data buffer */
|
|
USBH_SETUP_PKT_SIZE, /* data length */
|
|
0U);
|
|
return USBH_OK;
|
|
8009f5a: 2300 movs r3, #0
|
|
}
|
|
8009f5c: 4618 mov r0, r3
|
|
8009f5e: 3710 adds r7, #16
|
|
8009f60: 46bd mov sp, r7
|
|
8009f62: bd80 pop {r7, pc}
|
|
|
|
08009f64 <USBH_CtlSendData>:
|
|
USBH_StatusTypeDef USBH_CtlSendData(USBH_HandleTypeDef *phost,
|
|
uint8_t *buff,
|
|
uint16_t length,
|
|
uint8_t pipe_num,
|
|
uint8_t do_ping)
|
|
{
|
|
8009f64: b580 push {r7, lr}
|
|
8009f66: b088 sub sp, #32
|
|
8009f68: af04 add r7, sp, #16
|
|
8009f6a: 60f8 str r0, [r7, #12]
|
|
8009f6c: 60b9 str r1, [r7, #8]
|
|
8009f6e: 4611 mov r1, r2
|
|
8009f70: 461a mov r2, r3
|
|
8009f72: 460b mov r3, r1
|
|
8009f74: 80fb strh r3, [r7, #6]
|
|
8009f76: 4613 mov r3, r2
|
|
8009f78: 717b strb r3, [r7, #5]
|
|
if (phost->device.speed != USBH_SPEED_HIGH)
|
|
8009f7a: 68fb ldr r3, [r7, #12]
|
|
8009f7c: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
8009f80: 2b00 cmp r3, #0
|
|
8009f82: d001 beq.n 8009f88 <USBH_CtlSendData+0x24>
|
|
{
|
|
do_ping = 0U;
|
|
8009f84: 2300 movs r3, #0
|
|
8009f86: 763b strb r3, [r7, #24]
|
|
}
|
|
|
|
(void)USBH_LL_SubmitURB(phost, /* Driver handle */
|
|
8009f88: 7979 ldrb r1, [r7, #5]
|
|
8009f8a: 7e3b ldrb r3, [r7, #24]
|
|
8009f8c: 9303 str r3, [sp, #12]
|
|
8009f8e: 88fb ldrh r3, [r7, #6]
|
|
8009f90: 9302 str r3, [sp, #8]
|
|
8009f92: 68bb ldr r3, [r7, #8]
|
|
8009f94: 9301 str r3, [sp, #4]
|
|
8009f96: 2301 movs r3, #1
|
|
8009f98: 9300 str r3, [sp, #0]
|
|
8009f9a: 2300 movs r3, #0
|
|
8009f9c: 2200 movs r2, #0
|
|
8009f9e: 68f8 ldr r0, [r7, #12]
|
|
8009fa0: f002 fe37 bl 800cc12 <USBH_LL_SubmitURB>
|
|
USBH_PID_DATA, /* Type Data */
|
|
buff, /* data buffer */
|
|
length, /* data length */
|
|
do_ping); /* do ping (HS Only)*/
|
|
|
|
return USBH_OK;
|
|
8009fa4: 2300 movs r3, #0
|
|
}
|
|
8009fa6: 4618 mov r0, r3
|
|
8009fa8: 3710 adds r7, #16
|
|
8009faa: 46bd mov sp, r7
|
|
8009fac: bd80 pop {r7, pc}
|
|
|
|
08009fae <USBH_CtlReceiveData>:
|
|
*/
|
|
USBH_StatusTypeDef USBH_CtlReceiveData(USBH_HandleTypeDef *phost,
|
|
uint8_t *buff,
|
|
uint16_t length,
|
|
uint8_t pipe_num)
|
|
{
|
|
8009fae: b580 push {r7, lr}
|
|
8009fb0: b088 sub sp, #32
|
|
8009fb2: af04 add r7, sp, #16
|
|
8009fb4: 60f8 str r0, [r7, #12]
|
|
8009fb6: 60b9 str r1, [r7, #8]
|
|
8009fb8: 4611 mov r1, r2
|
|
8009fba: 461a mov r2, r3
|
|
8009fbc: 460b mov r3, r1
|
|
8009fbe: 80fb strh r3, [r7, #6]
|
|
8009fc0: 4613 mov r3, r2
|
|
8009fc2: 717b strb r3, [r7, #5]
|
|
(void)USBH_LL_SubmitURB(phost, /* Driver handle */
|
|
8009fc4: 7979 ldrb r1, [r7, #5]
|
|
8009fc6: 2300 movs r3, #0
|
|
8009fc8: 9303 str r3, [sp, #12]
|
|
8009fca: 88fb ldrh r3, [r7, #6]
|
|
8009fcc: 9302 str r3, [sp, #8]
|
|
8009fce: 68bb ldr r3, [r7, #8]
|
|
8009fd0: 9301 str r3, [sp, #4]
|
|
8009fd2: 2301 movs r3, #1
|
|
8009fd4: 9300 str r3, [sp, #0]
|
|
8009fd6: 2300 movs r3, #0
|
|
8009fd8: 2201 movs r2, #1
|
|
8009fda: 68f8 ldr r0, [r7, #12]
|
|
8009fdc: f002 fe19 bl 800cc12 <USBH_LL_SubmitURB>
|
|
USBH_EP_CONTROL, /* EP type */
|
|
USBH_PID_DATA, /* Type Data */
|
|
buff, /* data buffer */
|
|
length, /* data length */
|
|
0U);
|
|
return USBH_OK;
|
|
8009fe0: 2300 movs r3, #0
|
|
|
|
}
|
|
8009fe2: 4618 mov r0, r3
|
|
8009fe4: 3710 adds r7, #16
|
|
8009fe6: 46bd mov sp, r7
|
|
8009fe8: bd80 pop {r7, pc}
|
|
|
|
08009fea <USBH_BulkSendData>:
|
|
USBH_StatusTypeDef USBH_BulkSendData(USBH_HandleTypeDef *phost,
|
|
uint8_t *buff,
|
|
uint16_t length,
|
|
uint8_t pipe_num,
|
|
uint8_t do_ping)
|
|
{
|
|
8009fea: b580 push {r7, lr}
|
|
8009fec: b088 sub sp, #32
|
|
8009fee: af04 add r7, sp, #16
|
|
8009ff0: 60f8 str r0, [r7, #12]
|
|
8009ff2: 60b9 str r1, [r7, #8]
|
|
8009ff4: 4611 mov r1, r2
|
|
8009ff6: 461a mov r2, r3
|
|
8009ff8: 460b mov r3, r1
|
|
8009ffa: 80fb strh r3, [r7, #6]
|
|
8009ffc: 4613 mov r3, r2
|
|
8009ffe: 717b strb r3, [r7, #5]
|
|
if (phost->device.speed != USBH_SPEED_HIGH)
|
|
800a000: 68fb ldr r3, [r7, #12]
|
|
800a002: f893 331d ldrb.w r3, [r3, #797] @ 0x31d
|
|
800a006: 2b00 cmp r3, #0
|
|
800a008: d001 beq.n 800a00e <USBH_BulkSendData+0x24>
|
|
{
|
|
do_ping = 0U;
|
|
800a00a: 2300 movs r3, #0
|
|
800a00c: 763b strb r3, [r7, #24]
|
|
}
|
|
|
|
(void)USBH_LL_SubmitURB(phost, /* Driver handle */
|
|
800a00e: 7979 ldrb r1, [r7, #5]
|
|
800a010: 7e3b ldrb r3, [r7, #24]
|
|
800a012: 9303 str r3, [sp, #12]
|
|
800a014: 88fb ldrh r3, [r7, #6]
|
|
800a016: 9302 str r3, [sp, #8]
|
|
800a018: 68bb ldr r3, [r7, #8]
|
|
800a01a: 9301 str r3, [sp, #4]
|
|
800a01c: 2301 movs r3, #1
|
|
800a01e: 9300 str r3, [sp, #0]
|
|
800a020: 2302 movs r3, #2
|
|
800a022: 2200 movs r2, #0
|
|
800a024: 68f8 ldr r0, [r7, #12]
|
|
800a026: f002 fdf4 bl 800cc12 <USBH_LL_SubmitURB>
|
|
USBH_EP_BULK, /* EP type */
|
|
USBH_PID_DATA, /* Type Data */
|
|
buff, /* data buffer */
|
|
length, /* data length */
|
|
do_ping); /* do ping (HS Only)*/
|
|
return USBH_OK;
|
|
800a02a: 2300 movs r3, #0
|
|
}
|
|
800a02c: 4618 mov r0, r3
|
|
800a02e: 3710 adds r7, #16
|
|
800a030: 46bd mov sp, r7
|
|
800a032: bd80 pop {r7, pc}
|
|
|
|
0800a034 <USBH_BulkReceiveData>:
|
|
*/
|
|
USBH_StatusTypeDef USBH_BulkReceiveData(USBH_HandleTypeDef *phost,
|
|
uint8_t *buff,
|
|
uint16_t length,
|
|
uint8_t pipe_num)
|
|
{
|
|
800a034: b580 push {r7, lr}
|
|
800a036: b088 sub sp, #32
|
|
800a038: af04 add r7, sp, #16
|
|
800a03a: 60f8 str r0, [r7, #12]
|
|
800a03c: 60b9 str r1, [r7, #8]
|
|
800a03e: 4611 mov r1, r2
|
|
800a040: 461a mov r2, r3
|
|
800a042: 460b mov r3, r1
|
|
800a044: 80fb strh r3, [r7, #6]
|
|
800a046: 4613 mov r3, r2
|
|
800a048: 717b strb r3, [r7, #5]
|
|
(void)USBH_LL_SubmitURB(phost, /* Driver handle */
|
|
800a04a: 7979 ldrb r1, [r7, #5]
|
|
800a04c: 2300 movs r3, #0
|
|
800a04e: 9303 str r3, [sp, #12]
|
|
800a050: 88fb ldrh r3, [r7, #6]
|
|
800a052: 9302 str r3, [sp, #8]
|
|
800a054: 68bb ldr r3, [r7, #8]
|
|
800a056: 9301 str r3, [sp, #4]
|
|
800a058: 2301 movs r3, #1
|
|
800a05a: 9300 str r3, [sp, #0]
|
|
800a05c: 2302 movs r3, #2
|
|
800a05e: 2201 movs r2, #1
|
|
800a060: 68f8 ldr r0, [r7, #12]
|
|
800a062: f002 fdd6 bl 800cc12 <USBH_LL_SubmitURB>
|
|
USBH_EP_BULK, /* EP type */
|
|
USBH_PID_DATA, /* Type Data */
|
|
buff, /* data buffer */
|
|
length, /* data length */
|
|
0U);
|
|
return USBH_OK;
|
|
800a066: 2300 movs r3, #0
|
|
}
|
|
800a068: 4618 mov r0, r3
|
|
800a06a: 3710 adds r7, #16
|
|
800a06c: 46bd mov sp, r7
|
|
800a06e: bd80 pop {r7, pc}
|
|
|
|
0800a070 <USBH_OpenPipe>:
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_OpenPipe(USBH_HandleTypeDef *phost, uint8_t pipe_num,
|
|
uint8_t epnum, uint8_t dev_address,
|
|
uint8_t speed, uint8_t ep_type, uint16_t mps)
|
|
{
|
|
800a070: b580 push {r7, lr}
|
|
800a072: b086 sub sp, #24
|
|
800a074: af04 add r7, sp, #16
|
|
800a076: 6078 str r0, [r7, #4]
|
|
800a078: 4608 mov r0, r1
|
|
800a07a: 4611 mov r1, r2
|
|
800a07c: 461a mov r2, r3
|
|
800a07e: 4603 mov r3, r0
|
|
800a080: 70fb strb r3, [r7, #3]
|
|
800a082: 460b mov r3, r1
|
|
800a084: 70bb strb r3, [r7, #2]
|
|
800a086: 4613 mov r3, r2
|
|
800a088: 707b strb r3, [r7, #1]
|
|
(void)USBH_LL_OpenPipe(phost, pipe_num, epnum, dev_address, speed, ep_type, mps);
|
|
800a08a: 7878 ldrb r0, [r7, #1]
|
|
800a08c: 78ba ldrb r2, [r7, #2]
|
|
800a08e: 78f9 ldrb r1, [r7, #3]
|
|
800a090: 8b3b ldrh r3, [r7, #24]
|
|
800a092: 9302 str r3, [sp, #8]
|
|
800a094: 7d3b ldrb r3, [r7, #20]
|
|
800a096: 9301 str r3, [sp, #4]
|
|
800a098: 7c3b ldrb r3, [r7, #16]
|
|
800a09a: 9300 str r3, [sp, #0]
|
|
800a09c: 4603 mov r3, r0
|
|
800a09e: 6878 ldr r0, [r7, #4]
|
|
800a0a0: f002 fd7b bl 800cb9a <USBH_LL_OpenPipe>
|
|
|
|
return USBH_OK;
|
|
800a0a4: 2300 movs r3, #0
|
|
}
|
|
800a0a6: 4618 mov r0, r3
|
|
800a0a8: 3708 adds r7, #8
|
|
800a0aa: 46bd mov sp, r7
|
|
800a0ac: bd80 pop {r7, pc}
|
|
|
|
0800a0ae <USBH_ClosePipe>:
|
|
* @param phost: Host Handle
|
|
* @param pipe_num: Pipe Number
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe_num)
|
|
{
|
|
800a0ae: b580 push {r7, lr}
|
|
800a0b0: b082 sub sp, #8
|
|
800a0b2: af00 add r7, sp, #0
|
|
800a0b4: 6078 str r0, [r7, #4]
|
|
800a0b6: 460b mov r3, r1
|
|
800a0b8: 70fb strb r3, [r7, #3]
|
|
(void)USBH_LL_ClosePipe(phost, pipe_num);
|
|
800a0ba: 78fb ldrb r3, [r7, #3]
|
|
800a0bc: 4619 mov r1, r3
|
|
800a0be: 6878 ldr r0, [r7, #4]
|
|
800a0c0: f002 fd9a bl 800cbf8 <USBH_LL_ClosePipe>
|
|
|
|
return USBH_OK;
|
|
800a0c4: 2300 movs r3, #0
|
|
}
|
|
800a0c6: 4618 mov r0, r3
|
|
800a0c8: 3708 adds r7, #8
|
|
800a0ca: 46bd mov sp, r7
|
|
800a0cc: bd80 pop {r7, pc}
|
|
|
|
0800a0ce <USBH_AllocPipe>:
|
|
* @param phost: Host Handle
|
|
* @param ep_addr: End point for which the Pipe to be allocated
|
|
* @retval Pipe number
|
|
*/
|
|
uint8_t USBH_AllocPipe(USBH_HandleTypeDef *phost, uint8_t ep_addr)
|
|
{
|
|
800a0ce: b580 push {r7, lr}
|
|
800a0d0: b084 sub sp, #16
|
|
800a0d2: af00 add r7, sp, #0
|
|
800a0d4: 6078 str r0, [r7, #4]
|
|
800a0d6: 460b mov r3, r1
|
|
800a0d8: 70fb strb r3, [r7, #3]
|
|
uint16_t pipe;
|
|
|
|
pipe = USBH_GetFreePipe(phost);
|
|
800a0da: 6878 ldr r0, [r7, #4]
|
|
800a0dc: f000 f836 bl 800a14c <USBH_GetFreePipe>
|
|
800a0e0: 4603 mov r3, r0
|
|
800a0e2: 81fb strh r3, [r7, #14]
|
|
|
|
if (pipe != 0xFFFFU)
|
|
800a0e4: 89fb ldrh r3, [r7, #14]
|
|
800a0e6: f64f 72ff movw r2, #65535 @ 0xffff
|
|
800a0ea: 4293 cmp r3, r2
|
|
800a0ec: d00a beq.n 800a104 <USBH_AllocPipe+0x36>
|
|
{
|
|
phost->Pipes[pipe & 0xFU] = (uint32_t)(0x8000U | ep_addr);
|
|
800a0ee: 78fa ldrb r2, [r7, #3]
|
|
800a0f0: 89fb ldrh r3, [r7, #14]
|
|
800a0f2: f003 030f and.w r3, r3, #15
|
|
800a0f6: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
800a0fa: 6879 ldr r1, [r7, #4]
|
|
800a0fc: 33e0 adds r3, #224 @ 0xe0
|
|
800a0fe: 009b lsls r3, r3, #2
|
|
800a100: 440b add r3, r1
|
|
800a102: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return (uint8_t)pipe;
|
|
800a104: 89fb ldrh r3, [r7, #14]
|
|
800a106: b2db uxtb r3, r3
|
|
}
|
|
800a108: 4618 mov r0, r3
|
|
800a10a: 3710 adds r7, #16
|
|
800a10c: 46bd mov sp, r7
|
|
800a10e: bd80 pop {r7, pc}
|
|
|
|
0800a110 <USBH_FreePipe>:
|
|
* @param phost: Host Handle
|
|
* @param idx: Pipe number to be freed
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx)
|
|
{
|
|
800a110: b480 push {r7}
|
|
800a112: b083 sub sp, #12
|
|
800a114: af00 add r7, sp, #0
|
|
800a116: 6078 str r0, [r7, #4]
|
|
800a118: 460b mov r3, r1
|
|
800a11a: 70fb strb r3, [r7, #3]
|
|
if (idx < USBH_MAX_PIPES_NBR)
|
|
800a11c: 78fb ldrb r3, [r7, #3]
|
|
800a11e: 2b0f cmp r3, #15
|
|
800a120: d80d bhi.n 800a13e <USBH_FreePipe+0x2e>
|
|
{
|
|
phost->Pipes[idx] &= 0x7FFFU;
|
|
800a122: 78fb ldrb r3, [r7, #3]
|
|
800a124: 687a ldr r2, [r7, #4]
|
|
800a126: 33e0 adds r3, #224 @ 0xe0
|
|
800a128: 009b lsls r3, r3, #2
|
|
800a12a: 4413 add r3, r2
|
|
800a12c: 685a ldr r2, [r3, #4]
|
|
800a12e: 78fb ldrb r3, [r7, #3]
|
|
800a130: f3c2 020e ubfx r2, r2, #0, #15
|
|
800a134: 6879 ldr r1, [r7, #4]
|
|
800a136: 33e0 adds r3, #224 @ 0xe0
|
|
800a138: 009b lsls r3, r3, #2
|
|
800a13a: 440b add r3, r1
|
|
800a13c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return USBH_OK;
|
|
800a13e: 2300 movs r3, #0
|
|
}
|
|
800a140: 4618 mov r0, r3
|
|
800a142: 370c adds r7, #12
|
|
800a144: 46bd mov sp, r7
|
|
800a146: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a14a: 4770 bx lr
|
|
|
|
0800a14c <USBH_GetFreePipe>:
|
|
* @param phost: Host Handle
|
|
* Get a free Pipe number for allocation to a device endpoint
|
|
* @retval idx: Free Pipe number
|
|
*/
|
|
static uint16_t USBH_GetFreePipe(USBH_HandleTypeDef *phost)
|
|
{
|
|
800a14c: b480 push {r7}
|
|
800a14e: b085 sub sp, #20
|
|
800a150: af00 add r7, sp, #0
|
|
800a152: 6078 str r0, [r7, #4]
|
|
uint8_t idx = 0U;
|
|
800a154: 2300 movs r3, #0
|
|
800a156: 73fb strb r3, [r7, #15]
|
|
|
|
for (idx = 0U; idx < USBH_MAX_PIPES_NBR; idx++)
|
|
800a158: 2300 movs r3, #0
|
|
800a15a: 73fb strb r3, [r7, #15]
|
|
800a15c: e00f b.n 800a17e <USBH_GetFreePipe+0x32>
|
|
{
|
|
if ((phost->Pipes[idx] & 0x8000U) == 0U)
|
|
800a15e: 7bfb ldrb r3, [r7, #15]
|
|
800a160: 687a ldr r2, [r7, #4]
|
|
800a162: 33e0 adds r3, #224 @ 0xe0
|
|
800a164: 009b lsls r3, r3, #2
|
|
800a166: 4413 add r3, r2
|
|
800a168: 685b ldr r3, [r3, #4]
|
|
800a16a: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
800a16e: 2b00 cmp r3, #0
|
|
800a170: d102 bne.n 800a178 <USBH_GetFreePipe+0x2c>
|
|
{
|
|
return (uint16_t)idx;
|
|
800a172: 7bfb ldrb r3, [r7, #15]
|
|
800a174: b29b uxth r3, r3
|
|
800a176: e007 b.n 800a188 <USBH_GetFreePipe+0x3c>
|
|
for (idx = 0U; idx < USBH_MAX_PIPES_NBR; idx++)
|
|
800a178: 7bfb ldrb r3, [r7, #15]
|
|
800a17a: 3301 adds r3, #1
|
|
800a17c: 73fb strb r3, [r7, #15]
|
|
800a17e: 7bfb ldrb r3, [r7, #15]
|
|
800a180: 2b0f cmp r3, #15
|
|
800a182: d9ec bls.n 800a15e <USBH_GetFreePipe+0x12>
|
|
}
|
|
}
|
|
|
|
return 0xFFFFU;
|
|
800a184: f64f 73ff movw r3, #65535 @ 0xffff
|
|
}
|
|
800a188: 4618 mov r0, r3
|
|
800a18a: 3714 adds r7, #20
|
|
800a18c: 46bd mov sp, r7
|
|
800a18e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a192: 4770 bx lr
|
|
|
|
0800a194 <makeFreeRtosPriority>:
|
|
|
|
extern void xPortSysTickHandler(void);
|
|
|
|
/* Convert from CMSIS type osPriority to FreeRTOS priority number */
|
|
static unsigned portBASE_TYPE makeFreeRtosPriority (osPriority priority)
|
|
{
|
|
800a194: b480 push {r7}
|
|
800a196: b085 sub sp, #20
|
|
800a198: af00 add r7, sp, #0
|
|
800a19a: 4603 mov r3, r0
|
|
800a19c: 80fb strh r3, [r7, #6]
|
|
unsigned portBASE_TYPE fpriority = tskIDLE_PRIORITY;
|
|
800a19e: 2300 movs r3, #0
|
|
800a1a0: 60fb str r3, [r7, #12]
|
|
|
|
if (priority != osPriorityError) {
|
|
800a1a2: f9b7 3006 ldrsh.w r3, [r7, #6]
|
|
800a1a6: 2b84 cmp r3, #132 @ 0x84
|
|
800a1a8: d005 beq.n 800a1b6 <makeFreeRtosPriority+0x22>
|
|
fpriority += (priority - osPriorityIdle);
|
|
800a1aa: f9b7 2006 ldrsh.w r2, [r7, #6]
|
|
800a1ae: 68fb ldr r3, [r7, #12]
|
|
800a1b0: 4413 add r3, r2
|
|
800a1b2: 3303 adds r3, #3
|
|
800a1b4: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
return fpriority;
|
|
800a1b6: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800a1b8: 4618 mov r0, r3
|
|
800a1ba: 3714 adds r7, #20
|
|
800a1bc: 46bd mov sp, r7
|
|
800a1be: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a1c2: 4770 bx lr
|
|
|
|
0800a1c4 <inHandlerMode>:
|
|
#endif
|
|
|
|
|
|
/* Determine whether we are in thread mode or handler mode. */
|
|
static int inHandlerMode (void)
|
|
{
|
|
800a1c4: b480 push {r7}
|
|
800a1c6: b083 sub sp, #12
|
|
800a1c8: af00 add r7, sp, #0
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
800a1ca: f3ef 8305 mrs r3, IPSR
|
|
800a1ce: 607b str r3, [r7, #4]
|
|
return(result);
|
|
800a1d0: 687b ldr r3, [r7, #4]
|
|
return __get_IPSR() != 0;
|
|
800a1d2: 2b00 cmp r3, #0
|
|
800a1d4: bf14 ite ne
|
|
800a1d6: 2301 movne r3, #1
|
|
800a1d8: 2300 moveq r3, #0
|
|
800a1da: b2db uxtb r3, r3
|
|
}
|
|
800a1dc: 4618 mov r0, r3
|
|
800a1de: 370c adds r7, #12
|
|
800a1e0: 46bd mov sp, r7
|
|
800a1e2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a1e6: 4770 bx lr
|
|
|
|
0800a1e8 <osKernelStart>:
|
|
* @param argument pointer that is passed to the thread function as start argument.
|
|
* @retval status code that indicates the execution status of the function
|
|
* @note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osKernelStart (void)
|
|
{
|
|
800a1e8: b580 push {r7, lr}
|
|
800a1ea: af00 add r7, sp, #0
|
|
vTaskStartScheduler();
|
|
800a1ec: f001 f976 bl 800b4dc <vTaskStartScheduler>
|
|
|
|
return osOK;
|
|
800a1f0: 2300 movs r3, #0
|
|
}
|
|
800a1f2: 4618 mov r0, r3
|
|
800a1f4: bd80 pop {r7, pc}
|
|
|
|
0800a1f6 <osThreadCreate>:
|
|
* @param argument pointer that is passed to the thread function as start argument.
|
|
* @retval thread ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument)
|
|
{
|
|
800a1f6: b5f0 push {r4, r5, r6, r7, lr}
|
|
800a1f8: b089 sub sp, #36 @ 0x24
|
|
800a1fa: af04 add r7, sp, #16
|
|
800a1fc: 6078 str r0, [r7, #4]
|
|
800a1fe: 6039 str r1, [r7, #0]
|
|
TaskHandle_t handle;
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
if((thread_def->buffer != NULL) && (thread_def->controlblock != NULL)) {
|
|
800a200: 687b ldr r3, [r7, #4]
|
|
800a202: 695b ldr r3, [r3, #20]
|
|
800a204: 2b00 cmp r3, #0
|
|
800a206: d020 beq.n 800a24a <osThreadCreate+0x54>
|
|
800a208: 687b ldr r3, [r7, #4]
|
|
800a20a: 699b ldr r3, [r3, #24]
|
|
800a20c: 2b00 cmp r3, #0
|
|
800a20e: d01c beq.n 800a24a <osThreadCreate+0x54>
|
|
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a210: 687b ldr r3, [r7, #4]
|
|
800a212: 685c ldr r4, [r3, #4]
|
|
800a214: 687b ldr r3, [r7, #4]
|
|
800a216: 681d ldr r5, [r3, #0]
|
|
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
|
|
800a218: 687b ldr r3, [r7, #4]
|
|
800a21a: 691e ldr r6, [r3, #16]
|
|
800a21c: 687b ldr r3, [r7, #4]
|
|
800a21e: f9b3 3008 ldrsh.w r3, [r3, #8]
|
|
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a222: 4618 mov r0, r3
|
|
800a224: f7ff ffb6 bl 800a194 <makeFreeRtosPriority>
|
|
800a228: 4601 mov r1, r0
|
|
thread_def->buffer, thread_def->controlblock);
|
|
800a22a: 687b ldr r3, [r7, #4]
|
|
800a22c: 695b ldr r3, [r3, #20]
|
|
800a22e: 687a ldr r2, [r7, #4]
|
|
800a230: 6992 ldr r2, [r2, #24]
|
|
handle = xTaskCreateStatic((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a232: 9202 str r2, [sp, #8]
|
|
800a234: 9301 str r3, [sp, #4]
|
|
800a236: 9100 str r1, [sp, #0]
|
|
800a238: 683b ldr r3, [r7, #0]
|
|
800a23a: 4632 mov r2, r6
|
|
800a23c: 4629 mov r1, r5
|
|
800a23e: 4620 mov r0, r4
|
|
800a240: f000 ff74 bl 800b12c <xTaskCreateStatic>
|
|
800a244: 4603 mov r3, r0
|
|
800a246: 60fb str r3, [r7, #12]
|
|
800a248: e01c b.n 800a284 <osThreadCreate+0x8e>
|
|
}
|
|
else {
|
|
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a24a: 687b ldr r3, [r7, #4]
|
|
800a24c: 685c ldr r4, [r3, #4]
|
|
800a24e: 687b ldr r3, [r7, #4]
|
|
800a250: 681d ldr r5, [r3, #0]
|
|
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
|
|
800a252: 687b ldr r3, [r7, #4]
|
|
800a254: 691b ldr r3, [r3, #16]
|
|
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a256: b29e uxth r6, r3
|
|
thread_def->stacksize, argument, makeFreeRtosPriority(thread_def->tpriority),
|
|
800a258: 687b ldr r3, [r7, #4]
|
|
800a25a: f9b3 3008 ldrsh.w r3, [r3, #8]
|
|
if (xTaskCreate((TaskFunction_t)thread_def->pthread,(const portCHAR *)thread_def->name,
|
|
800a25e: 4618 mov r0, r3
|
|
800a260: f7ff ff98 bl 800a194 <makeFreeRtosPriority>
|
|
800a264: 4602 mov r2, r0
|
|
800a266: f107 030c add.w r3, r7, #12
|
|
800a26a: 9301 str r3, [sp, #4]
|
|
800a26c: 9200 str r2, [sp, #0]
|
|
800a26e: 683b ldr r3, [r7, #0]
|
|
800a270: 4632 mov r2, r6
|
|
800a272: 4629 mov r1, r5
|
|
800a274: 4620 mov r0, r4
|
|
800a276: f000 ffb9 bl 800b1ec <xTaskCreate>
|
|
800a27a: 4603 mov r3, r0
|
|
800a27c: 2b01 cmp r3, #1
|
|
800a27e: d001 beq.n 800a284 <osThreadCreate+0x8e>
|
|
&handle) != pdPASS) {
|
|
return NULL;
|
|
800a280: 2300 movs r3, #0
|
|
800a282: e000 b.n 800a286 <osThreadCreate+0x90>
|
|
&handle) != pdPASS) {
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
return handle;
|
|
800a284: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800a286: 4618 mov r0, r3
|
|
800a288: 3714 adds r7, #20
|
|
800a28a: 46bd mov sp, r7
|
|
800a28c: bdf0 pop {r4, r5, r6, r7, pc}
|
|
|
|
0800a28e <osDelay>:
|
|
* @brief Wait for Timeout (Time Delay)
|
|
* @param millisec time delay value
|
|
* @retval status code that indicates the execution status of the function.
|
|
*/
|
|
osStatus osDelay (uint32_t millisec)
|
|
{
|
|
800a28e: b580 push {r7, lr}
|
|
800a290: b084 sub sp, #16
|
|
800a292: af00 add r7, sp, #0
|
|
800a294: 6078 str r0, [r7, #4]
|
|
#if INCLUDE_vTaskDelay
|
|
TickType_t ticks = millisec / portTICK_PERIOD_MS;
|
|
800a296: 687b ldr r3, [r7, #4]
|
|
800a298: 60fb str r3, [r7, #12]
|
|
|
|
vTaskDelay(ticks ? ticks : 1); /* Minimum delay = 1 tick */
|
|
800a29a: 68fb ldr r3, [r7, #12]
|
|
800a29c: 2b00 cmp r3, #0
|
|
800a29e: d001 beq.n 800a2a4 <osDelay+0x16>
|
|
800a2a0: 68fb ldr r3, [r7, #12]
|
|
800a2a2: e000 b.n 800a2a6 <osDelay+0x18>
|
|
800a2a4: 2301 movs r3, #1
|
|
800a2a6: 4618 mov r0, r3
|
|
800a2a8: f001 f8e2 bl 800b470 <vTaskDelay>
|
|
|
|
return osOK;
|
|
800a2ac: 2300 movs r3, #0
|
|
#else
|
|
(void) millisec;
|
|
|
|
return osErrorResource;
|
|
#endif
|
|
}
|
|
800a2ae: 4618 mov r0, r3
|
|
800a2b0: 3710 adds r7, #16
|
|
800a2b2: 46bd mov sp, r7
|
|
800a2b4: bd80 pop {r7, pc}
|
|
|
|
0800a2b6 <osMessageCreate>:
|
|
* @param thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
|
|
* @retval message queue ID for reference by other functions or NULL in case of error.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id)
|
|
{
|
|
800a2b6: b590 push {r4, r7, lr}
|
|
800a2b8: b085 sub sp, #20
|
|
800a2ba: af02 add r7, sp, #8
|
|
800a2bc: 6078 str r0, [r7, #4]
|
|
800a2be: 6039 str r1, [r7, #0]
|
|
(void) thread_id;
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
if ((queue_def->buffer != NULL) && (queue_def->controlblock != NULL)) {
|
|
800a2c0: 687b ldr r3, [r7, #4]
|
|
800a2c2: 689b ldr r3, [r3, #8]
|
|
800a2c4: 2b00 cmp r3, #0
|
|
800a2c6: d011 beq.n 800a2ec <osMessageCreate+0x36>
|
|
800a2c8: 687b ldr r3, [r7, #4]
|
|
800a2ca: 68db ldr r3, [r3, #12]
|
|
800a2cc: 2b00 cmp r3, #0
|
|
800a2ce: d00d beq.n 800a2ec <osMessageCreate+0x36>
|
|
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
|
|
800a2d0: 687b ldr r3, [r7, #4]
|
|
800a2d2: 6818 ldr r0, [r3, #0]
|
|
800a2d4: 687b ldr r3, [r7, #4]
|
|
800a2d6: 6859 ldr r1, [r3, #4]
|
|
800a2d8: 687b ldr r3, [r7, #4]
|
|
800a2da: 689a ldr r2, [r3, #8]
|
|
800a2dc: 687b ldr r3, [r7, #4]
|
|
800a2de: 68db ldr r3, [r3, #12]
|
|
800a2e0: 2400 movs r4, #0
|
|
800a2e2: 9400 str r4, [sp, #0]
|
|
800a2e4: f000 f9f8 bl 800a6d8 <xQueueGenericCreateStatic>
|
|
800a2e8: 4603 mov r3, r0
|
|
800a2ea: e008 b.n 800a2fe <osMessageCreate+0x48>
|
|
}
|
|
else {
|
|
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
|
|
800a2ec: 687b ldr r3, [r7, #4]
|
|
800a2ee: 6818 ldr r0, [r3, #0]
|
|
800a2f0: 687b ldr r3, [r7, #4]
|
|
800a2f2: 685b ldr r3, [r3, #4]
|
|
800a2f4: 2200 movs r2, #0
|
|
800a2f6: 4619 mov r1, r3
|
|
800a2f8: f000 fa6b bl 800a7d2 <xQueueGenericCreate>
|
|
800a2fc: 4603 mov r3, r0
|
|
#elif ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
return xQueueCreateStatic(queue_def->queue_sz, queue_def->item_sz, queue_def->buffer, queue_def->controlblock);
|
|
#else
|
|
return xQueueCreate(queue_def->queue_sz, queue_def->item_sz);
|
|
#endif
|
|
}
|
|
800a2fe: 4618 mov r0, r3
|
|
800a300: 370c adds r7, #12
|
|
800a302: 46bd mov sp, r7
|
|
800a304: bd90 pop {r4, r7, pc}
|
|
...
|
|
|
|
0800a308 <osMessagePut>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
|
|
{
|
|
800a308: b580 push {r7, lr}
|
|
800a30a: b086 sub sp, #24
|
|
800a30c: af00 add r7, sp, #0
|
|
800a30e: 60f8 str r0, [r7, #12]
|
|
800a310: 60b9 str r1, [r7, #8]
|
|
800a312: 607a str r2, [r7, #4]
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
800a314: 2300 movs r3, #0
|
|
800a316: 613b str r3, [r7, #16]
|
|
TickType_t ticks;
|
|
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800a318: 687b ldr r3, [r7, #4]
|
|
800a31a: 617b str r3, [r7, #20]
|
|
if (ticks == 0) {
|
|
800a31c: 697b ldr r3, [r7, #20]
|
|
800a31e: 2b00 cmp r3, #0
|
|
800a320: d101 bne.n 800a326 <osMessagePut+0x1e>
|
|
ticks = 1;
|
|
800a322: 2301 movs r3, #1
|
|
800a324: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800a326: f7ff ff4d bl 800a1c4 <inHandlerMode>
|
|
800a32a: 4603 mov r3, r0
|
|
800a32c: 2b00 cmp r3, #0
|
|
800a32e: d018 beq.n 800a362 <osMessagePut+0x5a>
|
|
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
|
|
800a330: f107 0210 add.w r2, r7, #16
|
|
800a334: f107 0108 add.w r1, r7, #8
|
|
800a338: 2300 movs r3, #0
|
|
800a33a: 68f8 ldr r0, [r7, #12]
|
|
800a33c: f000 fba6 bl 800aa8c <xQueueGenericSendFromISR>
|
|
800a340: 4603 mov r3, r0
|
|
800a342: 2b01 cmp r3, #1
|
|
800a344: d001 beq.n 800a34a <osMessagePut+0x42>
|
|
return osErrorOS;
|
|
800a346: 23ff movs r3, #255 @ 0xff
|
|
800a348: e018 b.n 800a37c <osMessagePut+0x74>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800a34a: 693b ldr r3, [r7, #16]
|
|
800a34c: 2b00 cmp r3, #0
|
|
800a34e: d014 beq.n 800a37a <osMessagePut+0x72>
|
|
800a350: 4b0c ldr r3, [pc, #48] @ (800a384 <osMessagePut+0x7c>)
|
|
800a352: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800a356: 601a str r2, [r3, #0]
|
|
800a358: f3bf 8f4f dsb sy
|
|
800a35c: f3bf 8f6f isb sy
|
|
800a360: e00b b.n 800a37a <osMessagePut+0x72>
|
|
}
|
|
else {
|
|
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
|
|
800a362: f107 0108 add.w r1, r7, #8
|
|
800a366: 2300 movs r3, #0
|
|
800a368: 697a ldr r2, [r7, #20]
|
|
800a36a: 68f8 ldr r0, [r7, #12]
|
|
800a36c: f000 fa8c bl 800a888 <xQueueGenericSend>
|
|
800a370: 4603 mov r3, r0
|
|
800a372: 2b01 cmp r3, #1
|
|
800a374: d001 beq.n 800a37a <osMessagePut+0x72>
|
|
return osErrorOS;
|
|
800a376: 23ff movs r3, #255 @ 0xff
|
|
800a378: e000 b.n 800a37c <osMessagePut+0x74>
|
|
}
|
|
}
|
|
|
|
return osOK;
|
|
800a37a: 2300 movs r3, #0
|
|
}
|
|
800a37c: 4618 mov r0, r3
|
|
800a37e: 3718 adds r7, #24
|
|
800a380: 46bd mov sp, r7
|
|
800a382: bd80 pop {r7, pc}
|
|
800a384: e000ed04 .word 0xe000ed04
|
|
|
|
0800a388 <osMessageGet>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval event information that includes status code.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec)
|
|
{
|
|
800a388: b590 push {r4, r7, lr}
|
|
800a38a: b08b sub sp, #44 @ 0x2c
|
|
800a38c: af00 add r7, sp, #0
|
|
800a38e: 60f8 str r0, [r7, #12]
|
|
800a390: 60b9 str r1, [r7, #8]
|
|
800a392: 607a str r2, [r7, #4]
|
|
portBASE_TYPE taskWoken;
|
|
TickType_t ticks;
|
|
osEvent event;
|
|
|
|
event.def.message_id = queue_id;
|
|
800a394: 68bb ldr r3, [r7, #8]
|
|
800a396: 61fb str r3, [r7, #28]
|
|
event.value.v = 0;
|
|
800a398: 2300 movs r3, #0
|
|
800a39a: 61bb str r3, [r7, #24]
|
|
|
|
if (queue_id == NULL) {
|
|
800a39c: 68bb ldr r3, [r7, #8]
|
|
800a39e: 2b00 cmp r3, #0
|
|
800a3a0: d10a bne.n 800a3b8 <osMessageGet+0x30>
|
|
event.status = osErrorParameter;
|
|
800a3a2: 2380 movs r3, #128 @ 0x80
|
|
800a3a4: 617b str r3, [r7, #20]
|
|
return event;
|
|
800a3a6: 68fb ldr r3, [r7, #12]
|
|
800a3a8: 461c mov r4, r3
|
|
800a3aa: f107 0314 add.w r3, r7, #20
|
|
800a3ae: e893 0007 ldmia.w r3, {r0, r1, r2}
|
|
800a3b2: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
800a3b6: e054 b.n 800a462 <osMessageGet+0xda>
|
|
}
|
|
|
|
taskWoken = pdFALSE;
|
|
800a3b8: 2300 movs r3, #0
|
|
800a3ba: 623b str r3, [r7, #32]
|
|
|
|
ticks = 0;
|
|
800a3bc: 2300 movs r3, #0
|
|
800a3be: 627b str r3, [r7, #36] @ 0x24
|
|
if (millisec == osWaitForever) {
|
|
800a3c0: 687b ldr r3, [r7, #4]
|
|
800a3c2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800a3c6: d103 bne.n 800a3d0 <osMessageGet+0x48>
|
|
ticks = portMAX_DELAY;
|
|
800a3c8: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800a3cc: 627b str r3, [r7, #36] @ 0x24
|
|
800a3ce: e009 b.n 800a3e4 <osMessageGet+0x5c>
|
|
}
|
|
else if (millisec != 0) {
|
|
800a3d0: 687b ldr r3, [r7, #4]
|
|
800a3d2: 2b00 cmp r3, #0
|
|
800a3d4: d006 beq.n 800a3e4 <osMessageGet+0x5c>
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
800a3d6: 687b ldr r3, [r7, #4]
|
|
800a3d8: 627b str r3, [r7, #36] @ 0x24
|
|
if (ticks == 0) {
|
|
800a3da: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a3dc: 2b00 cmp r3, #0
|
|
800a3de: d101 bne.n 800a3e4 <osMessageGet+0x5c>
|
|
ticks = 1;
|
|
800a3e0: 2301 movs r3, #1
|
|
800a3e2: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
800a3e4: f7ff feee bl 800a1c4 <inHandlerMode>
|
|
800a3e8: 4603 mov r3, r0
|
|
800a3ea: 2b00 cmp r3, #0
|
|
800a3ec: d01c beq.n 800a428 <osMessageGet+0xa0>
|
|
if (xQueueReceiveFromISR(queue_id, &event.value.v, &taskWoken) == pdTRUE) {
|
|
800a3ee: f107 0220 add.w r2, r7, #32
|
|
800a3f2: f107 0314 add.w r3, r7, #20
|
|
800a3f6: 3304 adds r3, #4
|
|
800a3f8: 4619 mov r1, r3
|
|
800a3fa: 68b8 ldr r0, [r7, #8]
|
|
800a3fc: f000 fcc6 bl 800ad8c <xQueueReceiveFromISR>
|
|
800a400: 4603 mov r3, r0
|
|
800a402: 2b01 cmp r3, #1
|
|
800a404: d102 bne.n 800a40c <osMessageGet+0x84>
|
|
/* We have mail */
|
|
event.status = osEventMessage;
|
|
800a406: 2310 movs r3, #16
|
|
800a408: 617b str r3, [r7, #20]
|
|
800a40a: e001 b.n 800a410 <osMessageGet+0x88>
|
|
}
|
|
else {
|
|
event.status = osOK;
|
|
800a40c: 2300 movs r3, #0
|
|
800a40e: 617b str r3, [r7, #20]
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
800a410: 6a3b ldr r3, [r7, #32]
|
|
800a412: 2b00 cmp r3, #0
|
|
800a414: d01d beq.n 800a452 <osMessageGet+0xca>
|
|
800a416: 4b15 ldr r3, [pc, #84] @ (800a46c <osMessageGet+0xe4>)
|
|
800a418: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800a41c: 601a str r2, [r3, #0]
|
|
800a41e: f3bf 8f4f dsb sy
|
|
800a422: f3bf 8f6f isb sy
|
|
800a426: e014 b.n 800a452 <osMessageGet+0xca>
|
|
}
|
|
else {
|
|
if (xQueueReceive(queue_id, &event.value.v, ticks) == pdTRUE) {
|
|
800a428: f107 0314 add.w r3, r7, #20
|
|
800a42c: 3304 adds r3, #4
|
|
800a42e: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800a430: 4619 mov r1, r3
|
|
800a432: 68b8 ldr r0, [r7, #8]
|
|
800a434: f000 fbc8 bl 800abc8 <xQueueReceive>
|
|
800a438: 4603 mov r3, r0
|
|
800a43a: 2b01 cmp r3, #1
|
|
800a43c: d102 bne.n 800a444 <osMessageGet+0xbc>
|
|
/* We have mail */
|
|
event.status = osEventMessage;
|
|
800a43e: 2310 movs r3, #16
|
|
800a440: 617b str r3, [r7, #20]
|
|
800a442: e006 b.n 800a452 <osMessageGet+0xca>
|
|
}
|
|
else {
|
|
event.status = (ticks == 0) ? osOK : osEventTimeout;
|
|
800a444: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800a446: 2b00 cmp r3, #0
|
|
800a448: d101 bne.n 800a44e <osMessageGet+0xc6>
|
|
800a44a: 2300 movs r3, #0
|
|
800a44c: e000 b.n 800a450 <osMessageGet+0xc8>
|
|
800a44e: 2340 movs r3, #64 @ 0x40
|
|
800a450: 617b str r3, [r7, #20]
|
|
}
|
|
}
|
|
|
|
return event;
|
|
800a452: 68fb ldr r3, [r7, #12]
|
|
800a454: 461c mov r4, r3
|
|
800a456: f107 0314 add.w r3, r7, #20
|
|
800a45a: e893 0007 ldmia.w r3, {r0, r1, r2}
|
|
800a45e: e884 0007 stmia.w r4, {r0, r1, r2}
|
|
}
|
|
800a462: 68f8 ldr r0, [r7, #12]
|
|
800a464: 372c adds r7, #44 @ 0x2c
|
|
800a466: 46bd mov sp, r7
|
|
800a468: bd90 pop {r4, r7, pc}
|
|
800a46a: bf00 nop
|
|
800a46c: e000ed04 .word 0xe000ed04
|
|
|
|
0800a470 <osMessageWaiting>:
|
|
* @brief Get the number of messaged stored in a queue.
|
|
* @param queue_id message queue ID obtained with \ref osMessageCreate.
|
|
* @retval number of messages stored in a queue.
|
|
*/
|
|
uint32_t osMessageWaiting(osMessageQId queue_id)
|
|
{
|
|
800a470: b580 push {r7, lr}
|
|
800a472: b082 sub sp, #8
|
|
800a474: af00 add r7, sp, #0
|
|
800a476: 6078 str r0, [r7, #4]
|
|
if (inHandlerMode()) {
|
|
800a478: f7ff fea4 bl 800a1c4 <inHandlerMode>
|
|
800a47c: 4603 mov r3, r0
|
|
800a47e: 2b00 cmp r3, #0
|
|
800a480: d004 beq.n 800a48c <osMessageWaiting+0x1c>
|
|
return uxQueueMessagesWaitingFromISR(queue_id);
|
|
800a482: 6878 ldr r0, [r7, #4]
|
|
800a484: f000 fd23 bl 800aece <uxQueueMessagesWaitingFromISR>
|
|
800a488: 4603 mov r3, r0
|
|
800a48a: e003 b.n 800a494 <osMessageWaiting+0x24>
|
|
}
|
|
else
|
|
{
|
|
return uxQueueMessagesWaiting(queue_id);
|
|
800a48c: 6878 ldr r0, [r7, #4]
|
|
800a48e: f000 fcff bl 800ae90 <uxQueueMessagesWaiting>
|
|
800a492: 4603 mov r3, r0
|
|
}
|
|
}
|
|
800a494: 4618 mov r0, r3
|
|
800a496: 3708 adds r7, #8
|
|
800a498: 46bd mov sp, r7
|
|
800a49a: bd80 pop {r7, pc}
|
|
|
|
0800a49c <vListInitialise>:
|
|
/*-----------------------------------------------------------
|
|
* PUBLIC LIST API documented in list.h
|
|
*----------------------------------------------------------*/
|
|
|
|
void vListInitialise( List_t * const pxList )
|
|
{
|
|
800a49c: b480 push {r7}
|
|
800a49e: b083 sub sp, #12
|
|
800a4a0: af00 add r7, sp, #0
|
|
800a4a2: 6078 str r0, [r7, #4]
|
|
/* The list structure contains a list item which is used to mark the
|
|
end of the list. To initialise the list the list end is inserted
|
|
as the only list entry. */
|
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800a4a4: 687b ldr r3, [r7, #4]
|
|
800a4a6: f103 0208 add.w r2, r3, #8
|
|
800a4aa: 687b ldr r3, [r7, #4]
|
|
800a4ac: 605a str r2, [r3, #4]
|
|
|
|
/* The list end value is the highest possible value in the list to
|
|
ensure it remains at the end of the list. */
|
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
|
800a4ae: 687b ldr r3, [r7, #4]
|
|
800a4b0: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800a4b4: 609a str r2, [r3, #8]
|
|
|
|
/* The list end next and previous pointers point to itself so we know
|
|
when the list is empty. */
|
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800a4b6: 687b ldr r3, [r7, #4]
|
|
800a4b8: f103 0208 add.w r2, r3, #8
|
|
800a4bc: 687b ldr r3, [r7, #4]
|
|
800a4be: 60da str r2, [r3, #12]
|
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
|
800a4c0: 687b ldr r3, [r7, #4]
|
|
800a4c2: f103 0208 add.w r2, r3, #8
|
|
800a4c6: 687b ldr r3, [r7, #4]
|
|
800a4c8: 611a str r2, [r3, #16]
|
|
|
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
|
800a4ca: 687b ldr r3, [r7, #4]
|
|
800a4cc: 2200 movs r2, #0
|
|
800a4ce: 601a str r2, [r3, #0]
|
|
|
|
/* Write known values into the list if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
|
}
|
|
800a4d0: bf00 nop
|
|
800a4d2: 370c adds r7, #12
|
|
800a4d4: 46bd mov sp, r7
|
|
800a4d6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a4da: 4770 bx lr
|
|
|
|
0800a4dc <vListInitialiseItem>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
|
{
|
|
800a4dc: b480 push {r7}
|
|
800a4de: b083 sub sp, #12
|
|
800a4e0: af00 add r7, sp, #0
|
|
800a4e2: 6078 str r0, [r7, #4]
|
|
/* Make sure the list item is not recorded as being on a list. */
|
|
pxItem->pxContainer = NULL;
|
|
800a4e4: 687b ldr r3, [r7, #4]
|
|
800a4e6: 2200 movs r2, #0
|
|
800a4e8: 611a str r2, [r3, #16]
|
|
|
|
/* Write known values into the list item if
|
|
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
}
|
|
800a4ea: bf00 nop
|
|
800a4ec: 370c adds r7, #12
|
|
800a4ee: 46bd mov sp, r7
|
|
800a4f0: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a4f4: 4770 bx lr
|
|
|
|
0800a4f6 <vListInsertEnd>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800a4f6: b480 push {r7}
|
|
800a4f8: b085 sub sp, #20
|
|
800a4fa: af00 add r7, sp, #0
|
|
800a4fc: 6078 str r0, [r7, #4]
|
|
800a4fe: 6039 str r1, [r7, #0]
|
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
|
800a500: 687b ldr r3, [r7, #4]
|
|
800a502: 685b ldr r3, [r3, #4]
|
|
800a504: 60fb str r3, [r7, #12]
|
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
|
|
|
/* Insert a new list item into pxList, but rather than sort the list,
|
|
makes the new list item the last item to be removed by a call to
|
|
listGET_OWNER_OF_NEXT_ENTRY(). */
|
|
pxNewListItem->pxNext = pxIndex;
|
|
800a506: 683b ldr r3, [r7, #0]
|
|
800a508: 68fa ldr r2, [r7, #12]
|
|
800a50a: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
|
800a50c: 68fb ldr r3, [r7, #12]
|
|
800a50e: 689a ldr r2, [r3, #8]
|
|
800a510: 683b ldr r3, [r7, #0]
|
|
800a512: 609a str r2, [r3, #8]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
|
800a514: 68fb ldr r3, [r7, #12]
|
|
800a516: 689b ldr r3, [r3, #8]
|
|
800a518: 683a ldr r2, [r7, #0]
|
|
800a51a: 605a str r2, [r3, #4]
|
|
pxIndex->pxPrevious = pxNewListItem;
|
|
800a51c: 68fb ldr r3, [r7, #12]
|
|
800a51e: 683a ldr r2, [r7, #0]
|
|
800a520: 609a str r2, [r3, #8]
|
|
|
|
/* Remember which list the item is in. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800a522: 683b ldr r3, [r7, #0]
|
|
800a524: 687a ldr r2, [r7, #4]
|
|
800a526: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800a528: 687b ldr r3, [r7, #4]
|
|
800a52a: 681b ldr r3, [r3, #0]
|
|
800a52c: 1c5a adds r2, r3, #1
|
|
800a52e: 687b ldr r3, [r7, #4]
|
|
800a530: 601a str r2, [r3, #0]
|
|
}
|
|
800a532: bf00 nop
|
|
800a534: 3714 adds r7, #20
|
|
800a536: 46bd mov sp, r7
|
|
800a538: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a53c: 4770 bx lr
|
|
|
|
0800a53e <vListInsert>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
800a53e: b480 push {r7}
|
|
800a540: b085 sub sp, #20
|
|
800a542: af00 add r7, sp, #0
|
|
800a544: 6078 str r0, [r7, #4]
|
|
800a546: 6039 str r1, [r7, #0]
|
|
ListItem_t *pxIterator;
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
|
800a548: 683b ldr r3, [r7, #0]
|
|
800a54a: 681b ldr r3, [r3, #0]
|
|
800a54c: 60bb str r3, [r7, #8]
|
|
new list item should be placed after it. This ensures that TCBs which are
|
|
stored in ready lists (all of which have the same xItemValue value) get a
|
|
share of the CPU. However, if the xItemValue is the same as the back marker
|
|
the iteration loop below will not end. Therefore the value is checked
|
|
first, and the algorithm slightly modified if necessary. */
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
|
800a54e: 68bb ldr r3, [r7, #8]
|
|
800a550: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800a554: d103 bne.n 800a55e <vListInsert+0x20>
|
|
{
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
|
800a556: 687b ldr r3, [r7, #4]
|
|
800a558: 691b ldr r3, [r3, #16]
|
|
800a55a: 60fb str r3, [r7, #12]
|
|
800a55c: e00c b.n 800a578 <vListInsert+0x3a>
|
|
4) Using a queue or semaphore before it has been initialised or
|
|
before the scheduler has been started (are interrupts firing
|
|
before vTaskStartScheduler() has been called?).
|
|
**********************************************************************/
|
|
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
|
800a55e: 687b ldr r3, [r7, #4]
|
|
800a560: 3308 adds r3, #8
|
|
800a562: 60fb str r3, [r7, #12]
|
|
800a564: e002 b.n 800a56c <vListInsert+0x2e>
|
|
800a566: 68fb ldr r3, [r7, #12]
|
|
800a568: 685b ldr r3, [r3, #4]
|
|
800a56a: 60fb str r3, [r7, #12]
|
|
800a56c: 68fb ldr r3, [r7, #12]
|
|
800a56e: 685b ldr r3, [r3, #4]
|
|
800a570: 681b ldr r3, [r3, #0]
|
|
800a572: 68ba ldr r2, [r7, #8]
|
|
800a574: 429a cmp r2, r3
|
|
800a576: d2f6 bcs.n 800a566 <vListInsert+0x28>
|
|
/* There is nothing to do here, just iterating to the wanted
|
|
insertion position. */
|
|
}
|
|
}
|
|
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
|
800a578: 68fb ldr r3, [r7, #12]
|
|
800a57a: 685a ldr r2, [r3, #4]
|
|
800a57c: 683b ldr r3, [r7, #0]
|
|
800a57e: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
|
800a580: 683b ldr r3, [r7, #0]
|
|
800a582: 685b ldr r3, [r3, #4]
|
|
800a584: 683a ldr r2, [r7, #0]
|
|
800a586: 609a str r2, [r3, #8]
|
|
pxNewListItem->pxPrevious = pxIterator;
|
|
800a588: 683b ldr r3, [r7, #0]
|
|
800a58a: 68fa ldr r2, [r7, #12]
|
|
800a58c: 609a str r2, [r3, #8]
|
|
pxIterator->pxNext = pxNewListItem;
|
|
800a58e: 68fb ldr r3, [r7, #12]
|
|
800a590: 683a ldr r2, [r7, #0]
|
|
800a592: 605a str r2, [r3, #4]
|
|
|
|
/* Remember which list the item is in. This allows fast removal of the
|
|
item later. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
800a594: 683b ldr r3, [r7, #0]
|
|
800a596: 687a ldr r2, [r7, #4]
|
|
800a598: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
800a59a: 687b ldr r3, [r7, #4]
|
|
800a59c: 681b ldr r3, [r3, #0]
|
|
800a59e: 1c5a adds r2, r3, #1
|
|
800a5a0: 687b ldr r3, [r7, #4]
|
|
800a5a2: 601a str r2, [r3, #0]
|
|
}
|
|
800a5a4: bf00 nop
|
|
800a5a6: 3714 adds r7, #20
|
|
800a5a8: 46bd mov sp, r7
|
|
800a5aa: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a5ae: 4770 bx lr
|
|
|
|
0800a5b0 <uxListRemove>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
|
{
|
|
800a5b0: b480 push {r7}
|
|
800a5b2: b085 sub sp, #20
|
|
800a5b4: af00 add r7, sp, #0
|
|
800a5b6: 6078 str r0, [r7, #4]
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
|
item. */
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
|
800a5b8: 687b ldr r3, [r7, #4]
|
|
800a5ba: 691b ldr r3, [r3, #16]
|
|
800a5bc: 60fb str r3, [r7, #12]
|
|
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
|
800a5be: 687b ldr r3, [r7, #4]
|
|
800a5c0: 685b ldr r3, [r3, #4]
|
|
800a5c2: 687a ldr r2, [r7, #4]
|
|
800a5c4: 6892 ldr r2, [r2, #8]
|
|
800a5c6: 609a str r2, [r3, #8]
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
|
800a5c8: 687b ldr r3, [r7, #4]
|
|
800a5ca: 689b ldr r3, [r3, #8]
|
|
800a5cc: 687a ldr r2, [r7, #4]
|
|
800a5ce: 6852 ldr r2, [r2, #4]
|
|
800a5d0: 605a str r2, [r3, #4]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
/* Make sure the index is left pointing to a valid item. */
|
|
if( pxList->pxIndex == pxItemToRemove )
|
|
800a5d2: 68fb ldr r3, [r7, #12]
|
|
800a5d4: 685b ldr r3, [r3, #4]
|
|
800a5d6: 687a ldr r2, [r7, #4]
|
|
800a5d8: 429a cmp r2, r3
|
|
800a5da: d103 bne.n 800a5e4 <uxListRemove+0x34>
|
|
{
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
|
800a5dc: 687b ldr r3, [r7, #4]
|
|
800a5de: 689a ldr r2, [r3, #8]
|
|
800a5e0: 68fb ldr r3, [r7, #12]
|
|
800a5e2: 605a str r2, [r3, #4]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxItemToRemove->pxContainer = NULL;
|
|
800a5e4: 687b ldr r3, [r7, #4]
|
|
800a5e6: 2200 movs r2, #0
|
|
800a5e8: 611a str r2, [r3, #16]
|
|
( pxList->uxNumberOfItems )--;
|
|
800a5ea: 68fb ldr r3, [r7, #12]
|
|
800a5ec: 681b ldr r3, [r3, #0]
|
|
800a5ee: 1e5a subs r2, r3, #1
|
|
800a5f0: 68fb ldr r3, [r7, #12]
|
|
800a5f2: 601a str r2, [r3, #0]
|
|
|
|
return pxList->uxNumberOfItems;
|
|
800a5f4: 68fb ldr r3, [r7, #12]
|
|
800a5f6: 681b ldr r3, [r3, #0]
|
|
}
|
|
800a5f8: 4618 mov r0, r3
|
|
800a5fa: 3714 adds r7, #20
|
|
800a5fc: 46bd mov sp, r7
|
|
800a5fe: f85d 7b04 ldr.w r7, [sp], #4
|
|
800a602: 4770 bx lr
|
|
|
|
0800a604 <xQueueGenericReset>:
|
|
} \
|
|
taskEXIT_CRITICAL()
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
|
|
{
|
|
800a604: b580 push {r7, lr}
|
|
800a606: b084 sub sp, #16
|
|
800a608: af00 add r7, sp, #0
|
|
800a60a: 6078 str r0, [r7, #4]
|
|
800a60c: 6039 str r1, [r7, #0]
|
|
Queue_t * const pxQueue = xQueue;
|
|
800a60e: 687b ldr r3, [r7, #4]
|
|
800a610: 60fb str r3, [r7, #12]
|
|
|
|
configASSERT( pxQueue );
|
|
800a612: 68fb ldr r3, [r7, #12]
|
|
800a614: 2b00 cmp r3, #0
|
|
800a616: d10b bne.n 800a630 <xQueueGenericReset+0x2c>
|
|
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800a618: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a61c: f383 8811 msr BASEPRI, r3
|
|
800a620: f3bf 8f6f isb sy
|
|
800a624: f3bf 8f4f dsb sy
|
|
800a628: 60bb str r3, [r7, #8]
|
|
" msr basepri, %0 \n" \
|
|
" isb \n" \
|
|
" dsb \n" \
|
|
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
}
|
|
800a62a: bf00 nop
|
|
800a62c: bf00 nop
|
|
800a62e: e7fd b.n 800a62c <xQueueGenericReset+0x28>
|
|
|
|
taskENTER_CRITICAL();
|
|
800a630: f001 fdc2 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800a634: 68fb ldr r3, [r7, #12]
|
|
800a636: 681a ldr r2, [r3, #0]
|
|
800a638: 68fb ldr r3, [r7, #12]
|
|
800a63a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800a63c: 68f9 ldr r1, [r7, #12]
|
|
800a63e: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
800a640: fb01 f303 mul.w r3, r1, r3
|
|
800a644: 441a add r2, r3
|
|
800a646: 68fb ldr r3, [r7, #12]
|
|
800a648: 609a str r2, [r3, #8]
|
|
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
|
|
800a64a: 68fb ldr r3, [r7, #12]
|
|
800a64c: 2200 movs r2, #0
|
|
800a64e: 639a str r2, [r3, #56] @ 0x38
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800a650: 68fb ldr r3, [r7, #12]
|
|
800a652: 681a ldr r2, [r3, #0]
|
|
800a654: 68fb ldr r3, [r7, #12]
|
|
800a656: 605a str r2, [r3, #4]
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800a658: 68fb ldr r3, [r7, #12]
|
|
800a65a: 681a ldr r2, [r3, #0]
|
|
800a65c: 68fb ldr r3, [r7, #12]
|
|
800a65e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800a660: 3b01 subs r3, #1
|
|
800a662: 68f9 ldr r1, [r7, #12]
|
|
800a664: 6c09 ldr r1, [r1, #64] @ 0x40
|
|
800a666: fb01 f303 mul.w r3, r1, r3
|
|
800a66a: 441a add r2, r3
|
|
800a66c: 68fb ldr r3, [r7, #12]
|
|
800a66e: 60da str r2, [r3, #12]
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800a670: 68fb ldr r3, [r7, #12]
|
|
800a672: 22ff movs r2, #255 @ 0xff
|
|
800a674: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800a678: 68fb ldr r3, [r7, #12]
|
|
800a67a: 22ff movs r2, #255 @ 0xff
|
|
800a67c: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
if( xNewQueue == pdFALSE )
|
|
800a680: 683b ldr r3, [r7, #0]
|
|
800a682: 2b00 cmp r3, #0
|
|
800a684: d114 bne.n 800a6b0 <xQueueGenericReset+0xac>
|
|
/* If there are tasks blocked waiting to read from the queue, then
|
|
the tasks will remain blocked as after this function exits the queue
|
|
will still be empty. If there are tasks blocked waiting to write to
|
|
the queue, then one should be unblocked as after this function exits
|
|
it will be possible to write to it. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800a686: 68fb ldr r3, [r7, #12]
|
|
800a688: 691b ldr r3, [r3, #16]
|
|
800a68a: 2b00 cmp r3, #0
|
|
800a68c: d01a beq.n 800a6c4 <xQueueGenericReset+0xc0>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800a68e: 68fb ldr r3, [r7, #12]
|
|
800a690: 3310 adds r3, #16
|
|
800a692: 4618 mov r0, r3
|
|
800a694: f001 f992 bl 800b9bc <xTaskRemoveFromEventList>
|
|
800a698: 4603 mov r3, r0
|
|
800a69a: 2b00 cmp r3, #0
|
|
800a69c: d012 beq.n 800a6c4 <xQueueGenericReset+0xc0>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800a69e: 4b0d ldr r3, [pc, #52] @ (800a6d4 <xQueueGenericReset+0xd0>)
|
|
800a6a0: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800a6a4: 601a str r2, [r3, #0]
|
|
800a6a6: f3bf 8f4f dsb sy
|
|
800a6aa: f3bf 8f6f isb sy
|
|
800a6ae: e009 b.n 800a6c4 <xQueueGenericReset+0xc0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Ensure the event queues start in the correct state. */
|
|
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
|
|
800a6b0: 68fb ldr r3, [r7, #12]
|
|
800a6b2: 3310 adds r3, #16
|
|
800a6b4: 4618 mov r0, r3
|
|
800a6b6: f7ff fef1 bl 800a49c <vListInitialise>
|
|
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
|
|
800a6ba: 68fb ldr r3, [r7, #12]
|
|
800a6bc: 3324 adds r3, #36 @ 0x24
|
|
800a6be: 4618 mov r0, r3
|
|
800a6c0: f7ff feec bl 800a49c <vListInitialise>
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800a6c4: f001 fdaa bl 800c21c <vPortExitCritical>
|
|
|
|
/* A value is returned for calling semantic consistency with previous
|
|
versions. */
|
|
return pdPASS;
|
|
800a6c8: 2301 movs r3, #1
|
|
}
|
|
800a6ca: 4618 mov r0, r3
|
|
800a6cc: 3710 adds r7, #16
|
|
800a6ce: 46bd mov sp, r7
|
|
800a6d0: bd80 pop {r7, pc}
|
|
800a6d2: bf00 nop
|
|
800a6d4: e000ed04 .word 0xe000ed04
|
|
|
|
0800a6d8 <xQueueGenericCreateStatic>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
|
|
{
|
|
800a6d8: b580 push {r7, lr}
|
|
800a6da: b08e sub sp, #56 @ 0x38
|
|
800a6dc: af02 add r7, sp, #8
|
|
800a6de: 60f8 str r0, [r7, #12]
|
|
800a6e0: 60b9 str r1, [r7, #8]
|
|
800a6e2: 607a str r2, [r7, #4]
|
|
800a6e4: 603b str r3, [r7, #0]
|
|
Queue_t *pxNewQueue;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800a6e6: 68fb ldr r3, [r7, #12]
|
|
800a6e8: 2b00 cmp r3, #0
|
|
800a6ea: d10b bne.n 800a704 <xQueueGenericCreateStatic+0x2c>
|
|
__asm volatile
|
|
800a6ec: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a6f0: f383 8811 msr BASEPRI, r3
|
|
800a6f4: f3bf 8f6f isb sy
|
|
800a6f8: f3bf 8f4f dsb sy
|
|
800a6fc: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800a6fe: bf00 nop
|
|
800a700: bf00 nop
|
|
800a702: e7fd b.n 800a700 <xQueueGenericCreateStatic+0x28>
|
|
|
|
/* The StaticQueue_t structure and the queue storage area must be
|
|
supplied. */
|
|
configASSERT( pxStaticQueue != NULL );
|
|
800a704: 683b ldr r3, [r7, #0]
|
|
800a706: 2b00 cmp r3, #0
|
|
800a708: d10b bne.n 800a722 <xQueueGenericCreateStatic+0x4a>
|
|
__asm volatile
|
|
800a70a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a70e: f383 8811 msr BASEPRI, r3
|
|
800a712: f3bf 8f6f isb sy
|
|
800a716: f3bf 8f4f dsb sy
|
|
800a71a: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800a71c: bf00 nop
|
|
800a71e: bf00 nop
|
|
800a720: e7fd b.n 800a71e <xQueueGenericCreateStatic+0x46>
|
|
|
|
/* A queue storage area should be provided if the item size is not 0, and
|
|
should not be provided if the item size is 0. */
|
|
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
|
|
800a722: 687b ldr r3, [r7, #4]
|
|
800a724: 2b00 cmp r3, #0
|
|
800a726: d002 beq.n 800a72e <xQueueGenericCreateStatic+0x56>
|
|
800a728: 68bb ldr r3, [r7, #8]
|
|
800a72a: 2b00 cmp r3, #0
|
|
800a72c: d001 beq.n 800a732 <xQueueGenericCreateStatic+0x5a>
|
|
800a72e: 2301 movs r3, #1
|
|
800a730: e000 b.n 800a734 <xQueueGenericCreateStatic+0x5c>
|
|
800a732: 2300 movs r3, #0
|
|
800a734: 2b00 cmp r3, #0
|
|
800a736: d10b bne.n 800a750 <xQueueGenericCreateStatic+0x78>
|
|
__asm volatile
|
|
800a738: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a73c: f383 8811 msr BASEPRI, r3
|
|
800a740: f3bf 8f6f isb sy
|
|
800a744: f3bf 8f4f dsb sy
|
|
800a748: 623b str r3, [r7, #32]
|
|
}
|
|
800a74a: bf00 nop
|
|
800a74c: bf00 nop
|
|
800a74e: e7fd b.n 800a74c <xQueueGenericCreateStatic+0x74>
|
|
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
|
|
800a750: 687b ldr r3, [r7, #4]
|
|
800a752: 2b00 cmp r3, #0
|
|
800a754: d102 bne.n 800a75c <xQueueGenericCreateStatic+0x84>
|
|
800a756: 68bb ldr r3, [r7, #8]
|
|
800a758: 2b00 cmp r3, #0
|
|
800a75a: d101 bne.n 800a760 <xQueueGenericCreateStatic+0x88>
|
|
800a75c: 2301 movs r3, #1
|
|
800a75e: e000 b.n 800a762 <xQueueGenericCreateStatic+0x8a>
|
|
800a760: 2300 movs r3, #0
|
|
800a762: 2b00 cmp r3, #0
|
|
800a764: d10b bne.n 800a77e <xQueueGenericCreateStatic+0xa6>
|
|
__asm volatile
|
|
800a766: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a76a: f383 8811 msr BASEPRI, r3
|
|
800a76e: f3bf 8f6f isb sy
|
|
800a772: f3bf 8f4f dsb sy
|
|
800a776: 61fb str r3, [r7, #28]
|
|
}
|
|
800a778: bf00 nop
|
|
800a77a: bf00 nop
|
|
800a77c: e7fd b.n 800a77a <xQueueGenericCreateStatic+0xa2>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
|
|
the real queue and semaphore structures. */
|
|
volatile size_t xSize = sizeof( StaticQueue_t );
|
|
800a77e: 2348 movs r3, #72 @ 0x48
|
|
800a780: 617b str r3, [r7, #20]
|
|
configASSERT( xSize == sizeof( Queue_t ) );
|
|
800a782: 697b ldr r3, [r7, #20]
|
|
800a784: 2b48 cmp r3, #72 @ 0x48
|
|
800a786: d00b beq.n 800a7a0 <xQueueGenericCreateStatic+0xc8>
|
|
__asm volatile
|
|
800a788: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a78c: f383 8811 msr BASEPRI, r3
|
|
800a790: f3bf 8f6f isb sy
|
|
800a794: f3bf 8f4f dsb sy
|
|
800a798: 61bb str r3, [r7, #24]
|
|
}
|
|
800a79a: bf00 nop
|
|
800a79c: bf00 nop
|
|
800a79e: e7fd b.n 800a79c <xQueueGenericCreateStatic+0xc4>
|
|
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
|
|
800a7a0: 697b ldr r3, [r7, #20]
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* The address of a statically allocated queue was passed in, use it.
|
|
The address of a statically allocated storage area was also passed in
|
|
but is already set. */
|
|
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800a7a2: 683b ldr r3, [r7, #0]
|
|
800a7a4: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
if( pxNewQueue != NULL )
|
|
800a7a6: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a7a8: 2b00 cmp r3, #0
|
|
800a7aa: d00d beq.n 800a7c8 <xQueueGenericCreateStatic+0xf0>
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be allocated wither statically or dynamically, so
|
|
note this queue was allocated statically in case the queue is
|
|
later deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdTRUE;
|
|
800a7ac: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a7ae: 2201 movs r2, #1
|
|
800a7b0: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800a7b4: f897 2038 ldrb.w r2, [r7, #56] @ 0x38
|
|
800a7b8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a7ba: 9300 str r3, [sp, #0]
|
|
800a7bc: 4613 mov r3, r2
|
|
800a7be: 687a ldr r2, [r7, #4]
|
|
800a7c0: 68b9 ldr r1, [r7, #8]
|
|
800a7c2: 68f8 ldr r0, [r7, #12]
|
|
800a7c4: f000 f840 bl 800a848 <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800a7c8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
}
|
|
800a7ca: 4618 mov r0, r3
|
|
800a7cc: 3730 adds r7, #48 @ 0x30
|
|
800a7ce: 46bd mov sp, r7
|
|
800a7d0: bd80 pop {r7, pc}
|
|
|
|
0800a7d2 <xQueueGenericCreate>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
|
|
|
QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
|
|
{
|
|
800a7d2: b580 push {r7, lr}
|
|
800a7d4: b08a sub sp, #40 @ 0x28
|
|
800a7d6: af02 add r7, sp, #8
|
|
800a7d8: 60f8 str r0, [r7, #12]
|
|
800a7da: 60b9 str r1, [r7, #8]
|
|
800a7dc: 4613 mov r3, r2
|
|
800a7de: 71fb strb r3, [r7, #7]
|
|
Queue_t *pxNewQueue;
|
|
size_t xQueueSizeInBytes;
|
|
uint8_t *pucQueueStorage;
|
|
|
|
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
|
|
800a7e0: 68fb ldr r3, [r7, #12]
|
|
800a7e2: 2b00 cmp r3, #0
|
|
800a7e4: d10b bne.n 800a7fe <xQueueGenericCreate+0x2c>
|
|
__asm volatile
|
|
800a7e6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a7ea: f383 8811 msr BASEPRI, r3
|
|
800a7ee: f3bf 8f6f isb sy
|
|
800a7f2: f3bf 8f4f dsb sy
|
|
800a7f6: 613b str r3, [r7, #16]
|
|
}
|
|
800a7f8: bf00 nop
|
|
800a7fa: bf00 nop
|
|
800a7fc: e7fd b.n 800a7fa <xQueueGenericCreate+0x28>
|
|
|
|
/* Allocate enough space to hold the maximum number of items that
|
|
can be in the queue at any time. It is valid for uxItemSize to be
|
|
zero in the case the queue is used as a semaphore. */
|
|
xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800a7fe: 68fb ldr r3, [r7, #12]
|
|
800a800: 68ba ldr r2, [r7, #8]
|
|
800a802: fb02 f303 mul.w r3, r2, r3
|
|
800a806: 61fb str r3, [r7, #28]
|
|
alignment requirements of the Queue_t structure - which in this case
|
|
is an int8_t *. Therefore, whenever the stack alignment requirements
|
|
are greater than or equal to the pointer to char requirements the cast
|
|
is safe. In other cases alignment requirements are not strict (one or
|
|
two bytes). */
|
|
pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
|
|
800a808: 69fb ldr r3, [r7, #28]
|
|
800a80a: 3348 adds r3, #72 @ 0x48
|
|
800a80c: 4618 mov r0, r3
|
|
800a80e: f001 fdf5 bl 800c3fc <pvPortMalloc>
|
|
800a812: 61b8 str r0, [r7, #24]
|
|
|
|
if( pxNewQueue != NULL )
|
|
800a814: 69bb ldr r3, [r7, #24]
|
|
800a816: 2b00 cmp r3, #0
|
|
800a818: d011 beq.n 800a83e <xQueueGenericCreate+0x6c>
|
|
{
|
|
/* Jump past the queue structure to find the location of the queue
|
|
storage area. */
|
|
pucQueueStorage = ( uint8_t * ) pxNewQueue;
|
|
800a81a: 69bb ldr r3, [r7, #24]
|
|
800a81c: 617b str r3, [r7, #20]
|
|
pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
|
|
800a81e: 697b ldr r3, [r7, #20]
|
|
800a820: 3348 adds r3, #72 @ 0x48
|
|
800a822: 617b str r3, [r7, #20]
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
/* Queues can be created either statically or dynamically, so
|
|
note this task was created dynamically in case it is later
|
|
deleted. */
|
|
pxNewQueue->ucStaticallyAllocated = pdFALSE;
|
|
800a824: 69bb ldr r3, [r7, #24]
|
|
800a826: 2200 movs r2, #0
|
|
800a828: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
}
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
|
|
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
|
|
800a82c: 79fa ldrb r2, [r7, #7]
|
|
800a82e: 69bb ldr r3, [r7, #24]
|
|
800a830: 9300 str r3, [sp, #0]
|
|
800a832: 4613 mov r3, r2
|
|
800a834: 697a ldr r2, [r7, #20]
|
|
800a836: 68b9 ldr r1, [r7, #8]
|
|
800a838: 68f8 ldr r0, [r7, #12]
|
|
800a83a: f000 f805 bl 800a848 <prvInitialiseNewQueue>
|
|
{
|
|
traceQUEUE_CREATE_FAILED( ucQueueType );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return pxNewQueue;
|
|
800a83e: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800a840: 4618 mov r0, r3
|
|
800a842: 3720 adds r7, #32
|
|
800a844: 46bd mov sp, r7
|
|
800a846: bd80 pop {r7, pc}
|
|
|
|
0800a848 <prvInitialiseNewQueue>:
|
|
|
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
|
|
{
|
|
800a848: b580 push {r7, lr}
|
|
800a84a: b084 sub sp, #16
|
|
800a84c: af00 add r7, sp, #0
|
|
800a84e: 60f8 str r0, [r7, #12]
|
|
800a850: 60b9 str r1, [r7, #8]
|
|
800a852: 607a str r2, [r7, #4]
|
|
800a854: 70fb strb r3, [r7, #3]
|
|
/* Remove compiler warnings about unused parameters should
|
|
configUSE_TRACE_FACILITY not be set to 1. */
|
|
( void ) ucQueueType;
|
|
|
|
if( uxItemSize == ( UBaseType_t ) 0 )
|
|
800a856: 68bb ldr r3, [r7, #8]
|
|
800a858: 2b00 cmp r3, #0
|
|
800a85a: d103 bne.n 800a864 <prvInitialiseNewQueue+0x1c>
|
|
{
|
|
/* No RAM was allocated for the queue storage area, but PC head cannot
|
|
be set to NULL because NULL is used as a key to say the queue is used as
|
|
a mutex. Therefore just set pcHead to point to the queue as a benign
|
|
value that is known to be within the memory map. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
|
|
800a85c: 69bb ldr r3, [r7, #24]
|
|
800a85e: 69ba ldr r2, [r7, #24]
|
|
800a860: 601a str r2, [r3, #0]
|
|
800a862: e002 b.n 800a86a <prvInitialiseNewQueue+0x22>
|
|
}
|
|
else
|
|
{
|
|
/* Set the head to the start of the queue storage area. */
|
|
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
|
|
800a864: 69bb ldr r3, [r7, #24]
|
|
800a866: 687a ldr r2, [r7, #4]
|
|
800a868: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Initialise the queue members as described where the queue type is
|
|
defined. */
|
|
pxNewQueue->uxLength = uxQueueLength;
|
|
800a86a: 69bb ldr r3, [r7, #24]
|
|
800a86c: 68fa ldr r2, [r7, #12]
|
|
800a86e: 63da str r2, [r3, #60] @ 0x3c
|
|
pxNewQueue->uxItemSize = uxItemSize;
|
|
800a870: 69bb ldr r3, [r7, #24]
|
|
800a872: 68ba ldr r2, [r7, #8]
|
|
800a874: 641a str r2, [r3, #64] @ 0x40
|
|
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
|
|
800a876: 2101 movs r1, #1
|
|
800a878: 69b8 ldr r0, [r7, #24]
|
|
800a87a: f7ff fec3 bl 800a604 <xQueueGenericReset>
|
|
pxNewQueue->pxQueueSetContainer = NULL;
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
traceQUEUE_CREATE( pxNewQueue );
|
|
}
|
|
800a87e: bf00 nop
|
|
800a880: 3710 adds r7, #16
|
|
800a882: 46bd mov sp, r7
|
|
800a884: bd80 pop {r7, pc}
|
|
...
|
|
|
|
0800a888 <xQueueGenericSend>:
|
|
|
|
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
|
|
{
|
|
800a888: b580 push {r7, lr}
|
|
800a88a: b08e sub sp, #56 @ 0x38
|
|
800a88c: af00 add r7, sp, #0
|
|
800a88e: 60f8 str r0, [r7, #12]
|
|
800a890: 60b9 str r1, [r7, #8]
|
|
800a892: 607a str r2, [r7, #4]
|
|
800a894: 603b str r3, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
|
800a896: 2300 movs r3, #0
|
|
800a898: 637b str r3, [r7, #52] @ 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800a89a: 68fb ldr r3, [r7, #12]
|
|
800a89c: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800a89e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a8a0: 2b00 cmp r3, #0
|
|
800a8a2: d10b bne.n 800a8bc <xQueueGenericSend+0x34>
|
|
__asm volatile
|
|
800a8a4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a8a8: f383 8811 msr BASEPRI, r3
|
|
800a8ac: f3bf 8f6f isb sy
|
|
800a8b0: f3bf 8f4f dsb sy
|
|
800a8b4: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800a8b6: bf00 nop
|
|
800a8b8: bf00 nop
|
|
800a8ba: e7fd b.n 800a8b8 <xQueueGenericSend+0x30>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800a8bc: 68bb ldr r3, [r7, #8]
|
|
800a8be: 2b00 cmp r3, #0
|
|
800a8c0: d103 bne.n 800a8ca <xQueueGenericSend+0x42>
|
|
800a8c2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a8c4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800a8c6: 2b00 cmp r3, #0
|
|
800a8c8: d101 bne.n 800a8ce <xQueueGenericSend+0x46>
|
|
800a8ca: 2301 movs r3, #1
|
|
800a8cc: e000 b.n 800a8d0 <xQueueGenericSend+0x48>
|
|
800a8ce: 2300 movs r3, #0
|
|
800a8d0: 2b00 cmp r3, #0
|
|
800a8d2: d10b bne.n 800a8ec <xQueueGenericSend+0x64>
|
|
__asm volatile
|
|
800a8d4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a8d8: f383 8811 msr BASEPRI, r3
|
|
800a8dc: f3bf 8f6f isb sy
|
|
800a8e0: f3bf 8f4f dsb sy
|
|
800a8e4: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800a8e6: bf00 nop
|
|
800a8e8: bf00 nop
|
|
800a8ea: e7fd b.n 800a8e8 <xQueueGenericSend+0x60>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800a8ec: 683b ldr r3, [r7, #0]
|
|
800a8ee: 2b02 cmp r3, #2
|
|
800a8f0: d103 bne.n 800a8fa <xQueueGenericSend+0x72>
|
|
800a8f2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a8f4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800a8f6: 2b01 cmp r3, #1
|
|
800a8f8: d101 bne.n 800a8fe <xQueueGenericSend+0x76>
|
|
800a8fa: 2301 movs r3, #1
|
|
800a8fc: e000 b.n 800a900 <xQueueGenericSend+0x78>
|
|
800a8fe: 2300 movs r3, #0
|
|
800a900: 2b00 cmp r3, #0
|
|
800a902: d10b bne.n 800a91c <xQueueGenericSend+0x94>
|
|
__asm volatile
|
|
800a904: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a908: f383 8811 msr BASEPRI, r3
|
|
800a90c: f3bf 8f6f isb sy
|
|
800a910: f3bf 8f4f dsb sy
|
|
800a914: 623b str r3, [r7, #32]
|
|
}
|
|
800a916: bf00 nop
|
|
800a918: bf00 nop
|
|
800a91a: e7fd b.n 800a918 <xQueueGenericSend+0x90>
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800a91c: f001 fa10 bl 800bd40 <xTaskGetSchedulerState>
|
|
800a920: 4603 mov r3, r0
|
|
800a922: 2b00 cmp r3, #0
|
|
800a924: d102 bne.n 800a92c <xQueueGenericSend+0xa4>
|
|
800a926: 687b ldr r3, [r7, #4]
|
|
800a928: 2b00 cmp r3, #0
|
|
800a92a: d101 bne.n 800a930 <xQueueGenericSend+0xa8>
|
|
800a92c: 2301 movs r3, #1
|
|
800a92e: e000 b.n 800a932 <xQueueGenericSend+0xaa>
|
|
800a930: 2300 movs r3, #0
|
|
800a932: 2b00 cmp r3, #0
|
|
800a934: d10b bne.n 800a94e <xQueueGenericSend+0xc6>
|
|
__asm volatile
|
|
800a936: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800a93a: f383 8811 msr BASEPRI, r3
|
|
800a93e: f3bf 8f6f isb sy
|
|
800a942: f3bf 8f4f dsb sy
|
|
800a946: 61fb str r3, [r7, #28]
|
|
}
|
|
800a948: bf00 nop
|
|
800a94a: bf00 nop
|
|
800a94c: e7fd b.n 800a94a <xQueueGenericSend+0xc2>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800a94e: f001 fc33 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
/* Is there room on the queue now? The running task must be the
|
|
highest priority task wanting to access the queue. If the head item
|
|
in the queue is to be overwritten then it does not matter if the
|
|
queue is full. */
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800a952: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a954: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800a956: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a958: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800a95a: 429a cmp r2, r3
|
|
800a95c: d302 bcc.n 800a964 <xQueueGenericSend+0xdc>
|
|
800a95e: 683b ldr r3, [r7, #0]
|
|
800a960: 2b02 cmp r3, #2
|
|
800a962: d129 bne.n 800a9b8 <xQueueGenericSend+0x130>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800a964: 683a ldr r2, [r7, #0]
|
|
800a966: 68b9 ldr r1, [r7, #8]
|
|
800a968: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800a96a: f000 facf bl 800af0c <prvCopyDataToQueue>
|
|
800a96e: 62f8 str r0, [r7, #44] @ 0x2c
|
|
|
|
/* If there was a task waiting for data to arrive on the
|
|
queue then unblock it now. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800a970: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a972: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800a974: 2b00 cmp r3, #0
|
|
800a976: d010 beq.n 800a99a <xQueueGenericSend+0x112>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800a978: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a97a: 3324 adds r3, #36 @ 0x24
|
|
800a97c: 4618 mov r0, r3
|
|
800a97e: f001 f81d bl 800b9bc <xTaskRemoveFromEventList>
|
|
800a982: 4603 mov r3, r0
|
|
800a984: 2b00 cmp r3, #0
|
|
800a986: d013 beq.n 800a9b0 <xQueueGenericSend+0x128>
|
|
{
|
|
/* The unblocked task has a priority higher than
|
|
our own so yield immediately. Yes it is ok to do
|
|
this from within the critical section - the kernel
|
|
takes care of that. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800a988: 4b3f ldr r3, [pc, #252] @ (800aa88 <xQueueGenericSend+0x200>)
|
|
800a98a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800a98e: 601a str r2, [r3, #0]
|
|
800a990: f3bf 8f4f dsb sy
|
|
800a994: f3bf 8f6f isb sy
|
|
800a998: e00a b.n 800a9b0 <xQueueGenericSend+0x128>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else if( xYieldRequired != pdFALSE )
|
|
800a99a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800a99c: 2b00 cmp r3, #0
|
|
800a99e: d007 beq.n 800a9b0 <xQueueGenericSend+0x128>
|
|
{
|
|
/* This path is a special case that will only get
|
|
executed if the task was holding multiple mutexes and
|
|
the mutexes were given back in an order that is
|
|
different to that in which they were taken. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800a9a0: 4b39 ldr r3, [pc, #228] @ (800aa88 <xQueueGenericSend+0x200>)
|
|
800a9a2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800a9a6: 601a str r2, [r3, #0]
|
|
800a9a8: f3bf 8f4f dsb sy
|
|
800a9ac: f3bf 8f6f isb sy
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
taskEXIT_CRITICAL();
|
|
800a9b0: f001 fc34 bl 800c21c <vPortExitCritical>
|
|
return pdPASS;
|
|
800a9b4: 2301 movs r3, #1
|
|
800a9b6: e063 b.n 800aa80 <xQueueGenericSend+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800a9b8: 687b ldr r3, [r7, #4]
|
|
800a9ba: 2b00 cmp r3, #0
|
|
800a9bc: d103 bne.n 800a9c6 <xQueueGenericSend+0x13e>
|
|
{
|
|
/* The queue was full and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800a9be: f001 fc2d bl 800c21c <vPortExitCritical>
|
|
|
|
/* Return to the original privilege level before exiting
|
|
the function. */
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800a9c2: 2300 movs r3, #0
|
|
800a9c4: e05c b.n 800aa80 <xQueueGenericSend+0x1f8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800a9c6: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800a9c8: 2b00 cmp r3, #0
|
|
800a9ca: d106 bne.n 800a9da <xQueueGenericSend+0x152>
|
|
{
|
|
/* The queue was full and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800a9cc: f107 0314 add.w r3, r7, #20
|
|
800a9d0: 4618 mov r0, r3
|
|
800a9d2: f001 f857 bl 800ba84 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800a9d6: 2301 movs r3, #1
|
|
800a9d8: 637b str r3, [r7, #52] @ 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800a9da: f001 fc1f bl 800c21c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800a9de: f000 fddf bl 800b5a0 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800a9e2: f001 fbe9 bl 800c1b8 <vPortEnterCritical>
|
|
800a9e6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a9e8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800a9ec: b25b sxtb r3, r3
|
|
800a9ee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800a9f2: d103 bne.n 800a9fc <xQueueGenericSend+0x174>
|
|
800a9f4: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a9f6: 2200 movs r2, #0
|
|
800a9f8: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800a9fc: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800a9fe: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800aa02: b25b sxtb r3, r3
|
|
800aa04: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800aa08: d103 bne.n 800aa12 <xQueueGenericSend+0x18a>
|
|
800aa0a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800aa0c: 2200 movs r2, #0
|
|
800aa0e: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800aa12: f001 fc03 bl 800c21c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800aa16: 1d3a adds r2, r7, #4
|
|
800aa18: f107 0314 add.w r3, r7, #20
|
|
800aa1c: 4611 mov r1, r2
|
|
800aa1e: 4618 mov r0, r3
|
|
800aa20: f001 f846 bl 800bab0 <xTaskCheckForTimeOut>
|
|
800aa24: 4603 mov r3, r0
|
|
800aa26: 2b00 cmp r3, #0
|
|
800aa28: d124 bne.n 800aa74 <xQueueGenericSend+0x1ec>
|
|
{
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
|
800aa2a: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800aa2c: f000 fb66 bl 800b0fc <prvIsQueueFull>
|
|
800aa30: 4603 mov r3, r0
|
|
800aa32: 2b00 cmp r3, #0
|
|
800aa34: d018 beq.n 800aa68 <xQueueGenericSend+0x1e0>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
|
800aa36: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800aa38: 3310 adds r3, #16
|
|
800aa3a: 687a ldr r2, [r7, #4]
|
|
800aa3c: 4611 mov r1, r2
|
|
800aa3e: 4618 mov r0, r3
|
|
800aa40: f000 ff96 bl 800b970 <vTaskPlaceOnEventList>
|
|
/* Unlocking the queue means queue events can effect the
|
|
event list. It is possible that interrupts occurring now
|
|
remove this task from the event list again - but as the
|
|
scheduler is suspended the task will go onto the pending
|
|
ready last instead of the actual ready list. */
|
|
prvUnlockQueue( pxQueue );
|
|
800aa44: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800aa46: f000 faf1 bl 800b02c <prvUnlockQueue>
|
|
/* Resuming the scheduler will move tasks from the pending
|
|
ready list into the ready list - so it is feasible that this
|
|
task is already in a ready list before it yields - in which
|
|
case the yield will not cause a context switch unless there
|
|
is also a higher priority task in the pending ready list. */
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800aa4a: f000 fdb7 bl 800b5bc <xTaskResumeAll>
|
|
800aa4e: 4603 mov r3, r0
|
|
800aa50: 2b00 cmp r3, #0
|
|
800aa52: f47f af7c bne.w 800a94e <xQueueGenericSend+0xc6>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800aa56: 4b0c ldr r3, [pc, #48] @ (800aa88 <xQueueGenericSend+0x200>)
|
|
800aa58: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800aa5c: 601a str r2, [r3, #0]
|
|
800aa5e: f3bf 8f4f dsb sy
|
|
800aa62: f3bf 8f6f isb sy
|
|
800aa66: e772 b.n 800a94e <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Try again. */
|
|
prvUnlockQueue( pxQueue );
|
|
800aa68: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800aa6a: f000 fadf bl 800b02c <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800aa6e: f000 fda5 bl 800b5bc <xTaskResumeAll>
|
|
800aa72: e76c b.n 800a94e <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The timeout has expired. */
|
|
prvUnlockQueue( pxQueue );
|
|
800aa74: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800aa76: f000 fad9 bl 800b02c <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800aa7a: f000 fd9f bl 800b5bc <xTaskResumeAll>
|
|
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
800aa7e: 2300 movs r3, #0
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800aa80: 4618 mov r0, r3
|
|
800aa82: 3738 adds r7, #56 @ 0x38
|
|
800aa84: 46bd mov sp, r7
|
|
800aa86: bd80 pop {r7, pc}
|
|
800aa88: e000ed04 .word 0xe000ed04
|
|
|
|
0800aa8c <xQueueGenericSendFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
|
|
{
|
|
800aa8c: b580 push {r7, lr}
|
|
800aa8e: b090 sub sp, #64 @ 0x40
|
|
800aa90: af00 add r7, sp, #0
|
|
800aa92: 60f8 str r0, [r7, #12]
|
|
800aa94: 60b9 str r1, [r7, #8]
|
|
800aa96: 607a str r2, [r7, #4]
|
|
800aa98: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800aa9a: 68fb ldr r3, [r7, #12]
|
|
800aa9c: 63bb str r3, [r7, #56] @ 0x38
|
|
|
|
configASSERT( pxQueue );
|
|
800aa9e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800aaa0: 2b00 cmp r3, #0
|
|
800aaa2: d10b bne.n 800aabc <xQueueGenericSendFromISR+0x30>
|
|
__asm volatile
|
|
800aaa4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800aaa8: f383 8811 msr BASEPRI, r3
|
|
800aaac: f3bf 8f6f isb sy
|
|
800aab0: f3bf 8f4f dsb sy
|
|
800aab4: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
800aab6: bf00 nop
|
|
800aab8: bf00 nop
|
|
800aaba: e7fd b.n 800aab8 <xQueueGenericSendFromISR+0x2c>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800aabc: 68bb ldr r3, [r7, #8]
|
|
800aabe: 2b00 cmp r3, #0
|
|
800aac0: d103 bne.n 800aaca <xQueueGenericSendFromISR+0x3e>
|
|
800aac2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800aac4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800aac6: 2b00 cmp r3, #0
|
|
800aac8: d101 bne.n 800aace <xQueueGenericSendFromISR+0x42>
|
|
800aaca: 2301 movs r3, #1
|
|
800aacc: e000 b.n 800aad0 <xQueueGenericSendFromISR+0x44>
|
|
800aace: 2300 movs r3, #0
|
|
800aad0: 2b00 cmp r3, #0
|
|
800aad2: d10b bne.n 800aaec <xQueueGenericSendFromISR+0x60>
|
|
__asm volatile
|
|
800aad4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800aad8: f383 8811 msr BASEPRI, r3
|
|
800aadc: f3bf 8f6f isb sy
|
|
800aae0: f3bf 8f4f dsb sy
|
|
800aae4: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
800aae6: bf00 nop
|
|
800aae8: bf00 nop
|
|
800aaea: e7fd b.n 800aae8 <xQueueGenericSendFromISR+0x5c>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
800aaec: 683b ldr r3, [r7, #0]
|
|
800aaee: 2b02 cmp r3, #2
|
|
800aaf0: d103 bne.n 800aafa <xQueueGenericSendFromISR+0x6e>
|
|
800aaf2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800aaf4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800aaf6: 2b01 cmp r3, #1
|
|
800aaf8: d101 bne.n 800aafe <xQueueGenericSendFromISR+0x72>
|
|
800aafa: 2301 movs r3, #1
|
|
800aafc: e000 b.n 800ab00 <xQueueGenericSendFromISR+0x74>
|
|
800aafe: 2300 movs r3, #0
|
|
800ab00: 2b00 cmp r3, #0
|
|
800ab02: d10b bne.n 800ab1c <xQueueGenericSendFromISR+0x90>
|
|
__asm volatile
|
|
800ab04: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ab08: f383 8811 msr BASEPRI, r3
|
|
800ab0c: f3bf 8f6f isb sy
|
|
800ab10: f3bf 8f4f dsb sy
|
|
800ab14: 623b str r3, [r7, #32]
|
|
}
|
|
800ab16: bf00 nop
|
|
800ab18: bf00 nop
|
|
800ab1a: e7fd b.n 800ab18 <xQueueGenericSendFromISR+0x8c>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800ab1c: f001 fc2c bl 800c378 <vPortValidateInterruptPriority>
|
|
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
800ab20: f3ef 8211 mrs r2, BASEPRI
|
|
800ab24: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ab28: f383 8811 msr BASEPRI, r3
|
|
800ab2c: f3bf 8f6f isb sy
|
|
800ab30: f3bf 8f4f dsb sy
|
|
800ab34: 61fa str r2, [r7, #28]
|
|
800ab36: 61bb str r3, [r7, #24]
|
|
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
|
|
/* This return will not be reached but is necessary to prevent compiler
|
|
warnings. */
|
|
return ulOriginalBASEPRI;
|
|
800ab38: 69fb ldr r3, [r7, #28]
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
|
in the queue. Also don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800ab3a: 637b str r3, [r7, #52] @ 0x34
|
|
{
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
800ab3c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab3e: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800ab40: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab42: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800ab44: 429a cmp r2, r3
|
|
800ab46: d302 bcc.n 800ab4e <xQueueGenericSendFromISR+0xc2>
|
|
800ab48: 683b ldr r3, [r7, #0]
|
|
800ab4a: 2b02 cmp r3, #2
|
|
800ab4c: d12f bne.n 800abae <xQueueGenericSendFromISR+0x122>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
800ab4e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab50: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800ab54: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800ab58: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab5a: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800ab5c: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
|
semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
|
in a task disinheriting a priority and prvCopyDataToQueue() can be
|
|
called here even though the disinherit function does not check if
|
|
the scheduler is suspended before accessing the ready lists. */
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
800ab5e: 683a ldr r2, [r7, #0]
|
|
800ab60: 68b9 ldr r1, [r7, #8]
|
|
800ab62: 6bb8 ldr r0, [r7, #56] @ 0x38
|
|
800ab64: f000 f9d2 bl 800af0c <prvCopyDataToQueue>
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
800ab68: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33
|
|
800ab6c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ab70: d112 bne.n 800ab98 <xQueueGenericSendFromISR+0x10c>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800ab72: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab74: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800ab76: 2b00 cmp r3, #0
|
|
800ab78: d016 beq.n 800aba8 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800ab7a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800ab7c: 3324 adds r3, #36 @ 0x24
|
|
800ab7e: 4618 mov r0, r3
|
|
800ab80: f000 ff1c bl 800b9bc <xTaskRemoveFromEventList>
|
|
800ab84: 4603 mov r3, r0
|
|
800ab86: 2b00 cmp r3, #0
|
|
800ab88: d00e beq.n 800aba8 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800ab8a: 687b ldr r3, [r7, #4]
|
|
800ab8c: 2b00 cmp r3, #0
|
|
800ab8e: d00b beq.n 800aba8 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800ab90: 687b ldr r3, [r7, #4]
|
|
800ab92: 2201 movs r2, #1
|
|
800ab94: 601a str r2, [r3, #0]
|
|
800ab96: e007 b.n 800aba8 <xQueueGenericSendFromISR+0x11c>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
800ab98: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
800ab9c: 3301 adds r3, #1
|
|
800ab9e: b2db uxtb r3, r3
|
|
800aba0: b25a sxtb r2, r3
|
|
800aba2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800aba4: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800aba8: 2301 movs r3, #1
|
|
800abaa: 63fb str r3, [r7, #60] @ 0x3c
|
|
{
|
|
800abac: e001 b.n 800abb2 <xQueueGenericSendFromISR+0x126>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800abae: 2300 movs r3, #0
|
|
800abb0: 63fb str r3, [r7, #60] @ 0x3c
|
|
800abb2: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800abb4: 617b str r3, [r7, #20]
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
{
|
|
__asm volatile
|
|
800abb6: 697b ldr r3, [r7, #20]
|
|
800abb8: f383 8811 msr BASEPRI, r3
|
|
(
|
|
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
|
|
);
|
|
}
|
|
800abbc: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800abbe: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
}
|
|
800abc0: 4618 mov r0, r3
|
|
800abc2: 3740 adds r7, #64 @ 0x40
|
|
800abc4: 46bd mov sp, r7
|
|
800abc6: bd80 pop {r7, pc}
|
|
|
|
0800abc8 <xQueueReceive>:
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
|
|
{
|
|
800abc8: b580 push {r7, lr}
|
|
800abca: b08c sub sp, #48 @ 0x30
|
|
800abcc: af00 add r7, sp, #0
|
|
800abce: 60f8 str r0, [r7, #12]
|
|
800abd0: 60b9 str r1, [r7, #8]
|
|
800abd2: 607a str r2, [r7, #4]
|
|
BaseType_t xEntryTimeSet = pdFALSE;
|
|
800abd4: 2300 movs r3, #0
|
|
800abd6: 62fb str r3, [r7, #44] @ 0x2c
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800abd8: 68fb ldr r3, [r7, #12]
|
|
800abda: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Check the pointer is not NULL. */
|
|
configASSERT( ( pxQueue ) );
|
|
800abdc: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800abde: 2b00 cmp r3, #0
|
|
800abe0: d10b bne.n 800abfa <xQueueReceive+0x32>
|
|
__asm volatile
|
|
800abe2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800abe6: f383 8811 msr BASEPRI, r3
|
|
800abea: f3bf 8f6f isb sy
|
|
800abee: f3bf 8f4f dsb sy
|
|
800abf2: 623b str r3, [r7, #32]
|
|
}
|
|
800abf4: bf00 nop
|
|
800abf6: bf00 nop
|
|
800abf8: e7fd b.n 800abf6 <xQueueReceive+0x2e>
|
|
|
|
/* The buffer into which data is received can only be NULL if the data size
|
|
is zero (so no data is copied into the buffer. */
|
|
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800abfa: 68bb ldr r3, [r7, #8]
|
|
800abfc: 2b00 cmp r3, #0
|
|
800abfe: d103 bne.n 800ac08 <xQueueReceive+0x40>
|
|
800ac00: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac02: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800ac04: 2b00 cmp r3, #0
|
|
800ac06: d101 bne.n 800ac0c <xQueueReceive+0x44>
|
|
800ac08: 2301 movs r3, #1
|
|
800ac0a: e000 b.n 800ac0e <xQueueReceive+0x46>
|
|
800ac0c: 2300 movs r3, #0
|
|
800ac0e: 2b00 cmp r3, #0
|
|
800ac10: d10b bne.n 800ac2a <xQueueReceive+0x62>
|
|
__asm volatile
|
|
800ac12: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ac16: f383 8811 msr BASEPRI, r3
|
|
800ac1a: f3bf 8f6f isb sy
|
|
800ac1e: f3bf 8f4f dsb sy
|
|
800ac22: 61fb str r3, [r7, #28]
|
|
}
|
|
800ac24: bf00 nop
|
|
800ac26: bf00 nop
|
|
800ac28: e7fd b.n 800ac26 <xQueueReceive+0x5e>
|
|
|
|
/* Cannot block if the scheduler is suspended. */
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
800ac2a: f001 f889 bl 800bd40 <xTaskGetSchedulerState>
|
|
800ac2e: 4603 mov r3, r0
|
|
800ac30: 2b00 cmp r3, #0
|
|
800ac32: d102 bne.n 800ac3a <xQueueReceive+0x72>
|
|
800ac34: 687b ldr r3, [r7, #4]
|
|
800ac36: 2b00 cmp r3, #0
|
|
800ac38: d101 bne.n 800ac3e <xQueueReceive+0x76>
|
|
800ac3a: 2301 movs r3, #1
|
|
800ac3c: e000 b.n 800ac40 <xQueueReceive+0x78>
|
|
800ac3e: 2300 movs r3, #0
|
|
800ac40: 2b00 cmp r3, #0
|
|
800ac42: d10b bne.n 800ac5c <xQueueReceive+0x94>
|
|
__asm volatile
|
|
800ac44: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ac48: f383 8811 msr BASEPRI, r3
|
|
800ac4c: f3bf 8f6f isb sy
|
|
800ac50: f3bf 8f4f dsb sy
|
|
800ac54: 61bb str r3, [r7, #24]
|
|
}
|
|
800ac56: bf00 nop
|
|
800ac58: bf00 nop
|
|
800ac5a: e7fd b.n 800ac58 <xQueueReceive+0x90>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800ac5c: f001 faac bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800ac60: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac62: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800ac64: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
/* Is there data in the queue now? To be running the calling task
|
|
must be the highest priority task wanting to access the queue. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800ac66: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ac68: 2b00 cmp r3, #0
|
|
800ac6a: d01f beq.n 800acac <xQueueReceive+0xe4>
|
|
{
|
|
/* Data available, remove one item. */
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
800ac6c: 68b9 ldr r1, [r7, #8]
|
|
800ac6e: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ac70: f000 f9b6 bl 800afe0 <prvCopyDataFromQueue>
|
|
traceQUEUE_RECEIVE( pxQueue );
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
800ac74: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800ac76: 1e5a subs r2, r3, #1
|
|
800ac78: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac7a: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* There is now space in the queue, were any tasks waiting to
|
|
post to the queue? If so, unblock the highest priority waiting
|
|
task. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800ac7c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac7e: 691b ldr r3, [r3, #16]
|
|
800ac80: 2b00 cmp r3, #0
|
|
800ac82: d00f beq.n 800aca4 <xQueueReceive+0xdc>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800ac84: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ac86: 3310 adds r3, #16
|
|
800ac88: 4618 mov r0, r3
|
|
800ac8a: f000 fe97 bl 800b9bc <xTaskRemoveFromEventList>
|
|
800ac8e: 4603 mov r3, r0
|
|
800ac90: 2b00 cmp r3, #0
|
|
800ac92: d007 beq.n 800aca4 <xQueueReceive+0xdc>
|
|
{
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
800ac94: 4b3c ldr r3, [pc, #240] @ (800ad88 <xQueueReceive+0x1c0>)
|
|
800ac96: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800ac9a: 601a str r2, [r3, #0]
|
|
800ac9c: f3bf 8f4f dsb sy
|
|
800aca0: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
taskEXIT_CRITICAL();
|
|
800aca4: f001 faba bl 800c21c <vPortExitCritical>
|
|
return pdPASS;
|
|
800aca8: 2301 movs r3, #1
|
|
800acaa: e069 b.n 800ad80 <xQueueReceive+0x1b8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
800acac: 687b ldr r3, [r7, #4]
|
|
800acae: 2b00 cmp r3, #0
|
|
800acb0: d103 bne.n 800acba <xQueueReceive+0xf2>
|
|
{
|
|
/* The queue was empty and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
800acb2: f001 fab3 bl 800c21c <vPortExitCritical>
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800acb6: 2300 movs r3, #0
|
|
800acb8: e062 b.n 800ad80 <xQueueReceive+0x1b8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
800acba: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800acbc: 2b00 cmp r3, #0
|
|
800acbe: d106 bne.n 800acce <xQueueReceive+0x106>
|
|
{
|
|
/* The queue was empty and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
800acc0: f107 0310 add.w r3, r7, #16
|
|
800acc4: 4618 mov r0, r3
|
|
800acc6: f000 fedd bl 800ba84 <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
800acca: 2301 movs r3, #1
|
|
800accc: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800acce: f001 faa5 bl 800c21c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
800acd2: f000 fc65 bl 800b5a0 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
800acd6: f001 fa6f bl 800c1b8 <vPortEnterCritical>
|
|
800acda: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acdc: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800ace0: b25b sxtb r3, r3
|
|
800ace2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ace6: d103 bne.n 800acf0 <xQueueReceive+0x128>
|
|
800ace8: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acea: 2200 movs r2, #0
|
|
800acec: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
800acf0: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800acf2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800acf6: b25b sxtb r3, r3
|
|
800acf8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800acfc: d103 bne.n 800ad06 <xQueueReceive+0x13e>
|
|
800acfe: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ad00: 2200 movs r2, #0
|
|
800ad02: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
800ad06: f001 fa89 bl 800c21c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
800ad0a: 1d3a adds r2, r7, #4
|
|
800ad0c: f107 0310 add.w r3, r7, #16
|
|
800ad10: 4611 mov r1, r2
|
|
800ad12: 4618 mov r0, r3
|
|
800ad14: f000 fecc bl 800bab0 <xTaskCheckForTimeOut>
|
|
800ad18: 4603 mov r3, r0
|
|
800ad1a: 2b00 cmp r3, #0
|
|
800ad1c: d123 bne.n 800ad66 <xQueueReceive+0x19e>
|
|
{
|
|
/* The timeout has not expired. If the queue is still empty place
|
|
the task on the list of tasks waiting to receive from the queue. */
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800ad1e: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ad20: f000 f9d6 bl 800b0d0 <prvIsQueueEmpty>
|
|
800ad24: 4603 mov r3, r0
|
|
800ad26: 2b00 cmp r3, #0
|
|
800ad28: d017 beq.n 800ad5a <xQueueReceive+0x192>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
|
|
800ad2a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ad2c: 3324 adds r3, #36 @ 0x24
|
|
800ad2e: 687a ldr r2, [r7, #4]
|
|
800ad30: 4611 mov r1, r2
|
|
800ad32: 4618 mov r0, r3
|
|
800ad34: f000 fe1c bl 800b970 <vTaskPlaceOnEventList>
|
|
prvUnlockQueue( pxQueue );
|
|
800ad38: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ad3a: f000 f977 bl 800b02c <prvUnlockQueue>
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
800ad3e: f000 fc3d bl 800b5bc <xTaskResumeAll>
|
|
800ad42: 4603 mov r3, r0
|
|
800ad44: 2b00 cmp r3, #0
|
|
800ad46: d189 bne.n 800ac5c <xQueueReceive+0x94>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800ad48: 4b0f ldr r3, [pc, #60] @ (800ad88 <xQueueReceive+0x1c0>)
|
|
800ad4a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800ad4e: 601a str r2, [r3, #0]
|
|
800ad50: f3bf 8f4f dsb sy
|
|
800ad54: f3bf 8f6f isb sy
|
|
800ad58: e780 b.n 800ac5c <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* The queue contains data again. Loop back to try and read the
|
|
data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800ad5a: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ad5c: f000 f966 bl 800b02c <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800ad60: f000 fc2c bl 800b5bc <xTaskResumeAll>
|
|
800ad64: e77a b.n 800ac5c <xQueueReceive+0x94>
|
|
}
|
|
else
|
|
{
|
|
/* Timed out. If there is no data in the queue exit, otherwise loop
|
|
back and attempt to read the data. */
|
|
prvUnlockQueue( pxQueue );
|
|
800ad66: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ad68: f000 f960 bl 800b02c <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
800ad6c: f000 fc26 bl 800b5bc <xTaskResumeAll>
|
|
|
|
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
|
|
800ad70: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
800ad72: f000 f9ad bl 800b0d0 <prvIsQueueEmpty>
|
|
800ad76: 4603 mov r3, r0
|
|
800ad78: 2b00 cmp r3, #0
|
|
800ad7a: f43f af6f beq.w 800ac5c <xQueueReceive+0x94>
|
|
{
|
|
traceQUEUE_RECEIVE_FAILED( pxQueue );
|
|
return errQUEUE_EMPTY;
|
|
800ad7e: 2300 movs r3, #0
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
800ad80: 4618 mov r0, r3
|
|
800ad82: 3730 adds r7, #48 @ 0x30
|
|
800ad84: 46bd mov sp, r7
|
|
800ad86: bd80 pop {r7, pc}
|
|
800ad88: e000ed04 .word 0xe000ed04
|
|
|
|
0800ad8c <xQueueReceiveFromISR>:
|
|
} /*lint -restore */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
|
|
{
|
|
800ad8c: b580 push {r7, lr}
|
|
800ad8e: b08e sub sp, #56 @ 0x38
|
|
800ad90: af00 add r7, sp, #0
|
|
800ad92: 60f8 str r0, [r7, #12]
|
|
800ad94: 60b9 str r1, [r7, #8]
|
|
800ad96: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800ad98: 68fb ldr r3, [r7, #12]
|
|
800ad9a: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
800ad9c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ad9e: 2b00 cmp r3, #0
|
|
800ada0: d10b bne.n 800adba <xQueueReceiveFromISR+0x2e>
|
|
__asm volatile
|
|
800ada2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800ada6: f383 8811 msr BASEPRI, r3
|
|
800adaa: f3bf 8f6f isb sy
|
|
800adae: f3bf 8f4f dsb sy
|
|
800adb2: 623b str r3, [r7, #32]
|
|
}
|
|
800adb4: bf00 nop
|
|
800adb6: bf00 nop
|
|
800adb8: e7fd b.n 800adb6 <xQueueReceiveFromISR+0x2a>
|
|
configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
800adba: 68bb ldr r3, [r7, #8]
|
|
800adbc: 2b00 cmp r3, #0
|
|
800adbe: d103 bne.n 800adc8 <xQueueReceiveFromISR+0x3c>
|
|
800adc0: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800adc2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800adc4: 2b00 cmp r3, #0
|
|
800adc6: d101 bne.n 800adcc <xQueueReceiveFromISR+0x40>
|
|
800adc8: 2301 movs r3, #1
|
|
800adca: e000 b.n 800adce <xQueueReceiveFromISR+0x42>
|
|
800adcc: 2300 movs r3, #0
|
|
800adce: 2b00 cmp r3, #0
|
|
800add0: d10b bne.n 800adea <xQueueReceiveFromISR+0x5e>
|
|
__asm volatile
|
|
800add2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800add6: f383 8811 msr BASEPRI, r3
|
|
800adda: f3bf 8f6f isb sy
|
|
800adde: f3bf 8f4f dsb sy
|
|
800ade2: 61fb str r3, [r7, #28]
|
|
}
|
|
800ade4: bf00 nop
|
|
800ade6: bf00 nop
|
|
800ade8: e7fd b.n 800ade6 <xQueueReceiveFromISR+0x5a>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
800adea: f001 fac5 bl 800c378 <vPortValidateInterruptPriority>
|
|
__asm volatile
|
|
800adee: f3ef 8211 mrs r2, BASEPRI
|
|
800adf2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800adf6: f383 8811 msr BASEPRI, r3
|
|
800adfa: f3bf 8f6f isb sy
|
|
800adfe: f3bf 8f4f dsb sy
|
|
800ae02: 61ba str r2, [r7, #24]
|
|
800ae04: 617b str r3, [r7, #20]
|
|
return ulOriginalBASEPRI;
|
|
800ae06: 69bb ldr r3, [r7, #24]
|
|
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
800ae08: 62fb str r3, [r7, #44] @ 0x2c
|
|
{
|
|
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800ae0a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae0c: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800ae0e: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Cannot block in an ISR, so check there is data available. */
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800ae10: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ae12: 2b00 cmp r3, #0
|
|
800ae14: d02f beq.n 800ae76 <xQueueReceiveFromISR+0xea>
|
|
{
|
|
const int8_t cRxLock = pxQueue->cRxLock;
|
|
800ae16: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae18: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800ae1c: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
|
|
|
|
prvCopyDataFromQueue( pxQueue, pvBuffer );
|
|
800ae20: 68b9 ldr r1, [r7, #8]
|
|
800ae22: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
800ae24: f000 f8dc bl 800afe0 <prvCopyDataFromQueue>
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
|
|
800ae28: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800ae2a: 1e5a subs r2, r3, #1
|
|
800ae2c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae2e: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* If the queue is locked the event list will not be modified.
|
|
Instead update the lock count so the task that unlocks the queue
|
|
will know that an ISR has removed data while the queue was
|
|
locked. */
|
|
if( cRxLock == queueUNLOCKED )
|
|
800ae30: f997 3027 ldrsb.w r3, [r7, #39] @ 0x27
|
|
800ae34: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800ae38: d112 bne.n 800ae60 <xQueueReceiveFromISR+0xd4>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800ae3a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae3c: 691b ldr r3, [r3, #16]
|
|
800ae3e: 2b00 cmp r3, #0
|
|
800ae40: d016 beq.n 800ae70 <xQueueReceiveFromISR+0xe4>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800ae42: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae44: 3310 adds r3, #16
|
|
800ae46: 4618 mov r0, r3
|
|
800ae48: f000 fdb8 bl 800b9bc <xTaskRemoveFromEventList>
|
|
800ae4c: 4603 mov r3, r0
|
|
800ae4e: 2b00 cmp r3, #0
|
|
800ae50: d00e beq.n 800ae70 <xQueueReceiveFromISR+0xe4>
|
|
{
|
|
/* The task waiting has a higher priority than us so
|
|
force a context switch. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
800ae52: 687b ldr r3, [r7, #4]
|
|
800ae54: 2b00 cmp r3, #0
|
|
800ae56: d00b beq.n 800ae70 <xQueueReceiveFromISR+0xe4>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800ae58: 687b ldr r3, [r7, #4]
|
|
800ae5a: 2201 movs r2, #1
|
|
800ae5c: 601a str r2, [r3, #0]
|
|
800ae5e: e007 b.n 800ae70 <xQueueReceiveFromISR+0xe4>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was removed while it was locked. */
|
|
pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
|
|
800ae60: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
800ae64: 3301 adds r3, #1
|
|
800ae66: b2db uxtb r3, r3
|
|
800ae68: b25a sxtb r2, r3
|
|
800ae6a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800ae6c: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
800ae70: 2301 movs r3, #1
|
|
800ae72: 637b str r3, [r7, #52] @ 0x34
|
|
800ae74: e001 b.n 800ae7a <xQueueReceiveFromISR+0xee>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
800ae76: 2300 movs r3, #0
|
|
800ae78: 637b str r3, [r7, #52] @ 0x34
|
|
800ae7a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800ae7c: 613b str r3, [r7, #16]
|
|
__asm volatile
|
|
800ae7e: 693b ldr r3, [r7, #16]
|
|
800ae80: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800ae84: bf00 nop
|
|
traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800ae86: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
}
|
|
800ae88: 4618 mov r0, r3
|
|
800ae8a: 3738 adds r7, #56 @ 0x38
|
|
800ae8c: 46bd mov sp, r7
|
|
800ae8e: bd80 pop {r7, pc}
|
|
|
|
0800ae90 <uxQueueMessagesWaiting>:
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
|
|
{
|
|
800ae90: b580 push {r7, lr}
|
|
800ae92: b084 sub sp, #16
|
|
800ae94: af00 add r7, sp, #0
|
|
800ae96: 6078 str r0, [r7, #4]
|
|
UBaseType_t uxReturn;
|
|
|
|
configASSERT( xQueue );
|
|
800ae98: 687b ldr r3, [r7, #4]
|
|
800ae9a: 2b00 cmp r3, #0
|
|
800ae9c: d10b bne.n 800aeb6 <uxQueueMessagesWaiting+0x26>
|
|
__asm volatile
|
|
800ae9e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800aea2: f383 8811 msr BASEPRI, r3
|
|
800aea6: f3bf 8f6f isb sy
|
|
800aeaa: f3bf 8f4f dsb sy
|
|
800aeae: 60bb str r3, [r7, #8]
|
|
}
|
|
800aeb0: bf00 nop
|
|
800aeb2: bf00 nop
|
|
800aeb4: e7fd b.n 800aeb2 <uxQueueMessagesWaiting+0x22>
|
|
|
|
taskENTER_CRITICAL();
|
|
800aeb6: f001 f97f bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
|
|
800aeba: 687b ldr r3, [r7, #4]
|
|
800aebc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800aebe: 60fb str r3, [r7, #12]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800aec0: f001 f9ac bl 800c21c <vPortExitCritical>
|
|
|
|
return uxReturn;
|
|
800aec4: 68fb ldr r3, [r7, #12]
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
800aec6: 4618 mov r0, r3
|
|
800aec8: 3710 adds r7, #16
|
|
800aeca: 46bd mov sp, r7
|
|
800aecc: bd80 pop {r7, pc}
|
|
|
|
0800aece <uxQueueMessagesWaitingFromISR>:
|
|
return uxReturn;
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
|
|
{
|
|
800aece: b480 push {r7}
|
|
800aed0: b087 sub sp, #28
|
|
800aed2: af00 add r7, sp, #0
|
|
800aed4: 6078 str r0, [r7, #4]
|
|
UBaseType_t uxReturn;
|
|
Queue_t * const pxQueue = xQueue;
|
|
800aed6: 687b ldr r3, [r7, #4]
|
|
800aed8: 617b str r3, [r7, #20]
|
|
|
|
configASSERT( pxQueue );
|
|
800aeda: 697b ldr r3, [r7, #20]
|
|
800aedc: 2b00 cmp r3, #0
|
|
800aede: d10b bne.n 800aef8 <uxQueueMessagesWaitingFromISR+0x2a>
|
|
__asm volatile
|
|
800aee0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800aee4: f383 8811 msr BASEPRI, r3
|
|
800aee8: f3bf 8f6f isb sy
|
|
800aeec: f3bf 8f4f dsb sy
|
|
800aef0: 60fb str r3, [r7, #12]
|
|
}
|
|
800aef2: bf00 nop
|
|
800aef4: bf00 nop
|
|
800aef6: e7fd b.n 800aef4 <uxQueueMessagesWaitingFromISR+0x26>
|
|
uxReturn = pxQueue->uxMessagesWaiting;
|
|
800aef8: 697b ldr r3, [r7, #20]
|
|
800aefa: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800aefc: 613b str r3, [r7, #16]
|
|
|
|
return uxReturn;
|
|
800aefe: 693b ldr r3, [r7, #16]
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
800af00: 4618 mov r0, r3
|
|
800af02: 371c adds r7, #28
|
|
800af04: 46bd mov sp, r7
|
|
800af06: f85d 7b04 ldr.w r7, [sp], #4
|
|
800af0a: 4770 bx lr
|
|
|
|
0800af0c <prvCopyDataToQueue>:
|
|
|
|
#endif /* configUSE_MUTEXES */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
|
|
{
|
|
800af0c: b580 push {r7, lr}
|
|
800af0e: b086 sub sp, #24
|
|
800af10: af00 add r7, sp, #0
|
|
800af12: 60f8 str r0, [r7, #12]
|
|
800af14: 60b9 str r1, [r7, #8]
|
|
800af16: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800af18: 2300 movs r3, #0
|
|
800af1a: 617b str r3, [r7, #20]
|
|
UBaseType_t uxMessagesWaiting;
|
|
|
|
/* This function is called from a critical section. */
|
|
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
800af1c: 68fb ldr r3, [r7, #12]
|
|
800af1e: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800af20: 613b str r3, [r7, #16]
|
|
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
|
800af22: 68fb ldr r3, [r7, #12]
|
|
800af24: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800af26: 2b00 cmp r3, #0
|
|
800af28: d10d bne.n 800af46 <prvCopyDataToQueue+0x3a>
|
|
{
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
800af2a: 68fb ldr r3, [r7, #12]
|
|
800af2c: 681b ldr r3, [r3, #0]
|
|
800af2e: 2b00 cmp r3, #0
|
|
800af30: d14d bne.n 800afce <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* The mutex is no longer being held. */
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
800af32: 68fb ldr r3, [r7, #12]
|
|
800af34: 689b ldr r3, [r3, #8]
|
|
800af36: 4618 mov r0, r3
|
|
800af38: f000 ff20 bl 800bd7c <xTaskPriorityDisinherit>
|
|
800af3c: 6178 str r0, [r7, #20]
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
800af3e: 68fb ldr r3, [r7, #12]
|
|
800af40: 2200 movs r2, #0
|
|
800af42: 609a str r2, [r3, #8]
|
|
800af44: e043 b.n 800afce <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
}
|
|
else if( xPosition == queueSEND_TO_BACK )
|
|
800af46: 687b ldr r3, [r7, #4]
|
|
800af48: 2b00 cmp r3, #0
|
|
800af4a: d119 bne.n 800af80 <prvCopyDataToQueue+0x74>
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800af4c: 68fb ldr r3, [r7, #12]
|
|
800af4e: 6858 ldr r0, [r3, #4]
|
|
800af50: 68fb ldr r3, [r7, #12]
|
|
800af52: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800af54: 461a mov r2, r3
|
|
800af56: 68b9 ldr r1, [r7, #8]
|
|
800af58: f002 f83e bl 800cfd8 <memcpy>
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800af5c: 68fb ldr r3, [r7, #12]
|
|
800af5e: 685a ldr r2, [r3, #4]
|
|
800af60: 68fb ldr r3, [r7, #12]
|
|
800af62: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800af64: 441a add r2, r3
|
|
800af66: 68fb ldr r3, [r7, #12]
|
|
800af68: 605a str r2, [r3, #4]
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800af6a: 68fb ldr r3, [r7, #12]
|
|
800af6c: 685a ldr r2, [r3, #4]
|
|
800af6e: 68fb ldr r3, [r7, #12]
|
|
800af70: 689b ldr r3, [r3, #8]
|
|
800af72: 429a cmp r2, r3
|
|
800af74: d32b bcc.n 800afce <prvCopyDataToQueue+0xc2>
|
|
{
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800af76: 68fb ldr r3, [r7, #12]
|
|
800af78: 681a ldr r2, [r3, #0]
|
|
800af7a: 68fb ldr r3, [r7, #12]
|
|
800af7c: 605a str r2, [r3, #4]
|
|
800af7e: e026 b.n 800afce <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
|
800af80: 68fb ldr r3, [r7, #12]
|
|
800af82: 68d8 ldr r0, [r3, #12]
|
|
800af84: 68fb ldr r3, [r7, #12]
|
|
800af86: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800af88: 461a mov r2, r3
|
|
800af8a: 68b9 ldr r1, [r7, #8]
|
|
800af8c: f002 f824 bl 800cfd8 <memcpy>
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
|
800af90: 68fb ldr r3, [r7, #12]
|
|
800af92: 68da ldr r2, [r3, #12]
|
|
800af94: 68fb ldr r3, [r7, #12]
|
|
800af96: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800af98: 425b negs r3, r3
|
|
800af9a: 441a add r2, r3
|
|
800af9c: 68fb ldr r3, [r7, #12]
|
|
800af9e: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800afa0: 68fb ldr r3, [r7, #12]
|
|
800afa2: 68da ldr r2, [r3, #12]
|
|
800afa4: 68fb ldr r3, [r7, #12]
|
|
800afa6: 681b ldr r3, [r3, #0]
|
|
800afa8: 429a cmp r2, r3
|
|
800afaa: d207 bcs.n 800afbc <prvCopyDataToQueue+0xb0>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
|
800afac: 68fb ldr r3, [r7, #12]
|
|
800afae: 689a ldr r2, [r3, #8]
|
|
800afb0: 68fb ldr r3, [r7, #12]
|
|
800afb2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800afb4: 425b negs r3, r3
|
|
800afb6: 441a add r2, r3
|
|
800afb8: 68fb ldr r3, [r7, #12]
|
|
800afba: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xPosition == queueOVERWRITE )
|
|
800afbc: 687b ldr r3, [r7, #4]
|
|
800afbe: 2b02 cmp r3, #2
|
|
800afc0: d105 bne.n 800afce <prvCopyDataToQueue+0xc2>
|
|
{
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
800afc2: 693b ldr r3, [r7, #16]
|
|
800afc4: 2b00 cmp r3, #0
|
|
800afc6: d002 beq.n 800afce <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* An item is not being added but overwritten, so subtract
|
|
one from the recorded number of items in the queue so when
|
|
one is added again below the number of recorded items remains
|
|
correct. */
|
|
--uxMessagesWaiting;
|
|
800afc8: 693b ldr r3, [r7, #16]
|
|
800afca: 3b01 subs r3, #1
|
|
800afcc: 613b str r3, [r7, #16]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
800afce: 693b ldr r3, [r7, #16]
|
|
800afd0: 1c5a adds r2, r3, #1
|
|
800afd2: 68fb ldr r3, [r7, #12]
|
|
800afd4: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
return xReturn;
|
|
800afd6: 697b ldr r3, [r7, #20]
|
|
}
|
|
800afd8: 4618 mov r0, r3
|
|
800afda: 3718 adds r7, #24
|
|
800afdc: 46bd mov sp, r7
|
|
800afde: bd80 pop {r7, pc}
|
|
|
|
0800afe0 <prvCopyDataFromQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
|
|
{
|
|
800afe0: b580 push {r7, lr}
|
|
800afe2: b082 sub sp, #8
|
|
800afe4: af00 add r7, sp, #0
|
|
800afe6: 6078 str r0, [r7, #4]
|
|
800afe8: 6039 str r1, [r7, #0]
|
|
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
|
|
800afea: 687b ldr r3, [r7, #4]
|
|
800afec: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800afee: 2b00 cmp r3, #0
|
|
800aff0: d018 beq.n 800b024 <prvCopyDataFromQueue+0x44>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
800aff2: 687b ldr r3, [r7, #4]
|
|
800aff4: 68da ldr r2, [r3, #12]
|
|
800aff6: 687b ldr r3, [r7, #4]
|
|
800aff8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800affa: 441a add r2, r3
|
|
800affc: 687b ldr r3, [r7, #4]
|
|
800affe: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
|
|
800b000: 687b ldr r3, [r7, #4]
|
|
800b002: 68da ldr r2, [r3, #12]
|
|
800b004: 687b ldr r3, [r7, #4]
|
|
800b006: 689b ldr r3, [r3, #8]
|
|
800b008: 429a cmp r2, r3
|
|
800b00a: d303 bcc.n 800b014 <prvCopyDataFromQueue+0x34>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
|
|
800b00c: 687b ldr r3, [r7, #4]
|
|
800b00e: 681a ldr r2, [r3, #0]
|
|
800b010: 687b ldr r3, [r7, #4]
|
|
800b012: 60da str r2, [r3, #12]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
800b014: 687b ldr r3, [r7, #4]
|
|
800b016: 68d9 ldr r1, [r3, #12]
|
|
800b018: 687b ldr r3, [r7, #4]
|
|
800b01a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800b01c: 461a mov r2, r3
|
|
800b01e: 6838 ldr r0, [r7, #0]
|
|
800b020: f001 ffda bl 800cfd8 <memcpy>
|
|
}
|
|
}
|
|
800b024: bf00 nop
|
|
800b026: 3708 adds r7, #8
|
|
800b028: 46bd mov sp, r7
|
|
800b02a: bd80 pop {r7, pc}
|
|
|
|
0800b02c <prvUnlockQueue>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
|
{
|
|
800b02c: b580 push {r7, lr}
|
|
800b02e: b084 sub sp, #16
|
|
800b030: af00 add r7, sp, #0
|
|
800b032: 6078 str r0, [r7, #4]
|
|
|
|
/* The lock counts contains the number of extra data items placed or
|
|
removed from the queue while the queue was locked. When a queue is
|
|
locked items can be added or removed, but the event lists cannot be
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800b034: f001 f8c0 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
|
800b038: 687b ldr r3, [r7, #4]
|
|
800b03a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
800b03e: 73fb strb r3, [r7, #15]
|
|
|
|
/* See if data was added to the queue while it was locked. */
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800b040: e011 b.n 800b066 <prvUnlockQueue+0x3a>
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
/* Tasks that are removed from the event list will get added to
|
|
the pending ready list as the scheduler is still suspended. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800b042: 687b ldr r3, [r7, #4]
|
|
800b044: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800b046: 2b00 cmp r3, #0
|
|
800b048: d012 beq.n 800b070 <prvUnlockQueue+0x44>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
800b04a: 687b ldr r3, [r7, #4]
|
|
800b04c: 3324 adds r3, #36 @ 0x24
|
|
800b04e: 4618 mov r0, r3
|
|
800b050: f000 fcb4 bl 800b9bc <xTaskRemoveFromEventList>
|
|
800b054: 4603 mov r3, r0
|
|
800b056: 2b00 cmp r3, #0
|
|
800b058: d001 beq.n 800b05e <prvUnlockQueue+0x32>
|
|
{
|
|
/* The task waiting has a higher priority so record that
|
|
a context switch is required. */
|
|
vTaskMissedYield();
|
|
800b05a: f000 fd8d bl 800bb78 <vTaskMissedYield>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
--cTxLock;
|
|
800b05e: 7bfb ldrb r3, [r7, #15]
|
|
800b060: 3b01 subs r3, #1
|
|
800b062: b2db uxtb r3, r3
|
|
800b064: 73fb strb r3, [r7, #15]
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
800b066: f997 300f ldrsb.w r3, [r7, #15]
|
|
800b06a: 2b00 cmp r3, #0
|
|
800b06c: dce9 bgt.n 800b042 <prvUnlockQueue+0x16>
|
|
800b06e: e000 b.n 800b072 <prvUnlockQueue+0x46>
|
|
break;
|
|
800b070: bf00 nop
|
|
}
|
|
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
800b072: 687b ldr r3, [r7, #4]
|
|
800b074: 22ff movs r2, #255 @ 0xff
|
|
800b076: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b07a: f001 f8cf bl 800c21c <vPortExitCritical>
|
|
|
|
/* Do the same for the Rx lock. */
|
|
taskENTER_CRITICAL();
|
|
800b07e: f001 f89b bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
|
800b082: 687b ldr r3, [r7, #4]
|
|
800b084: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
800b088: 73bb strb r3, [r7, #14]
|
|
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800b08a: e011 b.n 800b0b0 <prvUnlockQueue+0x84>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
800b08c: 687b ldr r3, [r7, #4]
|
|
800b08e: 691b ldr r3, [r3, #16]
|
|
800b090: 2b00 cmp r3, #0
|
|
800b092: d012 beq.n 800b0ba <prvUnlockQueue+0x8e>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800b094: 687b ldr r3, [r7, #4]
|
|
800b096: 3310 adds r3, #16
|
|
800b098: 4618 mov r0, r3
|
|
800b09a: f000 fc8f bl 800b9bc <xTaskRemoveFromEventList>
|
|
800b09e: 4603 mov r3, r0
|
|
800b0a0: 2b00 cmp r3, #0
|
|
800b0a2: d001 beq.n 800b0a8 <prvUnlockQueue+0x7c>
|
|
{
|
|
vTaskMissedYield();
|
|
800b0a4: f000 fd68 bl 800bb78 <vTaskMissedYield>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--cRxLock;
|
|
800b0a8: 7bbb ldrb r3, [r7, #14]
|
|
800b0aa: 3b01 subs r3, #1
|
|
800b0ac: b2db uxtb r3, r3
|
|
800b0ae: 73bb strb r3, [r7, #14]
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
800b0b0: f997 300e ldrsb.w r3, [r7, #14]
|
|
800b0b4: 2b00 cmp r3, #0
|
|
800b0b6: dce9 bgt.n 800b08c <prvUnlockQueue+0x60>
|
|
800b0b8: e000 b.n 800b0bc <prvUnlockQueue+0x90>
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
800b0ba: bf00 nop
|
|
}
|
|
}
|
|
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
800b0bc: 687b ldr r3, [r7, #4]
|
|
800b0be: 22ff movs r2, #255 @ 0xff
|
|
800b0c0: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b0c4: f001 f8aa bl 800c21c <vPortExitCritical>
|
|
}
|
|
800b0c8: bf00 nop
|
|
800b0ca: 3710 adds r7, #16
|
|
800b0cc: 46bd mov sp, r7
|
|
800b0ce: bd80 pop {r7, pc}
|
|
|
|
0800b0d0 <prvIsQueueEmpty>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
|
|
{
|
|
800b0d0: b580 push {r7, lr}
|
|
800b0d2: b084 sub sp, #16
|
|
800b0d4: af00 add r7, sp, #0
|
|
800b0d6: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800b0d8: f001 f86e bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
|
|
800b0dc: 687b ldr r3, [r7, #4]
|
|
800b0de: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800b0e0: 2b00 cmp r3, #0
|
|
800b0e2: d102 bne.n 800b0ea <prvIsQueueEmpty+0x1a>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800b0e4: 2301 movs r3, #1
|
|
800b0e6: 60fb str r3, [r7, #12]
|
|
800b0e8: e001 b.n 800b0ee <prvIsQueueEmpty+0x1e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800b0ea: 2300 movs r3, #0
|
|
800b0ec: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b0ee: f001 f895 bl 800c21c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800b0f2: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800b0f4: 4618 mov r0, r3
|
|
800b0f6: 3710 adds r7, #16
|
|
800b0f8: 46bd mov sp, r7
|
|
800b0fa: bd80 pop {r7, pc}
|
|
|
|
0800b0fc <prvIsQueueFull>:
|
|
return xReturn;
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
|
|
{
|
|
800b0fc: b580 push {r7, lr}
|
|
800b0fe: b084 sub sp, #16
|
|
800b100: af00 add r7, sp, #0
|
|
800b102: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
800b104: f001 f858 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
|
800b108: 687b ldr r3, [r7, #4]
|
|
800b10a: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
800b10c: 687b ldr r3, [r7, #4]
|
|
800b10e: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800b110: 429a cmp r2, r3
|
|
800b112: d102 bne.n 800b11a <prvIsQueueFull+0x1e>
|
|
{
|
|
xReturn = pdTRUE;
|
|
800b114: 2301 movs r3, #1
|
|
800b116: 60fb str r3, [r7, #12]
|
|
800b118: e001 b.n 800b11e <prvIsQueueFull+0x22>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800b11a: 2300 movs r3, #0
|
|
800b11c: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b11e: f001 f87d bl 800c21c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800b122: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800b124: 4618 mov r0, r3
|
|
800b126: 3710 adds r7, #16
|
|
800b128: 46bd mov sp, r7
|
|
800b12a: bd80 pop {r7, pc}
|
|
|
|
0800b12c <xTaskCreateStatic>:
|
|
const uint32_t ulStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
StackType_t * const puxStackBuffer,
|
|
StaticTask_t * const pxTaskBuffer )
|
|
{
|
|
800b12c: b580 push {r7, lr}
|
|
800b12e: b08e sub sp, #56 @ 0x38
|
|
800b130: af04 add r7, sp, #16
|
|
800b132: 60f8 str r0, [r7, #12]
|
|
800b134: 60b9 str r1, [r7, #8]
|
|
800b136: 607a str r2, [r7, #4]
|
|
800b138: 603b str r3, [r7, #0]
|
|
TCB_t *pxNewTCB;
|
|
TaskHandle_t xReturn;
|
|
|
|
configASSERT( puxStackBuffer != NULL );
|
|
800b13a: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800b13c: 2b00 cmp r3, #0
|
|
800b13e: d10b bne.n 800b158 <xTaskCreateStatic+0x2c>
|
|
__asm volatile
|
|
800b140: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b144: f383 8811 msr BASEPRI, r3
|
|
800b148: f3bf 8f6f isb sy
|
|
800b14c: f3bf 8f4f dsb sy
|
|
800b150: 623b str r3, [r7, #32]
|
|
}
|
|
800b152: bf00 nop
|
|
800b154: bf00 nop
|
|
800b156: e7fd b.n 800b154 <xTaskCreateStatic+0x28>
|
|
configASSERT( pxTaskBuffer != NULL );
|
|
800b158: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800b15a: 2b00 cmp r3, #0
|
|
800b15c: d10b bne.n 800b176 <xTaskCreateStatic+0x4a>
|
|
__asm volatile
|
|
800b15e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b162: f383 8811 msr BASEPRI, r3
|
|
800b166: f3bf 8f6f isb sy
|
|
800b16a: f3bf 8f4f dsb sy
|
|
800b16e: 61fb str r3, [r7, #28]
|
|
}
|
|
800b170: bf00 nop
|
|
800b172: bf00 nop
|
|
800b174: e7fd b.n 800b172 <xTaskCreateStatic+0x46>
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
/* Sanity check that the size of the structure used to declare a
|
|
variable of type StaticTask_t equals the size of the real task
|
|
structure. */
|
|
volatile size_t xSize = sizeof( StaticTask_t );
|
|
800b176: 2358 movs r3, #88 @ 0x58
|
|
800b178: 613b str r3, [r7, #16]
|
|
configASSERT( xSize == sizeof( TCB_t ) );
|
|
800b17a: 693b ldr r3, [r7, #16]
|
|
800b17c: 2b58 cmp r3, #88 @ 0x58
|
|
800b17e: d00b beq.n 800b198 <xTaskCreateStatic+0x6c>
|
|
__asm volatile
|
|
800b180: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b184: f383 8811 msr BASEPRI, r3
|
|
800b188: f3bf 8f6f isb sy
|
|
800b18c: f3bf 8f4f dsb sy
|
|
800b190: 61bb str r3, [r7, #24]
|
|
}
|
|
800b192: bf00 nop
|
|
800b194: bf00 nop
|
|
800b196: e7fd b.n 800b194 <xTaskCreateStatic+0x68>
|
|
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
|
|
800b198: 693b ldr r3, [r7, #16]
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
|
|
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
|
|
800b19a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800b19c: 2b00 cmp r3, #0
|
|
800b19e: d01e beq.n 800b1de <xTaskCreateStatic+0xb2>
|
|
800b1a0: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
800b1a2: 2b00 cmp r3, #0
|
|
800b1a4: d01b beq.n 800b1de <xTaskCreateStatic+0xb2>
|
|
{
|
|
/* The memory used for the task's TCB and stack are passed into this
|
|
function - use them. */
|
|
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
|
|
800b1a6: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800b1a8: 627b str r3, [r7, #36] @ 0x24
|
|
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
|
|
800b1aa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b1ac: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
800b1ae: 631a str r2, [r3, #48] @ 0x30
|
|
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created statically in case the task is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800b1b0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b1b2: 2202 movs r2, #2
|
|
800b1b4: f883 2055 strb.w r2, [r3, #85] @ 0x55
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
|
|
800b1b8: 2300 movs r3, #0
|
|
800b1ba: 9303 str r3, [sp, #12]
|
|
800b1bc: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800b1be: 9302 str r3, [sp, #8]
|
|
800b1c0: f107 0314 add.w r3, r7, #20
|
|
800b1c4: 9301 str r3, [sp, #4]
|
|
800b1c6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b1c8: 9300 str r3, [sp, #0]
|
|
800b1ca: 683b ldr r3, [r7, #0]
|
|
800b1cc: 687a ldr r2, [r7, #4]
|
|
800b1ce: 68b9 ldr r1, [r7, #8]
|
|
800b1d0: 68f8 ldr r0, [r7, #12]
|
|
800b1d2: f000 f850 bl 800b276 <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800b1d6: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
800b1d8: f000 f8e0 bl 800b39c <prvAddNewTaskToReadyList>
|
|
800b1dc: e001 b.n 800b1e2 <xTaskCreateStatic+0xb6>
|
|
}
|
|
else
|
|
{
|
|
xReturn = NULL;
|
|
800b1de: 2300 movs r3, #0
|
|
800b1e0: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800b1e2: 697b ldr r3, [r7, #20]
|
|
}
|
|
800b1e4: 4618 mov r0, r3
|
|
800b1e6: 3728 adds r7, #40 @ 0x28
|
|
800b1e8: 46bd mov sp, r7
|
|
800b1ea: bd80 pop {r7, pc}
|
|
|
|
0800b1ec <xTaskCreate>:
|
|
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
|
|
const configSTACK_DEPTH_TYPE usStackDepth,
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask )
|
|
{
|
|
800b1ec: b580 push {r7, lr}
|
|
800b1ee: b08c sub sp, #48 @ 0x30
|
|
800b1f0: af04 add r7, sp, #16
|
|
800b1f2: 60f8 str r0, [r7, #12]
|
|
800b1f4: 60b9 str r1, [r7, #8]
|
|
800b1f6: 603b str r3, [r7, #0]
|
|
800b1f8: 4613 mov r3, r2
|
|
800b1fa: 80fb strh r3, [r7, #6]
|
|
#else /* portSTACK_GROWTH */
|
|
{
|
|
StackType_t *pxStack;
|
|
|
|
/* Allocate space for the stack used by the task being created. */
|
|
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
|
|
800b1fc: 88fb ldrh r3, [r7, #6]
|
|
800b1fe: 009b lsls r3, r3, #2
|
|
800b200: 4618 mov r0, r3
|
|
800b202: f001 f8fb bl 800c3fc <pvPortMalloc>
|
|
800b206: 6178 str r0, [r7, #20]
|
|
|
|
if( pxStack != NULL )
|
|
800b208: 697b ldr r3, [r7, #20]
|
|
800b20a: 2b00 cmp r3, #0
|
|
800b20c: d00e beq.n 800b22c <xTaskCreate+0x40>
|
|
{
|
|
/* Allocate space for the TCB. */
|
|
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
|
|
800b20e: 2058 movs r0, #88 @ 0x58
|
|
800b210: f001 f8f4 bl 800c3fc <pvPortMalloc>
|
|
800b214: 61f8 str r0, [r7, #28]
|
|
|
|
if( pxNewTCB != NULL )
|
|
800b216: 69fb ldr r3, [r7, #28]
|
|
800b218: 2b00 cmp r3, #0
|
|
800b21a: d003 beq.n 800b224 <xTaskCreate+0x38>
|
|
{
|
|
/* Store the stack location in the TCB. */
|
|
pxNewTCB->pxStack = pxStack;
|
|
800b21c: 69fb ldr r3, [r7, #28]
|
|
800b21e: 697a ldr r2, [r7, #20]
|
|
800b220: 631a str r2, [r3, #48] @ 0x30
|
|
800b222: e005 b.n 800b230 <xTaskCreate+0x44>
|
|
}
|
|
else
|
|
{
|
|
/* The stack cannot be used as the TCB was not created. Free
|
|
it again. */
|
|
vPortFree( pxStack );
|
|
800b224: 6978 ldr r0, [r7, #20]
|
|
800b226: f001 f9bd bl 800c5a4 <vPortFree>
|
|
800b22a: e001 b.n 800b230 <xTaskCreate+0x44>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxNewTCB = NULL;
|
|
800b22c: 2300 movs r3, #0
|
|
800b22e: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
if( pxNewTCB != NULL )
|
|
800b230: 69fb ldr r3, [r7, #28]
|
|
800b232: 2b00 cmp r3, #0
|
|
800b234: d017 beq.n 800b266 <xTaskCreate+0x7a>
|
|
{
|
|
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* Tasks can be created statically or dynamically, so note this
|
|
task was created dynamically in case it is later deleted. */
|
|
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
|
|
800b236: 69fb ldr r3, [r7, #28]
|
|
800b238: 2200 movs r2, #0
|
|
800b23a: f883 2055 strb.w r2, [r3, #85] @ 0x55
|
|
}
|
|
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
|
|
|
|
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
|
|
800b23e: 88fa ldrh r2, [r7, #6]
|
|
800b240: 2300 movs r3, #0
|
|
800b242: 9303 str r3, [sp, #12]
|
|
800b244: 69fb ldr r3, [r7, #28]
|
|
800b246: 9302 str r3, [sp, #8]
|
|
800b248: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800b24a: 9301 str r3, [sp, #4]
|
|
800b24c: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800b24e: 9300 str r3, [sp, #0]
|
|
800b250: 683b ldr r3, [r7, #0]
|
|
800b252: 68b9 ldr r1, [r7, #8]
|
|
800b254: 68f8 ldr r0, [r7, #12]
|
|
800b256: f000 f80e bl 800b276 <prvInitialiseNewTask>
|
|
prvAddNewTaskToReadyList( pxNewTCB );
|
|
800b25a: 69f8 ldr r0, [r7, #28]
|
|
800b25c: f000 f89e bl 800b39c <prvAddNewTaskToReadyList>
|
|
xReturn = pdPASS;
|
|
800b260: 2301 movs r3, #1
|
|
800b262: 61bb str r3, [r7, #24]
|
|
800b264: e002 b.n 800b26c <xTaskCreate+0x80>
|
|
}
|
|
else
|
|
{
|
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
|
800b266: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800b26a: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return xReturn;
|
|
800b26c: 69bb ldr r3, [r7, #24]
|
|
}
|
|
800b26e: 4618 mov r0, r3
|
|
800b270: 3720 adds r7, #32
|
|
800b272: 46bd mov sp, r7
|
|
800b274: bd80 pop {r7, pc}
|
|
|
|
0800b276 <prvInitialiseNewTask>:
|
|
void * const pvParameters,
|
|
UBaseType_t uxPriority,
|
|
TaskHandle_t * const pxCreatedTask,
|
|
TCB_t *pxNewTCB,
|
|
const MemoryRegion_t * const xRegions )
|
|
{
|
|
800b276: b580 push {r7, lr}
|
|
800b278: b088 sub sp, #32
|
|
800b27a: af00 add r7, sp, #0
|
|
800b27c: 60f8 str r0, [r7, #12]
|
|
800b27e: 60b9 str r1, [r7, #8]
|
|
800b280: 607a str r2, [r7, #4]
|
|
800b282: 603b str r3, [r7, #0]
|
|
|
|
/* Avoid dependency on memset() if it is not required. */
|
|
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
|
|
{
|
|
/* Fill the stack with a known value to assist debugging. */
|
|
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
|
|
800b284: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b286: 6b18 ldr r0, [r3, #48] @ 0x30
|
|
800b288: 687b ldr r3, [r7, #4]
|
|
800b28a: 009b lsls r3, r3, #2
|
|
800b28c: 461a mov r2, r3
|
|
800b28e: 21a5 movs r1, #165 @ 0xa5
|
|
800b290: f001 fe5e bl 800cf50 <memset>
|
|
grows from high memory to low (as per the 80x86) or vice versa.
|
|
portSTACK_GROWTH is used to make the result positive or negative as required
|
|
by the port. */
|
|
#if( portSTACK_GROWTH < 0 )
|
|
{
|
|
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
|
|
800b294: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b296: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
800b298: 687b ldr r3, [r7, #4]
|
|
800b29a: f103 4380 add.w r3, r3, #1073741824 @ 0x40000000
|
|
800b29e: 3b01 subs r3, #1
|
|
800b2a0: 009b lsls r3, r3, #2
|
|
800b2a2: 4413 add r3, r2
|
|
800b2a4: 61bb str r3, [r7, #24]
|
|
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
|
|
800b2a6: 69bb ldr r3, [r7, #24]
|
|
800b2a8: f023 0307 bic.w r3, r3, #7
|
|
800b2ac: 61bb str r3, [r7, #24]
|
|
|
|
/* Check the alignment of the calculated top of stack is correct. */
|
|
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
|
|
800b2ae: 69bb ldr r3, [r7, #24]
|
|
800b2b0: f003 0307 and.w r3, r3, #7
|
|
800b2b4: 2b00 cmp r3, #0
|
|
800b2b6: d00b beq.n 800b2d0 <prvInitialiseNewTask+0x5a>
|
|
__asm volatile
|
|
800b2b8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b2bc: f383 8811 msr BASEPRI, r3
|
|
800b2c0: f3bf 8f6f isb sy
|
|
800b2c4: f3bf 8f4f dsb sy
|
|
800b2c8: 617b str r3, [r7, #20]
|
|
}
|
|
800b2ca: bf00 nop
|
|
800b2cc: bf00 nop
|
|
800b2ce: e7fd b.n 800b2cc <prvInitialiseNewTask+0x56>
|
|
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
|
|
/* Store the task name in the TCB. */
|
|
if( pcName != NULL )
|
|
800b2d0: 68bb ldr r3, [r7, #8]
|
|
800b2d2: 2b00 cmp r3, #0
|
|
800b2d4: d01f beq.n 800b316 <prvInitialiseNewTask+0xa0>
|
|
{
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800b2d6: 2300 movs r3, #0
|
|
800b2d8: 61fb str r3, [r7, #28]
|
|
800b2da: e012 b.n 800b302 <prvInitialiseNewTask+0x8c>
|
|
{
|
|
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
|
|
800b2dc: 68ba ldr r2, [r7, #8]
|
|
800b2de: 69fb ldr r3, [r7, #28]
|
|
800b2e0: 4413 add r3, r2
|
|
800b2e2: 7819 ldrb r1, [r3, #0]
|
|
800b2e4: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800b2e6: 69fb ldr r3, [r7, #28]
|
|
800b2e8: 4413 add r3, r2
|
|
800b2ea: 3334 adds r3, #52 @ 0x34
|
|
800b2ec: 460a mov r2, r1
|
|
800b2ee: 701a strb r2, [r3, #0]
|
|
|
|
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
|
|
configMAX_TASK_NAME_LEN characters just in case the memory after the
|
|
string is not accessible (extremely unlikely). */
|
|
if( pcName[ x ] == ( char ) 0x00 )
|
|
800b2f0: 68ba ldr r2, [r7, #8]
|
|
800b2f2: 69fb ldr r3, [r7, #28]
|
|
800b2f4: 4413 add r3, r2
|
|
800b2f6: 781b ldrb r3, [r3, #0]
|
|
800b2f8: 2b00 cmp r3, #0
|
|
800b2fa: d006 beq.n 800b30a <prvInitialiseNewTask+0x94>
|
|
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
|
|
800b2fc: 69fb ldr r3, [r7, #28]
|
|
800b2fe: 3301 adds r3, #1
|
|
800b300: 61fb str r3, [r7, #28]
|
|
800b302: 69fb ldr r3, [r7, #28]
|
|
800b304: 2b0f cmp r3, #15
|
|
800b306: d9e9 bls.n 800b2dc <prvInitialiseNewTask+0x66>
|
|
800b308: e000 b.n 800b30c <prvInitialiseNewTask+0x96>
|
|
{
|
|
break;
|
|
800b30a: bf00 nop
|
|
}
|
|
}
|
|
|
|
/* Ensure the name string is terminated in the case that the string length
|
|
was greater or equal to configMAX_TASK_NAME_LEN. */
|
|
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
|
|
800b30c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b30e: 2200 movs r2, #0
|
|
800b310: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
800b314: e003 b.n 800b31e <prvInitialiseNewTask+0xa8>
|
|
}
|
|
else
|
|
{
|
|
/* The task has not been given a name, so just ensure there is a NULL
|
|
terminator when it is read out. */
|
|
pxNewTCB->pcTaskName[ 0 ] = 0x00;
|
|
800b316: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b318: 2200 movs r2, #0
|
|
800b31a: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
}
|
|
|
|
/* This is used as an array index so must ensure it's not too large. First
|
|
remove the privilege bit if one is present. */
|
|
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
|
|
800b31e: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800b320: 2b06 cmp r3, #6
|
|
800b322: d901 bls.n 800b328 <prvInitialiseNewTask+0xb2>
|
|
{
|
|
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
|
|
800b324: 2306 movs r3, #6
|
|
800b326: 62bb str r3, [r7, #40] @ 0x28
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxNewTCB->uxPriority = uxPriority;
|
|
800b328: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b32a: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800b32c: 62da str r2, [r3, #44] @ 0x2c
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
pxNewTCB->uxBasePriority = uxPriority;
|
|
800b32e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b330: 6aba ldr r2, [r7, #40] @ 0x28
|
|
800b332: 645a str r2, [r3, #68] @ 0x44
|
|
pxNewTCB->uxMutexesHeld = 0;
|
|
800b334: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b336: 2200 movs r2, #0
|
|
800b338: 649a str r2, [r3, #72] @ 0x48
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
|
|
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
|
|
800b33a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b33c: 3304 adds r3, #4
|
|
800b33e: 4618 mov r0, r3
|
|
800b340: f7ff f8cc bl 800a4dc <vListInitialiseItem>
|
|
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
|
|
800b344: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b346: 3318 adds r3, #24
|
|
800b348: 4618 mov r0, r3
|
|
800b34a: f7ff f8c7 bl 800a4dc <vListInitialiseItem>
|
|
|
|
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
|
|
back to the containing TCB from a generic item in a list. */
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
|
|
800b34e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b350: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800b352: 611a str r2, [r3, #16]
|
|
|
|
/* Event lists are always in priority order. */
|
|
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800b354: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800b356: f1c3 0207 rsb r2, r3, #7
|
|
800b35a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b35c: 619a str r2, [r3, #24]
|
|
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
|
|
800b35e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b360: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800b362: 625a str r2, [r3, #36] @ 0x24
|
|
}
|
|
#endif /* portCRITICAL_NESTING_IN_TCB */
|
|
|
|
#if ( configUSE_APPLICATION_TASK_TAG == 1 )
|
|
{
|
|
pxNewTCB->pxTaskTag = NULL;
|
|
800b364: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b366: 2200 movs r2, #0
|
|
800b368: 64da str r2, [r3, #76] @ 0x4c
|
|
}
|
|
#endif
|
|
|
|
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
|
|
{
|
|
pxNewTCB->ulNotifiedValue = 0;
|
|
800b36a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b36c: 2200 movs r2, #0
|
|
800b36e: 651a str r2, [r3, #80] @ 0x50
|
|
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
|
|
800b370: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b372: 2200 movs r2, #0
|
|
800b374: f883 2054 strb.w r2, [r3, #84] @ 0x54
|
|
}
|
|
#endif /* portSTACK_GROWTH */
|
|
}
|
|
#else /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
{
|
|
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
|
|
800b378: 683a ldr r2, [r7, #0]
|
|
800b37a: 68f9 ldr r1, [r7, #12]
|
|
800b37c: 69b8 ldr r0, [r7, #24]
|
|
800b37e: f000 fdeb bl 800bf58 <pxPortInitialiseStack>
|
|
800b382: 4602 mov r2, r0
|
|
800b384: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
800b386: 601a str r2, [r3, #0]
|
|
}
|
|
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
|
|
}
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
|
|
if( pxCreatedTask != NULL )
|
|
800b388: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800b38a: 2b00 cmp r3, #0
|
|
800b38c: d002 beq.n 800b394 <prvInitialiseNewTask+0x11e>
|
|
{
|
|
/* Pass the handle out in an anonymous way. The handle can be used to
|
|
change the created task's priority, delete the created task, etc.*/
|
|
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
|
|
800b38e: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800b390: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
800b392: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800b394: bf00 nop
|
|
800b396: 3720 adds r7, #32
|
|
800b398: 46bd mov sp, r7
|
|
800b39a: bd80 pop {r7, pc}
|
|
|
|
0800b39c <prvAddNewTaskToReadyList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
|
|
{
|
|
800b39c: b580 push {r7, lr}
|
|
800b39e: b082 sub sp, #8
|
|
800b3a0: af00 add r7, sp, #0
|
|
800b3a2: 6078 str r0, [r7, #4]
|
|
/* Ensure interrupts don't access the task lists while the lists are being
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
800b3a4: f000 ff08 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
uxCurrentNumberOfTasks++;
|
|
800b3a8: 4b2a ldr r3, [pc, #168] @ (800b454 <prvAddNewTaskToReadyList+0xb8>)
|
|
800b3aa: 681b ldr r3, [r3, #0]
|
|
800b3ac: 3301 adds r3, #1
|
|
800b3ae: 4a29 ldr r2, [pc, #164] @ (800b454 <prvAddNewTaskToReadyList+0xb8>)
|
|
800b3b0: 6013 str r3, [r2, #0]
|
|
if( pxCurrentTCB == NULL )
|
|
800b3b2: 4b29 ldr r3, [pc, #164] @ (800b458 <prvAddNewTaskToReadyList+0xbc>)
|
|
800b3b4: 681b ldr r3, [r3, #0]
|
|
800b3b6: 2b00 cmp r3, #0
|
|
800b3b8: d109 bne.n 800b3ce <prvAddNewTaskToReadyList+0x32>
|
|
{
|
|
/* There are no other tasks, or all the other tasks are in
|
|
the suspended state - make this the current task. */
|
|
pxCurrentTCB = pxNewTCB;
|
|
800b3ba: 4a27 ldr r2, [pc, #156] @ (800b458 <prvAddNewTaskToReadyList+0xbc>)
|
|
800b3bc: 687b ldr r3, [r7, #4]
|
|
800b3be: 6013 str r3, [r2, #0]
|
|
|
|
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
|
|
800b3c0: 4b24 ldr r3, [pc, #144] @ (800b454 <prvAddNewTaskToReadyList+0xb8>)
|
|
800b3c2: 681b ldr r3, [r3, #0]
|
|
800b3c4: 2b01 cmp r3, #1
|
|
800b3c6: d110 bne.n 800b3ea <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
/* This is the first task to be created so do the preliminary
|
|
initialisation required. We will not recover if this call
|
|
fails, but we will report the failure. */
|
|
prvInitialiseTaskLists();
|
|
800b3c8: f000 fbfc bl 800bbc4 <prvInitialiseTaskLists>
|
|
800b3cc: e00d b.n 800b3ea <prvAddNewTaskToReadyList+0x4e>
|
|
else
|
|
{
|
|
/* If the scheduler is not already running, make this task the
|
|
current task if it is the highest priority task to be created
|
|
so far. */
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800b3ce: 4b23 ldr r3, [pc, #140] @ (800b45c <prvAddNewTaskToReadyList+0xc0>)
|
|
800b3d0: 681b ldr r3, [r3, #0]
|
|
800b3d2: 2b00 cmp r3, #0
|
|
800b3d4: d109 bne.n 800b3ea <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
|
|
800b3d6: 4b20 ldr r3, [pc, #128] @ (800b458 <prvAddNewTaskToReadyList+0xbc>)
|
|
800b3d8: 681b ldr r3, [r3, #0]
|
|
800b3da: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b3dc: 687b ldr r3, [r7, #4]
|
|
800b3de: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b3e0: 429a cmp r2, r3
|
|
800b3e2: d802 bhi.n 800b3ea <prvAddNewTaskToReadyList+0x4e>
|
|
{
|
|
pxCurrentTCB = pxNewTCB;
|
|
800b3e4: 4a1c ldr r2, [pc, #112] @ (800b458 <prvAddNewTaskToReadyList+0xbc>)
|
|
800b3e6: 687b ldr r3, [r7, #4]
|
|
800b3e8: 6013 str r3, [r2, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
uxTaskNumber++;
|
|
800b3ea: 4b1d ldr r3, [pc, #116] @ (800b460 <prvAddNewTaskToReadyList+0xc4>)
|
|
800b3ec: 681b ldr r3, [r3, #0]
|
|
800b3ee: 3301 adds r3, #1
|
|
800b3f0: 4a1b ldr r2, [pc, #108] @ (800b460 <prvAddNewTaskToReadyList+0xc4>)
|
|
800b3f2: 6013 str r3, [r2, #0]
|
|
pxNewTCB->uxTCBNumber = uxTaskNumber;
|
|
}
|
|
#endif /* configUSE_TRACE_FACILITY */
|
|
traceTASK_CREATE( pxNewTCB );
|
|
|
|
prvAddTaskToReadyList( pxNewTCB );
|
|
800b3f4: 687b ldr r3, [r7, #4]
|
|
800b3f6: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b3f8: 2201 movs r2, #1
|
|
800b3fa: 409a lsls r2, r3
|
|
800b3fc: 4b19 ldr r3, [pc, #100] @ (800b464 <prvAddNewTaskToReadyList+0xc8>)
|
|
800b3fe: 681b ldr r3, [r3, #0]
|
|
800b400: 4313 orrs r3, r2
|
|
800b402: 4a18 ldr r2, [pc, #96] @ (800b464 <prvAddNewTaskToReadyList+0xc8>)
|
|
800b404: 6013 str r3, [r2, #0]
|
|
800b406: 687b ldr r3, [r7, #4]
|
|
800b408: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b40a: 4613 mov r3, r2
|
|
800b40c: 009b lsls r3, r3, #2
|
|
800b40e: 4413 add r3, r2
|
|
800b410: 009b lsls r3, r3, #2
|
|
800b412: 4a15 ldr r2, [pc, #84] @ (800b468 <prvAddNewTaskToReadyList+0xcc>)
|
|
800b414: 441a add r2, r3
|
|
800b416: 687b ldr r3, [r7, #4]
|
|
800b418: 3304 adds r3, #4
|
|
800b41a: 4619 mov r1, r3
|
|
800b41c: 4610 mov r0, r2
|
|
800b41e: f7ff f86a bl 800a4f6 <vListInsertEnd>
|
|
|
|
portSETUP_TCB( pxNewTCB );
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b422: f000 fefb bl 800c21c <vPortExitCritical>
|
|
|
|
if( xSchedulerRunning != pdFALSE )
|
|
800b426: 4b0d ldr r3, [pc, #52] @ (800b45c <prvAddNewTaskToReadyList+0xc0>)
|
|
800b428: 681b ldr r3, [r3, #0]
|
|
800b42a: 2b00 cmp r3, #0
|
|
800b42c: d00e beq.n 800b44c <prvAddNewTaskToReadyList+0xb0>
|
|
{
|
|
/* If the created task is of a higher priority than the current task
|
|
then it should run now. */
|
|
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
|
|
800b42e: 4b0a ldr r3, [pc, #40] @ (800b458 <prvAddNewTaskToReadyList+0xbc>)
|
|
800b430: 681b ldr r3, [r3, #0]
|
|
800b432: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b434: 687b ldr r3, [r7, #4]
|
|
800b436: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b438: 429a cmp r2, r3
|
|
800b43a: d207 bcs.n 800b44c <prvAddNewTaskToReadyList+0xb0>
|
|
{
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800b43c: 4b0b ldr r3, [pc, #44] @ (800b46c <prvAddNewTaskToReadyList+0xd0>)
|
|
800b43e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800b442: 601a str r2, [r3, #0]
|
|
800b444: f3bf 8f4f dsb sy
|
|
800b448: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800b44c: bf00 nop
|
|
800b44e: 3708 adds r7, #8
|
|
800b450: 46bd mov sp, r7
|
|
800b452: bd80 pop {r7, pc}
|
|
800b454: 200006ac .word 0x200006ac
|
|
800b458: 200005ac .word 0x200005ac
|
|
800b45c: 200006b8 .word 0x200006b8
|
|
800b460: 200006c8 .word 0x200006c8
|
|
800b464: 200006b4 .word 0x200006b4
|
|
800b468: 200005b0 .word 0x200005b0
|
|
800b46c: e000ed04 .word 0xe000ed04
|
|
|
|
0800b470 <vTaskDelay>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelay == 1 )
|
|
|
|
void vTaskDelay( const TickType_t xTicksToDelay )
|
|
{
|
|
800b470: b580 push {r7, lr}
|
|
800b472: b084 sub sp, #16
|
|
800b474: af00 add r7, sp, #0
|
|
800b476: 6078 str r0, [r7, #4]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
800b478: 2300 movs r3, #0
|
|
800b47a: 60fb str r3, [r7, #12]
|
|
|
|
/* A delay time of zero just forces a reschedule. */
|
|
if( xTicksToDelay > ( TickType_t ) 0U )
|
|
800b47c: 687b ldr r3, [r7, #4]
|
|
800b47e: 2b00 cmp r3, #0
|
|
800b480: d018 beq.n 800b4b4 <vTaskDelay+0x44>
|
|
{
|
|
configASSERT( uxSchedulerSuspended == 0 );
|
|
800b482: 4b14 ldr r3, [pc, #80] @ (800b4d4 <vTaskDelay+0x64>)
|
|
800b484: 681b ldr r3, [r3, #0]
|
|
800b486: 2b00 cmp r3, #0
|
|
800b488: d00b beq.n 800b4a2 <vTaskDelay+0x32>
|
|
__asm volatile
|
|
800b48a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b48e: f383 8811 msr BASEPRI, r3
|
|
800b492: f3bf 8f6f isb sy
|
|
800b496: f3bf 8f4f dsb sy
|
|
800b49a: 60bb str r3, [r7, #8]
|
|
}
|
|
800b49c: bf00 nop
|
|
800b49e: bf00 nop
|
|
800b4a0: e7fd b.n 800b49e <vTaskDelay+0x2e>
|
|
vTaskSuspendAll();
|
|
800b4a2: f000 f87d bl 800b5a0 <vTaskSuspendAll>
|
|
list or removed from the blocked list until the scheduler
|
|
is resumed.
|
|
|
|
This task cannot be in an event list as it is the currently
|
|
executing task. */
|
|
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
|
|
800b4a6: 2100 movs r1, #0
|
|
800b4a8: 6878 ldr r0, [r7, #4]
|
|
800b4aa: f000 fcef bl 800be8c <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
xAlreadyYielded = xTaskResumeAll();
|
|
800b4ae: f000 f885 bl 800b5bc <xTaskResumeAll>
|
|
800b4b2: 60f8 str r0, [r7, #12]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Force a reschedule if xTaskResumeAll has not already done so, we may
|
|
have put ourselves to sleep. */
|
|
if( xAlreadyYielded == pdFALSE )
|
|
800b4b4: 68fb ldr r3, [r7, #12]
|
|
800b4b6: 2b00 cmp r3, #0
|
|
800b4b8: d107 bne.n 800b4ca <vTaskDelay+0x5a>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
800b4ba: 4b07 ldr r3, [pc, #28] @ (800b4d8 <vTaskDelay+0x68>)
|
|
800b4bc: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800b4c0: 601a str r2, [r3, #0]
|
|
800b4c2: f3bf 8f4f dsb sy
|
|
800b4c6: f3bf 8f6f isb sy
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800b4ca: bf00 nop
|
|
800b4cc: 3710 adds r7, #16
|
|
800b4ce: 46bd mov sp, r7
|
|
800b4d0: bd80 pop {r7, pc}
|
|
800b4d2: bf00 nop
|
|
800b4d4: 200006d4 .word 0x200006d4
|
|
800b4d8: e000ed04 .word 0xe000ed04
|
|
|
|
0800b4dc <vTaskStartScheduler>:
|
|
|
|
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskStartScheduler( void )
|
|
{
|
|
800b4dc: b580 push {r7, lr}
|
|
800b4de: b08a sub sp, #40 @ 0x28
|
|
800b4e0: af04 add r7, sp, #16
|
|
BaseType_t xReturn;
|
|
|
|
/* Add the idle task at the lowest priority. */
|
|
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
|
{
|
|
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
|
|
800b4e2: 2300 movs r3, #0
|
|
800b4e4: 60bb str r3, [r7, #8]
|
|
StackType_t *pxIdleTaskStackBuffer = NULL;
|
|
800b4e6: 2300 movs r3, #0
|
|
800b4e8: 607b str r3, [r7, #4]
|
|
uint32_t ulIdleTaskStackSize;
|
|
|
|
/* The Idle task is created using user provided RAM - obtain the
|
|
address of the RAM then create the idle task. */
|
|
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
|
|
800b4ea: 463a mov r2, r7
|
|
800b4ec: 1d39 adds r1, r7, #4
|
|
800b4ee: f107 0308 add.w r3, r7, #8
|
|
800b4f2: 4618 mov r0, r3
|
|
800b4f4: f7f5 f82c bl 8000550 <vApplicationGetIdleTaskMemory>
|
|
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
|
|
800b4f8: 6839 ldr r1, [r7, #0]
|
|
800b4fa: 687b ldr r3, [r7, #4]
|
|
800b4fc: 68ba ldr r2, [r7, #8]
|
|
800b4fe: 9202 str r2, [sp, #8]
|
|
800b500: 9301 str r3, [sp, #4]
|
|
800b502: 2300 movs r3, #0
|
|
800b504: 9300 str r3, [sp, #0]
|
|
800b506: 2300 movs r3, #0
|
|
800b508: 460a mov r2, r1
|
|
800b50a: 491f ldr r1, [pc, #124] @ (800b588 <vTaskStartScheduler+0xac>)
|
|
800b50c: 481f ldr r0, [pc, #124] @ (800b58c <vTaskStartScheduler+0xb0>)
|
|
800b50e: f7ff fe0d bl 800b12c <xTaskCreateStatic>
|
|
800b512: 4603 mov r3, r0
|
|
800b514: 4a1e ldr r2, [pc, #120] @ (800b590 <vTaskStartScheduler+0xb4>)
|
|
800b516: 6013 str r3, [r2, #0]
|
|
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
|
|
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
|
|
pxIdleTaskStackBuffer,
|
|
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
|
|
|
|
if( xIdleTaskHandle != NULL )
|
|
800b518: 4b1d ldr r3, [pc, #116] @ (800b590 <vTaskStartScheduler+0xb4>)
|
|
800b51a: 681b ldr r3, [r3, #0]
|
|
800b51c: 2b00 cmp r3, #0
|
|
800b51e: d002 beq.n 800b526 <vTaskStartScheduler+0x4a>
|
|
{
|
|
xReturn = pdPASS;
|
|
800b520: 2301 movs r3, #1
|
|
800b522: 617b str r3, [r7, #20]
|
|
800b524: e001 b.n 800b52a <vTaskStartScheduler+0x4e>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFAIL;
|
|
800b526: 2300 movs r3, #0
|
|
800b528: 617b str r3, [r7, #20]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_TIMERS */
|
|
|
|
if( xReturn == pdPASS )
|
|
800b52a: 697b ldr r3, [r7, #20]
|
|
800b52c: 2b01 cmp r3, #1
|
|
800b52e: d116 bne.n 800b55e <vTaskStartScheduler+0x82>
|
|
__asm volatile
|
|
800b530: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b534: f383 8811 msr BASEPRI, r3
|
|
800b538: f3bf 8f6f isb sy
|
|
800b53c: f3bf 8f4f dsb sy
|
|
800b540: 613b str r3, [r7, #16]
|
|
}
|
|
800b542: bf00 nop
|
|
for additional information. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800b544: 4b13 ldr r3, [pc, #76] @ (800b594 <vTaskStartScheduler+0xb8>)
|
|
800b546: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800b54a: 601a str r2, [r3, #0]
|
|
xSchedulerRunning = pdTRUE;
|
|
800b54c: 4b12 ldr r3, [pc, #72] @ (800b598 <vTaskStartScheduler+0xbc>)
|
|
800b54e: 2201 movs r2, #1
|
|
800b550: 601a str r2, [r3, #0]
|
|
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
|
|
800b552: 4b12 ldr r3, [pc, #72] @ (800b59c <vTaskStartScheduler+0xc0>)
|
|
800b554: 2200 movs r2, #0
|
|
800b556: 601a str r2, [r3, #0]
|
|
|
|
traceTASK_SWITCHED_IN();
|
|
|
|
/* Setting up the timer tick is hardware specific and thus in the
|
|
portable interface. */
|
|
if( xPortStartScheduler() != pdFALSE )
|
|
800b558: f000 fd8a bl 800c070 <xPortStartScheduler>
|
|
}
|
|
|
|
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
|
|
meaning xIdleTaskHandle is not used anywhere else. */
|
|
( void ) xIdleTaskHandle;
|
|
}
|
|
800b55c: e00f b.n 800b57e <vTaskStartScheduler+0xa2>
|
|
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
|
|
800b55e: 697b ldr r3, [r7, #20]
|
|
800b560: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800b564: d10b bne.n 800b57e <vTaskStartScheduler+0xa2>
|
|
__asm volatile
|
|
800b566: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b56a: f383 8811 msr BASEPRI, r3
|
|
800b56e: f3bf 8f6f isb sy
|
|
800b572: f3bf 8f4f dsb sy
|
|
800b576: 60fb str r3, [r7, #12]
|
|
}
|
|
800b578: bf00 nop
|
|
800b57a: bf00 nop
|
|
800b57c: e7fd b.n 800b57a <vTaskStartScheduler+0x9e>
|
|
}
|
|
800b57e: bf00 nop
|
|
800b580: 3718 adds r7, #24
|
|
800b582: 46bd mov sp, r7
|
|
800b584: bd80 pop {r7, pc}
|
|
800b586: bf00 nop
|
|
800b588: 0800d104 .word 0x0800d104
|
|
800b58c: 0800bb91 .word 0x0800bb91
|
|
800b590: 200006d0 .word 0x200006d0
|
|
800b594: 200006cc .word 0x200006cc
|
|
800b598: 200006b8 .word 0x200006b8
|
|
800b59c: 200006b0 .word 0x200006b0
|
|
|
|
0800b5a0 <vTaskSuspendAll>:
|
|
vPortEndScheduler();
|
|
}
|
|
/*----------------------------------------------------------*/
|
|
|
|
void vTaskSuspendAll( void )
|
|
{
|
|
800b5a0: b480 push {r7}
|
|
800b5a2: af00 add r7, sp, #0
|
|
do not otherwise exhibit real time behaviour. */
|
|
portSOFTWARE_BARRIER();
|
|
|
|
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
|
|
is used to allow calls to vTaskSuspendAll() to nest. */
|
|
++uxSchedulerSuspended;
|
|
800b5a4: 4b04 ldr r3, [pc, #16] @ (800b5b8 <vTaskSuspendAll+0x18>)
|
|
800b5a6: 681b ldr r3, [r3, #0]
|
|
800b5a8: 3301 adds r3, #1
|
|
800b5aa: 4a03 ldr r2, [pc, #12] @ (800b5b8 <vTaskSuspendAll+0x18>)
|
|
800b5ac: 6013 str r3, [r2, #0]
|
|
|
|
/* Enforces ordering for ports and optimised compilers that may otherwise place
|
|
the above increment elsewhere. */
|
|
portMEMORY_BARRIER();
|
|
}
|
|
800b5ae: bf00 nop
|
|
800b5b0: 46bd mov sp, r7
|
|
800b5b2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800b5b6: 4770 bx lr
|
|
800b5b8: 200006d4 .word 0x200006d4
|
|
|
|
0800b5bc <xTaskResumeAll>:
|
|
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskResumeAll( void )
|
|
{
|
|
800b5bc: b580 push {r7, lr}
|
|
800b5be: b084 sub sp, #16
|
|
800b5c0: af00 add r7, sp, #0
|
|
TCB_t *pxTCB = NULL;
|
|
800b5c2: 2300 movs r3, #0
|
|
800b5c4: 60fb str r3, [r7, #12]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
800b5c6: 2300 movs r3, #0
|
|
800b5c8: 60bb str r3, [r7, #8]
|
|
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
|
previous call to vTaskSuspendAll(). */
|
|
configASSERT( uxSchedulerSuspended );
|
|
800b5ca: 4b42 ldr r3, [pc, #264] @ (800b6d4 <xTaskResumeAll+0x118>)
|
|
800b5cc: 681b ldr r3, [r3, #0]
|
|
800b5ce: 2b00 cmp r3, #0
|
|
800b5d0: d10b bne.n 800b5ea <xTaskResumeAll+0x2e>
|
|
__asm volatile
|
|
800b5d2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b5d6: f383 8811 msr BASEPRI, r3
|
|
800b5da: f3bf 8f6f isb sy
|
|
800b5de: f3bf 8f4f dsb sy
|
|
800b5e2: 603b str r3, [r7, #0]
|
|
}
|
|
800b5e4: bf00 nop
|
|
800b5e6: bf00 nop
|
|
800b5e8: e7fd b.n 800b5e6 <xTaskResumeAll+0x2a>
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
|
list while the scheduler was suspended. If this was the case then the
|
|
removed task will have been added to the xPendingReadyList. Once the
|
|
scheduler has been resumed it is safe to move all the pending ready
|
|
tasks from this list into their appropriate ready list. */
|
|
taskENTER_CRITICAL();
|
|
800b5ea: f000 fde5 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
--uxSchedulerSuspended;
|
|
800b5ee: 4b39 ldr r3, [pc, #228] @ (800b6d4 <xTaskResumeAll+0x118>)
|
|
800b5f0: 681b ldr r3, [r3, #0]
|
|
800b5f2: 3b01 subs r3, #1
|
|
800b5f4: 4a37 ldr r2, [pc, #220] @ (800b6d4 <xTaskResumeAll+0x118>)
|
|
800b5f6: 6013 str r3, [r2, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800b5f8: 4b36 ldr r3, [pc, #216] @ (800b6d4 <xTaskResumeAll+0x118>)
|
|
800b5fa: 681b ldr r3, [r3, #0]
|
|
800b5fc: 2b00 cmp r3, #0
|
|
800b5fe: d161 bne.n 800b6c4 <xTaskResumeAll+0x108>
|
|
{
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
|
800b600: 4b35 ldr r3, [pc, #212] @ (800b6d8 <xTaskResumeAll+0x11c>)
|
|
800b602: 681b ldr r3, [r3, #0]
|
|
800b604: 2b00 cmp r3, #0
|
|
800b606: d05d beq.n 800b6c4 <xTaskResumeAll+0x108>
|
|
{
|
|
/* Move any readied tasks from the pending list into the
|
|
appropriate ready list. */
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800b608: e02e b.n 800b668 <xTaskResumeAll+0xac>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800b60a: 4b34 ldr r3, [pc, #208] @ (800b6dc <xTaskResumeAll+0x120>)
|
|
800b60c: 68db ldr r3, [r3, #12]
|
|
800b60e: 68db ldr r3, [r3, #12]
|
|
800b610: 60fb str r3, [r7, #12]
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800b612: 68fb ldr r3, [r7, #12]
|
|
800b614: 3318 adds r3, #24
|
|
800b616: 4618 mov r0, r3
|
|
800b618: f7fe ffca bl 800a5b0 <uxListRemove>
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800b61c: 68fb ldr r3, [r7, #12]
|
|
800b61e: 3304 adds r3, #4
|
|
800b620: 4618 mov r0, r3
|
|
800b622: f7fe ffc5 bl 800a5b0 <uxListRemove>
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800b626: 68fb ldr r3, [r7, #12]
|
|
800b628: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b62a: 2201 movs r2, #1
|
|
800b62c: 409a lsls r2, r3
|
|
800b62e: 4b2c ldr r3, [pc, #176] @ (800b6e0 <xTaskResumeAll+0x124>)
|
|
800b630: 681b ldr r3, [r3, #0]
|
|
800b632: 4313 orrs r3, r2
|
|
800b634: 4a2a ldr r2, [pc, #168] @ (800b6e0 <xTaskResumeAll+0x124>)
|
|
800b636: 6013 str r3, [r2, #0]
|
|
800b638: 68fb ldr r3, [r7, #12]
|
|
800b63a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b63c: 4613 mov r3, r2
|
|
800b63e: 009b lsls r3, r3, #2
|
|
800b640: 4413 add r3, r2
|
|
800b642: 009b lsls r3, r3, #2
|
|
800b644: 4a27 ldr r2, [pc, #156] @ (800b6e4 <xTaskResumeAll+0x128>)
|
|
800b646: 441a add r2, r3
|
|
800b648: 68fb ldr r3, [r7, #12]
|
|
800b64a: 3304 adds r3, #4
|
|
800b64c: 4619 mov r1, r3
|
|
800b64e: 4610 mov r0, r2
|
|
800b650: f7fe ff51 bl 800a4f6 <vListInsertEnd>
|
|
|
|
/* If the moved task has a priority higher than the current
|
|
task then a yield must be performed. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800b654: 68fb ldr r3, [r7, #12]
|
|
800b656: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b658: 4b23 ldr r3, [pc, #140] @ (800b6e8 <xTaskResumeAll+0x12c>)
|
|
800b65a: 681b ldr r3, [r3, #0]
|
|
800b65c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b65e: 429a cmp r2, r3
|
|
800b660: d302 bcc.n 800b668 <xTaskResumeAll+0xac>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800b662: 4b22 ldr r3, [pc, #136] @ (800b6ec <xTaskResumeAll+0x130>)
|
|
800b664: 2201 movs r2, #1
|
|
800b666: 601a str r2, [r3, #0]
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
800b668: 4b1c ldr r3, [pc, #112] @ (800b6dc <xTaskResumeAll+0x120>)
|
|
800b66a: 681b ldr r3, [r3, #0]
|
|
800b66c: 2b00 cmp r3, #0
|
|
800b66e: d1cc bne.n 800b60a <xTaskResumeAll+0x4e>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( pxTCB != NULL )
|
|
800b670: 68fb ldr r3, [r7, #12]
|
|
800b672: 2b00 cmp r3, #0
|
|
800b674: d001 beq.n 800b67a <xTaskResumeAll+0xbe>
|
|
which may have prevented the next unblock time from being
|
|
re-calculated, in which case re-calculate it now. Mainly
|
|
important for low power tickless implementations, where
|
|
this can prevent an unnecessary exit from low power
|
|
state. */
|
|
prvResetNextTaskUnblockTime();
|
|
800b676: f000 fb43 bl 800bd00 <prvResetNextTaskUnblockTime>
|
|
/* If any ticks occurred while the scheduler was suspended then
|
|
they should be processed now. This ensures the tick count does
|
|
not slip, and that any delayed tasks are resumed at the correct
|
|
time. */
|
|
{
|
|
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
|
|
800b67a: 4b1d ldr r3, [pc, #116] @ (800b6f0 <xTaskResumeAll+0x134>)
|
|
800b67c: 681b ldr r3, [r3, #0]
|
|
800b67e: 607b str r3, [r7, #4]
|
|
|
|
if( xPendedCounts > ( TickType_t ) 0U )
|
|
800b680: 687b ldr r3, [r7, #4]
|
|
800b682: 2b00 cmp r3, #0
|
|
800b684: d010 beq.n 800b6a8 <xTaskResumeAll+0xec>
|
|
{
|
|
do
|
|
{
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800b686: f000 f837 bl 800b6f8 <xTaskIncrementTick>
|
|
800b68a: 4603 mov r3, r0
|
|
800b68c: 2b00 cmp r3, #0
|
|
800b68e: d002 beq.n 800b696 <xTaskResumeAll+0xda>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800b690: 4b16 ldr r3, [pc, #88] @ (800b6ec <xTaskResumeAll+0x130>)
|
|
800b692: 2201 movs r2, #1
|
|
800b694: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
--xPendedCounts;
|
|
800b696: 687b ldr r3, [r7, #4]
|
|
800b698: 3b01 subs r3, #1
|
|
800b69a: 607b str r3, [r7, #4]
|
|
} while( xPendedCounts > ( TickType_t ) 0U );
|
|
800b69c: 687b ldr r3, [r7, #4]
|
|
800b69e: 2b00 cmp r3, #0
|
|
800b6a0: d1f1 bne.n 800b686 <xTaskResumeAll+0xca>
|
|
|
|
xPendedTicks = 0;
|
|
800b6a2: 4b13 ldr r3, [pc, #76] @ (800b6f0 <xTaskResumeAll+0x134>)
|
|
800b6a4: 2200 movs r2, #0
|
|
800b6a6: 601a str r2, [r3, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( xYieldPending != pdFALSE )
|
|
800b6a8: 4b10 ldr r3, [pc, #64] @ (800b6ec <xTaskResumeAll+0x130>)
|
|
800b6aa: 681b ldr r3, [r3, #0]
|
|
800b6ac: 2b00 cmp r3, #0
|
|
800b6ae: d009 beq.n 800b6c4 <xTaskResumeAll+0x108>
|
|
{
|
|
#if( configUSE_PREEMPTION != 0 )
|
|
{
|
|
xAlreadyYielded = pdTRUE;
|
|
800b6b0: 2301 movs r3, #1
|
|
800b6b2: 60bb str r3, [r7, #8]
|
|
}
|
|
#endif
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800b6b4: 4b0f ldr r3, [pc, #60] @ (800b6f4 <xTaskResumeAll+0x138>)
|
|
800b6b6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800b6ba: 601a str r2, [r3, #0]
|
|
800b6bc: f3bf 8f4f dsb sy
|
|
800b6c0: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800b6c4: f000 fdaa bl 800c21c <vPortExitCritical>
|
|
|
|
return xAlreadyYielded;
|
|
800b6c8: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800b6ca: 4618 mov r0, r3
|
|
800b6cc: 3710 adds r7, #16
|
|
800b6ce: 46bd mov sp, r7
|
|
800b6d0: bd80 pop {r7, pc}
|
|
800b6d2: bf00 nop
|
|
800b6d4: 200006d4 .word 0x200006d4
|
|
800b6d8: 200006ac .word 0x200006ac
|
|
800b6dc: 2000066c .word 0x2000066c
|
|
800b6e0: 200006b4 .word 0x200006b4
|
|
800b6e4: 200005b0 .word 0x200005b0
|
|
800b6e8: 200005ac .word 0x200005ac
|
|
800b6ec: 200006c0 .word 0x200006c0
|
|
800b6f0: 200006bc .word 0x200006bc
|
|
800b6f4: e000ed04 .word 0xe000ed04
|
|
|
|
0800b6f8 <xTaskIncrementTick>:
|
|
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskIncrementTick( void )
|
|
{
|
|
800b6f8: b580 push {r7, lr}
|
|
800b6fa: b086 sub sp, #24
|
|
800b6fc: af00 add r7, sp, #0
|
|
TCB_t * pxTCB;
|
|
TickType_t xItemValue;
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
|
800b6fe: 2300 movs r3, #0
|
|
800b700: 617b str r3, [r7, #20]
|
|
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
|
Increments the tick then checks to see if the new tick value will cause any
|
|
tasks to be unblocked. */
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800b702: 4b4f ldr r3, [pc, #316] @ (800b840 <xTaskIncrementTick+0x148>)
|
|
800b704: 681b ldr r3, [r3, #0]
|
|
800b706: 2b00 cmp r3, #0
|
|
800b708: f040 808f bne.w 800b82a <xTaskIncrementTick+0x132>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
block. */
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
|
800b70c: 4b4d ldr r3, [pc, #308] @ (800b844 <xTaskIncrementTick+0x14c>)
|
|
800b70e: 681b ldr r3, [r3, #0]
|
|
800b710: 3301 adds r3, #1
|
|
800b712: 613b str r3, [r7, #16]
|
|
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
|
delayed lists if it wraps to 0. */
|
|
xTickCount = xConstTickCount;
|
|
800b714: 4a4b ldr r2, [pc, #300] @ (800b844 <xTaskIncrementTick+0x14c>)
|
|
800b716: 693b ldr r3, [r7, #16]
|
|
800b718: 6013 str r3, [r2, #0]
|
|
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
|
800b71a: 693b ldr r3, [r7, #16]
|
|
800b71c: 2b00 cmp r3, #0
|
|
800b71e: d121 bne.n 800b764 <xTaskIncrementTick+0x6c>
|
|
{
|
|
taskSWITCH_DELAYED_LISTS();
|
|
800b720: 4b49 ldr r3, [pc, #292] @ (800b848 <xTaskIncrementTick+0x150>)
|
|
800b722: 681b ldr r3, [r3, #0]
|
|
800b724: 681b ldr r3, [r3, #0]
|
|
800b726: 2b00 cmp r3, #0
|
|
800b728: d00b beq.n 800b742 <xTaskIncrementTick+0x4a>
|
|
__asm volatile
|
|
800b72a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b72e: f383 8811 msr BASEPRI, r3
|
|
800b732: f3bf 8f6f isb sy
|
|
800b736: f3bf 8f4f dsb sy
|
|
800b73a: 603b str r3, [r7, #0]
|
|
}
|
|
800b73c: bf00 nop
|
|
800b73e: bf00 nop
|
|
800b740: e7fd b.n 800b73e <xTaskIncrementTick+0x46>
|
|
800b742: 4b41 ldr r3, [pc, #260] @ (800b848 <xTaskIncrementTick+0x150>)
|
|
800b744: 681b ldr r3, [r3, #0]
|
|
800b746: 60fb str r3, [r7, #12]
|
|
800b748: 4b40 ldr r3, [pc, #256] @ (800b84c <xTaskIncrementTick+0x154>)
|
|
800b74a: 681b ldr r3, [r3, #0]
|
|
800b74c: 4a3e ldr r2, [pc, #248] @ (800b848 <xTaskIncrementTick+0x150>)
|
|
800b74e: 6013 str r3, [r2, #0]
|
|
800b750: 4a3e ldr r2, [pc, #248] @ (800b84c <xTaskIncrementTick+0x154>)
|
|
800b752: 68fb ldr r3, [r7, #12]
|
|
800b754: 6013 str r3, [r2, #0]
|
|
800b756: 4b3e ldr r3, [pc, #248] @ (800b850 <xTaskIncrementTick+0x158>)
|
|
800b758: 681b ldr r3, [r3, #0]
|
|
800b75a: 3301 adds r3, #1
|
|
800b75c: 4a3c ldr r2, [pc, #240] @ (800b850 <xTaskIncrementTick+0x158>)
|
|
800b75e: 6013 str r3, [r2, #0]
|
|
800b760: f000 face bl 800bd00 <prvResetNextTaskUnblockTime>
|
|
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
|
the queue in the order of their wake time - meaning once one task
|
|
has been found whose block time has not expired there is no need to
|
|
look any further down the list. */
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
|
800b764: 4b3b ldr r3, [pc, #236] @ (800b854 <xTaskIncrementTick+0x15c>)
|
|
800b766: 681b ldr r3, [r3, #0]
|
|
800b768: 693a ldr r2, [r7, #16]
|
|
800b76a: 429a cmp r2, r3
|
|
800b76c: d348 bcc.n 800b800 <xTaskIncrementTick+0x108>
|
|
{
|
|
for( ;; )
|
|
{
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800b76e: 4b36 ldr r3, [pc, #216] @ (800b848 <xTaskIncrementTick+0x150>)
|
|
800b770: 681b ldr r3, [r3, #0]
|
|
800b772: 681b ldr r3, [r3, #0]
|
|
800b774: 2b00 cmp r3, #0
|
|
800b776: d104 bne.n 800b782 <xTaskIncrementTick+0x8a>
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
|
to the maximum possible value so it is extremely
|
|
unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
|
next time through. */
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800b778: 4b36 ldr r3, [pc, #216] @ (800b854 <xTaskIncrementTick+0x15c>)
|
|
800b77a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800b77e: 601a str r2, [r3, #0]
|
|
break;
|
|
800b780: e03e b.n 800b800 <xTaskIncrementTick+0x108>
|
|
{
|
|
/* The delayed list is not empty, get the value of the
|
|
item at the head of the delayed list. This is the time
|
|
at which the task at the head of the delayed list must
|
|
be removed from the Blocked state. */
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800b782: 4b31 ldr r3, [pc, #196] @ (800b848 <xTaskIncrementTick+0x150>)
|
|
800b784: 681b ldr r3, [r3, #0]
|
|
800b786: 68db ldr r3, [r3, #12]
|
|
800b788: 68db ldr r3, [r3, #12]
|
|
800b78a: 60bb str r3, [r7, #8]
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
|
800b78c: 68bb ldr r3, [r7, #8]
|
|
800b78e: 685b ldr r3, [r3, #4]
|
|
800b790: 607b str r3, [r7, #4]
|
|
|
|
if( xConstTickCount < xItemValue )
|
|
800b792: 693a ldr r2, [r7, #16]
|
|
800b794: 687b ldr r3, [r7, #4]
|
|
800b796: 429a cmp r2, r3
|
|
800b798: d203 bcs.n 800b7a2 <xTaskIncrementTick+0xaa>
|
|
/* It is not time to unblock this item yet, but the
|
|
item value is the time at which the task at the head
|
|
of the blocked list must be removed from the Blocked
|
|
state - so record the item value in
|
|
xNextTaskUnblockTime. */
|
|
xNextTaskUnblockTime = xItemValue;
|
|
800b79a: 4a2e ldr r2, [pc, #184] @ (800b854 <xTaskIncrementTick+0x15c>)
|
|
800b79c: 687b ldr r3, [r7, #4]
|
|
800b79e: 6013 str r3, [r2, #0]
|
|
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
|
|
800b7a0: e02e b.n 800b800 <xTaskIncrementTick+0x108>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* It is time to remove the item from the Blocked state. */
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800b7a2: 68bb ldr r3, [r7, #8]
|
|
800b7a4: 3304 adds r3, #4
|
|
800b7a6: 4618 mov r0, r3
|
|
800b7a8: f7fe ff02 bl 800a5b0 <uxListRemove>
|
|
|
|
/* Is the task waiting on an event also? If so remove
|
|
it from the event list. */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
800b7ac: 68bb ldr r3, [r7, #8]
|
|
800b7ae: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800b7b0: 2b00 cmp r3, #0
|
|
800b7b2: d004 beq.n 800b7be <xTaskIncrementTick+0xc6>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800b7b4: 68bb ldr r3, [r7, #8]
|
|
800b7b6: 3318 adds r3, #24
|
|
800b7b8: 4618 mov r0, r3
|
|
800b7ba: f7fe fef9 bl 800a5b0 <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Place the unblocked task into the appropriate ready
|
|
list. */
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800b7be: 68bb ldr r3, [r7, #8]
|
|
800b7c0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b7c2: 2201 movs r2, #1
|
|
800b7c4: 409a lsls r2, r3
|
|
800b7c6: 4b24 ldr r3, [pc, #144] @ (800b858 <xTaskIncrementTick+0x160>)
|
|
800b7c8: 681b ldr r3, [r3, #0]
|
|
800b7ca: 4313 orrs r3, r2
|
|
800b7cc: 4a22 ldr r2, [pc, #136] @ (800b858 <xTaskIncrementTick+0x160>)
|
|
800b7ce: 6013 str r3, [r2, #0]
|
|
800b7d0: 68bb ldr r3, [r7, #8]
|
|
800b7d2: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b7d4: 4613 mov r3, r2
|
|
800b7d6: 009b lsls r3, r3, #2
|
|
800b7d8: 4413 add r3, r2
|
|
800b7da: 009b lsls r3, r3, #2
|
|
800b7dc: 4a1f ldr r2, [pc, #124] @ (800b85c <xTaskIncrementTick+0x164>)
|
|
800b7de: 441a add r2, r3
|
|
800b7e0: 68bb ldr r3, [r7, #8]
|
|
800b7e2: 3304 adds r3, #4
|
|
800b7e4: 4619 mov r1, r3
|
|
800b7e6: 4610 mov r0, r2
|
|
800b7e8: f7fe fe85 bl 800a4f6 <vListInsertEnd>
|
|
{
|
|
/* Preemption is on, but a context switch should
|
|
only be performed if the unblocked task has a
|
|
priority that is equal to or higher than the
|
|
currently executing task. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800b7ec: 68bb ldr r3, [r7, #8]
|
|
800b7ee: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b7f0: 4b1b ldr r3, [pc, #108] @ (800b860 <xTaskIncrementTick+0x168>)
|
|
800b7f2: 681b ldr r3, [r3, #0]
|
|
800b7f4: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800b7f6: 429a cmp r2, r3
|
|
800b7f8: d3b9 bcc.n 800b76e <xTaskIncrementTick+0x76>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800b7fa: 2301 movs r3, #1
|
|
800b7fc: 617b str r3, [r7, #20]
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800b7fe: e7b6 b.n 800b76e <xTaskIncrementTick+0x76>
|
|
/* Tasks of equal priority to the currently running task will share
|
|
processing time (time slice) if preemption is on, and the application
|
|
writer has not explicitly turned time slicing off. */
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
|
{
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
|
800b800: 4b17 ldr r3, [pc, #92] @ (800b860 <xTaskIncrementTick+0x168>)
|
|
800b802: 681b ldr r3, [r3, #0]
|
|
800b804: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800b806: 4915 ldr r1, [pc, #84] @ (800b85c <xTaskIncrementTick+0x164>)
|
|
800b808: 4613 mov r3, r2
|
|
800b80a: 009b lsls r3, r3, #2
|
|
800b80c: 4413 add r3, r2
|
|
800b80e: 009b lsls r3, r3, #2
|
|
800b810: 440b add r3, r1
|
|
800b812: 681b ldr r3, [r3, #0]
|
|
800b814: 2b01 cmp r3, #1
|
|
800b816: d901 bls.n 800b81c <xTaskIncrementTick+0x124>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800b818: 2301 movs r3, #1
|
|
800b81a: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* configUSE_TICK_HOOK */
|
|
|
|
#if ( configUSE_PREEMPTION == 1 )
|
|
{
|
|
if( xYieldPending != pdFALSE )
|
|
800b81c: 4b11 ldr r3, [pc, #68] @ (800b864 <xTaskIncrementTick+0x16c>)
|
|
800b81e: 681b ldr r3, [r3, #0]
|
|
800b820: 2b00 cmp r3, #0
|
|
800b822: d007 beq.n 800b834 <xTaskIncrementTick+0x13c>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800b824: 2301 movs r3, #1
|
|
800b826: 617b str r3, [r7, #20]
|
|
800b828: e004 b.n 800b834 <xTaskIncrementTick+0x13c>
|
|
}
|
|
#endif /* configUSE_PREEMPTION */
|
|
}
|
|
else
|
|
{
|
|
++xPendedTicks;
|
|
800b82a: 4b0f ldr r3, [pc, #60] @ (800b868 <xTaskIncrementTick+0x170>)
|
|
800b82c: 681b ldr r3, [r3, #0]
|
|
800b82e: 3301 adds r3, #1
|
|
800b830: 4a0d ldr r2, [pc, #52] @ (800b868 <xTaskIncrementTick+0x170>)
|
|
800b832: 6013 str r3, [r2, #0]
|
|
vApplicationTickHook();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return xSwitchRequired;
|
|
800b834: 697b ldr r3, [r7, #20]
|
|
}
|
|
800b836: 4618 mov r0, r3
|
|
800b838: 3718 adds r7, #24
|
|
800b83a: 46bd mov sp, r7
|
|
800b83c: bd80 pop {r7, pc}
|
|
800b83e: bf00 nop
|
|
800b840: 200006d4 .word 0x200006d4
|
|
800b844: 200006b0 .word 0x200006b0
|
|
800b848: 20000664 .word 0x20000664
|
|
800b84c: 20000668 .word 0x20000668
|
|
800b850: 200006c4 .word 0x200006c4
|
|
800b854: 200006cc .word 0x200006cc
|
|
800b858: 200006b4 .word 0x200006b4
|
|
800b85c: 200005b0 .word 0x200005b0
|
|
800b860: 200005ac .word 0x200005ac
|
|
800b864: 200006c0 .word 0x200006c0
|
|
800b868: 200006bc .word 0x200006bc
|
|
|
|
0800b86c <vTaskSwitchContext>:
|
|
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskSwitchContext( void )
|
|
{
|
|
800b86c: b580 push {r7, lr}
|
|
800b86e: b088 sub sp, #32
|
|
800b870: af00 add r7, sp, #0
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
|
|
800b872: 4b3a ldr r3, [pc, #232] @ (800b95c <vTaskSwitchContext+0xf0>)
|
|
800b874: 681b ldr r3, [r3, #0]
|
|
800b876: 2b00 cmp r3, #0
|
|
800b878: d003 beq.n 800b882 <vTaskSwitchContext+0x16>
|
|
{
|
|
/* The scheduler is currently suspended - do not allow a context
|
|
switch. */
|
|
xYieldPending = pdTRUE;
|
|
800b87a: 4b39 ldr r3, [pc, #228] @ (800b960 <vTaskSwitchContext+0xf4>)
|
|
800b87c: 2201 movs r2, #1
|
|
800b87e: 601a str r2, [r3, #0]
|
|
for additional information. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
}
|
|
}
|
|
800b880: e067 b.n 800b952 <vTaskSwitchContext+0xe6>
|
|
xYieldPending = pdFALSE;
|
|
800b882: 4b37 ldr r3, [pc, #220] @ (800b960 <vTaskSwitchContext+0xf4>)
|
|
800b884: 2200 movs r2, #0
|
|
800b886: 601a str r2, [r3, #0]
|
|
taskCHECK_FOR_STACK_OVERFLOW();
|
|
800b888: 4b36 ldr r3, [pc, #216] @ (800b964 <vTaskSwitchContext+0xf8>)
|
|
800b88a: 681b ldr r3, [r3, #0]
|
|
800b88c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800b88e: 61fb str r3, [r7, #28]
|
|
800b890: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5
|
|
800b894: 61bb str r3, [r7, #24]
|
|
800b896: 69fb ldr r3, [r7, #28]
|
|
800b898: 681b ldr r3, [r3, #0]
|
|
800b89a: 69ba ldr r2, [r7, #24]
|
|
800b89c: 429a cmp r2, r3
|
|
800b89e: d111 bne.n 800b8c4 <vTaskSwitchContext+0x58>
|
|
800b8a0: 69fb ldr r3, [r7, #28]
|
|
800b8a2: 3304 adds r3, #4
|
|
800b8a4: 681b ldr r3, [r3, #0]
|
|
800b8a6: 69ba ldr r2, [r7, #24]
|
|
800b8a8: 429a cmp r2, r3
|
|
800b8aa: d10b bne.n 800b8c4 <vTaskSwitchContext+0x58>
|
|
800b8ac: 69fb ldr r3, [r7, #28]
|
|
800b8ae: 3308 adds r3, #8
|
|
800b8b0: 681b ldr r3, [r3, #0]
|
|
800b8b2: 69ba ldr r2, [r7, #24]
|
|
800b8b4: 429a cmp r2, r3
|
|
800b8b6: d105 bne.n 800b8c4 <vTaskSwitchContext+0x58>
|
|
800b8b8: 69fb ldr r3, [r7, #28]
|
|
800b8ba: 330c adds r3, #12
|
|
800b8bc: 681b ldr r3, [r3, #0]
|
|
800b8be: 69ba ldr r2, [r7, #24]
|
|
800b8c0: 429a cmp r2, r3
|
|
800b8c2: d008 beq.n 800b8d6 <vTaskSwitchContext+0x6a>
|
|
800b8c4: 4b27 ldr r3, [pc, #156] @ (800b964 <vTaskSwitchContext+0xf8>)
|
|
800b8c6: 681a ldr r2, [r3, #0]
|
|
800b8c8: 4b26 ldr r3, [pc, #152] @ (800b964 <vTaskSwitchContext+0xf8>)
|
|
800b8ca: 681b ldr r3, [r3, #0]
|
|
800b8cc: 3334 adds r3, #52 @ 0x34
|
|
800b8ce: 4619 mov r1, r3
|
|
800b8d0: 4610 mov r0, r2
|
|
800b8d2: f7f4 fe2a bl 800052a <vApplicationStackOverflowHook>
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800b8d6: 4b24 ldr r3, [pc, #144] @ (800b968 <vTaskSwitchContext+0xfc>)
|
|
800b8d8: 681b ldr r3, [r3, #0]
|
|
800b8da: 60fb str r3, [r7, #12]
|
|
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
|
800b8dc: 68fb ldr r3, [r7, #12]
|
|
800b8de: fab3 f383 clz r3, r3
|
|
800b8e2: 72fb strb r3, [r7, #11]
|
|
return ucReturn;
|
|
800b8e4: 7afb ldrb r3, [r7, #11]
|
|
800b8e6: f1c3 031f rsb r3, r3, #31
|
|
800b8ea: 617b str r3, [r7, #20]
|
|
800b8ec: 491f ldr r1, [pc, #124] @ (800b96c <vTaskSwitchContext+0x100>)
|
|
800b8ee: 697a ldr r2, [r7, #20]
|
|
800b8f0: 4613 mov r3, r2
|
|
800b8f2: 009b lsls r3, r3, #2
|
|
800b8f4: 4413 add r3, r2
|
|
800b8f6: 009b lsls r3, r3, #2
|
|
800b8f8: 440b add r3, r1
|
|
800b8fa: 681b ldr r3, [r3, #0]
|
|
800b8fc: 2b00 cmp r3, #0
|
|
800b8fe: d10b bne.n 800b918 <vTaskSwitchContext+0xac>
|
|
__asm volatile
|
|
800b900: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b904: f383 8811 msr BASEPRI, r3
|
|
800b908: f3bf 8f6f isb sy
|
|
800b90c: f3bf 8f4f dsb sy
|
|
800b910: 607b str r3, [r7, #4]
|
|
}
|
|
800b912: bf00 nop
|
|
800b914: bf00 nop
|
|
800b916: e7fd b.n 800b914 <vTaskSwitchContext+0xa8>
|
|
800b918: 697a ldr r2, [r7, #20]
|
|
800b91a: 4613 mov r3, r2
|
|
800b91c: 009b lsls r3, r3, #2
|
|
800b91e: 4413 add r3, r2
|
|
800b920: 009b lsls r3, r3, #2
|
|
800b922: 4a12 ldr r2, [pc, #72] @ (800b96c <vTaskSwitchContext+0x100>)
|
|
800b924: 4413 add r3, r2
|
|
800b926: 613b str r3, [r7, #16]
|
|
800b928: 693b ldr r3, [r7, #16]
|
|
800b92a: 685b ldr r3, [r3, #4]
|
|
800b92c: 685a ldr r2, [r3, #4]
|
|
800b92e: 693b ldr r3, [r7, #16]
|
|
800b930: 605a str r2, [r3, #4]
|
|
800b932: 693b ldr r3, [r7, #16]
|
|
800b934: 685a ldr r2, [r3, #4]
|
|
800b936: 693b ldr r3, [r7, #16]
|
|
800b938: 3308 adds r3, #8
|
|
800b93a: 429a cmp r2, r3
|
|
800b93c: d104 bne.n 800b948 <vTaskSwitchContext+0xdc>
|
|
800b93e: 693b ldr r3, [r7, #16]
|
|
800b940: 685b ldr r3, [r3, #4]
|
|
800b942: 685a ldr r2, [r3, #4]
|
|
800b944: 693b ldr r3, [r7, #16]
|
|
800b946: 605a str r2, [r3, #4]
|
|
800b948: 693b ldr r3, [r7, #16]
|
|
800b94a: 685b ldr r3, [r3, #4]
|
|
800b94c: 68db ldr r3, [r3, #12]
|
|
800b94e: 4a05 ldr r2, [pc, #20] @ (800b964 <vTaskSwitchContext+0xf8>)
|
|
800b950: 6013 str r3, [r2, #0]
|
|
}
|
|
800b952: bf00 nop
|
|
800b954: 3720 adds r7, #32
|
|
800b956: 46bd mov sp, r7
|
|
800b958: bd80 pop {r7, pc}
|
|
800b95a: bf00 nop
|
|
800b95c: 200006d4 .word 0x200006d4
|
|
800b960: 200006c0 .word 0x200006c0
|
|
800b964: 200005ac .word 0x200005ac
|
|
800b968: 200006b4 .word 0x200006b4
|
|
800b96c: 200005b0 .word 0x200005b0
|
|
|
|
0800b970 <vTaskPlaceOnEventList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
|
|
{
|
|
800b970: b580 push {r7, lr}
|
|
800b972: b084 sub sp, #16
|
|
800b974: af00 add r7, sp, #0
|
|
800b976: 6078 str r0, [r7, #4]
|
|
800b978: 6039 str r1, [r7, #0]
|
|
configASSERT( pxEventList );
|
|
800b97a: 687b ldr r3, [r7, #4]
|
|
800b97c: 2b00 cmp r3, #0
|
|
800b97e: d10b bne.n 800b998 <vTaskPlaceOnEventList+0x28>
|
|
__asm volatile
|
|
800b980: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b984: f383 8811 msr BASEPRI, r3
|
|
800b988: f3bf 8f6f isb sy
|
|
800b98c: f3bf 8f4f dsb sy
|
|
800b990: 60fb str r3, [r7, #12]
|
|
}
|
|
800b992: bf00 nop
|
|
800b994: bf00 nop
|
|
800b996: e7fd b.n 800b994 <vTaskPlaceOnEventList+0x24>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
This is placed in the list in priority order so the highest priority task
|
|
is the first to be woken by the event. The queue that contains the event
|
|
list is locked, preventing simultaneous access from interrupts. */
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
800b998: 4b07 ldr r3, [pc, #28] @ (800b9b8 <vTaskPlaceOnEventList+0x48>)
|
|
800b99a: 681b ldr r3, [r3, #0]
|
|
800b99c: 3318 adds r3, #24
|
|
800b99e: 4619 mov r1, r3
|
|
800b9a0: 6878 ldr r0, [r7, #4]
|
|
800b9a2: f7fe fdcc bl 800a53e <vListInsert>
|
|
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
800b9a6: 2101 movs r1, #1
|
|
800b9a8: 6838 ldr r0, [r7, #0]
|
|
800b9aa: f000 fa6f bl 800be8c <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
800b9ae: bf00 nop
|
|
800b9b0: 3710 adds r7, #16
|
|
800b9b2: 46bd mov sp, r7
|
|
800b9b4: bd80 pop {r7, pc}
|
|
800b9b6: bf00 nop
|
|
800b9b8: 200005ac .word 0x200005ac
|
|
|
|
0800b9bc <xTaskRemoveFromEventList>:
|
|
|
|
#endif /* configUSE_TIMERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
|
{
|
|
800b9bc: b580 push {r7, lr}
|
|
800b9be: b086 sub sp, #24
|
|
800b9c0: af00 add r7, sp, #0
|
|
800b9c2: 6078 str r0, [r7, #4]
|
|
get called - the lock count on the queue will get modified instead. This
|
|
means exclusive access to the event list is guaranteed here.
|
|
|
|
This function assumes that a check has already been made to ensure that
|
|
pxEventList is not empty. */
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800b9c4: 687b ldr r3, [r7, #4]
|
|
800b9c6: 68db ldr r3, [r3, #12]
|
|
800b9c8: 68db ldr r3, [r3, #12]
|
|
800b9ca: 613b str r3, [r7, #16]
|
|
configASSERT( pxUnblockedTCB );
|
|
800b9cc: 693b ldr r3, [r7, #16]
|
|
800b9ce: 2b00 cmp r3, #0
|
|
800b9d0: d10b bne.n 800b9ea <xTaskRemoveFromEventList+0x2e>
|
|
__asm volatile
|
|
800b9d2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800b9d6: f383 8811 msr BASEPRI, r3
|
|
800b9da: f3bf 8f6f isb sy
|
|
800b9de: f3bf 8f4f dsb sy
|
|
800b9e2: 60fb str r3, [r7, #12]
|
|
}
|
|
800b9e4: bf00 nop
|
|
800b9e6: bf00 nop
|
|
800b9e8: e7fd b.n 800b9e6 <xTaskRemoveFromEventList+0x2a>
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
|
|
800b9ea: 693b ldr r3, [r7, #16]
|
|
800b9ec: 3318 adds r3, #24
|
|
800b9ee: 4618 mov r0, r3
|
|
800b9f0: f7fe fdde bl 800a5b0 <uxListRemove>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800b9f4: 4b1d ldr r3, [pc, #116] @ (800ba6c <xTaskRemoveFromEventList+0xb0>)
|
|
800b9f6: 681b ldr r3, [r3, #0]
|
|
800b9f8: 2b00 cmp r3, #0
|
|
800b9fa: d11c bne.n 800ba36 <xTaskRemoveFromEventList+0x7a>
|
|
{
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
|
|
800b9fc: 693b ldr r3, [r7, #16]
|
|
800b9fe: 3304 adds r3, #4
|
|
800ba00: 4618 mov r0, r3
|
|
800ba02: f7fe fdd5 bl 800a5b0 <uxListRemove>
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
|
800ba06: 693b ldr r3, [r7, #16]
|
|
800ba08: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800ba0a: 2201 movs r2, #1
|
|
800ba0c: 409a lsls r2, r3
|
|
800ba0e: 4b18 ldr r3, [pc, #96] @ (800ba70 <xTaskRemoveFromEventList+0xb4>)
|
|
800ba10: 681b ldr r3, [r3, #0]
|
|
800ba12: 4313 orrs r3, r2
|
|
800ba14: 4a16 ldr r2, [pc, #88] @ (800ba70 <xTaskRemoveFromEventList+0xb4>)
|
|
800ba16: 6013 str r3, [r2, #0]
|
|
800ba18: 693b ldr r3, [r7, #16]
|
|
800ba1a: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800ba1c: 4613 mov r3, r2
|
|
800ba1e: 009b lsls r3, r3, #2
|
|
800ba20: 4413 add r3, r2
|
|
800ba22: 009b lsls r3, r3, #2
|
|
800ba24: 4a13 ldr r2, [pc, #76] @ (800ba74 <xTaskRemoveFromEventList+0xb8>)
|
|
800ba26: 441a add r2, r3
|
|
800ba28: 693b ldr r3, [r7, #16]
|
|
800ba2a: 3304 adds r3, #4
|
|
800ba2c: 4619 mov r1, r3
|
|
800ba2e: 4610 mov r0, r2
|
|
800ba30: f7fe fd61 bl 800a4f6 <vListInsertEnd>
|
|
800ba34: e005 b.n 800ba42 <xTaskRemoveFromEventList+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
|
pending until the scheduler is resumed. */
|
|
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
|
800ba36: 693b ldr r3, [r7, #16]
|
|
800ba38: 3318 adds r3, #24
|
|
800ba3a: 4619 mov r1, r3
|
|
800ba3c: 480e ldr r0, [pc, #56] @ (800ba78 <xTaskRemoveFromEventList+0xbc>)
|
|
800ba3e: f7fe fd5a bl 800a4f6 <vListInsertEnd>
|
|
}
|
|
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
800ba42: 693b ldr r3, [r7, #16]
|
|
800ba44: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800ba46: 4b0d ldr r3, [pc, #52] @ (800ba7c <xTaskRemoveFromEventList+0xc0>)
|
|
800ba48: 681b ldr r3, [r3, #0]
|
|
800ba4a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800ba4c: 429a cmp r2, r3
|
|
800ba4e: d905 bls.n 800ba5c <xTaskRemoveFromEventList+0xa0>
|
|
{
|
|
/* Return true if the task removed from the event list has a higher
|
|
priority than the calling task. This allows the calling task to know if
|
|
it should force a context switch now. */
|
|
xReturn = pdTRUE;
|
|
800ba50: 2301 movs r3, #1
|
|
800ba52: 617b str r3, [r7, #20]
|
|
|
|
/* Mark that a yield is pending in case the user is not using the
|
|
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
800ba54: 4b0a ldr r3, [pc, #40] @ (800ba80 <xTaskRemoveFromEventList+0xc4>)
|
|
800ba56: 2201 movs r2, #1
|
|
800ba58: 601a str r2, [r3, #0]
|
|
800ba5a: e001 b.n 800ba60 <xTaskRemoveFromEventList+0xa4>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
800ba5c: 2300 movs r3, #0
|
|
800ba5e: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
800ba60: 697b ldr r3, [r7, #20]
|
|
}
|
|
800ba62: 4618 mov r0, r3
|
|
800ba64: 3718 adds r7, #24
|
|
800ba66: 46bd mov sp, r7
|
|
800ba68: bd80 pop {r7, pc}
|
|
800ba6a: bf00 nop
|
|
800ba6c: 200006d4 .word 0x200006d4
|
|
800ba70: 200006b4 .word 0x200006b4
|
|
800ba74: 200005b0 .word 0x200005b0
|
|
800ba78: 2000066c .word 0x2000066c
|
|
800ba7c: 200005ac .word 0x200005ac
|
|
800ba80: 200006c0 .word 0x200006c0
|
|
|
|
0800ba84 <vTaskInternalSetTimeOutState>:
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
|
{
|
|
800ba84: b480 push {r7}
|
|
800ba86: b083 sub sp, #12
|
|
800ba88: af00 add r7, sp, #0
|
|
800ba8a: 6078 str r0, [r7, #4]
|
|
/* For internal use only as it does not use a critical section. */
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
|
800ba8c: 4b06 ldr r3, [pc, #24] @ (800baa8 <vTaskInternalSetTimeOutState+0x24>)
|
|
800ba8e: 681a ldr r2, [r3, #0]
|
|
800ba90: 687b ldr r3, [r7, #4]
|
|
800ba92: 601a str r2, [r3, #0]
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
|
800ba94: 4b05 ldr r3, [pc, #20] @ (800baac <vTaskInternalSetTimeOutState+0x28>)
|
|
800ba96: 681a ldr r2, [r3, #0]
|
|
800ba98: 687b ldr r3, [r7, #4]
|
|
800ba9a: 605a str r2, [r3, #4]
|
|
}
|
|
800ba9c: bf00 nop
|
|
800ba9e: 370c adds r7, #12
|
|
800baa0: 46bd mov sp, r7
|
|
800baa2: f85d 7b04 ldr.w r7, [sp], #4
|
|
800baa6: 4770 bx lr
|
|
800baa8: 200006c4 .word 0x200006c4
|
|
800baac: 200006b0 .word 0x200006b0
|
|
|
|
0800bab0 <xTaskCheckForTimeOut>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
|
|
{
|
|
800bab0: b580 push {r7, lr}
|
|
800bab2: b088 sub sp, #32
|
|
800bab4: af00 add r7, sp, #0
|
|
800bab6: 6078 str r0, [r7, #4]
|
|
800bab8: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( pxTimeOut );
|
|
800baba: 687b ldr r3, [r7, #4]
|
|
800babc: 2b00 cmp r3, #0
|
|
800babe: d10b bne.n 800bad8 <xTaskCheckForTimeOut+0x28>
|
|
__asm volatile
|
|
800bac0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bac4: f383 8811 msr BASEPRI, r3
|
|
800bac8: f3bf 8f6f isb sy
|
|
800bacc: f3bf 8f4f dsb sy
|
|
800bad0: 613b str r3, [r7, #16]
|
|
}
|
|
800bad2: bf00 nop
|
|
800bad4: bf00 nop
|
|
800bad6: e7fd b.n 800bad4 <xTaskCheckForTimeOut+0x24>
|
|
configASSERT( pxTicksToWait );
|
|
800bad8: 683b ldr r3, [r7, #0]
|
|
800bada: 2b00 cmp r3, #0
|
|
800badc: d10b bne.n 800baf6 <xTaskCheckForTimeOut+0x46>
|
|
__asm volatile
|
|
800bade: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bae2: f383 8811 msr BASEPRI, r3
|
|
800bae6: f3bf 8f6f isb sy
|
|
800baea: f3bf 8f4f dsb sy
|
|
800baee: 60fb str r3, [r7, #12]
|
|
}
|
|
800baf0: bf00 nop
|
|
800baf2: bf00 nop
|
|
800baf4: e7fd b.n 800baf2 <xTaskCheckForTimeOut+0x42>
|
|
|
|
taskENTER_CRITICAL();
|
|
800baf6: f000 fb5f bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800bafa: 4b1d ldr r3, [pc, #116] @ (800bb70 <xTaskCheckForTimeOut+0xc0>)
|
|
800bafc: 681b ldr r3, [r3, #0]
|
|
800bafe: 61bb str r3, [r7, #24]
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
|
800bb00: 687b ldr r3, [r7, #4]
|
|
800bb02: 685b ldr r3, [r3, #4]
|
|
800bb04: 69ba ldr r2, [r7, #24]
|
|
800bb06: 1ad3 subs r3, r2, r3
|
|
800bb08: 617b str r3, [r7, #20]
|
|
}
|
|
else
|
|
#endif
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
|
800bb0a: 683b ldr r3, [r7, #0]
|
|
800bb0c: 681b ldr r3, [r3, #0]
|
|
800bb0e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800bb12: d102 bne.n 800bb1a <xTaskCheckForTimeOut+0x6a>
|
|
{
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
|
specified is the maximum block time then the task should block
|
|
indefinitely, and therefore never time out. */
|
|
xReturn = pdFALSE;
|
|
800bb14: 2300 movs r3, #0
|
|
800bb16: 61fb str r3, [r7, #28]
|
|
800bb18: e023 b.n 800bb62 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
#endif
|
|
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
|
800bb1a: 687b ldr r3, [r7, #4]
|
|
800bb1c: 681a ldr r2, [r3, #0]
|
|
800bb1e: 4b15 ldr r3, [pc, #84] @ (800bb74 <xTaskCheckForTimeOut+0xc4>)
|
|
800bb20: 681b ldr r3, [r3, #0]
|
|
800bb22: 429a cmp r2, r3
|
|
800bb24: d007 beq.n 800bb36 <xTaskCheckForTimeOut+0x86>
|
|
800bb26: 687b ldr r3, [r7, #4]
|
|
800bb28: 685b ldr r3, [r3, #4]
|
|
800bb2a: 69ba ldr r2, [r7, #24]
|
|
800bb2c: 429a cmp r2, r3
|
|
800bb2e: d302 bcc.n 800bb36 <xTaskCheckForTimeOut+0x86>
|
|
/* The tick count is greater than the time at which
|
|
vTaskSetTimeout() was called, but has also overflowed since
|
|
vTaskSetTimeOut() was called. It must have wrapped all the way
|
|
around and gone past again. This passed since vTaskSetTimeout()
|
|
was called. */
|
|
xReturn = pdTRUE;
|
|
800bb30: 2301 movs r3, #1
|
|
800bb32: 61fb str r3, [r7, #28]
|
|
800bb34: e015 b.n 800bb62 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
|
800bb36: 683b ldr r3, [r7, #0]
|
|
800bb38: 681b ldr r3, [r3, #0]
|
|
800bb3a: 697a ldr r2, [r7, #20]
|
|
800bb3c: 429a cmp r2, r3
|
|
800bb3e: d20b bcs.n 800bb58 <xTaskCheckForTimeOut+0xa8>
|
|
{
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
|
*pxTicksToWait -= xElapsedTime;
|
|
800bb40: 683b ldr r3, [r7, #0]
|
|
800bb42: 681a ldr r2, [r3, #0]
|
|
800bb44: 697b ldr r3, [r7, #20]
|
|
800bb46: 1ad2 subs r2, r2, r3
|
|
800bb48: 683b ldr r3, [r7, #0]
|
|
800bb4a: 601a str r2, [r3, #0]
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
|
800bb4c: 6878 ldr r0, [r7, #4]
|
|
800bb4e: f7ff ff99 bl 800ba84 <vTaskInternalSetTimeOutState>
|
|
xReturn = pdFALSE;
|
|
800bb52: 2300 movs r3, #0
|
|
800bb54: 61fb str r3, [r7, #28]
|
|
800bb56: e004 b.n 800bb62 <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
{
|
|
*pxTicksToWait = 0;
|
|
800bb58: 683b ldr r3, [r7, #0]
|
|
800bb5a: 2200 movs r2, #0
|
|
800bb5c: 601a str r2, [r3, #0]
|
|
xReturn = pdTRUE;
|
|
800bb5e: 2301 movs r3, #1
|
|
800bb60: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800bb62: f000 fb5b bl 800c21c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800bb66: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800bb68: 4618 mov r0, r3
|
|
800bb6a: 3720 adds r7, #32
|
|
800bb6c: 46bd mov sp, r7
|
|
800bb6e: bd80 pop {r7, pc}
|
|
800bb70: 200006b0 .word 0x200006b0
|
|
800bb74: 200006c4 .word 0x200006c4
|
|
|
|
0800bb78 <vTaskMissedYield>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskMissedYield( void )
|
|
{
|
|
800bb78: b480 push {r7}
|
|
800bb7a: af00 add r7, sp, #0
|
|
xYieldPending = pdTRUE;
|
|
800bb7c: 4b03 ldr r3, [pc, #12] @ (800bb8c <vTaskMissedYield+0x14>)
|
|
800bb7e: 2201 movs r2, #1
|
|
800bb80: 601a str r2, [r3, #0]
|
|
}
|
|
800bb82: bf00 nop
|
|
800bb84: 46bd mov sp, r7
|
|
800bb86: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bb8a: 4770 bx lr
|
|
800bb8c: 200006c0 .word 0x200006c0
|
|
|
|
0800bb90 <prvIdleTask>:
|
|
*
|
|
* void prvIdleTask( void *pvParameters );
|
|
*
|
|
*/
|
|
static portTASK_FUNCTION( prvIdleTask, pvParameters )
|
|
{
|
|
800bb90: b580 push {r7, lr}
|
|
800bb92: b082 sub sp, #8
|
|
800bb94: af00 add r7, sp, #0
|
|
800bb96: 6078 str r0, [r7, #4]
|
|
|
|
for( ;; )
|
|
{
|
|
/* See if any tasks have deleted themselves - if so then the idle task
|
|
is responsible for freeing the deleted task's TCB and stack. */
|
|
prvCheckTasksWaitingTermination();
|
|
800bb98: f000 f854 bl 800bc44 <prvCheckTasksWaitingTermination>
|
|
|
|
A critical region is not required here as we are just reading from
|
|
the list, and an occasional incorrect value will not matter. If
|
|
the ready list at the idle priority contains more than one task
|
|
then a task other than the idle task is ready to execute. */
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
|
|
800bb9c: 4b07 ldr r3, [pc, #28] @ (800bbbc <prvIdleTask+0x2c>)
|
|
800bb9e: 681b ldr r3, [r3, #0]
|
|
800bba0: 2b01 cmp r3, #1
|
|
800bba2: d907 bls.n 800bbb4 <prvIdleTask+0x24>
|
|
{
|
|
taskYIELD();
|
|
800bba4: 4b06 ldr r3, [pc, #24] @ (800bbc0 <prvIdleTask+0x30>)
|
|
800bba6: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800bbaa: 601a str r2, [r3, #0]
|
|
800bbac: f3bf 8f4f dsb sy
|
|
800bbb0: f3bf 8f6f isb sy
|
|
/* Call the user defined function from within the idle task. This
|
|
allows the application designer to add background functionality
|
|
without the overhead of a separate task.
|
|
NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
|
|
CALL A FUNCTION THAT MIGHT BLOCK. */
|
|
vApplicationIdleHook();
|
|
800bbb4: f7f4 fcb2 bl 800051c <vApplicationIdleHook>
|
|
prvCheckTasksWaitingTermination();
|
|
800bbb8: e7ee b.n 800bb98 <prvIdleTask+0x8>
|
|
800bbba: bf00 nop
|
|
800bbbc: 200005b0 .word 0x200005b0
|
|
800bbc0: e000ed04 .word 0xe000ed04
|
|
|
|
0800bbc4 <prvInitialiseTaskLists>:
|
|
|
|
#endif /* portUSING_MPU_WRAPPERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInitialiseTaskLists( void )
|
|
{
|
|
800bbc4: b580 push {r7, lr}
|
|
800bbc6: b082 sub sp, #8
|
|
800bbc8: af00 add r7, sp, #0
|
|
UBaseType_t uxPriority;
|
|
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800bbca: 2300 movs r3, #0
|
|
800bbcc: 607b str r3, [r7, #4]
|
|
800bbce: e00c b.n 800bbea <prvInitialiseTaskLists+0x26>
|
|
{
|
|
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
|
|
800bbd0: 687a ldr r2, [r7, #4]
|
|
800bbd2: 4613 mov r3, r2
|
|
800bbd4: 009b lsls r3, r3, #2
|
|
800bbd6: 4413 add r3, r2
|
|
800bbd8: 009b lsls r3, r3, #2
|
|
800bbda: 4a12 ldr r2, [pc, #72] @ (800bc24 <prvInitialiseTaskLists+0x60>)
|
|
800bbdc: 4413 add r3, r2
|
|
800bbde: 4618 mov r0, r3
|
|
800bbe0: f7fe fc5c bl 800a49c <vListInitialise>
|
|
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
|
|
800bbe4: 687b ldr r3, [r7, #4]
|
|
800bbe6: 3301 adds r3, #1
|
|
800bbe8: 607b str r3, [r7, #4]
|
|
800bbea: 687b ldr r3, [r7, #4]
|
|
800bbec: 2b06 cmp r3, #6
|
|
800bbee: d9ef bls.n 800bbd0 <prvInitialiseTaskLists+0xc>
|
|
}
|
|
|
|
vListInitialise( &xDelayedTaskList1 );
|
|
800bbf0: 480d ldr r0, [pc, #52] @ (800bc28 <prvInitialiseTaskLists+0x64>)
|
|
800bbf2: f7fe fc53 bl 800a49c <vListInitialise>
|
|
vListInitialise( &xDelayedTaskList2 );
|
|
800bbf6: 480d ldr r0, [pc, #52] @ (800bc2c <prvInitialiseTaskLists+0x68>)
|
|
800bbf8: f7fe fc50 bl 800a49c <vListInitialise>
|
|
vListInitialise( &xPendingReadyList );
|
|
800bbfc: 480c ldr r0, [pc, #48] @ (800bc30 <prvInitialiseTaskLists+0x6c>)
|
|
800bbfe: f7fe fc4d bl 800a49c <vListInitialise>
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
{
|
|
vListInitialise( &xTasksWaitingTermination );
|
|
800bc02: 480c ldr r0, [pc, #48] @ (800bc34 <prvInitialiseTaskLists+0x70>)
|
|
800bc04: f7fe fc4a bl 800a49c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
vListInitialise( &xSuspendedTaskList );
|
|
800bc08: 480b ldr r0, [pc, #44] @ (800bc38 <prvInitialiseTaskLists+0x74>)
|
|
800bc0a: f7fe fc47 bl 800a49c <vListInitialise>
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
|
|
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
|
|
using list2. */
|
|
pxDelayedTaskList = &xDelayedTaskList1;
|
|
800bc0e: 4b0b ldr r3, [pc, #44] @ (800bc3c <prvInitialiseTaskLists+0x78>)
|
|
800bc10: 4a05 ldr r2, [pc, #20] @ (800bc28 <prvInitialiseTaskLists+0x64>)
|
|
800bc12: 601a str r2, [r3, #0]
|
|
pxOverflowDelayedTaskList = &xDelayedTaskList2;
|
|
800bc14: 4b0a ldr r3, [pc, #40] @ (800bc40 <prvInitialiseTaskLists+0x7c>)
|
|
800bc16: 4a05 ldr r2, [pc, #20] @ (800bc2c <prvInitialiseTaskLists+0x68>)
|
|
800bc18: 601a str r2, [r3, #0]
|
|
}
|
|
800bc1a: bf00 nop
|
|
800bc1c: 3708 adds r7, #8
|
|
800bc1e: 46bd mov sp, r7
|
|
800bc20: bd80 pop {r7, pc}
|
|
800bc22: bf00 nop
|
|
800bc24: 200005b0 .word 0x200005b0
|
|
800bc28: 2000063c .word 0x2000063c
|
|
800bc2c: 20000650 .word 0x20000650
|
|
800bc30: 2000066c .word 0x2000066c
|
|
800bc34: 20000680 .word 0x20000680
|
|
800bc38: 20000698 .word 0x20000698
|
|
800bc3c: 20000664 .word 0x20000664
|
|
800bc40: 20000668 .word 0x20000668
|
|
|
|
0800bc44 <prvCheckTasksWaitingTermination>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvCheckTasksWaitingTermination( void )
|
|
{
|
|
800bc44: b580 push {r7, lr}
|
|
800bc46: b082 sub sp, #8
|
|
800bc48: af00 add r7, sp, #0
|
|
{
|
|
TCB_t *pxTCB;
|
|
|
|
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
|
|
being called too often in the idle task. */
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800bc4a: e019 b.n 800bc80 <prvCheckTasksWaitingTermination+0x3c>
|
|
{
|
|
taskENTER_CRITICAL();
|
|
800bc4c: f000 fab4 bl 800c1b8 <vPortEnterCritical>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800bc50: 4b10 ldr r3, [pc, #64] @ (800bc94 <prvCheckTasksWaitingTermination+0x50>)
|
|
800bc52: 68db ldr r3, [r3, #12]
|
|
800bc54: 68db ldr r3, [r3, #12]
|
|
800bc56: 607b str r3, [r7, #4]
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800bc58: 687b ldr r3, [r7, #4]
|
|
800bc5a: 3304 adds r3, #4
|
|
800bc5c: 4618 mov r0, r3
|
|
800bc5e: f7fe fca7 bl 800a5b0 <uxListRemove>
|
|
--uxCurrentNumberOfTasks;
|
|
800bc62: 4b0d ldr r3, [pc, #52] @ (800bc98 <prvCheckTasksWaitingTermination+0x54>)
|
|
800bc64: 681b ldr r3, [r3, #0]
|
|
800bc66: 3b01 subs r3, #1
|
|
800bc68: 4a0b ldr r2, [pc, #44] @ (800bc98 <prvCheckTasksWaitingTermination+0x54>)
|
|
800bc6a: 6013 str r3, [r2, #0]
|
|
--uxDeletedTasksWaitingCleanUp;
|
|
800bc6c: 4b0b ldr r3, [pc, #44] @ (800bc9c <prvCheckTasksWaitingTermination+0x58>)
|
|
800bc6e: 681b ldr r3, [r3, #0]
|
|
800bc70: 3b01 subs r3, #1
|
|
800bc72: 4a0a ldr r2, [pc, #40] @ (800bc9c <prvCheckTasksWaitingTermination+0x58>)
|
|
800bc74: 6013 str r3, [r2, #0]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800bc76: f000 fad1 bl 800c21c <vPortExitCritical>
|
|
|
|
prvDeleteTCB( pxTCB );
|
|
800bc7a: 6878 ldr r0, [r7, #4]
|
|
800bc7c: f000 f810 bl 800bca0 <prvDeleteTCB>
|
|
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
|
|
800bc80: 4b06 ldr r3, [pc, #24] @ (800bc9c <prvCheckTasksWaitingTermination+0x58>)
|
|
800bc82: 681b ldr r3, [r3, #0]
|
|
800bc84: 2b00 cmp r3, #0
|
|
800bc86: d1e1 bne.n 800bc4c <prvCheckTasksWaitingTermination+0x8>
|
|
}
|
|
}
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
}
|
|
800bc88: bf00 nop
|
|
800bc8a: bf00 nop
|
|
800bc8c: 3708 adds r7, #8
|
|
800bc8e: 46bd mov sp, r7
|
|
800bc90: bd80 pop {r7, pc}
|
|
800bc92: bf00 nop
|
|
800bc94: 20000680 .word 0x20000680
|
|
800bc98: 200006ac .word 0x200006ac
|
|
800bc9c: 20000694 .word 0x20000694
|
|
|
|
0800bca0 <prvDeleteTCB>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( INCLUDE_vTaskDelete == 1 )
|
|
|
|
static void prvDeleteTCB( TCB_t *pxTCB )
|
|
{
|
|
800bca0: b580 push {r7, lr}
|
|
800bca2: b084 sub sp, #16
|
|
800bca4: af00 add r7, sp, #0
|
|
800bca6: 6078 str r0, [r7, #4]
|
|
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
|
|
{
|
|
/* The task could have been allocated statically or dynamically, so
|
|
check what was statically allocated before trying to free the
|
|
memory. */
|
|
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
|
|
800bca8: 687b ldr r3, [r7, #4]
|
|
800bcaa: f893 3055 ldrb.w r3, [r3, #85] @ 0x55
|
|
800bcae: 2b00 cmp r3, #0
|
|
800bcb0: d108 bne.n 800bcc4 <prvDeleteTCB+0x24>
|
|
{
|
|
/* Both the stack and TCB were allocated dynamically, so both
|
|
must be freed. */
|
|
vPortFree( pxTCB->pxStack );
|
|
800bcb2: 687b ldr r3, [r7, #4]
|
|
800bcb4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800bcb6: 4618 mov r0, r3
|
|
800bcb8: f000 fc74 bl 800c5a4 <vPortFree>
|
|
vPortFree( pxTCB );
|
|
800bcbc: 6878 ldr r0, [r7, #4]
|
|
800bcbe: f000 fc71 bl 800c5a4 <vPortFree>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
|
}
|
|
800bcc2: e019 b.n 800bcf8 <prvDeleteTCB+0x58>
|
|
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
|
|
800bcc4: 687b ldr r3, [r7, #4]
|
|
800bcc6: f893 3055 ldrb.w r3, [r3, #85] @ 0x55
|
|
800bcca: 2b01 cmp r3, #1
|
|
800bccc: d103 bne.n 800bcd6 <prvDeleteTCB+0x36>
|
|
vPortFree( pxTCB );
|
|
800bcce: 6878 ldr r0, [r7, #4]
|
|
800bcd0: f000 fc68 bl 800c5a4 <vPortFree>
|
|
}
|
|
800bcd4: e010 b.n 800bcf8 <prvDeleteTCB+0x58>
|
|
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
|
|
800bcd6: 687b ldr r3, [r7, #4]
|
|
800bcd8: f893 3055 ldrb.w r3, [r3, #85] @ 0x55
|
|
800bcdc: 2b02 cmp r3, #2
|
|
800bcde: d00b beq.n 800bcf8 <prvDeleteTCB+0x58>
|
|
__asm volatile
|
|
800bce0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bce4: f383 8811 msr BASEPRI, r3
|
|
800bce8: f3bf 8f6f isb sy
|
|
800bcec: f3bf 8f4f dsb sy
|
|
800bcf0: 60fb str r3, [r7, #12]
|
|
}
|
|
800bcf2: bf00 nop
|
|
800bcf4: bf00 nop
|
|
800bcf6: e7fd b.n 800bcf4 <prvDeleteTCB+0x54>
|
|
}
|
|
800bcf8: bf00 nop
|
|
800bcfa: 3710 adds r7, #16
|
|
800bcfc: 46bd mov sp, r7
|
|
800bcfe: bd80 pop {r7, pc}
|
|
|
|
0800bd00 <prvResetNextTaskUnblockTime>:
|
|
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvResetNextTaskUnblockTime( void )
|
|
{
|
|
800bd00: b480 push {r7}
|
|
800bd02: b083 sub sp, #12
|
|
800bd04: af00 add r7, sp, #0
|
|
TCB_t *pxTCB;
|
|
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800bd06: 4b0c ldr r3, [pc, #48] @ (800bd38 <prvResetNextTaskUnblockTime+0x38>)
|
|
800bd08: 681b ldr r3, [r3, #0]
|
|
800bd0a: 681b ldr r3, [r3, #0]
|
|
800bd0c: 2b00 cmp r3, #0
|
|
800bd0e: d104 bne.n 800bd1a <prvResetNextTaskUnblockTime+0x1a>
|
|
{
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
|
the maximum possible value so it is extremely unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
|
there is an item in the delayed list. */
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
800bd10: 4b0a ldr r3, [pc, #40] @ (800bd3c <prvResetNextTaskUnblockTime+0x3c>)
|
|
800bd12: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800bd16: 601a str r2, [r3, #0]
|
|
which the task at the head of the delayed list should be removed
|
|
from the Blocked state. */
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
}
|
|
}
|
|
800bd18: e008 b.n 800bd2c <prvResetNextTaskUnblockTime+0x2c>
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800bd1a: 4b07 ldr r3, [pc, #28] @ (800bd38 <prvResetNextTaskUnblockTime+0x38>)
|
|
800bd1c: 681b ldr r3, [r3, #0]
|
|
800bd1e: 68db ldr r3, [r3, #12]
|
|
800bd20: 68db ldr r3, [r3, #12]
|
|
800bd22: 607b str r3, [r7, #4]
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
800bd24: 687b ldr r3, [r7, #4]
|
|
800bd26: 685b ldr r3, [r3, #4]
|
|
800bd28: 4a04 ldr r2, [pc, #16] @ (800bd3c <prvResetNextTaskUnblockTime+0x3c>)
|
|
800bd2a: 6013 str r3, [r2, #0]
|
|
}
|
|
800bd2c: bf00 nop
|
|
800bd2e: 370c adds r7, #12
|
|
800bd30: 46bd mov sp, r7
|
|
800bd32: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bd36: 4770 bx lr
|
|
800bd38: 20000664 .word 0x20000664
|
|
800bd3c: 200006cc .word 0x200006cc
|
|
|
|
0800bd40 <xTaskGetSchedulerState>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
|
|
BaseType_t xTaskGetSchedulerState( void )
|
|
{
|
|
800bd40: b480 push {r7}
|
|
800bd42: b083 sub sp, #12
|
|
800bd44: af00 add r7, sp, #0
|
|
BaseType_t xReturn;
|
|
|
|
if( xSchedulerRunning == pdFALSE )
|
|
800bd46: 4b0b ldr r3, [pc, #44] @ (800bd74 <xTaskGetSchedulerState+0x34>)
|
|
800bd48: 681b ldr r3, [r3, #0]
|
|
800bd4a: 2b00 cmp r3, #0
|
|
800bd4c: d102 bne.n 800bd54 <xTaskGetSchedulerState+0x14>
|
|
{
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
|
800bd4e: 2301 movs r3, #1
|
|
800bd50: 607b str r3, [r7, #4]
|
|
800bd52: e008 b.n 800bd66 <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
800bd54: 4b08 ldr r3, [pc, #32] @ (800bd78 <xTaskGetSchedulerState+0x38>)
|
|
800bd56: 681b ldr r3, [r3, #0]
|
|
800bd58: 2b00 cmp r3, #0
|
|
800bd5a: d102 bne.n 800bd62 <xTaskGetSchedulerState+0x22>
|
|
{
|
|
xReturn = taskSCHEDULER_RUNNING;
|
|
800bd5c: 2302 movs r3, #2
|
|
800bd5e: 607b str r3, [r7, #4]
|
|
800bd60: e001 b.n 800bd66 <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
|
800bd62: 2300 movs r3, #0
|
|
800bd64: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
800bd66: 687b ldr r3, [r7, #4]
|
|
}
|
|
800bd68: 4618 mov r0, r3
|
|
800bd6a: 370c adds r7, #12
|
|
800bd6c: 46bd mov sp, r7
|
|
800bd6e: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bd72: 4770 bx lr
|
|
800bd74: 200006b8 .word 0x200006b8
|
|
800bd78: 200006d4 .word 0x200006d4
|
|
|
|
0800bd7c <xTaskPriorityDisinherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
800bd7c: b580 push {r7, lr}
|
|
800bd7e: b086 sub sp, #24
|
|
800bd80: af00 add r7, sp, #0
|
|
800bd82: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
800bd84: 687b ldr r3, [r7, #4]
|
|
800bd86: 613b str r3, [r7, #16]
|
|
BaseType_t xReturn = pdFALSE;
|
|
800bd88: 2300 movs r3, #0
|
|
800bd8a: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
800bd8c: 687b ldr r3, [r7, #4]
|
|
800bd8e: 2b00 cmp r3, #0
|
|
800bd90: d070 beq.n 800be74 <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
|
If the mutex is held by a task then it cannot be given from an
|
|
interrupt, and if a mutex is given by the holding task then it must
|
|
be the running state task. */
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
|
800bd92: 4b3b ldr r3, [pc, #236] @ (800be80 <xTaskPriorityDisinherit+0x104>)
|
|
800bd94: 681b ldr r3, [r3, #0]
|
|
800bd96: 693a ldr r2, [r7, #16]
|
|
800bd98: 429a cmp r2, r3
|
|
800bd9a: d00b beq.n 800bdb4 <xTaskPriorityDisinherit+0x38>
|
|
__asm volatile
|
|
800bd9c: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bda0: f383 8811 msr BASEPRI, r3
|
|
800bda4: f3bf 8f6f isb sy
|
|
800bda8: f3bf 8f4f dsb sy
|
|
800bdac: 60fb str r3, [r7, #12]
|
|
}
|
|
800bdae: bf00 nop
|
|
800bdb0: bf00 nop
|
|
800bdb2: e7fd b.n 800bdb0 <xTaskPriorityDisinherit+0x34>
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800bdb4: 693b ldr r3, [r7, #16]
|
|
800bdb6: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800bdb8: 2b00 cmp r3, #0
|
|
800bdba: d10b bne.n 800bdd4 <xTaskPriorityDisinherit+0x58>
|
|
__asm volatile
|
|
800bdbc: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bdc0: f383 8811 msr BASEPRI, r3
|
|
800bdc4: f3bf 8f6f isb sy
|
|
800bdc8: f3bf 8f4f dsb sy
|
|
800bdcc: 60bb str r3, [r7, #8]
|
|
}
|
|
800bdce: bf00 nop
|
|
800bdd0: bf00 nop
|
|
800bdd2: e7fd b.n 800bdd0 <xTaskPriorityDisinherit+0x54>
|
|
( pxTCB->uxMutexesHeld )--;
|
|
800bdd4: 693b ldr r3, [r7, #16]
|
|
800bdd6: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800bdd8: 1e5a subs r2, r3, #1
|
|
800bdda: 693b ldr r3, [r7, #16]
|
|
800bddc: 649a str r2, [r3, #72] @ 0x48
|
|
|
|
/* Has the holder of the mutex inherited the priority of another
|
|
task? */
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
|
800bdde: 693b ldr r3, [r7, #16]
|
|
800bde0: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800bde2: 693b ldr r3, [r7, #16]
|
|
800bde4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800bde6: 429a cmp r2, r3
|
|
800bde8: d044 beq.n 800be74 <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. */
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
|
800bdea: 693b ldr r3, [r7, #16]
|
|
800bdec: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
800bdee: 2b00 cmp r3, #0
|
|
800bdf0: d140 bne.n 800be74 <xTaskPriorityDisinherit+0xf8>
|
|
/* A task can only have an inherited priority if it holds
|
|
the mutex. If the mutex is held by a task then it cannot be
|
|
given from an interrupt, and if a mutex is given by the
|
|
holding task then it must be the running state task. Remove
|
|
the holding task from the ready/delayed list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800bdf2: 693b ldr r3, [r7, #16]
|
|
800bdf4: 3304 adds r3, #4
|
|
800bdf6: 4618 mov r0, r3
|
|
800bdf8: f7fe fbda bl 800a5b0 <uxListRemove>
|
|
800bdfc: 4603 mov r3, r0
|
|
800bdfe: 2b00 cmp r3, #0
|
|
800be00: d115 bne.n 800be2e <xTaskPriorityDisinherit+0xb2>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
|
|
800be02: 693b ldr r3, [r7, #16]
|
|
800be04: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800be06: 491f ldr r1, [pc, #124] @ (800be84 <xTaskPriorityDisinherit+0x108>)
|
|
800be08: 4613 mov r3, r2
|
|
800be0a: 009b lsls r3, r3, #2
|
|
800be0c: 4413 add r3, r2
|
|
800be0e: 009b lsls r3, r3, #2
|
|
800be10: 440b add r3, r1
|
|
800be12: 681b ldr r3, [r3, #0]
|
|
800be14: 2b00 cmp r3, #0
|
|
800be16: d10a bne.n 800be2e <xTaskPriorityDisinherit+0xb2>
|
|
800be18: 693b ldr r3, [r7, #16]
|
|
800be1a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800be1c: 2201 movs r2, #1
|
|
800be1e: fa02 f303 lsl.w r3, r2, r3
|
|
800be22: 43da mvns r2, r3
|
|
800be24: 4b18 ldr r3, [pc, #96] @ (800be88 <xTaskPriorityDisinherit+0x10c>)
|
|
800be26: 681b ldr r3, [r3, #0]
|
|
800be28: 4013 ands r3, r2
|
|
800be2a: 4a17 ldr r2, [pc, #92] @ (800be88 <xTaskPriorityDisinherit+0x10c>)
|
|
800be2c: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Disinherit the priority before adding the task into the
|
|
new ready list. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
|
800be2e: 693b ldr r3, [r7, #16]
|
|
800be30: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
800be32: 693b ldr r3, [r7, #16]
|
|
800be34: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Reset the event list item value. It cannot be in use for
|
|
any other purpose if this task is running, and it must be
|
|
running to give back the mutex. */
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
800be36: 693b ldr r3, [r7, #16]
|
|
800be38: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800be3a: f1c3 0207 rsb r2, r3, #7
|
|
800be3e: 693b ldr r3, [r7, #16]
|
|
800be40: 619a str r2, [r3, #24]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800be42: 693b ldr r3, [r7, #16]
|
|
800be44: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800be46: 2201 movs r2, #1
|
|
800be48: 409a lsls r2, r3
|
|
800be4a: 4b0f ldr r3, [pc, #60] @ (800be88 <xTaskPriorityDisinherit+0x10c>)
|
|
800be4c: 681b ldr r3, [r3, #0]
|
|
800be4e: 4313 orrs r3, r2
|
|
800be50: 4a0d ldr r2, [pc, #52] @ (800be88 <xTaskPriorityDisinherit+0x10c>)
|
|
800be52: 6013 str r3, [r2, #0]
|
|
800be54: 693b ldr r3, [r7, #16]
|
|
800be56: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800be58: 4613 mov r3, r2
|
|
800be5a: 009b lsls r3, r3, #2
|
|
800be5c: 4413 add r3, r2
|
|
800be5e: 009b lsls r3, r3, #2
|
|
800be60: 4a08 ldr r2, [pc, #32] @ (800be84 <xTaskPriorityDisinherit+0x108>)
|
|
800be62: 441a add r2, r3
|
|
800be64: 693b ldr r3, [r7, #16]
|
|
800be66: 3304 adds r3, #4
|
|
800be68: 4619 mov r1, r3
|
|
800be6a: 4610 mov r0, r2
|
|
800be6c: f7fe fb43 bl 800a4f6 <vListInsertEnd>
|
|
in an order different to that in which they were taken.
|
|
If a context switch did not occur when the first mutex was
|
|
returned, even if a task was waiting on it, then a context
|
|
switch should occur when the last mutex is returned whether
|
|
a task is waiting on it or not. */
|
|
xReturn = pdTRUE;
|
|
800be70: 2301 movs r3, #1
|
|
800be72: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
800be74: 697b ldr r3, [r7, #20]
|
|
}
|
|
800be76: 4618 mov r0, r3
|
|
800be78: 3718 adds r7, #24
|
|
800be7a: 46bd mov sp, r7
|
|
800be7c: bd80 pop {r7, pc}
|
|
800be7e: bf00 nop
|
|
800be80: 200005ac .word 0x200005ac
|
|
800be84: 200005b0 .word 0x200005b0
|
|
800be88: 200006b4 .word 0x200006b4
|
|
|
|
0800be8c <prvAddCurrentTaskToDelayedList>:
|
|
|
|
#endif
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
|
|
{
|
|
800be8c: b580 push {r7, lr}
|
|
800be8e: b084 sub sp, #16
|
|
800be90: af00 add r7, sp, #0
|
|
800be92: 6078 str r0, [r7, #4]
|
|
800be94: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
800be96: 4b29 ldr r3, [pc, #164] @ (800bf3c <prvAddCurrentTaskToDelayedList+0xb0>)
|
|
800be98: 681b ldr r3, [r3, #0]
|
|
800be9a: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif
|
|
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
|
as the same list item is used for both lists. */
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800be9c: 4b28 ldr r3, [pc, #160] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800be9e: 681b ldr r3, [r3, #0]
|
|
800bea0: 3304 adds r3, #4
|
|
800bea2: 4618 mov r0, r3
|
|
800bea4: f7fe fb84 bl 800a5b0 <uxListRemove>
|
|
800bea8: 4603 mov r3, r0
|
|
800beaa: 2b00 cmp r3, #0
|
|
800beac: d10b bne.n 800bec6 <prvAddCurrentTaskToDelayedList+0x3a>
|
|
{
|
|
/* The current task must be in a ready list, so there is no need to
|
|
check, and the port reset macro can be called directly. */
|
|
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
|
|
800beae: 4b24 ldr r3, [pc, #144] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800beb0: 681b ldr r3, [r3, #0]
|
|
800beb2: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800beb4: 2201 movs r2, #1
|
|
800beb6: fa02 f303 lsl.w r3, r2, r3
|
|
800beba: 43da mvns r2, r3
|
|
800bebc: 4b21 ldr r3, [pc, #132] @ (800bf44 <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
800bebe: 681b ldr r3, [r3, #0]
|
|
800bec0: 4013 ands r3, r2
|
|
800bec2: 4a20 ldr r2, [pc, #128] @ (800bf44 <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
800bec4: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
|
800bec6: 687b ldr r3, [r7, #4]
|
|
800bec8: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800becc: d10a bne.n 800bee4 <prvAddCurrentTaskToDelayedList+0x58>
|
|
800bece: 683b ldr r3, [r7, #0]
|
|
800bed0: 2b00 cmp r3, #0
|
|
800bed2: d007 beq.n 800bee4 <prvAddCurrentTaskToDelayedList+0x58>
|
|
{
|
|
/* Add the task to the suspended task list instead of a delayed task
|
|
list to ensure it is not woken by a timing event. It will block
|
|
indefinitely. */
|
|
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800bed4: 4b1a ldr r3, [pc, #104] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800bed6: 681b ldr r3, [r3, #0]
|
|
800bed8: 3304 adds r3, #4
|
|
800beda: 4619 mov r1, r3
|
|
800bedc: 481a ldr r0, [pc, #104] @ (800bf48 <prvAddCurrentTaskToDelayedList+0xbc>)
|
|
800bede: f7fe fb0a bl 800a4f6 <vListInsertEnd>
|
|
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
|
( void ) xCanBlockIndefinitely;
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
}
|
|
800bee2: e026 b.n 800bf32 <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
|
800bee4: 68fa ldr r2, [r7, #12]
|
|
800bee6: 687b ldr r3, [r7, #4]
|
|
800bee8: 4413 add r3, r2
|
|
800beea: 60bb str r3, [r7, #8]
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
|
800beec: 4b14 ldr r3, [pc, #80] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800beee: 681b ldr r3, [r3, #0]
|
|
800bef0: 68ba ldr r2, [r7, #8]
|
|
800bef2: 605a str r2, [r3, #4]
|
|
if( xTimeToWake < xConstTickCount )
|
|
800bef4: 68ba ldr r2, [r7, #8]
|
|
800bef6: 68fb ldr r3, [r7, #12]
|
|
800bef8: 429a cmp r2, r3
|
|
800befa: d209 bcs.n 800bf10 <prvAddCurrentTaskToDelayedList+0x84>
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800befc: 4b13 ldr r3, [pc, #76] @ (800bf4c <prvAddCurrentTaskToDelayedList+0xc0>)
|
|
800befe: 681a ldr r2, [r3, #0]
|
|
800bf00: 4b0f ldr r3, [pc, #60] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800bf02: 681b ldr r3, [r3, #0]
|
|
800bf04: 3304 adds r3, #4
|
|
800bf06: 4619 mov r1, r3
|
|
800bf08: 4610 mov r0, r2
|
|
800bf0a: f7fe fb18 bl 800a53e <vListInsert>
|
|
}
|
|
800bf0e: e010 b.n 800bf32 <prvAddCurrentTaskToDelayedList+0xa6>
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
800bf10: 4b0f ldr r3, [pc, #60] @ (800bf50 <prvAddCurrentTaskToDelayedList+0xc4>)
|
|
800bf12: 681a ldr r2, [r3, #0]
|
|
800bf14: 4b0a ldr r3, [pc, #40] @ (800bf40 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
800bf16: 681b ldr r3, [r3, #0]
|
|
800bf18: 3304 adds r3, #4
|
|
800bf1a: 4619 mov r1, r3
|
|
800bf1c: 4610 mov r0, r2
|
|
800bf1e: f7fe fb0e bl 800a53e <vListInsert>
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
|
800bf22: 4b0c ldr r3, [pc, #48] @ (800bf54 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
800bf24: 681b ldr r3, [r3, #0]
|
|
800bf26: 68ba ldr r2, [r7, #8]
|
|
800bf28: 429a cmp r2, r3
|
|
800bf2a: d202 bcs.n 800bf32 <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xNextTaskUnblockTime = xTimeToWake;
|
|
800bf2c: 4a09 ldr r2, [pc, #36] @ (800bf54 <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
800bf2e: 68bb ldr r3, [r7, #8]
|
|
800bf30: 6013 str r3, [r2, #0]
|
|
}
|
|
800bf32: bf00 nop
|
|
800bf34: 3710 adds r7, #16
|
|
800bf36: 46bd mov sp, r7
|
|
800bf38: bd80 pop {r7, pc}
|
|
800bf3a: bf00 nop
|
|
800bf3c: 200006b0 .word 0x200006b0
|
|
800bf40: 200005ac .word 0x200005ac
|
|
800bf44: 200006b4 .word 0x200006b4
|
|
800bf48: 20000698 .word 0x20000698
|
|
800bf4c: 20000668 .word 0x20000668
|
|
800bf50: 20000664 .word 0x20000664
|
|
800bf54: 200006cc .word 0x200006cc
|
|
|
|
0800bf58 <pxPortInitialiseStack>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
|
|
{
|
|
800bf58: b480 push {r7}
|
|
800bf5a: b085 sub sp, #20
|
|
800bf5c: af00 add r7, sp, #0
|
|
800bf5e: 60f8 str r0, [r7, #12]
|
|
800bf60: 60b9 str r1, [r7, #8]
|
|
800bf62: 607a str r2, [r7, #4]
|
|
/* Simulate the stack frame as it would be created by a context switch
|
|
interrupt. */
|
|
|
|
/* Offset added to account for the way the MCU uses the stack on entry/exit
|
|
of interrupts, and to ensure alignment. */
|
|
pxTopOfStack--;
|
|
800bf64: 68fb ldr r3, [r7, #12]
|
|
800bf66: 3b04 subs r3, #4
|
|
800bf68: 60fb str r3, [r7, #12]
|
|
|
|
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
|
|
800bf6a: 68fb ldr r3, [r7, #12]
|
|
800bf6c: f04f 7280 mov.w r2, #16777216 @ 0x1000000
|
|
800bf70: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800bf72: 68fb ldr r3, [r7, #12]
|
|
800bf74: 3b04 subs r3, #4
|
|
800bf76: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
|
|
800bf78: 68bb ldr r3, [r7, #8]
|
|
800bf7a: f023 0201 bic.w r2, r3, #1
|
|
800bf7e: 68fb ldr r3, [r7, #12]
|
|
800bf80: 601a str r2, [r3, #0]
|
|
pxTopOfStack--;
|
|
800bf82: 68fb ldr r3, [r7, #12]
|
|
800bf84: 3b04 subs r3, #4
|
|
800bf86: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
|
|
800bf88: 4a0c ldr r2, [pc, #48] @ (800bfbc <pxPortInitialiseStack+0x64>)
|
|
800bf8a: 68fb ldr r3, [r7, #12]
|
|
800bf8c: 601a str r2, [r3, #0]
|
|
|
|
/* Save code space by skipping register initialisation. */
|
|
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
|
|
800bf8e: 68fb ldr r3, [r7, #12]
|
|
800bf90: 3b14 subs r3, #20
|
|
800bf92: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
|
|
800bf94: 687a ldr r2, [r7, #4]
|
|
800bf96: 68fb ldr r3, [r7, #12]
|
|
800bf98: 601a str r2, [r3, #0]
|
|
|
|
/* A save method is being used that requires each task to maintain its
|
|
own exec return value. */
|
|
pxTopOfStack--;
|
|
800bf9a: 68fb ldr r3, [r7, #12]
|
|
800bf9c: 3b04 subs r3, #4
|
|
800bf9e: 60fb str r3, [r7, #12]
|
|
*pxTopOfStack = portINITIAL_EXC_RETURN;
|
|
800bfa0: 68fb ldr r3, [r7, #12]
|
|
800bfa2: f06f 0202 mvn.w r2, #2
|
|
800bfa6: 601a str r2, [r3, #0]
|
|
|
|
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
|
|
800bfa8: 68fb ldr r3, [r7, #12]
|
|
800bfaa: 3b20 subs r3, #32
|
|
800bfac: 60fb str r3, [r7, #12]
|
|
|
|
return pxTopOfStack;
|
|
800bfae: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800bfb0: 4618 mov r0, r3
|
|
800bfb2: 3714 adds r7, #20
|
|
800bfb4: 46bd mov sp, r7
|
|
800bfb6: f85d 7b04 ldr.w r7, [sp], #4
|
|
800bfba: 4770 bx lr
|
|
800bfbc: 0800bfc1 .word 0x0800bfc1
|
|
|
|
0800bfc0 <prvTaskExitError>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvTaskExitError( void )
|
|
{
|
|
800bfc0: b480 push {r7}
|
|
800bfc2: b085 sub sp, #20
|
|
800bfc4: af00 add r7, sp, #0
|
|
volatile uint32_t ulDummy = 0;
|
|
800bfc6: 2300 movs r3, #0
|
|
800bfc8: 607b str r3, [r7, #4]
|
|
its caller as there is nothing to return to. If a task wants to exit it
|
|
should instead call vTaskDelete( NULL ).
|
|
|
|
Artificially force an assert() to be triggered if configASSERT() is
|
|
defined, then stop here so application writers can catch the error. */
|
|
configASSERT( uxCriticalNesting == ~0UL );
|
|
800bfca: 4b13 ldr r3, [pc, #76] @ (800c018 <prvTaskExitError+0x58>)
|
|
800bfcc: 681b ldr r3, [r3, #0]
|
|
800bfce: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800bfd2: d00b beq.n 800bfec <prvTaskExitError+0x2c>
|
|
__asm volatile
|
|
800bfd4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bfd8: f383 8811 msr BASEPRI, r3
|
|
800bfdc: f3bf 8f6f isb sy
|
|
800bfe0: f3bf 8f4f dsb sy
|
|
800bfe4: 60fb str r3, [r7, #12]
|
|
}
|
|
800bfe6: bf00 nop
|
|
800bfe8: bf00 nop
|
|
800bfea: e7fd b.n 800bfe8 <prvTaskExitError+0x28>
|
|
__asm volatile
|
|
800bfec: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800bff0: f383 8811 msr BASEPRI, r3
|
|
800bff4: f3bf 8f6f isb sy
|
|
800bff8: f3bf 8f4f dsb sy
|
|
800bffc: 60bb str r3, [r7, #8]
|
|
}
|
|
800bffe: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
while( ulDummy == 0 )
|
|
800c000: bf00 nop
|
|
800c002: 687b ldr r3, [r7, #4]
|
|
800c004: 2b00 cmp r3, #0
|
|
800c006: d0fc beq.n 800c002 <prvTaskExitError+0x42>
|
|
about code appearing after this function is called - making ulDummy
|
|
volatile makes the compiler think the function could return and
|
|
therefore not output an 'unreachable code' warning for code that appears
|
|
after it. */
|
|
}
|
|
}
|
|
800c008: bf00 nop
|
|
800c00a: bf00 nop
|
|
800c00c: 3714 adds r7, #20
|
|
800c00e: 46bd mov sp, r7
|
|
800c010: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c014: 4770 bx lr
|
|
800c016: bf00 nop
|
|
800c018: 2000002c .word 0x2000002c
|
|
800c01c: 00000000 .word 0x00000000
|
|
|
|
0800c020 <SVC_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortSVCHandler( void )
|
|
{
|
|
__asm volatile (
|
|
800c020: 4b07 ldr r3, [pc, #28] @ (800c040 <pxCurrentTCBConst2>)
|
|
800c022: 6819 ldr r1, [r3, #0]
|
|
800c024: 6808 ldr r0, [r1, #0]
|
|
800c026: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800c02a: f380 8809 msr PSP, r0
|
|
800c02e: f3bf 8f6f isb sy
|
|
800c032: f04f 0000 mov.w r0, #0
|
|
800c036: f380 8811 msr BASEPRI, r0
|
|
800c03a: 4770 bx lr
|
|
800c03c: f3af 8000 nop.w
|
|
|
|
0800c040 <pxCurrentTCBConst2>:
|
|
800c040: 200005ac .word 0x200005ac
|
|
" bx r14 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
|
);
|
|
}
|
|
800c044: bf00 nop
|
|
800c046: bf00 nop
|
|
|
|
0800c048 <prvPortStartFirstTask>:
|
|
{
|
|
/* Start the first task. This also clears the bit that indicates the FPU is
|
|
in use in case the FPU was used before the scheduler was started - which
|
|
would otherwise result in the unnecessary leaving of space in the SVC stack
|
|
for lazy saving of FPU registers. */
|
|
__asm volatile(
|
|
800c048: 4808 ldr r0, [pc, #32] @ (800c06c <prvPortStartFirstTask+0x24>)
|
|
800c04a: 6800 ldr r0, [r0, #0]
|
|
800c04c: 6800 ldr r0, [r0, #0]
|
|
800c04e: f380 8808 msr MSP, r0
|
|
800c052: f04f 0000 mov.w r0, #0
|
|
800c056: f380 8814 msr CONTROL, r0
|
|
800c05a: b662 cpsie i
|
|
800c05c: b661 cpsie f
|
|
800c05e: f3bf 8f4f dsb sy
|
|
800c062: f3bf 8f6f isb sy
|
|
800c066: df00 svc 0
|
|
800c068: bf00 nop
|
|
" dsb \n"
|
|
" isb \n"
|
|
" svc 0 \n" /* System call to start first task. */
|
|
" nop \n"
|
|
);
|
|
}
|
|
800c06a: bf00 nop
|
|
800c06c: e000ed08 .word 0xe000ed08
|
|
|
|
0800c070 <xPortStartScheduler>:
|
|
|
|
/*
|
|
* See header file for description.
|
|
*/
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
800c070: b580 push {r7, lr}
|
|
800c072: b086 sub sp, #24
|
|
800c074: af00 add r7, sp, #0
|
|
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
|
|
|
|
/* This port can be used on all revisions of the Cortex-M7 core other than
|
|
the r0p1 parts. r0p1 parts should use the port from the
|
|
/source/portable/GCC/ARM_CM7/r0p1 directory. */
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
|
|
800c076: 4b47 ldr r3, [pc, #284] @ (800c194 <xPortStartScheduler+0x124>)
|
|
800c078: 681b ldr r3, [r3, #0]
|
|
800c07a: 4a47 ldr r2, [pc, #284] @ (800c198 <xPortStartScheduler+0x128>)
|
|
800c07c: 4293 cmp r3, r2
|
|
800c07e: d10b bne.n 800c098 <xPortStartScheduler+0x28>
|
|
__asm volatile
|
|
800c080: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c084: f383 8811 msr BASEPRI, r3
|
|
800c088: f3bf 8f6f isb sy
|
|
800c08c: f3bf 8f4f dsb sy
|
|
800c090: 60fb str r3, [r7, #12]
|
|
}
|
|
800c092: bf00 nop
|
|
800c094: bf00 nop
|
|
800c096: e7fd b.n 800c094 <xPortStartScheduler+0x24>
|
|
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
|
|
800c098: 4b3e ldr r3, [pc, #248] @ (800c194 <xPortStartScheduler+0x124>)
|
|
800c09a: 681b ldr r3, [r3, #0]
|
|
800c09c: 4a3f ldr r2, [pc, #252] @ (800c19c <xPortStartScheduler+0x12c>)
|
|
800c09e: 4293 cmp r3, r2
|
|
800c0a0: d10b bne.n 800c0ba <xPortStartScheduler+0x4a>
|
|
__asm volatile
|
|
800c0a2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c0a6: f383 8811 msr BASEPRI, r3
|
|
800c0aa: f3bf 8f6f isb sy
|
|
800c0ae: f3bf 8f4f dsb sy
|
|
800c0b2: 613b str r3, [r7, #16]
|
|
}
|
|
800c0b4: bf00 nop
|
|
800c0b6: bf00 nop
|
|
800c0b8: e7fd b.n 800c0b6 <xPortStartScheduler+0x46>
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
{
|
|
volatile uint32_t ulOriginalPriority;
|
|
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
|
|
800c0ba: 4b39 ldr r3, [pc, #228] @ (800c1a0 <xPortStartScheduler+0x130>)
|
|
800c0bc: 617b str r3, [r7, #20]
|
|
functions can be called. ISR safe functions are those that end in
|
|
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
|
|
ensure interrupt entry is as fast and simple as possible.
|
|
|
|
Save the interrupt priority value that is about to be clobbered. */
|
|
ulOriginalPriority = *pucFirstUserPriorityRegister;
|
|
800c0be: 697b ldr r3, [r7, #20]
|
|
800c0c0: 781b ldrb r3, [r3, #0]
|
|
800c0c2: b2db uxtb r3, r3
|
|
800c0c4: 607b str r3, [r7, #4]
|
|
|
|
/* Determine the number of priority bits available. First write to all
|
|
possible bits. */
|
|
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
|
|
800c0c6: 697b ldr r3, [r7, #20]
|
|
800c0c8: 22ff movs r2, #255 @ 0xff
|
|
800c0ca: 701a strb r2, [r3, #0]
|
|
|
|
/* Read the value back to see how many bits stuck. */
|
|
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
|
|
800c0cc: 697b ldr r3, [r7, #20]
|
|
800c0ce: 781b ldrb r3, [r3, #0]
|
|
800c0d0: b2db uxtb r3, r3
|
|
800c0d2: 70fb strb r3, [r7, #3]
|
|
|
|
/* Use the same mask on the maximum system call priority. */
|
|
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
|
|
800c0d4: 78fb ldrb r3, [r7, #3]
|
|
800c0d6: b2db uxtb r3, r3
|
|
800c0d8: f003 0350 and.w r3, r3, #80 @ 0x50
|
|
800c0dc: b2da uxtb r2, r3
|
|
800c0de: 4b31 ldr r3, [pc, #196] @ (800c1a4 <xPortStartScheduler+0x134>)
|
|
800c0e0: 701a strb r2, [r3, #0]
|
|
|
|
/* Calculate the maximum acceptable priority group value for the number
|
|
of bits read back. */
|
|
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
|
|
800c0e2: 4b31 ldr r3, [pc, #196] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c0e4: 2207 movs r2, #7
|
|
800c0e6: 601a str r2, [r3, #0]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
800c0e8: e009 b.n 800c0fe <xPortStartScheduler+0x8e>
|
|
{
|
|
ulMaxPRIGROUPValue--;
|
|
800c0ea: 4b2f ldr r3, [pc, #188] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c0ec: 681b ldr r3, [r3, #0]
|
|
800c0ee: 3b01 subs r3, #1
|
|
800c0f0: 4a2d ldr r2, [pc, #180] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c0f2: 6013 str r3, [r2, #0]
|
|
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
|
|
800c0f4: 78fb ldrb r3, [r7, #3]
|
|
800c0f6: b2db uxtb r3, r3
|
|
800c0f8: 005b lsls r3, r3, #1
|
|
800c0fa: b2db uxtb r3, r3
|
|
800c0fc: 70fb strb r3, [r7, #3]
|
|
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
|
|
800c0fe: 78fb ldrb r3, [r7, #3]
|
|
800c100: b2db uxtb r3, r3
|
|
800c102: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800c106: 2b80 cmp r3, #128 @ 0x80
|
|
800c108: d0ef beq.n 800c0ea <xPortStartScheduler+0x7a>
|
|
#ifdef configPRIO_BITS
|
|
{
|
|
/* Check the FreeRTOS configuration that defines the number of
|
|
priority bits matches the number of priority bits actually queried
|
|
from the hardware. */
|
|
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
|
|
800c10a: 4b27 ldr r3, [pc, #156] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c10c: 681b ldr r3, [r3, #0]
|
|
800c10e: f1c3 0307 rsb r3, r3, #7
|
|
800c112: 2b04 cmp r3, #4
|
|
800c114: d00b beq.n 800c12e <xPortStartScheduler+0xbe>
|
|
__asm volatile
|
|
800c116: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c11a: f383 8811 msr BASEPRI, r3
|
|
800c11e: f3bf 8f6f isb sy
|
|
800c122: f3bf 8f4f dsb sy
|
|
800c126: 60bb str r3, [r7, #8]
|
|
}
|
|
800c128: bf00 nop
|
|
800c12a: bf00 nop
|
|
800c12c: e7fd b.n 800c12a <xPortStartScheduler+0xba>
|
|
}
|
|
#endif
|
|
|
|
/* Shift the priority group value back to its position within the AIRCR
|
|
register. */
|
|
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
|
|
800c12e: 4b1e ldr r3, [pc, #120] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c130: 681b ldr r3, [r3, #0]
|
|
800c132: 021b lsls r3, r3, #8
|
|
800c134: 4a1c ldr r2, [pc, #112] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c136: 6013 str r3, [r2, #0]
|
|
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
|
|
800c138: 4b1b ldr r3, [pc, #108] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c13a: 681b ldr r3, [r3, #0]
|
|
800c13c: f403 63e0 and.w r3, r3, #1792 @ 0x700
|
|
800c140: 4a19 ldr r2, [pc, #100] @ (800c1a8 <xPortStartScheduler+0x138>)
|
|
800c142: 6013 str r3, [r2, #0]
|
|
|
|
/* Restore the clobbered interrupt priority register to its original
|
|
value. */
|
|
*pucFirstUserPriorityRegister = ulOriginalPriority;
|
|
800c144: 687b ldr r3, [r7, #4]
|
|
800c146: b2da uxtb r2, r3
|
|
800c148: 697b ldr r3, [r7, #20]
|
|
800c14a: 701a strb r2, [r3, #0]
|
|
}
|
|
#endif /* conifgASSERT_DEFINED */
|
|
|
|
/* Make PendSV and SysTick the lowest priority interrupts. */
|
|
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
|
|
800c14c: 4b17 ldr r3, [pc, #92] @ (800c1ac <xPortStartScheduler+0x13c>)
|
|
800c14e: 681b ldr r3, [r3, #0]
|
|
800c150: 4a16 ldr r2, [pc, #88] @ (800c1ac <xPortStartScheduler+0x13c>)
|
|
800c152: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
800c156: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
|
|
800c158: 4b14 ldr r3, [pc, #80] @ (800c1ac <xPortStartScheduler+0x13c>)
|
|
800c15a: 681b ldr r3, [r3, #0]
|
|
800c15c: 4a13 ldr r2, [pc, #76] @ (800c1ac <xPortStartScheduler+0x13c>)
|
|
800c15e: f043 4370 orr.w r3, r3, #4026531840 @ 0xf0000000
|
|
800c162: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the timer that generates the tick ISR. Interrupts are disabled
|
|
here already. */
|
|
vPortSetupTimerInterrupt();
|
|
800c164: f000 f8da bl 800c31c <vPortSetupTimerInterrupt>
|
|
|
|
/* Initialise the critical nesting count ready for the first task. */
|
|
uxCriticalNesting = 0;
|
|
800c168: 4b11 ldr r3, [pc, #68] @ (800c1b0 <xPortStartScheduler+0x140>)
|
|
800c16a: 2200 movs r2, #0
|
|
800c16c: 601a str r2, [r3, #0]
|
|
|
|
/* Ensure the VFP is enabled - it should be anyway. */
|
|
vPortEnableVFP();
|
|
800c16e: f000 f8f9 bl 800c364 <vPortEnableVFP>
|
|
|
|
/* Lazy save always. */
|
|
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
|
|
800c172: 4b10 ldr r3, [pc, #64] @ (800c1b4 <xPortStartScheduler+0x144>)
|
|
800c174: 681b ldr r3, [r3, #0]
|
|
800c176: 4a0f ldr r2, [pc, #60] @ (800c1b4 <xPortStartScheduler+0x144>)
|
|
800c178: f043 4340 orr.w r3, r3, #3221225472 @ 0xc0000000
|
|
800c17c: 6013 str r3, [r2, #0]
|
|
|
|
/* Start the first task. */
|
|
prvPortStartFirstTask();
|
|
800c17e: f7ff ff63 bl 800c048 <prvPortStartFirstTask>
|
|
exit error function to prevent compiler warnings about a static function
|
|
not being called in the case that the application writer overrides this
|
|
functionality by defining configTASK_RETURN_ADDRESS. Call
|
|
vTaskSwitchContext() so link time optimisation does not remove the
|
|
symbol. */
|
|
vTaskSwitchContext();
|
|
800c182: f7ff fb73 bl 800b86c <vTaskSwitchContext>
|
|
prvTaskExitError();
|
|
800c186: f7ff ff1b bl 800bfc0 <prvTaskExitError>
|
|
|
|
/* Should not get here! */
|
|
return 0;
|
|
800c18a: 2300 movs r3, #0
|
|
}
|
|
800c18c: 4618 mov r0, r3
|
|
800c18e: 3718 adds r7, #24
|
|
800c190: 46bd mov sp, r7
|
|
800c192: bd80 pop {r7, pc}
|
|
800c194: e000ed00 .word 0xe000ed00
|
|
800c198: 410fc271 .word 0x410fc271
|
|
800c19c: 410fc270 .word 0x410fc270
|
|
800c1a0: e000e400 .word 0xe000e400
|
|
800c1a4: 200006d8 .word 0x200006d8
|
|
800c1a8: 200006dc .word 0x200006dc
|
|
800c1ac: e000ed20 .word 0xe000ed20
|
|
800c1b0: 2000002c .word 0x2000002c
|
|
800c1b4: e000ef34 .word 0xe000ef34
|
|
|
|
0800c1b8 <vPortEnterCritical>:
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
800c1b8: b480 push {r7}
|
|
800c1ba: b083 sub sp, #12
|
|
800c1bc: af00 add r7, sp, #0
|
|
__asm volatile
|
|
800c1be: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c1c2: f383 8811 msr BASEPRI, r3
|
|
800c1c6: f3bf 8f6f isb sy
|
|
800c1ca: f3bf 8f4f dsb sy
|
|
800c1ce: 607b str r3, [r7, #4]
|
|
}
|
|
800c1d0: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
800c1d2: 4b10 ldr r3, [pc, #64] @ (800c214 <vPortEnterCritical+0x5c>)
|
|
800c1d4: 681b ldr r3, [r3, #0]
|
|
800c1d6: 3301 adds r3, #1
|
|
800c1d8: 4a0e ldr r2, [pc, #56] @ (800c214 <vPortEnterCritical+0x5c>)
|
|
800c1da: 6013 str r3, [r2, #0]
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
assert() if it is being called from an interrupt context. Only API
|
|
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
the critical nesting count is 1 to protect against recursive calls if the
|
|
assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
800c1dc: 4b0d ldr r3, [pc, #52] @ (800c214 <vPortEnterCritical+0x5c>)
|
|
800c1de: 681b ldr r3, [r3, #0]
|
|
800c1e0: 2b01 cmp r3, #1
|
|
800c1e2: d110 bne.n 800c206 <vPortEnterCritical+0x4e>
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
800c1e4: 4b0c ldr r3, [pc, #48] @ (800c218 <vPortEnterCritical+0x60>)
|
|
800c1e6: 681b ldr r3, [r3, #0]
|
|
800c1e8: b2db uxtb r3, r3
|
|
800c1ea: 2b00 cmp r3, #0
|
|
800c1ec: d00b beq.n 800c206 <vPortEnterCritical+0x4e>
|
|
__asm volatile
|
|
800c1ee: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c1f2: f383 8811 msr BASEPRI, r3
|
|
800c1f6: f3bf 8f6f isb sy
|
|
800c1fa: f3bf 8f4f dsb sy
|
|
800c1fe: 603b str r3, [r7, #0]
|
|
}
|
|
800c200: bf00 nop
|
|
800c202: bf00 nop
|
|
800c204: e7fd b.n 800c202 <vPortEnterCritical+0x4a>
|
|
}
|
|
}
|
|
800c206: bf00 nop
|
|
800c208: 370c adds r7, #12
|
|
800c20a: 46bd mov sp, r7
|
|
800c20c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c210: 4770 bx lr
|
|
800c212: bf00 nop
|
|
800c214: 2000002c .word 0x2000002c
|
|
800c218: e000ed04 .word 0xe000ed04
|
|
|
|
0800c21c <vPortExitCritical>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
800c21c: b480 push {r7}
|
|
800c21e: b083 sub sp, #12
|
|
800c220: af00 add r7, sp, #0
|
|
configASSERT( uxCriticalNesting );
|
|
800c222: 4b12 ldr r3, [pc, #72] @ (800c26c <vPortExitCritical+0x50>)
|
|
800c224: 681b ldr r3, [r3, #0]
|
|
800c226: 2b00 cmp r3, #0
|
|
800c228: d10b bne.n 800c242 <vPortExitCritical+0x26>
|
|
__asm volatile
|
|
800c22a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c22e: f383 8811 msr BASEPRI, r3
|
|
800c232: f3bf 8f6f isb sy
|
|
800c236: f3bf 8f4f dsb sy
|
|
800c23a: 607b str r3, [r7, #4]
|
|
}
|
|
800c23c: bf00 nop
|
|
800c23e: bf00 nop
|
|
800c240: e7fd b.n 800c23e <vPortExitCritical+0x22>
|
|
uxCriticalNesting--;
|
|
800c242: 4b0a ldr r3, [pc, #40] @ (800c26c <vPortExitCritical+0x50>)
|
|
800c244: 681b ldr r3, [r3, #0]
|
|
800c246: 3b01 subs r3, #1
|
|
800c248: 4a08 ldr r2, [pc, #32] @ (800c26c <vPortExitCritical+0x50>)
|
|
800c24a: 6013 str r3, [r2, #0]
|
|
if( uxCriticalNesting == 0 )
|
|
800c24c: 4b07 ldr r3, [pc, #28] @ (800c26c <vPortExitCritical+0x50>)
|
|
800c24e: 681b ldr r3, [r3, #0]
|
|
800c250: 2b00 cmp r3, #0
|
|
800c252: d105 bne.n 800c260 <vPortExitCritical+0x44>
|
|
800c254: 2300 movs r3, #0
|
|
800c256: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
800c258: 683b ldr r3, [r7, #0]
|
|
800c25a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800c25e: bf00 nop
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
}
|
|
800c260: bf00 nop
|
|
800c262: 370c adds r7, #12
|
|
800c264: 46bd mov sp, r7
|
|
800c266: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c26a: 4770 bx lr
|
|
800c26c: 2000002c .word 0x2000002c
|
|
|
|
0800c270 <PendSV_Handler>:
|
|
|
|
void xPortPendSVHandler( void )
|
|
{
|
|
/* This is a naked function. */
|
|
|
|
__asm volatile
|
|
800c270: f3ef 8009 mrs r0, PSP
|
|
800c274: f3bf 8f6f isb sy
|
|
800c278: 4b15 ldr r3, [pc, #84] @ (800c2d0 <pxCurrentTCBConst>)
|
|
800c27a: 681a ldr r2, [r3, #0]
|
|
800c27c: f01e 0f10 tst.w lr, #16
|
|
800c280: bf08 it eq
|
|
800c282: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
|
800c286: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800c28a: 6010 str r0, [r2, #0]
|
|
800c28c: e92d 0009 stmdb sp!, {r0, r3}
|
|
800c290: f04f 0050 mov.w r0, #80 @ 0x50
|
|
800c294: f380 8811 msr BASEPRI, r0
|
|
800c298: f3bf 8f4f dsb sy
|
|
800c29c: f3bf 8f6f isb sy
|
|
800c2a0: f7ff fae4 bl 800b86c <vTaskSwitchContext>
|
|
800c2a4: f04f 0000 mov.w r0, #0
|
|
800c2a8: f380 8811 msr BASEPRI, r0
|
|
800c2ac: bc09 pop {r0, r3}
|
|
800c2ae: 6819 ldr r1, [r3, #0]
|
|
800c2b0: 6808 ldr r0, [r1, #0]
|
|
800c2b2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
800c2b6: f01e 0f10 tst.w lr, #16
|
|
800c2ba: bf08 it eq
|
|
800c2bc: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
|
800c2c0: f380 8809 msr PSP, r0
|
|
800c2c4: f3bf 8f6f isb sy
|
|
800c2c8: 4770 bx lr
|
|
800c2ca: bf00 nop
|
|
800c2cc: f3af 8000 nop.w
|
|
|
|
0800c2d0 <pxCurrentTCBConst>:
|
|
800c2d0: 200005ac .word 0x200005ac
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
|
);
|
|
}
|
|
800c2d4: bf00 nop
|
|
800c2d6: bf00 nop
|
|
|
|
0800c2d8 <SysTick_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
800c2d8: b580 push {r7, lr}
|
|
800c2da: b082 sub sp, #8
|
|
800c2dc: af00 add r7, sp, #0
|
|
__asm volatile
|
|
800c2de: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c2e2: f383 8811 msr BASEPRI, r3
|
|
800c2e6: f3bf 8f6f isb sy
|
|
800c2ea: f3bf 8f4f dsb sy
|
|
800c2ee: 607b str r3, [r7, #4]
|
|
}
|
|
800c2f0: bf00 nop
|
|
save and then restore the interrupt mask value as its value is already
|
|
known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800c2f2: f7ff fa01 bl 800b6f8 <xTaskIncrementTick>
|
|
800c2f6: 4603 mov r3, r0
|
|
800c2f8: 2b00 cmp r3, #0
|
|
800c2fa: d003 beq.n 800c304 <SysTick_Handler+0x2c>
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
800c2fc: 4b06 ldr r3, [pc, #24] @ (800c318 <SysTick_Handler+0x40>)
|
|
800c2fe: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
800c302: 601a str r2, [r3, #0]
|
|
800c304: 2300 movs r3, #0
|
|
800c306: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
800c308: 683b ldr r3, [r7, #0]
|
|
800c30a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
800c30e: bf00 nop
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
800c310: bf00 nop
|
|
800c312: 3708 adds r7, #8
|
|
800c314: 46bd mov sp, r7
|
|
800c316: bd80 pop {r7, pc}
|
|
800c318: e000ed04 .word 0xe000ed04
|
|
|
|
0800c31c <vPortSetupTimerInterrupt>:
|
|
/*
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
|
* frequency.
|
|
*/
|
|
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
|
|
{
|
|
800c31c: b480 push {r7}
|
|
800c31e: af00 add r7, sp, #0
|
|
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
|
|
}
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
|
|
/* Stop and clear the SysTick. */
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
800c320: 4b0b ldr r3, [pc, #44] @ (800c350 <vPortSetupTimerInterrupt+0x34>)
|
|
800c322: 2200 movs r2, #0
|
|
800c324: 601a str r2, [r3, #0]
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
800c326: 4b0b ldr r3, [pc, #44] @ (800c354 <vPortSetupTimerInterrupt+0x38>)
|
|
800c328: 2200 movs r2, #0
|
|
800c32a: 601a str r2, [r3, #0]
|
|
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
800c32c: 4b0a ldr r3, [pc, #40] @ (800c358 <vPortSetupTimerInterrupt+0x3c>)
|
|
800c32e: 681b ldr r3, [r3, #0]
|
|
800c330: 4a0a ldr r2, [pc, #40] @ (800c35c <vPortSetupTimerInterrupt+0x40>)
|
|
800c332: fba2 2303 umull r2, r3, r2, r3
|
|
800c336: 099b lsrs r3, r3, #6
|
|
800c338: 4a09 ldr r2, [pc, #36] @ (800c360 <vPortSetupTimerInterrupt+0x44>)
|
|
800c33a: 3b01 subs r3, #1
|
|
800c33c: 6013 str r3, [r2, #0]
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
800c33e: 4b04 ldr r3, [pc, #16] @ (800c350 <vPortSetupTimerInterrupt+0x34>)
|
|
800c340: 2207 movs r2, #7
|
|
800c342: 601a str r2, [r3, #0]
|
|
}
|
|
800c344: bf00 nop
|
|
800c346: 46bd mov sp, r7
|
|
800c348: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c34c: 4770 bx lr
|
|
800c34e: bf00 nop
|
|
800c350: e000e010 .word 0xe000e010
|
|
800c354: e000e018 .word 0xe000e018
|
|
800c358: 20000000 .word 0x20000000
|
|
800c35c: 10624dd3 .word 0x10624dd3
|
|
800c360: e000e014 .word 0xe000e014
|
|
|
|
0800c364 <vPortEnableVFP>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/* This is a naked function. */
|
|
static void vPortEnableVFP( void )
|
|
{
|
|
__asm volatile
|
|
800c364: f8df 000c ldr.w r0, [pc, #12] @ 800c374 <vPortEnableVFP+0x10>
|
|
800c368: 6801 ldr r1, [r0, #0]
|
|
800c36a: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800c36e: 6001 str r1, [r0, #0]
|
|
800c370: 4770 bx lr
|
|
" \n"
|
|
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
|
|
" str r1, [r0] \n"
|
|
" bx r14 "
|
|
);
|
|
}
|
|
800c372: bf00 nop
|
|
800c374: e000ed88 .word 0xe000ed88
|
|
|
|
0800c378 <vPortValidateInterruptPriority>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
800c378: b480 push {r7}
|
|
800c37a: b085 sub sp, #20
|
|
800c37c: af00 add r7, sp, #0
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
800c37e: f3ef 8305 mrs r3, IPSR
|
|
800c382: 60fb str r3, [r7, #12]
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
800c384: 68fb ldr r3, [r7, #12]
|
|
800c386: 2b0f cmp r3, #15
|
|
800c388: d915 bls.n 800c3b6 <vPortValidateInterruptPriority+0x3e>
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
800c38a: 4a18 ldr r2, [pc, #96] @ (800c3ec <vPortValidateInterruptPriority+0x74>)
|
|
800c38c: 68fb ldr r3, [r7, #12]
|
|
800c38e: 4413 add r3, r2
|
|
800c390: 781b ldrb r3, [r3, #0]
|
|
800c392: 72fb strb r3, [r7, #11]
|
|
interrupt entry is as fast and simple as possible.
|
|
|
|
The following links provide detailed information:
|
|
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
http://www.freertos.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
800c394: 4b16 ldr r3, [pc, #88] @ (800c3f0 <vPortValidateInterruptPriority+0x78>)
|
|
800c396: 781b ldrb r3, [r3, #0]
|
|
800c398: 7afa ldrb r2, [r7, #11]
|
|
800c39a: 429a cmp r2, r3
|
|
800c39c: d20b bcs.n 800c3b6 <vPortValidateInterruptPriority+0x3e>
|
|
__asm volatile
|
|
800c39e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c3a2: f383 8811 msr BASEPRI, r3
|
|
800c3a6: f3bf 8f6f isb sy
|
|
800c3aa: f3bf 8f4f dsb sy
|
|
800c3ae: 607b str r3, [r7, #4]
|
|
}
|
|
800c3b0: bf00 nop
|
|
800c3b2: bf00 nop
|
|
800c3b4: e7fd b.n 800c3b2 <vPortValidateInterruptPriority+0x3a>
|
|
configuration then the correct setting can be achieved on all Cortex-M
|
|
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
scheduler. Note however that some vendor specific peripheral libraries
|
|
assume a non-zero priority group setting, in which cases using a value
|
|
of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
800c3b6: 4b0f ldr r3, [pc, #60] @ (800c3f4 <vPortValidateInterruptPriority+0x7c>)
|
|
800c3b8: 681b ldr r3, [r3, #0]
|
|
800c3ba: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
800c3be: 4b0e ldr r3, [pc, #56] @ (800c3f8 <vPortValidateInterruptPriority+0x80>)
|
|
800c3c0: 681b ldr r3, [r3, #0]
|
|
800c3c2: 429a cmp r2, r3
|
|
800c3c4: d90b bls.n 800c3de <vPortValidateInterruptPriority+0x66>
|
|
__asm volatile
|
|
800c3c6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c3ca: f383 8811 msr BASEPRI, r3
|
|
800c3ce: f3bf 8f6f isb sy
|
|
800c3d2: f3bf 8f4f dsb sy
|
|
800c3d6: 603b str r3, [r7, #0]
|
|
}
|
|
800c3d8: bf00 nop
|
|
800c3da: bf00 nop
|
|
800c3dc: e7fd b.n 800c3da <vPortValidateInterruptPriority+0x62>
|
|
}
|
|
800c3de: bf00 nop
|
|
800c3e0: 3714 adds r7, #20
|
|
800c3e2: 46bd mov sp, r7
|
|
800c3e4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c3e8: 4770 bx lr
|
|
800c3ea: bf00 nop
|
|
800c3ec: e000e3f0 .word 0xe000e3f0
|
|
800c3f0: 200006d8 .word 0x200006d8
|
|
800c3f4: e000ed0c .word 0xe000ed0c
|
|
800c3f8: 200006dc .word 0x200006dc
|
|
|
|
0800c3fc <pvPortMalloc>:
|
|
static size_t xBlockAllocatedBit = 0;
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void *pvPortMalloc( size_t xWantedSize )
|
|
{
|
|
800c3fc: b580 push {r7, lr}
|
|
800c3fe: b08a sub sp, #40 @ 0x28
|
|
800c400: af00 add r7, sp, #0
|
|
800c402: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
|
|
void *pvReturn = NULL;
|
|
800c404: 2300 movs r3, #0
|
|
800c406: 61fb str r3, [r7, #28]
|
|
|
|
vTaskSuspendAll();
|
|
800c408: f7ff f8ca bl 800b5a0 <vTaskSuspendAll>
|
|
{
|
|
/* If this is the first call to malloc then the heap will require
|
|
initialisation to setup the list of free blocks. */
|
|
if( pxEnd == NULL )
|
|
800c40c: 4b5f ldr r3, [pc, #380] @ (800c58c <pvPortMalloc+0x190>)
|
|
800c40e: 681b ldr r3, [r3, #0]
|
|
800c410: 2b00 cmp r3, #0
|
|
800c412: d101 bne.n 800c418 <pvPortMalloc+0x1c>
|
|
{
|
|
prvHeapInit();
|
|
800c414: f000 f92a bl 800c66c <prvHeapInit>
|
|
|
|
/* Check the requested block size is not so large that the top bit is
|
|
set. The top bit of the block size member of the BlockLink_t structure
|
|
is used to determine who owns the block - the application or the
|
|
kernel, so it must be free. */
|
|
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
|
|
800c418: 4b5d ldr r3, [pc, #372] @ (800c590 <pvPortMalloc+0x194>)
|
|
800c41a: 681a ldr r2, [r3, #0]
|
|
800c41c: 687b ldr r3, [r7, #4]
|
|
800c41e: 4013 ands r3, r2
|
|
800c420: 2b00 cmp r3, #0
|
|
800c422: f040 8095 bne.w 800c550 <pvPortMalloc+0x154>
|
|
{
|
|
/* The wanted size is increased so it can contain a BlockLink_t
|
|
structure in addition to the requested amount of bytes. */
|
|
if( xWantedSize > 0 )
|
|
800c426: 687b ldr r3, [r7, #4]
|
|
800c428: 2b00 cmp r3, #0
|
|
800c42a: d01e beq.n 800c46a <pvPortMalloc+0x6e>
|
|
{
|
|
xWantedSize += xHeapStructSize;
|
|
800c42c: 2208 movs r2, #8
|
|
800c42e: 687b ldr r3, [r7, #4]
|
|
800c430: 4413 add r3, r2
|
|
800c432: 607b str r3, [r7, #4]
|
|
|
|
/* Ensure that blocks are always aligned to the required number
|
|
of bytes. */
|
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
|
800c434: 687b ldr r3, [r7, #4]
|
|
800c436: f003 0307 and.w r3, r3, #7
|
|
800c43a: 2b00 cmp r3, #0
|
|
800c43c: d015 beq.n 800c46a <pvPortMalloc+0x6e>
|
|
{
|
|
/* Byte alignment required. */
|
|
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
|
|
800c43e: 687b ldr r3, [r7, #4]
|
|
800c440: f023 0307 bic.w r3, r3, #7
|
|
800c444: 3308 adds r3, #8
|
|
800c446: 607b str r3, [r7, #4]
|
|
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800c448: 687b ldr r3, [r7, #4]
|
|
800c44a: f003 0307 and.w r3, r3, #7
|
|
800c44e: 2b00 cmp r3, #0
|
|
800c450: d00b beq.n 800c46a <pvPortMalloc+0x6e>
|
|
__asm volatile
|
|
800c452: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c456: f383 8811 msr BASEPRI, r3
|
|
800c45a: f3bf 8f6f isb sy
|
|
800c45e: f3bf 8f4f dsb sy
|
|
800c462: 617b str r3, [r7, #20]
|
|
}
|
|
800c464: bf00 nop
|
|
800c466: bf00 nop
|
|
800c468: e7fd b.n 800c466 <pvPortMalloc+0x6a>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
|
800c46a: 687b ldr r3, [r7, #4]
|
|
800c46c: 2b00 cmp r3, #0
|
|
800c46e: d06f beq.n 800c550 <pvPortMalloc+0x154>
|
|
800c470: 4b48 ldr r3, [pc, #288] @ (800c594 <pvPortMalloc+0x198>)
|
|
800c472: 681b ldr r3, [r3, #0]
|
|
800c474: 687a ldr r2, [r7, #4]
|
|
800c476: 429a cmp r2, r3
|
|
800c478: d86a bhi.n 800c550 <pvPortMalloc+0x154>
|
|
{
|
|
/* Traverse the list from the start (lowest address) block until
|
|
one of adequate size is found. */
|
|
pxPreviousBlock = &xStart;
|
|
800c47a: 4b47 ldr r3, [pc, #284] @ (800c598 <pvPortMalloc+0x19c>)
|
|
800c47c: 623b str r3, [r7, #32]
|
|
pxBlock = xStart.pxNextFreeBlock;
|
|
800c47e: 4b46 ldr r3, [pc, #280] @ (800c598 <pvPortMalloc+0x19c>)
|
|
800c480: 681b ldr r3, [r3, #0]
|
|
800c482: 627b str r3, [r7, #36] @ 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
800c484: e004 b.n 800c490 <pvPortMalloc+0x94>
|
|
{
|
|
pxPreviousBlock = pxBlock;
|
|
800c486: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c488: 623b str r3, [r7, #32]
|
|
pxBlock = pxBlock->pxNextFreeBlock;
|
|
800c48a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c48c: 681b ldr r3, [r3, #0]
|
|
800c48e: 627b str r3, [r7, #36] @ 0x24
|
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
|
800c490: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c492: 685b ldr r3, [r3, #4]
|
|
800c494: 687a ldr r2, [r7, #4]
|
|
800c496: 429a cmp r2, r3
|
|
800c498: d903 bls.n 800c4a2 <pvPortMalloc+0xa6>
|
|
800c49a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c49c: 681b ldr r3, [r3, #0]
|
|
800c49e: 2b00 cmp r3, #0
|
|
800c4a0: d1f1 bne.n 800c486 <pvPortMalloc+0x8a>
|
|
}
|
|
|
|
/* If the end marker was reached then a block of adequate size
|
|
was not found. */
|
|
if( pxBlock != pxEnd )
|
|
800c4a2: 4b3a ldr r3, [pc, #232] @ (800c58c <pvPortMalloc+0x190>)
|
|
800c4a4: 681b ldr r3, [r3, #0]
|
|
800c4a6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800c4a8: 429a cmp r2, r3
|
|
800c4aa: d051 beq.n 800c550 <pvPortMalloc+0x154>
|
|
{
|
|
/* Return the memory space pointed to - jumping over the
|
|
BlockLink_t structure at its start. */
|
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
|
800c4ac: 6a3b ldr r3, [r7, #32]
|
|
800c4ae: 681b ldr r3, [r3, #0]
|
|
800c4b0: 2208 movs r2, #8
|
|
800c4b2: 4413 add r3, r2
|
|
800c4b4: 61fb str r3, [r7, #28]
|
|
|
|
/* This block is being returned for use so must be taken out
|
|
of the list of free blocks. */
|
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
|
800c4b6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c4b8: 681a ldr r2, [r3, #0]
|
|
800c4ba: 6a3b ldr r3, [r7, #32]
|
|
800c4bc: 601a str r2, [r3, #0]
|
|
|
|
/* If the block is larger than required it can be split into
|
|
two. */
|
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
|
800c4be: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c4c0: 685a ldr r2, [r3, #4]
|
|
800c4c2: 687b ldr r3, [r7, #4]
|
|
800c4c4: 1ad2 subs r2, r2, r3
|
|
800c4c6: 2308 movs r3, #8
|
|
800c4c8: 005b lsls r3, r3, #1
|
|
800c4ca: 429a cmp r2, r3
|
|
800c4cc: d920 bls.n 800c510 <pvPortMalloc+0x114>
|
|
{
|
|
/* This block is to be split into two. Create a new
|
|
block following the number of bytes requested. The void
|
|
cast is used to prevent byte alignment warnings from the
|
|
compiler. */
|
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
|
800c4ce: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
800c4d0: 687b ldr r3, [r7, #4]
|
|
800c4d2: 4413 add r3, r2
|
|
800c4d4: 61bb str r3, [r7, #24]
|
|
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800c4d6: 69bb ldr r3, [r7, #24]
|
|
800c4d8: f003 0307 and.w r3, r3, #7
|
|
800c4dc: 2b00 cmp r3, #0
|
|
800c4de: d00b beq.n 800c4f8 <pvPortMalloc+0xfc>
|
|
__asm volatile
|
|
800c4e0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c4e4: f383 8811 msr BASEPRI, r3
|
|
800c4e8: f3bf 8f6f isb sy
|
|
800c4ec: f3bf 8f4f dsb sy
|
|
800c4f0: 613b str r3, [r7, #16]
|
|
}
|
|
800c4f2: bf00 nop
|
|
800c4f4: bf00 nop
|
|
800c4f6: e7fd b.n 800c4f4 <pvPortMalloc+0xf8>
|
|
|
|
/* Calculate the sizes of two blocks split from the
|
|
single block. */
|
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
|
800c4f8: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c4fa: 685a ldr r2, [r3, #4]
|
|
800c4fc: 687b ldr r3, [r7, #4]
|
|
800c4fe: 1ad2 subs r2, r2, r3
|
|
800c500: 69bb ldr r3, [r7, #24]
|
|
800c502: 605a str r2, [r3, #4]
|
|
pxBlock->xBlockSize = xWantedSize;
|
|
800c504: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c506: 687a ldr r2, [r7, #4]
|
|
800c508: 605a str r2, [r3, #4]
|
|
|
|
/* Insert the new block into the list of free blocks. */
|
|
prvInsertBlockIntoFreeList( pxNewBlockLink );
|
|
800c50a: 69b8 ldr r0, [r7, #24]
|
|
800c50c: f000 f910 bl 800c730 <prvInsertBlockIntoFreeList>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
|
800c510: 4b20 ldr r3, [pc, #128] @ (800c594 <pvPortMalloc+0x198>)
|
|
800c512: 681a ldr r2, [r3, #0]
|
|
800c514: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c516: 685b ldr r3, [r3, #4]
|
|
800c518: 1ad3 subs r3, r2, r3
|
|
800c51a: 4a1e ldr r2, [pc, #120] @ (800c594 <pvPortMalloc+0x198>)
|
|
800c51c: 6013 str r3, [r2, #0]
|
|
|
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
|
800c51e: 4b1d ldr r3, [pc, #116] @ (800c594 <pvPortMalloc+0x198>)
|
|
800c520: 681a ldr r2, [r3, #0]
|
|
800c522: 4b1e ldr r3, [pc, #120] @ (800c59c <pvPortMalloc+0x1a0>)
|
|
800c524: 681b ldr r3, [r3, #0]
|
|
800c526: 429a cmp r2, r3
|
|
800c528: d203 bcs.n 800c532 <pvPortMalloc+0x136>
|
|
{
|
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
|
800c52a: 4b1a ldr r3, [pc, #104] @ (800c594 <pvPortMalloc+0x198>)
|
|
800c52c: 681b ldr r3, [r3, #0]
|
|
800c52e: 4a1b ldr r2, [pc, #108] @ (800c59c <pvPortMalloc+0x1a0>)
|
|
800c530: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* The block is being returned - it is allocated and owned
|
|
by the application and has no "next" block. */
|
|
pxBlock->xBlockSize |= xBlockAllocatedBit;
|
|
800c532: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c534: 685a ldr r2, [r3, #4]
|
|
800c536: 4b16 ldr r3, [pc, #88] @ (800c590 <pvPortMalloc+0x194>)
|
|
800c538: 681b ldr r3, [r3, #0]
|
|
800c53a: 431a orrs r2, r3
|
|
800c53c: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c53e: 605a str r2, [r3, #4]
|
|
pxBlock->pxNextFreeBlock = NULL;
|
|
800c540: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800c542: 2200 movs r2, #0
|
|
800c544: 601a str r2, [r3, #0]
|
|
xNumberOfSuccessfulAllocations++;
|
|
800c546: 4b16 ldr r3, [pc, #88] @ (800c5a0 <pvPortMalloc+0x1a4>)
|
|
800c548: 681b ldr r3, [r3, #0]
|
|
800c54a: 3301 adds r3, #1
|
|
800c54c: 4a14 ldr r2, [pc, #80] @ (800c5a0 <pvPortMalloc+0x1a4>)
|
|
800c54e: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
traceMALLOC( pvReturn, xWantedSize );
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
800c550: f7ff f834 bl 800b5bc <xTaskResumeAll>
|
|
|
|
#if( configUSE_MALLOC_FAILED_HOOK == 1 )
|
|
{
|
|
if( pvReturn == NULL )
|
|
800c554: 69fb ldr r3, [r7, #28]
|
|
800c556: 2b00 cmp r3, #0
|
|
800c558: d101 bne.n 800c55e <pvPortMalloc+0x162>
|
|
{
|
|
extern void vApplicationMallocFailedHook( void );
|
|
vApplicationMallocFailedHook();
|
|
800c55a: f7f3 fff1 bl 8000540 <vApplicationMallocFailedHook>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
|
|
800c55e: 69fb ldr r3, [r7, #28]
|
|
800c560: f003 0307 and.w r3, r3, #7
|
|
800c564: 2b00 cmp r3, #0
|
|
800c566: d00b beq.n 800c580 <pvPortMalloc+0x184>
|
|
__asm volatile
|
|
800c568: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c56c: f383 8811 msr BASEPRI, r3
|
|
800c570: f3bf 8f6f isb sy
|
|
800c574: f3bf 8f4f dsb sy
|
|
800c578: 60fb str r3, [r7, #12]
|
|
}
|
|
800c57a: bf00 nop
|
|
800c57c: bf00 nop
|
|
800c57e: e7fd b.n 800c57c <pvPortMalloc+0x180>
|
|
return pvReturn;
|
|
800c580: 69fb ldr r3, [r7, #28]
|
|
}
|
|
800c582: 4618 mov r0, r3
|
|
800c584: 3728 adds r7, #40 @ 0x28
|
|
800c586: 46bd mov sp, r7
|
|
800c588: bd80 pop {r7, pc}
|
|
800c58a: bf00 nop
|
|
800c58c: 200086e8 .word 0x200086e8
|
|
800c590: 200086fc .word 0x200086fc
|
|
800c594: 200086ec .word 0x200086ec
|
|
800c598: 200086e0 .word 0x200086e0
|
|
800c59c: 200086f0 .word 0x200086f0
|
|
800c5a0: 200086f4 .word 0x200086f4
|
|
|
|
0800c5a4 <vPortFree>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortFree( void *pv )
|
|
{
|
|
800c5a4: b580 push {r7, lr}
|
|
800c5a6: b086 sub sp, #24
|
|
800c5a8: af00 add r7, sp, #0
|
|
800c5aa: 6078 str r0, [r7, #4]
|
|
uint8_t *puc = ( uint8_t * ) pv;
|
|
800c5ac: 687b ldr r3, [r7, #4]
|
|
800c5ae: 617b str r3, [r7, #20]
|
|
BlockLink_t *pxLink;
|
|
|
|
if( pv != NULL )
|
|
800c5b0: 687b ldr r3, [r7, #4]
|
|
800c5b2: 2b00 cmp r3, #0
|
|
800c5b4: d04f beq.n 800c656 <vPortFree+0xb2>
|
|
{
|
|
/* The memory being freed will have an BlockLink_t structure immediately
|
|
before it. */
|
|
puc -= xHeapStructSize;
|
|
800c5b6: 2308 movs r3, #8
|
|
800c5b8: 425b negs r3, r3
|
|
800c5ba: 697a ldr r2, [r7, #20]
|
|
800c5bc: 4413 add r3, r2
|
|
800c5be: 617b str r3, [r7, #20]
|
|
|
|
/* This casting is to keep the compiler from issuing warnings. */
|
|
pxLink = ( void * ) puc;
|
|
800c5c0: 697b ldr r3, [r7, #20]
|
|
800c5c2: 613b str r3, [r7, #16]
|
|
|
|
/* Check the block is actually allocated. */
|
|
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
|
|
800c5c4: 693b ldr r3, [r7, #16]
|
|
800c5c6: 685a ldr r2, [r3, #4]
|
|
800c5c8: 4b25 ldr r3, [pc, #148] @ (800c660 <vPortFree+0xbc>)
|
|
800c5ca: 681b ldr r3, [r3, #0]
|
|
800c5cc: 4013 ands r3, r2
|
|
800c5ce: 2b00 cmp r3, #0
|
|
800c5d0: d10b bne.n 800c5ea <vPortFree+0x46>
|
|
__asm volatile
|
|
800c5d2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c5d6: f383 8811 msr BASEPRI, r3
|
|
800c5da: f3bf 8f6f isb sy
|
|
800c5de: f3bf 8f4f dsb sy
|
|
800c5e2: 60fb str r3, [r7, #12]
|
|
}
|
|
800c5e4: bf00 nop
|
|
800c5e6: bf00 nop
|
|
800c5e8: e7fd b.n 800c5e6 <vPortFree+0x42>
|
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
|
800c5ea: 693b ldr r3, [r7, #16]
|
|
800c5ec: 681b ldr r3, [r3, #0]
|
|
800c5ee: 2b00 cmp r3, #0
|
|
800c5f0: d00b beq.n 800c60a <vPortFree+0x66>
|
|
__asm volatile
|
|
800c5f2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800c5f6: f383 8811 msr BASEPRI, r3
|
|
800c5fa: f3bf 8f6f isb sy
|
|
800c5fe: f3bf 8f4f dsb sy
|
|
800c602: 60bb str r3, [r7, #8]
|
|
}
|
|
800c604: bf00 nop
|
|
800c606: bf00 nop
|
|
800c608: e7fd b.n 800c606 <vPortFree+0x62>
|
|
|
|
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
|
|
800c60a: 693b ldr r3, [r7, #16]
|
|
800c60c: 685a ldr r2, [r3, #4]
|
|
800c60e: 4b14 ldr r3, [pc, #80] @ (800c660 <vPortFree+0xbc>)
|
|
800c610: 681b ldr r3, [r3, #0]
|
|
800c612: 4013 ands r3, r2
|
|
800c614: 2b00 cmp r3, #0
|
|
800c616: d01e beq.n 800c656 <vPortFree+0xb2>
|
|
{
|
|
if( pxLink->pxNextFreeBlock == NULL )
|
|
800c618: 693b ldr r3, [r7, #16]
|
|
800c61a: 681b ldr r3, [r3, #0]
|
|
800c61c: 2b00 cmp r3, #0
|
|
800c61e: d11a bne.n 800c656 <vPortFree+0xb2>
|
|
{
|
|
/* The block is being returned to the heap - it is no longer
|
|
allocated. */
|
|
pxLink->xBlockSize &= ~xBlockAllocatedBit;
|
|
800c620: 693b ldr r3, [r7, #16]
|
|
800c622: 685a ldr r2, [r3, #4]
|
|
800c624: 4b0e ldr r3, [pc, #56] @ (800c660 <vPortFree+0xbc>)
|
|
800c626: 681b ldr r3, [r3, #0]
|
|
800c628: 43db mvns r3, r3
|
|
800c62a: 401a ands r2, r3
|
|
800c62c: 693b ldr r3, [r7, #16]
|
|
800c62e: 605a str r2, [r3, #4]
|
|
|
|
vTaskSuspendAll();
|
|
800c630: f7fe ffb6 bl 800b5a0 <vTaskSuspendAll>
|
|
{
|
|
/* Add this block to the list of free blocks. */
|
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
|
800c634: 693b ldr r3, [r7, #16]
|
|
800c636: 685a ldr r2, [r3, #4]
|
|
800c638: 4b0a ldr r3, [pc, #40] @ (800c664 <vPortFree+0xc0>)
|
|
800c63a: 681b ldr r3, [r3, #0]
|
|
800c63c: 4413 add r3, r2
|
|
800c63e: 4a09 ldr r2, [pc, #36] @ (800c664 <vPortFree+0xc0>)
|
|
800c640: 6013 str r3, [r2, #0]
|
|
traceFREE( pv, pxLink->xBlockSize );
|
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
|
800c642: 6938 ldr r0, [r7, #16]
|
|
800c644: f000 f874 bl 800c730 <prvInsertBlockIntoFreeList>
|
|
xNumberOfSuccessfulFrees++;
|
|
800c648: 4b07 ldr r3, [pc, #28] @ (800c668 <vPortFree+0xc4>)
|
|
800c64a: 681b ldr r3, [r3, #0]
|
|
800c64c: 3301 adds r3, #1
|
|
800c64e: 4a06 ldr r2, [pc, #24] @ (800c668 <vPortFree+0xc4>)
|
|
800c650: 6013 str r3, [r2, #0]
|
|
}
|
|
( void ) xTaskResumeAll();
|
|
800c652: f7fe ffb3 bl 800b5bc <xTaskResumeAll>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
800c656: bf00 nop
|
|
800c658: 3718 adds r7, #24
|
|
800c65a: 46bd mov sp, r7
|
|
800c65c: bd80 pop {r7, pc}
|
|
800c65e: bf00 nop
|
|
800c660: 200086fc .word 0x200086fc
|
|
800c664: 200086ec .word 0x200086ec
|
|
800c668: 200086f8 .word 0x200086f8
|
|
|
|
0800c66c <prvHeapInit>:
|
|
/* This just exists to keep the linker quiet. */
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvHeapInit( void )
|
|
{
|
|
800c66c: b480 push {r7}
|
|
800c66e: b085 sub sp, #20
|
|
800c670: af00 add r7, sp, #0
|
|
BlockLink_t *pxFirstFreeBlock;
|
|
uint8_t *pucAlignedHeap;
|
|
size_t uxAddress;
|
|
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
|
|
800c672: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
800c676: 60bb str r3, [r7, #8]
|
|
|
|
/* Ensure the heap starts on a correctly aligned boundary. */
|
|
uxAddress = ( size_t ) ucHeap;
|
|
800c678: 4b27 ldr r3, [pc, #156] @ (800c718 <prvHeapInit+0xac>)
|
|
800c67a: 60fb str r3, [r7, #12]
|
|
|
|
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
|
800c67c: 68fb ldr r3, [r7, #12]
|
|
800c67e: f003 0307 and.w r3, r3, #7
|
|
800c682: 2b00 cmp r3, #0
|
|
800c684: d00c beq.n 800c6a0 <prvHeapInit+0x34>
|
|
{
|
|
uxAddress += ( portBYTE_ALIGNMENT - 1 );
|
|
800c686: 68fb ldr r3, [r7, #12]
|
|
800c688: 3307 adds r3, #7
|
|
800c68a: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
800c68c: 68fb ldr r3, [r7, #12]
|
|
800c68e: f023 0307 bic.w r3, r3, #7
|
|
800c692: 60fb str r3, [r7, #12]
|
|
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
|
|
800c694: 68ba ldr r2, [r7, #8]
|
|
800c696: 68fb ldr r3, [r7, #12]
|
|
800c698: 1ad3 subs r3, r2, r3
|
|
800c69a: 4a1f ldr r2, [pc, #124] @ (800c718 <prvHeapInit+0xac>)
|
|
800c69c: 4413 add r3, r2
|
|
800c69e: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
pucAlignedHeap = ( uint8_t * ) uxAddress;
|
|
800c6a0: 68fb ldr r3, [r7, #12]
|
|
800c6a2: 607b str r3, [r7, #4]
|
|
|
|
/* xStart is used to hold a pointer to the first item in the list of free
|
|
blocks. The void cast is used to prevent compiler warnings. */
|
|
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
|
|
800c6a4: 4a1d ldr r2, [pc, #116] @ (800c71c <prvHeapInit+0xb0>)
|
|
800c6a6: 687b ldr r3, [r7, #4]
|
|
800c6a8: 6013 str r3, [r2, #0]
|
|
xStart.xBlockSize = ( size_t ) 0;
|
|
800c6aa: 4b1c ldr r3, [pc, #112] @ (800c71c <prvHeapInit+0xb0>)
|
|
800c6ac: 2200 movs r2, #0
|
|
800c6ae: 605a str r2, [r3, #4]
|
|
|
|
/* pxEnd is used to mark the end of the list of free blocks and is inserted
|
|
at the end of the heap space. */
|
|
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
|
|
800c6b0: 687b ldr r3, [r7, #4]
|
|
800c6b2: 68ba ldr r2, [r7, #8]
|
|
800c6b4: 4413 add r3, r2
|
|
800c6b6: 60fb str r3, [r7, #12]
|
|
uxAddress -= xHeapStructSize;
|
|
800c6b8: 2208 movs r2, #8
|
|
800c6ba: 68fb ldr r3, [r7, #12]
|
|
800c6bc: 1a9b subs r3, r3, r2
|
|
800c6be: 60fb str r3, [r7, #12]
|
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
|
800c6c0: 68fb ldr r3, [r7, #12]
|
|
800c6c2: f023 0307 bic.w r3, r3, #7
|
|
800c6c6: 60fb str r3, [r7, #12]
|
|
pxEnd = ( void * ) uxAddress;
|
|
800c6c8: 68fb ldr r3, [r7, #12]
|
|
800c6ca: 4a15 ldr r2, [pc, #84] @ (800c720 <prvHeapInit+0xb4>)
|
|
800c6cc: 6013 str r3, [r2, #0]
|
|
pxEnd->xBlockSize = 0;
|
|
800c6ce: 4b14 ldr r3, [pc, #80] @ (800c720 <prvHeapInit+0xb4>)
|
|
800c6d0: 681b ldr r3, [r3, #0]
|
|
800c6d2: 2200 movs r2, #0
|
|
800c6d4: 605a str r2, [r3, #4]
|
|
pxEnd->pxNextFreeBlock = NULL;
|
|
800c6d6: 4b12 ldr r3, [pc, #72] @ (800c720 <prvHeapInit+0xb4>)
|
|
800c6d8: 681b ldr r3, [r3, #0]
|
|
800c6da: 2200 movs r2, #0
|
|
800c6dc: 601a str r2, [r3, #0]
|
|
|
|
/* To start with there is a single free block that is sized to take up the
|
|
entire heap space, minus the space taken by pxEnd. */
|
|
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
|
|
800c6de: 687b ldr r3, [r7, #4]
|
|
800c6e0: 603b str r3, [r7, #0]
|
|
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
|
|
800c6e2: 683b ldr r3, [r7, #0]
|
|
800c6e4: 68fa ldr r2, [r7, #12]
|
|
800c6e6: 1ad2 subs r2, r2, r3
|
|
800c6e8: 683b ldr r3, [r7, #0]
|
|
800c6ea: 605a str r2, [r3, #4]
|
|
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
|
|
800c6ec: 4b0c ldr r3, [pc, #48] @ (800c720 <prvHeapInit+0xb4>)
|
|
800c6ee: 681a ldr r2, [r3, #0]
|
|
800c6f0: 683b ldr r3, [r7, #0]
|
|
800c6f2: 601a str r2, [r3, #0]
|
|
|
|
/* Only one block exists - and it covers the entire usable heap space. */
|
|
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
800c6f4: 683b ldr r3, [r7, #0]
|
|
800c6f6: 685b ldr r3, [r3, #4]
|
|
800c6f8: 4a0a ldr r2, [pc, #40] @ (800c724 <prvHeapInit+0xb8>)
|
|
800c6fa: 6013 str r3, [r2, #0]
|
|
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
|
800c6fc: 683b ldr r3, [r7, #0]
|
|
800c6fe: 685b ldr r3, [r3, #4]
|
|
800c700: 4a09 ldr r2, [pc, #36] @ (800c728 <prvHeapInit+0xbc>)
|
|
800c702: 6013 str r3, [r2, #0]
|
|
|
|
/* Work out the position of the top bit in a size_t variable. */
|
|
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
|
|
800c704: 4b09 ldr r3, [pc, #36] @ (800c72c <prvHeapInit+0xc0>)
|
|
800c706: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
|
|
800c70a: 601a str r2, [r3, #0]
|
|
}
|
|
800c70c: bf00 nop
|
|
800c70e: 3714 adds r7, #20
|
|
800c710: 46bd mov sp, r7
|
|
800c712: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c716: 4770 bx lr
|
|
800c718: 200006e0 .word 0x200006e0
|
|
800c71c: 200086e0 .word 0x200086e0
|
|
800c720: 200086e8 .word 0x200086e8
|
|
800c724: 200086f0 .word 0x200086f0
|
|
800c728: 200086ec .word 0x200086ec
|
|
800c72c: 200086fc .word 0x200086fc
|
|
|
|
0800c730 <prvInsertBlockIntoFreeList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
|
|
{
|
|
800c730: b480 push {r7}
|
|
800c732: b085 sub sp, #20
|
|
800c734: af00 add r7, sp, #0
|
|
800c736: 6078 str r0, [r7, #4]
|
|
BlockLink_t *pxIterator;
|
|
uint8_t *puc;
|
|
|
|
/* Iterate through the list until a block is found that has a higher address
|
|
than the block being inserted. */
|
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
|
800c738: 4b28 ldr r3, [pc, #160] @ (800c7dc <prvInsertBlockIntoFreeList+0xac>)
|
|
800c73a: 60fb str r3, [r7, #12]
|
|
800c73c: e002 b.n 800c744 <prvInsertBlockIntoFreeList+0x14>
|
|
800c73e: 68fb ldr r3, [r7, #12]
|
|
800c740: 681b ldr r3, [r3, #0]
|
|
800c742: 60fb str r3, [r7, #12]
|
|
800c744: 68fb ldr r3, [r7, #12]
|
|
800c746: 681b ldr r3, [r3, #0]
|
|
800c748: 687a ldr r2, [r7, #4]
|
|
800c74a: 429a cmp r2, r3
|
|
800c74c: d8f7 bhi.n 800c73e <prvInsertBlockIntoFreeList+0xe>
|
|
/* Nothing to do here, just iterate to the right position. */
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted after
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxIterator;
|
|
800c74e: 68fb ldr r3, [r7, #12]
|
|
800c750: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
|
800c752: 68fb ldr r3, [r7, #12]
|
|
800c754: 685b ldr r3, [r3, #4]
|
|
800c756: 68ba ldr r2, [r7, #8]
|
|
800c758: 4413 add r3, r2
|
|
800c75a: 687a ldr r2, [r7, #4]
|
|
800c75c: 429a cmp r2, r3
|
|
800c75e: d108 bne.n 800c772 <prvInsertBlockIntoFreeList+0x42>
|
|
{
|
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
|
800c760: 68fb ldr r3, [r7, #12]
|
|
800c762: 685a ldr r2, [r3, #4]
|
|
800c764: 687b ldr r3, [r7, #4]
|
|
800c766: 685b ldr r3, [r3, #4]
|
|
800c768: 441a add r2, r3
|
|
800c76a: 68fb ldr r3, [r7, #12]
|
|
800c76c: 605a str r2, [r3, #4]
|
|
pxBlockToInsert = pxIterator;
|
|
800c76e: 68fb ldr r3, [r7, #12]
|
|
800c770: 607b str r3, [r7, #4]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Do the block being inserted, and the block it is being inserted before
|
|
make a contiguous block of memory? */
|
|
puc = ( uint8_t * ) pxBlockToInsert;
|
|
800c772: 687b ldr r3, [r7, #4]
|
|
800c774: 60bb str r3, [r7, #8]
|
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
|
800c776: 687b ldr r3, [r7, #4]
|
|
800c778: 685b ldr r3, [r3, #4]
|
|
800c77a: 68ba ldr r2, [r7, #8]
|
|
800c77c: 441a add r2, r3
|
|
800c77e: 68fb ldr r3, [r7, #12]
|
|
800c780: 681b ldr r3, [r3, #0]
|
|
800c782: 429a cmp r2, r3
|
|
800c784: d118 bne.n 800c7b8 <prvInsertBlockIntoFreeList+0x88>
|
|
{
|
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
|
800c786: 68fb ldr r3, [r7, #12]
|
|
800c788: 681a ldr r2, [r3, #0]
|
|
800c78a: 4b15 ldr r3, [pc, #84] @ (800c7e0 <prvInsertBlockIntoFreeList+0xb0>)
|
|
800c78c: 681b ldr r3, [r3, #0]
|
|
800c78e: 429a cmp r2, r3
|
|
800c790: d00d beq.n 800c7ae <prvInsertBlockIntoFreeList+0x7e>
|
|
{
|
|
/* Form one big block from the two blocks. */
|
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
|
800c792: 687b ldr r3, [r7, #4]
|
|
800c794: 685a ldr r2, [r3, #4]
|
|
800c796: 68fb ldr r3, [r7, #12]
|
|
800c798: 681b ldr r3, [r3, #0]
|
|
800c79a: 685b ldr r3, [r3, #4]
|
|
800c79c: 441a add r2, r3
|
|
800c79e: 687b ldr r3, [r7, #4]
|
|
800c7a0: 605a str r2, [r3, #4]
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
|
800c7a2: 68fb ldr r3, [r7, #12]
|
|
800c7a4: 681b ldr r3, [r3, #0]
|
|
800c7a6: 681a ldr r2, [r3, #0]
|
|
800c7a8: 687b ldr r3, [r7, #4]
|
|
800c7aa: 601a str r2, [r3, #0]
|
|
800c7ac: e008 b.n 800c7c0 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
|
800c7ae: 4b0c ldr r3, [pc, #48] @ (800c7e0 <prvInsertBlockIntoFreeList+0xb0>)
|
|
800c7b0: 681a ldr r2, [r3, #0]
|
|
800c7b2: 687b ldr r3, [r7, #4]
|
|
800c7b4: 601a str r2, [r3, #0]
|
|
800c7b6: e003 b.n 800c7c0 <prvInsertBlockIntoFreeList+0x90>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
|
800c7b8: 68fb ldr r3, [r7, #12]
|
|
800c7ba: 681a ldr r2, [r3, #0]
|
|
800c7bc: 687b ldr r3, [r7, #4]
|
|
800c7be: 601a str r2, [r3, #0]
|
|
|
|
/* If the block being inserted plugged a gab, so was merged with the block
|
|
before and the block after, then it's pxNextFreeBlock pointer will have
|
|
already been set, and should not be set here as that would make it point
|
|
to itself. */
|
|
if( pxIterator != pxBlockToInsert )
|
|
800c7c0: 68fa ldr r2, [r7, #12]
|
|
800c7c2: 687b ldr r3, [r7, #4]
|
|
800c7c4: 429a cmp r2, r3
|
|
800c7c6: d002 beq.n 800c7ce <prvInsertBlockIntoFreeList+0x9e>
|
|
{
|
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
|
800c7c8: 68fb ldr r3, [r7, #12]
|
|
800c7ca: 687a ldr r2, [r7, #4]
|
|
800c7cc: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
800c7ce: bf00 nop
|
|
800c7d0: 3714 adds r7, #20
|
|
800c7d2: 46bd mov sp, r7
|
|
800c7d4: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c7d8: 4770 bx lr
|
|
800c7da: bf00 nop
|
|
800c7dc: 200086e0 .word 0x200086e0
|
|
800c7e0: 200086e8 .word 0x200086e8
|
|
|
|
0800c7e4 <MX_USB_HOST_Init>:
|
|
/**
|
|
* Init USB host library, add supported class and start the library
|
|
* @retval None
|
|
*/
|
|
void MX_USB_HOST_Init(void)
|
|
{
|
|
800c7e4: b580 push {r7, lr}
|
|
800c7e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USB_HOST_Init_PreTreatment */
|
|
|
|
/* USER CODE END USB_HOST_Init_PreTreatment */
|
|
|
|
/* Init host Library, add supported class and start the library. */
|
|
if (USBH_Init(&hUsbHostHS, USBH_UserProcess, HOST_HS) != USBH_OK)
|
|
800c7e8: 2200 movs r2, #0
|
|
800c7ea: 490e ldr r1, [pc, #56] @ (800c824 <MX_USB_HOST_Init+0x40>)
|
|
800c7ec: 480e ldr r0, [pc, #56] @ (800c828 <MX_USB_HOST_Init+0x44>)
|
|
800c7ee: f7fb feb1 bl 8008554 <USBH_Init>
|
|
800c7f2: 4603 mov r3, r0
|
|
800c7f4: 2b00 cmp r3, #0
|
|
800c7f6: d001 beq.n 800c7fc <MX_USB_HOST_Init+0x18>
|
|
{
|
|
Error_Handler();
|
|
800c7f8: f7f4 faa4 bl 8000d44 <Error_Handler>
|
|
}
|
|
if (USBH_RegisterClass(&hUsbHostHS, USBH_CDC_CLASS) != USBH_OK)
|
|
800c7fc: 490b ldr r1, [pc, #44] @ (800c82c <MX_USB_HOST_Init+0x48>)
|
|
800c7fe: 480a ldr r0, [pc, #40] @ (800c828 <MX_USB_HOST_Init+0x44>)
|
|
800c800: f7fb ff7b bl 80086fa <USBH_RegisterClass>
|
|
800c804: 4603 mov r3, r0
|
|
800c806: 2b00 cmp r3, #0
|
|
800c808: d001 beq.n 800c80e <MX_USB_HOST_Init+0x2a>
|
|
{
|
|
Error_Handler();
|
|
800c80a: f7f4 fa9b bl 8000d44 <Error_Handler>
|
|
}
|
|
if (USBH_Start(&hUsbHostHS) != USBH_OK)
|
|
800c80e: 4806 ldr r0, [pc, #24] @ (800c828 <MX_USB_HOST_Init+0x44>)
|
|
800c810: f7fb ffff bl 8008812 <USBH_Start>
|
|
800c814: 4603 mov r3, r0
|
|
800c816: 2b00 cmp r3, #0
|
|
800c818: d001 beq.n 800c81e <MX_USB_HOST_Init+0x3a>
|
|
{
|
|
Error_Handler();
|
|
800c81a: f7f4 fa93 bl 8000d44 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USB_HOST_Init_PostTreatment */
|
|
|
|
/* USER CODE END USB_HOST_Init_PostTreatment */
|
|
}
|
|
800c81e: bf00 nop
|
|
800c820: bd80 pop {r7, pc}
|
|
800c822: bf00 nop
|
|
800c824: 0800c831 .word 0x0800c831
|
|
800c828: 20008700 .word 0x20008700
|
|
800c82c: 2000000c .word 0x2000000c
|
|
|
|
0800c830 <USBH_UserProcess>:
|
|
|
|
/*
|
|
* user callback definition
|
|
*/
|
|
static void USBH_UserProcess (USBH_HandleTypeDef *phost, uint8_t id)
|
|
{
|
|
800c830: b480 push {r7}
|
|
800c832: b083 sub sp, #12
|
|
800c834: af00 add r7, sp, #0
|
|
800c836: 6078 str r0, [r7, #4]
|
|
800c838: 460b mov r3, r1
|
|
800c83a: 70fb strb r3, [r7, #3]
|
|
/* USER CODE BEGIN CALL_BACK_1 */
|
|
switch(id)
|
|
800c83c: 78fb ldrb r3, [r7, #3]
|
|
800c83e: 3b01 subs r3, #1
|
|
800c840: 2b04 cmp r3, #4
|
|
800c842: d819 bhi.n 800c878 <USBH_UserProcess+0x48>
|
|
800c844: a201 add r2, pc, #4 @ (adr r2, 800c84c <USBH_UserProcess+0x1c>)
|
|
800c846: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800c84a: bf00 nop
|
|
800c84c: 0800c879 .word 0x0800c879
|
|
800c850: 0800c869 .word 0x0800c869
|
|
800c854: 0800c879 .word 0x0800c879
|
|
800c858: 0800c871 .word 0x0800c871
|
|
800c85c: 0800c861 .word 0x0800c861
|
|
{
|
|
case HOST_USER_SELECT_CONFIGURATION:
|
|
break;
|
|
|
|
case HOST_USER_DISCONNECTION:
|
|
Appli_state = APPLICATION_DISCONNECT;
|
|
800c860: 4b09 ldr r3, [pc, #36] @ (800c888 <USBH_UserProcess+0x58>)
|
|
800c862: 2203 movs r2, #3
|
|
800c864: 701a strb r2, [r3, #0]
|
|
break;
|
|
800c866: e008 b.n 800c87a <USBH_UserProcess+0x4a>
|
|
|
|
case HOST_USER_CLASS_ACTIVE:
|
|
Appli_state = APPLICATION_READY;
|
|
800c868: 4b07 ldr r3, [pc, #28] @ (800c888 <USBH_UserProcess+0x58>)
|
|
800c86a: 2202 movs r2, #2
|
|
800c86c: 701a strb r2, [r3, #0]
|
|
break;
|
|
800c86e: e004 b.n 800c87a <USBH_UserProcess+0x4a>
|
|
|
|
case HOST_USER_CONNECTION:
|
|
Appli_state = APPLICATION_START;
|
|
800c870: 4b05 ldr r3, [pc, #20] @ (800c888 <USBH_UserProcess+0x58>)
|
|
800c872: 2201 movs r2, #1
|
|
800c874: 701a strb r2, [r3, #0]
|
|
break;
|
|
800c876: e000 b.n 800c87a <USBH_UserProcess+0x4a>
|
|
|
|
default:
|
|
break;
|
|
800c878: bf00 nop
|
|
}
|
|
/* USER CODE END CALL_BACK_1 */
|
|
}
|
|
800c87a: bf00 nop
|
|
800c87c: 370c adds r7, #12
|
|
800c87e: 46bd mov sp, r7
|
|
800c880: f85d 7b04 ldr.w r7, [sp], #4
|
|
800c884: 4770 bx lr
|
|
800c886: bf00 nop
|
|
800c888: 20008ae4 .word 0x20008ae4
|
|
|
|
0800c88c <HAL_HCD_MspInit>:
|
|
LL Driver Callbacks (HCD -> USB Host Library)
|
|
*******************************************************************************/
|
|
/* MSP Init */
|
|
|
|
void HAL_HCD_MspInit(HCD_HandleTypeDef* hcdHandle)
|
|
{
|
|
800c88c: b580 push {r7, lr}
|
|
800c88e: b08a sub sp, #40 @ 0x28
|
|
800c890: af00 add r7, sp, #0
|
|
800c892: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800c894: f107 0314 add.w r3, r7, #20
|
|
800c898: 2200 movs r2, #0
|
|
800c89a: 601a str r2, [r3, #0]
|
|
800c89c: 605a str r2, [r3, #4]
|
|
800c89e: 609a str r2, [r3, #8]
|
|
800c8a0: 60da str r2, [r3, #12]
|
|
800c8a2: 611a str r2, [r3, #16]
|
|
if(hcdHandle->Instance==USB_OTG_HS)
|
|
800c8a4: 687b ldr r3, [r7, #4]
|
|
800c8a6: 681b ldr r3, [r3, #0]
|
|
800c8a8: 4a24 ldr r2, [pc, #144] @ (800c93c <HAL_HCD_MspInit+0xb0>)
|
|
800c8aa: 4293 cmp r3, r2
|
|
800c8ac: d141 bne.n 800c932 <HAL_HCD_MspInit+0xa6>
|
|
{
|
|
/* USER CODE BEGIN USB_OTG_HS_MspInit 0 */
|
|
|
|
/* USER CODE END USB_OTG_HS_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
800c8ae: 2300 movs r3, #0
|
|
800c8b0: 613b str r3, [r7, #16]
|
|
800c8b2: 4b23 ldr r3, [pc, #140] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c8b4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c8b6: 4a22 ldr r2, [pc, #136] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c8b8: f043 0302 orr.w r3, r3, #2
|
|
800c8bc: 6313 str r3, [r2, #48] @ 0x30
|
|
800c8be: 4b20 ldr r3, [pc, #128] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c8c0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c8c2: f003 0302 and.w r3, r3, #2
|
|
800c8c6: 613b str r3, [r7, #16]
|
|
800c8c8: 693b ldr r3, [r7, #16]
|
|
PB12 ------> USB_OTG_HS_ID
|
|
PB13 ------> USB_OTG_HS_VBUS
|
|
PB14 ------> USB_OTG_HS_DM
|
|
PB15 ------> USB_OTG_HS_DP
|
|
*/
|
|
GPIO_InitStruct.Pin = OTG_HS_ID_Pin|OTG_HS_DM_Pin|OTG_HS_DP_Pin;
|
|
800c8ca: f44f 4350 mov.w r3, #53248 @ 0xd000
|
|
800c8ce: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800c8d0: 2302 movs r3, #2
|
|
800c8d2: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800c8d4: 2300 movs r3, #0
|
|
800c8d6: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800c8d8: 2300 movs r3, #0
|
|
800c8da: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_OTG_HS_FS;
|
|
800c8dc: 230c movs r3, #12
|
|
800c8de: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
800c8e0: f107 0314 add.w r3, r7, #20
|
|
800c8e4: 4619 mov r1, r3
|
|
800c8e6: 4817 ldr r0, [pc, #92] @ (800c944 <HAL_HCD_MspInit+0xb8>)
|
|
800c8e8: f7f5 fa12 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = VBUS_HS_Pin;
|
|
800c8ec: f44f 5300 mov.w r3, #8192 @ 0x2000
|
|
800c8f0: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
800c8f2: 2300 movs r3, #0
|
|
800c8f4: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800c8f6: 2300 movs r3, #0
|
|
800c8f8: 61fb str r3, [r7, #28]
|
|
HAL_GPIO_Init(VBUS_HS_GPIO_Port, &GPIO_InitStruct);
|
|
800c8fa: f107 0314 add.w r3, r7, #20
|
|
800c8fe: 4619 mov r1, r3
|
|
800c900: 4810 ldr r0, [pc, #64] @ (800c944 <HAL_HCD_MspInit+0xb8>)
|
|
800c902: f7f5 fa05 bl 8001d10 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USB_OTG_HS_CLK_ENABLE();
|
|
800c906: 2300 movs r3, #0
|
|
800c908: 60fb str r3, [r7, #12]
|
|
800c90a: 4b0d ldr r3, [pc, #52] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c90c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c90e: 4a0c ldr r2, [pc, #48] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c910: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
800c914: 6313 str r3, [r2, #48] @ 0x30
|
|
800c916: 4b0a ldr r3, [pc, #40] @ (800c940 <HAL_HCD_MspInit+0xb4>)
|
|
800c918: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800c91a: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
800c91e: 60fb str r3, [r7, #12]
|
|
800c920: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Peripheral interrupt init */
|
|
HAL_NVIC_SetPriority(OTG_HS_IRQn, 5, 0);
|
|
800c922: 2200 movs r2, #0
|
|
800c924: 2105 movs r1, #5
|
|
800c926: 204d movs r0, #77 @ 0x4d
|
|
800c928: f7f4 ffc0 bl 80018ac <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(OTG_HS_IRQn);
|
|
800c92c: 204d movs r0, #77 @ 0x4d
|
|
800c92e: f7f4 ffd9 bl 80018e4 <HAL_NVIC_EnableIRQ>
|
|
/* USER CODE BEGIN USB_OTG_HS_MspInit 1 */
|
|
|
|
/* USER CODE END USB_OTG_HS_MspInit 1 */
|
|
}
|
|
}
|
|
800c932: bf00 nop
|
|
800c934: 3728 adds r7, #40 @ 0x28
|
|
800c936: 46bd mov sp, r7
|
|
800c938: bd80 pop {r7, pc}
|
|
800c93a: bf00 nop
|
|
800c93c: 40040000 .word 0x40040000
|
|
800c940: 40023800 .word 0x40023800
|
|
800c944: 40020400 .word 0x40020400
|
|
|
|
0800c948 <HAL_HCD_SOF_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800c948: b580 push {r7, lr}
|
|
800c94a: b082 sub sp, #8
|
|
800c94c: af00 add r7, sp, #0
|
|
800c94e: 6078 str r0, [r7, #4]
|
|
USBH_LL_IncTimer(hhcd->pData);
|
|
800c950: 687b ldr r3, [r7, #4]
|
|
800c952: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c956: 4618 mov r0, r3
|
|
800c958: f7fc fb93 bl 8009082 <USBH_LL_IncTimer>
|
|
}
|
|
800c95c: bf00 nop
|
|
800c95e: 3708 adds r7, #8
|
|
800c960: 46bd mov sp, r7
|
|
800c962: bd80 pop {r7, pc}
|
|
|
|
0800c964 <HAL_HCD_Connect_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800c964: b580 push {r7, lr}
|
|
800c966: b082 sub sp, #8
|
|
800c968: af00 add r7, sp, #0
|
|
800c96a: 6078 str r0, [r7, #4]
|
|
USBH_LL_Connect(hhcd->pData);
|
|
800c96c: 687b ldr r3, [r7, #4]
|
|
800c96e: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c972: 4618 mov r0, r3
|
|
800c974: f7fc fbd3 bl 800911e <USBH_LL_Connect>
|
|
}
|
|
800c978: bf00 nop
|
|
800c97a: 3708 adds r7, #8
|
|
800c97c: 46bd mov sp, r7
|
|
800c97e: bd80 pop {r7, pc}
|
|
|
|
0800c980 <HAL_HCD_Disconnect_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800c980: b580 push {r7, lr}
|
|
800c982: b082 sub sp, #8
|
|
800c984: af00 add r7, sp, #0
|
|
800c986: 6078 str r0, [r7, #4]
|
|
USBH_LL_Disconnect(hhcd->pData);
|
|
800c988: 687b ldr r3, [r7, #4]
|
|
800c98a: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c98e: 4618 mov r0, r3
|
|
800c990: f7fc fbe0 bl 8009154 <USBH_LL_Disconnect>
|
|
}
|
|
800c994: bf00 nop
|
|
800c996: 3708 adds r7, #8
|
|
800c998: 46bd mov sp, r7
|
|
800c99a: bd80 pop {r7, pc}
|
|
|
|
0800c99c <HAL_HCD_HC_NotifyURBChange_Callback>:
|
|
* @param chnum: channel number
|
|
* @param urb_state: state
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
|
|
{
|
|
800c99c: b580 push {r7, lr}
|
|
800c99e: b082 sub sp, #8
|
|
800c9a0: af00 add r7, sp, #0
|
|
800c9a2: 6078 str r0, [r7, #4]
|
|
800c9a4: 460b mov r3, r1
|
|
800c9a6: 70fb strb r3, [r7, #3]
|
|
800c9a8: 4613 mov r3, r2
|
|
800c9aa: 70bb strb r3, [r7, #2]
|
|
/* To be used with OS to sync URB state with the global state machine */
|
|
#if (USBH_USE_OS == 1)
|
|
USBH_LL_NotifyURBChange(hhcd->pData);
|
|
800c9ac: 687b ldr r3, [r7, #4]
|
|
800c9ae: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c9b2: 4618 mov r0, r3
|
|
800c9b4: f7fc fc34 bl 8009220 <USBH_LL_NotifyURBChange>
|
|
#endif
|
|
}
|
|
800c9b8: bf00 nop
|
|
800c9ba: 3708 adds r7, #8
|
|
800c9bc: 46bd mov sp, r7
|
|
800c9be: bd80 pop {r7, pc}
|
|
|
|
0800c9c0 <HAL_HCD_PortEnabled_Callback>:
|
|
* @brief Port Port Enabled callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800c9c0: b580 push {r7, lr}
|
|
800c9c2: b082 sub sp, #8
|
|
800c9c4: af00 add r7, sp, #0
|
|
800c9c6: 6078 str r0, [r7, #4]
|
|
USBH_LL_PortEnabled(hhcd->pData);
|
|
800c9c8: 687b ldr r3, [r7, #4]
|
|
800c9ca: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c9ce: 4618 mov r0, r3
|
|
800c9d0: f7fc fb81 bl 80090d6 <USBH_LL_PortEnabled>
|
|
}
|
|
800c9d4: bf00 nop
|
|
800c9d6: 3708 adds r7, #8
|
|
800c9d8: 46bd mov sp, r7
|
|
800c9da: bd80 pop {r7, pc}
|
|
|
|
0800c9dc <HAL_HCD_PortDisabled_Callback>:
|
|
* @brief Port Port Disabled callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
800c9dc: b580 push {r7, lr}
|
|
800c9de: b082 sub sp, #8
|
|
800c9e0: af00 add r7, sp, #0
|
|
800c9e2: 6078 str r0, [r7, #4]
|
|
USBH_LL_PortDisabled(hhcd->pData);
|
|
800c9e4: 687b ldr r3, [r7, #4]
|
|
800c9e6: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
800c9ea: 4618 mov r0, r3
|
|
800c9ec: f7fc fb85 bl 80090fa <USBH_LL_PortDisabled>
|
|
}
|
|
800c9f0: bf00 nop
|
|
800c9f2: 3708 adds r7, #8
|
|
800c9f4: 46bd mov sp, r7
|
|
800c9f6: bd80 pop {r7, pc}
|
|
|
|
0800c9f8 <USBH_LL_Init>:
|
|
* @brief Initialize the low level portion of the host driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Init(USBH_HandleTypeDef *phost)
|
|
{
|
|
800c9f8: b580 push {r7, lr}
|
|
800c9fa: b082 sub sp, #8
|
|
800c9fc: af00 add r7, sp, #0
|
|
800c9fe: 6078 str r0, [r7, #4]
|
|
/* Init USB_IP */
|
|
if (phost->id == HOST_HS) {
|
|
800ca00: 687b ldr r3, [r7, #4]
|
|
800ca02: f893 33cc ldrb.w r3, [r3, #972] @ 0x3cc
|
|
800ca06: 2b00 cmp r3, #0
|
|
800ca08: d132 bne.n 800ca70 <USBH_LL_Init+0x78>
|
|
/* Link the driver to the stack. */
|
|
hhcd_USB_OTG_HS.pData = phost;
|
|
800ca0a: 4a1c ldr r2, [pc, #112] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca0c: 687b ldr r3, [r7, #4]
|
|
800ca0e: f8c2 33dc str.w r3, [r2, #988] @ 0x3dc
|
|
phost->pData = &hhcd_USB_OTG_HS;
|
|
800ca12: 687b ldr r3, [r7, #4]
|
|
800ca14: 4a19 ldr r2, [pc, #100] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca16: f8c3 23d0 str.w r2, [r3, #976] @ 0x3d0
|
|
|
|
hhcd_USB_OTG_HS.Instance = USB_OTG_HS;
|
|
800ca1a: 4b18 ldr r3, [pc, #96] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca1c: 4a18 ldr r2, [pc, #96] @ (800ca80 <USBH_LL_Init+0x88>)
|
|
800ca1e: 601a str r2, [r3, #0]
|
|
hhcd_USB_OTG_HS.Init.Host_channels = 12;
|
|
800ca20: 4b16 ldr r3, [pc, #88] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca22: 220c movs r2, #12
|
|
800ca24: 715a strb r2, [r3, #5]
|
|
hhcd_USB_OTG_HS.Init.speed = HCD_SPEED_FULL;
|
|
800ca26: 4b15 ldr r3, [pc, #84] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca28: 2201 movs r2, #1
|
|
800ca2a: 71da strb r2, [r3, #7]
|
|
hhcd_USB_OTG_HS.Init.dma_enable = DISABLE;
|
|
800ca2c: 4b13 ldr r3, [pc, #76] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca2e: 2200 movs r2, #0
|
|
800ca30: 719a strb r2, [r3, #6]
|
|
hhcd_USB_OTG_HS.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
|
|
800ca32: 4b12 ldr r3, [pc, #72] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca34: 2202 movs r2, #2
|
|
800ca36: 725a strb r2, [r3, #9]
|
|
hhcd_USB_OTG_HS.Init.Sof_enable = DISABLE;
|
|
800ca38: 4b10 ldr r3, [pc, #64] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca3a: 2200 movs r2, #0
|
|
800ca3c: 729a strb r2, [r3, #10]
|
|
hhcd_USB_OTG_HS.Init.low_power_enable = DISABLE;
|
|
800ca3e: 4b0f ldr r3, [pc, #60] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca40: 2200 movs r2, #0
|
|
800ca42: 72da strb r2, [r3, #11]
|
|
hhcd_USB_OTG_HS.Init.vbus_sensing_enable = DISABLE;
|
|
800ca44: 4b0d ldr r3, [pc, #52] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca46: 2200 movs r2, #0
|
|
800ca48: 739a strb r2, [r3, #14]
|
|
hhcd_USB_OTG_HS.Init.use_external_vbus = DISABLE;
|
|
800ca4a: 4b0c ldr r3, [pc, #48] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca4c: 2200 movs r2, #0
|
|
800ca4e: 741a strb r2, [r3, #16]
|
|
if (HAL_HCD_Init(&hhcd_USB_OTG_HS) != HAL_OK)
|
|
800ca50: 480a ldr r0, [pc, #40] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca52: f7f5 fb3c bl 80020ce <HAL_HCD_Init>
|
|
800ca56: 4603 mov r3, r0
|
|
800ca58: 2b00 cmp r3, #0
|
|
800ca5a: d001 beq.n 800ca60 <USBH_LL_Init+0x68>
|
|
{
|
|
Error_Handler( );
|
|
800ca5c: f7f4 f972 bl 8000d44 <Error_Handler>
|
|
}
|
|
|
|
USBH_LL_SetTimer(phost, HAL_HCD_GetCurrentFrame(&hhcd_USB_OTG_HS));
|
|
800ca60: 4806 ldr r0, [pc, #24] @ (800ca7c <USBH_LL_Init+0x84>)
|
|
800ca62: f7f5 ff79 bl 8002958 <HAL_HCD_GetCurrentFrame>
|
|
800ca66: 4603 mov r3, r0
|
|
800ca68: 4619 mov r1, r3
|
|
800ca6a: 6878 ldr r0, [r7, #4]
|
|
800ca6c: f7fc fafa bl 8009064 <USBH_LL_SetTimer>
|
|
}
|
|
return USBH_OK;
|
|
800ca70: 2300 movs r3, #0
|
|
}
|
|
800ca72: 4618 mov r0, r3
|
|
800ca74: 3708 adds r7, #8
|
|
800ca76: 46bd mov sp, r7
|
|
800ca78: bd80 pop {r7, pc}
|
|
800ca7a: bf00 nop
|
|
800ca7c: 20008ae8 .word 0x20008ae8
|
|
800ca80: 40040000 .word 0x40040000
|
|
|
|
0800ca84 <USBH_LL_Start>:
|
|
* @brief Start the low level portion of the host driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Start(USBH_HandleTypeDef *phost)
|
|
{
|
|
800ca84: b580 push {r7, lr}
|
|
800ca86: b084 sub sp, #16
|
|
800ca88: af00 add r7, sp, #0
|
|
800ca8a: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800ca8c: 2300 movs r3, #0
|
|
800ca8e: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800ca90: 2300 movs r3, #0
|
|
800ca92: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_Start(phost->pData);
|
|
800ca94: 687b ldr r3, [r7, #4]
|
|
800ca96: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800ca9a: 4618 mov r0, r3
|
|
800ca9c: f7f5 fee4 bl 8002868 <HAL_HCD_Start>
|
|
800caa0: 4603 mov r3, r0
|
|
800caa2: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
800caa4: 7bfb ldrb r3, [r7, #15]
|
|
800caa6: 4618 mov r0, r3
|
|
800caa8: f000 f94c bl 800cd44 <USBH_Get_USB_Status>
|
|
800caac: 4603 mov r3, r0
|
|
800caae: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800cab0: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800cab2: 4618 mov r0, r3
|
|
800cab4: 3710 adds r7, #16
|
|
800cab6: 46bd mov sp, r7
|
|
800cab8: bd80 pop {r7, pc}
|
|
|
|
0800caba <USBH_LL_Stop>:
|
|
* @brief Stop the low level portion of the host driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost)
|
|
{
|
|
800caba: b580 push {r7, lr}
|
|
800cabc: b084 sub sp, #16
|
|
800cabe: af00 add r7, sp, #0
|
|
800cac0: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800cac2: 2300 movs r3, #0
|
|
800cac4: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800cac6: 2300 movs r3, #0
|
|
800cac8: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_Stop(phost->pData);
|
|
800caca: 687b ldr r3, [r7, #4]
|
|
800cacc: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800cad0: 4618 mov r0, r3
|
|
800cad2: f7f5 feec bl 80028ae <HAL_HCD_Stop>
|
|
800cad6: 4603 mov r3, r0
|
|
800cad8: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
800cada: 7bfb ldrb r3, [r7, #15]
|
|
800cadc: 4618 mov r0, r3
|
|
800cade: f000 f931 bl 800cd44 <USBH_Get_USB_Status>
|
|
800cae2: 4603 mov r3, r0
|
|
800cae4: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800cae6: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800cae8: 4618 mov r0, r3
|
|
800caea: 3710 adds r7, #16
|
|
800caec: 46bd mov sp, r7
|
|
800caee: bd80 pop {r7, pc}
|
|
|
|
0800caf0 <USBH_LL_GetSpeed>:
|
|
* @brief Return the USB host speed from the low level driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH speeds
|
|
*/
|
|
USBH_SpeedTypeDef USBH_LL_GetSpeed(USBH_HandleTypeDef *phost)
|
|
{
|
|
800caf0: b580 push {r7, lr}
|
|
800caf2: b084 sub sp, #16
|
|
800caf4: af00 add r7, sp, #0
|
|
800caf6: 6078 str r0, [r7, #4]
|
|
USBH_SpeedTypeDef speed = USBH_SPEED_FULL;
|
|
800caf8: 2301 movs r3, #1
|
|
800cafa: 73fb strb r3, [r7, #15]
|
|
|
|
switch (HAL_HCD_GetCurrentSpeed(phost->pData))
|
|
800cafc: 687b ldr r3, [r7, #4]
|
|
800cafe: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800cb02: 4618 mov r0, r3
|
|
800cb04: f7f5 ff36 bl 8002974 <HAL_HCD_GetCurrentSpeed>
|
|
800cb08: 4603 mov r3, r0
|
|
800cb0a: 2b02 cmp r3, #2
|
|
800cb0c: d00c beq.n 800cb28 <USBH_LL_GetSpeed+0x38>
|
|
800cb0e: 2b02 cmp r3, #2
|
|
800cb10: d80d bhi.n 800cb2e <USBH_LL_GetSpeed+0x3e>
|
|
800cb12: 2b00 cmp r3, #0
|
|
800cb14: d002 beq.n 800cb1c <USBH_LL_GetSpeed+0x2c>
|
|
800cb16: 2b01 cmp r3, #1
|
|
800cb18: d003 beq.n 800cb22 <USBH_LL_GetSpeed+0x32>
|
|
800cb1a: e008 b.n 800cb2e <USBH_LL_GetSpeed+0x3e>
|
|
{
|
|
case 0 :
|
|
speed = USBH_SPEED_HIGH;
|
|
800cb1c: 2300 movs r3, #0
|
|
800cb1e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cb20: e008 b.n 800cb34 <USBH_LL_GetSpeed+0x44>
|
|
|
|
case 1 :
|
|
speed = USBH_SPEED_FULL;
|
|
800cb22: 2301 movs r3, #1
|
|
800cb24: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cb26: e005 b.n 800cb34 <USBH_LL_GetSpeed+0x44>
|
|
|
|
case 2 :
|
|
speed = USBH_SPEED_LOW;
|
|
800cb28: 2302 movs r3, #2
|
|
800cb2a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cb2c: e002 b.n 800cb34 <USBH_LL_GetSpeed+0x44>
|
|
|
|
default:
|
|
speed = USBH_SPEED_FULL;
|
|
800cb2e: 2301 movs r3, #1
|
|
800cb30: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cb32: bf00 nop
|
|
}
|
|
return speed;
|
|
800cb34: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cb36: 4618 mov r0, r3
|
|
800cb38: 3710 adds r7, #16
|
|
800cb3a: 46bd mov sp, r7
|
|
800cb3c: bd80 pop {r7, pc}
|
|
|
|
0800cb3e <USBH_LL_ResetPort>:
|
|
* @brief Reset the Host port of the low level driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_ResetPort(USBH_HandleTypeDef *phost)
|
|
{
|
|
800cb3e: b580 push {r7, lr}
|
|
800cb40: b084 sub sp, #16
|
|
800cb42: af00 add r7, sp, #0
|
|
800cb44: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800cb46: 2300 movs r3, #0
|
|
800cb48: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800cb4a: 2300 movs r3, #0
|
|
800cb4c: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_ResetPort(phost->pData);
|
|
800cb4e: 687b ldr r3, [r7, #4]
|
|
800cb50: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800cb54: 4618 mov r0, r3
|
|
800cb56: f7f5 fec7 bl 80028e8 <HAL_HCD_ResetPort>
|
|
800cb5a: 4603 mov r3, r0
|
|
800cb5c: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
800cb5e: 7bfb ldrb r3, [r7, #15]
|
|
800cb60: 4618 mov r0, r3
|
|
800cb62: f000 f8ef bl 800cd44 <USBH_Get_USB_Status>
|
|
800cb66: 4603 mov r3, r0
|
|
800cb68: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800cb6a: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800cb6c: 4618 mov r0, r3
|
|
800cb6e: 3710 adds r7, #16
|
|
800cb70: 46bd mov sp, r7
|
|
800cb72: bd80 pop {r7, pc}
|
|
|
|
0800cb74 <USBH_LL_GetLastXferSize>:
|
|
* @param phost: Host handle
|
|
* @param pipe: Pipe index
|
|
* @retval Packet size
|
|
*/
|
|
uint32_t USBH_LL_GetLastXferSize(USBH_HandleTypeDef *phost, uint8_t pipe)
|
|
{
|
|
800cb74: b580 push {r7, lr}
|
|
800cb76: b082 sub sp, #8
|
|
800cb78: af00 add r7, sp, #0
|
|
800cb7a: 6078 str r0, [r7, #4]
|
|
800cb7c: 460b mov r3, r1
|
|
800cb7e: 70fb strb r3, [r7, #3]
|
|
return HAL_HCD_HC_GetXferCount(phost->pData, pipe);
|
|
800cb80: 687b ldr r3, [r7, #4]
|
|
800cb82: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800cb86: 78fa ldrb r2, [r7, #3]
|
|
800cb88: 4611 mov r1, r2
|
|
800cb8a: 4618 mov r0, r3
|
|
800cb8c: f7f5 fecf bl 800292e <HAL_HCD_HC_GetXferCount>
|
|
800cb90: 4603 mov r3, r0
|
|
}
|
|
800cb92: 4618 mov r0, r3
|
|
800cb94: 3708 adds r7, #8
|
|
800cb96: 46bd mov sp, r7
|
|
800cb98: bd80 pop {r7, pc}
|
|
|
|
0800cb9a <USBH_LL_OpenPipe>:
|
|
uint8_t epnum,
|
|
uint8_t dev_address,
|
|
uint8_t speed,
|
|
uint8_t ep_type,
|
|
uint16_t mps)
|
|
{
|
|
800cb9a: b590 push {r4, r7, lr}
|
|
800cb9c: b089 sub sp, #36 @ 0x24
|
|
800cb9e: af04 add r7, sp, #16
|
|
800cba0: 6078 str r0, [r7, #4]
|
|
800cba2: 4608 mov r0, r1
|
|
800cba4: 4611 mov r1, r2
|
|
800cba6: 461a mov r2, r3
|
|
800cba8: 4603 mov r3, r0
|
|
800cbaa: 70fb strb r3, [r7, #3]
|
|
800cbac: 460b mov r3, r1
|
|
800cbae: 70bb strb r3, [r7, #2]
|
|
800cbb0: 4613 mov r3, r2
|
|
800cbb2: 707b strb r3, [r7, #1]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800cbb4: 2300 movs r3, #0
|
|
800cbb6: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800cbb8: 2300 movs r3, #0
|
|
800cbba: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_HC_Init(phost->pData, pipe, epnum,
|
|
800cbbc: 687b ldr r3, [r7, #4]
|
|
800cbbe: f8d3 03d0 ldr.w r0, [r3, #976] @ 0x3d0
|
|
800cbc2: 787c ldrb r4, [r7, #1]
|
|
800cbc4: 78ba ldrb r2, [r7, #2]
|
|
800cbc6: 78f9 ldrb r1, [r7, #3]
|
|
800cbc8: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
800cbca: 9302 str r3, [sp, #8]
|
|
800cbcc: f897 3024 ldrb.w r3, [r7, #36] @ 0x24
|
|
800cbd0: 9301 str r3, [sp, #4]
|
|
800cbd2: f897 3020 ldrb.w r3, [r7, #32]
|
|
800cbd6: 9300 str r3, [sp, #0]
|
|
800cbd8: 4623 mov r3, r4
|
|
800cbda: f7f5 fadf bl 800219c <HAL_HCD_HC_Init>
|
|
800cbde: 4603 mov r3, r0
|
|
800cbe0: 73fb strb r3, [r7, #15]
|
|
dev_address, speed, ep_type, mps);
|
|
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
800cbe2: 7bfb ldrb r3, [r7, #15]
|
|
800cbe4: 4618 mov r0, r3
|
|
800cbe6: f000 f8ad bl 800cd44 <USBH_Get_USB_Status>
|
|
800cbea: 4603 mov r3, r0
|
|
800cbec: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800cbee: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800cbf0: 4618 mov r0, r3
|
|
800cbf2: 3714 adds r7, #20
|
|
800cbf4: 46bd mov sp, r7
|
|
800cbf6: bd90 pop {r4, r7, pc}
|
|
|
|
0800cbf8 <USBH_LL_ClosePipe>:
|
|
* @param phost: Host handle
|
|
* @param pipe: Pipe index
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_ClosePipe(USBH_HandleTypeDef *phost, uint8_t pipe)
|
|
{
|
|
800cbf8: b480 push {r7}
|
|
800cbfa: b083 sub sp, #12
|
|
800cbfc: af00 add r7, sp, #0
|
|
800cbfe: 6078 str r0, [r7, #4]
|
|
800cc00: 460b mov r3, r1
|
|
800cc02: 70fb strb r3, [r7, #3]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(phost);
|
|
UNUSED(pipe);
|
|
|
|
return USBH_OK;
|
|
800cc04: 2300 movs r3, #0
|
|
}
|
|
800cc06: 4618 mov r0, r3
|
|
800cc08: 370c adds r7, #12
|
|
800cc0a: 46bd mov sp, r7
|
|
800cc0c: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cc10: 4770 bx lr
|
|
|
|
0800cc12 <USBH_LL_SubmitURB>:
|
|
* @retval Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_SubmitURB(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t direction,
|
|
uint8_t ep_type, uint8_t token, uint8_t *pbuff, uint16_t length,
|
|
uint8_t do_ping)
|
|
{
|
|
800cc12: b590 push {r4, r7, lr}
|
|
800cc14: b089 sub sp, #36 @ 0x24
|
|
800cc16: af04 add r7, sp, #16
|
|
800cc18: 6078 str r0, [r7, #4]
|
|
800cc1a: 4608 mov r0, r1
|
|
800cc1c: 4611 mov r1, r2
|
|
800cc1e: 461a mov r2, r3
|
|
800cc20: 4603 mov r3, r0
|
|
800cc22: 70fb strb r3, [r7, #3]
|
|
800cc24: 460b mov r3, r1
|
|
800cc26: 70bb strb r3, [r7, #2]
|
|
800cc28: 4613 mov r3, r2
|
|
800cc2a: 707b strb r3, [r7, #1]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
800cc2c: 2300 movs r3, #0
|
|
800cc2e: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800cc30: 2300 movs r3, #0
|
|
800cc32: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_HC_SubmitRequest(phost->pData, pipe, direction ,
|
|
800cc34: 687b ldr r3, [r7, #4]
|
|
800cc36: f8d3 03d0 ldr.w r0, [r3, #976] @ 0x3d0
|
|
800cc3a: 787c ldrb r4, [r7, #1]
|
|
800cc3c: 78ba ldrb r2, [r7, #2]
|
|
800cc3e: 78f9 ldrb r1, [r7, #3]
|
|
800cc40: f897 302c ldrb.w r3, [r7, #44] @ 0x2c
|
|
800cc44: 9303 str r3, [sp, #12]
|
|
800cc46: 8d3b ldrh r3, [r7, #40] @ 0x28
|
|
800cc48: 9302 str r3, [sp, #8]
|
|
800cc4a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800cc4c: 9301 str r3, [sp, #4]
|
|
800cc4e: f897 3020 ldrb.w r3, [r7, #32]
|
|
800cc52: 9300 str r3, [sp, #0]
|
|
800cc54: 4623 mov r3, r4
|
|
800cc56: f7f5 fb59 bl 800230c <HAL_HCD_HC_SubmitRequest>
|
|
800cc5a: 4603 mov r3, r0
|
|
800cc5c: 73fb strb r3, [r7, #15]
|
|
ep_type, token, pbuff, length,
|
|
do_ping);
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
800cc5e: 7bfb ldrb r3, [r7, #15]
|
|
800cc60: 4618 mov r0, r3
|
|
800cc62: f000 f86f bl 800cd44 <USBH_Get_USB_Status>
|
|
800cc66: 4603 mov r3, r0
|
|
800cc68: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
800cc6a: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
800cc6c: 4618 mov r0, r3
|
|
800cc6e: 3714 adds r7, #20
|
|
800cc70: 46bd mov sp, r7
|
|
800cc72: bd90 pop {r4, r7, pc}
|
|
|
|
0800cc74 <USBH_LL_GetURBState>:
|
|
* @arg URB_NYET
|
|
* @arg URB_ERROR
|
|
* @arg URB_STALL
|
|
*/
|
|
USBH_URBStateTypeDef USBH_LL_GetURBState(USBH_HandleTypeDef *phost, uint8_t pipe)
|
|
{
|
|
800cc74: b580 push {r7, lr}
|
|
800cc76: b082 sub sp, #8
|
|
800cc78: af00 add r7, sp, #0
|
|
800cc7a: 6078 str r0, [r7, #4]
|
|
800cc7c: 460b mov r3, r1
|
|
800cc7e: 70fb strb r3, [r7, #3]
|
|
return (USBH_URBStateTypeDef)HAL_HCD_HC_GetURBState (phost->pData, pipe);
|
|
800cc80: 687b ldr r3, [r7, #4]
|
|
800cc82: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800cc86: 78fa ldrb r2, [r7, #3]
|
|
800cc88: 4611 mov r1, r2
|
|
800cc8a: 4618 mov r0, r3
|
|
800cc8c: f7f5 fe3a bl 8002904 <HAL_HCD_HC_GetURBState>
|
|
800cc90: 4603 mov r3, r0
|
|
}
|
|
800cc92: 4618 mov r0, r3
|
|
800cc94: 3708 adds r7, #8
|
|
800cc96: 46bd mov sp, r7
|
|
800cc98: bd80 pop {r7, pc}
|
|
|
|
0800cc9a <USBH_LL_DriverVBUS>:
|
|
* 0 : VBUS Inactive
|
|
* 1 : VBUS Active
|
|
* @retval Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_DriverVBUS(USBH_HandleTypeDef *phost, uint8_t state)
|
|
{
|
|
800cc9a: b580 push {r7, lr}
|
|
800cc9c: b082 sub sp, #8
|
|
800cc9e: af00 add r7, sp, #0
|
|
800cca0: 6078 str r0, [r7, #4]
|
|
800cca2: 460b mov r3, r1
|
|
800cca4: 70fb strb r3, [r7, #3]
|
|
if (phost->id == HOST_HS) {
|
|
800cca6: 687b ldr r3, [r7, #4]
|
|
800cca8: f893 33cc ldrb.w r3, [r3, #972] @ 0x3cc
|
|
800ccac: 2b00 cmp r3, #0
|
|
800ccae: d103 bne.n 800ccb8 <USBH_LL_DriverVBUS+0x1e>
|
|
MX_DriverVbusHS(state);
|
|
800ccb0: 78fb ldrb r3, [r7, #3]
|
|
800ccb2: 4618 mov r0, r3
|
|
800ccb4: f000 f872 bl 800cd9c <MX_DriverVbusHS>
|
|
|
|
/* USER CODE BEGIN 0 */
|
|
|
|
/* USER CODE END 0*/
|
|
|
|
HAL_Delay(200);
|
|
800ccb8: 20c8 movs r0, #200 @ 0xc8
|
|
800ccba: f7f4 fd1b bl 80016f4 <HAL_Delay>
|
|
return USBH_OK;
|
|
800ccbe: 2300 movs r3, #0
|
|
}
|
|
800ccc0: 4618 mov r0, r3
|
|
800ccc2: 3708 adds r7, #8
|
|
800ccc4: 46bd mov sp, r7
|
|
800ccc6: bd80 pop {r7, pc}
|
|
|
|
0800ccc8 <USBH_LL_SetToggle>:
|
|
* @param pipe: Pipe index
|
|
* @param toggle: toggle (0/1)
|
|
* @retval Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_SetToggle(USBH_HandleTypeDef *phost, uint8_t pipe, uint8_t toggle)
|
|
{
|
|
800ccc8: b480 push {r7}
|
|
800ccca: b085 sub sp, #20
|
|
800cccc: af00 add r7, sp, #0
|
|
800ccce: 6078 str r0, [r7, #4]
|
|
800ccd0: 460b mov r3, r1
|
|
800ccd2: 70fb strb r3, [r7, #3]
|
|
800ccd4: 4613 mov r3, r2
|
|
800ccd6: 70bb strb r3, [r7, #2]
|
|
HCD_HandleTypeDef *pHandle;
|
|
pHandle = phost->pData;
|
|
800ccd8: 687b ldr r3, [r7, #4]
|
|
800ccda: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
800ccde: 60fb str r3, [r7, #12]
|
|
|
|
if(pHandle->hc[pipe].ep_is_in)
|
|
800cce0: 78fa ldrb r2, [r7, #3]
|
|
800cce2: 68f9 ldr r1, [r7, #12]
|
|
800cce4: 4613 mov r3, r2
|
|
800cce6: 011b lsls r3, r3, #4
|
|
800cce8: 1a9b subs r3, r3, r2
|
|
800ccea: 009b lsls r3, r3, #2
|
|
800ccec: 440b add r3, r1
|
|
800ccee: 3317 adds r3, #23
|
|
800ccf0: 781b ldrb r3, [r3, #0]
|
|
800ccf2: 2b00 cmp r3, #0
|
|
800ccf4: d00a beq.n 800cd0c <USBH_LL_SetToggle+0x44>
|
|
{
|
|
pHandle->hc[pipe].toggle_in = toggle;
|
|
800ccf6: 78fa ldrb r2, [r7, #3]
|
|
800ccf8: 68f9 ldr r1, [r7, #12]
|
|
800ccfa: 4613 mov r3, r2
|
|
800ccfc: 011b lsls r3, r3, #4
|
|
800ccfe: 1a9b subs r3, r3, r2
|
|
800cd00: 009b lsls r3, r3, #2
|
|
800cd02: 440b add r3, r1
|
|
800cd04: 333c adds r3, #60 @ 0x3c
|
|
800cd06: 78ba ldrb r2, [r7, #2]
|
|
800cd08: 701a strb r2, [r3, #0]
|
|
800cd0a: e009 b.n 800cd20 <USBH_LL_SetToggle+0x58>
|
|
}
|
|
else
|
|
{
|
|
pHandle->hc[pipe].toggle_out = toggle;
|
|
800cd0c: 78fa ldrb r2, [r7, #3]
|
|
800cd0e: 68f9 ldr r1, [r7, #12]
|
|
800cd10: 4613 mov r3, r2
|
|
800cd12: 011b lsls r3, r3, #4
|
|
800cd14: 1a9b subs r3, r3, r2
|
|
800cd16: 009b lsls r3, r3, #2
|
|
800cd18: 440b add r3, r1
|
|
800cd1a: 333d adds r3, #61 @ 0x3d
|
|
800cd1c: 78ba ldrb r2, [r7, #2]
|
|
800cd1e: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
return USBH_OK;
|
|
800cd20: 2300 movs r3, #0
|
|
}
|
|
800cd22: 4618 mov r0, r3
|
|
800cd24: 3714 adds r7, #20
|
|
800cd26: 46bd mov sp, r7
|
|
800cd28: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cd2c: 4770 bx lr
|
|
|
|
0800cd2e <USBH_Delay>:
|
|
* @brief Delay routine for the USB Host Library
|
|
* @param Delay: Delay in ms
|
|
* @retval None
|
|
*/
|
|
void USBH_Delay(uint32_t Delay)
|
|
{
|
|
800cd2e: b580 push {r7, lr}
|
|
800cd30: b082 sub sp, #8
|
|
800cd32: af00 add r7, sp, #0
|
|
800cd34: 6078 str r0, [r7, #4]
|
|
HAL_Delay(Delay);
|
|
800cd36: 6878 ldr r0, [r7, #4]
|
|
800cd38: f7f4 fcdc bl 80016f4 <HAL_Delay>
|
|
}
|
|
800cd3c: bf00 nop
|
|
800cd3e: 3708 adds r7, #8
|
|
800cd40: 46bd mov sp, r7
|
|
800cd42: bd80 pop {r7, pc}
|
|
|
|
0800cd44 <USBH_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
800cd44: b480 push {r7}
|
|
800cd46: b085 sub sp, #20
|
|
800cd48: af00 add r7, sp, #0
|
|
800cd4a: 4603 mov r3, r0
|
|
800cd4c: 71fb strb r3, [r7, #7]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
800cd4e: 2300 movs r3, #0
|
|
800cd50: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
800cd52: 79fb ldrb r3, [r7, #7]
|
|
800cd54: 2b03 cmp r3, #3
|
|
800cd56: d817 bhi.n 800cd88 <USBH_Get_USB_Status+0x44>
|
|
800cd58: a201 add r2, pc, #4 @ (adr r2, 800cd60 <USBH_Get_USB_Status+0x1c>)
|
|
800cd5a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800cd5e: bf00 nop
|
|
800cd60: 0800cd71 .word 0x0800cd71
|
|
800cd64: 0800cd77 .word 0x0800cd77
|
|
800cd68: 0800cd7d .word 0x0800cd7d
|
|
800cd6c: 0800cd83 .word 0x0800cd83
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBH_OK;
|
|
800cd70: 2300 movs r3, #0
|
|
800cd72: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cd74: e00b b.n 800cd8e <USBH_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBH_FAIL;
|
|
800cd76: 2302 movs r3, #2
|
|
800cd78: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cd7a: e008 b.n 800cd8e <USBH_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBH_BUSY;
|
|
800cd7c: 2301 movs r3, #1
|
|
800cd7e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cd80: e005 b.n 800cd8e <USBH_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBH_FAIL;
|
|
800cd82: 2302 movs r3, #2
|
|
800cd84: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cd86: e002 b.n 800cd8e <USBH_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBH_FAIL;
|
|
800cd88: 2302 movs r3, #2
|
|
800cd8a: 73fb strb r3, [r7, #15]
|
|
break;
|
|
800cd8c: bf00 nop
|
|
}
|
|
return usb_status;
|
|
800cd8e: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800cd90: 4618 mov r0, r3
|
|
800cd92: 3714 adds r7, #20
|
|
800cd94: 46bd mov sp, r7
|
|
800cd96: f85d 7b04 ldr.w r7, [sp], #4
|
|
800cd9a: 4770 bx lr
|
|
|
|
0800cd9c <MX_DriverVbusHS>:
|
|
* This parameter can be one of the these values:
|
|
* - 1 : VBUS Active
|
|
* - 0 : VBUS Inactive
|
|
*/
|
|
void MX_DriverVbusHS(uint8_t state)
|
|
{
|
|
800cd9c: b580 push {r7, lr}
|
|
800cd9e: b084 sub sp, #16
|
|
800cda0: af00 add r7, sp, #0
|
|
800cda2: 4603 mov r3, r0
|
|
800cda4: 71fb strb r3, [r7, #7]
|
|
uint8_t data = state;
|
|
800cda6: 79fb ldrb r3, [r7, #7]
|
|
800cda8: 73fb strb r3, [r7, #15]
|
|
/* USER CODE BEGIN PREPARE_GPIO_DATA_VBUS_HS */
|
|
if(state == 0)
|
|
800cdaa: 79fb ldrb r3, [r7, #7]
|
|
800cdac: 2b00 cmp r3, #0
|
|
800cdae: d102 bne.n 800cdb6 <MX_DriverVbusHS+0x1a>
|
|
{
|
|
/* Drive high Charge pump */
|
|
data = GPIO_PIN_SET;
|
|
800cdb0: 2301 movs r3, #1
|
|
800cdb2: 73fb strb r3, [r7, #15]
|
|
800cdb4: e001 b.n 800cdba <MX_DriverVbusHS+0x1e>
|
|
}
|
|
else
|
|
{
|
|
/* Drive low Charge pump */
|
|
data = GPIO_PIN_RESET;
|
|
800cdb6: 2300 movs r3, #0
|
|
800cdb8: 73fb strb r3, [r7, #15]
|
|
}
|
|
/* USER CODE END PREPARE_GPIO_DATA_VBUS_HS */
|
|
HAL_GPIO_WritePin(GPIOC,GPIO_PIN_4,(GPIO_PinState)data);
|
|
800cdba: 7bfb ldrb r3, [r7, #15]
|
|
800cdbc: 461a mov r2, r3
|
|
800cdbe: 2110 movs r1, #16
|
|
800cdc0: 4803 ldr r0, [pc, #12] @ (800cdd0 <MX_DriverVbusHS+0x34>)
|
|
800cdc2: f7f5 f951 bl 8002068 <HAL_GPIO_WritePin>
|
|
}
|
|
800cdc6: bf00 nop
|
|
800cdc8: 3710 adds r7, #16
|
|
800cdca: 46bd mov sp, r7
|
|
800cdcc: bd80 pop {r7, pc}
|
|
800cdce: bf00 nop
|
|
800cdd0: 40020800 .word 0x40020800
|
|
|
|
0800cdd4 <malloc>:
|
|
800cdd4: 4b02 ldr r3, [pc, #8] @ (800cde0 <malloc+0xc>)
|
|
800cdd6: 4601 mov r1, r0
|
|
800cdd8: 6818 ldr r0, [r3, #0]
|
|
800cdda: f000 b82d b.w 800ce38 <_malloc_r>
|
|
800cdde: bf00 nop
|
|
800cde0: 20000030 .word 0x20000030
|
|
|
|
0800cde4 <free>:
|
|
800cde4: 4b02 ldr r3, [pc, #8] @ (800cdf0 <free+0xc>)
|
|
800cde6: 4601 mov r1, r0
|
|
800cde8: 6818 ldr r0, [r3, #0]
|
|
800cdea: f000 b903 b.w 800cff4 <_free_r>
|
|
800cdee: bf00 nop
|
|
800cdf0: 20000030 .word 0x20000030
|
|
|
|
0800cdf4 <sbrk_aligned>:
|
|
800cdf4: b570 push {r4, r5, r6, lr}
|
|
800cdf6: 4e0f ldr r6, [pc, #60] @ (800ce34 <sbrk_aligned+0x40>)
|
|
800cdf8: 460c mov r4, r1
|
|
800cdfa: 6831 ldr r1, [r6, #0]
|
|
800cdfc: 4605 mov r5, r0
|
|
800cdfe: b911 cbnz r1, 800ce06 <sbrk_aligned+0x12>
|
|
800ce00: f000 f8ae bl 800cf60 <_sbrk_r>
|
|
800ce04: 6030 str r0, [r6, #0]
|
|
800ce06: 4621 mov r1, r4
|
|
800ce08: 4628 mov r0, r5
|
|
800ce0a: f000 f8a9 bl 800cf60 <_sbrk_r>
|
|
800ce0e: 1c43 adds r3, r0, #1
|
|
800ce10: d103 bne.n 800ce1a <sbrk_aligned+0x26>
|
|
800ce12: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
800ce16: 4620 mov r0, r4
|
|
800ce18: bd70 pop {r4, r5, r6, pc}
|
|
800ce1a: 1cc4 adds r4, r0, #3
|
|
800ce1c: f024 0403 bic.w r4, r4, #3
|
|
800ce20: 42a0 cmp r0, r4
|
|
800ce22: d0f8 beq.n 800ce16 <sbrk_aligned+0x22>
|
|
800ce24: 1a21 subs r1, r4, r0
|
|
800ce26: 4628 mov r0, r5
|
|
800ce28: f000 f89a bl 800cf60 <_sbrk_r>
|
|
800ce2c: 3001 adds r0, #1
|
|
800ce2e: d1f2 bne.n 800ce16 <sbrk_aligned+0x22>
|
|
800ce30: e7ef b.n 800ce12 <sbrk_aligned+0x1e>
|
|
800ce32: bf00 nop
|
|
800ce34: 20008ec8 .word 0x20008ec8
|
|
|
|
0800ce38 <_malloc_r>:
|
|
800ce38: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
800ce3c: 1ccd adds r5, r1, #3
|
|
800ce3e: f025 0503 bic.w r5, r5, #3
|
|
800ce42: 3508 adds r5, #8
|
|
800ce44: 2d0c cmp r5, #12
|
|
800ce46: bf38 it cc
|
|
800ce48: 250c movcc r5, #12
|
|
800ce4a: 2d00 cmp r5, #0
|
|
800ce4c: 4606 mov r6, r0
|
|
800ce4e: db01 blt.n 800ce54 <_malloc_r+0x1c>
|
|
800ce50: 42a9 cmp r1, r5
|
|
800ce52: d904 bls.n 800ce5e <_malloc_r+0x26>
|
|
800ce54: 230c movs r3, #12
|
|
800ce56: 6033 str r3, [r6, #0]
|
|
800ce58: 2000 movs r0, #0
|
|
800ce5a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800ce5e: f8df 80d4 ldr.w r8, [pc, #212] @ 800cf34 <_malloc_r+0xfc>
|
|
800ce62: f000 f869 bl 800cf38 <__malloc_lock>
|
|
800ce66: f8d8 3000 ldr.w r3, [r8]
|
|
800ce6a: 461c mov r4, r3
|
|
800ce6c: bb44 cbnz r4, 800cec0 <_malloc_r+0x88>
|
|
800ce6e: 4629 mov r1, r5
|
|
800ce70: 4630 mov r0, r6
|
|
800ce72: f7ff ffbf bl 800cdf4 <sbrk_aligned>
|
|
800ce76: 1c43 adds r3, r0, #1
|
|
800ce78: 4604 mov r4, r0
|
|
800ce7a: d158 bne.n 800cf2e <_malloc_r+0xf6>
|
|
800ce7c: f8d8 4000 ldr.w r4, [r8]
|
|
800ce80: 4627 mov r7, r4
|
|
800ce82: 2f00 cmp r7, #0
|
|
800ce84: d143 bne.n 800cf0e <_malloc_r+0xd6>
|
|
800ce86: 2c00 cmp r4, #0
|
|
800ce88: d04b beq.n 800cf22 <_malloc_r+0xea>
|
|
800ce8a: 6823 ldr r3, [r4, #0]
|
|
800ce8c: 4639 mov r1, r7
|
|
800ce8e: 4630 mov r0, r6
|
|
800ce90: eb04 0903 add.w r9, r4, r3
|
|
800ce94: f000 f864 bl 800cf60 <_sbrk_r>
|
|
800ce98: 4581 cmp r9, r0
|
|
800ce9a: d142 bne.n 800cf22 <_malloc_r+0xea>
|
|
800ce9c: 6821 ldr r1, [r4, #0]
|
|
800ce9e: 1a6d subs r5, r5, r1
|
|
800cea0: 4629 mov r1, r5
|
|
800cea2: 4630 mov r0, r6
|
|
800cea4: f7ff ffa6 bl 800cdf4 <sbrk_aligned>
|
|
800cea8: 3001 adds r0, #1
|
|
800ceaa: d03a beq.n 800cf22 <_malloc_r+0xea>
|
|
800ceac: 6823 ldr r3, [r4, #0]
|
|
800ceae: 442b add r3, r5
|
|
800ceb0: 6023 str r3, [r4, #0]
|
|
800ceb2: f8d8 3000 ldr.w r3, [r8]
|
|
800ceb6: 685a ldr r2, [r3, #4]
|
|
800ceb8: bb62 cbnz r2, 800cf14 <_malloc_r+0xdc>
|
|
800ceba: f8c8 7000 str.w r7, [r8]
|
|
800cebe: e00f b.n 800cee0 <_malloc_r+0xa8>
|
|
800cec0: 6822 ldr r2, [r4, #0]
|
|
800cec2: 1b52 subs r2, r2, r5
|
|
800cec4: d420 bmi.n 800cf08 <_malloc_r+0xd0>
|
|
800cec6: 2a0b cmp r2, #11
|
|
800cec8: d917 bls.n 800cefa <_malloc_r+0xc2>
|
|
800ceca: 1961 adds r1, r4, r5
|
|
800cecc: 42a3 cmp r3, r4
|
|
800cece: 6025 str r5, [r4, #0]
|
|
800ced0: bf18 it ne
|
|
800ced2: 6059 strne r1, [r3, #4]
|
|
800ced4: 6863 ldr r3, [r4, #4]
|
|
800ced6: bf08 it eq
|
|
800ced8: f8c8 1000 streq.w r1, [r8]
|
|
800cedc: 5162 str r2, [r4, r5]
|
|
800cede: 604b str r3, [r1, #4]
|
|
800cee0: 4630 mov r0, r6
|
|
800cee2: f000 f82f bl 800cf44 <__malloc_unlock>
|
|
800cee6: f104 000b add.w r0, r4, #11
|
|
800ceea: 1d23 adds r3, r4, #4
|
|
800ceec: f020 0007 bic.w r0, r0, #7
|
|
800cef0: 1ac2 subs r2, r0, r3
|
|
800cef2: bf1c itt ne
|
|
800cef4: 1a1b subne r3, r3, r0
|
|
800cef6: 50a3 strne r3, [r4, r2]
|
|
800cef8: e7af b.n 800ce5a <_malloc_r+0x22>
|
|
800cefa: 6862 ldr r2, [r4, #4]
|
|
800cefc: 42a3 cmp r3, r4
|
|
800cefe: bf0c ite eq
|
|
800cf00: f8c8 2000 streq.w r2, [r8]
|
|
800cf04: 605a strne r2, [r3, #4]
|
|
800cf06: e7eb b.n 800cee0 <_malloc_r+0xa8>
|
|
800cf08: 4623 mov r3, r4
|
|
800cf0a: 6864 ldr r4, [r4, #4]
|
|
800cf0c: e7ae b.n 800ce6c <_malloc_r+0x34>
|
|
800cf0e: 463c mov r4, r7
|
|
800cf10: 687f ldr r7, [r7, #4]
|
|
800cf12: e7b6 b.n 800ce82 <_malloc_r+0x4a>
|
|
800cf14: 461a mov r2, r3
|
|
800cf16: 685b ldr r3, [r3, #4]
|
|
800cf18: 42a3 cmp r3, r4
|
|
800cf1a: d1fb bne.n 800cf14 <_malloc_r+0xdc>
|
|
800cf1c: 2300 movs r3, #0
|
|
800cf1e: 6053 str r3, [r2, #4]
|
|
800cf20: e7de b.n 800cee0 <_malloc_r+0xa8>
|
|
800cf22: 230c movs r3, #12
|
|
800cf24: 6033 str r3, [r6, #0]
|
|
800cf26: 4630 mov r0, r6
|
|
800cf28: f000 f80c bl 800cf44 <__malloc_unlock>
|
|
800cf2c: e794 b.n 800ce58 <_malloc_r+0x20>
|
|
800cf2e: 6005 str r5, [r0, #0]
|
|
800cf30: e7d6 b.n 800cee0 <_malloc_r+0xa8>
|
|
800cf32: bf00 nop
|
|
800cf34: 20008ecc .word 0x20008ecc
|
|
|
|
0800cf38 <__malloc_lock>:
|
|
800cf38: 4801 ldr r0, [pc, #4] @ (800cf40 <__malloc_lock+0x8>)
|
|
800cf3a: f000 b84b b.w 800cfd4 <__retarget_lock_acquire_recursive>
|
|
800cf3e: bf00 nop
|
|
800cf40: 2000900c .word 0x2000900c
|
|
|
|
0800cf44 <__malloc_unlock>:
|
|
800cf44: 4801 ldr r0, [pc, #4] @ (800cf4c <__malloc_unlock+0x8>)
|
|
800cf46: f000 b846 b.w 800cfd6 <__retarget_lock_release_recursive>
|
|
800cf4a: bf00 nop
|
|
800cf4c: 2000900c .word 0x2000900c
|
|
|
|
0800cf50 <memset>:
|
|
800cf50: 4402 add r2, r0
|
|
800cf52: 4603 mov r3, r0
|
|
800cf54: 4293 cmp r3, r2
|
|
800cf56: d100 bne.n 800cf5a <memset+0xa>
|
|
800cf58: 4770 bx lr
|
|
800cf5a: f803 1b01 strb.w r1, [r3], #1
|
|
800cf5e: e7f9 b.n 800cf54 <memset+0x4>
|
|
|
|
0800cf60 <_sbrk_r>:
|
|
800cf60: b538 push {r3, r4, r5, lr}
|
|
800cf62: 4d06 ldr r5, [pc, #24] @ (800cf7c <_sbrk_r+0x1c>)
|
|
800cf64: 2300 movs r3, #0
|
|
800cf66: 4604 mov r4, r0
|
|
800cf68: 4608 mov r0, r1
|
|
800cf6a: 602b str r3, [r5, #0]
|
|
800cf6c: f7f4 fb0e bl 800158c <_sbrk>
|
|
800cf70: 1c43 adds r3, r0, #1
|
|
800cf72: d102 bne.n 800cf7a <_sbrk_r+0x1a>
|
|
800cf74: 682b ldr r3, [r5, #0]
|
|
800cf76: b103 cbz r3, 800cf7a <_sbrk_r+0x1a>
|
|
800cf78: 6023 str r3, [r4, #0]
|
|
800cf7a: bd38 pop {r3, r4, r5, pc}
|
|
800cf7c: 20009008 .word 0x20009008
|
|
|
|
0800cf80 <__errno>:
|
|
800cf80: 4b01 ldr r3, [pc, #4] @ (800cf88 <__errno+0x8>)
|
|
800cf82: 6818 ldr r0, [r3, #0]
|
|
800cf84: 4770 bx lr
|
|
800cf86: bf00 nop
|
|
800cf88: 20000030 .word 0x20000030
|
|
|
|
0800cf8c <__libc_init_array>:
|
|
800cf8c: b570 push {r4, r5, r6, lr}
|
|
800cf8e: 4d0d ldr r5, [pc, #52] @ (800cfc4 <__libc_init_array+0x38>)
|
|
800cf90: 4c0d ldr r4, [pc, #52] @ (800cfc8 <__libc_init_array+0x3c>)
|
|
800cf92: 1b64 subs r4, r4, r5
|
|
800cf94: 10a4 asrs r4, r4, #2
|
|
800cf96: 2600 movs r6, #0
|
|
800cf98: 42a6 cmp r6, r4
|
|
800cf9a: d109 bne.n 800cfb0 <__libc_init_array+0x24>
|
|
800cf9c: 4d0b ldr r5, [pc, #44] @ (800cfcc <__libc_init_array+0x40>)
|
|
800cf9e: 4c0c ldr r4, [pc, #48] @ (800cfd0 <__libc_init_array+0x44>)
|
|
800cfa0: f000 f872 bl 800d088 <_init>
|
|
800cfa4: 1b64 subs r4, r4, r5
|
|
800cfa6: 10a4 asrs r4, r4, #2
|
|
800cfa8: 2600 movs r6, #0
|
|
800cfaa: 42a6 cmp r6, r4
|
|
800cfac: d105 bne.n 800cfba <__libc_init_array+0x2e>
|
|
800cfae: bd70 pop {r4, r5, r6, pc}
|
|
800cfb0: f855 3b04 ldr.w r3, [r5], #4
|
|
800cfb4: 4798 blx r3
|
|
800cfb6: 3601 adds r6, #1
|
|
800cfb8: e7ee b.n 800cf98 <__libc_init_array+0xc>
|
|
800cfba: f855 3b04 ldr.w r3, [r5], #4
|
|
800cfbe: 4798 blx r3
|
|
800cfc0: 3601 adds r6, #1
|
|
800cfc2: e7f2 b.n 800cfaa <__libc_init_array+0x1e>
|
|
800cfc4: 0800d12c .word 0x0800d12c
|
|
800cfc8: 0800d12c .word 0x0800d12c
|
|
800cfcc: 0800d12c .word 0x0800d12c
|
|
800cfd0: 0800d130 .word 0x0800d130
|
|
|
|
0800cfd4 <__retarget_lock_acquire_recursive>:
|
|
800cfd4: 4770 bx lr
|
|
|
|
0800cfd6 <__retarget_lock_release_recursive>:
|
|
800cfd6: 4770 bx lr
|
|
|
|
0800cfd8 <memcpy>:
|
|
800cfd8: 440a add r2, r1
|
|
800cfda: 4291 cmp r1, r2
|
|
800cfdc: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
800cfe0: d100 bne.n 800cfe4 <memcpy+0xc>
|
|
800cfe2: 4770 bx lr
|
|
800cfe4: b510 push {r4, lr}
|
|
800cfe6: f811 4b01 ldrb.w r4, [r1], #1
|
|
800cfea: f803 4f01 strb.w r4, [r3, #1]!
|
|
800cfee: 4291 cmp r1, r2
|
|
800cff0: d1f9 bne.n 800cfe6 <memcpy+0xe>
|
|
800cff2: bd10 pop {r4, pc}
|
|
|
|
0800cff4 <_free_r>:
|
|
800cff4: b538 push {r3, r4, r5, lr}
|
|
800cff6: 4605 mov r5, r0
|
|
800cff8: 2900 cmp r1, #0
|
|
800cffa: d041 beq.n 800d080 <_free_r+0x8c>
|
|
800cffc: f851 3c04 ldr.w r3, [r1, #-4]
|
|
800d000: 1f0c subs r4, r1, #4
|
|
800d002: 2b00 cmp r3, #0
|
|
800d004: bfb8 it lt
|
|
800d006: 18e4 addlt r4, r4, r3
|
|
800d008: f7ff ff96 bl 800cf38 <__malloc_lock>
|
|
800d00c: 4a1d ldr r2, [pc, #116] @ (800d084 <_free_r+0x90>)
|
|
800d00e: 6813 ldr r3, [r2, #0]
|
|
800d010: b933 cbnz r3, 800d020 <_free_r+0x2c>
|
|
800d012: 6063 str r3, [r4, #4]
|
|
800d014: 6014 str r4, [r2, #0]
|
|
800d016: 4628 mov r0, r5
|
|
800d018: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
800d01c: f7ff bf92 b.w 800cf44 <__malloc_unlock>
|
|
800d020: 42a3 cmp r3, r4
|
|
800d022: d908 bls.n 800d036 <_free_r+0x42>
|
|
800d024: 6820 ldr r0, [r4, #0]
|
|
800d026: 1821 adds r1, r4, r0
|
|
800d028: 428b cmp r3, r1
|
|
800d02a: bf01 itttt eq
|
|
800d02c: 6819 ldreq r1, [r3, #0]
|
|
800d02e: 685b ldreq r3, [r3, #4]
|
|
800d030: 1809 addeq r1, r1, r0
|
|
800d032: 6021 streq r1, [r4, #0]
|
|
800d034: e7ed b.n 800d012 <_free_r+0x1e>
|
|
800d036: 461a mov r2, r3
|
|
800d038: 685b ldr r3, [r3, #4]
|
|
800d03a: b10b cbz r3, 800d040 <_free_r+0x4c>
|
|
800d03c: 42a3 cmp r3, r4
|
|
800d03e: d9fa bls.n 800d036 <_free_r+0x42>
|
|
800d040: 6811 ldr r1, [r2, #0]
|
|
800d042: 1850 adds r0, r2, r1
|
|
800d044: 42a0 cmp r0, r4
|
|
800d046: d10b bne.n 800d060 <_free_r+0x6c>
|
|
800d048: 6820 ldr r0, [r4, #0]
|
|
800d04a: 4401 add r1, r0
|
|
800d04c: 1850 adds r0, r2, r1
|
|
800d04e: 4283 cmp r3, r0
|
|
800d050: 6011 str r1, [r2, #0]
|
|
800d052: d1e0 bne.n 800d016 <_free_r+0x22>
|
|
800d054: 6818 ldr r0, [r3, #0]
|
|
800d056: 685b ldr r3, [r3, #4]
|
|
800d058: 6053 str r3, [r2, #4]
|
|
800d05a: 4408 add r0, r1
|
|
800d05c: 6010 str r0, [r2, #0]
|
|
800d05e: e7da b.n 800d016 <_free_r+0x22>
|
|
800d060: d902 bls.n 800d068 <_free_r+0x74>
|
|
800d062: 230c movs r3, #12
|
|
800d064: 602b str r3, [r5, #0]
|
|
800d066: e7d6 b.n 800d016 <_free_r+0x22>
|
|
800d068: 6820 ldr r0, [r4, #0]
|
|
800d06a: 1821 adds r1, r4, r0
|
|
800d06c: 428b cmp r3, r1
|
|
800d06e: bf04 itt eq
|
|
800d070: 6819 ldreq r1, [r3, #0]
|
|
800d072: 685b ldreq r3, [r3, #4]
|
|
800d074: 6063 str r3, [r4, #4]
|
|
800d076: bf04 itt eq
|
|
800d078: 1809 addeq r1, r1, r0
|
|
800d07a: 6021 streq r1, [r4, #0]
|
|
800d07c: 6054 str r4, [r2, #4]
|
|
800d07e: e7ca b.n 800d016 <_free_r+0x22>
|
|
800d080: bd38 pop {r3, r4, r5, pc}
|
|
800d082: bf00 nop
|
|
800d084: 20008ecc .word 0x20008ecc
|
|
|
|
0800d088 <_init>:
|
|
800d088: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d08a: bf00 nop
|
|
800d08c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800d08e: bc08 pop {r3}
|
|
800d090: 469e mov lr, r3
|
|
800d092: 4770 bx lr
|
|
|
|
0800d094 <_fini>:
|
|
800d094: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800d096: bf00 nop
|
|
800d098: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800d09a: bc08 pop {r3}
|
|
800d09c: 469e mov lr, r3
|
|
800d09e: 4770 bx lr
|