20940 lines
769 KiB
Plaintext
20940 lines
769 KiB
Plaintext
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MyNewProject.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000001ac 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00007cfc 080001b0 080001b0 000011b0 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 00000018 08007eac 08007eac 00008eac 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 08007ec4 08007ec4 00009010 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 08007ec4 08007ec4 00008ec4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 08007ecc 08007ecc 00009010 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 08007ecc 08007ecc 00008ecc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 08007ed0 08007ed0 00008ed0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000010 20000000 08007ed4 00009000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .ccmram 00000000 10000000 10000000 00009010 2**0
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CONTENTS
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10 .bss 00000798 20000010 20000010 00009010 2**2
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ALLOC
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11 ._user_heap_stack 00000600 200007a8 200007a8 00009010 2**0
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ALLOC
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12 .ARM.attributes 00000030 00000000 00000000 00009010 2**0
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CONTENTS, READONLY
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13 .debug_info 00024e1f 00000000 00000000 00009040 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_abbrev 00004d52 00000000 00000000 0002de5f 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_aranges 00002070 00000000 00000000 00032bb8 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_rnglists 00001943 00000000 00000000 00034c28 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_macro 00028b6e 00000000 00000000 0003656b 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_line 00024c67 00000000 00000000 0005f0d9 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_str 000f405f 00000000 00000000 00083d40 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .comment 00000043 00000000 00000000 00177d9f 2**0
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CONTENTS, READONLY
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21 .debug_frame 00008bb8 00000000 00000000 00177de4 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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22 .debug_line_str 0000004c 00000000 00000000 0018099c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080001b0 <__do_global_dtors_aux>:
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80001b0: b510 push {r4, lr}
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80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>)
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80001b4: 7823 ldrb r3, [r4, #0]
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80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16>
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80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>)
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80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12>
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80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>)
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80001be: f3af 8000 nop.w
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80001c2: 2301 movs r3, #1
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80001c4: 7023 strb r3, [r4, #0]
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80001c6: bd10 pop {r4, pc}
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80001c8: 20000010 .word 0x20000010
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80001cc: 00000000 .word 0x00000000
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80001d0: 08007e94 .word 0x08007e94
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080001d4 <frame_dummy>:
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80001d4: b508 push {r3, lr}
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80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 <frame_dummy+0x10>)
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80001d8: b11b cbz r3, 80001e2 <frame_dummy+0xe>
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80001da: 4903 ldr r1, [pc, #12] @ (80001e8 <frame_dummy+0x14>)
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80001dc: 4803 ldr r0, [pc, #12] @ (80001ec <frame_dummy+0x18>)
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80001de: f3af 8000 nop.w
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80001e2: bd08 pop {r3, pc}
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80001e4: 00000000 .word 0x00000000
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80001e8: 20000014 .word 0x20000014
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80001ec: 08007e94 .word 0x08007e94
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080001f0 <__aeabi_uldivmod>:
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80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18>
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80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18>
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80001f4: 2900 cmp r1, #0
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80001f6: bf08 it eq
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80001f8: 2800 cmpeq r0, #0
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80001fa: bf1c itt ne
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80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
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8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
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8000204: f000 b988 b.w 8000518 <__aeabi_idiv0>
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8000208: f1ad 0c08 sub.w ip, sp, #8
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800020c: e96d ce04 strd ip, lr, [sp, #-16]!
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8000210: f000 f806 bl 8000220 <__udivmoddi4>
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8000214: f8dd e004 ldr.w lr, [sp, #4]
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8000218: e9dd 2302 ldrd r2, r3, [sp, #8]
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800021c: b004 add sp, #16
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800021e: 4770 bx lr
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08000220 <__udivmoddi4>:
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8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
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8000224: 9d08 ldr r5, [sp, #32]
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8000226: 468e mov lr, r1
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8000228: 4604 mov r4, r0
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800022a: 4688 mov r8, r1
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800022c: 2b00 cmp r3, #0
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800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6>
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8000230: 428a cmp r2, r1
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8000232: 4617 mov r7, r2
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8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc>
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8000236: fab2 f682 clz r6, r2
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800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30>
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800023c: f1c6 0320 rsb r3, r6, #32
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8000240: fa01 f806 lsl.w r8, r1, r6
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8000244: fa20 f303 lsr.w r3, r0, r3
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8000248: 40b7 lsls r7, r6
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800024a: ea43 0808 orr.w r8, r3, r8
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800024e: 40b4 lsls r4, r6
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8000250: ea4f 4e17 mov.w lr, r7, lsr #16
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8000254: fa1f fc87 uxth.w ip, r7
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8000258: fbb8 f1fe udiv r1, r8, lr
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800025c: 0c23 lsrs r3, r4, #16
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800025e: fb0e 8811 mls r8, lr, r1, r8
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8000262: ea43 4308 orr.w r3, r3, r8, lsl #16
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8000266: fb01 f20c mul.w r2, r1, ip
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800026a: 429a cmp r2, r3
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800026c: d909 bls.n 8000282 <__udivmoddi4+0x62>
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800026e: 18fb adds r3, r7, r3
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8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
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8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c>
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8000278: 429a cmp r2, r3
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800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c>
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800027e: 3902 subs r1, #2
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8000280: 443b add r3, r7
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8000282: 1a9a subs r2, r3, r2
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8000284: b2a3 uxth r3, r4
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8000286: fbb2 f0fe udiv r0, r2, lr
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800028a: fb0e 2210 mls r2, lr, r0, r2
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800028e: ea43 4302 orr.w r3, r3, r2, lsl #16
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8000292: fb00 fc0c mul.w ip, r0, ip
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8000296: 459c cmp ip, r3
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8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e>
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800029a: 18fb adds r3, r7, r3
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800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
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80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230>
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80002a4: 459c cmp ip, r3
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80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230>
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80002aa: 443b add r3, r7
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80002ac: 3802 subs r0, #2
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80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16
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80002b2: eba3 030c sub.w r3, r3, ip
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80002b6: 2100 movs r1, #0
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80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2>
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80002ba: 40f3 lsrs r3, r6
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80002bc: 2200 movs r2, #0
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80002be: e9c5 3200 strd r3, r2, [r5]
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80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
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80002c6: 428b cmp r3, r1
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80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6>
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80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0>
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80002cc: e9c5 0100 strd r0, r1, [r5]
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80002d0: 2100 movs r1, #0
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80002d2: 4608 mov r0, r1
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80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2>
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80002d6: fab3 f183 clz r1, r3
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80002da: 2900 cmp r1, #0
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80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c>
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80002de: 4573 cmp r3, lr
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80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8>
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80002e2: 4282 cmp r2, r0
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80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2>
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80002e8: 1a84 subs r4, r0, r2
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80002ea: eb6e 0203 sbc.w r2, lr, r3
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80002ee: 2001 movs r0, #1
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80002f0: 4690 mov r8, r2
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80002f2: 2d00 cmp r5, #0
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80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2>
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80002f6: e9c5 4800 strd r4, r8, [r5]
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80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2>
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80002fc: 2a00 cmp r2, #0
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80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202>
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8000302: fab2 f682 clz r6, r2
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8000306: 2e00 cmp r6, #0
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8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234>
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800030c: 1a8a subs r2, r1, r2
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800030e: 0c03 lsrs r3, r0, #16
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8000310: ea4f 4e17 mov.w lr, r7, lsr #16
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8000314: b280 uxth r0, r0
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8000316: b2bc uxth r4, r7
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8000318: 2101 movs r1, #1
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800031a: fbb2 fcfe udiv ip, r2, lr
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800031e: fb0e 221c mls r2, lr, ip, r2
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8000322: ea43 4302 orr.w r3, r3, r2, lsl #16
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8000326: fb04 f20c mul.w r2, r4, ip
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800032a: 429a cmp r2, r3
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800032c: d907 bls.n 800033e <__udivmoddi4+0x11e>
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800032e: 18fb adds r3, r7, r3
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8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
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8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c>
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8000336: 429a cmp r2, r3
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8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc>
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800033c: 46c4 mov ip, r8
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800033e: 1a9b subs r3, r3, r2
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8000340: fbb3 f2fe udiv r2, r3, lr
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8000344: fb0e 3312 mls r3, lr, r2, r3
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8000348: ea40 4303 orr.w r3, r0, r3, lsl #16
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800034c: fb02 f404 mul.w r4, r2, r4
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8000350: 429c cmp r4, r3
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8000352: d907 bls.n 8000364 <__udivmoddi4+0x144>
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8000354: 18fb adds r3, r7, r3
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8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
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800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142>
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800035c: 429c cmp r4, r3
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800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6>
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8000362: 4602 mov r2, r0
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8000364: 1b1b subs r3, r3, r4
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8000366: ea42 400c orr.w r0, r2, ip, lsl #16
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800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98>
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800036c: f1c1 0620 rsb r6, r1, #32
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8000370: 408b lsls r3, r1
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8000372: fa22 f706 lsr.w r7, r2, r6
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8000376: 431f orrs r7, r3
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8000378: fa0e f401 lsl.w r4, lr, r1
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800037c: fa20 f306 lsr.w r3, r0, r6
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8000380: fa2e fe06 lsr.w lr, lr, r6
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8000384: ea4f 4917 mov.w r9, r7, lsr #16
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8000388: 4323 orrs r3, r4
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800038a: fa00 f801 lsl.w r8, r0, r1
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800038e: fa1f fc87 uxth.w ip, r7
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8000392: fbbe f0f9 udiv r0, lr, r9
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8000396: 0c1c lsrs r4, r3, #16
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8000398: fb09 ee10 mls lr, r9, r0, lr
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800039c: ea44 440e orr.w r4, r4, lr, lsl #16
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80003a0: fb00 fe0c mul.w lr, r0, ip
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80003a4: 45a6 cmp lr, r4
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80003a6: fa02 f201 lsl.w r2, r2, r1
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80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0>
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80003ac: 193c adds r4, r7, r4
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80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
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80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce>
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80003b6: 45a6 cmp lr, r4
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80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce>
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80003bc: 3802 subs r0, #2
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80003be: 443c add r4, r7
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80003c0: eba4 040e sub.w r4, r4, lr
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80003c4: fa1f fe83 uxth.w lr, r3
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80003c8: fbb4 f3f9 udiv r3, r4, r9
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80003cc: fb09 4413 mls r4, r9, r3, r4
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80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16
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80003d4: fb03 fc0c mul.w ip, r3, ip
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80003d8: 45a4 cmp ip, r4
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80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce>
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80003dc: 193c adds r4, r7, r4
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80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
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80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca>
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80003e6: 45a4 cmp ip, r4
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80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca>
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80003ea: 3b02 subs r3, #2
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80003ec: 443c add r4, r7
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80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16
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80003f2: eba4 040c sub.w r4, r4, ip
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80003f6: fba0 ec02 umull lr, ip, r0, r2
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80003fa: 4564 cmp r4, ip
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80003fc: 4673 mov r3, lr
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80003fe: 46e1 mov r9, ip
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8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8>
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8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4>
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8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe>
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8000406: ebb8 0203 subs.w r2, r8, r3
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800040a: eb64 0409 sbc.w r4, r4, r9
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800040e: fa04 f606 lsl.w r6, r4, r6
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8000412: fa22 f301 lsr.w r3, r2, r1
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8000416: 431e orrs r6, r3
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8000418: 40cc lsrs r4, r1
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800041a: e9c5 6400 strd r6, r4, [r5]
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800041e: 2100 movs r1, #0
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8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2>
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8000422: fbb1 fcf2 udiv ip, r1, r2
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8000426: 0c01 lsrs r1, r0, #16
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8000428: ea41 410e orr.w r1, r1, lr, lsl #16
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800042c: b280 uxth r0, r0
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800042e: ea40 4201 orr.w r2, r0, r1, lsl #16
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8000432: 463b mov r3, r7
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8000434: 4638 mov r0, r7
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8000436: 463c mov r4, r7
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8000438: 46b8 mov r8, r7
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800043a: 46be mov lr, r7
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800043c: 2620 movs r6, #32
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800043e: fbb1 f1f7 udiv r1, r1, r7
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8000442: eba2 0208 sub.w r2, r2, r8
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8000446: ea41 410c orr.w r1, r1, ip, lsl #16
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800044a: e766 b.n 800031a <__udivmoddi4+0xfa>
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800044c: 4601 mov r1, r0
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800044e: e718 b.n 8000282 <__udivmoddi4+0x62>
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8000450: 4610 mov r0, r2
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8000452: e72c b.n 80002ae <__udivmoddi4+0x8e>
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8000454: f1c6 0220 rsb r2, r6, #32
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8000458: fa2e f302 lsr.w r3, lr, r2
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800045c: 40b7 lsls r7, r6
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800045e: 40b1 lsls r1, r6
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8000460: fa20 f202 lsr.w r2, r0, r2
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8000464: ea4f 4e17 mov.w lr, r7, lsr #16
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8000468: 430a orrs r2, r1
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800046a: fbb3 f8fe udiv r8, r3, lr
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800046e: b2bc uxth r4, r7
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8000470: fb0e 3318 mls r3, lr, r8, r3
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8000474: 0c11 lsrs r1, r2, #16
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8000476: ea41 4103 orr.w r1, r1, r3, lsl #16
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800047a: fb08 f904 mul.w r9, r8, r4
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800047e: 40b0 lsls r0, r6
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8000480: 4589 cmp r9, r1
|
|
8000482: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000486: b280 uxth r0, r0
|
|
8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8>
|
|
800048a: 1879 adds r1, r7, r1
|
|
800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276>
|
|
8000492: 4589 cmp r9, r1
|
|
8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6>
|
|
8000496: eba1 0109 sub.w r1, r1, r9
|
|
800049a: fbb1 f9fe udiv r9, r1, lr
|
|
800049e: fb09 f804 mul.w r8, r9, r4
|
|
80004a2: fb0e 1119 mls r1, lr, r9, r1
|
|
80004a6: b292 uxth r2, r2
|
|
80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
80004ac: 4542 cmp r2, r8
|
|
80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4>
|
|
80004b0: 18ba adds r2, r7, r2
|
|
80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222>
|
|
80004b8: 4542 cmp r2, r8
|
|
80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222>
|
|
80004bc: f1a9 0102 sub.w r1, r9, #2
|
|
80004c0: 443a add r2, r7
|
|
80004c2: e7be b.n 8000442 <__udivmoddi4+0x222>
|
|
80004c4: 45f0 cmp r8, lr
|
|
80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4>
|
|
80004c8: ebbe 0302 subs.w r3, lr, r2
|
|
80004cc: eb6c 0c07 sbc.w ip, ip, r7
|
|
80004d0: 3801 subs r0, #1
|
|
80004d2: 46e1 mov r9, ip
|
|
80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4>
|
|
80004d6: eba7 0909 sub.w r9, r7, r9
|
|
80004da: 4449 add r1, r9
|
|
80004dc: f1a8 0c02 sub.w ip, r8, #2
|
|
80004e0: fbb1 f9fe udiv r9, r1, lr
|
|
80004e4: fb09 f804 mul.w r8, r9, r4
|
|
80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282>
|
|
80004ea: 4673 mov r3, lr
|
|
80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce>
|
|
80004ee: 4650 mov r0, sl
|
|
80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0>
|
|
80004f2: 4608 mov r0, r1
|
|
80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2>
|
|
80004f6: 443b add r3, r7
|
|
80004f8: 3a02 subs r2, #2
|
|
80004fa: e733 b.n 8000364 <__udivmoddi4+0x144>
|
|
80004fc: f1ac 0c02 sub.w ip, ip, #2
|
|
8000500: 443b add r3, r7
|
|
8000502: e71c b.n 800033e <__udivmoddi4+0x11e>
|
|
8000504: 4649 mov r1, r9
|
|
8000506: e79c b.n 8000442 <__udivmoddi4+0x222>
|
|
8000508: eba1 0109 sub.w r1, r1, r9
|
|
800050c: 46c4 mov ip, r8
|
|
800050e: fbb1 f9fe udiv r9, r1, lr
|
|
8000512: fb09 f804 mul.w r8, r9, r4
|
|
8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282>
|
|
|
|
08000518 <__aeabi_idiv0>:
|
|
8000518: 4770 bx lr
|
|
800051a: bf00 nop
|
|
|
|
0800051c <vApplicationStackOverflowHook>:
|
|
}
|
|
/* USER CODE END 2 */
|
|
|
|
/* USER CODE BEGIN 4 */
|
|
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
|
|
{
|
|
800051c: b480 push {r7}
|
|
800051e: b083 sub sp, #12
|
|
8000520: af00 add r7, sp, #0
|
|
8000522: 6078 str r0, [r7, #4]
|
|
8000524: 6039 str r1, [r7, #0]
|
|
/* Run time stack overflow checking is performed if
|
|
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
|
|
called if a stack overflow is detected. */
|
|
}
|
|
8000526: bf00 nop
|
|
8000528: 370c adds r7, #12
|
|
800052a: 46bd mov sp, r7
|
|
800052c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000530: 4770 bx lr
|
|
...
|
|
|
|
08000534 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8000534: b580 push {r7, lr}
|
|
8000536: af00 add r7, sp, #0
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
8000538: f001 f81a bl 8001570 <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
800053c: f000 f826 bl 800058c <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8000540: f000 fa94 bl 8000a6c <MX_GPIO_Init>
|
|
MX_CRC_Init();
|
|
8000544: f000 f88c bl 8000660 <MX_CRC_Init>
|
|
MX_DMA2D_Init();
|
|
8000548: f000 f89e bl 8000688 <MX_DMA2D_Init>
|
|
MX_FMC_Init();
|
|
800054c: f000 fa3e bl 80009cc <MX_FMC_Init>
|
|
MX_I2C3_Init();
|
|
8000550: f000 f8cc bl 80006ec <MX_I2C3_Init>
|
|
MX_LTDC_Init();
|
|
8000554: f000 f90a bl 800076c <MX_LTDC_Init>
|
|
MX_SPI5_Init();
|
|
8000558: f000 f988 bl 800086c <MX_SPI5_Init>
|
|
MX_TIM1_Init();
|
|
800055c: f000 f9bc bl 80008d8 <MX_TIM1_Init>
|
|
MX_USART1_UART_Init();
|
|
8000560: f000 fa0a bl 8000978 <MX_USART1_UART_Init>
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
// Flashing lights go here
|
|
// Toggle LD3
|
|
HAL_GPIO_TogglePin(LD3_GPIO_Port, LD3_Pin);
|
|
8000564: f44f 5100 mov.w r1, #8192 @ 0x2000
|
|
8000568: 4807 ldr r0, [pc, #28] @ (8000588 <main+0x54>)
|
|
800056a: f001 fd16 bl 8001f9a <HAL_GPIO_TogglePin>
|
|
// Insert delay 100ms
|
|
HAL_Delay(200);
|
|
800056e: 20c8 movs r0, #200 @ 0xc8
|
|
8000570: f001 f840 bl 80015f4 <HAL_Delay>
|
|
|
|
// Toggle LD4
|
|
HAL_GPIO_TogglePin(LD4_GPIO_Port, LD4_Pin);
|
|
8000574: f44f 4180 mov.w r1, #16384 @ 0x4000
|
|
8000578: 4803 ldr r0, [pc, #12] @ (8000588 <main+0x54>)
|
|
800057a: f001 fd0e bl 8001f9a <HAL_GPIO_TogglePin>
|
|
// Insert delay 200ms
|
|
HAL_Delay(100);
|
|
800057e: 2064 movs r0, #100 @ 0x64
|
|
8000580: f001 f838 bl 80015f4 <HAL_Delay>
|
|
HAL_GPIO_TogglePin(LD3_GPIO_Port, LD3_Pin);
|
|
8000584: bf00 nop
|
|
8000586: e7ed b.n 8000564 <main+0x30>
|
|
8000588: 40021800 .word 0x40021800
|
|
|
|
0800058c <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
800058c: b580 push {r7, lr}
|
|
800058e: b094 sub sp, #80 @ 0x50
|
|
8000590: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000592: f107 0320 add.w r3, r7, #32
|
|
8000596: 2230 movs r2, #48 @ 0x30
|
|
8000598: 2100 movs r1, #0
|
|
800059a: 4618 mov r0, r3
|
|
800059c: f007 fc40 bl 8007e20 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
80005a0: f107 030c add.w r3, r7, #12
|
|
80005a4: 2200 movs r2, #0
|
|
80005a6: 601a str r2, [r3, #0]
|
|
80005a8: 605a str r2, [r3, #4]
|
|
80005aa: 609a str r2, [r3, #8]
|
|
80005ac: 60da str r2, [r3, #12]
|
|
80005ae: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80005b0: 2300 movs r3, #0
|
|
80005b2: 60bb str r3, [r7, #8]
|
|
80005b4: 4b28 ldr r3, [pc, #160] @ (8000658 <SystemClock_Config+0xcc>)
|
|
80005b6: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80005b8: 4a27 ldr r2, [pc, #156] @ (8000658 <SystemClock_Config+0xcc>)
|
|
80005ba: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80005be: 6413 str r3, [r2, #64] @ 0x40
|
|
80005c0: 4b25 ldr r3, [pc, #148] @ (8000658 <SystemClock_Config+0xcc>)
|
|
80005c2: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80005c4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80005c8: 60bb str r3, [r7, #8]
|
|
80005ca: 68bb ldr r3, [r7, #8]
|
|
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
|
|
80005cc: 2300 movs r3, #0
|
|
80005ce: 607b str r3, [r7, #4]
|
|
80005d0: 4b22 ldr r3, [pc, #136] @ (800065c <SystemClock_Config+0xd0>)
|
|
80005d2: 681b ldr r3, [r3, #0]
|
|
80005d4: f423 4340 bic.w r3, r3, #49152 @ 0xc000
|
|
80005d8: 4a20 ldr r2, [pc, #128] @ (800065c <SystemClock_Config+0xd0>)
|
|
80005da: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
80005de: 6013 str r3, [r2, #0]
|
|
80005e0: 4b1e ldr r3, [pc, #120] @ (800065c <SystemClock_Config+0xd0>)
|
|
80005e2: 681b ldr r3, [r3, #0]
|
|
80005e4: f403 4340 and.w r3, r3, #49152 @ 0xc000
|
|
80005e8: 607b str r3, [r7, #4]
|
|
80005ea: 687b ldr r3, [r7, #4]
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
|
80005ec: 2301 movs r3, #1
|
|
80005ee: 623b str r3, [r7, #32]
|
|
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
|
80005f0: f44f 3380 mov.w r3, #65536 @ 0x10000
|
|
80005f4: 627b str r3, [r7, #36] @ 0x24
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
80005f6: 2302 movs r3, #2
|
|
80005f8: 63bb str r3, [r7, #56] @ 0x38
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
|
80005fa: f44f 0380 mov.w r3, #4194304 @ 0x400000
|
|
80005fe: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLM = 4;
|
|
8000600: 2304 movs r3, #4
|
|
8000602: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLN = 72;
|
|
8000604: 2348 movs r3, #72 @ 0x48
|
|
8000606: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
|
|
8000608: 2302 movs r3, #2
|
|
800060a: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLQ = 3;
|
|
800060c: 2303 movs r3, #3
|
|
800060e: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8000610: f107 0320 add.w r3, r7, #32
|
|
8000614: 4618 mov r0, r3
|
|
8000616: f003 ff51 bl 80044bc <HAL_RCC_OscConfig>
|
|
800061a: 4603 mov r3, r0
|
|
800061c: 2b00 cmp r3, #0
|
|
800061e: d001 beq.n 8000624 <SystemClock_Config+0x98>
|
|
{
|
|
Error_Handler();
|
|
8000620: f000 fb46 bl 8000cb0 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8000624: 230f movs r3, #15
|
|
8000626: 60fb str r3, [r7, #12]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8000628: 2302 movs r3, #2
|
|
800062a: 613b str r3, [r7, #16]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
800062c: 2300 movs r3, #0
|
|
800062e: 617b str r3, [r7, #20]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
|
8000630: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000634: 61bb str r3, [r7, #24]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8000636: 2300 movs r3, #0
|
|
8000638: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
|
800063a: f107 030c add.w r3, r7, #12
|
|
800063e: 2102 movs r1, #2
|
|
8000640: 4618 mov r0, r3
|
|
8000642: f004 f9b3 bl 80049ac <HAL_RCC_ClockConfig>
|
|
8000646: 4603 mov r3, r0
|
|
8000648: 2b00 cmp r3, #0
|
|
800064a: d001 beq.n 8000650 <SystemClock_Config+0xc4>
|
|
{
|
|
Error_Handler();
|
|
800064c: f000 fb30 bl 8000cb0 <Error_Handler>
|
|
}
|
|
}
|
|
8000650: bf00 nop
|
|
8000652: 3750 adds r7, #80 @ 0x50
|
|
8000654: 46bd mov sp, r7
|
|
8000656: bd80 pop {r7, pc}
|
|
8000658: 40023800 .word 0x40023800
|
|
800065c: 40007000 .word 0x40007000
|
|
|
|
08000660 <MX_CRC_Init>:
|
|
* @brief CRC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_CRC_Init(void)
|
|
{
|
|
8000660: b580 push {r7, lr}
|
|
8000662: af00 add r7, sp, #0
|
|
/* USER CODE END CRC_Init 0 */
|
|
|
|
/* USER CODE BEGIN CRC_Init 1 */
|
|
|
|
/* USER CODE END CRC_Init 1 */
|
|
hcrc.Instance = CRC;
|
|
8000664: 4b06 ldr r3, [pc, #24] @ (8000680 <MX_CRC_Init+0x20>)
|
|
8000666: 4a07 ldr r2, [pc, #28] @ (8000684 <MX_CRC_Init+0x24>)
|
|
8000668: 601a str r2, [r3, #0]
|
|
if (HAL_CRC_Init(&hcrc) != HAL_OK)
|
|
800066a: 4805 ldr r0, [pc, #20] @ (8000680 <MX_CRC_Init+0x20>)
|
|
800066c: f001 f8c8 bl 8001800 <HAL_CRC_Init>
|
|
8000670: 4603 mov r3, r0
|
|
8000672: 2b00 cmp r3, #0
|
|
8000674: d001 beq.n 800067a <MX_CRC_Init+0x1a>
|
|
{
|
|
Error_Handler();
|
|
8000676: f000 fb1b bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN CRC_Init 2 */
|
|
|
|
/* USER CODE END CRC_Init 2 */
|
|
|
|
}
|
|
800067a: bf00 nop
|
|
800067c: bd80 pop {r7, pc}
|
|
800067e: bf00 nop
|
|
8000680: 2000002c .word 0x2000002c
|
|
8000684: 40023000 .word 0x40023000
|
|
|
|
08000688 <MX_DMA2D_Init>:
|
|
* @brief DMA2D Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_DMA2D_Init(void)
|
|
{
|
|
8000688: b580 push {r7, lr}
|
|
800068a: af00 add r7, sp, #0
|
|
/* USER CODE END DMA2D_Init 0 */
|
|
|
|
/* USER CODE BEGIN DMA2D_Init 1 */
|
|
|
|
/* USER CODE END DMA2D_Init 1 */
|
|
hdma2d.Instance = DMA2D;
|
|
800068c: 4b15 ldr r3, [pc, #84] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
800068e: 4a16 ldr r2, [pc, #88] @ (80006e8 <MX_DMA2D_Init+0x60>)
|
|
8000690: 601a str r2, [r3, #0]
|
|
hdma2d.Init.Mode = DMA2D_M2M;
|
|
8000692: 4b14 ldr r3, [pc, #80] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
8000694: 2200 movs r2, #0
|
|
8000696: 605a str r2, [r3, #4]
|
|
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
|
|
8000698: 4b12 ldr r3, [pc, #72] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
800069a: 2200 movs r2, #0
|
|
800069c: 609a str r2, [r3, #8]
|
|
hdma2d.Init.OutputOffset = 0;
|
|
800069e: 4b11 ldr r3, [pc, #68] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006a0: 2200 movs r2, #0
|
|
80006a2: 60da str r2, [r3, #12]
|
|
hdma2d.LayerCfg[1].InputOffset = 0;
|
|
80006a4: 4b0f ldr r3, [pc, #60] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006a6: 2200 movs r2, #0
|
|
80006a8: 629a str r2, [r3, #40] @ 0x28
|
|
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
|
|
80006aa: 4b0e ldr r3, [pc, #56] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006ac: 2200 movs r2, #0
|
|
80006ae: 62da str r2, [r3, #44] @ 0x2c
|
|
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
|
|
80006b0: 4b0c ldr r3, [pc, #48] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006b2: 2200 movs r2, #0
|
|
80006b4: 631a str r2, [r3, #48] @ 0x30
|
|
hdma2d.LayerCfg[1].InputAlpha = 0;
|
|
80006b6: 4b0b ldr r3, [pc, #44] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006b8: 2200 movs r2, #0
|
|
80006ba: 635a str r2, [r3, #52] @ 0x34
|
|
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
|
|
80006bc: 4809 ldr r0, [pc, #36] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006be: f001 f8bb bl 8001838 <HAL_DMA2D_Init>
|
|
80006c2: 4603 mov r3, r0
|
|
80006c4: 2b00 cmp r3, #0
|
|
80006c6: d001 beq.n 80006cc <MX_DMA2D_Init+0x44>
|
|
{
|
|
Error_Handler();
|
|
80006c8: f000 faf2 bl 8000cb0 <Error_Handler>
|
|
}
|
|
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
|
|
80006cc: 2101 movs r1, #1
|
|
80006ce: 4805 ldr r0, [pc, #20] @ (80006e4 <MX_DMA2D_Init+0x5c>)
|
|
80006d0: f001 fa0c bl 8001aec <HAL_DMA2D_ConfigLayer>
|
|
80006d4: 4603 mov r3, r0
|
|
80006d6: 2b00 cmp r3, #0
|
|
80006d8: d001 beq.n 80006de <MX_DMA2D_Init+0x56>
|
|
{
|
|
Error_Handler();
|
|
80006da: f000 fae9 bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN DMA2D_Init 2 */
|
|
|
|
/* USER CODE END DMA2D_Init 2 */
|
|
|
|
}
|
|
80006de: bf00 nop
|
|
80006e0: bd80 pop {r7, pc}
|
|
80006e2: bf00 nop
|
|
80006e4: 20000034 .word 0x20000034
|
|
80006e8: 4002b000 .word 0x4002b000
|
|
|
|
080006ec <MX_I2C3_Init>:
|
|
* @brief I2C3 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C3_Init(void)
|
|
{
|
|
80006ec: b580 push {r7, lr}
|
|
80006ee: af00 add r7, sp, #0
|
|
/* USER CODE END I2C3_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C3_Init 1 */
|
|
|
|
/* USER CODE END I2C3_Init 1 */
|
|
hi2c3.Instance = I2C3;
|
|
80006f0: 4b1b ldr r3, [pc, #108] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
80006f2: 4a1c ldr r2, [pc, #112] @ (8000764 <MX_I2C3_Init+0x78>)
|
|
80006f4: 601a str r2, [r3, #0]
|
|
hi2c3.Init.ClockSpeed = 100000;
|
|
80006f6: 4b1a ldr r3, [pc, #104] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
80006f8: 4a1b ldr r2, [pc, #108] @ (8000768 <MX_I2C3_Init+0x7c>)
|
|
80006fa: 605a str r2, [r3, #4]
|
|
hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2;
|
|
80006fc: 4b18 ldr r3, [pc, #96] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
80006fe: 2200 movs r2, #0
|
|
8000700: 609a str r2, [r3, #8]
|
|
hi2c3.Init.OwnAddress1 = 0;
|
|
8000702: 4b17 ldr r3, [pc, #92] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
8000704: 2200 movs r2, #0
|
|
8000706: 60da str r2, [r3, #12]
|
|
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8000708: 4b15 ldr r3, [pc, #84] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
800070a: f44f 4280 mov.w r2, #16384 @ 0x4000
|
|
800070e: 611a str r2, [r3, #16]
|
|
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8000710: 4b13 ldr r3, [pc, #76] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
8000712: 2200 movs r2, #0
|
|
8000714: 615a str r2, [r3, #20]
|
|
hi2c3.Init.OwnAddress2 = 0;
|
|
8000716: 4b12 ldr r3, [pc, #72] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
8000718: 2200 movs r2, #0
|
|
800071a: 619a str r2, [r3, #24]
|
|
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
800071c: 4b10 ldr r3, [pc, #64] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
800071e: 2200 movs r2, #0
|
|
8000720: 61da str r2, [r3, #28]
|
|
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8000722: 4b0f ldr r3, [pc, #60] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
8000724: 2200 movs r2, #0
|
|
8000726: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
|
|
8000728: 480d ldr r0, [pc, #52] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
800072a: f003 f9f7 bl 8003b1c <HAL_I2C_Init>
|
|
800072e: 4603 mov r3, r0
|
|
8000730: 2b00 cmp r3, #0
|
|
8000732: d001 beq.n 8000738 <MX_I2C3_Init+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8000734: f000 fabc bl 8000cb0 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8000738: 2100 movs r1, #0
|
|
800073a: 4809 ldr r0, [pc, #36] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
800073c: f003 fb32 bl 8003da4 <HAL_I2CEx_ConfigAnalogFilter>
|
|
8000740: 4603 mov r3, r0
|
|
8000742: 2b00 cmp r3, #0
|
|
8000744: d001 beq.n 800074a <MX_I2C3_Init+0x5e>
|
|
{
|
|
Error_Handler();
|
|
8000746: f000 fab3 bl 8000cb0 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
|
|
800074a: 2100 movs r1, #0
|
|
800074c: 4804 ldr r0, [pc, #16] @ (8000760 <MX_I2C3_Init+0x74>)
|
|
800074e: f003 fb65 bl 8003e1c <HAL_I2CEx_ConfigDigitalFilter>
|
|
8000752: 4603 mov r3, r0
|
|
8000754: 2b00 cmp r3, #0
|
|
8000756: d001 beq.n 800075c <MX_I2C3_Init+0x70>
|
|
{
|
|
Error_Handler();
|
|
8000758: f000 faaa bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C3_Init 2 */
|
|
|
|
/* USER CODE END I2C3_Init 2 */
|
|
|
|
}
|
|
800075c: bf00 nop
|
|
800075e: bd80 pop {r7, pc}
|
|
8000760: 20000074 .word 0x20000074
|
|
8000764: 40005c00 .word 0x40005c00
|
|
8000768: 000186a0 .word 0x000186a0
|
|
|
|
0800076c <MX_LTDC_Init>:
|
|
* @brief LTDC Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_LTDC_Init(void)
|
|
{
|
|
800076c: b580 push {r7, lr}
|
|
800076e: b08e sub sp, #56 @ 0x38
|
|
8000770: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN LTDC_Init 0 */
|
|
|
|
/* USER CODE END LTDC_Init 0 */
|
|
|
|
LTDC_LayerCfgTypeDef pLayerCfg = {0};
|
|
8000772: 1d3b adds r3, r7, #4
|
|
8000774: 2234 movs r2, #52 @ 0x34
|
|
8000776: 2100 movs r1, #0
|
|
8000778: 4618 mov r0, r3
|
|
800077a: f007 fb51 bl 8007e20 <memset>
|
|
|
|
/* USER CODE BEGIN LTDC_Init 1 */
|
|
|
|
/* USER CODE END LTDC_Init 1 */
|
|
hltdc.Instance = LTDC;
|
|
800077e: 4b39 ldr r3, [pc, #228] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
8000780: 4a39 ldr r2, [pc, #228] @ (8000868 <MX_LTDC_Init+0xfc>)
|
|
8000782: 601a str r2, [r3, #0]
|
|
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
|
|
8000784: 4b37 ldr r3, [pc, #220] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
8000786: 2200 movs r2, #0
|
|
8000788: 605a str r2, [r3, #4]
|
|
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
|
|
800078a: 4b36 ldr r3, [pc, #216] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
800078c: 2200 movs r2, #0
|
|
800078e: 609a str r2, [r3, #8]
|
|
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
|
|
8000790: 4b34 ldr r3, [pc, #208] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
8000792: 2200 movs r2, #0
|
|
8000794: 60da str r2, [r3, #12]
|
|
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
|
|
8000796: 4b33 ldr r3, [pc, #204] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
8000798: 2200 movs r2, #0
|
|
800079a: 611a str r2, [r3, #16]
|
|
hltdc.Init.HorizontalSync = 9;
|
|
800079c: 4b31 ldr r3, [pc, #196] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
800079e: 2209 movs r2, #9
|
|
80007a0: 615a str r2, [r3, #20]
|
|
hltdc.Init.VerticalSync = 1;
|
|
80007a2: 4b30 ldr r3, [pc, #192] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007a4: 2201 movs r2, #1
|
|
80007a6: 619a str r2, [r3, #24]
|
|
hltdc.Init.AccumulatedHBP = 29;
|
|
80007a8: 4b2e ldr r3, [pc, #184] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007aa: 221d movs r2, #29
|
|
80007ac: 61da str r2, [r3, #28]
|
|
hltdc.Init.AccumulatedVBP = 3;
|
|
80007ae: 4b2d ldr r3, [pc, #180] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007b0: 2203 movs r2, #3
|
|
80007b2: 621a str r2, [r3, #32]
|
|
hltdc.Init.AccumulatedActiveW = 269;
|
|
80007b4: 4b2b ldr r3, [pc, #172] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007b6: f240 120d movw r2, #269 @ 0x10d
|
|
80007ba: 625a str r2, [r3, #36] @ 0x24
|
|
hltdc.Init.AccumulatedActiveH = 323;
|
|
80007bc: 4b29 ldr r3, [pc, #164] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007be: f240 1243 movw r2, #323 @ 0x143
|
|
80007c2: 629a str r2, [r3, #40] @ 0x28
|
|
hltdc.Init.TotalWidth = 279;
|
|
80007c4: 4b27 ldr r3, [pc, #156] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007c6: f240 1217 movw r2, #279 @ 0x117
|
|
80007ca: 62da str r2, [r3, #44] @ 0x2c
|
|
hltdc.Init.TotalHeigh = 327;
|
|
80007cc: 4b25 ldr r3, [pc, #148] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007ce: f240 1247 movw r2, #327 @ 0x147
|
|
80007d2: 631a str r2, [r3, #48] @ 0x30
|
|
hltdc.Init.Backcolor.Blue = 0;
|
|
80007d4: 4b23 ldr r3, [pc, #140] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007d6: 2200 movs r2, #0
|
|
80007d8: f883 2034 strb.w r2, [r3, #52] @ 0x34
|
|
hltdc.Init.Backcolor.Green = 0;
|
|
80007dc: 4b21 ldr r3, [pc, #132] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007de: 2200 movs r2, #0
|
|
80007e0: f883 2035 strb.w r2, [r3, #53] @ 0x35
|
|
hltdc.Init.Backcolor.Red = 0;
|
|
80007e4: 4b1f ldr r3, [pc, #124] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007e6: 2200 movs r2, #0
|
|
80007e8: f883 2036 strb.w r2, [r3, #54] @ 0x36
|
|
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
|
|
80007ec: 481d ldr r0, [pc, #116] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
80007ee: f003 fb54 bl 8003e9a <HAL_LTDC_Init>
|
|
80007f2: 4603 mov r3, r0
|
|
80007f4: 2b00 cmp r3, #0
|
|
80007f6: d001 beq.n 80007fc <MX_LTDC_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
80007f8: f000 fa5a bl 8000cb0 <Error_Handler>
|
|
}
|
|
pLayerCfg.WindowX0 = 0;
|
|
80007fc: 2300 movs r3, #0
|
|
80007fe: 607b str r3, [r7, #4]
|
|
pLayerCfg.WindowX1 = 240;
|
|
8000800: 23f0 movs r3, #240 @ 0xf0
|
|
8000802: 60bb str r3, [r7, #8]
|
|
pLayerCfg.WindowY0 = 0;
|
|
8000804: 2300 movs r3, #0
|
|
8000806: 60fb str r3, [r7, #12]
|
|
pLayerCfg.WindowY1 = 320;
|
|
8000808: f44f 73a0 mov.w r3, #320 @ 0x140
|
|
800080c: 613b str r3, [r7, #16]
|
|
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
|
|
800080e: 2302 movs r3, #2
|
|
8000810: 617b str r3, [r7, #20]
|
|
pLayerCfg.Alpha = 255;
|
|
8000812: 23ff movs r3, #255 @ 0xff
|
|
8000814: 61bb str r3, [r7, #24]
|
|
pLayerCfg.Alpha0 = 0;
|
|
8000816: 2300 movs r3, #0
|
|
8000818: 61fb str r3, [r7, #28]
|
|
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
|
|
800081a: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
800081e: 623b str r3, [r7, #32]
|
|
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
|
|
8000820: 2307 movs r3, #7
|
|
8000822: 627b str r3, [r7, #36] @ 0x24
|
|
pLayerCfg.FBStartAdress = 0xD0000000;
|
|
8000824: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000
|
|
8000828: 62bb str r3, [r7, #40] @ 0x28
|
|
pLayerCfg.ImageWidth = 240;
|
|
800082a: 23f0 movs r3, #240 @ 0xf0
|
|
800082c: 62fb str r3, [r7, #44] @ 0x2c
|
|
pLayerCfg.ImageHeight = 320;
|
|
800082e: f44f 73a0 mov.w r3, #320 @ 0x140
|
|
8000832: 633b str r3, [r7, #48] @ 0x30
|
|
pLayerCfg.Backcolor.Blue = 0;
|
|
8000834: 2300 movs r3, #0
|
|
8000836: f887 3034 strb.w r3, [r7, #52] @ 0x34
|
|
pLayerCfg.Backcolor.Green = 0;
|
|
800083a: 2300 movs r3, #0
|
|
800083c: f887 3035 strb.w r3, [r7, #53] @ 0x35
|
|
pLayerCfg.Backcolor.Red = 0;
|
|
8000840: 2300 movs r3, #0
|
|
8000842: f887 3036 strb.w r3, [r7, #54] @ 0x36
|
|
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
|
|
8000846: 1d3b adds r3, r7, #4
|
|
8000848: 2200 movs r2, #0
|
|
800084a: 4619 mov r1, r3
|
|
800084c: 4805 ldr r0, [pc, #20] @ (8000864 <MX_LTDC_Init+0xf8>)
|
|
800084e: f003 fc83 bl 8004158 <HAL_LTDC_ConfigLayer>
|
|
8000852: 4603 mov r3, r0
|
|
8000854: 2b00 cmp r3, #0
|
|
8000856: d001 beq.n 800085c <MX_LTDC_Init+0xf0>
|
|
{
|
|
Error_Handler();
|
|
8000858: f000 fa2a bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN LTDC_Init 2 */
|
|
|
|
/* USER CODE END LTDC_Init 2 */
|
|
|
|
}
|
|
800085c: bf00 nop
|
|
800085e: 3738 adds r7, #56 @ 0x38
|
|
8000860: 46bd mov sp, r7
|
|
8000862: bd80 pop {r7, pc}
|
|
8000864: 200000c8 .word 0x200000c8
|
|
8000868: 40016800 .word 0x40016800
|
|
|
|
0800086c <MX_SPI5_Init>:
|
|
* @brief SPI5 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_SPI5_Init(void)
|
|
{
|
|
800086c: b580 push {r7, lr}
|
|
800086e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN SPI5_Init 1 */
|
|
|
|
/* USER CODE END SPI5_Init 1 */
|
|
/* SPI5 parameter configuration*/
|
|
hspi5.Instance = SPI5;
|
|
8000870: 4b17 ldr r3, [pc, #92] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000872: 4a18 ldr r2, [pc, #96] @ (80008d4 <MX_SPI5_Init+0x68>)
|
|
8000874: 601a str r2, [r3, #0]
|
|
hspi5.Init.Mode = SPI_MODE_MASTER;
|
|
8000876: 4b16 ldr r3, [pc, #88] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000878: f44f 7282 mov.w r2, #260 @ 0x104
|
|
800087c: 605a str r2, [r3, #4]
|
|
hspi5.Init.Direction = SPI_DIRECTION_2LINES;
|
|
800087e: 4b14 ldr r3, [pc, #80] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000880: 2200 movs r2, #0
|
|
8000882: 609a str r2, [r3, #8]
|
|
hspi5.Init.DataSize = SPI_DATASIZE_8BIT;
|
|
8000884: 4b12 ldr r3, [pc, #72] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000886: 2200 movs r2, #0
|
|
8000888: 60da str r2, [r3, #12]
|
|
hspi5.Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
800088a: 4b11 ldr r3, [pc, #68] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
800088c: 2200 movs r2, #0
|
|
800088e: 611a str r2, [r3, #16]
|
|
hspi5.Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
8000890: 4b0f ldr r3, [pc, #60] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000892: 2200 movs r2, #0
|
|
8000894: 615a str r2, [r3, #20]
|
|
hspi5.Init.NSS = SPI_NSS_SOFT;
|
|
8000896: 4b0e ldr r3, [pc, #56] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
8000898: f44f 7200 mov.w r2, #512 @ 0x200
|
|
800089c: 619a str r2, [r3, #24]
|
|
hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
|
800089e: 4b0c ldr r3, [pc, #48] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008a0: 2218 movs r2, #24
|
|
80008a2: 61da str r2, [r3, #28]
|
|
hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
|
80008a4: 4b0a ldr r3, [pc, #40] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008a6: 2200 movs r2, #0
|
|
80008a8: 621a str r2, [r3, #32]
|
|
hspi5.Init.TIMode = SPI_TIMODE_DISABLE;
|
|
80008aa: 4b09 ldr r3, [pc, #36] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008ac: 2200 movs r2, #0
|
|
80008ae: 625a str r2, [r3, #36] @ 0x24
|
|
hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
80008b0: 4b07 ldr r3, [pc, #28] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008b2: 2200 movs r2, #0
|
|
80008b4: 629a str r2, [r3, #40] @ 0x28
|
|
hspi5.Init.CRCPolynomial = 10;
|
|
80008b6: 4b06 ldr r3, [pc, #24] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008b8: 220a movs r2, #10
|
|
80008ba: 62da str r2, [r3, #44] @ 0x2c
|
|
if (HAL_SPI_Init(&hspi5) != HAL_OK)
|
|
80008bc: 4804 ldr r0, [pc, #16] @ (80008d0 <MX_SPI5_Init+0x64>)
|
|
80008be: f004 fcbb bl 8005238 <HAL_SPI_Init>
|
|
80008c2: 4603 mov r3, r0
|
|
80008c4: 2b00 cmp r3, #0
|
|
80008c6: d001 beq.n 80008cc <MX_SPI5_Init+0x60>
|
|
{
|
|
Error_Handler();
|
|
80008c8: f000 f9f2 bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN SPI5_Init 2 */
|
|
|
|
/* USER CODE END SPI5_Init 2 */
|
|
|
|
}
|
|
80008cc: bf00 nop
|
|
80008ce: bd80 pop {r7, pc}
|
|
80008d0: 20000170 .word 0x20000170
|
|
80008d4: 40015000 .word 0x40015000
|
|
|
|
080008d8 <MX_TIM1_Init>:
|
|
* @brief TIM1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_TIM1_Init(void)
|
|
{
|
|
80008d8: b580 push {r7, lr}
|
|
80008da: b086 sub sp, #24
|
|
80008dc: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN TIM1_Init 0 */
|
|
|
|
/* USER CODE END TIM1_Init 0 */
|
|
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
80008de: f107 0308 add.w r3, r7, #8
|
|
80008e2: 2200 movs r2, #0
|
|
80008e4: 601a str r2, [r3, #0]
|
|
80008e6: 605a str r2, [r3, #4]
|
|
80008e8: 609a str r2, [r3, #8]
|
|
80008ea: 60da str r2, [r3, #12]
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
80008ec: 463b mov r3, r7
|
|
80008ee: 2200 movs r2, #0
|
|
80008f0: 601a str r2, [r3, #0]
|
|
80008f2: 605a str r2, [r3, #4]
|
|
|
|
/* USER CODE BEGIN TIM1_Init 1 */
|
|
|
|
/* USER CODE END TIM1_Init 1 */
|
|
htim1.Instance = TIM1;
|
|
80008f4: 4b1e ldr r3, [pc, #120] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
80008f6: 4a1f ldr r2, [pc, #124] @ (8000974 <MX_TIM1_Init+0x9c>)
|
|
80008f8: 601a str r2, [r3, #0]
|
|
htim1.Init.Prescaler = 0;
|
|
80008fa: 4b1d ldr r3, [pc, #116] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
80008fc: 2200 movs r2, #0
|
|
80008fe: 605a str r2, [r3, #4]
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8000900: 4b1b ldr r3, [pc, #108] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
8000902: 2200 movs r2, #0
|
|
8000904: 609a str r2, [r3, #8]
|
|
htim1.Init.Period = 65535;
|
|
8000906: 4b1a ldr r3, [pc, #104] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
8000908: f64f 72ff movw r2, #65535 @ 0xffff
|
|
800090c: 60da str r2, [r3, #12]
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
800090e: 4b18 ldr r3, [pc, #96] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
8000910: 2200 movs r2, #0
|
|
8000912: 611a str r2, [r3, #16]
|
|
htim1.Init.RepetitionCounter = 0;
|
|
8000914: 4b16 ldr r3, [pc, #88] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
8000916: 2200 movs r2, #0
|
|
8000918: 615a str r2, [r3, #20]
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
800091a: 4b15 ldr r3, [pc, #84] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
800091c: 2200 movs r2, #0
|
|
800091e: 619a str r2, [r3, #24]
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
8000920: 4813 ldr r0, [pc, #76] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
8000922: f004 fd12 bl 800534a <HAL_TIM_Base_Init>
|
|
8000926: 4603 mov r3, r0
|
|
8000928: 2b00 cmp r3, #0
|
|
800092a: d001 beq.n 8000930 <MX_TIM1_Init+0x58>
|
|
{
|
|
Error_Handler();
|
|
800092c: f000 f9c0 bl 8000cb0 <Error_Handler>
|
|
}
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8000930: f44f 5380 mov.w r3, #4096 @ 0x1000
|
|
8000934: 60bb str r3, [r7, #8]
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
8000936: f107 0308 add.w r3, r7, #8
|
|
800093a: 4619 mov r1, r3
|
|
800093c: 480c ldr r0, [pc, #48] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
800093e: f004 feb3 bl 80056a8 <HAL_TIM_ConfigClockSource>
|
|
8000942: 4603 mov r3, r0
|
|
8000944: 2b00 cmp r3, #0
|
|
8000946: d001 beq.n 800094c <MX_TIM1_Init+0x74>
|
|
{
|
|
Error_Handler();
|
|
8000948: f000 f9b2 bl 8000cb0 <Error_Handler>
|
|
}
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
800094c: 2300 movs r3, #0
|
|
800094e: 603b str r3, [r7, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8000950: 2300 movs r3, #0
|
|
8000952: 607b str r3, [r7, #4]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
8000954: 463b mov r3, r7
|
|
8000956: 4619 mov r1, r3
|
|
8000958: 4805 ldr r0, [pc, #20] @ (8000970 <MX_TIM1_Init+0x98>)
|
|
800095a: f005 f8d5 bl 8005b08 <HAL_TIMEx_MasterConfigSynchronization>
|
|
800095e: 4603 mov r3, r0
|
|
8000960: 2b00 cmp r3, #0
|
|
8000962: d001 beq.n 8000968 <MX_TIM1_Init+0x90>
|
|
{
|
|
Error_Handler();
|
|
8000964: f000 f9a4 bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN TIM1_Init 2 */
|
|
|
|
/* USER CODE END TIM1_Init 2 */
|
|
|
|
}
|
|
8000968: bf00 nop
|
|
800096a: 3718 adds r7, #24
|
|
800096c: 46bd mov sp, r7
|
|
800096e: bd80 pop {r7, pc}
|
|
8000970: 200001c8 .word 0x200001c8
|
|
8000974: 40010000 .word 0x40010000
|
|
|
|
08000978 <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8000978: b580 push {r7, lr}
|
|
800097a: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
800097c: 4b11 ldr r3, [pc, #68] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
800097e: 4a12 ldr r2, [pc, #72] @ (80009c8 <MX_USART1_UART_Init+0x50>)
|
|
8000980: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8000982: 4b10 ldr r3, [pc, #64] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
8000984: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8000988: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
800098a: 4b0e ldr r3, [pc, #56] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
800098c: 2200 movs r2, #0
|
|
800098e: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8000990: 4b0c ldr r3, [pc, #48] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
8000992: 2200 movs r2, #0
|
|
8000994: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8000996: 4b0b ldr r3, [pc, #44] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
8000998: 2200 movs r2, #0
|
|
800099a: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
800099c: 4b09 ldr r3, [pc, #36] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
800099e: 220c movs r2, #12
|
|
80009a0: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
80009a2: 4b08 ldr r3, [pc, #32] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
80009a4: 2200 movs r2, #0
|
|
80009a6: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
80009a8: 4b06 ldr r3, [pc, #24] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
80009aa: 2200 movs r2, #0
|
|
80009ac: 61da str r2, [r3, #28]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
80009ae: 4805 ldr r0, [pc, #20] @ (80009c4 <MX_USART1_UART_Init+0x4c>)
|
|
80009b0: f005 f93a bl 8005c28 <HAL_UART_Init>
|
|
80009b4: 4603 mov r3, r0
|
|
80009b6: 2b00 cmp r3, #0
|
|
80009b8: d001 beq.n 80009be <MX_USART1_UART_Init+0x46>
|
|
{
|
|
Error_Handler();
|
|
80009ba: f000 f979 bl 8000cb0 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
80009be: bf00 nop
|
|
80009c0: bd80 pop {r7, pc}
|
|
80009c2: bf00 nop
|
|
80009c4: 20000210 .word 0x20000210
|
|
80009c8: 40011000 .word 0x40011000
|
|
|
|
080009cc <MX_FMC_Init>:
|
|
|
|
/* FMC initialization function */
|
|
static void MX_FMC_Init(void)
|
|
{
|
|
80009cc: b580 push {r7, lr}
|
|
80009ce: b088 sub sp, #32
|
|
80009d0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN FMC_Init 0 */
|
|
|
|
/* USER CODE END FMC_Init 0 */
|
|
|
|
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
|
|
80009d2: 1d3b adds r3, r7, #4
|
|
80009d4: 2200 movs r2, #0
|
|
80009d6: 601a str r2, [r3, #0]
|
|
80009d8: 605a str r2, [r3, #4]
|
|
80009da: 609a str r2, [r3, #8]
|
|
80009dc: 60da str r2, [r3, #12]
|
|
80009de: 611a str r2, [r3, #16]
|
|
80009e0: 615a str r2, [r3, #20]
|
|
80009e2: 619a str r2, [r3, #24]
|
|
|
|
/* USER CODE END FMC_Init 1 */
|
|
|
|
/** Perform the SDRAM1 memory initialization sequence
|
|
*/
|
|
hsdram1.Instance = FMC_SDRAM_DEVICE;
|
|
80009e4: 4b1f ldr r3, [pc, #124] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
80009e6: 4a20 ldr r2, [pc, #128] @ (8000a68 <MX_FMC_Init+0x9c>)
|
|
80009e8: 601a str r2, [r3, #0]
|
|
/* hsdram1.Init */
|
|
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
|
|
80009ea: 4b1e ldr r3, [pc, #120] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
80009ec: 2201 movs r2, #1
|
|
80009ee: 605a str r2, [r3, #4]
|
|
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
|
|
80009f0: 4b1c ldr r3, [pc, #112] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
80009f2: 2200 movs r2, #0
|
|
80009f4: 609a str r2, [r3, #8]
|
|
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
|
80009f6: 4b1b ldr r3, [pc, #108] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
80009f8: 2204 movs r2, #4
|
|
80009fa: 60da str r2, [r3, #12]
|
|
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
|
|
80009fc: 4b19 ldr r3, [pc, #100] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
80009fe: 2210 movs r2, #16
|
|
8000a00: 611a str r2, [r3, #16]
|
|
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
|
8000a02: 4b18 ldr r3, [pc, #96] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a04: 2240 movs r2, #64 @ 0x40
|
|
8000a06: 615a str r2, [r3, #20]
|
|
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
|
|
8000a08: 4b16 ldr r3, [pc, #88] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a0a: f44f 72c0 mov.w r2, #384 @ 0x180
|
|
8000a0e: 619a str r2, [r3, #24]
|
|
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
|
8000a10: 4b14 ldr r3, [pc, #80] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a12: 2200 movs r2, #0
|
|
8000a14: 61da str r2, [r3, #28]
|
|
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
|
|
8000a16: 4b13 ldr r3, [pc, #76] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a18: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8000a1c: 621a str r2, [r3, #32]
|
|
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
|
|
8000a1e: 4b11 ldr r3, [pc, #68] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a20: 2200 movs r2, #0
|
|
8000a22: 625a str r2, [r3, #36] @ 0x24
|
|
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
|
|
8000a24: 4b0f ldr r3, [pc, #60] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a26: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8000a2a: 629a str r2, [r3, #40] @ 0x28
|
|
/* SdramTiming */
|
|
SdramTiming.LoadToActiveDelay = 2;
|
|
8000a2c: 2302 movs r3, #2
|
|
8000a2e: 607b str r3, [r7, #4]
|
|
SdramTiming.ExitSelfRefreshDelay = 7;
|
|
8000a30: 2307 movs r3, #7
|
|
8000a32: 60bb str r3, [r7, #8]
|
|
SdramTiming.SelfRefreshTime = 4;
|
|
8000a34: 2304 movs r3, #4
|
|
8000a36: 60fb str r3, [r7, #12]
|
|
SdramTiming.RowCycleDelay = 7;
|
|
8000a38: 2307 movs r3, #7
|
|
8000a3a: 613b str r3, [r7, #16]
|
|
SdramTiming.WriteRecoveryTime = 3;
|
|
8000a3c: 2303 movs r3, #3
|
|
8000a3e: 617b str r3, [r7, #20]
|
|
SdramTiming.RPDelay = 2;
|
|
8000a40: 2302 movs r3, #2
|
|
8000a42: 61bb str r3, [r7, #24]
|
|
SdramTiming.RCDDelay = 2;
|
|
8000a44: 2302 movs r3, #2
|
|
8000a46: 61fb str r3, [r7, #28]
|
|
|
|
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
|
|
8000a48: 1d3b adds r3, r7, #4
|
|
8000a4a: 4619 mov r1, r3
|
|
8000a4c: 4805 ldr r0, [pc, #20] @ (8000a64 <MX_FMC_Init+0x98>)
|
|
8000a4e: f004 fbbf bl 80051d0 <HAL_SDRAM_Init>
|
|
8000a52: 4603 mov r3, r0
|
|
8000a54: 2b00 cmp r3, #0
|
|
8000a56: d001 beq.n 8000a5c <MX_FMC_Init+0x90>
|
|
{
|
|
Error_Handler( );
|
|
8000a58: f000 f92a bl 8000cb0 <Error_Handler>
|
|
}
|
|
|
|
/* USER CODE BEGIN FMC_Init 2 */
|
|
|
|
/* USER CODE END FMC_Init 2 */
|
|
}
|
|
8000a5c: bf00 nop
|
|
8000a5e: 3720 adds r7, #32
|
|
8000a60: 46bd mov sp, r7
|
|
8000a62: bd80 pop {r7, pc}
|
|
8000a64: 20000258 .word 0x20000258
|
|
8000a68: a0000140 .word 0xa0000140
|
|
|
|
08000a6c <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8000a6c: b580 push {r7, lr}
|
|
8000a6e: b08e sub sp, #56 @ 0x38
|
|
8000a70: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000a72: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000a76: 2200 movs r2, #0
|
|
8000a78: 601a str r2, [r3, #0]
|
|
8000a7a: 605a str r2, [r3, #4]
|
|
8000a7c: 609a str r2, [r3, #8]
|
|
8000a7e: 60da str r2, [r3, #12]
|
|
8000a80: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000a82: 2300 movs r3, #0
|
|
8000a84: 623b str r3, [r7, #32]
|
|
8000a86: 4b7b ldr r3, [pc, #492] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000a88: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a8a: 4a7a ldr r2, [pc, #488] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000a8c: f043 0304 orr.w r3, r3, #4
|
|
8000a90: 6313 str r3, [r2, #48] @ 0x30
|
|
8000a92: 4b78 ldr r3, [pc, #480] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000a94: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000a96: f003 0304 and.w r3, r3, #4
|
|
8000a9a: 623b str r3, [r7, #32]
|
|
8000a9c: 6a3b ldr r3, [r7, #32]
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8000a9e: 2300 movs r3, #0
|
|
8000aa0: 61fb str r3, [r7, #28]
|
|
8000aa2: 4b74 ldr r3, [pc, #464] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000aa4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000aa6: 4a73 ldr r2, [pc, #460] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000aa8: f043 0320 orr.w r3, r3, #32
|
|
8000aac: 6313 str r3, [r2, #48] @ 0x30
|
|
8000aae: 4b71 ldr r3, [pc, #452] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000ab0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ab2: f003 0320 and.w r3, r3, #32
|
|
8000ab6: 61fb str r3, [r7, #28]
|
|
8000ab8: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOH_CLK_ENABLE();
|
|
8000aba: 2300 movs r3, #0
|
|
8000abc: 61bb str r3, [r7, #24]
|
|
8000abe: 4b6d ldr r3, [pc, #436] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000ac0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ac2: 4a6c ldr r2, [pc, #432] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000ac4: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8000ac8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000aca: 4b6a ldr r3, [pc, #424] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000acc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ace: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8000ad2: 61bb str r3, [r7, #24]
|
|
8000ad4: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000ad6: 2300 movs r3, #0
|
|
8000ad8: 617b str r3, [r7, #20]
|
|
8000ada: 4b66 ldr r3, [pc, #408] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000adc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ade: 4a65 ldr r2, [pc, #404] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000ae0: f043 0301 orr.w r3, r3, #1
|
|
8000ae4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000ae6: 4b63 ldr r3, [pc, #396] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000ae8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000aea: f003 0301 and.w r3, r3, #1
|
|
8000aee: 617b str r3, [r7, #20]
|
|
8000af0: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000af2: 2300 movs r3, #0
|
|
8000af4: 613b str r3, [r7, #16]
|
|
8000af6: 4b5f ldr r3, [pc, #380] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000af8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000afa: 4a5e ldr r2, [pc, #376] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000afc: f043 0302 orr.w r3, r3, #2
|
|
8000b00: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b02: 4b5c ldr r3, [pc, #368] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b04: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b06: f003 0302 and.w r3, r3, #2
|
|
8000b0a: 613b str r3, [r7, #16]
|
|
8000b0c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8000b0e: 2300 movs r3, #0
|
|
8000b10: 60fb str r3, [r7, #12]
|
|
8000b12: 4b58 ldr r3, [pc, #352] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b14: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b16: 4a57 ldr r2, [pc, #348] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b18: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8000b1c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b1e: 4b55 ldr r3, [pc, #340] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b20: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b22: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8000b26: 60fb str r3, [r7, #12]
|
|
8000b28: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOE_CLK_ENABLE();
|
|
8000b2a: 2300 movs r3, #0
|
|
8000b2c: 60bb str r3, [r7, #8]
|
|
8000b2e: 4b51 ldr r3, [pc, #324] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b30: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b32: 4a50 ldr r2, [pc, #320] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b34: f043 0310 orr.w r3, r3, #16
|
|
8000b38: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b3a: 4b4e ldr r3, [pc, #312] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b3c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b3e: f003 0310 and.w r3, r3, #16
|
|
8000b42: 60bb str r3, [r7, #8]
|
|
8000b44: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000b46: 2300 movs r3, #0
|
|
8000b48: 607b str r3, [r7, #4]
|
|
8000b4a: 4b4a ldr r3, [pc, #296] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b4c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b4e: 4a49 ldr r2, [pc, #292] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b50: f043 0308 orr.w r3, r3, #8
|
|
8000b54: 6313 str r3, [r2, #48] @ 0x30
|
|
8000b56: 4b47 ldr r3, [pc, #284] @ (8000c74 <MX_GPIO_Init+0x208>)
|
|
8000b58: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000b5a: f003 0308 and.w r3, r3, #8
|
|
8000b5e: 607b str r3, [r7, #4]
|
|
8000b60: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET);
|
|
8000b62: 2200 movs r2, #0
|
|
8000b64: 2116 movs r1, #22
|
|
8000b66: 4844 ldr r0, [pc, #272] @ (8000c78 <MX_GPIO_Init+0x20c>)
|
|
8000b68: f001 f9fe bl 8001f68 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET);
|
|
8000b6c: 2200 movs r2, #0
|
|
8000b6e: 2180 movs r1, #128 @ 0x80
|
|
8000b70: 4842 ldr r0, [pc, #264] @ (8000c7c <MX_GPIO_Init+0x210>)
|
|
8000b72: f001 f9f9 bl 8001f68 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET);
|
|
8000b76: 2200 movs r2, #0
|
|
8000b78: f44f 5140 mov.w r1, #12288 @ 0x3000
|
|
8000b7c: 4840 ldr r0, [pc, #256] @ (8000c80 <MX_GPIO_Init+0x214>)
|
|
8000b7e: f001 f9f3 bl 8001f68 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET);
|
|
8000b82: 2200 movs r2, #0
|
|
8000b84: f44f 41c0 mov.w r1, #24576 @ 0x6000
|
|
8000b88: 483e ldr r0, [pc, #248] @ (8000c84 <MX_GPIO_Init+0x218>)
|
|
8000b8a: f001 f9ed bl 8001f68 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */
|
|
GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin;
|
|
8000b8e: 2316 movs r3, #22
|
|
8000b90: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000b92: 2301 movs r3, #1
|
|
8000b94: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000b96: 2300 movs r3, #0
|
|
8000b98: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000b9a: 2300 movs r3, #0
|
|
8000b9c: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8000b9e: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000ba2: 4619 mov r1, r3
|
|
8000ba4: 4834 ldr r0, [pc, #208] @ (8000c78 <MX_GPIO_Init+0x20c>)
|
|
8000ba6: f001 f833 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */
|
|
GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin;
|
|
8000baa: f248 0307 movw r3, #32775 @ 0x8007
|
|
8000bae: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8000bb0: f44f 1390 mov.w r3, #1179648 @ 0x120000
|
|
8000bb4: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bb6: 2300 movs r3, #0
|
|
8000bb8: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000bba: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000bbe: 4619 mov r1, r3
|
|
8000bc0: 482e ldr r0, [pc, #184] @ (8000c7c <MX_GPIO_Init+0x210>)
|
|
8000bc2: f001 f825 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : ACP_RST_Pin */
|
|
GPIO_InitStruct.Pin = ACP_RST_Pin;
|
|
8000bc6: 2380 movs r3, #128 @ 0x80
|
|
8000bc8: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000bca: 2301 movs r3, #1
|
|
8000bcc: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bce: 2300 movs r3, #0
|
|
8000bd0: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000bd2: 2300 movs r3, #0
|
|
8000bd4: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct);
|
|
8000bd6: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000bda: 4619 mov r1, r3
|
|
8000bdc: 4827 ldr r0, [pc, #156] @ (8000c7c <MX_GPIO_Init+0x210>)
|
|
8000bde: f001 f817 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : OTG_FS_OC_Pin */
|
|
GPIO_InitStruct.Pin = OTG_FS_OC_Pin;
|
|
8000be2: 2320 movs r3, #32
|
|
8000be4: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
|
|
8000be6: f44f 1390 mov.w r3, #1179648 @ 0x120000
|
|
8000bea: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000bec: 2300 movs r3, #0
|
|
8000bee: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct);
|
|
8000bf0: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000bf4: 4619 mov r1, r3
|
|
8000bf6: 4820 ldr r0, [pc, #128] @ (8000c78 <MX_GPIO_Init+0x20c>)
|
|
8000bf8: f001 f80a bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : BOOT1_Pin */
|
|
GPIO_InitStruct.Pin = BOOT1_Pin;
|
|
8000bfc: 2304 movs r3, #4
|
|
8000bfe: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c00: 2300 movs r3, #0
|
|
8000c02: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c04: 2300 movs r3, #0
|
|
8000c06: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
|
|
8000c08: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c0c: 4619 mov r1, r3
|
|
8000c0e: 481e ldr r0, [pc, #120] @ (8000c88 <MX_GPIO_Init+0x21c>)
|
|
8000c10: f000 fffe bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pin : TE_Pin */
|
|
GPIO_InitStruct.Pin = TE_Pin;
|
|
8000c14: f44f 6300 mov.w r3, #2048 @ 0x800
|
|
8000c18: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
|
8000c1a: 2300 movs r3, #0
|
|
8000c1c: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c1e: 2300 movs r3, #0
|
|
8000c20: 62fb str r3, [r7, #44] @ 0x2c
|
|
HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct);
|
|
8000c22: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c26: 4619 mov r1, r3
|
|
8000c28: 4815 ldr r0, [pc, #84] @ (8000c80 <MX_GPIO_Init+0x214>)
|
|
8000c2a: f000 fff1 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */
|
|
GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin;
|
|
8000c2e: f44f 5340 mov.w r3, #12288 @ 0x3000
|
|
8000c32: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c34: 2301 movs r3, #1
|
|
8000c36: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c38: 2300 movs r3, #0
|
|
8000c3a: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c3c: 2300 movs r3, #0
|
|
8000c3e: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8000c40: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c44: 4619 mov r1, r3
|
|
8000c46: 480e ldr r0, [pc, #56] @ (8000c80 <MX_GPIO_Init+0x214>)
|
|
8000c48: f000 ffe2 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : LD3_Pin LD4_Pin */
|
|
GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin;
|
|
8000c4c: f44f 43c0 mov.w r3, #24576 @ 0x6000
|
|
8000c50: 627b str r3, [r7, #36] @ 0x24
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8000c52: 2301 movs r3, #1
|
|
8000c54: 62bb str r3, [r7, #40] @ 0x28
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000c56: 2300 movs r3, #0
|
|
8000c58: 62fb str r3, [r7, #44] @ 0x2c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000c5a: 2300 movs r3, #0
|
|
8000c5c: 633b str r3, [r7, #48] @ 0x30
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8000c5e: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000c62: 4619 mov r1, r3
|
|
8000c64: 4807 ldr r0, [pc, #28] @ (8000c84 <MX_GPIO_Init+0x218>)
|
|
8000c66: f000 ffd3 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8000c6a: bf00 nop
|
|
8000c6c: 3738 adds r7, #56 @ 0x38
|
|
8000c6e: 46bd mov sp, r7
|
|
8000c70: bd80 pop {r7, pc}
|
|
8000c72: bf00 nop
|
|
8000c74: 40023800 .word 0x40023800
|
|
8000c78: 40020800 .word 0x40020800
|
|
8000c7c: 40020000 .word 0x40020000
|
|
8000c80: 40020c00 .word 0x40020c00
|
|
8000c84: 40021800 .word 0x40021800
|
|
8000c88: 40020400 .word 0x40020400
|
|
|
|
08000c8c <HAL_TIM_PeriodElapsedCallback>:
|
|
* a global variable "uwTick" used as application time base.
|
|
* @param htim : TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8000c8c: b580 push {r7, lr}
|
|
8000c8e: b082 sub sp, #8
|
|
8000c90: af00 add r7, sp, #0
|
|
8000c92: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN Callback 0 */
|
|
|
|
/* USER CODE END Callback 0 */
|
|
if (htim->Instance == TIM6)
|
|
8000c94: 687b ldr r3, [r7, #4]
|
|
8000c96: 681b ldr r3, [r3, #0]
|
|
8000c98: 4a04 ldr r2, [pc, #16] @ (8000cac <HAL_TIM_PeriodElapsedCallback+0x20>)
|
|
8000c9a: 4293 cmp r3, r2
|
|
8000c9c: d101 bne.n 8000ca2 <HAL_TIM_PeriodElapsedCallback+0x16>
|
|
{
|
|
HAL_IncTick();
|
|
8000c9e: f000 fc89 bl 80015b4 <HAL_IncTick>
|
|
}
|
|
/* USER CODE BEGIN Callback 1 */
|
|
|
|
/* USER CODE END Callback 1 */
|
|
}
|
|
8000ca2: bf00 nop
|
|
8000ca4: 3708 adds r7, #8
|
|
8000ca6: 46bd mov sp, r7
|
|
8000ca8: bd80 pop {r7, pc}
|
|
8000caa: bf00 nop
|
|
8000cac: 40001000 .word 0x40001000
|
|
|
|
08000cb0 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8000cb0: b480 push {r7}
|
|
8000cb2: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8000cb4: b672 cpsid i
|
|
}
|
|
8000cb6: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8000cb8: bf00 nop
|
|
8000cba: e7fd b.n 8000cb8 <Error_Handler+0x8>
|
|
|
|
08000cbc <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8000cbc: b580 push {r7, lr}
|
|
8000cbe: b082 sub sp, #8
|
|
8000cc0: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8000cc2: 2300 movs r3, #0
|
|
8000cc4: 607b str r3, [r7, #4]
|
|
8000cc6: 4b12 ldr r3, [pc, #72] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000cc8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000cca: 4a11 ldr r2, [pc, #68] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000ccc: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8000cd0: 6453 str r3, [r2, #68] @ 0x44
|
|
8000cd2: 4b0f ldr r3, [pc, #60] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000cd4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000cd6: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8000cda: 607b str r3, [r7, #4]
|
|
8000cdc: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8000cde: 2300 movs r3, #0
|
|
8000ce0: 603b str r3, [r7, #0]
|
|
8000ce2: 4b0b ldr r3, [pc, #44] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000ce4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000ce6: 4a0a ldr r2, [pc, #40] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000ce8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8000cec: 6413 str r3, [r2, #64] @ 0x40
|
|
8000cee: 4b08 ldr r3, [pc, #32] @ (8000d10 <HAL_MspInit+0x54>)
|
|
8000cf0: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000cf2: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8000cf6: 603b str r3, [r7, #0]
|
|
8000cf8: 683b ldr r3, [r7, #0]
|
|
|
|
/* System interrupt init*/
|
|
/* PendSV_IRQn interrupt configuration */
|
|
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
|
|
8000cfa: 2200 movs r2, #0
|
|
8000cfc: 210f movs r1, #15
|
|
8000cfe: f06f 0001 mvn.w r0, #1
|
|
8000d02: f000 fd53 bl 80017ac <HAL_NVIC_SetPriority>
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8000d06: bf00 nop
|
|
8000d08: 3708 adds r7, #8
|
|
8000d0a: 46bd mov sp, r7
|
|
8000d0c: bd80 pop {r7, pc}
|
|
8000d0e: bf00 nop
|
|
8000d10: 40023800 .word 0x40023800
|
|
|
|
08000d14 <HAL_CRC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hcrc: CRC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
|
|
{
|
|
8000d14: b480 push {r7}
|
|
8000d16: b085 sub sp, #20
|
|
8000d18: af00 add r7, sp, #0
|
|
8000d1a: 6078 str r0, [r7, #4]
|
|
if(hcrc->Instance==CRC)
|
|
8000d1c: 687b ldr r3, [r7, #4]
|
|
8000d1e: 681b ldr r3, [r3, #0]
|
|
8000d20: 4a0b ldr r2, [pc, #44] @ (8000d50 <HAL_CRC_MspInit+0x3c>)
|
|
8000d22: 4293 cmp r3, r2
|
|
8000d24: d10d bne.n 8000d42 <HAL_CRC_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN CRC_MspInit 0 */
|
|
|
|
/* USER CODE END CRC_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_CRC_CLK_ENABLE();
|
|
8000d26: 2300 movs r3, #0
|
|
8000d28: 60fb str r3, [r7, #12]
|
|
8000d2a: 4b0a ldr r3, [pc, #40] @ (8000d54 <HAL_CRC_MspInit+0x40>)
|
|
8000d2c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d2e: 4a09 ldr r2, [pc, #36] @ (8000d54 <HAL_CRC_MspInit+0x40>)
|
|
8000d30: f443 5380 orr.w r3, r3, #4096 @ 0x1000
|
|
8000d34: 6313 str r3, [r2, #48] @ 0x30
|
|
8000d36: 4b07 ldr r3, [pc, #28] @ (8000d54 <HAL_CRC_MspInit+0x40>)
|
|
8000d38: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d3a: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8000d3e: 60fb str r3, [r7, #12]
|
|
8000d40: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END CRC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000d42: bf00 nop
|
|
8000d44: 3714 adds r7, #20
|
|
8000d46: 46bd mov sp, r7
|
|
8000d48: f85d 7b04 ldr.w r7, [sp], #4
|
|
8000d4c: 4770 bx lr
|
|
8000d4e: bf00 nop
|
|
8000d50: 40023000 .word 0x40023000
|
|
8000d54: 40023800 .word 0x40023800
|
|
|
|
08000d58 <HAL_DMA2D_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hdma2d: DMA2D handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
|
|
{
|
|
8000d58: b580 push {r7, lr}
|
|
8000d5a: b084 sub sp, #16
|
|
8000d5c: af00 add r7, sp, #0
|
|
8000d5e: 6078 str r0, [r7, #4]
|
|
if(hdma2d->Instance==DMA2D)
|
|
8000d60: 687b ldr r3, [r7, #4]
|
|
8000d62: 681b ldr r3, [r3, #0]
|
|
8000d64: 4a0e ldr r2, [pc, #56] @ (8000da0 <HAL_DMA2D_MspInit+0x48>)
|
|
8000d66: 4293 cmp r3, r2
|
|
8000d68: d115 bne.n 8000d96 <HAL_DMA2D_MspInit+0x3e>
|
|
{
|
|
/* USER CODE BEGIN DMA2D_MspInit 0 */
|
|
|
|
/* USER CODE END DMA2D_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_DMA2D_CLK_ENABLE();
|
|
8000d6a: 2300 movs r3, #0
|
|
8000d6c: 60fb str r3, [r7, #12]
|
|
8000d6e: 4b0d ldr r3, [pc, #52] @ (8000da4 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000d70: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d72: 4a0c ldr r2, [pc, #48] @ (8000da4 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000d74: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
8000d78: 6313 str r3, [r2, #48] @ 0x30
|
|
8000d7a: 4b0a ldr r3, [pc, #40] @ (8000da4 <HAL_DMA2D_MspInit+0x4c>)
|
|
8000d7c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000d7e: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8000d82: 60fb str r3, [r7, #12]
|
|
8000d84: 68fb ldr r3, [r7, #12]
|
|
/* DMA2D interrupt Init */
|
|
HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
|
|
8000d86: 2200 movs r2, #0
|
|
8000d88: 2105 movs r1, #5
|
|
8000d8a: 205a movs r0, #90 @ 0x5a
|
|
8000d8c: f000 fd0e bl 80017ac <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
|
|
8000d90: 205a movs r0, #90 @ 0x5a
|
|
8000d92: f000 fd27 bl 80017e4 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END DMA2D_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000d96: bf00 nop
|
|
8000d98: 3710 adds r7, #16
|
|
8000d9a: 46bd mov sp, r7
|
|
8000d9c: bd80 pop {r7, pc}
|
|
8000d9e: bf00 nop
|
|
8000da0: 4002b000 .word 0x4002b000
|
|
8000da4: 40023800 .word 0x40023800
|
|
|
|
08000da8 <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8000da8: b580 push {r7, lr}
|
|
8000daa: b08a sub sp, #40 @ 0x28
|
|
8000dac: af00 add r7, sp, #0
|
|
8000dae: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000db0: f107 0314 add.w r3, r7, #20
|
|
8000db4: 2200 movs r2, #0
|
|
8000db6: 601a str r2, [r3, #0]
|
|
8000db8: 605a str r2, [r3, #4]
|
|
8000dba: 609a str r2, [r3, #8]
|
|
8000dbc: 60da str r2, [r3, #12]
|
|
8000dbe: 611a str r2, [r3, #16]
|
|
if(hi2c->Instance==I2C3)
|
|
8000dc0: 687b ldr r3, [r7, #4]
|
|
8000dc2: 681b ldr r3, [r3, #0]
|
|
8000dc4: 4a29 ldr r2, [pc, #164] @ (8000e6c <HAL_I2C_MspInit+0xc4>)
|
|
8000dc6: 4293 cmp r3, r2
|
|
8000dc8: d14b bne.n 8000e62 <HAL_I2C_MspInit+0xba>
|
|
{
|
|
/* USER CODE BEGIN I2C3_MspInit 0 */
|
|
|
|
/* USER CODE END I2C3_MspInit 0 */
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000dca: 2300 movs r3, #0
|
|
8000dcc: 613b str r3, [r7, #16]
|
|
8000dce: 4b28 ldr r3, [pc, #160] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000dd0: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dd2: 4a27 ldr r2, [pc, #156] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000dd4: f043 0304 orr.w r3, r3, #4
|
|
8000dd8: 6313 str r3, [r2, #48] @ 0x30
|
|
8000dda: 4b25 ldr r3, [pc, #148] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000ddc: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dde: f003 0304 and.w r3, r3, #4
|
|
8000de2: 613b str r3, [r7, #16]
|
|
8000de4: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000de6: 2300 movs r3, #0
|
|
8000de8: 60fb str r3, [r7, #12]
|
|
8000dea: 4b21 ldr r3, [pc, #132] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000dec: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dee: 4a20 ldr r2, [pc, #128] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000df0: f043 0301 orr.w r3, r3, #1
|
|
8000df4: 6313 str r3, [r2, #48] @ 0x30
|
|
8000df6: 4b1e ldr r3, [pc, #120] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000df8: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000dfa: f003 0301 and.w r3, r3, #1
|
|
8000dfe: 60fb str r3, [r7, #12]
|
|
8000e00: 68fb ldr r3, [r7, #12]
|
|
/**I2C3 GPIO Configuration
|
|
PC9 ------> I2C3_SDA
|
|
PA8 ------> I2C3_SCL
|
|
*/
|
|
GPIO_InitStruct.Pin = I2C3_SDA_Pin;
|
|
8000e02: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8000e06: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000e08: 2312 movs r3, #18
|
|
8000e0a: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8000e0c: 2301 movs r3, #1
|
|
8000e0e: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000e10: 2300 movs r3, #0
|
|
8000e12: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
|
|
8000e14: 2304 movs r3, #4
|
|
8000e16: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct);
|
|
8000e18: f107 0314 add.w r3, r7, #20
|
|
8000e1c: 4619 mov r1, r3
|
|
8000e1e: 4815 ldr r0, [pc, #84] @ (8000e74 <HAL_I2C_MspInit+0xcc>)
|
|
8000e20: f000 fef6 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = I2C3_SCL_Pin;
|
|
8000e24: f44f 7380 mov.w r3, #256 @ 0x100
|
|
8000e28: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8000e2a: 2312 movs r3, #18
|
|
8000e2c: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
|
8000e2e: 2301 movs r3, #1
|
|
8000e30: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000e32: 2300 movs r3, #0
|
|
8000e34: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
|
|
8000e36: 2304 movs r3, #4
|
|
8000e38: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct);
|
|
8000e3a: f107 0314 add.w r3, r7, #20
|
|
8000e3e: 4619 mov r1, r3
|
|
8000e40: 480d ldr r0, [pc, #52] @ (8000e78 <HAL_I2C_MspInit+0xd0>)
|
|
8000e42: f000 fee5 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C3_CLK_ENABLE();
|
|
8000e46: 2300 movs r3, #0
|
|
8000e48: 60bb str r3, [r7, #8]
|
|
8000e4a: 4b09 ldr r3, [pc, #36] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000e4c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000e4e: 4a08 ldr r2, [pc, #32] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000e50: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
|
|
8000e54: 6413 str r3, [r2, #64] @ 0x40
|
|
8000e56: 4b06 ldr r3, [pc, #24] @ (8000e70 <HAL_I2C_MspInit+0xc8>)
|
|
8000e58: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8000e5a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8000e5e: 60bb str r3, [r7, #8]
|
|
8000e60: 68bb ldr r3, [r7, #8]
|
|
|
|
/* USER CODE END I2C3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8000e62: bf00 nop
|
|
8000e64: 3728 adds r7, #40 @ 0x28
|
|
8000e66: 46bd mov sp, r7
|
|
8000e68: bd80 pop {r7, pc}
|
|
8000e6a: bf00 nop
|
|
8000e6c: 40005c00 .word 0x40005c00
|
|
8000e70: 40023800 .word 0x40023800
|
|
8000e74: 40020800 .word 0x40020800
|
|
8000e78: 40020000 .word 0x40020000
|
|
|
|
08000e7c <HAL_LTDC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hltdc: LTDC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
|
|
{
|
|
8000e7c: b580 push {r7, lr}
|
|
8000e7e: b09a sub sp, #104 @ 0x68
|
|
8000e80: af00 add r7, sp, #0
|
|
8000e82: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8000e84: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8000e88: 2200 movs r2, #0
|
|
8000e8a: 601a str r2, [r3, #0]
|
|
8000e8c: 605a str r2, [r3, #4]
|
|
8000e8e: 609a str r2, [r3, #8]
|
|
8000e90: 60da str r2, [r3, #12]
|
|
8000e92: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
|
8000e94: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000e98: 2230 movs r2, #48 @ 0x30
|
|
8000e9a: 2100 movs r1, #0
|
|
8000e9c: 4618 mov r0, r3
|
|
8000e9e: f006 ffbf bl 8007e20 <memset>
|
|
if(hltdc->Instance==LTDC)
|
|
8000ea2: 687b ldr r3, [r7, #4]
|
|
8000ea4: 681b ldr r3, [r3, #0]
|
|
8000ea6: 4a85 ldr r2, [pc, #532] @ (80010bc <HAL_LTDC_MspInit+0x240>)
|
|
8000ea8: 4293 cmp r3, r2
|
|
8000eaa: f040 8102 bne.w 80010b2 <HAL_LTDC_MspInit+0x236>
|
|
|
|
/* USER CODE END LTDC_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
|
|
8000eae: 2308 movs r3, #8
|
|
8000eb0: 627b str r3, [r7, #36] @ 0x24
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIN = 50;
|
|
8000eb2: 2332 movs r3, #50 @ 0x32
|
|
8000eb4: 637b str r3, [r7, #52] @ 0x34
|
|
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
|
|
8000eb6: 2302 movs r3, #2
|
|
8000eb8: 63fb str r3, [r7, #60] @ 0x3c
|
|
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
|
|
8000eba: 2300 movs r3, #0
|
|
8000ebc: 64bb str r3, [r7, #72] @ 0x48
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
|
8000ebe: f107 0324 add.w r3, r7, #36 @ 0x24
|
|
8000ec2: 4618 mov r0, r3
|
|
8000ec4: f003 ffc4 bl 8004e50 <HAL_RCCEx_PeriphCLKConfig>
|
|
8000ec8: 4603 mov r3, r0
|
|
8000eca: 2b00 cmp r3, #0
|
|
8000ecc: d001 beq.n 8000ed2 <HAL_LTDC_MspInit+0x56>
|
|
{
|
|
Error_Handler();
|
|
8000ece: f7ff feef bl 8000cb0 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_LTDC_CLK_ENABLE();
|
|
8000ed2: 2300 movs r3, #0
|
|
8000ed4: 623b str r3, [r7, #32]
|
|
8000ed6: 4b7a ldr r3, [pc, #488] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000ed8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000eda: 4a79 ldr r2, [pc, #484] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000edc: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8000ee0: 6453 str r3, [r2, #68] @ 0x44
|
|
8000ee2: 4b77 ldr r3, [pc, #476] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000ee4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8000ee6: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8000eea: 623b str r3, [r7, #32]
|
|
8000eec: 6a3b ldr r3, [r7, #32]
|
|
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8000eee: 2300 movs r3, #0
|
|
8000ef0: 61fb str r3, [r7, #28]
|
|
8000ef2: 4b73 ldr r3, [pc, #460] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000ef4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000ef6: 4a72 ldr r2, [pc, #456] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000ef8: f043 0320 orr.w r3, r3, #32
|
|
8000efc: 6313 str r3, [r2, #48] @ 0x30
|
|
8000efe: 4b70 ldr r3, [pc, #448] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f00: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f02: f003 0320 and.w r3, r3, #32
|
|
8000f06: 61fb str r3, [r7, #28]
|
|
8000f08: 69fb ldr r3, [r7, #28]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8000f0a: 2300 movs r3, #0
|
|
8000f0c: 61bb str r3, [r7, #24]
|
|
8000f0e: 4b6c ldr r3, [pc, #432] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f10: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f12: 4a6b ldr r2, [pc, #428] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f14: f043 0301 orr.w r3, r3, #1
|
|
8000f18: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f1a: 4b69 ldr r3, [pc, #420] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f1c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f1e: f003 0301 and.w r3, r3, #1
|
|
8000f22: 61bb str r3, [r7, #24]
|
|
8000f24: 69bb ldr r3, [r7, #24]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8000f26: 2300 movs r3, #0
|
|
8000f28: 617b str r3, [r7, #20]
|
|
8000f2a: 4b65 ldr r3, [pc, #404] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f2c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f2e: 4a64 ldr r2, [pc, #400] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f30: f043 0302 orr.w r3, r3, #2
|
|
8000f34: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f36: 4b62 ldr r3, [pc, #392] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f38: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f3a: f003 0302 and.w r3, r3, #2
|
|
8000f3e: 617b str r3, [r7, #20]
|
|
8000f40: 697b ldr r3, [r7, #20]
|
|
__HAL_RCC_GPIOG_CLK_ENABLE();
|
|
8000f42: 2300 movs r3, #0
|
|
8000f44: 613b str r3, [r7, #16]
|
|
8000f46: 4b5e ldr r3, [pc, #376] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f48: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f4a: 4a5d ldr r2, [pc, #372] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f4c: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8000f50: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f52: 4b5b ldr r3, [pc, #364] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f54: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f56: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8000f5a: 613b str r3, [r7, #16]
|
|
8000f5c: 693b ldr r3, [r7, #16]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8000f5e: 2300 movs r3, #0
|
|
8000f60: 60fb str r3, [r7, #12]
|
|
8000f62: 4b57 ldr r3, [pc, #348] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f64: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f66: 4a56 ldr r2, [pc, #344] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f68: f043 0304 orr.w r3, r3, #4
|
|
8000f6c: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f6e: 4b54 ldr r3, [pc, #336] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f70: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f72: f003 0304 and.w r3, r3, #4
|
|
8000f76: 60fb str r3, [r7, #12]
|
|
8000f78: 68fb ldr r3, [r7, #12]
|
|
__HAL_RCC_GPIOD_CLK_ENABLE();
|
|
8000f7a: 2300 movs r3, #0
|
|
8000f7c: 60bb str r3, [r7, #8]
|
|
8000f7e: 4b50 ldr r3, [pc, #320] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f80: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f82: 4a4f ldr r2, [pc, #316] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f84: f043 0308 orr.w r3, r3, #8
|
|
8000f88: 6313 str r3, [r2, #48] @ 0x30
|
|
8000f8a: 4b4d ldr r3, [pc, #308] @ (80010c0 <HAL_LTDC_MspInit+0x244>)
|
|
8000f8c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8000f8e: f003 0308 and.w r3, r3, #8
|
|
8000f92: 60bb str r3, [r7, #8]
|
|
8000f94: 68bb ldr r3, [r7, #8]
|
|
PG11 ------> LTDC_B3
|
|
PG12 ------> LTDC_B4
|
|
PB8 ------> LTDC_B6
|
|
PB9 ------> LTDC_B7
|
|
*/
|
|
GPIO_InitStruct.Pin = ENABLE_Pin;
|
|
8000f96: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8000f9a: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000f9c: 2302 movs r3, #2
|
|
8000f9e: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000fa0: 2300 movs r3, #0
|
|
8000fa2: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000fa4: 2300 movs r3, #0
|
|
8000fa6: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8000fa8: 230e movs r3, #14
|
|
8000faa: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct);
|
|
8000fac: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8000fb0: 4619 mov r1, r3
|
|
8000fb2: 4844 ldr r0, [pc, #272] @ (80010c4 <HAL_LTDC_MspInit+0x248>)
|
|
8000fb4: f000 fe2c bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin
|
|
8000fb8: f641 0358 movw r3, #6232 @ 0x1858
|
|
8000fbc: 657b str r3, [r7, #84] @ 0x54
|
|
|R5_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000fbe: 2302 movs r3, #2
|
|
8000fc0: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000fc2: 2300 movs r3, #0
|
|
8000fc4: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000fc6: 2300 movs r3, #0
|
|
8000fc8: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8000fca: 230e movs r3, #14
|
|
8000fcc: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8000fce: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8000fd2: 4619 mov r1, r3
|
|
8000fd4: 483c ldr r0, [pc, #240] @ (80010c8 <HAL_LTDC_MspInit+0x24c>)
|
|
8000fd6: f000 fe1b bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = R3_Pin|R6_Pin;
|
|
8000fda: 2303 movs r3, #3
|
|
8000fdc: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8000fde: 2302 movs r3, #2
|
|
8000fe0: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8000fe2: 2300 movs r3, #0
|
|
8000fe4: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8000fe6: 2300 movs r3, #0
|
|
8000fe8: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
|
|
8000fea: 2309 movs r3, #9
|
|
8000fec: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8000fee: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8000ff2: 4619 mov r1, r3
|
|
8000ff4: 4835 ldr r0, [pc, #212] @ (80010cc <HAL_LTDC_MspInit+0x250>)
|
|
8000ff6: f000 fe0b bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin;
|
|
8000ffa: f44f 6370 mov.w r3, #3840 @ 0xf00
|
|
8000ffe: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001000: 2302 movs r3, #2
|
|
8001002: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001004: 2300 movs r3, #0
|
|
8001006: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001008: 2300 movs r3, #0
|
|
800100a: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800100c: 230e movs r3, #14
|
|
800100e: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001010: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001014: 4619 mov r1, r3
|
|
8001016: 482d ldr r0, [pc, #180] @ (80010cc <HAL_LTDC_MspInit+0x250>)
|
|
8001018: f000 fdfa bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin;
|
|
800101c: f44f 630c mov.w r3, #2240 @ 0x8c0
|
|
8001020: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001022: 2302 movs r3, #2
|
|
8001024: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001026: 2300 movs r3, #0
|
|
8001028: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800102a: 2300 movs r3, #0
|
|
800102c: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
800102e: 230e movs r3, #14
|
|
8001030: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8001032: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001036: 4619 mov r1, r3
|
|
8001038: 4825 ldr r0, [pc, #148] @ (80010d0 <HAL_LTDC_MspInit+0x254>)
|
|
800103a: f000 fde9 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin;
|
|
800103e: f44f 6398 mov.w r3, #1216 @ 0x4c0
|
|
8001042: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001044: 2302 movs r3, #2
|
|
8001046: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001048: 2300 movs r3, #0
|
|
800104a: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800104c: 2300 movs r3, #0
|
|
800104e: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8001050: 230e movs r3, #14
|
|
8001052: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
8001054: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001058: 4619 mov r1, r3
|
|
800105a: 481e ldr r0, [pc, #120] @ (80010d4 <HAL_LTDC_MspInit+0x258>)
|
|
800105c: f000 fdd8 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G7_Pin|B2_Pin;
|
|
8001060: 2348 movs r3, #72 @ 0x48
|
|
8001062: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001064: 2302 movs r3, #2
|
|
8001066: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001068: 2300 movs r3, #0
|
|
800106a: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800106c: 2300 movs r3, #0
|
|
800106e: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
|
|
8001070: 230e movs r3, #14
|
|
8001072: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8001074: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
8001078: 4619 mov r1, r3
|
|
800107a: 4817 ldr r0, [pc, #92] @ (80010d8 <HAL_LTDC_MspInit+0x25c>)
|
|
800107c: f000 fdc8 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = G3_Pin|B4_Pin;
|
|
8001080: f44f 53a0 mov.w r3, #5120 @ 0x1400
|
|
8001084: 657b str r3, [r7, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001086: 2302 movs r3, #2
|
|
8001088: 65bb str r3, [r7, #88] @ 0x58
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800108a: 2300 movs r3, #0
|
|
800108c: 65fb str r3, [r7, #92] @ 0x5c
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
800108e: 2300 movs r3, #0
|
|
8001090: 663b str r3, [r7, #96] @ 0x60
|
|
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
|
|
8001092: 2309 movs r3, #9
|
|
8001094: 667b str r3, [r7, #100] @ 0x64
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
8001096: f107 0354 add.w r3, r7, #84 @ 0x54
|
|
800109a: 4619 mov r1, r3
|
|
800109c: 480c ldr r0, [pc, #48] @ (80010d0 <HAL_LTDC_MspInit+0x254>)
|
|
800109e: f000 fdb7 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/* LTDC interrupt Init */
|
|
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
|
|
80010a2: 2200 movs r2, #0
|
|
80010a4: 2105 movs r1, #5
|
|
80010a6: 2058 movs r0, #88 @ 0x58
|
|
80010a8: f000 fb80 bl 80017ac <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(LTDC_IRQn);
|
|
80010ac: 2058 movs r0, #88 @ 0x58
|
|
80010ae: f000 fb99 bl 80017e4 <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END LTDC_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80010b2: bf00 nop
|
|
80010b4: 3768 adds r7, #104 @ 0x68
|
|
80010b6: 46bd mov sp, r7
|
|
80010b8: bd80 pop {r7, pc}
|
|
80010ba: bf00 nop
|
|
80010bc: 40016800 .word 0x40016800
|
|
80010c0: 40023800 .word 0x40023800
|
|
80010c4: 40021400 .word 0x40021400
|
|
80010c8: 40020000 .word 0x40020000
|
|
80010cc: 40020400 .word 0x40020400
|
|
80010d0: 40021800 .word 0x40021800
|
|
80010d4: 40020800 .word 0x40020800
|
|
80010d8: 40020c00 .word 0x40020c00
|
|
|
|
080010dc <HAL_SPI_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hspi: SPI handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
|
{
|
|
80010dc: b580 push {r7, lr}
|
|
80010de: b08a sub sp, #40 @ 0x28
|
|
80010e0: af00 add r7, sp, #0
|
|
80010e2: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80010e4: f107 0314 add.w r3, r7, #20
|
|
80010e8: 2200 movs r2, #0
|
|
80010ea: 601a str r2, [r3, #0]
|
|
80010ec: 605a str r2, [r3, #4]
|
|
80010ee: 609a str r2, [r3, #8]
|
|
80010f0: 60da str r2, [r3, #12]
|
|
80010f2: 611a str r2, [r3, #16]
|
|
if(hspi->Instance==SPI5)
|
|
80010f4: 687b ldr r3, [r7, #4]
|
|
80010f6: 681b ldr r3, [r3, #0]
|
|
80010f8: 4a19 ldr r2, [pc, #100] @ (8001160 <HAL_SPI_MspInit+0x84>)
|
|
80010fa: 4293 cmp r3, r2
|
|
80010fc: d12c bne.n 8001158 <HAL_SPI_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN SPI5_MspInit 0 */
|
|
|
|
/* USER CODE END SPI5_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_SPI5_CLK_ENABLE();
|
|
80010fe: 2300 movs r3, #0
|
|
8001100: 613b str r3, [r7, #16]
|
|
8001102: 4b18 ldr r3, [pc, #96] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
8001104: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001106: 4a17 ldr r2, [pc, #92] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
8001108: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
800110c: 6453 str r3, [r2, #68] @ 0x44
|
|
800110e: 4b15 ldr r3, [pc, #84] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
8001110: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001112: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001116: 613b str r3, [r7, #16]
|
|
8001118: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
800111a: 2300 movs r3, #0
|
|
800111c: 60fb str r3, [r7, #12]
|
|
800111e: 4b11 ldr r3, [pc, #68] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
8001120: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001122: 4a10 ldr r2, [pc, #64] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
8001124: f043 0320 orr.w r3, r3, #32
|
|
8001128: 6313 str r3, [r2, #48] @ 0x30
|
|
800112a: 4b0e ldr r3, [pc, #56] @ (8001164 <HAL_SPI_MspInit+0x88>)
|
|
800112c: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800112e: f003 0320 and.w r3, r3, #32
|
|
8001132: 60fb str r3, [r7, #12]
|
|
8001134: 68fb ldr r3, [r7, #12]
|
|
/**SPI5 GPIO Configuration
|
|
PF7 ------> SPI5_SCK
|
|
PF8 ------> SPI5_MISO
|
|
PF9 ------> SPI5_MOSI
|
|
*/
|
|
GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin;
|
|
8001136: f44f 7360 mov.w r3, #896 @ 0x380
|
|
800113a: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800113c: 2302 movs r3, #2
|
|
800113e: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001140: 2300 movs r3, #0
|
|
8001142: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001144: 2300 movs r3, #0
|
|
8001146: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
|
|
8001148: 2305 movs r3, #5
|
|
800114a: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
800114c: f107 0314 add.w r3, r7, #20
|
|
8001150: 4619 mov r1, r3
|
|
8001152: 4805 ldr r0, [pc, #20] @ (8001168 <HAL_SPI_MspInit+0x8c>)
|
|
8001154: f000 fd5c bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END SPI5_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8001158: bf00 nop
|
|
800115a: 3728 adds r7, #40 @ 0x28
|
|
800115c: 46bd mov sp, r7
|
|
800115e: bd80 pop {r7, pc}
|
|
8001160: 40015000 .word 0x40015000
|
|
8001164: 40023800 .word 0x40023800
|
|
8001168: 40021400 .word 0x40021400
|
|
|
|
0800116c <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
800116c: b480 push {r7}
|
|
800116e: b085 sub sp, #20
|
|
8001170: af00 add r7, sp, #0
|
|
8001172: 6078 str r0, [r7, #4]
|
|
if(htim_base->Instance==TIM1)
|
|
8001174: 687b ldr r3, [r7, #4]
|
|
8001176: 681b ldr r3, [r3, #0]
|
|
8001178: 4a0b ldr r2, [pc, #44] @ (80011a8 <HAL_TIM_Base_MspInit+0x3c>)
|
|
800117a: 4293 cmp r3, r2
|
|
800117c: d10d bne.n 800119a <HAL_TIM_Base_MspInit+0x2e>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
800117e: 2300 movs r3, #0
|
|
8001180: 60fb str r3, [r7, #12]
|
|
8001182: 4b0a ldr r3, [pc, #40] @ (80011ac <HAL_TIM_Base_MspInit+0x40>)
|
|
8001184: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001186: 4a09 ldr r2, [pc, #36] @ (80011ac <HAL_TIM_Base_MspInit+0x40>)
|
|
8001188: f043 0301 orr.w r3, r3, #1
|
|
800118c: 6453 str r3, [r2, #68] @ 0x44
|
|
800118e: 4b07 ldr r3, [pc, #28] @ (80011ac <HAL_TIM_Base_MspInit+0x40>)
|
|
8001190: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001192: f003 0301 and.w r3, r3, #1
|
|
8001196: 60fb str r3, [r7, #12]
|
|
8001198: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END TIM1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800119a: bf00 nop
|
|
800119c: 3714 adds r7, #20
|
|
800119e: 46bd mov sp, r7
|
|
80011a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80011a4: 4770 bx lr
|
|
80011a6: bf00 nop
|
|
80011a8: 40010000 .word 0x40010000
|
|
80011ac: 40023800 .word 0x40023800
|
|
|
|
080011b0 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
80011b0: b580 push {r7, lr}
|
|
80011b2: b08a sub sp, #40 @ 0x28
|
|
80011b4: af00 add r7, sp, #0
|
|
80011b6: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80011b8: f107 0314 add.w r3, r7, #20
|
|
80011bc: 2200 movs r2, #0
|
|
80011be: 601a str r2, [r3, #0]
|
|
80011c0: 605a str r2, [r3, #4]
|
|
80011c2: 609a str r2, [r3, #8]
|
|
80011c4: 60da str r2, [r3, #12]
|
|
80011c6: 611a str r2, [r3, #16]
|
|
if(huart->Instance==USART1)
|
|
80011c8: 687b ldr r3, [r7, #4]
|
|
80011ca: 681b ldr r3, [r3, #0]
|
|
80011cc: 4a19 ldr r2, [pc, #100] @ (8001234 <HAL_UART_MspInit+0x84>)
|
|
80011ce: 4293 cmp r3, r2
|
|
80011d0: d12c bne.n 800122c <HAL_UART_MspInit+0x7c>
|
|
{
|
|
/* USER CODE BEGIN USART1_MspInit 0 */
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
80011d2: 2300 movs r3, #0
|
|
80011d4: 613b str r3, [r7, #16]
|
|
80011d6: 4b18 ldr r3, [pc, #96] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
80011d8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80011da: 4a17 ldr r2, [pc, #92] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
80011dc: f043 0310 orr.w r3, r3, #16
|
|
80011e0: 6453 str r3, [r2, #68] @ 0x44
|
|
80011e2: 4b15 ldr r3, [pc, #84] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
80011e4: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80011e6: f003 0310 and.w r3, r3, #16
|
|
80011ea: 613b str r3, [r7, #16]
|
|
80011ec: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80011ee: 2300 movs r3, #0
|
|
80011f0: 60fb str r3, [r7, #12]
|
|
80011f2: 4b11 ldr r3, [pc, #68] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
80011f4: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
80011f6: 4a10 ldr r2, [pc, #64] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
80011f8: f043 0301 orr.w r3, r3, #1
|
|
80011fc: 6313 str r3, [r2, #48] @ 0x30
|
|
80011fe: 4b0e ldr r3, [pc, #56] @ (8001238 <HAL_UART_MspInit+0x88>)
|
|
8001200: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8001202: f003 0301 and.w r3, r3, #1
|
|
8001206: 60fb str r3, [r7, #12]
|
|
8001208: 68fb ldr r3, [r7, #12]
|
|
/**USART1 GPIO Configuration
|
|
PA9 ------> USART1_TX
|
|
PA10 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
|
|
800120a: f44f 63c0 mov.w r3, #1536 @ 0x600
|
|
800120e: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001210: 2302 movs r3, #2
|
|
8001212: 61bb str r3, [r7, #24]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001214: 2300 movs r3, #0
|
|
8001216: 61fb str r3, [r7, #28]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001218: 2303 movs r3, #3
|
|
800121a: 623b str r3, [r7, #32]
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
800121c: 2307 movs r3, #7
|
|
800121e: 627b str r3, [r7, #36] @ 0x24
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001220: f107 0314 add.w r3, r7, #20
|
|
8001224: 4619 mov r1, r3
|
|
8001226: 4805 ldr r0, [pc, #20] @ (800123c <HAL_UART_MspInit+0x8c>)
|
|
8001228: f000 fcf2 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
800122c: bf00 nop
|
|
800122e: 3728 adds r7, #40 @ 0x28
|
|
8001230: 46bd mov sp, r7
|
|
8001232: bd80 pop {r7, pc}
|
|
8001234: 40011000 .word 0x40011000
|
|
8001238: 40023800 .word 0x40023800
|
|
800123c: 40020000 .word 0x40020000
|
|
|
|
08001240 <HAL_FMC_MspInit>:
|
|
|
|
}
|
|
|
|
static uint32_t FMC_Initialized = 0;
|
|
|
|
static void HAL_FMC_MspInit(void){
|
|
8001240: b580 push {r7, lr}
|
|
8001242: b086 sub sp, #24
|
|
8001244: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN FMC_MspInit 0 */
|
|
|
|
/* USER CODE END FMC_MspInit 0 */
|
|
GPIO_InitTypeDef GPIO_InitStruct ={0};
|
|
8001246: 1d3b adds r3, r7, #4
|
|
8001248: 2200 movs r2, #0
|
|
800124a: 601a str r2, [r3, #0]
|
|
800124c: 605a str r2, [r3, #4]
|
|
800124e: 609a str r2, [r3, #8]
|
|
8001250: 60da str r2, [r3, #12]
|
|
8001252: 611a str r2, [r3, #16]
|
|
if (FMC_Initialized) {
|
|
8001254: 4b3b ldr r3, [pc, #236] @ (8001344 <HAL_FMC_MspInit+0x104>)
|
|
8001256: 681b ldr r3, [r3, #0]
|
|
8001258: 2b00 cmp r3, #0
|
|
800125a: d16f bne.n 800133c <HAL_FMC_MspInit+0xfc>
|
|
return;
|
|
}
|
|
FMC_Initialized = 1;
|
|
800125c: 4b39 ldr r3, [pc, #228] @ (8001344 <HAL_FMC_MspInit+0x104>)
|
|
800125e: 2201 movs r2, #1
|
|
8001260: 601a str r2, [r3, #0]
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_FMC_CLK_ENABLE();
|
|
8001262: 2300 movs r3, #0
|
|
8001264: 603b str r3, [r7, #0]
|
|
8001266: 4b38 ldr r3, [pc, #224] @ (8001348 <HAL_FMC_MspInit+0x108>)
|
|
8001268: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
800126a: 4a37 ldr r2, [pc, #220] @ (8001348 <HAL_FMC_MspInit+0x108>)
|
|
800126c: f043 0301 orr.w r3, r3, #1
|
|
8001270: 6393 str r3, [r2, #56] @ 0x38
|
|
8001272: 4b35 ldr r3, [pc, #212] @ (8001348 <HAL_FMC_MspInit+0x108>)
|
|
8001274: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8001276: f003 0301 and.w r3, r3, #1
|
|
800127a: 603b str r3, [r7, #0]
|
|
800127c: 683b ldr r3, [r7, #0]
|
|
PB5 ------> FMC_SDCKE1
|
|
PB6 ------> FMC_SDNE1
|
|
PE0 ------> FMC_NBL0
|
|
PE1 ------> FMC_NBL1
|
|
*/
|
|
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
|
|
800127e: f64f 033f movw r3, #63551 @ 0xf83f
|
|
8001282: 607b str r3, [r7, #4]
|
|
|A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin
|
|
|A7_Pin|A8_Pin|A9_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001284: 2302 movs r3, #2
|
|
8001286: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001288: 2300 movs r3, #0
|
|
800128a: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800128c: 2303 movs r3, #3
|
|
800128e: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
8001290: 230c movs r3, #12
|
|
8001292: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
|
8001294: 1d3b adds r3, r7, #4
|
|
8001296: 4619 mov r1, r3
|
|
8001298: 482c ldr r0, [pc, #176] @ (800134c <HAL_FMC_MspInit+0x10c>)
|
|
800129a: f000 fcb9 bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = SDNWE_Pin;
|
|
800129e: 2301 movs r3, #1
|
|
80012a0: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012a2: 2302 movs r3, #2
|
|
80012a4: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012a6: 2300 movs r3, #0
|
|
80012a8: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012aa: 2303 movs r3, #3
|
|
80012ac: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
80012ae: 230c movs r3, #12
|
|
80012b0: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
|
|
80012b2: 1d3b adds r3, r7, #4
|
|
80012b4: 4619 mov r1, r3
|
|
80012b6: 4826 ldr r0, [pc, #152] @ (8001350 <HAL_FMC_MspInit+0x110>)
|
|
80012b8: f000 fcaa bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin
|
|
80012bc: f248 1333 movw r3, #33075 @ 0x8133
|
|
80012c0: 607b str r3, [r7, #4]
|
|
|SDCLK_Pin|SDNCAS_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012c2: 2302 movs r3, #2
|
|
80012c4: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012c6: 2300 movs r3, #0
|
|
80012c8: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012ca: 2303 movs r3, #3
|
|
80012cc: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
80012ce: 230c movs r3, #12
|
|
80012d0: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
|
80012d2: 1d3b adds r3, r7, #4
|
|
80012d4: 4619 mov r1, r3
|
|
80012d6: 481f ldr r0, [pc, #124] @ (8001354 <HAL_FMC_MspInit+0x114>)
|
|
80012d8: f000 fc9a bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin
|
|
80012dc: f64f 7383 movw r3, #65411 @ 0xff83
|
|
80012e0: 607b str r3, [r7, #4]
|
|
|D8_Pin|D9_Pin|D10_Pin|D11_Pin
|
|
|D12_Pin|NBL0_Pin|NBL1_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80012e2: 2302 movs r3, #2
|
|
80012e4: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80012e6: 2300 movs r3, #0
|
|
80012e8: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80012ea: 2303 movs r3, #3
|
|
80012ec: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
80012ee: 230c movs r3, #12
|
|
80012f0: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
|
80012f2: 1d3b adds r3, r7, #4
|
|
80012f4: 4619 mov r1, r3
|
|
80012f6: 4818 ldr r0, [pc, #96] @ (8001358 <HAL_FMC_MspInit+0x118>)
|
|
80012f8: f000 fc8a bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin
|
|
80012fc: f24c 7303 movw r3, #50947 @ 0xc703
|
|
8001300: 607b str r3, [r7, #4]
|
|
|D1_Pin|D2_Pin|D3_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001302: 2302 movs r3, #2
|
|
8001304: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001306: 2300 movs r3, #0
|
|
8001308: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
800130a: 2303 movs r3, #3
|
|
800130c: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
800130e: 230c movs r3, #12
|
|
8001310: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
|
8001312: 1d3b adds r3, r7, #4
|
|
8001314: 4619 mov r1, r3
|
|
8001316: 4811 ldr r0, [pc, #68] @ (800135c <HAL_FMC_MspInit+0x11c>)
|
|
8001318: f000 fc7a bl 8001c10 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin;
|
|
800131c: 2360 movs r3, #96 @ 0x60
|
|
800131e: 607b str r3, [r7, #4]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8001320: 2302 movs r3, #2
|
|
8001322: 60bb str r3, [r7, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001324: 2300 movs r3, #0
|
|
8001326: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8001328: 2303 movs r3, #3
|
|
800132a: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
|
800132c: 230c movs r3, #12
|
|
800132e: 617b str r3, [r7, #20]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001330: 1d3b adds r3, r7, #4
|
|
8001332: 4619 mov r1, r3
|
|
8001334: 480a ldr r0, [pc, #40] @ (8001360 <HAL_FMC_MspInit+0x120>)
|
|
8001336: f000 fc6b bl 8001c10 <HAL_GPIO_Init>
|
|
800133a: e000 b.n 800133e <HAL_FMC_MspInit+0xfe>
|
|
return;
|
|
800133c: bf00 nop
|
|
|
|
/* USER CODE BEGIN FMC_MspInit 1 */
|
|
|
|
/* USER CODE END FMC_MspInit 1 */
|
|
}
|
|
800133e: 3718 adds r7, #24
|
|
8001340: 46bd mov sp, r7
|
|
8001342: bd80 pop {r7, pc}
|
|
8001344: 2000028c .word 0x2000028c
|
|
8001348: 40023800 .word 0x40023800
|
|
800134c: 40021400 .word 0x40021400
|
|
8001350: 40020800 .word 0x40020800
|
|
8001354: 40021800 .word 0x40021800
|
|
8001358: 40021000 .word 0x40021000
|
|
800135c: 40020c00 .word 0x40020c00
|
|
8001360: 40020400 .word 0x40020400
|
|
|
|
08001364 <HAL_SDRAM_MspInit>:
|
|
|
|
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
|
|
8001364: b580 push {r7, lr}
|
|
8001366: b082 sub sp, #8
|
|
8001368: af00 add r7, sp, #0
|
|
800136a: 6078 str r0, [r7, #4]
|
|
/* USER CODE BEGIN SDRAM_MspInit 0 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 0 */
|
|
HAL_FMC_MspInit();
|
|
800136c: f7ff ff68 bl 8001240 <HAL_FMC_MspInit>
|
|
/* USER CODE BEGIN SDRAM_MspInit 1 */
|
|
|
|
/* USER CODE END SDRAM_MspInit 1 */
|
|
}
|
|
8001370: bf00 nop
|
|
8001372: 3708 adds r7, #8
|
|
8001374: 46bd mov sp, r7
|
|
8001376: bd80 pop {r7, pc}
|
|
|
|
08001378 <HAL_InitTick>:
|
|
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
|
|
* @param TickPriority: Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8001378: b580 push {r7, lr}
|
|
800137a: b08e sub sp, #56 @ 0x38
|
|
800137c: af00 add r7, sp, #0
|
|
800137e: 6078 str r0, [r7, #4]
|
|
RCC_ClkInitTypeDef clkconfig;
|
|
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
|
|
8001380: 2300 movs r3, #0
|
|
8001382: 62fb str r3, [r7, #44] @ 0x2c
|
|
|
|
uint32_t uwPrescalerValue = 0U;
|
|
8001384: 2300 movs r3, #0
|
|
8001386: 62bb str r3, [r7, #40] @ 0x28
|
|
uint32_t pFLatency;
|
|
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Enable TIM6 clock */
|
|
__HAL_RCC_TIM6_CLK_ENABLE();
|
|
8001388: 2300 movs r3, #0
|
|
800138a: 60fb str r3, [r7, #12]
|
|
800138c: 4b33 ldr r3, [pc, #204] @ (800145c <HAL_InitTick+0xe4>)
|
|
800138e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8001390: 4a32 ldr r2, [pc, #200] @ (800145c <HAL_InitTick+0xe4>)
|
|
8001392: f043 0310 orr.w r3, r3, #16
|
|
8001396: 6413 str r3, [r2, #64] @ 0x40
|
|
8001398: 4b30 ldr r3, [pc, #192] @ (800145c <HAL_InitTick+0xe4>)
|
|
800139a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800139c: f003 0310 and.w r3, r3, #16
|
|
80013a0: 60fb str r3, [r7, #12]
|
|
80013a2: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Get clock configuration */
|
|
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
|
|
80013a4: f107 0210 add.w r2, r7, #16
|
|
80013a8: f107 0314 add.w r3, r7, #20
|
|
80013ac: 4611 mov r1, r2
|
|
80013ae: 4618 mov r0, r3
|
|
80013b0: f003 fd1c bl 8004dec <HAL_RCC_GetClockConfig>
|
|
|
|
/* Get APB1 prescaler */
|
|
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
|
|
80013b4: 6a3b ldr r3, [r7, #32]
|
|
80013b6: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Compute TIM6 clock */
|
|
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
|
|
80013b8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
80013ba: 2b00 cmp r3, #0
|
|
80013bc: d103 bne.n 80013c6 <HAL_InitTick+0x4e>
|
|
{
|
|
uwTimclock = HAL_RCC_GetPCLK1Freq();
|
|
80013be: f003 fced bl 8004d9c <HAL_RCC_GetPCLK1Freq>
|
|
80013c2: 6378 str r0, [r7, #52] @ 0x34
|
|
80013c4: e004 b.n 80013d0 <HAL_InitTick+0x58>
|
|
}
|
|
else
|
|
{
|
|
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
|
|
80013c6: f003 fce9 bl 8004d9c <HAL_RCC_GetPCLK1Freq>
|
|
80013ca: 4603 mov r3, r0
|
|
80013cc: 005b lsls r3, r3, #1
|
|
80013ce: 637b str r3, [r7, #52] @ 0x34
|
|
}
|
|
|
|
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
|
|
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
|
|
80013d0: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80013d2: 4a23 ldr r2, [pc, #140] @ (8001460 <HAL_InitTick+0xe8>)
|
|
80013d4: fba2 2303 umull r2, r3, r2, r3
|
|
80013d8: 0c9b lsrs r3, r3, #18
|
|
80013da: 3b01 subs r3, #1
|
|
80013dc: 62bb str r3, [r7, #40] @ 0x28
|
|
|
|
/* Initialize TIM6 */
|
|
htim6.Instance = TIM6;
|
|
80013de: 4b21 ldr r3, [pc, #132] @ (8001464 <HAL_InitTick+0xec>)
|
|
80013e0: 4a21 ldr r2, [pc, #132] @ (8001468 <HAL_InitTick+0xf0>)
|
|
80013e2: 601a str r2, [r3, #0]
|
|
* Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
|
|
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
|
|
* ClockDivision = 0
|
|
* Counter direction = Up
|
|
*/
|
|
htim6.Init.Period = (1000000U / 1000U) - 1U;
|
|
80013e4: 4b1f ldr r3, [pc, #124] @ (8001464 <HAL_InitTick+0xec>)
|
|
80013e6: f240 32e7 movw r2, #999 @ 0x3e7
|
|
80013ea: 60da str r2, [r3, #12]
|
|
htim6.Init.Prescaler = uwPrescalerValue;
|
|
80013ec: 4a1d ldr r2, [pc, #116] @ (8001464 <HAL_InitTick+0xec>)
|
|
80013ee: 6abb ldr r3, [r7, #40] @ 0x28
|
|
80013f0: 6053 str r3, [r2, #4]
|
|
htim6.Init.ClockDivision = 0;
|
|
80013f2: 4b1c ldr r3, [pc, #112] @ (8001464 <HAL_InitTick+0xec>)
|
|
80013f4: 2200 movs r2, #0
|
|
80013f6: 611a str r2, [r3, #16]
|
|
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
80013f8: 4b1a ldr r3, [pc, #104] @ (8001464 <HAL_InitTick+0xec>)
|
|
80013fa: 2200 movs r2, #0
|
|
80013fc: 609a str r2, [r3, #8]
|
|
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
80013fe: 4b19 ldr r3, [pc, #100] @ (8001464 <HAL_InitTick+0xec>)
|
|
8001400: 2200 movs r2, #0
|
|
8001402: 619a str r2, [r3, #24]
|
|
|
|
status = HAL_TIM_Base_Init(&htim6);
|
|
8001404: 4817 ldr r0, [pc, #92] @ (8001464 <HAL_InitTick+0xec>)
|
|
8001406: f003 ffa0 bl 800534a <HAL_TIM_Base_Init>
|
|
800140a: 4603 mov r3, r0
|
|
800140c: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
if (status == HAL_OK)
|
|
8001410: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
8001414: 2b00 cmp r3, #0
|
|
8001416: d11b bne.n 8001450 <HAL_InitTick+0xd8>
|
|
{
|
|
/* Start the TIM time Base generation in interrupt mode */
|
|
status = HAL_TIM_Base_Start_IT(&htim6);
|
|
8001418: 4812 ldr r0, [pc, #72] @ (8001464 <HAL_InitTick+0xec>)
|
|
800141a: f003 ffe5 bl 80053e8 <HAL_TIM_Base_Start_IT>
|
|
800141e: 4603 mov r3, r0
|
|
8001420: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
if (status == HAL_OK)
|
|
8001424: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
8001428: 2b00 cmp r3, #0
|
|
800142a: d111 bne.n 8001450 <HAL_InitTick+0xd8>
|
|
{
|
|
/* Enable the TIM6 global Interrupt */
|
|
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
|
|
800142c: 2036 movs r0, #54 @ 0x36
|
|
800142e: f000 f9d9 bl 80017e4 <HAL_NVIC_EnableIRQ>
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
8001432: 687b ldr r3, [r7, #4]
|
|
8001434: 2b0f cmp r3, #15
|
|
8001436: d808 bhi.n 800144a <HAL_InitTick+0xd2>
|
|
{
|
|
/* Configure the TIM IRQ priority */
|
|
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
|
|
8001438: 2200 movs r2, #0
|
|
800143a: 6879 ldr r1, [r7, #4]
|
|
800143c: 2036 movs r0, #54 @ 0x36
|
|
800143e: f000 f9b5 bl 80017ac <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8001442: 4a0a ldr r2, [pc, #40] @ (800146c <HAL_InitTick+0xf4>)
|
|
8001444: 687b ldr r3, [r7, #4]
|
|
8001446: 6013 str r3, [r2, #0]
|
|
8001448: e002 b.n 8001450 <HAL_InitTick+0xd8>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800144a: 2301 movs r3, #1
|
|
800144c: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
8001450: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
}
|
|
8001454: 4618 mov r0, r3
|
|
8001456: 3738 adds r7, #56 @ 0x38
|
|
8001458: 46bd mov sp, r7
|
|
800145a: bd80 pop {r7, pc}
|
|
800145c: 40023800 .word 0x40023800
|
|
8001460: 431bde83 .word 0x431bde83
|
|
8001464: 20000290 .word 0x20000290
|
|
8001468: 40001000 .word 0x40001000
|
|
800146c: 20000004 .word 0x20000004
|
|
|
|
08001470 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8001470: b480 push {r7}
|
|
8001472: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8001474: bf00 nop
|
|
8001476: e7fd b.n 8001474 <NMI_Handler+0x4>
|
|
|
|
08001478 <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
8001478: b480 push {r7}
|
|
800147a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
800147c: bf00 nop
|
|
800147e: e7fd b.n 800147c <HardFault_Handler+0x4>
|
|
|
|
08001480 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8001480: b480 push {r7}
|
|
8001482: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8001484: bf00 nop
|
|
8001486: e7fd b.n 8001484 <MemManage_Handler+0x4>
|
|
|
|
08001488 <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pre-fetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
8001488: b480 push {r7}
|
|
800148a: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
800148c: bf00 nop
|
|
800148e: e7fd b.n 800148c <BusFault_Handler+0x4>
|
|
|
|
08001490 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8001490: b480 push {r7}
|
|
8001492: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8001494: bf00 nop
|
|
8001496: e7fd b.n 8001494 <UsageFault_Handler+0x4>
|
|
|
|
08001498 <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
8001498: b480 push {r7}
|
|
800149a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800149c: bf00 nop
|
|
800149e: 46bd mov sp, r7
|
|
80014a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80014a4: 4770 bx lr
|
|
...
|
|
|
|
080014a8 <TIM6_DAC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
|
|
*/
|
|
void TIM6_DAC_IRQHandler(void)
|
|
{
|
|
80014a8: b580 push {r7, lr}
|
|
80014aa: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim6);
|
|
80014ac: 4802 ldr r0, [pc, #8] @ (80014b8 <TIM6_DAC_IRQHandler+0x10>)
|
|
80014ae: f004 f80b bl 80054c8 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
|
|
|
|
/* USER CODE END TIM6_DAC_IRQn 1 */
|
|
}
|
|
80014b2: bf00 nop
|
|
80014b4: bd80 pop {r7, pc}
|
|
80014b6: bf00 nop
|
|
80014b8: 20000290 .word 0x20000290
|
|
|
|
080014bc <OTG_HS_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USB On The Go HS global interrupt.
|
|
*/
|
|
void OTG_HS_IRQHandler(void)
|
|
{
|
|
80014bc: b580 push {r7, lr}
|
|
80014be: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN OTG_HS_IRQn 0 */
|
|
|
|
/* USER CODE END OTG_HS_IRQn 0 */
|
|
HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS);
|
|
80014c0: 4802 ldr r0, [pc, #8] @ (80014cc <OTG_HS_IRQHandler+0x10>)
|
|
80014c2: f000 fd84 bl 8001fce <HAL_HCD_IRQHandler>
|
|
/* USER CODE BEGIN OTG_HS_IRQn 1 */
|
|
|
|
/* USER CODE END OTG_HS_IRQn 1 */
|
|
}
|
|
80014c6: bf00 nop
|
|
80014c8: bd80 pop {r7, pc}
|
|
80014ca: bf00 nop
|
|
80014cc: 200003c8 .word 0x200003c8
|
|
|
|
080014d0 <LTDC_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles LTDC global interrupt.
|
|
*/
|
|
void LTDC_IRQHandler(void)
|
|
{
|
|
80014d0: b580 push {r7, lr}
|
|
80014d2: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN LTDC_IRQn 0 */
|
|
|
|
/* USER CODE END LTDC_IRQn 0 */
|
|
HAL_LTDC_IRQHandler(&hltdc);
|
|
80014d4: 4802 ldr r0, [pc, #8] @ (80014e0 <LTDC_IRQHandler+0x10>)
|
|
80014d6: f002 fd7d bl 8003fd4 <HAL_LTDC_IRQHandler>
|
|
/* USER CODE BEGIN LTDC_IRQn 1 */
|
|
|
|
/* USER CODE END LTDC_IRQn 1 */
|
|
}
|
|
80014da: bf00 nop
|
|
80014dc: bd80 pop {r7, pc}
|
|
80014de: bf00 nop
|
|
80014e0: 200000c8 .word 0x200000c8
|
|
|
|
080014e4 <DMA2D_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA2D global interrupt.
|
|
*/
|
|
void DMA2D_IRQHandler(void)
|
|
{
|
|
80014e4: b580 push {r7, lr}
|
|
80014e6: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN DMA2D_IRQn 0 */
|
|
|
|
/* USER CODE END DMA2D_IRQn 0 */
|
|
HAL_DMA2D_IRQHandler(&hdma2d);
|
|
80014e8: 4802 ldr r0, [pc, #8] @ (80014f4 <DMA2D_IRQHandler+0x10>)
|
|
80014ea: f000 f9ee bl 80018ca <HAL_DMA2D_IRQHandler>
|
|
/* USER CODE BEGIN DMA2D_IRQn 1 */
|
|
|
|
/* USER CODE END DMA2D_IRQn 1 */
|
|
}
|
|
80014ee: bf00 nop
|
|
80014f0: bd80 pop {r7, pc}
|
|
80014f2: bf00 nop
|
|
80014f4: 20000034 .word 0x20000034
|
|
|
|
080014f8 <SystemInit>:
|
|
* configuration.
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
void SystemInit(void)
|
|
{
|
|
80014f8: b480 push {r7}
|
|
80014fa: af00 add r7, sp, #0
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
|
80014fc: 4b06 ldr r3, [pc, #24] @ (8001518 <SystemInit+0x20>)
|
|
80014fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8001502: 4a05 ldr r2, [pc, #20] @ (8001518 <SystemInit+0x20>)
|
|
8001504: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8001508: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
|
|
/* Configure the Vector Table location -------------------------------------*/
|
|
#if defined(USER_VECT_TAB_ADDRESS)
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#endif /* USER_VECT_TAB_ADDRESS */
|
|
}
|
|
800150c: bf00 nop
|
|
800150e: 46bd mov sp, r7
|
|
8001510: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001514: 4770 bx lr
|
|
8001516: bf00 nop
|
|
8001518: e000ed00 .word 0xe000ed00
|
|
|
|
0800151c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* set stack pointer */
|
|
800151c: f8df d034 ldr.w sp, [pc, #52] @ 8001554 <LoopFillZerobss+0xe>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8001520: f7ff ffea bl 80014f8 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8001524: 480c ldr r0, [pc, #48] @ (8001558 <LoopFillZerobss+0x12>)
|
|
ldr r1, =_edata
|
|
8001526: 490d ldr r1, [pc, #52] @ (800155c <LoopFillZerobss+0x16>)
|
|
ldr r2, =_sidata
|
|
8001528: 4a0d ldr r2, [pc, #52] @ (8001560 <LoopFillZerobss+0x1a>)
|
|
movs r3, #0
|
|
800152a: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
800152c: e002 b.n 8001534 <LoopCopyDataInit>
|
|
|
|
0800152e <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800152e: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
8001530: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
8001532: 3304 adds r3, #4
|
|
|
|
08001534 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8001534: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8001536: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8001538: d3f9 bcc.n 800152e <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
800153a: 4a0a ldr r2, [pc, #40] @ (8001564 <LoopFillZerobss+0x1e>)
|
|
ldr r4, =_ebss
|
|
800153c: 4c0a ldr r4, [pc, #40] @ (8001568 <LoopFillZerobss+0x22>)
|
|
movs r3, #0
|
|
800153e: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
8001540: e001 b.n 8001546 <LoopFillZerobss>
|
|
|
|
08001542 <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
8001542: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8001544: 3204 adds r2, #4
|
|
|
|
08001546 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8001546: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8001548: d3fb bcc.n 8001542 <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800154a: f006 fc71 bl 8007e30 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800154e: f7fe fff1 bl 8000534 <main>
|
|
bx lr
|
|
8001552: 4770 bx lr
|
|
ldr sp, =_estack /* set stack pointer */
|
|
8001554: 20030000 .word 0x20030000
|
|
ldr r0, =_sdata
|
|
8001558: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
800155c: 20000010 .word 0x20000010
|
|
ldr r2, =_sidata
|
|
8001560: 08007ed4 .word 0x08007ed4
|
|
ldr r2, =_sbss
|
|
8001564: 20000010 .word 0x20000010
|
|
ldr r4, =_ebss
|
|
8001568: 200007a8 .word 0x200007a8
|
|
|
|
0800156c <ADC_IRQHandler>:
|
|
* @retval None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800156c: e7fe b.n 800156c <ADC_IRQHandler>
|
|
...
|
|
|
|
08001570 <HAL_Init>:
|
|
* need to ensure that the SysTick time base is always set to 1 millisecond
|
|
* to have correct HAL operation.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
8001570: b580 push {r7, lr}
|
|
8001572: af00 add r7, sp, #0
|
|
/* Configure Flash prefetch, Instruction cache, Data cache */
|
|
#if (INSTRUCTION_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
|
|
8001574: 4b0e ldr r3, [pc, #56] @ (80015b0 <HAL_Init+0x40>)
|
|
8001576: 681b ldr r3, [r3, #0]
|
|
8001578: 4a0d ldr r2, [pc, #52] @ (80015b0 <HAL_Init+0x40>)
|
|
800157a: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
800157e: 6013 str r3, [r2, #0]
|
|
#endif /* INSTRUCTION_CACHE_ENABLE */
|
|
|
|
#if (DATA_CACHE_ENABLE != 0U)
|
|
__HAL_FLASH_DATA_CACHE_ENABLE();
|
|
8001580: 4b0b ldr r3, [pc, #44] @ (80015b0 <HAL_Init+0x40>)
|
|
8001582: 681b ldr r3, [r3, #0]
|
|
8001584: 4a0a ldr r2, [pc, #40] @ (80015b0 <HAL_Init+0x40>)
|
|
8001586: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
800158a: 6013 str r3, [r2, #0]
|
|
#endif /* DATA_CACHE_ENABLE */
|
|
|
|
#if (PREFETCH_ENABLE != 0U)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
800158c: 4b08 ldr r3, [pc, #32] @ (80015b0 <HAL_Init+0x40>)
|
|
800158e: 681b ldr r3, [r3, #0]
|
|
8001590: 4a07 ldr r2, [pc, #28] @ (80015b0 <HAL_Init+0x40>)
|
|
8001592: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8001596: 6013 str r3, [r2, #0]
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8001598: 2003 movs r0, #3
|
|
800159a: f000 f8fc bl 8001796 <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
|
HAL_InitTick(TICK_INT_PRIORITY);
|
|
800159e: 2000 movs r0, #0
|
|
80015a0: f7ff feea bl 8001378 <HAL_InitTick>
|
|
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80015a4: f7ff fb8a bl 8000cbc <HAL_MspInit>
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
80015a8: 2300 movs r3, #0
|
|
}
|
|
80015aa: 4618 mov r0, r3
|
|
80015ac: bd80 pop {r7, pc}
|
|
80015ae: bf00 nop
|
|
80015b0: 40023c00 .word 0x40023c00
|
|
|
|
080015b4 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
80015b4: b480 push {r7}
|
|
80015b6: af00 add r7, sp, #0
|
|
uwTick += uwTickFreq;
|
|
80015b8: 4b06 ldr r3, [pc, #24] @ (80015d4 <HAL_IncTick+0x20>)
|
|
80015ba: 781b ldrb r3, [r3, #0]
|
|
80015bc: 461a mov r2, r3
|
|
80015be: 4b06 ldr r3, [pc, #24] @ (80015d8 <HAL_IncTick+0x24>)
|
|
80015c0: 681b ldr r3, [r3, #0]
|
|
80015c2: 4413 add r3, r2
|
|
80015c4: 4a04 ldr r2, [pc, #16] @ (80015d8 <HAL_IncTick+0x24>)
|
|
80015c6: 6013 str r3, [r2, #0]
|
|
}
|
|
80015c8: bf00 nop
|
|
80015ca: 46bd mov sp, r7
|
|
80015cc: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015d0: 4770 bx lr
|
|
80015d2: bf00 nop
|
|
80015d4: 20000008 .word 0x20000008
|
|
80015d8: 200002d8 .word 0x200002d8
|
|
|
|
080015dc <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
80015dc: b480 push {r7}
|
|
80015de: af00 add r7, sp, #0
|
|
return uwTick;
|
|
80015e0: 4b03 ldr r3, [pc, #12] @ (80015f0 <HAL_GetTick+0x14>)
|
|
80015e2: 681b ldr r3, [r3, #0]
|
|
}
|
|
80015e4: 4618 mov r0, r3
|
|
80015e6: 46bd mov sp, r7
|
|
80015e8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80015ec: 4770 bx lr
|
|
80015ee: bf00 nop
|
|
80015f0: 200002d8 .word 0x200002d8
|
|
|
|
080015f4 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
80015f4: b580 push {r7, lr}
|
|
80015f6: b084 sub sp, #16
|
|
80015f8: af00 add r7, sp, #0
|
|
80015fa: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
80015fc: f7ff ffee bl 80015dc <HAL_GetTick>
|
|
8001600: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8001602: 687b ldr r3, [r7, #4]
|
|
8001604: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8001606: 68fb ldr r3, [r7, #12]
|
|
8001608: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800160c: d005 beq.n 800161a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800160e: 4b0a ldr r3, [pc, #40] @ (8001638 <HAL_Delay+0x44>)
|
|
8001610: 781b ldrb r3, [r3, #0]
|
|
8001612: 461a mov r2, r3
|
|
8001614: 68fb ldr r3, [r7, #12]
|
|
8001616: 4413 add r3, r2
|
|
8001618: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while((HAL_GetTick() - tickstart) < wait)
|
|
800161a: bf00 nop
|
|
800161c: f7ff ffde bl 80015dc <HAL_GetTick>
|
|
8001620: 4602 mov r2, r0
|
|
8001622: 68bb ldr r3, [r7, #8]
|
|
8001624: 1ad3 subs r3, r2, r3
|
|
8001626: 68fa ldr r2, [r7, #12]
|
|
8001628: 429a cmp r2, r3
|
|
800162a: d8f7 bhi.n 800161c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
800162c: bf00 nop
|
|
800162e: bf00 nop
|
|
8001630: 3710 adds r7, #16
|
|
8001632: 46bd mov sp, r7
|
|
8001634: bd80 pop {r7, pc}
|
|
8001636: bf00 nop
|
|
8001638: 20000008 .word 0x20000008
|
|
|
|
0800163c <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800163c: b480 push {r7}
|
|
800163e: b085 sub sp, #20
|
|
8001640: af00 add r7, sp, #0
|
|
8001642: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
8001644: 687b ldr r3, [r7, #4]
|
|
8001646: f003 0307 and.w r3, r3, #7
|
|
800164a: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
800164c: 4b0c ldr r3, [pc, #48] @ (8001680 <__NVIC_SetPriorityGrouping+0x44>)
|
|
800164e: 68db ldr r3, [r3, #12]
|
|
8001650: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
8001652: 68ba ldr r2, [r7, #8]
|
|
8001654: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
8001658: 4013 ands r3, r2
|
|
800165a: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
800165c: 68fb ldr r3, [r7, #12]
|
|
800165e: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8001660: 68bb ldr r3, [r7, #8]
|
|
8001662: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
8001664: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
8001668: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
800166c: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
800166e: 4a04 ldr r2, [pc, #16] @ (8001680 <__NVIC_SetPriorityGrouping+0x44>)
|
|
8001670: 68bb ldr r3, [r7, #8]
|
|
8001672: 60d3 str r3, [r2, #12]
|
|
}
|
|
8001674: bf00 nop
|
|
8001676: 3714 adds r7, #20
|
|
8001678: 46bd mov sp, r7
|
|
800167a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800167e: 4770 bx lr
|
|
8001680: e000ed00 .word 0xe000ed00
|
|
|
|
08001684 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8001684: b480 push {r7}
|
|
8001686: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8001688: 4b04 ldr r3, [pc, #16] @ (800169c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800168a: 68db ldr r3, [r3, #12]
|
|
800168c: 0a1b lsrs r3, r3, #8
|
|
800168e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8001692: 4618 mov r0, r3
|
|
8001694: 46bd mov sp, r7
|
|
8001696: f85d 7b04 ldr.w r7, [sp], #4
|
|
800169a: 4770 bx lr
|
|
800169c: e000ed00 .word 0xe000ed00
|
|
|
|
080016a0 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80016a0: b480 push {r7}
|
|
80016a2: b083 sub sp, #12
|
|
80016a4: af00 add r7, sp, #0
|
|
80016a6: 4603 mov r3, r0
|
|
80016a8: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80016aa: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80016ae: 2b00 cmp r3, #0
|
|
80016b0: db0b blt.n 80016ca <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
80016b2: 79fb ldrb r3, [r7, #7]
|
|
80016b4: f003 021f and.w r2, r3, #31
|
|
80016b8: 4907 ldr r1, [pc, #28] @ (80016d8 <__NVIC_EnableIRQ+0x38>)
|
|
80016ba: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80016be: 095b lsrs r3, r3, #5
|
|
80016c0: 2001 movs r0, #1
|
|
80016c2: fa00 f202 lsl.w r2, r0, r2
|
|
80016c6: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
80016ca: bf00 nop
|
|
80016cc: 370c adds r7, #12
|
|
80016ce: 46bd mov sp, r7
|
|
80016d0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80016d4: 4770 bx lr
|
|
80016d6: bf00 nop
|
|
80016d8: e000e100 .word 0xe000e100
|
|
|
|
080016dc <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
80016dc: b480 push {r7}
|
|
80016de: b083 sub sp, #12
|
|
80016e0: af00 add r7, sp, #0
|
|
80016e2: 4603 mov r3, r0
|
|
80016e4: 6039 str r1, [r7, #0]
|
|
80016e6: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
80016e8: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80016ec: 2b00 cmp r3, #0
|
|
80016ee: db0a blt.n 8001706 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
80016f0: 683b ldr r3, [r7, #0]
|
|
80016f2: b2da uxtb r2, r3
|
|
80016f4: 490c ldr r1, [pc, #48] @ (8001728 <__NVIC_SetPriority+0x4c>)
|
|
80016f6: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80016fa: 0112 lsls r2, r2, #4
|
|
80016fc: b2d2 uxtb r2, r2
|
|
80016fe: 440b add r3, r1
|
|
8001700: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8001704: e00a b.n 800171c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8001706: 683b ldr r3, [r7, #0]
|
|
8001708: b2da uxtb r2, r3
|
|
800170a: 4908 ldr r1, [pc, #32] @ (800172c <__NVIC_SetPriority+0x50>)
|
|
800170c: 79fb ldrb r3, [r7, #7]
|
|
800170e: f003 030f and.w r3, r3, #15
|
|
8001712: 3b04 subs r3, #4
|
|
8001714: 0112 lsls r2, r2, #4
|
|
8001716: b2d2 uxtb r2, r2
|
|
8001718: 440b add r3, r1
|
|
800171a: 761a strb r2, [r3, #24]
|
|
}
|
|
800171c: bf00 nop
|
|
800171e: 370c adds r7, #12
|
|
8001720: 46bd mov sp, r7
|
|
8001722: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001726: 4770 bx lr
|
|
8001728: e000e100 .word 0xe000e100
|
|
800172c: e000ed00 .word 0xe000ed00
|
|
|
|
08001730 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8001730: b480 push {r7}
|
|
8001732: b089 sub sp, #36 @ 0x24
|
|
8001734: af00 add r7, sp, #0
|
|
8001736: 60f8 str r0, [r7, #12]
|
|
8001738: 60b9 str r1, [r7, #8]
|
|
800173a: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
800173c: 68fb ldr r3, [r7, #12]
|
|
800173e: f003 0307 and.w r3, r3, #7
|
|
8001742: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
8001744: 69fb ldr r3, [r7, #28]
|
|
8001746: f1c3 0307 rsb r3, r3, #7
|
|
800174a: 2b04 cmp r3, #4
|
|
800174c: bf28 it cs
|
|
800174e: 2304 movcs r3, #4
|
|
8001750: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
8001752: 69fb ldr r3, [r7, #28]
|
|
8001754: 3304 adds r3, #4
|
|
8001756: 2b06 cmp r3, #6
|
|
8001758: d902 bls.n 8001760 <NVIC_EncodePriority+0x30>
|
|
800175a: 69fb ldr r3, [r7, #28]
|
|
800175c: 3b03 subs r3, #3
|
|
800175e: e000 b.n 8001762 <NVIC_EncodePriority+0x32>
|
|
8001760: 2300 movs r3, #0
|
|
8001762: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001764: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8001768: 69bb ldr r3, [r7, #24]
|
|
800176a: fa02 f303 lsl.w r3, r2, r3
|
|
800176e: 43da mvns r2, r3
|
|
8001770: 68bb ldr r3, [r7, #8]
|
|
8001772: 401a ands r2, r3
|
|
8001774: 697b ldr r3, [r7, #20]
|
|
8001776: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
8001778: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
800177c: 697b ldr r3, [r7, #20]
|
|
800177e: fa01 f303 lsl.w r3, r1, r3
|
|
8001782: 43d9 mvns r1, r3
|
|
8001784: 687b ldr r3, [r7, #4]
|
|
8001786: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8001788: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
800178a: 4618 mov r0, r3
|
|
800178c: 3724 adds r7, #36 @ 0x24
|
|
800178e: 46bd mov sp, r7
|
|
8001790: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001794: 4770 bx lr
|
|
|
|
08001796 <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
8001796: b580 push {r7, lr}
|
|
8001798: b082 sub sp, #8
|
|
800179a: af00 add r7, sp, #0
|
|
800179c: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
800179e: 6878 ldr r0, [r7, #4]
|
|
80017a0: f7ff ff4c bl 800163c <__NVIC_SetPriorityGrouping>
|
|
}
|
|
80017a4: bf00 nop
|
|
80017a6: 3708 adds r7, #8
|
|
80017a8: 46bd mov sp, r7
|
|
80017aa: bd80 pop {r7, pc}
|
|
|
|
080017ac <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80017ac: b580 push {r7, lr}
|
|
80017ae: b086 sub sp, #24
|
|
80017b0: af00 add r7, sp, #0
|
|
80017b2: 4603 mov r3, r0
|
|
80017b4: 60b9 str r1, [r7, #8]
|
|
80017b6: 607a str r2, [r7, #4]
|
|
80017b8: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00U;
|
|
80017ba: 2300 movs r3, #0
|
|
80017bc: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
80017be: f7ff ff61 bl 8001684 <__NVIC_GetPriorityGrouping>
|
|
80017c2: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
80017c4: 687a ldr r2, [r7, #4]
|
|
80017c6: 68b9 ldr r1, [r7, #8]
|
|
80017c8: 6978 ldr r0, [r7, #20]
|
|
80017ca: f7ff ffb1 bl 8001730 <NVIC_EncodePriority>
|
|
80017ce: 4602 mov r2, r0
|
|
80017d0: f997 300f ldrsb.w r3, [r7, #15]
|
|
80017d4: 4611 mov r1, r2
|
|
80017d6: 4618 mov r0, r3
|
|
80017d8: f7ff ff80 bl 80016dc <__NVIC_SetPriority>
|
|
}
|
|
80017dc: bf00 nop
|
|
80017de: 3718 adds r7, #24
|
|
80017e0: 46bd mov sp, r7
|
|
80017e2: bd80 pop {r7, pc}
|
|
|
|
080017e4 <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80017e4: b580 push {r7, lr}
|
|
80017e6: b082 sub sp, #8
|
|
80017e8: af00 add r7, sp, #0
|
|
80017ea: 4603 mov r3, r0
|
|
80017ec: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
80017ee: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80017f2: 4618 mov r0, r3
|
|
80017f4: f7ff ff54 bl 80016a0 <__NVIC_EnableIRQ>
|
|
}
|
|
80017f8: bf00 nop
|
|
80017fa: 3708 adds r7, #8
|
|
80017fc: 46bd mov sp, r7
|
|
80017fe: bd80 pop {r7, pc}
|
|
|
|
08001800 <HAL_CRC_Init>:
|
|
* parameters in the CRC_InitTypeDef and create the associated handle.
|
|
* @param hcrc CRC handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
|
{
|
|
8001800: b580 push {r7, lr}
|
|
8001802: b082 sub sp, #8
|
|
8001804: af00 add r7, sp, #0
|
|
8001806: 6078 str r0, [r7, #4]
|
|
/* Check the CRC handle allocation */
|
|
if (hcrc == NULL)
|
|
8001808: 687b ldr r3, [r7, #4]
|
|
800180a: 2b00 cmp r3, #0
|
|
800180c: d101 bne.n 8001812 <HAL_CRC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800180e: 2301 movs r3, #1
|
|
8001810: e00e b.n 8001830 <HAL_CRC_Init+0x30>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
|
|
|
if (hcrc->State == HAL_CRC_STATE_RESET)
|
|
8001812: 687b ldr r3, [r7, #4]
|
|
8001814: 795b ldrb r3, [r3, #5]
|
|
8001816: b2db uxtb r3, r3
|
|
8001818: 2b00 cmp r3, #0
|
|
800181a: d105 bne.n 8001828 <HAL_CRC_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hcrc->Lock = HAL_UNLOCKED;
|
|
800181c: 687b ldr r3, [r7, #4]
|
|
800181e: 2200 movs r2, #0
|
|
8001820: 711a strb r2, [r3, #4]
|
|
/* Init the low level hardware */
|
|
HAL_CRC_MspInit(hcrc);
|
|
8001822: 6878 ldr r0, [r7, #4]
|
|
8001824: f7ff fa76 bl 8000d14 <HAL_CRC_MspInit>
|
|
}
|
|
|
|
/* Change CRC peripheral state */
|
|
hcrc->State = HAL_CRC_STATE_READY;
|
|
8001828: 687b ldr r3, [r7, #4]
|
|
800182a: 2201 movs r2, #1
|
|
800182c: 715a strb r2, [r3, #5]
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800182e: 2300 movs r3, #0
|
|
}
|
|
8001830: 4618 mov r0, r3
|
|
8001832: 3708 adds r7, #8
|
|
8001834: 46bd mov sp, r7
|
|
8001836: bd80 pop {r7, pc}
|
|
|
|
08001838 <HAL_DMA2D_Init>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001838: b580 push {r7, lr}
|
|
800183a: b082 sub sp, #8
|
|
800183c: af00 add r7, sp, #0
|
|
800183e: 6078 str r0, [r7, #4]
|
|
/* Check the DMA2D peripheral state */
|
|
if (hdma2d == NULL)
|
|
8001840: 687b ldr r3, [r7, #4]
|
|
8001842: 2b00 cmp r3, #0
|
|
8001844: d101 bne.n 800184a <HAL_DMA2D_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8001846: 2301 movs r3, #1
|
|
8001848: e03b b.n 80018c2 <HAL_DMA2D_Init+0x8a>
|
|
|
|
/* Init the low level hardware */
|
|
hdma2d->MspInitCallback(hdma2d);
|
|
}
|
|
#else
|
|
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
|
|
800184a: 687b ldr r3, [r7, #4]
|
|
800184c: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
|
|
8001850: b2db uxtb r3, r3
|
|
8001852: 2b00 cmp r3, #0
|
|
8001854: d106 bne.n 8001864 <HAL_DMA2D_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hdma2d->Lock = HAL_UNLOCKED;
|
|
8001856: 687b ldr r3, [r7, #4]
|
|
8001858: 2200 movs r2, #0
|
|
800185a: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
/* Init the low level hardware */
|
|
HAL_DMA2D_MspInit(hdma2d);
|
|
800185e: 6878 ldr r0, [r7, #4]
|
|
8001860: f7ff fa7a bl 8000d58 <HAL_DMA2D_MspInit>
|
|
}
|
|
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8001864: 687b ldr r3, [r7, #4]
|
|
8001866: 2202 movs r2, #2
|
|
8001868: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* DMA2D CR register configuration -------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
|
|
800186c: 687b ldr r3, [r7, #4]
|
|
800186e: 681b ldr r3, [r3, #0]
|
|
8001870: 681b ldr r3, [r3, #0]
|
|
8001872: f423 3140 bic.w r1, r3, #196608 @ 0x30000
|
|
8001876: 687b ldr r3, [r7, #4]
|
|
8001878: 685a ldr r2, [r3, #4]
|
|
800187a: 687b ldr r3, [r7, #4]
|
|
800187c: 681b ldr r3, [r3, #0]
|
|
800187e: 430a orrs r2, r1
|
|
8001880: 601a str r2, [r3, #0]
|
|
|
|
/* DMA2D OPFCCR register configuration ---------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
|
|
8001882: 687b ldr r3, [r7, #4]
|
|
8001884: 681b ldr r3, [r3, #0]
|
|
8001886: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8001888: f023 0107 bic.w r1, r3, #7
|
|
800188c: 687b ldr r3, [r7, #4]
|
|
800188e: 689a ldr r2, [r3, #8]
|
|
8001890: 687b ldr r3, [r7, #4]
|
|
8001892: 681b ldr r3, [r3, #0]
|
|
8001894: 430a orrs r2, r1
|
|
8001896: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* DMA2D OOR register configuration ------------------------------------------*/
|
|
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
|
|
8001898: 687b ldr r3, [r7, #4]
|
|
800189a: 681b ldr r3, [r3, #0]
|
|
800189c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800189e: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
|
|
80018a2: f023 033f bic.w r3, r3, #63 @ 0x3f
|
|
80018a6: 687a ldr r2, [r7, #4]
|
|
80018a8: 68d1 ldr r1, [r2, #12]
|
|
80018aa: 687a ldr r2, [r7, #4]
|
|
80018ac: 6812 ldr r2, [r2, #0]
|
|
80018ae: 430b orrs r3, r1
|
|
80018b0: 6413 str r3, [r2, #64] @ 0x40
|
|
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
|
|
80018b2: 687b ldr r3, [r7, #4]
|
|
80018b4: 2200 movs r2, #0
|
|
80018b6: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
80018b8: 687b ldr r3, [r7, #4]
|
|
80018ba: 2201 movs r2, #1
|
|
80018bc: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
return HAL_OK;
|
|
80018c0: 2300 movs r3, #0
|
|
}
|
|
80018c2: 4618 mov r0, r3
|
|
80018c4: 3708 adds r7, #8
|
|
80018c6: 46bd mov sp, r7
|
|
80018c8: bd80 pop {r7, pc}
|
|
|
|
080018ca <HAL_DMA2D_IRQHandler>:
|
|
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
80018ca: b580 push {r7, lr}
|
|
80018cc: b084 sub sp, #16
|
|
80018ce: af00 add r7, sp, #0
|
|
80018d0: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
|
|
80018d2: 687b ldr r3, [r7, #4]
|
|
80018d4: 681b ldr r3, [r3, #0]
|
|
80018d6: 685b ldr r3, [r3, #4]
|
|
80018d8: 60fb str r3, [r7, #12]
|
|
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
|
|
80018da: 687b ldr r3, [r7, #4]
|
|
80018dc: 681b ldr r3, [r3, #0]
|
|
80018de: 681b ldr r3, [r3, #0]
|
|
80018e0: 60bb str r3, [r7, #8]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if ((isrflags & DMA2D_FLAG_TE) != 0U)
|
|
80018e2: 68fb ldr r3, [r7, #12]
|
|
80018e4: f003 0301 and.w r3, r3, #1
|
|
80018e8: 2b00 cmp r3, #0
|
|
80018ea: d026 beq.n 800193a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
if ((crflags & DMA2D_IT_TE) != 0U)
|
|
80018ec: 68bb ldr r3, [r7, #8]
|
|
80018ee: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80018f2: 2b00 cmp r3, #0
|
|
80018f4: d021 beq.n 800193a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
/* Disable the transfer Error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
|
|
80018f6: 687b ldr r3, [r7, #4]
|
|
80018f8: 681b ldr r3, [r3, #0]
|
|
80018fa: 681a ldr r2, [r3, #0]
|
|
80018fc: 687b ldr r3, [r7, #4]
|
|
80018fe: 681b ldr r3, [r3, #0]
|
|
8001900: f422 7280 bic.w r2, r2, #256 @ 0x100
|
|
8001904: 601a str r2, [r3, #0]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
|
|
8001906: 687b ldr r3, [r7, #4]
|
|
8001908: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800190a: f043 0201 orr.w r2, r3, #1
|
|
800190e: 687b ldr r3, [r7, #4]
|
|
8001910: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Clear the transfer error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
|
|
8001912: 687b ldr r3, [r7, #4]
|
|
8001914: 681b ldr r3, [r3, #0]
|
|
8001916: 2201 movs r2, #1
|
|
8001918: 609a str r2, [r3, #8]
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
800191a: 687b ldr r3, [r7, #4]
|
|
800191c: 2204 movs r2, #4
|
|
800191e: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001922: 687b ldr r3, [r7, #4]
|
|
8001924: 2200 movs r2, #0
|
|
8001926: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
800192a: 687b ldr r3, [r7, #4]
|
|
800192c: 695b ldr r3, [r3, #20]
|
|
800192e: 2b00 cmp r3, #0
|
|
8001930: d003 beq.n 800193a <HAL_DMA2D_IRQHandler+0x70>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
8001932: 687b ldr r3, [r7, #4]
|
|
8001934: 695b ldr r3, [r3, #20]
|
|
8001936: 6878 ldr r0, [r7, #4]
|
|
8001938: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* Configuration Error Interrupt management **********************************/
|
|
if ((isrflags & DMA2D_FLAG_CE) != 0U)
|
|
800193a: 68fb ldr r3, [r7, #12]
|
|
800193c: f003 0320 and.w r3, r3, #32
|
|
8001940: 2b00 cmp r3, #0
|
|
8001942: d026 beq.n 8001992 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
if ((crflags & DMA2D_IT_CE) != 0U)
|
|
8001944: 68bb ldr r3, [r7, #8]
|
|
8001946: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800194a: 2b00 cmp r3, #0
|
|
800194c: d021 beq.n 8001992 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
/* Disable the Configuration Error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
|
|
800194e: 687b ldr r3, [r7, #4]
|
|
8001950: 681b ldr r3, [r3, #0]
|
|
8001952: 681a ldr r2, [r3, #0]
|
|
8001954: 687b ldr r3, [r7, #4]
|
|
8001956: 681b ldr r3, [r3, #0]
|
|
8001958: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
800195c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the Configuration error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
|
|
800195e: 687b ldr r3, [r7, #4]
|
|
8001960: 681b ldr r3, [r3, #0]
|
|
8001962: 2220 movs r2, #32
|
|
8001964: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
|
|
8001966: 687b ldr r3, [r7, #4]
|
|
8001968: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800196a: f043 0202 orr.w r2, r3, #2
|
|
800196e: 687b ldr r3, [r7, #4]
|
|
8001970: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
8001972: 687b ldr r3, [r7, #4]
|
|
8001974: 2204 movs r2, #4
|
|
8001976: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
800197a: 687b ldr r3, [r7, #4]
|
|
800197c: 2200 movs r2, #0
|
|
800197e: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
8001982: 687b ldr r3, [r7, #4]
|
|
8001984: 695b ldr r3, [r3, #20]
|
|
8001986: 2b00 cmp r3, #0
|
|
8001988: d003 beq.n 8001992 <HAL_DMA2D_IRQHandler+0xc8>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
800198a: 687b ldr r3, [r7, #4]
|
|
800198c: 695b ldr r3, [r3, #20]
|
|
800198e: 6878 ldr r0, [r7, #4]
|
|
8001990: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* CLUT access Error Interrupt management ***********************************/
|
|
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
|
|
8001992: 68fb ldr r3, [r7, #12]
|
|
8001994: f003 0308 and.w r3, r3, #8
|
|
8001998: 2b00 cmp r3, #0
|
|
800199a: d026 beq.n 80019ea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
if ((crflags & DMA2D_IT_CAE) != 0U)
|
|
800199c: 68bb ldr r3, [r7, #8]
|
|
800199e: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80019a2: 2b00 cmp r3, #0
|
|
80019a4: d021 beq.n 80019ea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
/* Disable the CLUT access error interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
|
|
80019a6: 687b ldr r3, [r7, #4]
|
|
80019a8: 681b ldr r3, [r3, #0]
|
|
80019aa: 681a ldr r2, [r3, #0]
|
|
80019ac: 687b ldr r3, [r7, #4]
|
|
80019ae: 681b ldr r3, [r3, #0]
|
|
80019b0: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
80019b4: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the CLUT access error flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
|
|
80019b6: 687b ldr r3, [r7, #4]
|
|
80019b8: 681b ldr r3, [r3, #0]
|
|
80019ba: 2208 movs r2, #8
|
|
80019bc: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
|
|
80019be: 687b ldr r3, [r7, #4]
|
|
80019c0: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
80019c2: f043 0204 orr.w r2, r3, #4
|
|
80019c6: 687b ldr r3, [r7, #4]
|
|
80019c8: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_ERROR;
|
|
80019ca: 687b ldr r3, [r7, #4]
|
|
80019cc: 2204 movs r2, #4
|
|
80019ce: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
80019d2: 687b ldr r3, [r7, #4]
|
|
80019d4: 2200 movs r2, #0
|
|
80019d6: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferErrorCallback != NULL)
|
|
80019da: 687b ldr r3, [r7, #4]
|
|
80019dc: 695b ldr r3, [r3, #20]
|
|
80019de: 2b00 cmp r3, #0
|
|
80019e0: d003 beq.n 80019ea <HAL_DMA2D_IRQHandler+0x120>
|
|
{
|
|
/* Transfer error Callback */
|
|
hdma2d->XferErrorCallback(hdma2d);
|
|
80019e2: 687b ldr r3, [r7, #4]
|
|
80019e4: 695b ldr r3, [r3, #20]
|
|
80019e6: 6878 ldr r0, [r7, #4]
|
|
80019e8: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* Transfer watermark Interrupt management **********************************/
|
|
if ((isrflags & DMA2D_FLAG_TW) != 0U)
|
|
80019ea: 68fb ldr r3, [r7, #12]
|
|
80019ec: f003 0304 and.w r3, r3, #4
|
|
80019f0: 2b00 cmp r3, #0
|
|
80019f2: d013 beq.n 8001a1c <HAL_DMA2D_IRQHandler+0x152>
|
|
{
|
|
if ((crflags & DMA2D_IT_TW) != 0U)
|
|
80019f4: 68bb ldr r3, [r7, #8]
|
|
80019f6: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80019fa: 2b00 cmp r3, #0
|
|
80019fc: d00e beq.n 8001a1c <HAL_DMA2D_IRQHandler+0x152>
|
|
{
|
|
/* Disable the transfer watermark interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
|
|
80019fe: 687b ldr r3, [r7, #4]
|
|
8001a00: 681b ldr r3, [r3, #0]
|
|
8001a02: 681a ldr r2, [r3, #0]
|
|
8001a04: 687b ldr r3, [r7, #4]
|
|
8001a06: 681b ldr r3, [r3, #0]
|
|
8001a08: f422 6280 bic.w r2, r2, #1024 @ 0x400
|
|
8001a0c: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer watermark flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
|
|
8001a0e: 687b ldr r3, [r7, #4]
|
|
8001a10: 681b ldr r3, [r3, #0]
|
|
8001a12: 2204 movs r2, #4
|
|
8001a14: 609a str r2, [r3, #8]
|
|
|
|
/* Transfer watermark Callback */
|
|
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
|
hdma2d->LineEventCallback(hdma2d);
|
|
#else
|
|
HAL_DMA2D_LineEventCallback(hdma2d);
|
|
8001a16: 6878 ldr r0, [r7, #4]
|
|
8001a18: f000 f853 bl 8001ac2 <HAL_DMA2D_LineEventCallback>
|
|
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
|
|
|
}
|
|
}
|
|
/* Transfer Complete Interrupt management ************************************/
|
|
if ((isrflags & DMA2D_FLAG_TC) != 0U)
|
|
8001a1c: 68fb ldr r3, [r7, #12]
|
|
8001a1e: f003 0302 and.w r3, r3, #2
|
|
8001a22: 2b00 cmp r3, #0
|
|
8001a24: d024 beq.n 8001a70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
if ((crflags & DMA2D_IT_TC) != 0U)
|
|
8001a26: 68bb ldr r3, [r7, #8]
|
|
8001a28: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8001a2c: 2b00 cmp r3, #0
|
|
8001a2e: d01f beq.n 8001a70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
/* Disable the transfer complete interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
|
|
8001a30: 687b ldr r3, [r7, #4]
|
|
8001a32: 681b ldr r3, [r3, #0]
|
|
8001a34: 681a ldr r2, [r3, #0]
|
|
8001a36: 687b ldr r3, [r7, #4]
|
|
8001a38: 681b ldr r3, [r3, #0]
|
|
8001a3a: f422 7200 bic.w r2, r2, #512 @ 0x200
|
|
8001a3e: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the transfer complete flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
|
|
8001a40: 687b ldr r3, [r7, #4]
|
|
8001a42: 681b ldr r3, [r3, #0]
|
|
8001a44: 2202 movs r2, #2
|
|
8001a46: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
|
|
8001a48: 687b ldr r3, [r7, #4]
|
|
8001a4a: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8001a4c: 687b ldr r3, [r7, #4]
|
|
8001a4e: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001a50: 687b ldr r3, [r7, #4]
|
|
8001a52: 2201 movs r2, #1
|
|
8001a54: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001a58: 687b ldr r3, [r7, #4]
|
|
8001a5a: 2200 movs r2, #0
|
|
8001a5c: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
if (hdma2d->XferCpltCallback != NULL)
|
|
8001a60: 687b ldr r3, [r7, #4]
|
|
8001a62: 691b ldr r3, [r3, #16]
|
|
8001a64: 2b00 cmp r3, #0
|
|
8001a66: d003 beq.n 8001a70 <HAL_DMA2D_IRQHandler+0x1a6>
|
|
{
|
|
/* Transfer complete Callback */
|
|
hdma2d->XferCpltCallback(hdma2d);
|
|
8001a68: 687b ldr r3, [r7, #4]
|
|
8001a6a: 691b ldr r3, [r3, #16]
|
|
8001a6c: 6878 ldr r0, [r7, #4]
|
|
8001a6e: 4798 blx r3
|
|
}
|
|
}
|
|
}
|
|
/* CLUT Transfer Complete Interrupt management ******************************/
|
|
if ((isrflags & DMA2D_FLAG_CTC) != 0U)
|
|
8001a70: 68fb ldr r3, [r7, #12]
|
|
8001a72: f003 0310 and.w r3, r3, #16
|
|
8001a76: 2b00 cmp r3, #0
|
|
8001a78: d01f beq.n 8001aba <HAL_DMA2D_IRQHandler+0x1f0>
|
|
{
|
|
if ((crflags & DMA2D_IT_CTC) != 0U)
|
|
8001a7a: 68bb ldr r3, [r7, #8]
|
|
8001a7c: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8001a80: 2b00 cmp r3, #0
|
|
8001a82: d01a beq.n 8001aba <HAL_DMA2D_IRQHandler+0x1f0>
|
|
{
|
|
/* Disable the CLUT transfer complete interrupt */
|
|
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
|
|
8001a84: 687b ldr r3, [r7, #4]
|
|
8001a86: 681b ldr r3, [r3, #0]
|
|
8001a88: 681a ldr r2, [r3, #0]
|
|
8001a8a: 687b ldr r3, [r7, #4]
|
|
8001a8c: 681b ldr r3, [r3, #0]
|
|
8001a8e: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
8001a92: 601a str r2, [r3, #0]
|
|
|
|
/* Clear the CLUT transfer complete flag */
|
|
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
|
|
8001a94: 687b ldr r3, [r7, #4]
|
|
8001a96: 681b ldr r3, [r3, #0]
|
|
8001a98: 2210 movs r2, #16
|
|
8001a9a: 609a str r2, [r3, #8]
|
|
|
|
/* Update error code */
|
|
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
|
|
8001a9c: 687b ldr r3, [r7, #4]
|
|
8001a9e: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8001aa0: 687b ldr r3, [r7, #4]
|
|
8001aa2: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change DMA2D state */
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001aa4: 687b ldr r3, [r7, #4]
|
|
8001aa6: 2201 movs r2, #1
|
|
8001aa8: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001aac: 687b ldr r3, [r7, #4]
|
|
8001aae: 2200 movs r2, #0
|
|
8001ab0: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* CLUT Transfer complete Callback */
|
|
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
|
|
hdma2d->CLUTLoadingCpltCallback(hdma2d);
|
|
#else
|
|
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
|
|
8001ab4: 6878 ldr r0, [r7, #4]
|
|
8001ab6: f000 f80e bl 8001ad6 <HAL_DMA2D_CLUTLoadingCpltCallback>
|
|
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
}
|
|
8001aba: bf00 nop
|
|
8001abc: 3710 adds r7, #16
|
|
8001abe: 46bd mov sp, r7
|
|
8001ac0: bd80 pop {r7, pc}
|
|
|
|
08001ac2 <HAL_DMA2D_LineEventCallback>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001ac2: b480 push {r7}
|
|
8001ac4: b083 sub sp, #12
|
|
8001ac6: af00 add r7, sp, #0
|
|
8001ac8: 6078 str r0, [r7, #4]
|
|
UNUSED(hdma2d);
|
|
|
|
/* NOTE : This function should not be modified; when the callback is needed,
|
|
the HAL_DMA2D_LineEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8001aca: bf00 nop
|
|
8001acc: 370c adds r7, #12
|
|
8001ace: 46bd mov sp, r7
|
|
8001ad0: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ad4: 4770 bx lr
|
|
|
|
08001ad6 <HAL_DMA2D_CLUTLoadingCpltCallback>:
|
|
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
|
|
* the configuration information for the DMA2D.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
|
|
{
|
|
8001ad6: b480 push {r7}
|
|
8001ad8: b083 sub sp, #12
|
|
8001ada: af00 add r7, sp, #0
|
|
8001adc: 6078 str r0, [r7, #4]
|
|
UNUSED(hdma2d);
|
|
|
|
/* NOTE : This function should not be modified; when the callback is needed,
|
|
the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8001ade: bf00 nop
|
|
8001ae0: 370c adds r7, #12
|
|
8001ae2: 46bd mov sp, r7
|
|
8001ae4: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001ae8: 4770 bx lr
|
|
...
|
|
|
|
08001aec <HAL_DMA2D_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
|
|
{
|
|
8001aec: b480 push {r7}
|
|
8001aee: b087 sub sp, #28
|
|
8001af0: af00 add r7, sp, #0
|
|
8001af2: 6078 str r0, [r7, #4]
|
|
8001af4: 6039 str r1, [r7, #0]
|
|
uint32_t regValue;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA2D_LAYER(LayerIdx));
|
|
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
|
|
if (hdma2d->Init.Mode != DMA2D_R2M)
|
|
8001af6: 687b ldr r3, [r7, #4]
|
|
8001af8: 685b ldr r3, [r3, #4]
|
|
8001afa: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
|
|
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
|
|
}
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hdma2d);
|
|
8001afe: 687b ldr r3, [r7, #4]
|
|
8001b00: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
|
|
8001b04: 2b01 cmp r3, #1
|
|
8001b06: d101 bne.n 8001b0c <HAL_DMA2D_ConfigLayer+0x20>
|
|
8001b08: 2302 movs r3, #2
|
|
8001b0a: e079 b.n 8001c00 <HAL_DMA2D_ConfigLayer+0x114>
|
|
8001b0c: 687b ldr r3, [r7, #4]
|
|
8001b0e: 2201 movs r2, #1
|
|
8001b10: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
/* Change DMA2D peripheral state */
|
|
hdma2d->State = HAL_DMA2D_STATE_BUSY;
|
|
8001b14: 687b ldr r3, [r7, #4]
|
|
8001b16: 2202 movs r2, #2
|
|
8001b18: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
|
|
8001b1c: 683b ldr r3, [r7, #0]
|
|
8001b1e: 011b lsls r3, r3, #4
|
|
8001b20: 3318 adds r3, #24
|
|
8001b22: 687a ldr r2, [r7, #4]
|
|
8001b24: 4413 add r3, r2
|
|
8001b26: 613b str r3, [r7, #16]
|
|
|
|
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
|
|
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
|
|
8001b28: 693b ldr r3, [r7, #16]
|
|
8001b2a: 685a ldr r2, [r3, #4]
|
|
8001b2c: 693b ldr r3, [r7, #16]
|
|
8001b2e: 689b ldr r3, [r3, #8]
|
|
8001b30: 041b lsls r3, r3, #16
|
|
8001b32: 4313 orrs r3, r2
|
|
8001b34: 617b str r3, [r7, #20]
|
|
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
|
|
8001b36: 4b35 ldr r3, [pc, #212] @ (8001c0c <HAL_DMA2D_ConfigLayer+0x120>)
|
|
8001b38: 60fb str r3, [r7, #12]
|
|
|
|
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001b3a: 693b ldr r3, [r7, #16]
|
|
8001b3c: 685b ldr r3, [r3, #4]
|
|
8001b3e: 2b0a cmp r3, #10
|
|
8001b40: d003 beq.n 8001b4a <HAL_DMA2D_ConfigLayer+0x5e>
|
|
8001b42: 693b ldr r3, [r7, #16]
|
|
8001b44: 685b ldr r3, [r3, #4]
|
|
8001b46: 2b09 cmp r3, #9
|
|
8001b48: d107 bne.n 8001b5a <HAL_DMA2D_ConfigLayer+0x6e>
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
|
|
8001b4a: 693b ldr r3, [r7, #16]
|
|
8001b4c: 68db ldr r3, [r3, #12]
|
|
8001b4e: f003 437f and.w r3, r3, #4278190080 @ 0xff000000
|
|
8001b52: 697a ldr r2, [r7, #20]
|
|
8001b54: 4313 orrs r3, r2
|
|
8001b56: 617b str r3, [r7, #20]
|
|
8001b58: e005 b.n 8001b66 <HAL_DMA2D_ConfigLayer+0x7a>
|
|
}
|
|
else
|
|
{
|
|
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
|
|
8001b5a: 693b ldr r3, [r7, #16]
|
|
8001b5c: 68db ldr r3, [r3, #12]
|
|
8001b5e: 061b lsls r3, r3, #24
|
|
8001b60: 697a ldr r2, [r7, #20]
|
|
8001b62: 4313 orrs r3, r2
|
|
8001b64: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
/* Configure the background DMA2D layer */
|
|
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
|
|
8001b66: 683b ldr r3, [r7, #0]
|
|
8001b68: 2b00 cmp r3, #0
|
|
8001b6a: d120 bne.n 8001bae <HAL_DMA2D_ConfigLayer+0xc2>
|
|
{
|
|
/* Write DMA2D BGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
|
|
8001b6c: 687b ldr r3, [r7, #4]
|
|
8001b6e: 681b ldr r3, [r3, #0]
|
|
8001b70: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8001b72: 68fb ldr r3, [r7, #12]
|
|
8001b74: 43db mvns r3, r3
|
|
8001b76: ea02 0103 and.w r1, r2, r3
|
|
8001b7a: 687b ldr r3, [r7, #4]
|
|
8001b7c: 681b ldr r3, [r3, #0]
|
|
8001b7e: 697a ldr r2, [r7, #20]
|
|
8001b80: 430a orrs r2, r1
|
|
8001b82: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* DMA2D BGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
|
|
8001b84: 687b ldr r3, [r7, #4]
|
|
8001b86: 681b ldr r3, [r3, #0]
|
|
8001b88: 693a ldr r2, [r7, #16]
|
|
8001b8a: 6812 ldr r2, [r2, #0]
|
|
8001b8c: 619a str r2, [r3, #24]
|
|
|
|
/* DMA2D BGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001b8e: 693b ldr r3, [r7, #16]
|
|
8001b90: 685b ldr r3, [r3, #4]
|
|
8001b92: 2b0a cmp r3, #10
|
|
8001b94: d003 beq.n 8001b9e <HAL_DMA2D_ConfigLayer+0xb2>
|
|
8001b96: 693b ldr r3, [r7, #16]
|
|
8001b98: 685b ldr r3, [r3, #4]
|
|
8001b9a: 2b09 cmp r3, #9
|
|
8001b9c: d127 bne.n 8001bee <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
|
|
8001b9e: 693b ldr r3, [r7, #16]
|
|
8001ba0: 68da ldr r2, [r3, #12]
|
|
8001ba2: 687b ldr r3, [r7, #4]
|
|
8001ba4: 681b ldr r3, [r3, #0]
|
|
8001ba6: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
|
|
8001baa: 629a str r2, [r3, #40] @ 0x28
|
|
8001bac: e01f b.n 8001bee <HAL_DMA2D_ConfigLayer+0x102>
|
|
else
|
|
{
|
|
|
|
|
|
/* Write DMA2D FGPFCCR register */
|
|
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
|
|
8001bae: 687b ldr r3, [r7, #4]
|
|
8001bb0: 681b ldr r3, [r3, #0]
|
|
8001bb2: 69da ldr r2, [r3, #28]
|
|
8001bb4: 68fb ldr r3, [r7, #12]
|
|
8001bb6: 43db mvns r3, r3
|
|
8001bb8: ea02 0103 and.w r1, r2, r3
|
|
8001bbc: 687b ldr r3, [r7, #4]
|
|
8001bbe: 681b ldr r3, [r3, #0]
|
|
8001bc0: 697a ldr r2, [r7, #20]
|
|
8001bc2: 430a orrs r2, r1
|
|
8001bc4: 61da str r2, [r3, #28]
|
|
|
|
/* DMA2D FGOR register configuration -------------------------------------*/
|
|
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
|
|
8001bc6: 687b ldr r3, [r7, #4]
|
|
8001bc8: 681b ldr r3, [r3, #0]
|
|
8001bca: 693a ldr r2, [r7, #16]
|
|
8001bcc: 6812 ldr r2, [r2, #0]
|
|
8001bce: 611a str r2, [r3, #16]
|
|
|
|
/* DMA2D FGCOLR register configuration -------------------------------------*/
|
|
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
|
|
8001bd0: 693b ldr r3, [r7, #16]
|
|
8001bd2: 685b ldr r3, [r3, #4]
|
|
8001bd4: 2b0a cmp r3, #10
|
|
8001bd6: d003 beq.n 8001be0 <HAL_DMA2D_ConfigLayer+0xf4>
|
|
8001bd8: 693b ldr r3, [r7, #16]
|
|
8001bda: 685b ldr r3, [r3, #4]
|
|
8001bdc: 2b09 cmp r3, #9
|
|
8001bde: d106 bne.n 8001bee <HAL_DMA2D_ConfigLayer+0x102>
|
|
{
|
|
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
|
|
8001be0: 693b ldr r3, [r7, #16]
|
|
8001be2: 68da ldr r2, [r3, #12]
|
|
8001be4: 687b ldr r3, [r7, #4]
|
|
8001be6: 681b ldr r3, [r3, #0]
|
|
8001be8: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
|
|
8001bec: 621a str r2, [r3, #32]
|
|
DMA2D_FGCOLR_RED));
|
|
}
|
|
}
|
|
/* Initialize the DMA2D state*/
|
|
hdma2d->State = HAL_DMA2D_STATE_READY;
|
|
8001bee: 687b ldr r3, [r7, #4]
|
|
8001bf0: 2201 movs r2, #1
|
|
8001bf2: f883 2039 strb.w r2, [r3, #57] @ 0x39
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hdma2d);
|
|
8001bf6: 687b ldr r3, [r7, #4]
|
|
8001bf8: 2200 movs r2, #0
|
|
8001bfa: f883 2038 strb.w r2, [r3, #56] @ 0x38
|
|
|
|
return HAL_OK;
|
|
8001bfe: 2300 movs r3, #0
|
|
}
|
|
8001c00: 4618 mov r0, r3
|
|
8001c02: 371c adds r7, #28
|
|
8001c04: 46bd mov sp, r7
|
|
8001c06: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001c0a: 4770 bx lr
|
|
8001c0c: ff03000f .word 0xff03000f
|
|
|
|
08001c10 <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
8001c10: b480 push {r7}
|
|
8001c12: b089 sub sp, #36 @ 0x24
|
|
8001c14: af00 add r7, sp, #0
|
|
8001c16: 6078 str r0, [r7, #4]
|
|
8001c18: 6039 str r1, [r7, #0]
|
|
uint32_t position;
|
|
uint32_t ioposition = 0x00U;
|
|
8001c1a: 2300 movs r3, #0
|
|
8001c1c: 617b str r3, [r7, #20]
|
|
uint32_t iocurrent = 0x00U;
|
|
8001c1e: 2300 movs r3, #0
|
|
8001c20: 613b str r3, [r7, #16]
|
|
uint32_t temp = 0x00U;
|
|
8001c22: 2300 movs r3, #0
|
|
8001c24: 61bb str r3, [r7, #24]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8001c26: 2300 movs r3, #0
|
|
8001c28: 61fb str r3, [r7, #28]
|
|
8001c2a: e177 b.n 8001f1c <HAL_GPIO_Init+0x30c>
|
|
{
|
|
/* Get the IO position */
|
|
ioposition = 0x01U << position;
|
|
8001c2c: 2201 movs r2, #1
|
|
8001c2e: 69fb ldr r3, [r7, #28]
|
|
8001c30: fa02 f303 lsl.w r3, r2, r3
|
|
8001c34: 617b str r3, [r7, #20]
|
|
/* Get the current IO position */
|
|
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
8001c36: 683b ldr r3, [r7, #0]
|
|
8001c38: 681b ldr r3, [r3, #0]
|
|
8001c3a: 697a ldr r2, [r7, #20]
|
|
8001c3c: 4013 ands r3, r2
|
|
8001c3e: 613b str r3, [r7, #16]
|
|
|
|
if(iocurrent == ioposition)
|
|
8001c40: 693a ldr r2, [r7, #16]
|
|
8001c42: 697b ldr r3, [r7, #20]
|
|
8001c44: 429a cmp r2, r3
|
|
8001c46: f040 8166 bne.w 8001f16 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
8001c4a: 683b ldr r3, [r7, #0]
|
|
8001c4c: 685b ldr r3, [r3, #4]
|
|
8001c4e: f003 0303 and.w r3, r3, #3
|
|
8001c52: 2b01 cmp r3, #1
|
|
8001c54: d005 beq.n 8001c62 <HAL_GPIO_Init+0x52>
|
|
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001c56: 683b ldr r3, [r7, #0]
|
|
8001c58: 685b ldr r3, [r3, #4]
|
|
8001c5a: f003 0303 and.w r3, r3, #3
|
|
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
|
|
8001c5e: 2b02 cmp r3, #2
|
|
8001c60: d130 bne.n 8001cc4 <HAL_GPIO_Init+0xb4>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
8001c62: 687b ldr r3, [r7, #4]
|
|
8001c64: 689b ldr r3, [r3, #8]
|
|
8001c66: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
8001c68: 69fb ldr r3, [r7, #28]
|
|
8001c6a: 005b lsls r3, r3, #1
|
|
8001c6c: 2203 movs r2, #3
|
|
8001c6e: fa02 f303 lsl.w r3, r2, r3
|
|
8001c72: 43db mvns r3, r3
|
|
8001c74: 69ba ldr r2, [r7, #24]
|
|
8001c76: 4013 ands r3, r2
|
|
8001c78: 61bb str r3, [r7, #24]
|
|
temp |= (GPIO_Init->Speed << (position * 2U));
|
|
8001c7a: 683b ldr r3, [r7, #0]
|
|
8001c7c: 68da ldr r2, [r3, #12]
|
|
8001c7e: 69fb ldr r3, [r7, #28]
|
|
8001c80: 005b lsls r3, r3, #1
|
|
8001c82: fa02 f303 lsl.w r3, r2, r3
|
|
8001c86: 69ba ldr r2, [r7, #24]
|
|
8001c88: 4313 orrs r3, r2
|
|
8001c8a: 61bb str r3, [r7, #24]
|
|
GPIOx->OSPEEDR = temp;
|
|
8001c8c: 687b ldr r3, [r7, #4]
|
|
8001c8e: 69ba ldr r2, [r7, #24]
|
|
8001c90: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
8001c92: 687b ldr r3, [r7, #4]
|
|
8001c94: 685b ldr r3, [r3, #4]
|
|
8001c96: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
8001c98: 2201 movs r2, #1
|
|
8001c9a: 69fb ldr r3, [r7, #28]
|
|
8001c9c: fa02 f303 lsl.w r3, r2, r3
|
|
8001ca0: 43db mvns r3, r3
|
|
8001ca2: 69ba ldr r2, [r7, #24]
|
|
8001ca4: 4013 ands r3, r2
|
|
8001ca6: 61bb str r3, [r7, #24]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8001ca8: 683b ldr r3, [r7, #0]
|
|
8001caa: 685b ldr r3, [r3, #4]
|
|
8001cac: 091b lsrs r3, r3, #4
|
|
8001cae: f003 0201 and.w r2, r3, #1
|
|
8001cb2: 69fb ldr r3, [r7, #28]
|
|
8001cb4: fa02 f303 lsl.w r3, r2, r3
|
|
8001cb8: 69ba ldr r2, [r7, #24]
|
|
8001cba: 4313 orrs r3, r2
|
|
8001cbc: 61bb str r3, [r7, #24]
|
|
GPIOx->OTYPER = temp;
|
|
8001cbe: 687b ldr r3, [r7, #4]
|
|
8001cc0: 69ba ldr r2, [r7, #24]
|
|
8001cc2: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
8001cc4: 683b ldr r3, [r7, #0]
|
|
8001cc6: 685b ldr r3, [r3, #4]
|
|
8001cc8: f003 0303 and.w r3, r3, #3
|
|
8001ccc: 2b03 cmp r3, #3
|
|
8001cce: d017 beq.n 8001d00 <HAL_GPIO_Init+0xf0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
temp = GPIOx->PUPDR;
|
|
8001cd0: 687b ldr r3, [r7, #4]
|
|
8001cd2: 68db ldr r3, [r3, #12]
|
|
8001cd4: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
|
8001cd6: 69fb ldr r3, [r7, #28]
|
|
8001cd8: 005b lsls r3, r3, #1
|
|
8001cda: 2203 movs r2, #3
|
|
8001cdc: fa02 f303 lsl.w r3, r2, r3
|
|
8001ce0: 43db mvns r3, r3
|
|
8001ce2: 69ba ldr r2, [r7, #24]
|
|
8001ce4: 4013 ands r3, r2
|
|
8001ce6: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
8001ce8: 683b ldr r3, [r7, #0]
|
|
8001cea: 689a ldr r2, [r3, #8]
|
|
8001cec: 69fb ldr r3, [r7, #28]
|
|
8001cee: 005b lsls r3, r3, #1
|
|
8001cf0: fa02 f303 lsl.w r3, r2, r3
|
|
8001cf4: 69ba ldr r2, [r7, #24]
|
|
8001cf6: 4313 orrs r3, r2
|
|
8001cf8: 61bb str r3, [r7, #24]
|
|
GPIOx->PUPDR = temp;
|
|
8001cfa: 687b ldr r3, [r7, #4]
|
|
8001cfc: 69ba ldr r2, [r7, #24]
|
|
8001cfe: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
8001d00: 683b ldr r3, [r7, #0]
|
|
8001d02: 685b ldr r3, [r3, #4]
|
|
8001d04: f003 0303 and.w r3, r3, #3
|
|
8001d08: 2b02 cmp r3, #2
|
|
8001d0a: d123 bne.n 8001d54 <HAL_GPIO_Init+0x144>
|
|
{
|
|
/* Check the Alternate function parameter */
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3U];
|
|
8001d0c: 69fb ldr r3, [r7, #28]
|
|
8001d0e: 08da lsrs r2, r3, #3
|
|
8001d10: 687b ldr r3, [r7, #4]
|
|
8001d12: 3208 adds r2, #8
|
|
8001d14: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8001d18: 61bb str r3, [r7, #24]
|
|
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
8001d1a: 69fb ldr r3, [r7, #28]
|
|
8001d1c: f003 0307 and.w r3, r3, #7
|
|
8001d20: 009b lsls r3, r3, #2
|
|
8001d22: 220f movs r2, #15
|
|
8001d24: fa02 f303 lsl.w r3, r2, r3
|
|
8001d28: 43db mvns r3, r3
|
|
8001d2a: 69ba ldr r2, [r7, #24]
|
|
8001d2c: 4013 ands r3, r2
|
|
8001d2e: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
8001d30: 683b ldr r3, [r7, #0]
|
|
8001d32: 691a ldr r2, [r3, #16]
|
|
8001d34: 69fb ldr r3, [r7, #28]
|
|
8001d36: f003 0307 and.w r3, r3, #7
|
|
8001d3a: 009b lsls r3, r3, #2
|
|
8001d3c: fa02 f303 lsl.w r3, r2, r3
|
|
8001d40: 69ba ldr r2, [r7, #24]
|
|
8001d42: 4313 orrs r3, r2
|
|
8001d44: 61bb str r3, [r7, #24]
|
|
GPIOx->AFR[position >> 3U] = temp;
|
|
8001d46: 69fb ldr r3, [r7, #28]
|
|
8001d48: 08da lsrs r2, r3, #3
|
|
8001d4a: 687b ldr r3, [r7, #4]
|
|
8001d4c: 3208 adds r2, #8
|
|
8001d4e: 69b9 ldr r1, [r7, #24]
|
|
8001d50: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
8001d54: 687b ldr r3, [r7, #4]
|
|
8001d56: 681b ldr r3, [r3, #0]
|
|
8001d58: 61bb str r3, [r7, #24]
|
|
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
8001d5a: 69fb ldr r3, [r7, #28]
|
|
8001d5c: 005b lsls r3, r3, #1
|
|
8001d5e: 2203 movs r2, #3
|
|
8001d60: fa02 f303 lsl.w r3, r2, r3
|
|
8001d64: 43db mvns r3, r3
|
|
8001d66: 69ba ldr r2, [r7, #24]
|
|
8001d68: 4013 ands r3, r2
|
|
8001d6a: 61bb str r3, [r7, #24]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
8001d6c: 683b ldr r3, [r7, #0]
|
|
8001d6e: 685b ldr r3, [r3, #4]
|
|
8001d70: f003 0203 and.w r2, r3, #3
|
|
8001d74: 69fb ldr r3, [r7, #28]
|
|
8001d76: 005b lsls r3, r3, #1
|
|
8001d78: fa02 f303 lsl.w r3, r2, r3
|
|
8001d7c: 69ba ldr r2, [r7, #24]
|
|
8001d7e: 4313 orrs r3, r2
|
|
8001d80: 61bb str r3, [r7, #24]
|
|
GPIOx->MODER = temp;
|
|
8001d82: 687b ldr r3, [r7, #4]
|
|
8001d84: 69ba ldr r2, [r7, #24]
|
|
8001d86: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
|
|
8001d88: 683b ldr r3, [r7, #0]
|
|
8001d8a: 685b ldr r3, [r3, #4]
|
|
8001d8c: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8001d90: 2b00 cmp r3, #0
|
|
8001d92: f000 80c0 beq.w 8001f16 <HAL_GPIO_Init+0x306>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001d96: 2300 movs r3, #0
|
|
8001d98: 60fb str r3, [r7, #12]
|
|
8001d9a: 4b66 ldr r3, [pc, #408] @ (8001f34 <HAL_GPIO_Init+0x324>)
|
|
8001d9c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001d9e: 4a65 ldr r2, [pc, #404] @ (8001f34 <HAL_GPIO_Init+0x324>)
|
|
8001da0: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
8001da4: 6453 str r3, [r2, #68] @ 0x44
|
|
8001da6: 4b63 ldr r3, [pc, #396] @ (8001f34 <HAL_GPIO_Init+0x324>)
|
|
8001da8: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8001daa: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
8001dae: 60fb str r3, [r7, #12]
|
|
8001db0: 68fb ldr r3, [r7, #12]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2U];
|
|
8001db2: 4a61 ldr r2, [pc, #388] @ (8001f38 <HAL_GPIO_Init+0x328>)
|
|
8001db4: 69fb ldr r3, [r7, #28]
|
|
8001db6: 089b lsrs r3, r3, #2
|
|
8001db8: 3302 adds r3, #2
|
|
8001dba: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
8001dbe: 61bb str r3, [r7, #24]
|
|
temp &= ~(0x0FU << (4U * (position & 0x03U)));
|
|
8001dc0: 69fb ldr r3, [r7, #28]
|
|
8001dc2: f003 0303 and.w r3, r3, #3
|
|
8001dc6: 009b lsls r3, r3, #2
|
|
8001dc8: 220f movs r2, #15
|
|
8001dca: fa02 f303 lsl.w r3, r2, r3
|
|
8001dce: 43db mvns r3, r3
|
|
8001dd0: 69ba ldr r2, [r7, #24]
|
|
8001dd2: 4013 ands r3, r2
|
|
8001dd4: 61bb str r3, [r7, #24]
|
|
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
|
8001dd6: 687b ldr r3, [r7, #4]
|
|
8001dd8: 4a58 ldr r2, [pc, #352] @ (8001f3c <HAL_GPIO_Init+0x32c>)
|
|
8001dda: 4293 cmp r3, r2
|
|
8001ddc: d037 beq.n 8001e4e <HAL_GPIO_Init+0x23e>
|
|
8001dde: 687b ldr r3, [r7, #4]
|
|
8001de0: 4a57 ldr r2, [pc, #348] @ (8001f40 <HAL_GPIO_Init+0x330>)
|
|
8001de2: 4293 cmp r3, r2
|
|
8001de4: d031 beq.n 8001e4a <HAL_GPIO_Init+0x23a>
|
|
8001de6: 687b ldr r3, [r7, #4]
|
|
8001de8: 4a56 ldr r2, [pc, #344] @ (8001f44 <HAL_GPIO_Init+0x334>)
|
|
8001dea: 4293 cmp r3, r2
|
|
8001dec: d02b beq.n 8001e46 <HAL_GPIO_Init+0x236>
|
|
8001dee: 687b ldr r3, [r7, #4]
|
|
8001df0: 4a55 ldr r2, [pc, #340] @ (8001f48 <HAL_GPIO_Init+0x338>)
|
|
8001df2: 4293 cmp r3, r2
|
|
8001df4: d025 beq.n 8001e42 <HAL_GPIO_Init+0x232>
|
|
8001df6: 687b ldr r3, [r7, #4]
|
|
8001df8: 4a54 ldr r2, [pc, #336] @ (8001f4c <HAL_GPIO_Init+0x33c>)
|
|
8001dfa: 4293 cmp r3, r2
|
|
8001dfc: d01f beq.n 8001e3e <HAL_GPIO_Init+0x22e>
|
|
8001dfe: 687b ldr r3, [r7, #4]
|
|
8001e00: 4a53 ldr r2, [pc, #332] @ (8001f50 <HAL_GPIO_Init+0x340>)
|
|
8001e02: 4293 cmp r3, r2
|
|
8001e04: d019 beq.n 8001e3a <HAL_GPIO_Init+0x22a>
|
|
8001e06: 687b ldr r3, [r7, #4]
|
|
8001e08: 4a52 ldr r2, [pc, #328] @ (8001f54 <HAL_GPIO_Init+0x344>)
|
|
8001e0a: 4293 cmp r3, r2
|
|
8001e0c: d013 beq.n 8001e36 <HAL_GPIO_Init+0x226>
|
|
8001e0e: 687b ldr r3, [r7, #4]
|
|
8001e10: 4a51 ldr r2, [pc, #324] @ (8001f58 <HAL_GPIO_Init+0x348>)
|
|
8001e12: 4293 cmp r3, r2
|
|
8001e14: d00d beq.n 8001e32 <HAL_GPIO_Init+0x222>
|
|
8001e16: 687b ldr r3, [r7, #4]
|
|
8001e18: 4a50 ldr r2, [pc, #320] @ (8001f5c <HAL_GPIO_Init+0x34c>)
|
|
8001e1a: 4293 cmp r3, r2
|
|
8001e1c: d007 beq.n 8001e2e <HAL_GPIO_Init+0x21e>
|
|
8001e1e: 687b ldr r3, [r7, #4]
|
|
8001e20: 4a4f ldr r2, [pc, #316] @ (8001f60 <HAL_GPIO_Init+0x350>)
|
|
8001e22: 4293 cmp r3, r2
|
|
8001e24: d101 bne.n 8001e2a <HAL_GPIO_Init+0x21a>
|
|
8001e26: 2309 movs r3, #9
|
|
8001e28: e012 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e2a: 230a movs r3, #10
|
|
8001e2c: e010 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e2e: 2308 movs r3, #8
|
|
8001e30: e00e b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e32: 2307 movs r3, #7
|
|
8001e34: e00c b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e36: 2306 movs r3, #6
|
|
8001e38: e00a b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e3a: 2305 movs r3, #5
|
|
8001e3c: e008 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e3e: 2304 movs r3, #4
|
|
8001e40: e006 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e42: 2303 movs r3, #3
|
|
8001e44: e004 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e46: 2302 movs r3, #2
|
|
8001e48: e002 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e4a: 2301 movs r3, #1
|
|
8001e4c: e000 b.n 8001e50 <HAL_GPIO_Init+0x240>
|
|
8001e4e: 2300 movs r3, #0
|
|
8001e50: 69fa ldr r2, [r7, #28]
|
|
8001e52: f002 0203 and.w r2, r2, #3
|
|
8001e56: 0092 lsls r2, r2, #2
|
|
8001e58: 4093 lsls r3, r2
|
|
8001e5a: 69ba ldr r2, [r7, #24]
|
|
8001e5c: 4313 orrs r3, r2
|
|
8001e5e: 61bb str r3, [r7, #24]
|
|
SYSCFG->EXTICR[position >> 2U] = temp;
|
|
8001e60: 4935 ldr r1, [pc, #212] @ (8001f38 <HAL_GPIO_Init+0x328>)
|
|
8001e62: 69fb ldr r3, [r7, #28]
|
|
8001e64: 089b lsrs r3, r3, #2
|
|
8001e66: 3302 adds r3, #2
|
|
8001e68: 69ba ldr r2, [r7, #24]
|
|
8001e6a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR;
|
|
8001e6e: 4b3d ldr r3, [pc, #244] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001e70: 689b ldr r3, [r3, #8]
|
|
8001e72: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001e74: 693b ldr r3, [r7, #16]
|
|
8001e76: 43db mvns r3, r3
|
|
8001e78: 69ba ldr r2, [r7, #24]
|
|
8001e7a: 4013 ands r3, r2
|
|
8001e7c: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
|
|
8001e7e: 683b ldr r3, [r7, #0]
|
|
8001e80: 685b ldr r3, [r3, #4]
|
|
8001e82: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8001e86: 2b00 cmp r3, #0
|
|
8001e88: d003 beq.n 8001e92 <HAL_GPIO_Init+0x282>
|
|
{
|
|
temp |= iocurrent;
|
|
8001e8a: 69ba ldr r2, [r7, #24]
|
|
8001e8c: 693b ldr r3, [r7, #16]
|
|
8001e8e: 4313 orrs r3, r2
|
|
8001e90: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->RTSR = temp;
|
|
8001e92: 4a34 ldr r2, [pc, #208] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001e94: 69bb ldr r3, [r7, #24]
|
|
8001e96: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR;
|
|
8001e98: 4b32 ldr r3, [pc, #200] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001e9a: 68db ldr r3, [r3, #12]
|
|
8001e9c: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001e9e: 693b ldr r3, [r7, #16]
|
|
8001ea0: 43db mvns r3, r3
|
|
8001ea2: 69ba ldr r2, [r7, #24]
|
|
8001ea4: 4013 ands r3, r2
|
|
8001ea6: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
|
|
8001ea8: 683b ldr r3, [r7, #0]
|
|
8001eaa: 685b ldr r3, [r3, #4]
|
|
8001eac: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8001eb0: 2b00 cmp r3, #0
|
|
8001eb2: d003 beq.n 8001ebc <HAL_GPIO_Init+0x2ac>
|
|
{
|
|
temp |= iocurrent;
|
|
8001eb4: 69ba ldr r2, [r7, #24]
|
|
8001eb6: 693b ldr r3, [r7, #16]
|
|
8001eb8: 4313 orrs r3, r2
|
|
8001eba: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->FTSR = temp;
|
|
8001ebc: 4a29 ldr r2, [pc, #164] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001ebe: 69bb ldr r3, [r7, #24]
|
|
8001ec0: 60d3 str r3, [r2, #12]
|
|
|
|
temp = EXTI->EMR;
|
|
8001ec2: 4b28 ldr r3, [pc, #160] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001ec4: 685b ldr r3, [r3, #4]
|
|
8001ec6: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001ec8: 693b ldr r3, [r7, #16]
|
|
8001eca: 43db mvns r3, r3
|
|
8001ecc: 69ba ldr r2, [r7, #24]
|
|
8001ece: 4013 ands r3, r2
|
|
8001ed0: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
|
|
8001ed2: 683b ldr r3, [r7, #0]
|
|
8001ed4: 685b ldr r3, [r3, #4]
|
|
8001ed6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8001eda: 2b00 cmp r3, #0
|
|
8001edc: d003 beq.n 8001ee6 <HAL_GPIO_Init+0x2d6>
|
|
{
|
|
temp |= iocurrent;
|
|
8001ede: 69ba ldr r2, [r7, #24]
|
|
8001ee0: 693b ldr r3, [r7, #16]
|
|
8001ee2: 4313 orrs r3, r2
|
|
8001ee4: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->EMR = temp;
|
|
8001ee6: 4a1f ldr r2, [pc, #124] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001ee8: 69bb ldr r3, [r7, #24]
|
|
8001eea: 6053 str r3, [r2, #4]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->IMR;
|
|
8001eec: 4b1d ldr r3, [pc, #116] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001eee: 681b ldr r3, [r3, #0]
|
|
8001ef0: 61bb str r3, [r7, #24]
|
|
temp &= ~((uint32_t)iocurrent);
|
|
8001ef2: 693b ldr r3, [r7, #16]
|
|
8001ef4: 43db mvns r3, r3
|
|
8001ef6: 69ba ldr r2, [r7, #24]
|
|
8001ef8: 4013 ands r3, r2
|
|
8001efa: 61bb str r3, [r7, #24]
|
|
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
|
|
8001efc: 683b ldr r3, [r7, #0]
|
|
8001efe: 685b ldr r3, [r3, #4]
|
|
8001f00: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8001f04: 2b00 cmp r3, #0
|
|
8001f06: d003 beq.n 8001f10 <HAL_GPIO_Init+0x300>
|
|
{
|
|
temp |= iocurrent;
|
|
8001f08: 69ba ldr r2, [r7, #24]
|
|
8001f0a: 693b ldr r3, [r7, #16]
|
|
8001f0c: 4313 orrs r3, r2
|
|
8001f0e: 61bb str r3, [r7, #24]
|
|
}
|
|
EXTI->IMR = temp;
|
|
8001f10: 4a14 ldr r2, [pc, #80] @ (8001f64 <HAL_GPIO_Init+0x354>)
|
|
8001f12: 69bb ldr r3, [r7, #24]
|
|
8001f14: 6013 str r3, [r2, #0]
|
|
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
8001f16: 69fb ldr r3, [r7, #28]
|
|
8001f18: 3301 adds r3, #1
|
|
8001f1a: 61fb str r3, [r7, #28]
|
|
8001f1c: 69fb ldr r3, [r7, #28]
|
|
8001f1e: 2b0f cmp r3, #15
|
|
8001f20: f67f ae84 bls.w 8001c2c <HAL_GPIO_Init+0x1c>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
8001f24: bf00 nop
|
|
8001f26: bf00 nop
|
|
8001f28: 3724 adds r7, #36 @ 0x24
|
|
8001f2a: 46bd mov sp, r7
|
|
8001f2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f30: 4770 bx lr
|
|
8001f32: bf00 nop
|
|
8001f34: 40023800 .word 0x40023800
|
|
8001f38: 40013800 .word 0x40013800
|
|
8001f3c: 40020000 .word 0x40020000
|
|
8001f40: 40020400 .word 0x40020400
|
|
8001f44: 40020800 .word 0x40020800
|
|
8001f48: 40020c00 .word 0x40020c00
|
|
8001f4c: 40021000 .word 0x40021000
|
|
8001f50: 40021400 .word 0x40021400
|
|
8001f54: 40021800 .word 0x40021800
|
|
8001f58: 40021c00 .word 0x40021c00
|
|
8001f5c: 40022000 .word 0x40022000
|
|
8001f60: 40022400 .word 0x40022400
|
|
8001f64: 40013c00 .word 0x40013c00
|
|
|
|
08001f68 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8001f68: b480 push {r7}
|
|
8001f6a: b083 sub sp, #12
|
|
8001f6c: af00 add r7, sp, #0
|
|
8001f6e: 6078 str r0, [r7, #4]
|
|
8001f70: 460b mov r3, r1
|
|
8001f72: 807b strh r3, [r7, #2]
|
|
8001f74: 4613 mov r3, r2
|
|
8001f76: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8001f78: 787b ldrb r3, [r7, #1]
|
|
8001f7a: 2b00 cmp r3, #0
|
|
8001f7c: d003 beq.n 8001f86 <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = GPIO_Pin;
|
|
8001f7e: 887a ldrh r2, [r7, #2]
|
|
8001f80: 687b ldr r3, [r7, #4]
|
|
8001f82: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
}
|
|
}
|
|
8001f84: e003 b.n 8001f8e <HAL_GPIO_WritePin+0x26>
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
|
|
8001f86: 887b ldrh r3, [r7, #2]
|
|
8001f88: 041a lsls r2, r3, #16
|
|
8001f8a: 687b ldr r3, [r7, #4]
|
|
8001f8c: 619a str r2, [r3, #24]
|
|
}
|
|
8001f8e: bf00 nop
|
|
8001f90: 370c adds r7, #12
|
|
8001f92: 46bd mov sp, r7
|
|
8001f94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f98: 4770 bx lr
|
|
|
|
08001f9a <HAL_GPIO_TogglePin>:
|
|
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
|
|
* @param GPIO_Pin Specifies the pins to be toggled.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
|
{
|
|
8001f9a: b480 push {r7}
|
|
8001f9c: b085 sub sp, #20
|
|
8001f9e: af00 add r7, sp, #0
|
|
8001fa0: 6078 str r0, [r7, #4]
|
|
8001fa2: 460b mov r3, r1
|
|
8001fa4: 807b strh r3, [r7, #2]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
/* get current Output Data Register value */
|
|
odr = GPIOx->ODR;
|
|
8001fa6: 687b ldr r3, [r7, #4]
|
|
8001fa8: 695b ldr r3, [r3, #20]
|
|
8001faa: 60fb str r3, [r7, #12]
|
|
|
|
/* Set selected pins that were at low level, and reset ones that were high */
|
|
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
|
8001fac: 887a ldrh r2, [r7, #2]
|
|
8001fae: 68fb ldr r3, [r7, #12]
|
|
8001fb0: 4013 ands r3, r2
|
|
8001fb2: 041a lsls r2, r3, #16
|
|
8001fb4: 68fb ldr r3, [r7, #12]
|
|
8001fb6: 43d9 mvns r1, r3
|
|
8001fb8: 887b ldrh r3, [r7, #2]
|
|
8001fba: 400b ands r3, r1
|
|
8001fbc: 431a orrs r2, r3
|
|
8001fbe: 687b ldr r3, [r7, #4]
|
|
8001fc0: 619a str r2, [r3, #24]
|
|
}
|
|
8001fc2: bf00 nop
|
|
8001fc4: 3714 adds r7, #20
|
|
8001fc6: 46bd mov sp, r7
|
|
8001fc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001fcc: 4770 bx lr
|
|
|
|
08001fce <HAL_HCD_IRQHandler>:
|
|
* @brief Handle HCD interrupt request.
|
|
* @param hhcd HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8001fce: b580 push {r7, lr}
|
|
8001fd0: b086 sub sp, #24
|
|
8001fd2: af00 add r7, sp, #0
|
|
8001fd4: 6078 str r0, [r7, #4]
|
|
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8001fd6: 687b ldr r3, [r7, #4]
|
|
8001fd8: 681b ldr r3, [r3, #0]
|
|
8001fda: 613b str r3, [r7, #16]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8001fdc: 693b ldr r3, [r7, #16]
|
|
8001fde: 60fb str r3, [r7, #12]
|
|
uint32_t i;
|
|
uint32_t interrupt;
|
|
|
|
/* Ensure that we are in device mode */
|
|
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
|
|
8001fe0: 687b ldr r3, [r7, #4]
|
|
8001fe2: 681b ldr r3, [r3, #0]
|
|
8001fe4: 4618 mov r0, r3
|
|
8001fe6: f004 fab7 bl 8006558 <USB_GetMode>
|
|
8001fea: 4603 mov r3, r0
|
|
8001fec: 2b01 cmp r3, #1
|
|
8001fee: f040 80fb bne.w 80021e8 <HAL_HCD_IRQHandler+0x21a>
|
|
{
|
|
/* Avoid spurious interrupt */
|
|
if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
|
|
8001ff2: 687b ldr r3, [r7, #4]
|
|
8001ff4: 681b ldr r3, [r3, #0]
|
|
8001ff6: 4618 mov r0, r3
|
|
8001ff8: f004 fa7a bl 80064f0 <USB_ReadInterrupts>
|
|
8001ffc: 4603 mov r3, r0
|
|
8001ffe: 2b00 cmp r3, #0
|
|
8002000: f000 80f1 beq.w 80021e6 <HAL_HCD_IRQHandler+0x218>
|
|
{
|
|
return;
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
|
|
8002004: 687b ldr r3, [r7, #4]
|
|
8002006: 681b ldr r3, [r3, #0]
|
|
8002008: 4618 mov r0, r3
|
|
800200a: f004 fa71 bl 80064f0 <USB_ReadInterrupts>
|
|
800200e: 4603 mov r3, r0
|
|
8002010: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8002014: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
|
|
8002018: d104 bne.n 8002024 <HAL_HCD_IRQHandler+0x56>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
|
|
800201a: 687b ldr r3, [r7, #4]
|
|
800201c: 681b ldr r3, [r3, #0]
|
|
800201e: f44f 1200 mov.w r2, #2097152 @ 0x200000
|
|
8002022: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
|
|
8002024: 687b ldr r3, [r7, #4]
|
|
8002026: 681b ldr r3, [r3, #0]
|
|
8002028: 4618 mov r0, r3
|
|
800202a: f004 fa61 bl 80064f0 <USB_ReadInterrupts>
|
|
800202e: 4603 mov r3, r0
|
|
8002030: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002034: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8002038: d104 bne.n 8002044 <HAL_HCD_IRQHandler+0x76>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
|
|
800203a: 687b ldr r3, [r7, #4]
|
|
800203c: 681b ldr r3, [r3, #0]
|
|
800203e: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
8002042: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
|
|
8002044: 687b ldr r3, [r7, #4]
|
|
8002046: 681b ldr r3, [r3, #0]
|
|
8002048: 4618 mov r0, r3
|
|
800204a: f004 fa51 bl 80064f0 <USB_ReadInterrupts>
|
|
800204e: 4603 mov r3, r0
|
|
8002050: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8002054: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8002058: d104 bne.n 8002064 <HAL_HCD_IRQHandler+0x96>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
|
|
800205a: 687b ldr r3, [r7, #4]
|
|
800205c: 681b ldr r3, [r3, #0]
|
|
800205e: f04f 6280 mov.w r2, #67108864 @ 0x4000000
|
|
8002062: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
|
|
8002064: 687b ldr r3, [r7, #4]
|
|
8002066: 681b ldr r3, [r3, #0]
|
|
8002068: 4618 mov r0, r3
|
|
800206a: f004 fa41 bl 80064f0 <USB_ReadInterrupts>
|
|
800206e: 4603 mov r3, r0
|
|
8002070: f003 0302 and.w r3, r3, #2
|
|
8002074: 2b02 cmp r3, #2
|
|
8002076: d103 bne.n 8002080 <HAL_HCD_IRQHandler+0xb2>
|
|
{
|
|
/* Incorrect mode, acknowledge the interrupt */
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
|
|
8002078: 687b ldr r3, [r7, #4]
|
|
800207a: 681b ldr r3, [r3, #0]
|
|
800207c: 2202 movs r2, #2
|
|
800207e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Host Disconnect Interrupts */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
|
|
8002080: 687b ldr r3, [r7, #4]
|
|
8002082: 681b ldr r3, [r3, #0]
|
|
8002084: 4618 mov r0, r3
|
|
8002086: f004 fa33 bl 80064f0 <USB_ReadInterrupts>
|
|
800208a: 4603 mov r3, r0
|
|
800208c: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8002090: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8002094: d120 bne.n 80020d8 <HAL_HCD_IRQHandler+0x10a>
|
|
{
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
|
|
8002096: 687b ldr r3, [r7, #4]
|
|
8002098: 681b ldr r3, [r3, #0]
|
|
800209a: f04f 5200 mov.w r2, #536870912 @ 0x20000000
|
|
800209e: 615a str r2, [r3, #20]
|
|
|
|
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
|
|
80020a0: 68fb ldr r3, [r7, #12]
|
|
80020a2: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
80020a6: 681b ldr r3, [r3, #0]
|
|
80020a8: f003 0301 and.w r3, r3, #1
|
|
80020ac: 2b00 cmp r3, #0
|
|
80020ae: d113 bne.n 80020d8 <HAL_HCD_IRQHandler+0x10a>
|
|
{
|
|
/* Flush USB Fifo */
|
|
(void)USB_FlushTxFifo(USBx, 0x10U);
|
|
80020b0: 2110 movs r1, #16
|
|
80020b2: 6938 ldr r0, [r7, #16]
|
|
80020b4: f004 f964 bl 8006380 <USB_FlushTxFifo>
|
|
(void)USB_FlushRxFifo(USBx);
|
|
80020b8: 6938 ldr r0, [r7, #16]
|
|
80020ba: f004 f993 bl 80063e4 <USB_FlushRxFifo>
|
|
|
|
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
|
|
80020be: 687b ldr r3, [r7, #4]
|
|
80020c0: 7a5b ldrb r3, [r3, #9]
|
|
80020c2: 2b02 cmp r3, #2
|
|
80020c4: d105 bne.n 80020d2 <HAL_HCD_IRQHandler+0x104>
|
|
{
|
|
/* Restore FS Clock */
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
|
|
80020c6: 687b ldr r3, [r7, #4]
|
|
80020c8: 681b ldr r3, [r3, #0]
|
|
80020ca: 2101 movs r1, #1
|
|
80020cc: 4618 mov r0, r3
|
|
80020ce: f004 fa51 bl 8006574 <USB_InitFSLSPClkSel>
|
|
|
|
/* Handle Host Port Disconnect Interrupt */
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->DisconnectCallback(hhcd);
|
|
#else
|
|
HAL_HCD_Disconnect_Callback(hhcd);
|
|
80020d2: 6878 ldr r0, [r7, #4]
|
|
80020d4: f005 fe20 bl 8007d18 <HAL_HCD_Disconnect_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Handle Host Port Interrupts */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
|
|
80020d8: 687b ldr r3, [r7, #4]
|
|
80020da: 681b ldr r3, [r3, #0]
|
|
80020dc: 4618 mov r0, r3
|
|
80020de: f004 fa07 bl 80064f0 <USB_ReadInterrupts>
|
|
80020e2: 4603 mov r3, r0
|
|
80020e4: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
|
|
80020e8: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80020ec: d102 bne.n 80020f4 <HAL_HCD_IRQHandler+0x126>
|
|
{
|
|
HCD_Port_IRQHandler(hhcd);
|
|
80020ee: 6878 ldr r0, [r7, #4]
|
|
80020f0: f001 fca1 bl 8003a36 <HCD_Port_IRQHandler>
|
|
}
|
|
|
|
/* Handle Host SOF Interrupt */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
|
|
80020f4: 687b ldr r3, [r7, #4]
|
|
80020f6: 681b ldr r3, [r3, #0]
|
|
80020f8: 4618 mov r0, r3
|
|
80020fa: f004 f9f9 bl 80064f0 <USB_ReadInterrupts>
|
|
80020fe: 4603 mov r3, r0
|
|
8002100: f003 0308 and.w r3, r3, #8
|
|
8002104: 2b08 cmp r3, #8
|
|
8002106: d106 bne.n 8002116 <HAL_HCD_IRQHandler+0x148>
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->SOFCallback(hhcd);
|
|
#else
|
|
HAL_HCD_SOF_Callback(hhcd);
|
|
8002108: 6878 ldr r0, [r7, #4]
|
|
800210a: f005 fde9 bl 8007ce0 <HAL_HCD_SOF_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
|
|
800210e: 687b ldr r3, [r7, #4]
|
|
8002110: 681b ldr r3, [r3, #0]
|
|
8002112: 2208 movs r2, #8
|
|
8002114: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Host channel Interrupt */
|
|
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
|
|
8002116: 687b ldr r3, [r7, #4]
|
|
8002118: 681b ldr r3, [r3, #0]
|
|
800211a: 4618 mov r0, r3
|
|
800211c: f004 f9e8 bl 80064f0 <USB_ReadInterrupts>
|
|
8002120: 4603 mov r3, r0
|
|
8002122: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8002126: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
800212a: d139 bne.n 80021a0 <HAL_HCD_IRQHandler+0x1d2>
|
|
{
|
|
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
|
|
800212c: 687b ldr r3, [r7, #4]
|
|
800212e: 681b ldr r3, [r3, #0]
|
|
8002130: 4618 mov r0, r3
|
|
8002132: f004 fa5c bl 80065ee <USB_HC_ReadInterrupt>
|
|
8002136: 60b8 str r0, [r7, #8]
|
|
for (i = 0U; i < hhcd->Init.Host_channels; i++)
|
|
8002138: 2300 movs r3, #0
|
|
800213a: 617b str r3, [r7, #20]
|
|
800213c: e025 b.n 800218a <HAL_HCD_IRQHandler+0x1bc>
|
|
{
|
|
if ((interrupt & (1UL << (i & 0xFU))) != 0U)
|
|
800213e: 697b ldr r3, [r7, #20]
|
|
8002140: f003 030f and.w r3, r3, #15
|
|
8002144: 68ba ldr r2, [r7, #8]
|
|
8002146: fa22 f303 lsr.w r3, r2, r3
|
|
800214a: f003 0301 and.w r3, r3, #1
|
|
800214e: 2b00 cmp r3, #0
|
|
8002150: d018 beq.n 8002184 <HAL_HCD_IRQHandler+0x1b6>
|
|
{
|
|
if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
|
|
8002152: 697b ldr r3, [r7, #20]
|
|
8002154: 015a lsls r2, r3, #5
|
|
8002156: 68fb ldr r3, [r7, #12]
|
|
8002158: 4413 add r3, r2
|
|
800215a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800215e: 681b ldr r3, [r3, #0]
|
|
8002160: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
8002164: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8002168: d106 bne.n 8002178 <HAL_HCD_IRQHandler+0x1aa>
|
|
{
|
|
HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
|
|
800216a: 697b ldr r3, [r7, #20]
|
|
800216c: b2db uxtb r3, r3
|
|
800216e: 4619 mov r1, r3
|
|
8002170: 6878 ldr r0, [r7, #4]
|
|
8002172: f000 f859 bl 8002228 <HCD_HC_IN_IRQHandler>
|
|
8002176: e005 b.n 8002184 <HAL_HCD_IRQHandler+0x1b6>
|
|
}
|
|
else
|
|
{
|
|
HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
|
|
8002178: 697b ldr r3, [r7, #20]
|
|
800217a: b2db uxtb r3, r3
|
|
800217c: 4619 mov r1, r3
|
|
800217e: 6878 ldr r0, [r7, #4]
|
|
8002180: f000 febb bl 8002efa <HCD_HC_OUT_IRQHandler>
|
|
for (i = 0U; i < hhcd->Init.Host_channels; i++)
|
|
8002184: 697b ldr r3, [r7, #20]
|
|
8002186: 3301 adds r3, #1
|
|
8002188: 617b str r3, [r7, #20]
|
|
800218a: 687b ldr r3, [r7, #4]
|
|
800218c: 795b ldrb r3, [r3, #5]
|
|
800218e: 461a mov r2, r3
|
|
8002190: 697b ldr r3, [r7, #20]
|
|
8002192: 4293 cmp r3, r2
|
|
8002194: d3d3 bcc.n 800213e <HAL_HCD_IRQHandler+0x170>
|
|
}
|
|
}
|
|
}
|
|
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
|
|
8002196: 687b ldr r3, [r7, #4]
|
|
8002198: 681b ldr r3, [r3, #0]
|
|
800219a: f04f 7200 mov.w r2, #33554432 @ 0x2000000
|
|
800219e: 615a str r2, [r3, #20]
|
|
}
|
|
|
|
/* Handle Rx Queue Level Interrupts */
|
|
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
|
|
80021a0: 687b ldr r3, [r7, #4]
|
|
80021a2: 681b ldr r3, [r3, #0]
|
|
80021a4: 4618 mov r0, r3
|
|
80021a6: f004 f9a3 bl 80064f0 <USB_ReadInterrupts>
|
|
80021aa: 4603 mov r3, r0
|
|
80021ac: f003 0310 and.w r3, r3, #16
|
|
80021b0: 2b10 cmp r3, #16
|
|
80021b2: d101 bne.n 80021b8 <HAL_HCD_IRQHandler+0x1ea>
|
|
80021b4: 2301 movs r3, #1
|
|
80021b6: e000 b.n 80021ba <HAL_HCD_IRQHandler+0x1ec>
|
|
80021b8: 2300 movs r3, #0
|
|
80021ba: 2b00 cmp r3, #0
|
|
80021bc: d014 beq.n 80021e8 <HAL_HCD_IRQHandler+0x21a>
|
|
{
|
|
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
80021be: 687b ldr r3, [r7, #4]
|
|
80021c0: 681b ldr r3, [r3, #0]
|
|
80021c2: 699a ldr r2, [r3, #24]
|
|
80021c4: 687b ldr r3, [r7, #4]
|
|
80021c6: 681b ldr r3, [r3, #0]
|
|
80021c8: f022 0210 bic.w r2, r2, #16
|
|
80021cc: 619a str r2, [r3, #24]
|
|
|
|
HCD_RXQLVL_IRQHandler(hhcd);
|
|
80021ce: 6878 ldr r0, [r7, #4]
|
|
80021d0: f001 fb52 bl 8003878 <HCD_RXQLVL_IRQHandler>
|
|
|
|
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
|
|
80021d4: 687b ldr r3, [r7, #4]
|
|
80021d6: 681b ldr r3, [r3, #0]
|
|
80021d8: 699a ldr r2, [r3, #24]
|
|
80021da: 687b ldr r3, [r7, #4]
|
|
80021dc: 681b ldr r3, [r3, #0]
|
|
80021de: f042 0210 orr.w r2, r2, #16
|
|
80021e2: 619a str r2, [r3, #24]
|
|
80021e4: e000 b.n 80021e8 <HAL_HCD_IRQHandler+0x21a>
|
|
return;
|
|
80021e6: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
80021e8: 3718 adds r7, #24
|
|
80021ea: 46bd mov sp, r7
|
|
80021ec: bd80 pop {r7, pc}
|
|
|
|
080021ee <HAL_HCD_Stop>:
|
|
* @param hhcd HCD handle
|
|
* @retval HAL status
|
|
*/
|
|
|
|
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
80021ee: b580 push {r7, lr}
|
|
80021f0: b082 sub sp, #8
|
|
80021f2: af00 add r7, sp, #0
|
|
80021f4: 6078 str r0, [r7, #4]
|
|
__HAL_LOCK(hhcd);
|
|
80021f6: 687b ldr r3, [r7, #4]
|
|
80021f8: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4
|
|
80021fc: 2b01 cmp r3, #1
|
|
80021fe: d101 bne.n 8002204 <HAL_HCD_Stop+0x16>
|
|
8002200: 2302 movs r3, #2
|
|
8002202: e00d b.n 8002220 <HAL_HCD_Stop+0x32>
|
|
8002204: 687b ldr r3, [r7, #4]
|
|
8002206: 2201 movs r2, #1
|
|
8002208: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
(void)USB_StopHost(hhcd->Instance);
|
|
800220c: 687b ldr r3, [r7, #4]
|
|
800220e: 681b ldr r3, [r3, #0]
|
|
8002210: 4618 mov r0, r3
|
|
8002212: f004 fb1d bl 8006850 <USB_StopHost>
|
|
__HAL_UNLOCK(hhcd);
|
|
8002216: 687b ldr r3, [r7, #4]
|
|
8002218: 2200 movs r2, #0
|
|
800221a: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
|
|
|
|
return HAL_OK;
|
|
800221e: 2300 movs r3, #0
|
|
}
|
|
8002220: 4618 mov r0, r3
|
|
8002222: 3708 adds r7, #8
|
|
8002224: 46bd mov sp, r7
|
|
8002226: bd80 pop {r7, pc}
|
|
|
|
08002228 <HCD_HC_IN_IRQHandler>:
|
|
* @param chnum Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval none
|
|
*/
|
|
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|
{
|
|
8002228: b580 push {r7, lr}
|
|
800222a: b086 sub sp, #24
|
|
800222c: af00 add r7, sp, #0
|
|
800222e: 6078 str r0, [r7, #4]
|
|
8002230: 460b mov r3, r1
|
|
8002232: 70fb strb r3, [r7, #3]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8002234: 687b ldr r3, [r7, #4]
|
|
8002236: 681b ldr r3, [r3, #0]
|
|
8002238: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800223a: 697b ldr r3, [r7, #20]
|
|
800223c: 613b str r3, [r7, #16]
|
|
uint32_t tmpreg;
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
|
|
800223e: 687b ldr r3, [r7, #4]
|
|
8002240: 681b ldr r3, [r3, #0]
|
|
8002242: 78fa ldrb r2, [r7, #3]
|
|
8002244: 4611 mov r1, r2
|
|
8002246: 4618 mov r0, r3
|
|
8002248: f004 f965 bl 8006516 <USB_ReadChInterrupts>
|
|
800224c: 4603 mov r3, r0
|
|
800224e: f003 0304 and.w r3, r3, #4
|
|
8002252: 2b04 cmp r3, #4
|
|
8002254: d11a bne.n 800228c <HCD_HC_IN_IRQHandler+0x64>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
|
|
8002256: 78fb ldrb r3, [r7, #3]
|
|
8002258: 015a lsls r2, r3, #5
|
|
800225a: 693b ldr r3, [r7, #16]
|
|
800225c: 4413 add r3, r2
|
|
800225e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002262: 461a mov r2, r3
|
|
8002264: 2304 movs r3, #4
|
|
8002266: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8002268: 78fa ldrb r2, [r7, #3]
|
|
800226a: 6879 ldr r1, [r7, #4]
|
|
800226c: 4613 mov r3, r2
|
|
800226e: 011b lsls r3, r3, #4
|
|
8002270: 1a9b subs r3, r3, r2
|
|
8002272: 009b lsls r3, r3, #2
|
|
8002274: 440b add r3, r1
|
|
8002276: 334d adds r3, #77 @ 0x4d
|
|
8002278: 2207 movs r2, #7
|
|
800227a: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800227c: 687b ldr r3, [r7, #4]
|
|
800227e: 681b ldr r3, [r3, #0]
|
|
8002280: 78fa ldrb r2, [r7, #3]
|
|
8002282: 4611 mov r1, r2
|
|
8002284: 4618 mov r0, r3
|
|
8002286: f004 f9c3 bl 8006610 <USB_HC_Halt>
|
|
800228a: e09e b.n 80023ca <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
|
|
800228c: 687b ldr r3, [r7, #4]
|
|
800228e: 681b ldr r3, [r3, #0]
|
|
8002290: 78fa ldrb r2, [r7, #3]
|
|
8002292: 4611 mov r1, r2
|
|
8002294: 4618 mov r0, r3
|
|
8002296: f004 f93e bl 8006516 <USB_ReadChInterrupts>
|
|
800229a: 4603 mov r3, r0
|
|
800229c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80022a0: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80022a4: d11b bne.n 80022de <HCD_HC_IN_IRQHandler+0xb6>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
|
|
80022a6: 78fb ldrb r3, [r7, #3]
|
|
80022a8: 015a lsls r2, r3, #5
|
|
80022aa: 693b ldr r3, [r7, #16]
|
|
80022ac: 4413 add r3, r2
|
|
80022ae: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80022b2: 461a mov r2, r3
|
|
80022b4: f44f 7380 mov.w r3, #256 @ 0x100
|
|
80022b8: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_BBLERR;
|
|
80022ba: 78fa ldrb r2, [r7, #3]
|
|
80022bc: 6879 ldr r1, [r7, #4]
|
|
80022be: 4613 mov r3, r2
|
|
80022c0: 011b lsls r3, r3, #4
|
|
80022c2: 1a9b subs r3, r3, r2
|
|
80022c4: 009b lsls r3, r3, #2
|
|
80022c6: 440b add r3, r1
|
|
80022c8: 334d adds r3, #77 @ 0x4d
|
|
80022ca: 2208 movs r2, #8
|
|
80022cc: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 681b ldr r3, [r3, #0]
|
|
80022d2: 78fa ldrb r2, [r7, #3]
|
|
80022d4: 4611 mov r1, r2
|
|
80022d6: 4618 mov r0, r3
|
|
80022d8: f004 f99a bl 8006610 <USB_HC_Halt>
|
|
80022dc: e075 b.n 80023ca <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
|
|
80022de: 687b ldr r3, [r7, #4]
|
|
80022e0: 681b ldr r3, [r3, #0]
|
|
80022e2: 78fa ldrb r2, [r7, #3]
|
|
80022e4: 4611 mov r1, r2
|
|
80022e6: 4618 mov r0, r3
|
|
80022e8: f004 f915 bl 8006516 <USB_ReadChInterrupts>
|
|
80022ec: 4603 mov r3, r0
|
|
80022ee: f003 0308 and.w r3, r3, #8
|
|
80022f2: 2b08 cmp r3, #8
|
|
80022f4: d11a bne.n 800232c <HCD_HC_IN_IRQHandler+0x104>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
|
|
80022f6: 78fb ldrb r3, [r7, #3]
|
|
80022f8: 015a lsls r2, r3, #5
|
|
80022fa: 693b ldr r3, [r7, #16]
|
|
80022fc: 4413 add r3, r2
|
|
80022fe: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002302: 461a mov r2, r3
|
|
8002304: 2308 movs r3, #8
|
|
8002306: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_STALL;
|
|
8002308: 78fa ldrb r2, [r7, #3]
|
|
800230a: 6879 ldr r1, [r7, #4]
|
|
800230c: 4613 mov r3, r2
|
|
800230e: 011b lsls r3, r3, #4
|
|
8002310: 1a9b subs r3, r3, r2
|
|
8002312: 009b lsls r3, r3, #2
|
|
8002314: 440b add r3, r1
|
|
8002316: 334d adds r3, #77 @ 0x4d
|
|
8002318: 2206 movs r2, #6
|
|
800231a: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800231c: 687b ldr r3, [r7, #4]
|
|
800231e: 681b ldr r3, [r3, #0]
|
|
8002320: 78fa ldrb r2, [r7, #3]
|
|
8002322: 4611 mov r1, r2
|
|
8002324: 4618 mov r0, r3
|
|
8002326: f004 f973 bl 8006610 <USB_HC_Halt>
|
|
800232a: e04e b.n 80023ca <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
|
|
800232c: 687b ldr r3, [r7, #4]
|
|
800232e: 681b ldr r3, [r3, #0]
|
|
8002330: 78fa ldrb r2, [r7, #3]
|
|
8002332: 4611 mov r1, r2
|
|
8002334: 4618 mov r0, r3
|
|
8002336: f004 f8ee bl 8006516 <USB_ReadChInterrupts>
|
|
800233a: 4603 mov r3, r0
|
|
800233c: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8002340: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8002344: d11b bne.n 800237e <HCD_HC_IN_IRQHandler+0x156>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
|
|
8002346: 78fb ldrb r3, [r7, #3]
|
|
8002348: 015a lsls r2, r3, #5
|
|
800234a: 693b ldr r3, [r7, #16]
|
|
800234c: 4413 add r3, r2
|
|
800234e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002352: 461a mov r2, r3
|
|
8002354: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8002358: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_DATATGLERR;
|
|
800235a: 78fa ldrb r2, [r7, #3]
|
|
800235c: 6879 ldr r1, [r7, #4]
|
|
800235e: 4613 mov r3, r2
|
|
8002360: 011b lsls r3, r3, #4
|
|
8002362: 1a9b subs r3, r3, r2
|
|
8002364: 009b lsls r3, r3, #2
|
|
8002366: 440b add r3, r1
|
|
8002368: 334d adds r3, #77 @ 0x4d
|
|
800236a: 2209 movs r2, #9
|
|
800236c: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800236e: 687b ldr r3, [r7, #4]
|
|
8002370: 681b ldr r3, [r3, #0]
|
|
8002372: 78fa ldrb r2, [r7, #3]
|
|
8002374: 4611 mov r1, r2
|
|
8002376: 4618 mov r0, r3
|
|
8002378: f004 f94a bl 8006610 <USB_HC_Halt>
|
|
800237c: e025 b.n 80023ca <HCD_HC_IN_IRQHandler+0x1a2>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
|
|
800237e: 687b ldr r3, [r7, #4]
|
|
8002380: 681b ldr r3, [r3, #0]
|
|
8002382: 78fa ldrb r2, [r7, #3]
|
|
8002384: 4611 mov r1, r2
|
|
8002386: 4618 mov r0, r3
|
|
8002388: f004 f8c5 bl 8006516 <USB_ReadChInterrupts>
|
|
800238c: 4603 mov r3, r0
|
|
800238e: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8002392: 2b80 cmp r3, #128 @ 0x80
|
|
8002394: d119 bne.n 80023ca <HCD_HC_IN_IRQHandler+0x1a2>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
|
|
8002396: 78fb ldrb r3, [r7, #3]
|
|
8002398: 015a lsls r2, r3, #5
|
|
800239a: 693b ldr r3, [r7, #16]
|
|
800239c: 4413 add r3, r2
|
|
800239e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80023a2: 461a mov r2, r3
|
|
80023a4: 2380 movs r3, #128 @ 0x80
|
|
80023a6: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
80023a8: 78fa ldrb r2, [r7, #3]
|
|
80023aa: 6879 ldr r1, [r7, #4]
|
|
80023ac: 4613 mov r3, r2
|
|
80023ae: 011b lsls r3, r3, #4
|
|
80023b0: 1a9b subs r3, r3, r2
|
|
80023b2: 009b lsls r3, r3, #2
|
|
80023b4: 440b add r3, r1
|
|
80023b6: 334d adds r3, #77 @ 0x4d
|
|
80023b8: 2207 movs r2, #7
|
|
80023ba: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80023bc: 687b ldr r3, [r7, #4]
|
|
80023be: 681b ldr r3, [r3, #0]
|
|
80023c0: 78fa ldrb r2, [r7, #3]
|
|
80023c2: 4611 mov r1, r2
|
|
80023c4: 4618 mov r0, r3
|
|
80023c6: f004 f923 bl 8006610 <USB_HC_Halt>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
|
|
80023ca: 687b ldr r3, [r7, #4]
|
|
80023cc: 681b ldr r3, [r3, #0]
|
|
80023ce: 78fa ldrb r2, [r7, #3]
|
|
80023d0: 4611 mov r1, r2
|
|
80023d2: 4618 mov r0, r3
|
|
80023d4: f004 f89f bl 8006516 <USB_ReadChInterrupts>
|
|
80023d8: 4603 mov r3, r0
|
|
80023da: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80023de: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80023e2: d112 bne.n 800240a <HCD_HC_IN_IRQHandler+0x1e2>
|
|
{
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80023e4: 687b ldr r3, [r7, #4]
|
|
80023e6: 681b ldr r3, [r3, #0]
|
|
80023e8: 78fa ldrb r2, [r7, #3]
|
|
80023ea: 4611 mov r1, r2
|
|
80023ec: 4618 mov r0, r3
|
|
80023ee: f004 f90f bl 8006610 <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
|
|
80023f2: 78fb ldrb r3, [r7, #3]
|
|
80023f4: 015a lsls r2, r3, #5
|
|
80023f6: 693b ldr r3, [r7, #16]
|
|
80023f8: 4413 add r3, r2
|
|
80023fa: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80023fe: 461a mov r2, r3
|
|
8002400: f44f 7300 mov.w r3, #512 @ 0x200
|
|
8002404: 6093 str r3, [r2, #8]
|
|
8002406: f000 bd75 b.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
|
|
800240a: 687b ldr r3, [r7, #4]
|
|
800240c: 681b ldr r3, [r3, #0]
|
|
800240e: 78fa ldrb r2, [r7, #3]
|
|
8002410: 4611 mov r1, r2
|
|
8002412: 4618 mov r0, r3
|
|
8002414: f004 f87f bl 8006516 <USB_ReadChInterrupts>
|
|
8002418: 4603 mov r3, r0
|
|
800241a: f003 0301 and.w r3, r3, #1
|
|
800241e: 2b01 cmp r3, #1
|
|
8002420: f040 8128 bne.w 8002674 <HCD_HC_IN_IRQHandler+0x44c>
|
|
{
|
|
/* Clear any pending ACK IT */
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
8002424: 78fb ldrb r3, [r7, #3]
|
|
8002426: 015a lsls r2, r3, #5
|
|
8002428: 693b ldr r3, [r7, #16]
|
|
800242a: 4413 add r3, r2
|
|
800242c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002430: 461a mov r2, r3
|
|
8002432: 2320 movs r3, #32
|
|
8002434: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8002436: 78fa ldrb r2, [r7, #3]
|
|
8002438: 6879 ldr r1, [r7, #4]
|
|
800243a: 4613 mov r3, r2
|
|
800243c: 011b lsls r3, r3, #4
|
|
800243e: 1a9b subs r3, r3, r2
|
|
8002440: 009b lsls r3, r3, #2
|
|
8002442: 440b add r3, r1
|
|
8002444: 331b adds r3, #27
|
|
8002446: 781b ldrb r3, [r3, #0]
|
|
8002448: 2b01 cmp r3, #1
|
|
800244a: d119 bne.n 8002480 <HCD_HC_IN_IRQHandler+0x258>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
800244c: 78fa ldrb r2, [r7, #3]
|
|
800244e: 6879 ldr r1, [r7, #4]
|
|
8002450: 4613 mov r3, r2
|
|
8002452: 011b lsls r3, r3, #4
|
|
8002454: 1a9b subs r3, r3, r2
|
|
8002456: 009b lsls r3, r3, #2
|
|
8002458: 440b add r3, r1
|
|
800245a: 331b adds r3, #27
|
|
800245c: 2200 movs r2, #0
|
|
800245e: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8002460: 78fb ldrb r3, [r7, #3]
|
|
8002462: 015a lsls r2, r3, #5
|
|
8002464: 693b ldr r3, [r7, #16]
|
|
8002466: 4413 add r3, r2
|
|
8002468: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800246c: 685b ldr r3, [r3, #4]
|
|
800246e: 78fa ldrb r2, [r7, #3]
|
|
8002470: 0151 lsls r1, r2, #5
|
|
8002472: 693a ldr r2, [r7, #16]
|
|
8002474: 440a add r2, r1
|
|
8002476: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800247a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800247e: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
if (hhcd->Init.dma_enable != 0U)
|
|
8002480: 687b ldr r3, [r7, #4]
|
|
8002482: 799b ldrb r3, [r3, #6]
|
|
8002484: 2b00 cmp r3, #0
|
|
8002486: d01b beq.n 80024c0 <HCD_HC_IN_IRQHandler+0x298>
|
|
{
|
|
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
|
|
8002488: 78fa ldrb r2, [r7, #3]
|
|
800248a: 6879 ldr r1, [r7, #4]
|
|
800248c: 4613 mov r3, r2
|
|
800248e: 011b lsls r3, r3, #4
|
|
8002490: 1a9b subs r3, r3, r2
|
|
8002492: 009b lsls r3, r3, #2
|
|
8002494: 440b add r3, r1
|
|
8002496: 3330 adds r3, #48 @ 0x30
|
|
8002498: 6819 ldr r1, [r3, #0]
|
|
800249a: 78fb ldrb r3, [r7, #3]
|
|
800249c: 015a lsls r2, r3, #5
|
|
800249e: 693b ldr r3, [r7, #16]
|
|
80024a0: 4413 add r3, r2
|
|
80024a2: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80024a6: 691b ldr r3, [r3, #16]
|
|
80024a8: f3c3 0312 ubfx r3, r3, #0, #19
|
|
80024ac: 78fa ldrb r2, [r7, #3]
|
|
80024ae: 1ac9 subs r1, r1, r3
|
|
80024b0: 6878 ldr r0, [r7, #4]
|
|
80024b2: 4613 mov r3, r2
|
|
80024b4: 011b lsls r3, r3, #4
|
|
80024b6: 1a9b subs r3, r3, r2
|
|
80024b8: 009b lsls r3, r3, #2
|
|
80024ba: 4403 add r3, r0
|
|
80024bc: 3338 adds r3, #56 @ 0x38
|
|
80024be: 6019 str r1, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].state = HC_XFRC;
|
|
80024c0: 78fa ldrb r2, [r7, #3]
|
|
80024c2: 6879 ldr r1, [r7, #4]
|
|
80024c4: 4613 mov r3, r2
|
|
80024c6: 011b lsls r3, r3, #4
|
|
80024c8: 1a9b subs r3, r3, r2
|
|
80024ca: 009b lsls r3, r3, #2
|
|
80024cc: 440b add r3, r1
|
|
80024ce: 334d adds r3, #77 @ 0x4d
|
|
80024d0: 2201 movs r2, #1
|
|
80024d2: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80024d4: 78fa ldrb r2, [r7, #3]
|
|
80024d6: 6879 ldr r1, [r7, #4]
|
|
80024d8: 4613 mov r3, r2
|
|
80024da: 011b lsls r3, r3, #4
|
|
80024dc: 1a9b subs r3, r3, r2
|
|
80024de: 009b lsls r3, r3, #2
|
|
80024e0: 440b add r3, r1
|
|
80024e2: 3344 adds r3, #68 @ 0x44
|
|
80024e4: 2200 movs r2, #0
|
|
80024e6: 601a str r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
|
|
80024e8: 78fb ldrb r3, [r7, #3]
|
|
80024ea: 015a lsls r2, r3, #5
|
|
80024ec: 693b ldr r3, [r7, #16]
|
|
80024ee: 4413 add r3, r2
|
|
80024f0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80024f4: 461a mov r2, r3
|
|
80024f6: 2301 movs r3, #1
|
|
80024f8: 6093 str r3, [r2, #8]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80024fa: 78fa ldrb r2, [r7, #3]
|
|
80024fc: 6879 ldr r1, [r7, #4]
|
|
80024fe: 4613 mov r3, r2
|
|
8002500: 011b lsls r3, r3, #4
|
|
8002502: 1a9b subs r3, r3, r2
|
|
8002504: 009b lsls r3, r3, #2
|
|
8002506: 440b add r3, r1
|
|
8002508: 3326 adds r3, #38 @ 0x26
|
|
800250a: 781b ldrb r3, [r3, #0]
|
|
800250c: 2b00 cmp r3, #0
|
|
800250e: d00a beq.n 8002526 <HCD_HC_IN_IRQHandler+0x2fe>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002510: 78fa ldrb r2, [r7, #3]
|
|
8002512: 6879 ldr r1, [r7, #4]
|
|
8002514: 4613 mov r3, r2
|
|
8002516: 011b lsls r3, r3, #4
|
|
8002518: 1a9b subs r3, r3, r2
|
|
800251a: 009b lsls r3, r3, #2
|
|
800251c: 440b add r3, r1
|
|
800251e: 3326 adds r3, #38 @ 0x26
|
|
8002520: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002522: 2b02 cmp r3, #2
|
|
8002524: d110 bne.n 8002548 <HCD_HC_IN_IRQHandler+0x320>
|
|
{
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002526: 687b ldr r3, [r7, #4]
|
|
8002528: 681b ldr r3, [r3, #0]
|
|
800252a: 78fa ldrb r2, [r7, #3]
|
|
800252c: 4611 mov r1, r2
|
|
800252e: 4618 mov r0, r3
|
|
8002530: f004 f86e bl 8006610 <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
8002534: 78fb ldrb r3, [r7, #3]
|
|
8002536: 015a lsls r2, r3, #5
|
|
8002538: 693b ldr r3, [r7, #16]
|
|
800253a: 4413 add r3, r2
|
|
800253c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002540: 461a mov r2, r3
|
|
8002542: 2310 movs r3, #16
|
|
8002544: 6093 str r3, [r2, #8]
|
|
8002546: e03d b.n 80025c4 <HCD_HC_IN_IRQHandler+0x39c>
|
|
}
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
|
|
8002548: 78fa ldrb r2, [r7, #3]
|
|
800254a: 6879 ldr r1, [r7, #4]
|
|
800254c: 4613 mov r3, r2
|
|
800254e: 011b lsls r3, r3, #4
|
|
8002550: 1a9b subs r3, r3, r2
|
|
8002552: 009b lsls r3, r3, #2
|
|
8002554: 440b add r3, r1
|
|
8002556: 3326 adds r3, #38 @ 0x26
|
|
8002558: 781b ldrb r3, [r3, #0]
|
|
800255a: 2b03 cmp r3, #3
|
|
800255c: d00a beq.n 8002574 <HCD_HC_IN_IRQHandler+0x34c>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
|
|
800255e: 78fa ldrb r2, [r7, #3]
|
|
8002560: 6879 ldr r1, [r7, #4]
|
|
8002562: 4613 mov r3, r2
|
|
8002564: 011b lsls r3, r3, #4
|
|
8002566: 1a9b subs r3, r3, r2
|
|
8002568: 009b lsls r3, r3, #2
|
|
800256a: 440b add r3, r1
|
|
800256c: 3326 adds r3, #38 @ 0x26
|
|
800256e: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
|
|
8002570: 2b01 cmp r3, #1
|
|
8002572: d127 bne.n 80025c4 <HCD_HC_IN_IRQHandler+0x39c>
|
|
{
|
|
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
|
|
8002574: 78fb ldrb r3, [r7, #3]
|
|
8002576: 015a lsls r2, r3, #5
|
|
8002578: 693b ldr r3, [r7, #16]
|
|
800257a: 4413 add r3, r2
|
|
800257c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002580: 681b ldr r3, [r3, #0]
|
|
8002582: 78fa ldrb r2, [r7, #3]
|
|
8002584: 0151 lsls r1, r2, #5
|
|
8002586: 693a ldr r2, [r7, #16]
|
|
8002588: 440a add r2, r1
|
|
800258a: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800258e: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
|
|
8002592: 6013 str r3, [r2, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
8002594: 78fa ldrb r2, [r7, #3]
|
|
8002596: 6879 ldr r1, [r7, #4]
|
|
8002598: 4613 mov r3, r2
|
|
800259a: 011b lsls r3, r3, #4
|
|
800259c: 1a9b subs r3, r3, r2
|
|
800259e: 009b lsls r3, r3, #2
|
|
80025a0: 440b add r3, r1
|
|
80025a2: 334c adds r3, #76 @ 0x4c
|
|
80025a4: 2201 movs r2, #1
|
|
80025a6: 701a strb r2, [r3, #0]
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
80025a8: 78fa ldrb r2, [r7, #3]
|
|
80025aa: 6879 ldr r1, [r7, #4]
|
|
80025ac: 4613 mov r3, r2
|
|
80025ae: 011b lsls r3, r3, #4
|
|
80025b0: 1a9b subs r3, r3, r2
|
|
80025b2: 009b lsls r3, r3, #2
|
|
80025b4: 440b add r3, r1
|
|
80025b6: 334c adds r3, #76 @ 0x4c
|
|
80025b8: 781a ldrb r2, [r3, #0]
|
|
80025ba: 78fb ldrb r3, [r7, #3]
|
|
80025bc: 4619 mov r1, r3
|
|
80025be: 6878 ldr r0, [r7, #4]
|
|
80025c0: f005 fbb8 bl 8007d34 <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (hhcd->Init.dma_enable == 1U)
|
|
80025c4: 687b ldr r3, [r7, #4]
|
|
80025c6: 799b ldrb r3, [r3, #6]
|
|
80025c8: 2b01 cmp r3, #1
|
|
80025ca: d13b bne.n 8002644 <HCD_HC_IN_IRQHandler+0x41c>
|
|
{
|
|
if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
|
|
80025cc: 78fa ldrb r2, [r7, #3]
|
|
80025ce: 6879 ldr r1, [r7, #4]
|
|
80025d0: 4613 mov r3, r2
|
|
80025d2: 011b lsls r3, r3, #4
|
|
80025d4: 1a9b subs r3, r3, r2
|
|
80025d6: 009b lsls r3, r3, #2
|
|
80025d8: 440b add r3, r1
|
|
80025da: 3338 adds r3, #56 @ 0x38
|
|
80025dc: 6819 ldr r1, [r3, #0]
|
|
80025de: 78fa ldrb r2, [r7, #3]
|
|
80025e0: 6878 ldr r0, [r7, #4]
|
|
80025e2: 4613 mov r3, r2
|
|
80025e4: 011b lsls r3, r3, #4
|
|
80025e6: 1a9b subs r3, r3, r2
|
|
80025e8: 009b lsls r3, r3, #2
|
|
80025ea: 4403 add r3, r0
|
|
80025ec: 3328 adds r3, #40 @ 0x28
|
|
80025ee: 881b ldrh r3, [r3, #0]
|
|
80025f0: 440b add r3, r1
|
|
80025f2: 1e59 subs r1, r3, #1
|
|
80025f4: 78fa ldrb r2, [r7, #3]
|
|
80025f6: 6878 ldr r0, [r7, #4]
|
|
80025f8: 4613 mov r3, r2
|
|
80025fa: 011b lsls r3, r3, #4
|
|
80025fc: 1a9b subs r3, r3, r2
|
|
80025fe: 009b lsls r3, r3, #2
|
|
8002600: 4403 add r3, r0
|
|
8002602: 3328 adds r3, #40 @ 0x28
|
|
8002604: 881b ldrh r3, [r3, #0]
|
|
8002606: fbb1 f3f3 udiv r3, r1, r3
|
|
800260a: f003 0301 and.w r3, r3, #1
|
|
800260e: 2b00 cmp r3, #0
|
|
8002610: f000 8470 beq.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
8002614: 78fa ldrb r2, [r7, #3]
|
|
8002616: 6879 ldr r1, [r7, #4]
|
|
8002618: 4613 mov r3, r2
|
|
800261a: 011b lsls r3, r3, #4
|
|
800261c: 1a9b subs r3, r3, r2
|
|
800261e: 009b lsls r3, r3, #2
|
|
8002620: 440b add r3, r1
|
|
8002622: 333c adds r3, #60 @ 0x3c
|
|
8002624: 781b ldrb r3, [r3, #0]
|
|
8002626: 78fa ldrb r2, [r7, #3]
|
|
8002628: f083 0301 eor.w r3, r3, #1
|
|
800262c: b2d8 uxtb r0, r3
|
|
800262e: 6879 ldr r1, [r7, #4]
|
|
8002630: 4613 mov r3, r2
|
|
8002632: 011b lsls r3, r3, #4
|
|
8002634: 1a9b subs r3, r3, r2
|
|
8002636: 009b lsls r3, r3, #2
|
|
8002638: 440b add r3, r1
|
|
800263a: 333c adds r3, #60 @ 0x3c
|
|
800263c: 4602 mov r2, r0
|
|
800263e: 701a strb r2, [r3, #0]
|
|
8002640: f000 bc58 b.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
8002644: 78fa ldrb r2, [r7, #3]
|
|
8002646: 6879 ldr r1, [r7, #4]
|
|
8002648: 4613 mov r3, r2
|
|
800264a: 011b lsls r3, r3, #4
|
|
800264c: 1a9b subs r3, r3, r2
|
|
800264e: 009b lsls r3, r3, #2
|
|
8002650: 440b add r3, r1
|
|
8002652: 333c adds r3, #60 @ 0x3c
|
|
8002654: 781b ldrb r3, [r3, #0]
|
|
8002656: 78fa ldrb r2, [r7, #3]
|
|
8002658: f083 0301 eor.w r3, r3, #1
|
|
800265c: b2d8 uxtb r0, r3
|
|
800265e: 6879 ldr r1, [r7, #4]
|
|
8002660: 4613 mov r3, r2
|
|
8002662: 011b lsls r3, r3, #4
|
|
8002664: 1a9b subs r3, r3, r2
|
|
8002666: 009b lsls r3, r3, #2
|
|
8002668: 440b add r3, r1
|
|
800266a: 333c adds r3, #60 @ 0x3c
|
|
800266c: 4602 mov r2, r0
|
|
800266e: 701a strb r2, [r3, #0]
|
|
8002670: f000 bc40 b.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
|
|
8002674: 687b ldr r3, [r7, #4]
|
|
8002676: 681b ldr r3, [r3, #0]
|
|
8002678: 78fa ldrb r2, [r7, #3]
|
|
800267a: 4611 mov r1, r2
|
|
800267c: 4618 mov r0, r3
|
|
800267e: f003 ff4a bl 8006516 <USB_ReadChInterrupts>
|
|
8002682: 4603 mov r3, r0
|
|
8002684: f003 0320 and.w r3, r3, #32
|
|
8002688: 2b20 cmp r3, #32
|
|
800268a: d131 bne.n 80026f0 <HCD_HC_IN_IRQHandler+0x4c8>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
800268c: 78fb ldrb r3, [r7, #3]
|
|
800268e: 015a lsls r2, r3, #5
|
|
8002690: 693b ldr r3, [r7, #16]
|
|
8002692: 4413 add r3, r2
|
|
8002694: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002698: 461a mov r2, r3
|
|
800269a: 2320 movs r3, #32
|
|
800269c: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 1U)
|
|
800269e: 78fa ldrb r2, [r7, #3]
|
|
80026a0: 6879 ldr r1, [r7, #4]
|
|
80026a2: 4613 mov r3, r2
|
|
80026a4: 011b lsls r3, r3, #4
|
|
80026a6: 1a9b subs r3, r3, r2
|
|
80026a8: 009b lsls r3, r3, #2
|
|
80026aa: 440b add r3, r1
|
|
80026ac: 331a adds r3, #26
|
|
80026ae: 781b ldrb r3, [r3, #0]
|
|
80026b0: 2b01 cmp r3, #1
|
|
80026b2: f040 841f bne.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 1U;
|
|
80026b6: 78fa ldrb r2, [r7, #3]
|
|
80026b8: 6879 ldr r1, [r7, #4]
|
|
80026ba: 4613 mov r3, r2
|
|
80026bc: 011b lsls r3, r3, #4
|
|
80026be: 1a9b subs r3, r3, r2
|
|
80026c0: 009b lsls r3, r3, #2
|
|
80026c2: 440b add r3, r1
|
|
80026c4: 331b adds r3, #27
|
|
80026c6: 2201 movs r2, #1
|
|
80026c8: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
80026ca: 78fa ldrb r2, [r7, #3]
|
|
80026cc: 6879 ldr r1, [r7, #4]
|
|
80026ce: 4613 mov r3, r2
|
|
80026d0: 011b lsls r3, r3, #4
|
|
80026d2: 1a9b subs r3, r3, r2
|
|
80026d4: 009b lsls r3, r3, #2
|
|
80026d6: 440b add r3, r1
|
|
80026d8: 334d adds r3, #77 @ 0x4d
|
|
80026da: 2203 movs r2, #3
|
|
80026dc: 701a strb r2, [r3, #0]
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80026de: 687b ldr r3, [r7, #4]
|
|
80026e0: 681b ldr r3, [r3, #0]
|
|
80026e2: 78fa ldrb r2, [r7, #3]
|
|
80026e4: 4611 mov r1, r2
|
|
80026e6: 4618 mov r0, r3
|
|
80026e8: f003 ff92 bl 8006610 <USB_HC_Halt>
|
|
80026ec: f000 bc02 b.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
|
|
80026f0: 687b ldr r3, [r7, #4]
|
|
80026f2: 681b ldr r3, [r3, #0]
|
|
80026f4: 78fa ldrb r2, [r7, #3]
|
|
80026f6: 4611 mov r1, r2
|
|
80026f8: 4618 mov r0, r3
|
|
80026fa: f003 ff0c bl 8006516 <USB_ReadChInterrupts>
|
|
80026fe: 4603 mov r3, r0
|
|
8002700: f003 0302 and.w r3, r3, #2
|
|
8002704: 2b02 cmp r3, #2
|
|
8002706: f040 8305 bne.w 8002d14 <HCD_HC_IN_IRQHandler+0xaec>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
|
|
800270a: 78fb ldrb r3, [r7, #3]
|
|
800270c: 015a lsls r2, r3, #5
|
|
800270e: 693b ldr r3, [r7, #16]
|
|
8002710: 4413 add r3, r2
|
|
8002712: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002716: 461a mov r2, r3
|
|
8002718: 2302 movs r3, #2
|
|
800271a: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].state == HC_XFRC)
|
|
800271c: 78fa ldrb r2, [r7, #3]
|
|
800271e: 6879 ldr r1, [r7, #4]
|
|
8002720: 4613 mov r3, r2
|
|
8002722: 011b lsls r3, r3, #4
|
|
8002724: 1a9b subs r3, r3, r2
|
|
8002726: 009b lsls r3, r3, #2
|
|
8002728: 440b add r3, r1
|
|
800272a: 334d adds r3, #77 @ 0x4d
|
|
800272c: 781b ldrb r3, [r3, #0]
|
|
800272e: 2b01 cmp r3, #1
|
|
8002730: d114 bne.n 800275c <HCD_HC_IN_IRQHandler+0x534>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002732: 78fa ldrb r2, [r7, #3]
|
|
8002734: 6879 ldr r1, [r7, #4]
|
|
8002736: 4613 mov r3, r2
|
|
8002738: 011b lsls r3, r3, #4
|
|
800273a: 1a9b subs r3, r3, r2
|
|
800273c: 009b lsls r3, r3, #2
|
|
800273e: 440b add r3, r1
|
|
8002740: 334d adds r3, #77 @ 0x4d
|
|
8002742: 2202 movs r2, #2
|
|
8002744: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
8002746: 78fa ldrb r2, [r7, #3]
|
|
8002748: 6879 ldr r1, [r7, #4]
|
|
800274a: 4613 mov r3, r2
|
|
800274c: 011b lsls r3, r3, #4
|
|
800274e: 1a9b subs r3, r3, r2
|
|
8002750: 009b lsls r3, r3, #2
|
|
8002752: 440b add r3, r1
|
|
8002754: 334c adds r3, #76 @ 0x4c
|
|
8002756: 2201 movs r2, #1
|
|
8002758: 701a strb r2, [r3, #0]
|
|
800275a: e2cc b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_STALL)
|
|
800275c: 78fa ldrb r2, [r7, #3]
|
|
800275e: 6879 ldr r1, [r7, #4]
|
|
8002760: 4613 mov r3, r2
|
|
8002762: 011b lsls r3, r3, #4
|
|
8002764: 1a9b subs r3, r3, r2
|
|
8002766: 009b lsls r3, r3, #2
|
|
8002768: 440b add r3, r1
|
|
800276a: 334d adds r3, #77 @ 0x4d
|
|
800276c: 781b ldrb r3, [r3, #0]
|
|
800276e: 2b06 cmp r3, #6
|
|
8002770: d114 bne.n 800279c <HCD_HC_IN_IRQHandler+0x574>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002772: 78fa ldrb r2, [r7, #3]
|
|
8002774: 6879 ldr r1, [r7, #4]
|
|
8002776: 4613 mov r3, r2
|
|
8002778: 011b lsls r3, r3, #4
|
|
800277a: 1a9b subs r3, r3, r2
|
|
800277c: 009b lsls r3, r3, #2
|
|
800277e: 440b add r3, r1
|
|
8002780: 334d adds r3, #77 @ 0x4d
|
|
8002782: 2202 movs r2, #2
|
|
8002784: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_STALL;
|
|
8002786: 78fa ldrb r2, [r7, #3]
|
|
8002788: 6879 ldr r1, [r7, #4]
|
|
800278a: 4613 mov r3, r2
|
|
800278c: 011b lsls r3, r3, #4
|
|
800278e: 1a9b subs r3, r3, r2
|
|
8002790: 009b lsls r3, r3, #2
|
|
8002792: 440b add r3, r1
|
|
8002794: 334c adds r3, #76 @ 0x4c
|
|
8002796: 2205 movs r2, #5
|
|
8002798: 701a strb r2, [r3, #0]
|
|
800279a: e2ac b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
800279c: 78fa ldrb r2, [r7, #3]
|
|
800279e: 6879 ldr r1, [r7, #4]
|
|
80027a0: 4613 mov r3, r2
|
|
80027a2: 011b lsls r3, r3, #4
|
|
80027a4: 1a9b subs r3, r3, r2
|
|
80027a6: 009b lsls r3, r3, #2
|
|
80027a8: 440b add r3, r1
|
|
80027aa: 334d adds r3, #77 @ 0x4d
|
|
80027ac: 781b ldrb r3, [r3, #0]
|
|
80027ae: 2b07 cmp r3, #7
|
|
80027b0: d00b beq.n 80027ca <HCD_HC_IN_IRQHandler+0x5a2>
|
|
(hhcd->hc[chnum].state == HC_DATATGLERR))
|
|
80027b2: 78fa ldrb r2, [r7, #3]
|
|
80027b4: 6879 ldr r1, [r7, #4]
|
|
80027b6: 4613 mov r3, r2
|
|
80027b8: 011b lsls r3, r3, #4
|
|
80027ba: 1a9b subs r3, r3, r2
|
|
80027bc: 009b lsls r3, r3, #2
|
|
80027be: 440b add r3, r1
|
|
80027c0: 334d adds r3, #77 @ 0x4d
|
|
80027c2: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
80027c4: 2b09 cmp r3, #9
|
|
80027c6: f040 80a6 bne.w 8002916 <HCD_HC_IN_IRQHandler+0x6ee>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
80027ca: 78fa ldrb r2, [r7, #3]
|
|
80027cc: 6879 ldr r1, [r7, #4]
|
|
80027ce: 4613 mov r3, r2
|
|
80027d0: 011b lsls r3, r3, #4
|
|
80027d2: 1a9b subs r3, r3, r2
|
|
80027d4: 009b lsls r3, r3, #2
|
|
80027d6: 440b add r3, r1
|
|
80027d8: 334d adds r3, #77 @ 0x4d
|
|
80027da: 2202 movs r2, #2
|
|
80027dc: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
80027de: 78fa ldrb r2, [r7, #3]
|
|
80027e0: 6879 ldr r1, [r7, #4]
|
|
80027e2: 4613 mov r3, r2
|
|
80027e4: 011b lsls r3, r3, #4
|
|
80027e6: 1a9b subs r3, r3, r2
|
|
80027e8: 009b lsls r3, r3, #2
|
|
80027ea: 440b add r3, r1
|
|
80027ec: 3344 adds r3, #68 @ 0x44
|
|
80027ee: 681b ldr r3, [r3, #0]
|
|
80027f0: 1c59 adds r1, r3, #1
|
|
80027f2: 6878 ldr r0, [r7, #4]
|
|
80027f4: 4613 mov r3, r2
|
|
80027f6: 011b lsls r3, r3, #4
|
|
80027f8: 1a9b subs r3, r3, r2
|
|
80027fa: 009b lsls r3, r3, #2
|
|
80027fc: 4403 add r3, r0
|
|
80027fe: 3344 adds r3, #68 @ 0x44
|
|
8002800: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8002802: 78fa ldrb r2, [r7, #3]
|
|
8002804: 6879 ldr r1, [r7, #4]
|
|
8002806: 4613 mov r3, r2
|
|
8002808: 011b lsls r3, r3, #4
|
|
800280a: 1a9b subs r3, r3, r2
|
|
800280c: 009b lsls r3, r3, #2
|
|
800280e: 440b add r3, r1
|
|
8002810: 3344 adds r3, #68 @ 0x44
|
|
8002812: 681b ldr r3, [r3, #0]
|
|
8002814: 2b02 cmp r3, #2
|
|
8002816: d943 bls.n 80028a0 <HCD_HC_IN_IRQHandler+0x678>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002818: 78fa ldrb r2, [r7, #3]
|
|
800281a: 6879 ldr r1, [r7, #4]
|
|
800281c: 4613 mov r3, r2
|
|
800281e: 011b lsls r3, r3, #4
|
|
8002820: 1a9b subs r3, r3, r2
|
|
8002822: 009b lsls r3, r3, #2
|
|
8002824: 440b add r3, r1
|
|
8002826: 3344 adds r3, #68 @ 0x44
|
|
8002828: 2200 movs r2, #0
|
|
800282a: 601a str r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 1U)
|
|
800282c: 78fa ldrb r2, [r7, #3]
|
|
800282e: 6879 ldr r1, [r7, #4]
|
|
8002830: 4613 mov r3, r2
|
|
8002832: 011b lsls r3, r3, #4
|
|
8002834: 1a9b subs r3, r3, r2
|
|
8002836: 009b lsls r3, r3, #2
|
|
8002838: 440b add r3, r1
|
|
800283a: 331a adds r3, #26
|
|
800283c: 781b ldrb r3, [r3, #0]
|
|
800283e: 2b01 cmp r3, #1
|
|
8002840: d123 bne.n 800288a <HCD_HC_IN_IRQHandler+0x662>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8002842: 78fa ldrb r2, [r7, #3]
|
|
8002844: 6879 ldr r1, [r7, #4]
|
|
8002846: 4613 mov r3, r2
|
|
8002848: 011b lsls r3, r3, #4
|
|
800284a: 1a9b subs r3, r3, r2
|
|
800284c: 009b lsls r3, r3, #2
|
|
800284e: 440b add r3, r1
|
|
8002850: 331b adds r3, #27
|
|
8002852: 2200 movs r2, #0
|
|
8002854: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ep_ss_schedule = 0U;
|
|
8002856: 78fa ldrb r2, [r7, #3]
|
|
8002858: 6879 ldr r1, [r7, #4]
|
|
800285a: 4613 mov r3, r2
|
|
800285c: 011b lsls r3, r3, #4
|
|
800285e: 1a9b subs r3, r3, r2
|
|
8002860: 009b lsls r3, r3, #2
|
|
8002862: 440b add r3, r1
|
|
8002864: 331c adds r3, #28
|
|
8002866: 2200 movs r2, #0
|
|
8002868: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
800286a: 78fb ldrb r3, [r7, #3]
|
|
800286c: 015a lsls r2, r3, #5
|
|
800286e: 693b ldr r3, [r7, #16]
|
|
8002870: 4413 add r3, r2
|
|
8002872: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002876: 685b ldr r3, [r3, #4]
|
|
8002878: 78fa ldrb r2, [r7, #3]
|
|
800287a: 0151 lsls r1, r2, #5
|
|
800287c: 693a ldr r2, [r7, #16]
|
|
800287e: 440a add r2, r1
|
|
8002880: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002884: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002888: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
800288a: 78fa ldrb r2, [r7, #3]
|
|
800288c: 6879 ldr r1, [r7, #4]
|
|
800288e: 4613 mov r3, r2
|
|
8002890: 011b lsls r3, r3, #4
|
|
8002892: 1a9b subs r3, r3, r2
|
|
8002894: 009b lsls r3, r3, #2
|
|
8002896: 440b add r3, r1
|
|
8002898: 334c adds r3, #76 @ 0x4c
|
|
800289a: 2204 movs r2, #4
|
|
800289c: 701a strb r2, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
800289e: e229 b.n 8002cf4 <HCD_HC_IN_IRQHandler+0xacc>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
80028a0: 78fa ldrb r2, [r7, #3]
|
|
80028a2: 6879 ldr r1, [r7, #4]
|
|
80028a4: 4613 mov r3, r2
|
|
80028a6: 011b lsls r3, r3, #4
|
|
80028a8: 1a9b subs r3, r3, r2
|
|
80028aa: 009b lsls r3, r3, #2
|
|
80028ac: 440b add r3, r1
|
|
80028ae: 334c adds r3, #76 @ 0x4c
|
|
80028b0: 2202 movs r2, #2
|
|
80028b2: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80028b4: 78fa ldrb r2, [r7, #3]
|
|
80028b6: 6879 ldr r1, [r7, #4]
|
|
80028b8: 4613 mov r3, r2
|
|
80028ba: 011b lsls r3, r3, #4
|
|
80028bc: 1a9b subs r3, r3, r2
|
|
80028be: 009b lsls r3, r3, #2
|
|
80028c0: 440b add r3, r1
|
|
80028c2: 3326 adds r3, #38 @ 0x26
|
|
80028c4: 781b ldrb r3, [r3, #0]
|
|
80028c6: 2b00 cmp r3, #0
|
|
80028c8: d00b beq.n 80028e2 <HCD_HC_IN_IRQHandler+0x6ba>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
80028ca: 78fa ldrb r2, [r7, #3]
|
|
80028cc: 6879 ldr r1, [r7, #4]
|
|
80028ce: 4613 mov r3, r2
|
|
80028d0: 011b lsls r3, r3, #4
|
|
80028d2: 1a9b subs r3, r3, r2
|
|
80028d4: 009b lsls r3, r3, #2
|
|
80028d6: 440b add r3, r1
|
|
80028d8: 3326 adds r3, #38 @ 0x26
|
|
80028da: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
80028dc: 2b02 cmp r3, #2
|
|
80028de: f040 8209 bne.w 8002cf4 <HCD_HC_IN_IRQHandler+0xacc>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
80028e2: 78fb ldrb r3, [r7, #3]
|
|
80028e4: 015a lsls r2, r3, #5
|
|
80028e6: 693b ldr r3, [r7, #16]
|
|
80028e8: 4413 add r3, r2
|
|
80028ea: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80028ee: 681b ldr r3, [r3, #0]
|
|
80028f0: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
80028f2: 68fb ldr r3, [r7, #12]
|
|
80028f4: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
80028f8: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
80028fa: 68fb ldr r3, [r7, #12]
|
|
80028fc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8002900: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8002902: 78fb ldrb r3, [r7, #3]
|
|
8002904: 015a lsls r2, r3, #5
|
|
8002906: 693b ldr r3, [r7, #16]
|
|
8002908: 4413 add r3, r2
|
|
800290a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800290e: 461a mov r2, r3
|
|
8002910: 68fb ldr r3, [r7, #12]
|
|
8002912: 6013 str r3, [r2, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8002914: e1ee b.n 8002cf4 <HCD_HC_IN_IRQHandler+0xacc>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NYET)
|
|
8002916: 78fa ldrb r2, [r7, #3]
|
|
8002918: 6879 ldr r1, [r7, #4]
|
|
800291a: 4613 mov r3, r2
|
|
800291c: 011b lsls r3, r3, #4
|
|
800291e: 1a9b subs r3, r3, r2
|
|
8002920: 009b lsls r3, r3, #2
|
|
8002922: 440b add r3, r1
|
|
8002924: 334d adds r3, #77 @ 0x4d
|
|
8002926: 781b ldrb r3, [r3, #0]
|
|
8002928: 2b05 cmp r3, #5
|
|
800292a: f040 80c8 bne.w 8002abe <HCD_HC_IN_IRQHandler+0x896>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
800292e: 78fa ldrb r2, [r7, #3]
|
|
8002930: 6879 ldr r1, [r7, #4]
|
|
8002932: 4613 mov r3, r2
|
|
8002934: 011b lsls r3, r3, #4
|
|
8002936: 1a9b subs r3, r3, r2
|
|
8002938: 009b lsls r3, r3, #2
|
|
800293a: 440b add r3, r1
|
|
800293c: 334d adds r3, #77 @ 0x4d
|
|
800293e: 2202 movs r2, #2
|
|
8002940: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8002942: 78fa ldrb r2, [r7, #3]
|
|
8002944: 6879 ldr r1, [r7, #4]
|
|
8002946: 4613 mov r3, r2
|
|
8002948: 011b lsls r3, r3, #4
|
|
800294a: 1a9b subs r3, r3, r2
|
|
800294c: 009b lsls r3, r3, #2
|
|
800294e: 440b add r3, r1
|
|
8002950: 331b adds r3, #27
|
|
8002952: 781b ldrb r3, [r3, #0]
|
|
8002954: 2b01 cmp r3, #1
|
|
8002956: f040 81ce bne.w 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
|
|
800295a: 78fa ldrb r2, [r7, #3]
|
|
800295c: 6879 ldr r1, [r7, #4]
|
|
800295e: 4613 mov r3, r2
|
|
8002960: 011b lsls r3, r3, #4
|
|
8002962: 1a9b subs r3, r3, r2
|
|
8002964: 009b lsls r3, r3, #2
|
|
8002966: 440b add r3, r1
|
|
8002968: 3326 adds r3, #38 @ 0x26
|
|
800296a: 781b ldrb r3, [r3, #0]
|
|
800296c: 2b03 cmp r3, #3
|
|
800296e: d16b bne.n 8002a48 <HCD_HC_IN_IRQHandler+0x820>
|
|
{
|
|
hhcd->hc[chnum].NyetErrCnt++;
|
|
8002970: 78fa ldrb r2, [r7, #3]
|
|
8002972: 6879 ldr r1, [r7, #4]
|
|
8002974: 4613 mov r3, r2
|
|
8002976: 011b lsls r3, r3, #4
|
|
8002978: 1a9b subs r3, r3, r2
|
|
800297a: 009b lsls r3, r3, #2
|
|
800297c: 440b add r3, r1
|
|
800297e: 3348 adds r3, #72 @ 0x48
|
|
8002980: 681b ldr r3, [r3, #0]
|
|
8002982: 1c59 adds r1, r3, #1
|
|
8002984: 6878 ldr r0, [r7, #4]
|
|
8002986: 4613 mov r3, r2
|
|
8002988: 011b lsls r3, r3, #4
|
|
800298a: 1a9b subs r3, r3, r2
|
|
800298c: 009b lsls r3, r3, #2
|
|
800298e: 4403 add r3, r0
|
|
8002990: 3348 adds r3, #72 @ 0x48
|
|
8002992: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].NyetErrCnt > 2U)
|
|
8002994: 78fa ldrb r2, [r7, #3]
|
|
8002996: 6879 ldr r1, [r7, #4]
|
|
8002998: 4613 mov r3, r2
|
|
800299a: 011b lsls r3, r3, #4
|
|
800299c: 1a9b subs r3, r3, r2
|
|
800299e: 009b lsls r3, r3, #2
|
|
80029a0: 440b add r3, r1
|
|
80029a2: 3348 adds r3, #72 @ 0x48
|
|
80029a4: 681b ldr r3, [r3, #0]
|
|
80029a6: 2b02 cmp r3, #2
|
|
80029a8: d943 bls.n 8002a32 <HCD_HC_IN_IRQHandler+0x80a>
|
|
{
|
|
hhcd->hc[chnum].NyetErrCnt = 0U;
|
|
80029aa: 78fa ldrb r2, [r7, #3]
|
|
80029ac: 6879 ldr r1, [r7, #4]
|
|
80029ae: 4613 mov r3, r2
|
|
80029b0: 011b lsls r3, r3, #4
|
|
80029b2: 1a9b subs r3, r3, r2
|
|
80029b4: 009b lsls r3, r3, #2
|
|
80029b6: 440b add r3, r1
|
|
80029b8: 3348 adds r3, #72 @ 0x48
|
|
80029ba: 2200 movs r2, #0
|
|
80029bc: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
80029be: 78fa ldrb r2, [r7, #3]
|
|
80029c0: 6879 ldr r1, [r7, #4]
|
|
80029c2: 4613 mov r3, r2
|
|
80029c4: 011b lsls r3, r3, #4
|
|
80029c6: 1a9b subs r3, r3, r2
|
|
80029c8: 009b lsls r3, r3, #2
|
|
80029ca: 440b add r3, r1
|
|
80029cc: 331b adds r3, #27
|
|
80029ce: 2200 movs r2, #0
|
|
80029d0: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].ErrCnt < 3U)
|
|
80029d2: 78fa ldrb r2, [r7, #3]
|
|
80029d4: 6879 ldr r1, [r7, #4]
|
|
80029d6: 4613 mov r3, r2
|
|
80029d8: 011b lsls r3, r3, #4
|
|
80029da: 1a9b subs r3, r3, r2
|
|
80029dc: 009b lsls r3, r3, #2
|
|
80029de: 440b add r3, r1
|
|
80029e0: 3344 adds r3, #68 @ 0x44
|
|
80029e2: 681b ldr r3, [r3, #0]
|
|
80029e4: 2b02 cmp r3, #2
|
|
80029e6: d809 bhi.n 80029fc <HCD_HC_IN_IRQHandler+0x7d4>
|
|
{
|
|
hhcd->hc[chnum].ep_ss_schedule = 1U;
|
|
80029e8: 78fa ldrb r2, [r7, #3]
|
|
80029ea: 6879 ldr r1, [r7, #4]
|
|
80029ec: 4613 mov r3, r2
|
|
80029ee: 011b lsls r3, r3, #4
|
|
80029f0: 1a9b subs r3, r3, r2
|
|
80029f2: 009b lsls r3, r3, #2
|
|
80029f4: 440b add r3, r1
|
|
80029f6: 331c adds r3, #28
|
|
80029f8: 2201 movs r2, #1
|
|
80029fa: 701a strb r2, [r3, #0]
|
|
}
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
80029fc: 78fb ldrb r3, [r7, #3]
|
|
80029fe: 015a lsls r2, r3, #5
|
|
8002a00: 693b ldr r3, [r7, #16]
|
|
8002a02: 4413 add r3, r2
|
|
8002a04: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002a08: 685b ldr r3, [r3, #4]
|
|
8002a0a: 78fa ldrb r2, [r7, #3]
|
|
8002a0c: 0151 lsls r1, r2, #5
|
|
8002a0e: 693a ldr r2, [r7, #16]
|
|
8002a10: 440a add r2, r1
|
|
8002a12: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002a16: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002a1a: 6053 str r3, [r2, #4]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8002a1c: 78fa ldrb r2, [r7, #3]
|
|
8002a1e: 6879 ldr r1, [r7, #4]
|
|
8002a20: 4613 mov r3, r2
|
|
8002a22: 011b lsls r3, r3, #4
|
|
8002a24: 1a9b subs r3, r3, r2
|
|
8002a26: 009b lsls r3, r3, #2
|
|
8002a28: 440b add r3, r1
|
|
8002a2a: 334c adds r3, #76 @ 0x4c
|
|
8002a2c: 2204 movs r2, #4
|
|
8002a2e: 701a strb r2, [r3, #0]
|
|
8002a30: e014 b.n 8002a5c <HCD_HC_IN_IRQHandler+0x834>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8002a32: 78fa ldrb r2, [r7, #3]
|
|
8002a34: 6879 ldr r1, [r7, #4]
|
|
8002a36: 4613 mov r3, r2
|
|
8002a38: 011b lsls r3, r3, #4
|
|
8002a3a: 1a9b subs r3, r3, r2
|
|
8002a3c: 009b lsls r3, r3, #2
|
|
8002a3e: 440b add r3, r1
|
|
8002a40: 334c adds r3, #76 @ 0x4c
|
|
8002a42: 2202 movs r2, #2
|
|
8002a44: 701a strb r2, [r3, #0]
|
|
8002a46: e009 b.n 8002a5c <HCD_HC_IN_IRQHandler+0x834>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8002a48: 78fa ldrb r2, [r7, #3]
|
|
8002a4a: 6879 ldr r1, [r7, #4]
|
|
8002a4c: 4613 mov r3, r2
|
|
8002a4e: 011b lsls r3, r3, #4
|
|
8002a50: 1a9b subs r3, r3, r2
|
|
8002a52: 009b lsls r3, r3, #2
|
|
8002a54: 440b add r3, r1
|
|
8002a56: 334c adds r3, #76 @ 0x4c
|
|
8002a58: 2202 movs r2, #2
|
|
8002a5a: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002a5c: 78fa ldrb r2, [r7, #3]
|
|
8002a5e: 6879 ldr r1, [r7, #4]
|
|
8002a60: 4613 mov r3, r2
|
|
8002a62: 011b lsls r3, r3, #4
|
|
8002a64: 1a9b subs r3, r3, r2
|
|
8002a66: 009b lsls r3, r3, #2
|
|
8002a68: 440b add r3, r1
|
|
8002a6a: 3326 adds r3, #38 @ 0x26
|
|
8002a6c: 781b ldrb r3, [r3, #0]
|
|
8002a6e: 2b00 cmp r3, #0
|
|
8002a70: d00b beq.n 8002a8a <HCD_HC_IN_IRQHandler+0x862>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002a72: 78fa ldrb r2, [r7, #3]
|
|
8002a74: 6879 ldr r1, [r7, #4]
|
|
8002a76: 4613 mov r3, r2
|
|
8002a78: 011b lsls r3, r3, #4
|
|
8002a7a: 1a9b subs r3, r3, r2
|
|
8002a7c: 009b lsls r3, r3, #2
|
|
8002a7e: 440b add r3, r1
|
|
8002a80: 3326 adds r3, #38 @ 0x26
|
|
8002a82: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002a84: 2b02 cmp r3, #2
|
|
8002a86: f040 8136 bne.w 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8002a8a: 78fb ldrb r3, [r7, #3]
|
|
8002a8c: 015a lsls r2, r3, #5
|
|
8002a8e: 693b ldr r3, [r7, #16]
|
|
8002a90: 4413 add r3, r2
|
|
8002a92: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002a96: 681b ldr r3, [r3, #0]
|
|
8002a98: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8002a9a: 68fb ldr r3, [r7, #12]
|
|
8002a9c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8002aa0: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8002aa2: 68fb ldr r3, [r7, #12]
|
|
8002aa4: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8002aa8: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8002aaa: 78fb ldrb r3, [r7, #3]
|
|
8002aac: 015a lsls r2, r3, #5
|
|
8002aae: 693b ldr r3, [r7, #16]
|
|
8002ab0: 4413 add r3, r2
|
|
8002ab2: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002ab6: 461a mov r2, r3
|
|
8002ab8: 68fb ldr r3, [r7, #12]
|
|
8002aba: 6013 str r3, [r2, #0]
|
|
8002abc: e11b b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_ACK)
|
|
8002abe: 78fa ldrb r2, [r7, #3]
|
|
8002ac0: 6879 ldr r1, [r7, #4]
|
|
8002ac2: 4613 mov r3, r2
|
|
8002ac4: 011b lsls r3, r3, #4
|
|
8002ac6: 1a9b subs r3, r3, r2
|
|
8002ac8: 009b lsls r3, r3, #2
|
|
8002aca: 440b add r3, r1
|
|
8002acc: 334d adds r3, #77 @ 0x4d
|
|
8002ace: 781b ldrb r3, [r3, #0]
|
|
8002ad0: 2b03 cmp r3, #3
|
|
8002ad2: f040 8081 bne.w 8002bd8 <HCD_HC_IN_IRQHandler+0x9b0>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002ad6: 78fa ldrb r2, [r7, #3]
|
|
8002ad8: 6879 ldr r1, [r7, #4]
|
|
8002ada: 4613 mov r3, r2
|
|
8002adc: 011b lsls r3, r3, #4
|
|
8002ade: 1a9b subs r3, r3, r2
|
|
8002ae0: 009b lsls r3, r3, #2
|
|
8002ae2: 440b add r3, r1
|
|
8002ae4: 334d adds r3, #77 @ 0x4d
|
|
8002ae6: 2202 movs r2, #2
|
|
8002ae8: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8002aea: 78fa ldrb r2, [r7, #3]
|
|
8002aec: 6879 ldr r1, [r7, #4]
|
|
8002aee: 4613 mov r3, r2
|
|
8002af0: 011b lsls r3, r3, #4
|
|
8002af2: 1a9b subs r3, r3, r2
|
|
8002af4: 009b lsls r3, r3, #2
|
|
8002af6: 440b add r3, r1
|
|
8002af8: 331b adds r3, #27
|
|
8002afa: 781b ldrb r3, [r3, #0]
|
|
8002afc: 2b01 cmp r3, #1
|
|
8002afe: f040 80fa bne.w 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8002b02: 78fa ldrb r2, [r7, #3]
|
|
8002b04: 6879 ldr r1, [r7, #4]
|
|
8002b06: 4613 mov r3, r2
|
|
8002b08: 011b lsls r3, r3, #4
|
|
8002b0a: 1a9b subs r3, r3, r2
|
|
8002b0c: 009b lsls r3, r3, #2
|
|
8002b0e: 440b add r3, r1
|
|
8002b10: 334c adds r3, #76 @ 0x4c
|
|
8002b12: 2202 movs r2, #2
|
|
8002b14: 701a strb r2, [r3, #0]
|
|
|
|
/* Set Complete split and re-activate the channel */
|
|
USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
|
|
8002b16: 78fb ldrb r3, [r7, #3]
|
|
8002b18: 015a lsls r2, r3, #5
|
|
8002b1a: 693b ldr r3, [r7, #16]
|
|
8002b1c: 4413 add r3, r2
|
|
8002b1e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002b22: 685b ldr r3, [r3, #4]
|
|
8002b24: 78fa ldrb r2, [r7, #3]
|
|
8002b26: 0151 lsls r1, r2, #5
|
|
8002b28: 693a ldr r2, [r7, #16]
|
|
8002b2a: 440a add r2, r1
|
|
8002b2c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002b30: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8002b34: 6053 str r3, [r2, #4]
|
|
USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
|
|
8002b36: 78fb ldrb r3, [r7, #3]
|
|
8002b38: 015a lsls r2, r3, #5
|
|
8002b3a: 693b ldr r3, [r7, #16]
|
|
8002b3c: 4413 add r3, r2
|
|
8002b3e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002b42: 68db ldr r3, [r3, #12]
|
|
8002b44: 78fa ldrb r2, [r7, #3]
|
|
8002b46: 0151 lsls r1, r2, #5
|
|
8002b48: 693a ldr r2, [r7, #16]
|
|
8002b4a: 440a add r2, r1
|
|
8002b4c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002b50: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8002b54: 60d3 str r3, [r2, #12]
|
|
USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
|
|
8002b56: 78fb ldrb r3, [r7, #3]
|
|
8002b58: 015a lsls r2, r3, #5
|
|
8002b5a: 693b ldr r3, [r7, #16]
|
|
8002b5c: 4413 add r3, r2
|
|
8002b5e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002b62: 68db ldr r3, [r3, #12]
|
|
8002b64: 78fa ldrb r2, [r7, #3]
|
|
8002b66: 0151 lsls r1, r2, #5
|
|
8002b68: 693a ldr r2, [r7, #16]
|
|
8002b6a: 440a add r2, r1
|
|
8002b6c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002b70: f023 0320 bic.w r3, r3, #32
|
|
8002b74: 60d3 str r3, [r2, #12]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002b76: 78fa ldrb r2, [r7, #3]
|
|
8002b78: 6879 ldr r1, [r7, #4]
|
|
8002b7a: 4613 mov r3, r2
|
|
8002b7c: 011b lsls r3, r3, #4
|
|
8002b7e: 1a9b subs r3, r3, r2
|
|
8002b80: 009b lsls r3, r3, #2
|
|
8002b82: 440b add r3, r1
|
|
8002b84: 3326 adds r3, #38 @ 0x26
|
|
8002b86: 781b ldrb r3, [r3, #0]
|
|
8002b88: 2b00 cmp r3, #0
|
|
8002b8a: d00b beq.n 8002ba4 <HCD_HC_IN_IRQHandler+0x97c>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002b8c: 78fa ldrb r2, [r7, #3]
|
|
8002b8e: 6879 ldr r1, [r7, #4]
|
|
8002b90: 4613 mov r3, r2
|
|
8002b92: 011b lsls r3, r3, #4
|
|
8002b94: 1a9b subs r3, r3, r2
|
|
8002b96: 009b lsls r3, r3, #2
|
|
8002b98: 440b add r3, r1
|
|
8002b9a: 3326 adds r3, #38 @ 0x26
|
|
8002b9c: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002b9e: 2b02 cmp r3, #2
|
|
8002ba0: f040 80a9 bne.w 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8002ba4: 78fb ldrb r3, [r7, #3]
|
|
8002ba6: 015a lsls r2, r3, #5
|
|
8002ba8: 693b ldr r3, [r7, #16]
|
|
8002baa: 4413 add r3, r2
|
|
8002bac: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002bb0: 681b ldr r3, [r3, #0]
|
|
8002bb2: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8002bb4: 68fb ldr r3, [r7, #12]
|
|
8002bb6: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8002bba: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8002bbc: 68fb ldr r3, [r7, #12]
|
|
8002bbe: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8002bc2: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8002bc4: 78fb ldrb r3, [r7, #3]
|
|
8002bc6: 015a lsls r2, r3, #5
|
|
8002bc8: 693b ldr r3, [r7, #16]
|
|
8002bca: 4413 add r3, r2
|
|
8002bcc: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002bd0: 461a mov r2, r3
|
|
8002bd2: 68fb ldr r3, [r7, #12]
|
|
8002bd4: 6013 str r3, [r2, #0]
|
|
8002bd6: e08e b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NAK)
|
|
8002bd8: 78fa ldrb r2, [r7, #3]
|
|
8002bda: 6879 ldr r1, [r7, #4]
|
|
8002bdc: 4613 mov r3, r2
|
|
8002bde: 011b lsls r3, r3, #4
|
|
8002be0: 1a9b subs r3, r3, r2
|
|
8002be2: 009b lsls r3, r3, #2
|
|
8002be4: 440b add r3, r1
|
|
8002be6: 334d adds r3, #77 @ 0x4d
|
|
8002be8: 781b ldrb r3, [r3, #0]
|
|
8002bea: 2b04 cmp r3, #4
|
|
8002bec: d143 bne.n 8002c76 <HCD_HC_IN_IRQHandler+0xa4e>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002bee: 78fa ldrb r2, [r7, #3]
|
|
8002bf0: 6879 ldr r1, [r7, #4]
|
|
8002bf2: 4613 mov r3, r2
|
|
8002bf4: 011b lsls r3, r3, #4
|
|
8002bf6: 1a9b subs r3, r3, r2
|
|
8002bf8: 009b lsls r3, r3, #2
|
|
8002bfa: 440b add r3, r1
|
|
8002bfc: 334d adds r3, #77 @ 0x4d
|
|
8002bfe: 2202 movs r2, #2
|
|
8002c00: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8002c02: 78fa ldrb r2, [r7, #3]
|
|
8002c04: 6879 ldr r1, [r7, #4]
|
|
8002c06: 4613 mov r3, r2
|
|
8002c08: 011b lsls r3, r3, #4
|
|
8002c0a: 1a9b subs r3, r3, r2
|
|
8002c0c: 009b lsls r3, r3, #2
|
|
8002c0e: 440b add r3, r1
|
|
8002c10: 334c adds r3, #76 @ 0x4c
|
|
8002c12: 2202 movs r2, #2
|
|
8002c14: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002c16: 78fa ldrb r2, [r7, #3]
|
|
8002c18: 6879 ldr r1, [r7, #4]
|
|
8002c1a: 4613 mov r3, r2
|
|
8002c1c: 011b lsls r3, r3, #4
|
|
8002c1e: 1a9b subs r3, r3, r2
|
|
8002c20: 009b lsls r3, r3, #2
|
|
8002c22: 440b add r3, r1
|
|
8002c24: 3326 adds r3, #38 @ 0x26
|
|
8002c26: 781b ldrb r3, [r3, #0]
|
|
8002c28: 2b00 cmp r3, #0
|
|
8002c2a: d00a beq.n 8002c42 <HCD_HC_IN_IRQHandler+0xa1a>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002c2c: 78fa ldrb r2, [r7, #3]
|
|
8002c2e: 6879 ldr r1, [r7, #4]
|
|
8002c30: 4613 mov r3, r2
|
|
8002c32: 011b lsls r3, r3, #4
|
|
8002c34: 1a9b subs r3, r3, r2
|
|
8002c36: 009b lsls r3, r3, #2
|
|
8002c38: 440b add r3, r1
|
|
8002c3a: 3326 adds r3, #38 @ 0x26
|
|
8002c3c: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002c3e: 2b02 cmp r3, #2
|
|
8002c40: d159 bne.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
{
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
8002c42: 78fb ldrb r3, [r7, #3]
|
|
8002c44: 015a lsls r2, r3, #5
|
|
8002c46: 693b ldr r3, [r7, #16]
|
|
8002c48: 4413 add r3, r2
|
|
8002c4a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002c4e: 681b ldr r3, [r3, #0]
|
|
8002c50: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
8002c52: 68fb ldr r3, [r7, #12]
|
|
8002c54: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8002c58: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8002c5a: 68fb ldr r3, [r7, #12]
|
|
8002c5c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8002c60: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
8002c62: 78fb ldrb r3, [r7, #3]
|
|
8002c64: 015a lsls r2, r3, #5
|
|
8002c66: 693b ldr r3, [r7, #16]
|
|
8002c68: 4413 add r3, r2
|
|
8002c6a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002c6e: 461a mov r2, r3
|
|
8002c70: 68fb ldr r3, [r7, #12]
|
|
8002c72: 6013 str r3, [r2, #0]
|
|
8002c74: e03f b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_BBLERR)
|
|
8002c76: 78fa ldrb r2, [r7, #3]
|
|
8002c78: 6879 ldr r1, [r7, #4]
|
|
8002c7a: 4613 mov r3, r2
|
|
8002c7c: 011b lsls r3, r3, #4
|
|
8002c7e: 1a9b subs r3, r3, r2
|
|
8002c80: 009b lsls r3, r3, #2
|
|
8002c82: 440b add r3, r1
|
|
8002c84: 334d adds r3, #77 @ 0x4d
|
|
8002c86: 781b ldrb r3, [r3, #0]
|
|
8002c88: 2b08 cmp r3, #8
|
|
8002c8a: d126 bne.n 8002cda <HCD_HC_IN_IRQHandler+0xab2>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8002c8c: 78fa ldrb r2, [r7, #3]
|
|
8002c8e: 6879 ldr r1, [r7, #4]
|
|
8002c90: 4613 mov r3, r2
|
|
8002c92: 011b lsls r3, r3, #4
|
|
8002c94: 1a9b subs r3, r3, r2
|
|
8002c96: 009b lsls r3, r3, #2
|
|
8002c98: 440b add r3, r1
|
|
8002c9a: 334d adds r3, #77 @ 0x4d
|
|
8002c9c: 2202 movs r2, #2
|
|
8002c9e: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8002ca0: 78fa ldrb r2, [r7, #3]
|
|
8002ca2: 6879 ldr r1, [r7, #4]
|
|
8002ca4: 4613 mov r3, r2
|
|
8002ca6: 011b lsls r3, r3, #4
|
|
8002ca8: 1a9b subs r3, r3, r2
|
|
8002caa: 009b lsls r3, r3, #2
|
|
8002cac: 440b add r3, r1
|
|
8002cae: 3344 adds r3, #68 @ 0x44
|
|
8002cb0: 681b ldr r3, [r3, #0]
|
|
8002cb2: 1c59 adds r1, r3, #1
|
|
8002cb4: 6878 ldr r0, [r7, #4]
|
|
8002cb6: 4613 mov r3, r2
|
|
8002cb8: 011b lsls r3, r3, #4
|
|
8002cba: 1a9b subs r3, r3, r2
|
|
8002cbc: 009b lsls r3, r3, #2
|
|
8002cbe: 4403 add r3, r0
|
|
8002cc0: 3344 adds r3, #68 @ 0x44
|
|
8002cc2: 6019 str r1, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8002cc4: 78fa ldrb r2, [r7, #3]
|
|
8002cc6: 6879 ldr r1, [r7, #4]
|
|
8002cc8: 4613 mov r3, r2
|
|
8002cca: 011b lsls r3, r3, #4
|
|
8002ccc: 1a9b subs r3, r3, r2
|
|
8002cce: 009b lsls r3, r3, #2
|
|
8002cd0: 440b add r3, r1
|
|
8002cd2: 334c adds r3, #76 @ 0x4c
|
|
8002cd4: 2204 movs r2, #4
|
|
8002cd6: 701a strb r2, [r3, #0]
|
|
8002cd8: e00d b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
}
|
|
else
|
|
{
|
|
if (hhcd->hc[chnum].state == HC_HALTED)
|
|
8002cda: 78fa ldrb r2, [r7, #3]
|
|
8002cdc: 6879 ldr r1, [r7, #4]
|
|
8002cde: 4613 mov r3, r2
|
|
8002ce0: 011b lsls r3, r3, #4
|
|
8002ce2: 1a9b subs r3, r3, r2
|
|
8002ce4: 009b lsls r3, r3, #2
|
|
8002ce6: 440b add r3, r1
|
|
8002ce8: 334d adds r3, #77 @ 0x4d
|
|
8002cea: 781b ldrb r3, [r3, #0]
|
|
8002cec: 2b02 cmp r3, #2
|
|
8002cee: f000 8100 beq.w 8002ef2 <HCD_HC_IN_IRQHandler+0xcca>
|
|
8002cf2: e000 b.n 8002cf6 <HCD_HC_IN_IRQHandler+0xace>
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8002cf4: bf00 nop
|
|
}
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
8002cf6: 78fa ldrb r2, [r7, #3]
|
|
8002cf8: 6879 ldr r1, [r7, #4]
|
|
8002cfa: 4613 mov r3, r2
|
|
8002cfc: 011b lsls r3, r3, #4
|
|
8002cfe: 1a9b subs r3, r3, r2
|
|
8002d00: 009b lsls r3, r3, #2
|
|
8002d02: 440b add r3, r1
|
|
8002d04: 334c adds r3, #76 @ 0x4c
|
|
8002d06: 781a ldrb r2, [r3, #0]
|
|
8002d08: 78fb ldrb r3, [r7, #3]
|
|
8002d0a: 4619 mov r1, r3
|
|
8002d0c: 6878 ldr r0, [r7, #4]
|
|
8002d0e: f005 f811 bl 8007d34 <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
8002d12: e0ef b.n 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
8002d14: 687b ldr r3, [r7, #4]
|
|
8002d16: 681b ldr r3, [r3, #0]
|
|
8002d18: 78fa ldrb r2, [r7, #3]
|
|
8002d1a: 4611 mov r1, r2
|
|
8002d1c: 4618 mov r0, r3
|
|
8002d1e: f003 fbfa bl 8006516 <USB_ReadChInterrupts>
|
|
8002d22: 4603 mov r3, r0
|
|
8002d24: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8002d28: 2b40 cmp r3, #64 @ 0x40
|
|
8002d2a: d12f bne.n 8002d8c <HCD_HC_IN_IRQHandler+0xb64>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
8002d2c: 78fb ldrb r3, [r7, #3]
|
|
8002d2e: 015a lsls r2, r3, #5
|
|
8002d30: 693b ldr r3, [r7, #16]
|
|
8002d32: 4413 add r3, r2
|
|
8002d34: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002d38: 461a mov r2, r3
|
|
8002d3a: 2340 movs r3, #64 @ 0x40
|
|
8002d3c: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_NYET;
|
|
8002d3e: 78fa ldrb r2, [r7, #3]
|
|
8002d40: 6879 ldr r1, [r7, #4]
|
|
8002d42: 4613 mov r3, r2
|
|
8002d44: 011b lsls r3, r3, #4
|
|
8002d46: 1a9b subs r3, r3, r2
|
|
8002d48: 009b lsls r3, r3, #2
|
|
8002d4a: 440b add r3, r1
|
|
8002d4c: 334d adds r3, #77 @ 0x4d
|
|
8002d4e: 2205 movs r2, #5
|
|
8002d50: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 0U)
|
|
8002d52: 78fa ldrb r2, [r7, #3]
|
|
8002d54: 6879 ldr r1, [r7, #4]
|
|
8002d56: 4613 mov r3, r2
|
|
8002d58: 011b lsls r3, r3, #4
|
|
8002d5a: 1a9b subs r3, r3, r2
|
|
8002d5c: 009b lsls r3, r3, #2
|
|
8002d5e: 440b add r3, r1
|
|
8002d60: 331a adds r3, #26
|
|
8002d62: 781b ldrb r3, [r3, #0]
|
|
8002d64: 2b00 cmp r3, #0
|
|
8002d66: d109 bne.n 8002d7c <HCD_HC_IN_IRQHandler+0xb54>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002d68: 78fa ldrb r2, [r7, #3]
|
|
8002d6a: 6879 ldr r1, [r7, #4]
|
|
8002d6c: 4613 mov r3, r2
|
|
8002d6e: 011b lsls r3, r3, #4
|
|
8002d70: 1a9b subs r3, r3, r2
|
|
8002d72: 009b lsls r3, r3, #2
|
|
8002d74: 440b add r3, r1
|
|
8002d76: 3344 adds r3, #68 @ 0x44
|
|
8002d78: 2200 movs r2, #0
|
|
8002d7a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002d7c: 687b ldr r3, [r7, #4]
|
|
8002d7e: 681b ldr r3, [r3, #0]
|
|
8002d80: 78fa ldrb r2, [r7, #3]
|
|
8002d82: 4611 mov r1, r2
|
|
8002d84: 4618 mov r0, r3
|
|
8002d86: f003 fc43 bl 8006610 <USB_HC_Halt>
|
|
8002d8a: e0b3 b.n 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
|
|
8002d8c: 687b ldr r3, [r7, #4]
|
|
8002d8e: 681b ldr r3, [r3, #0]
|
|
8002d90: 78fa ldrb r2, [r7, #3]
|
|
8002d92: 4611 mov r1, r2
|
|
8002d94: 4618 mov r0, r3
|
|
8002d96: f003 fbbe bl 8006516 <USB_ReadChInterrupts>
|
|
8002d9a: 4603 mov r3, r0
|
|
8002d9c: f003 0310 and.w r3, r3, #16
|
|
8002da0: 2b10 cmp r3, #16
|
|
8002da2: f040 80a7 bne.w 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
|
|
8002da6: 78fa ldrb r2, [r7, #3]
|
|
8002da8: 6879 ldr r1, [r7, #4]
|
|
8002daa: 4613 mov r3, r2
|
|
8002dac: 011b lsls r3, r3, #4
|
|
8002dae: 1a9b subs r3, r3, r2
|
|
8002db0: 009b lsls r3, r3, #2
|
|
8002db2: 440b add r3, r1
|
|
8002db4: 3326 adds r3, #38 @ 0x26
|
|
8002db6: 781b ldrb r3, [r3, #0]
|
|
8002db8: 2b03 cmp r3, #3
|
|
8002dba: d11b bne.n 8002df4 <HCD_HC_IN_IRQHandler+0xbcc>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002dbc: 78fa ldrb r2, [r7, #3]
|
|
8002dbe: 6879 ldr r1, [r7, #4]
|
|
8002dc0: 4613 mov r3, r2
|
|
8002dc2: 011b lsls r3, r3, #4
|
|
8002dc4: 1a9b subs r3, r3, r2
|
|
8002dc6: 009b lsls r3, r3, #2
|
|
8002dc8: 440b add r3, r1
|
|
8002dca: 3344 adds r3, #68 @ 0x44
|
|
8002dcc: 2200 movs r2, #0
|
|
8002dce: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
8002dd0: 78fa ldrb r2, [r7, #3]
|
|
8002dd2: 6879 ldr r1, [r7, #4]
|
|
8002dd4: 4613 mov r3, r2
|
|
8002dd6: 011b lsls r3, r3, #4
|
|
8002dd8: 1a9b subs r3, r3, r2
|
|
8002dda: 009b lsls r3, r3, #2
|
|
8002ddc: 440b add r3, r1
|
|
8002dde: 334d adds r3, #77 @ 0x4d
|
|
8002de0: 2204 movs r2, #4
|
|
8002de2: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002de4: 687b ldr r3, [r7, #4]
|
|
8002de6: 681b ldr r3, [r3, #0]
|
|
8002de8: 78fa ldrb r2, [r7, #3]
|
|
8002dea: 4611 mov r1, r2
|
|
8002dec: 4618 mov r0, r3
|
|
8002dee: f003 fc0f bl 8006610 <USB_HC_Halt>
|
|
8002df2: e03f b.n 8002e74 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
}
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002df4: 78fa ldrb r2, [r7, #3]
|
|
8002df6: 6879 ldr r1, [r7, #4]
|
|
8002df8: 4613 mov r3, r2
|
|
8002dfa: 011b lsls r3, r3, #4
|
|
8002dfc: 1a9b subs r3, r3, r2
|
|
8002dfe: 009b lsls r3, r3, #2
|
|
8002e00: 440b add r3, r1
|
|
8002e02: 3326 adds r3, #38 @ 0x26
|
|
8002e04: 781b ldrb r3, [r3, #0]
|
|
8002e06: 2b00 cmp r3, #0
|
|
8002e08: d00a beq.n 8002e20 <HCD_HC_IN_IRQHandler+0xbf8>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
|
|
8002e0a: 78fa ldrb r2, [r7, #3]
|
|
8002e0c: 6879 ldr r1, [r7, #4]
|
|
8002e0e: 4613 mov r3, r2
|
|
8002e10: 011b lsls r3, r3, #4
|
|
8002e12: 1a9b subs r3, r3, r2
|
|
8002e14: 009b lsls r3, r3, #2
|
|
8002e16: 440b add r3, r1
|
|
8002e18: 3326 adds r3, #38 @ 0x26
|
|
8002e1a: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
|
|
8002e1c: 2b02 cmp r3, #2
|
|
8002e1e: d129 bne.n 8002e74 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8002e20: 78fa ldrb r2, [r7, #3]
|
|
8002e22: 6879 ldr r1, [r7, #4]
|
|
8002e24: 4613 mov r3, r2
|
|
8002e26: 011b lsls r3, r3, #4
|
|
8002e28: 1a9b subs r3, r3, r2
|
|
8002e2a: 009b lsls r3, r3, #2
|
|
8002e2c: 440b add r3, r1
|
|
8002e2e: 3344 adds r3, #68 @ 0x44
|
|
8002e30: 2200 movs r2, #0
|
|
8002e32: 601a str r2, [r3, #0]
|
|
|
|
if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
|
|
8002e34: 687b ldr r3, [r7, #4]
|
|
8002e36: 799b ldrb r3, [r3, #6]
|
|
8002e38: 2b00 cmp r3, #0
|
|
8002e3a: d00a beq.n 8002e52 <HCD_HC_IN_IRQHandler+0xc2a>
|
|
8002e3c: 78fa ldrb r2, [r7, #3]
|
|
8002e3e: 6879 ldr r1, [r7, #4]
|
|
8002e40: 4613 mov r3, r2
|
|
8002e42: 011b lsls r3, r3, #4
|
|
8002e44: 1a9b subs r3, r3, r2
|
|
8002e46: 009b lsls r3, r3, #2
|
|
8002e48: 440b add r3, r1
|
|
8002e4a: 331b adds r3, #27
|
|
8002e4c: 781b ldrb r3, [r3, #0]
|
|
8002e4e: 2b01 cmp r3, #1
|
|
8002e50: d110 bne.n 8002e74 <HCD_HC_IN_IRQHandler+0xc4c>
|
|
{
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
8002e52: 78fa ldrb r2, [r7, #3]
|
|
8002e54: 6879 ldr r1, [r7, #4]
|
|
8002e56: 4613 mov r3, r2
|
|
8002e58: 011b lsls r3, r3, #4
|
|
8002e5a: 1a9b subs r3, r3, r2
|
|
8002e5c: 009b lsls r3, r3, #2
|
|
8002e5e: 440b add r3, r1
|
|
8002e60: 334d adds r3, #77 @ 0x4d
|
|
8002e62: 2204 movs r2, #4
|
|
8002e64: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002e66: 687b ldr r3, [r7, #4]
|
|
8002e68: 681b ldr r3, [r3, #0]
|
|
8002e6a: 78fa ldrb r2, [r7, #3]
|
|
8002e6c: 4611 mov r1, r2
|
|
8002e6e: 4618 mov r0, r3
|
|
8002e70: f003 fbce bl 8006610 <USB_HC_Halt>
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8002e74: 78fa ldrb r2, [r7, #3]
|
|
8002e76: 6879 ldr r1, [r7, #4]
|
|
8002e78: 4613 mov r3, r2
|
|
8002e7a: 011b lsls r3, r3, #4
|
|
8002e7c: 1a9b subs r3, r3, r2
|
|
8002e7e: 009b lsls r3, r3, #2
|
|
8002e80: 440b add r3, r1
|
|
8002e82: 331b adds r3, #27
|
|
8002e84: 781b ldrb r3, [r3, #0]
|
|
8002e86: 2b01 cmp r3, #1
|
|
8002e88: d129 bne.n 8002ede <HCD_HC_IN_IRQHandler+0xcb6>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
8002e8a: 78fa ldrb r2, [r7, #3]
|
|
8002e8c: 6879 ldr r1, [r7, #4]
|
|
8002e8e: 4613 mov r3, r2
|
|
8002e90: 011b lsls r3, r3, #4
|
|
8002e92: 1a9b subs r3, r3, r2
|
|
8002e94: 009b lsls r3, r3, #2
|
|
8002e96: 440b add r3, r1
|
|
8002e98: 331b adds r3, #27
|
|
8002e9a: 2200 movs r2, #0
|
|
8002e9c: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8002e9e: 78fb ldrb r3, [r7, #3]
|
|
8002ea0: 015a lsls r2, r3, #5
|
|
8002ea2: 693b ldr r3, [r7, #16]
|
|
8002ea4: 4413 add r3, r2
|
|
8002ea6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002eaa: 685b ldr r3, [r3, #4]
|
|
8002eac: 78fa ldrb r2, [r7, #3]
|
|
8002eae: 0151 lsls r1, r2, #5
|
|
8002eb0: 693a ldr r2, [r7, #16]
|
|
8002eb2: 440a add r2, r1
|
|
8002eb4: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002eb8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8002ebc: 6053 str r3, [r2, #4]
|
|
__HAL_HCD_UNMASK_ACK_HC_INT(chnum);
|
|
8002ebe: 78fb ldrb r3, [r7, #3]
|
|
8002ec0: 015a lsls r2, r3, #5
|
|
8002ec2: 693b ldr r3, [r7, #16]
|
|
8002ec4: 4413 add r3, r2
|
|
8002ec6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002eca: 68db ldr r3, [r3, #12]
|
|
8002ecc: 78fa ldrb r2, [r7, #3]
|
|
8002ece: 0151 lsls r1, r2, #5
|
|
8002ed0: 693a ldr r2, [r7, #16]
|
|
8002ed2: 440a add r2, r1
|
|
8002ed4: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8002ed8: f043 0320 orr.w r3, r3, #32
|
|
8002edc: 60d3 str r3, [r2, #12]
|
|
}
|
|
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
8002ede: 78fb ldrb r3, [r7, #3]
|
|
8002ee0: 015a lsls r2, r3, #5
|
|
8002ee2: 693b ldr r3, [r7, #16]
|
|
8002ee4: 4413 add r3, r2
|
|
8002ee6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002eea: 461a mov r2, r3
|
|
8002eec: 2310 movs r3, #16
|
|
8002eee: 6093 str r3, [r2, #8]
|
|
8002ef0: e000 b.n 8002ef4 <HCD_HC_IN_IRQHandler+0xccc>
|
|
return;
|
|
8002ef2: bf00 nop
|
|
}
|
|
else
|
|
{
|
|
/* ... */
|
|
}
|
|
}
|
|
8002ef4: 3718 adds r7, #24
|
|
8002ef6: 46bd mov sp, r7
|
|
8002ef8: bd80 pop {r7, pc}
|
|
|
|
08002efa <HCD_HC_OUT_IRQHandler>:
|
|
* @param chnum Channel number.
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval none
|
|
*/
|
|
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
|
|
{
|
|
8002efa: b580 push {r7, lr}
|
|
8002efc: b086 sub sp, #24
|
|
8002efe: af00 add r7, sp, #0
|
|
8002f00: 6078 str r0, [r7, #4]
|
|
8002f02: 460b mov r3, r1
|
|
8002f04: 70fb strb r3, [r7, #3]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8002f06: 687b ldr r3, [r7, #4]
|
|
8002f08: 681b ldr r3, [r3, #0]
|
|
8002f0a: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8002f0c: 697b ldr r3, [r7, #20]
|
|
8002f0e: 613b str r3, [r7, #16]
|
|
uint32_t tmpreg;
|
|
uint32_t num_packets;
|
|
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
|
|
8002f10: 687b ldr r3, [r7, #4]
|
|
8002f12: 681b ldr r3, [r3, #0]
|
|
8002f14: 78fa ldrb r2, [r7, #3]
|
|
8002f16: 4611 mov r1, r2
|
|
8002f18: 4618 mov r0, r3
|
|
8002f1a: f003 fafc bl 8006516 <USB_ReadChInterrupts>
|
|
8002f1e: 4603 mov r3, r0
|
|
8002f20: f003 0304 and.w r3, r3, #4
|
|
8002f24: 2b04 cmp r3, #4
|
|
8002f26: d11b bne.n 8002f60 <HCD_HC_OUT_IRQHandler+0x66>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
|
|
8002f28: 78fb ldrb r3, [r7, #3]
|
|
8002f2a: 015a lsls r2, r3, #5
|
|
8002f2c: 693b ldr r3, [r7, #16]
|
|
8002f2e: 4413 add r3, r2
|
|
8002f30: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002f34: 461a mov r2, r3
|
|
8002f36: 2304 movs r3, #4
|
|
8002f38: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8002f3a: 78fa ldrb r2, [r7, #3]
|
|
8002f3c: 6879 ldr r1, [r7, #4]
|
|
8002f3e: 4613 mov r3, r2
|
|
8002f40: 011b lsls r3, r3, #4
|
|
8002f42: 1a9b subs r3, r3, r2
|
|
8002f44: 009b lsls r3, r3, #2
|
|
8002f46: 440b add r3, r1
|
|
8002f48: 334d adds r3, #77 @ 0x4d
|
|
8002f4a: 2207 movs r2, #7
|
|
8002f4c: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002f4e: 687b ldr r3, [r7, #4]
|
|
8002f50: 681b ldr r3, [r3, #0]
|
|
8002f52: 78fa ldrb r2, [r7, #3]
|
|
8002f54: 4611 mov r1, r2
|
|
8002f56: 4618 mov r0, r3
|
|
8002f58: f003 fb5a bl 8006610 <USB_HC_Halt>
|
|
8002f5c: f000 bc89 b.w 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
|
|
8002f60: 687b ldr r3, [r7, #4]
|
|
8002f62: 681b ldr r3, [r3, #0]
|
|
8002f64: 78fa ldrb r2, [r7, #3]
|
|
8002f66: 4611 mov r1, r2
|
|
8002f68: 4618 mov r0, r3
|
|
8002f6a: f003 fad4 bl 8006516 <USB_ReadChInterrupts>
|
|
8002f6e: 4603 mov r3, r0
|
|
8002f70: f003 0320 and.w r3, r3, #32
|
|
8002f74: 2b20 cmp r3, #32
|
|
8002f76: f040 8082 bne.w 800307e <HCD_HC_OUT_IRQHandler+0x184>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
|
|
8002f7a: 78fb ldrb r3, [r7, #3]
|
|
8002f7c: 015a lsls r2, r3, #5
|
|
8002f7e: 693b ldr r3, [r7, #16]
|
|
8002f80: 4413 add r3, r2
|
|
8002f82: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8002f86: 461a mov r2, r3
|
|
8002f88: 2320 movs r3, #32
|
|
8002f8a: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].do_ping == 1U)
|
|
8002f8c: 78fa ldrb r2, [r7, #3]
|
|
8002f8e: 6879 ldr r1, [r7, #4]
|
|
8002f90: 4613 mov r3, r2
|
|
8002f92: 011b lsls r3, r3, #4
|
|
8002f94: 1a9b subs r3, r3, r2
|
|
8002f96: 009b lsls r3, r3, #2
|
|
8002f98: 440b add r3, r1
|
|
8002f9a: 3319 adds r3, #25
|
|
8002f9c: 781b ldrb r3, [r3, #0]
|
|
8002f9e: 2b01 cmp r3, #1
|
|
8002fa0: d124 bne.n 8002fec <HCD_HC_OUT_IRQHandler+0xf2>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 0U;
|
|
8002fa2: 78fa ldrb r2, [r7, #3]
|
|
8002fa4: 6879 ldr r1, [r7, #4]
|
|
8002fa6: 4613 mov r3, r2
|
|
8002fa8: 011b lsls r3, r3, #4
|
|
8002faa: 1a9b subs r3, r3, r2
|
|
8002fac: 009b lsls r3, r3, #2
|
|
8002fae: 440b add r3, r1
|
|
8002fb0: 3319 adds r3, #25
|
|
8002fb2: 2200 movs r2, #0
|
|
8002fb4: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8002fb6: 78fa ldrb r2, [r7, #3]
|
|
8002fb8: 6879 ldr r1, [r7, #4]
|
|
8002fba: 4613 mov r3, r2
|
|
8002fbc: 011b lsls r3, r3, #4
|
|
8002fbe: 1a9b subs r3, r3, r2
|
|
8002fc0: 009b lsls r3, r3, #2
|
|
8002fc2: 440b add r3, r1
|
|
8002fc4: 334c adds r3, #76 @ 0x4c
|
|
8002fc6: 2202 movs r2, #2
|
|
8002fc8: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
8002fca: 78fa ldrb r2, [r7, #3]
|
|
8002fcc: 6879 ldr r1, [r7, #4]
|
|
8002fce: 4613 mov r3, r2
|
|
8002fd0: 011b lsls r3, r3, #4
|
|
8002fd2: 1a9b subs r3, r3, r2
|
|
8002fd4: 009b lsls r3, r3, #2
|
|
8002fd6: 440b add r3, r1
|
|
8002fd8: 334d adds r3, #77 @ 0x4d
|
|
8002fda: 2203 movs r2, #3
|
|
8002fdc: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8002fde: 687b ldr r3, [r7, #4]
|
|
8002fe0: 681b ldr r3, [r3, #0]
|
|
8002fe2: 78fa ldrb r2, [r7, #3]
|
|
8002fe4: 4611 mov r1, r2
|
|
8002fe6: 4618 mov r0, r3
|
|
8002fe8: f003 fb12 bl 8006610 <USB_HC_Halt>
|
|
}
|
|
|
|
if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
|
|
8002fec: 78fa ldrb r2, [r7, #3]
|
|
8002fee: 6879 ldr r1, [r7, #4]
|
|
8002ff0: 4613 mov r3, r2
|
|
8002ff2: 011b lsls r3, r3, #4
|
|
8002ff4: 1a9b subs r3, r3, r2
|
|
8002ff6: 009b lsls r3, r3, #2
|
|
8002ff8: 440b add r3, r1
|
|
8002ffa: 331a adds r3, #26
|
|
8002ffc: 781b ldrb r3, [r3, #0]
|
|
8002ffe: 2b01 cmp r3, #1
|
|
8003000: f040 8437 bne.w 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
8003004: 78fa ldrb r2, [r7, #3]
|
|
8003006: 6879 ldr r1, [r7, #4]
|
|
8003008: 4613 mov r3, r2
|
|
800300a: 011b lsls r3, r3, #4
|
|
800300c: 1a9b subs r3, r3, r2
|
|
800300e: 009b lsls r3, r3, #2
|
|
8003010: 440b add r3, r1
|
|
8003012: 331b adds r3, #27
|
|
8003014: 781b ldrb r3, [r3, #0]
|
|
8003016: 2b00 cmp r3, #0
|
|
8003018: f040 842b bne.w 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
{
|
|
if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
|
|
800301c: 78fa ldrb r2, [r7, #3]
|
|
800301e: 6879 ldr r1, [r7, #4]
|
|
8003020: 4613 mov r3, r2
|
|
8003022: 011b lsls r3, r3, #4
|
|
8003024: 1a9b subs r3, r3, r2
|
|
8003026: 009b lsls r3, r3, #2
|
|
8003028: 440b add r3, r1
|
|
800302a: 3326 adds r3, #38 @ 0x26
|
|
800302c: 781b ldrb r3, [r3, #0]
|
|
800302e: 2b01 cmp r3, #1
|
|
8003030: d009 beq.n 8003046 <HCD_HC_OUT_IRQHandler+0x14c>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 1U;
|
|
8003032: 78fa ldrb r2, [r7, #3]
|
|
8003034: 6879 ldr r1, [r7, #4]
|
|
8003036: 4613 mov r3, r2
|
|
8003038: 011b lsls r3, r3, #4
|
|
800303a: 1a9b subs r3, r3, r2
|
|
800303c: 009b lsls r3, r3, #2
|
|
800303e: 440b add r3, r1
|
|
8003040: 331b adds r3, #27
|
|
8003042: 2201 movs r2, #1
|
|
8003044: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].state = HC_ACK;
|
|
8003046: 78fa ldrb r2, [r7, #3]
|
|
8003048: 6879 ldr r1, [r7, #4]
|
|
800304a: 4613 mov r3, r2
|
|
800304c: 011b lsls r3, r3, #4
|
|
800304e: 1a9b subs r3, r3, r2
|
|
8003050: 009b lsls r3, r3, #2
|
|
8003052: 440b add r3, r1
|
|
8003054: 334d adds r3, #77 @ 0x4d
|
|
8003056: 2203 movs r2, #3
|
|
8003058: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
800305a: 687b ldr r3, [r7, #4]
|
|
800305c: 681b ldr r3, [r3, #0]
|
|
800305e: 78fa ldrb r2, [r7, #3]
|
|
8003060: 4611 mov r1, r2
|
|
8003062: 4618 mov r0, r3
|
|
8003064: f003 fad4 bl 8006610 <USB_HC_Halt>
|
|
|
|
/* reset error_count */
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8003068: 78fa ldrb r2, [r7, #3]
|
|
800306a: 6879 ldr r1, [r7, #4]
|
|
800306c: 4613 mov r3, r2
|
|
800306e: 011b lsls r3, r3, #4
|
|
8003070: 1a9b subs r3, r3, r2
|
|
8003072: 009b lsls r3, r3, #2
|
|
8003074: 440b add r3, r1
|
|
8003076: 3344 adds r3, #68 @ 0x44
|
|
8003078: 2200 movs r2, #0
|
|
800307a: 601a str r2, [r3, #0]
|
|
800307c: e3f9 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
|
|
800307e: 687b ldr r3, [r7, #4]
|
|
8003080: 681b ldr r3, [r3, #0]
|
|
8003082: 78fa ldrb r2, [r7, #3]
|
|
8003084: 4611 mov r1, r2
|
|
8003086: 4618 mov r0, r3
|
|
8003088: f003 fa45 bl 8006516 <USB_ReadChInterrupts>
|
|
800308c: 4603 mov r3, r0
|
|
800308e: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
8003092: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8003096: d111 bne.n 80030bc <HCD_HC_OUT_IRQHandler+0x1c2>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
|
|
8003098: 78fb ldrb r3, [r7, #3]
|
|
800309a: 015a lsls r2, r3, #5
|
|
800309c: 693b ldr r3, [r7, #16]
|
|
800309e: 4413 add r3, r2
|
|
80030a0: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80030a4: 461a mov r2, r3
|
|
80030a6: f44f 7300 mov.w r3, #512 @ 0x200
|
|
80030aa: 6093 str r3, [r2, #8]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
80030ac: 687b ldr r3, [r7, #4]
|
|
80030ae: 681b ldr r3, [r3, #0]
|
|
80030b0: 78fa ldrb r2, [r7, #3]
|
|
80030b2: 4611 mov r1, r2
|
|
80030b4: 4618 mov r0, r3
|
|
80030b6: f003 faab bl 8006610 <USB_HC_Halt>
|
|
80030ba: e3da b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
|
|
80030bc: 687b ldr r3, [r7, #4]
|
|
80030be: 681b ldr r3, [r3, #0]
|
|
80030c0: 78fa ldrb r2, [r7, #3]
|
|
80030c2: 4611 mov r1, r2
|
|
80030c4: 4618 mov r0, r3
|
|
80030c6: f003 fa26 bl 8006516 <USB_ReadChInterrupts>
|
|
80030ca: 4603 mov r3, r0
|
|
80030cc: f003 0301 and.w r3, r3, #1
|
|
80030d0: 2b01 cmp r3, #1
|
|
80030d2: d168 bne.n 80031a6 <HCD_HC_OUT_IRQHandler+0x2ac>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80030d4: 78fa ldrb r2, [r7, #3]
|
|
80030d6: 6879 ldr r1, [r7, #4]
|
|
80030d8: 4613 mov r3, r2
|
|
80030da: 011b lsls r3, r3, #4
|
|
80030dc: 1a9b subs r3, r3, r2
|
|
80030de: 009b lsls r3, r3, #2
|
|
80030e0: 440b add r3, r1
|
|
80030e2: 3344 adds r3, #68 @ 0x44
|
|
80030e4: 2200 movs r2, #0
|
|
80030e6: 601a str r2, [r3, #0]
|
|
|
|
/* transaction completed with NYET state, update do ping state */
|
|
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
80030e8: 687b ldr r3, [r7, #4]
|
|
80030ea: 681b ldr r3, [r3, #0]
|
|
80030ec: 78fa ldrb r2, [r7, #3]
|
|
80030ee: 4611 mov r1, r2
|
|
80030f0: 4618 mov r0, r3
|
|
80030f2: f003 fa10 bl 8006516 <USB_ReadChInterrupts>
|
|
80030f6: 4603 mov r3, r0
|
|
80030f8: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80030fc: 2b40 cmp r3, #64 @ 0x40
|
|
80030fe: d112 bne.n 8003126 <HCD_HC_OUT_IRQHandler+0x22c>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
8003100: 78fa ldrb r2, [r7, #3]
|
|
8003102: 6879 ldr r1, [r7, #4]
|
|
8003104: 4613 mov r3, r2
|
|
8003106: 011b lsls r3, r3, #4
|
|
8003108: 1a9b subs r3, r3, r2
|
|
800310a: 009b lsls r3, r3, #2
|
|
800310c: 440b add r3, r1
|
|
800310e: 3319 adds r3, #25
|
|
8003110: 2201 movs r2, #1
|
|
8003112: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
8003114: 78fb ldrb r3, [r7, #3]
|
|
8003116: 015a lsls r2, r3, #5
|
|
8003118: 693b ldr r3, [r7, #16]
|
|
800311a: 4413 add r3, r2
|
|
800311c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003120: 461a mov r2, r3
|
|
8003122: 2340 movs r3, #64 @ 0x40
|
|
8003124: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (hhcd->hc[chnum].do_csplit != 0U)
|
|
8003126: 78fa ldrb r2, [r7, #3]
|
|
8003128: 6879 ldr r1, [r7, #4]
|
|
800312a: 4613 mov r3, r2
|
|
800312c: 011b lsls r3, r3, #4
|
|
800312e: 1a9b subs r3, r3, r2
|
|
8003130: 009b lsls r3, r3, #2
|
|
8003132: 440b add r3, r1
|
|
8003134: 331b adds r3, #27
|
|
8003136: 781b ldrb r3, [r3, #0]
|
|
8003138: 2b00 cmp r3, #0
|
|
800313a: d019 beq.n 8003170 <HCD_HC_OUT_IRQHandler+0x276>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
800313c: 78fa ldrb r2, [r7, #3]
|
|
800313e: 6879 ldr r1, [r7, #4]
|
|
8003140: 4613 mov r3, r2
|
|
8003142: 011b lsls r3, r3, #4
|
|
8003144: 1a9b subs r3, r3, r2
|
|
8003146: 009b lsls r3, r3, #2
|
|
8003148: 440b add r3, r1
|
|
800314a: 331b adds r3, #27
|
|
800314c: 2200 movs r2, #0
|
|
800314e: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
8003150: 78fb ldrb r3, [r7, #3]
|
|
8003152: 015a lsls r2, r3, #5
|
|
8003154: 693b ldr r3, [r7, #16]
|
|
8003156: 4413 add r3, r2
|
|
8003158: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800315c: 685b ldr r3, [r3, #4]
|
|
800315e: 78fa ldrb r2, [r7, #3]
|
|
8003160: 0151 lsls r1, r2, #5
|
|
8003162: 693a ldr r2, [r7, #16]
|
|
8003164: 440a add r2, r1
|
|
8003166: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800316a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800316e: 6053 str r3, [r2, #4]
|
|
}
|
|
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
|
|
8003170: 78fb ldrb r3, [r7, #3]
|
|
8003172: 015a lsls r2, r3, #5
|
|
8003174: 693b ldr r3, [r7, #16]
|
|
8003176: 4413 add r3, r2
|
|
8003178: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800317c: 461a mov r2, r3
|
|
800317e: 2301 movs r3, #1
|
|
8003180: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_XFRC;
|
|
8003182: 78fa ldrb r2, [r7, #3]
|
|
8003184: 6879 ldr r1, [r7, #4]
|
|
8003186: 4613 mov r3, r2
|
|
8003188: 011b lsls r3, r3, #4
|
|
800318a: 1a9b subs r3, r3, r2
|
|
800318c: 009b lsls r3, r3, #2
|
|
800318e: 440b add r3, r1
|
|
8003190: 334d adds r3, #77 @ 0x4d
|
|
8003192: 2201 movs r2, #1
|
|
8003194: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003196: 687b ldr r3, [r7, #4]
|
|
8003198: 681b ldr r3, [r3, #0]
|
|
800319a: 78fa ldrb r2, [r7, #3]
|
|
800319c: 4611 mov r1, r2
|
|
800319e: 4618 mov r0, r3
|
|
80031a0: f003 fa36 bl 8006610 <USB_HC_Halt>
|
|
80031a4: e365 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
|
|
80031a6: 687b ldr r3, [r7, #4]
|
|
80031a8: 681b ldr r3, [r3, #0]
|
|
80031aa: 78fa ldrb r2, [r7, #3]
|
|
80031ac: 4611 mov r1, r2
|
|
80031ae: 4618 mov r0, r3
|
|
80031b0: f003 f9b1 bl 8006516 <USB_ReadChInterrupts>
|
|
80031b4: 4603 mov r3, r0
|
|
80031b6: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
80031ba: 2b40 cmp r3, #64 @ 0x40
|
|
80031bc: d139 bne.n 8003232 <HCD_HC_OUT_IRQHandler+0x338>
|
|
{
|
|
hhcd->hc[chnum].state = HC_NYET;
|
|
80031be: 78fa ldrb r2, [r7, #3]
|
|
80031c0: 6879 ldr r1, [r7, #4]
|
|
80031c2: 4613 mov r3, r2
|
|
80031c4: 011b lsls r3, r3, #4
|
|
80031c6: 1a9b subs r3, r3, r2
|
|
80031c8: 009b lsls r3, r3, #2
|
|
80031ca: 440b add r3, r1
|
|
80031cc: 334d adds r3, #77 @ 0x4d
|
|
80031ce: 2205 movs r2, #5
|
|
80031d0: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ssplit == 0U)
|
|
80031d2: 78fa ldrb r2, [r7, #3]
|
|
80031d4: 6879 ldr r1, [r7, #4]
|
|
80031d6: 4613 mov r3, r2
|
|
80031d8: 011b lsls r3, r3, #4
|
|
80031da: 1a9b subs r3, r3, r2
|
|
80031dc: 009b lsls r3, r3, #2
|
|
80031de: 440b add r3, r1
|
|
80031e0: 331a adds r3, #26
|
|
80031e2: 781b ldrb r3, [r3, #0]
|
|
80031e4: 2b00 cmp r3, #0
|
|
80031e6: d109 bne.n 80031fc <HCD_HC_OUT_IRQHandler+0x302>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
80031e8: 78fa ldrb r2, [r7, #3]
|
|
80031ea: 6879 ldr r1, [r7, #4]
|
|
80031ec: 4613 mov r3, r2
|
|
80031ee: 011b lsls r3, r3, #4
|
|
80031f0: 1a9b subs r3, r3, r2
|
|
80031f2: 009b lsls r3, r3, #2
|
|
80031f4: 440b add r3, r1
|
|
80031f6: 3319 adds r3, #25
|
|
80031f8: 2201 movs r2, #1
|
|
80031fa: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80031fc: 78fa ldrb r2, [r7, #3]
|
|
80031fe: 6879 ldr r1, [r7, #4]
|
|
8003200: 4613 mov r3, r2
|
|
8003202: 011b lsls r3, r3, #4
|
|
8003204: 1a9b subs r3, r3, r2
|
|
8003206: 009b lsls r3, r3, #2
|
|
8003208: 440b add r3, r1
|
|
800320a: 3344 adds r3, #68 @ 0x44
|
|
800320c: 2200 movs r2, #0
|
|
800320e: 601a str r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003210: 687b ldr r3, [r7, #4]
|
|
8003212: 681b ldr r3, [r3, #0]
|
|
8003214: 78fa ldrb r2, [r7, #3]
|
|
8003216: 4611 mov r1, r2
|
|
8003218: 4618 mov r0, r3
|
|
800321a: f003 f9f9 bl 8006610 <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
|
|
800321e: 78fb ldrb r3, [r7, #3]
|
|
8003220: 015a lsls r2, r3, #5
|
|
8003222: 693b ldr r3, [r7, #16]
|
|
8003224: 4413 add r3, r2
|
|
8003226: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800322a: 461a mov r2, r3
|
|
800322c: 2340 movs r3, #64 @ 0x40
|
|
800322e: 6093 str r3, [r2, #8]
|
|
8003230: e31f b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
|
|
8003232: 687b ldr r3, [r7, #4]
|
|
8003234: 681b ldr r3, [r3, #0]
|
|
8003236: 78fa ldrb r2, [r7, #3]
|
|
8003238: 4611 mov r1, r2
|
|
800323a: 4618 mov r0, r3
|
|
800323c: f003 f96b bl 8006516 <USB_ReadChInterrupts>
|
|
8003240: 4603 mov r3, r0
|
|
8003242: f003 0308 and.w r3, r3, #8
|
|
8003246: 2b08 cmp r3, #8
|
|
8003248: d11a bne.n 8003280 <HCD_HC_OUT_IRQHandler+0x386>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
|
|
800324a: 78fb ldrb r3, [r7, #3]
|
|
800324c: 015a lsls r2, r3, #5
|
|
800324e: 693b ldr r3, [r7, #16]
|
|
8003250: 4413 add r3, r2
|
|
8003252: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003256: 461a mov r2, r3
|
|
8003258: 2308 movs r3, #8
|
|
800325a: 6093 str r3, [r2, #8]
|
|
hhcd->hc[chnum].state = HC_STALL;
|
|
800325c: 78fa ldrb r2, [r7, #3]
|
|
800325e: 6879 ldr r1, [r7, #4]
|
|
8003260: 4613 mov r3, r2
|
|
8003262: 011b lsls r3, r3, #4
|
|
8003264: 1a9b subs r3, r3, r2
|
|
8003266: 009b lsls r3, r3, #2
|
|
8003268: 440b add r3, r1
|
|
800326a: 334d adds r3, #77 @ 0x4d
|
|
800326c: 2206 movs r2, #6
|
|
800326e: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003270: 687b ldr r3, [r7, #4]
|
|
8003272: 681b ldr r3, [r3, #0]
|
|
8003274: 78fa ldrb r2, [r7, #3]
|
|
8003276: 4611 mov r1, r2
|
|
8003278: 4618 mov r0, r3
|
|
800327a: f003 f9c9 bl 8006610 <USB_HC_Halt>
|
|
800327e: e2f8 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
|
|
8003280: 687b ldr r3, [r7, #4]
|
|
8003282: 681b ldr r3, [r3, #0]
|
|
8003284: 78fa ldrb r2, [r7, #3]
|
|
8003286: 4611 mov r1, r2
|
|
8003288: 4618 mov r0, r3
|
|
800328a: f003 f944 bl 8006516 <USB_ReadChInterrupts>
|
|
800328e: 4603 mov r3, r0
|
|
8003290: f003 0310 and.w r3, r3, #16
|
|
8003294: 2b10 cmp r3, #16
|
|
8003296: d144 bne.n 8003322 <HCD_HC_OUT_IRQHandler+0x428>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
8003298: 78fa ldrb r2, [r7, #3]
|
|
800329a: 6879 ldr r1, [r7, #4]
|
|
800329c: 4613 mov r3, r2
|
|
800329e: 011b lsls r3, r3, #4
|
|
80032a0: 1a9b subs r3, r3, r2
|
|
80032a2: 009b lsls r3, r3, #2
|
|
80032a4: 440b add r3, r1
|
|
80032a6: 3344 adds r3, #68 @ 0x44
|
|
80032a8: 2200 movs r2, #0
|
|
80032aa: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].state = HC_NAK;
|
|
80032ac: 78fa ldrb r2, [r7, #3]
|
|
80032ae: 6879 ldr r1, [r7, #4]
|
|
80032b0: 4613 mov r3, r2
|
|
80032b2: 011b lsls r3, r3, #4
|
|
80032b4: 1a9b subs r3, r3, r2
|
|
80032b6: 009b lsls r3, r3, #2
|
|
80032b8: 440b add r3, r1
|
|
80032ba: 334d adds r3, #77 @ 0x4d
|
|
80032bc: 2204 movs r2, #4
|
|
80032be: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_ping == 0U)
|
|
80032c0: 78fa ldrb r2, [r7, #3]
|
|
80032c2: 6879 ldr r1, [r7, #4]
|
|
80032c4: 4613 mov r3, r2
|
|
80032c6: 011b lsls r3, r3, #4
|
|
80032c8: 1a9b subs r3, r3, r2
|
|
80032ca: 009b lsls r3, r3, #2
|
|
80032cc: 440b add r3, r1
|
|
80032ce: 3319 adds r3, #25
|
|
80032d0: 781b ldrb r3, [r3, #0]
|
|
80032d2: 2b00 cmp r3, #0
|
|
80032d4: d114 bne.n 8003300 <HCD_HC_OUT_IRQHandler+0x406>
|
|
{
|
|
if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
|
|
80032d6: 78fa ldrb r2, [r7, #3]
|
|
80032d8: 6879 ldr r1, [r7, #4]
|
|
80032da: 4613 mov r3, r2
|
|
80032dc: 011b lsls r3, r3, #4
|
|
80032de: 1a9b subs r3, r3, r2
|
|
80032e0: 009b lsls r3, r3, #2
|
|
80032e2: 440b add r3, r1
|
|
80032e4: 3318 adds r3, #24
|
|
80032e6: 781b ldrb r3, [r3, #0]
|
|
80032e8: 2b00 cmp r3, #0
|
|
80032ea: d109 bne.n 8003300 <HCD_HC_OUT_IRQHandler+0x406>
|
|
{
|
|
hhcd->hc[chnum].do_ping = 1U;
|
|
80032ec: 78fa ldrb r2, [r7, #3]
|
|
80032ee: 6879 ldr r1, [r7, #4]
|
|
80032f0: 4613 mov r3, r2
|
|
80032f2: 011b lsls r3, r3, #4
|
|
80032f4: 1a9b subs r3, r3, r2
|
|
80032f6: 009b lsls r3, r3, #2
|
|
80032f8: 440b add r3, r1
|
|
80032fa: 3319 adds r3, #25
|
|
80032fc: 2201 movs r2, #1
|
|
80032fe: 701a strb r2, [r3, #0]
|
|
}
|
|
}
|
|
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003300: 687b ldr r3, [r7, #4]
|
|
8003302: 681b ldr r3, [r3, #0]
|
|
8003304: 78fa ldrb r2, [r7, #3]
|
|
8003306: 4611 mov r1, r2
|
|
8003308: 4618 mov r0, r3
|
|
800330a: f003 f981 bl 8006610 <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
|
|
800330e: 78fb ldrb r3, [r7, #3]
|
|
8003310: 015a lsls r2, r3, #5
|
|
8003312: 693b ldr r3, [r7, #16]
|
|
8003314: 4413 add r3, r2
|
|
8003316: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800331a: 461a mov r2, r3
|
|
800331c: 2310 movs r3, #16
|
|
800331e: 6093 str r3, [r2, #8]
|
|
8003320: e2a7 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
|
|
8003322: 687b ldr r3, [r7, #4]
|
|
8003324: 681b ldr r3, [r3, #0]
|
|
8003326: 78fa ldrb r2, [r7, #3]
|
|
8003328: 4611 mov r1, r2
|
|
800332a: 4618 mov r0, r3
|
|
800332c: f003 f8f3 bl 8006516 <USB_ReadChInterrupts>
|
|
8003330: 4603 mov r3, r0
|
|
8003332: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8003336: 2b80 cmp r3, #128 @ 0x80
|
|
8003338: f040 8083 bne.w 8003442 <HCD_HC_OUT_IRQHandler+0x548>
|
|
{
|
|
if (hhcd->Init.dma_enable == 0U)
|
|
800333c: 687b ldr r3, [r7, #4]
|
|
800333e: 799b ldrb r3, [r3, #6]
|
|
8003340: 2b00 cmp r3, #0
|
|
8003342: d111 bne.n 8003368 <HCD_HC_OUT_IRQHandler+0x46e>
|
|
{
|
|
hhcd->hc[chnum].state = HC_XACTERR;
|
|
8003344: 78fa ldrb r2, [r7, #3]
|
|
8003346: 6879 ldr r1, [r7, #4]
|
|
8003348: 4613 mov r3, r2
|
|
800334a: 011b lsls r3, r3, #4
|
|
800334c: 1a9b subs r3, r3, r2
|
|
800334e: 009b lsls r3, r3, #2
|
|
8003350: 440b add r3, r1
|
|
8003352: 334d adds r3, #77 @ 0x4d
|
|
8003354: 2207 movs r2, #7
|
|
8003356: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003358: 687b ldr r3, [r7, #4]
|
|
800335a: 681b ldr r3, [r3, #0]
|
|
800335c: 78fa ldrb r2, [r7, #3]
|
|
800335e: 4611 mov r1, r2
|
|
8003360: 4618 mov r0, r3
|
|
8003362: f003 f955 bl 8006610 <USB_HC_Halt>
|
|
8003366: e062 b.n 800342e <HCD_HC_OUT_IRQHandler+0x534>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
8003368: 78fa ldrb r2, [r7, #3]
|
|
800336a: 6879 ldr r1, [r7, #4]
|
|
800336c: 4613 mov r3, r2
|
|
800336e: 011b lsls r3, r3, #4
|
|
8003370: 1a9b subs r3, r3, r2
|
|
8003372: 009b lsls r3, r3, #2
|
|
8003374: 440b add r3, r1
|
|
8003376: 3344 adds r3, #68 @ 0x44
|
|
8003378: 681b ldr r3, [r3, #0]
|
|
800337a: 1c59 adds r1, r3, #1
|
|
800337c: 6878 ldr r0, [r7, #4]
|
|
800337e: 4613 mov r3, r2
|
|
8003380: 011b lsls r3, r3, #4
|
|
8003382: 1a9b subs r3, r3, r2
|
|
8003384: 009b lsls r3, r3, #2
|
|
8003386: 4403 add r3, r0
|
|
8003388: 3344 adds r3, #68 @ 0x44
|
|
800338a: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
800338c: 78fa ldrb r2, [r7, #3]
|
|
800338e: 6879 ldr r1, [r7, #4]
|
|
8003390: 4613 mov r3, r2
|
|
8003392: 011b lsls r3, r3, #4
|
|
8003394: 1a9b subs r3, r3, r2
|
|
8003396: 009b lsls r3, r3, #2
|
|
8003398: 440b add r3, r1
|
|
800339a: 3344 adds r3, #68 @ 0x44
|
|
800339c: 681b ldr r3, [r3, #0]
|
|
800339e: 2b02 cmp r3, #2
|
|
80033a0: d922 bls.n 80033e8 <HCD_HC_OUT_IRQHandler+0x4ee>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80033a2: 78fa ldrb r2, [r7, #3]
|
|
80033a4: 6879 ldr r1, [r7, #4]
|
|
80033a6: 4613 mov r3, r2
|
|
80033a8: 011b lsls r3, r3, #4
|
|
80033aa: 1a9b subs r3, r3, r2
|
|
80033ac: 009b lsls r3, r3, #2
|
|
80033ae: 440b add r3, r1
|
|
80033b0: 3344 adds r3, #68 @ 0x44
|
|
80033b2: 2200 movs r2, #0
|
|
80033b4: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
80033b6: 78fa ldrb r2, [r7, #3]
|
|
80033b8: 6879 ldr r1, [r7, #4]
|
|
80033ba: 4613 mov r3, r2
|
|
80033bc: 011b lsls r3, r3, #4
|
|
80033be: 1a9b subs r3, r3, r2
|
|
80033c0: 009b lsls r3, r3, #2
|
|
80033c2: 440b add r3, r1
|
|
80033c4: 334c adds r3, #76 @ 0x4c
|
|
80033c6: 2204 movs r2, #4
|
|
80033c8: 701a strb r2, [r3, #0]
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
80033ca: 78fa ldrb r2, [r7, #3]
|
|
80033cc: 6879 ldr r1, [r7, #4]
|
|
80033ce: 4613 mov r3, r2
|
|
80033d0: 011b lsls r3, r3, #4
|
|
80033d2: 1a9b subs r3, r3, r2
|
|
80033d4: 009b lsls r3, r3, #2
|
|
80033d6: 440b add r3, r1
|
|
80033d8: 334c adds r3, #76 @ 0x4c
|
|
80033da: 781a ldrb r2, [r3, #0]
|
|
80033dc: 78fb ldrb r3, [r7, #3]
|
|
80033de: 4619 mov r1, r3
|
|
80033e0: 6878 ldr r0, [r7, #4]
|
|
80033e2: f004 fca7 bl 8007d34 <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
80033e6: e022 b.n 800342e <HCD_HC_OUT_IRQHandler+0x534>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
80033e8: 78fa ldrb r2, [r7, #3]
|
|
80033ea: 6879 ldr r1, [r7, #4]
|
|
80033ec: 4613 mov r3, r2
|
|
80033ee: 011b lsls r3, r3, #4
|
|
80033f0: 1a9b subs r3, r3, r2
|
|
80033f2: 009b lsls r3, r3, #2
|
|
80033f4: 440b add r3, r1
|
|
80033f6: 334c adds r3, #76 @ 0x4c
|
|
80033f8: 2202 movs r2, #2
|
|
80033fa: 701a strb r2, [r3, #0]
|
|
|
|
/* Re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
80033fc: 78fb ldrb r3, [r7, #3]
|
|
80033fe: 015a lsls r2, r3, #5
|
|
8003400: 693b ldr r3, [r7, #16]
|
|
8003402: 4413 add r3, r2
|
|
8003404: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003408: 681b ldr r3, [r3, #0]
|
|
800340a: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
800340c: 68fb ldr r3, [r7, #12]
|
|
800340e: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003412: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8003414: 68fb ldr r3, [r7, #12]
|
|
8003416: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800341a: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
800341c: 78fb ldrb r3, [r7, #3]
|
|
800341e: 015a lsls r2, r3, #5
|
|
8003420: 693b ldr r3, [r7, #16]
|
|
8003422: 4413 add r3, r2
|
|
8003424: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003428: 461a mov r2, r3
|
|
800342a: 68fb ldr r3, [r7, #12]
|
|
800342c: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
|
|
800342e: 78fb ldrb r3, [r7, #3]
|
|
8003430: 015a lsls r2, r3, #5
|
|
8003432: 693b ldr r3, [r7, #16]
|
|
8003434: 4413 add r3, r2
|
|
8003436: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800343a: 461a mov r2, r3
|
|
800343c: 2380 movs r3, #128 @ 0x80
|
|
800343e: 6093 str r3, [r2, #8]
|
|
8003440: e217 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
|
|
8003442: 687b ldr r3, [r7, #4]
|
|
8003444: 681b ldr r3, [r3, #0]
|
|
8003446: 78fa ldrb r2, [r7, #3]
|
|
8003448: 4611 mov r1, r2
|
|
800344a: 4618 mov r0, r3
|
|
800344c: f003 f863 bl 8006516 <USB_ReadChInterrupts>
|
|
8003450: 4603 mov r3, r0
|
|
8003452: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003456: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800345a: d11b bne.n 8003494 <HCD_HC_OUT_IRQHandler+0x59a>
|
|
{
|
|
hhcd->hc[chnum].state = HC_DATATGLERR;
|
|
800345c: 78fa ldrb r2, [r7, #3]
|
|
800345e: 6879 ldr r1, [r7, #4]
|
|
8003460: 4613 mov r3, r2
|
|
8003462: 011b lsls r3, r3, #4
|
|
8003464: 1a9b subs r3, r3, r2
|
|
8003466: 009b lsls r3, r3, #2
|
|
8003468: 440b add r3, r1
|
|
800346a: 334d adds r3, #77 @ 0x4d
|
|
800346c: 2209 movs r2, #9
|
|
800346e: 701a strb r2, [r3, #0]
|
|
(void)USB_HC_Halt(hhcd->Instance, chnum);
|
|
8003470: 687b ldr r3, [r7, #4]
|
|
8003472: 681b ldr r3, [r3, #0]
|
|
8003474: 78fa ldrb r2, [r7, #3]
|
|
8003476: 4611 mov r1, r2
|
|
8003478: 4618 mov r0, r3
|
|
800347a: f003 f8c9 bl 8006610 <USB_HC_Halt>
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
|
|
800347e: 78fb ldrb r3, [r7, #3]
|
|
8003480: 015a lsls r2, r3, #5
|
|
8003482: 693b ldr r3, [r7, #16]
|
|
8003484: 4413 add r3, r2
|
|
8003486: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800348a: 461a mov r2, r3
|
|
800348c: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8003490: 6093 str r3, [r2, #8]
|
|
8003492: e1ee b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
}
|
|
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
|
|
8003494: 687b ldr r3, [r7, #4]
|
|
8003496: 681b ldr r3, [r3, #0]
|
|
8003498: 78fa ldrb r2, [r7, #3]
|
|
800349a: 4611 mov r1, r2
|
|
800349c: 4618 mov r0, r3
|
|
800349e: f003 f83a bl 8006516 <USB_ReadChInterrupts>
|
|
80034a2: 4603 mov r3, r0
|
|
80034a4: f003 0302 and.w r3, r3, #2
|
|
80034a8: 2b02 cmp r3, #2
|
|
80034aa: f040 81df bne.w 800386c <HCD_HC_OUT_IRQHandler+0x972>
|
|
{
|
|
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
|
|
80034ae: 78fb ldrb r3, [r7, #3]
|
|
80034b0: 015a lsls r2, r3, #5
|
|
80034b2: 693b ldr r3, [r7, #16]
|
|
80034b4: 4413 add r3, r2
|
|
80034b6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80034ba: 461a mov r2, r3
|
|
80034bc: 2302 movs r3, #2
|
|
80034be: 6093 str r3, [r2, #8]
|
|
|
|
if (hhcd->hc[chnum].state == HC_XFRC)
|
|
80034c0: 78fa ldrb r2, [r7, #3]
|
|
80034c2: 6879 ldr r1, [r7, #4]
|
|
80034c4: 4613 mov r3, r2
|
|
80034c6: 011b lsls r3, r3, #4
|
|
80034c8: 1a9b subs r3, r3, r2
|
|
80034ca: 009b lsls r3, r3, #2
|
|
80034cc: 440b add r3, r1
|
|
80034ce: 334d adds r3, #77 @ 0x4d
|
|
80034d0: 781b ldrb r3, [r3, #0]
|
|
80034d2: 2b01 cmp r3, #1
|
|
80034d4: f040 8093 bne.w 80035fe <HCD_HC_OUT_IRQHandler+0x704>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
80034d8: 78fa ldrb r2, [r7, #3]
|
|
80034da: 6879 ldr r1, [r7, #4]
|
|
80034dc: 4613 mov r3, r2
|
|
80034de: 011b lsls r3, r3, #4
|
|
80034e0: 1a9b subs r3, r3, r2
|
|
80034e2: 009b lsls r3, r3, #2
|
|
80034e4: 440b add r3, r1
|
|
80034e6: 334d adds r3, #77 @ 0x4d
|
|
80034e8: 2202 movs r2, #2
|
|
80034ea: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_DONE;
|
|
80034ec: 78fa ldrb r2, [r7, #3]
|
|
80034ee: 6879 ldr r1, [r7, #4]
|
|
80034f0: 4613 mov r3, r2
|
|
80034f2: 011b lsls r3, r3, #4
|
|
80034f4: 1a9b subs r3, r3, r2
|
|
80034f6: 009b lsls r3, r3, #2
|
|
80034f8: 440b add r3, r1
|
|
80034fa: 334c adds r3, #76 @ 0x4c
|
|
80034fc: 2201 movs r2, #1
|
|
80034fe: 701a strb r2, [r3, #0]
|
|
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
|
|
8003500: 78fa ldrb r2, [r7, #3]
|
|
8003502: 6879 ldr r1, [r7, #4]
|
|
8003504: 4613 mov r3, r2
|
|
8003506: 011b lsls r3, r3, #4
|
|
8003508: 1a9b subs r3, r3, r2
|
|
800350a: 009b lsls r3, r3, #2
|
|
800350c: 440b add r3, r1
|
|
800350e: 3326 adds r3, #38 @ 0x26
|
|
8003510: 781b ldrb r3, [r3, #0]
|
|
8003512: 2b02 cmp r3, #2
|
|
8003514: d00b beq.n 800352e <HCD_HC_OUT_IRQHandler+0x634>
|
|
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
|
|
8003516: 78fa ldrb r2, [r7, #3]
|
|
8003518: 6879 ldr r1, [r7, #4]
|
|
800351a: 4613 mov r3, r2
|
|
800351c: 011b lsls r3, r3, #4
|
|
800351e: 1a9b subs r3, r3, r2
|
|
8003520: 009b lsls r3, r3, #2
|
|
8003522: 440b add r3, r1
|
|
8003524: 3326 adds r3, #38 @ 0x26
|
|
8003526: 781b ldrb r3, [r3, #0]
|
|
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
|
|
8003528: 2b03 cmp r3, #3
|
|
800352a: f040 8190 bne.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
if (hhcd->Init.dma_enable == 0U)
|
|
800352e: 687b ldr r3, [r7, #4]
|
|
8003530: 799b ldrb r3, [r3, #6]
|
|
8003532: 2b00 cmp r3, #0
|
|
8003534: d115 bne.n 8003562 <HCD_HC_OUT_IRQHandler+0x668>
|
|
{
|
|
hhcd->hc[chnum].toggle_out ^= 1U;
|
|
8003536: 78fa ldrb r2, [r7, #3]
|
|
8003538: 6879 ldr r1, [r7, #4]
|
|
800353a: 4613 mov r3, r2
|
|
800353c: 011b lsls r3, r3, #4
|
|
800353e: 1a9b subs r3, r3, r2
|
|
8003540: 009b lsls r3, r3, #2
|
|
8003542: 440b add r3, r1
|
|
8003544: 333d adds r3, #61 @ 0x3d
|
|
8003546: 781b ldrb r3, [r3, #0]
|
|
8003548: 78fa ldrb r2, [r7, #3]
|
|
800354a: f083 0301 eor.w r3, r3, #1
|
|
800354e: b2d8 uxtb r0, r3
|
|
8003550: 6879 ldr r1, [r7, #4]
|
|
8003552: 4613 mov r3, r2
|
|
8003554: 011b lsls r3, r3, #4
|
|
8003556: 1a9b subs r3, r3, r2
|
|
8003558: 009b lsls r3, r3, #2
|
|
800355a: 440b add r3, r1
|
|
800355c: 333d adds r3, #61 @ 0x3d
|
|
800355e: 4602 mov r2, r0
|
|
8003560: 701a strb r2, [r3, #0]
|
|
}
|
|
|
|
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
|
|
8003562: 687b ldr r3, [r7, #4]
|
|
8003564: 799b ldrb r3, [r3, #6]
|
|
8003566: 2b01 cmp r3, #1
|
|
8003568: f040 8171 bne.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
800356c: 78fa ldrb r2, [r7, #3]
|
|
800356e: 6879 ldr r1, [r7, #4]
|
|
8003570: 4613 mov r3, r2
|
|
8003572: 011b lsls r3, r3, #4
|
|
8003574: 1a9b subs r3, r3, r2
|
|
8003576: 009b lsls r3, r3, #2
|
|
8003578: 440b add r3, r1
|
|
800357a: 3334 adds r3, #52 @ 0x34
|
|
800357c: 681b ldr r3, [r3, #0]
|
|
800357e: 2b00 cmp r3, #0
|
|
8003580: f000 8165 beq.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
|
|
8003584: 78fa ldrb r2, [r7, #3]
|
|
8003586: 6879 ldr r1, [r7, #4]
|
|
8003588: 4613 mov r3, r2
|
|
800358a: 011b lsls r3, r3, #4
|
|
800358c: 1a9b subs r3, r3, r2
|
|
800358e: 009b lsls r3, r3, #2
|
|
8003590: 440b add r3, r1
|
|
8003592: 3334 adds r3, #52 @ 0x34
|
|
8003594: 6819 ldr r1, [r3, #0]
|
|
8003596: 78fa ldrb r2, [r7, #3]
|
|
8003598: 6878 ldr r0, [r7, #4]
|
|
800359a: 4613 mov r3, r2
|
|
800359c: 011b lsls r3, r3, #4
|
|
800359e: 1a9b subs r3, r3, r2
|
|
80035a0: 009b lsls r3, r3, #2
|
|
80035a2: 4403 add r3, r0
|
|
80035a4: 3328 adds r3, #40 @ 0x28
|
|
80035a6: 881b ldrh r3, [r3, #0]
|
|
80035a8: 440b add r3, r1
|
|
80035aa: 1e59 subs r1, r3, #1
|
|
80035ac: 78fa ldrb r2, [r7, #3]
|
|
80035ae: 6878 ldr r0, [r7, #4]
|
|
80035b0: 4613 mov r3, r2
|
|
80035b2: 011b lsls r3, r3, #4
|
|
80035b4: 1a9b subs r3, r3, r2
|
|
80035b6: 009b lsls r3, r3, #2
|
|
80035b8: 4403 add r3, r0
|
|
80035ba: 3328 adds r3, #40 @ 0x28
|
|
80035bc: 881b ldrh r3, [r3, #0]
|
|
80035be: fbb1 f3f3 udiv r3, r1, r3
|
|
80035c2: 60bb str r3, [r7, #8]
|
|
|
|
if ((num_packets & 1U) != 0U)
|
|
80035c4: 68bb ldr r3, [r7, #8]
|
|
80035c6: f003 0301 and.w r3, r3, #1
|
|
80035ca: 2b00 cmp r3, #0
|
|
80035cc: f000 813f beq.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].toggle_out ^= 1U;
|
|
80035d0: 78fa ldrb r2, [r7, #3]
|
|
80035d2: 6879 ldr r1, [r7, #4]
|
|
80035d4: 4613 mov r3, r2
|
|
80035d6: 011b lsls r3, r3, #4
|
|
80035d8: 1a9b subs r3, r3, r2
|
|
80035da: 009b lsls r3, r3, #2
|
|
80035dc: 440b add r3, r1
|
|
80035de: 333d adds r3, #61 @ 0x3d
|
|
80035e0: 781b ldrb r3, [r3, #0]
|
|
80035e2: 78fa ldrb r2, [r7, #3]
|
|
80035e4: f083 0301 eor.w r3, r3, #1
|
|
80035e8: b2d8 uxtb r0, r3
|
|
80035ea: 6879 ldr r1, [r7, #4]
|
|
80035ec: 4613 mov r3, r2
|
|
80035ee: 011b lsls r3, r3, #4
|
|
80035f0: 1a9b subs r3, r3, r2
|
|
80035f2: 009b lsls r3, r3, #2
|
|
80035f4: 440b add r3, r1
|
|
80035f6: 333d adds r3, #61 @ 0x3d
|
|
80035f8: 4602 mov r2, r0
|
|
80035fa: 701a strb r2, [r3, #0]
|
|
80035fc: e127 b.n 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_ACK)
|
|
80035fe: 78fa ldrb r2, [r7, #3]
|
|
8003600: 6879 ldr r1, [r7, #4]
|
|
8003602: 4613 mov r3, r2
|
|
8003604: 011b lsls r3, r3, #4
|
|
8003606: 1a9b subs r3, r3, r2
|
|
8003608: 009b lsls r3, r3, #2
|
|
800360a: 440b add r3, r1
|
|
800360c: 334d adds r3, #77 @ 0x4d
|
|
800360e: 781b ldrb r3, [r3, #0]
|
|
8003610: 2b03 cmp r3, #3
|
|
8003612: d120 bne.n 8003656 <HCD_HC_OUT_IRQHandler+0x75c>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003614: 78fa ldrb r2, [r7, #3]
|
|
8003616: 6879 ldr r1, [r7, #4]
|
|
8003618: 4613 mov r3, r2
|
|
800361a: 011b lsls r3, r3, #4
|
|
800361c: 1a9b subs r3, r3, r2
|
|
800361e: 009b lsls r3, r3, #2
|
|
8003620: 440b add r3, r1
|
|
8003622: 334d adds r3, #77 @ 0x4d
|
|
8003624: 2202 movs r2, #2
|
|
8003626: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003628: 78fa ldrb r2, [r7, #3]
|
|
800362a: 6879 ldr r1, [r7, #4]
|
|
800362c: 4613 mov r3, r2
|
|
800362e: 011b lsls r3, r3, #4
|
|
8003630: 1a9b subs r3, r3, r2
|
|
8003632: 009b lsls r3, r3, #2
|
|
8003634: 440b add r3, r1
|
|
8003636: 331b adds r3, #27
|
|
8003638: 781b ldrb r3, [r3, #0]
|
|
800363a: 2b01 cmp r3, #1
|
|
800363c: f040 8107 bne.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003640: 78fa ldrb r2, [r7, #3]
|
|
8003642: 6879 ldr r1, [r7, #4]
|
|
8003644: 4613 mov r3, r2
|
|
8003646: 011b lsls r3, r3, #4
|
|
8003648: 1a9b subs r3, r3, r2
|
|
800364a: 009b lsls r3, r3, #2
|
|
800364c: 440b add r3, r1
|
|
800364e: 334c adds r3, #76 @ 0x4c
|
|
8003650: 2202 movs r2, #2
|
|
8003652: 701a strb r2, [r3, #0]
|
|
8003654: e0fb b.n 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NAK)
|
|
8003656: 78fa ldrb r2, [r7, #3]
|
|
8003658: 6879 ldr r1, [r7, #4]
|
|
800365a: 4613 mov r3, r2
|
|
800365c: 011b lsls r3, r3, #4
|
|
800365e: 1a9b subs r3, r3, r2
|
|
8003660: 009b lsls r3, r3, #2
|
|
8003662: 440b add r3, r1
|
|
8003664: 334d adds r3, #77 @ 0x4d
|
|
8003666: 781b ldrb r3, [r3, #0]
|
|
8003668: 2b04 cmp r3, #4
|
|
800366a: d13a bne.n 80036e2 <HCD_HC_OUT_IRQHandler+0x7e8>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
800366c: 78fa ldrb r2, [r7, #3]
|
|
800366e: 6879 ldr r1, [r7, #4]
|
|
8003670: 4613 mov r3, r2
|
|
8003672: 011b lsls r3, r3, #4
|
|
8003674: 1a9b subs r3, r3, r2
|
|
8003676: 009b lsls r3, r3, #2
|
|
8003678: 440b add r3, r1
|
|
800367a: 334d adds r3, #77 @ 0x4d
|
|
800367c: 2202 movs r2, #2
|
|
800367e: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003680: 78fa ldrb r2, [r7, #3]
|
|
8003682: 6879 ldr r1, [r7, #4]
|
|
8003684: 4613 mov r3, r2
|
|
8003686: 011b lsls r3, r3, #4
|
|
8003688: 1a9b subs r3, r3, r2
|
|
800368a: 009b lsls r3, r3, #2
|
|
800368c: 440b add r3, r1
|
|
800368e: 334c adds r3, #76 @ 0x4c
|
|
8003690: 2202 movs r2, #2
|
|
8003692: 701a strb r2, [r3, #0]
|
|
|
|
if (hhcd->hc[chnum].do_csplit == 1U)
|
|
8003694: 78fa ldrb r2, [r7, #3]
|
|
8003696: 6879 ldr r1, [r7, #4]
|
|
8003698: 4613 mov r3, r2
|
|
800369a: 011b lsls r3, r3, #4
|
|
800369c: 1a9b subs r3, r3, r2
|
|
800369e: 009b lsls r3, r3, #2
|
|
80036a0: 440b add r3, r1
|
|
80036a2: 331b adds r3, #27
|
|
80036a4: 781b ldrb r3, [r3, #0]
|
|
80036a6: 2b01 cmp r3, #1
|
|
80036a8: f040 80d1 bne.w 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
{
|
|
hhcd->hc[chnum].do_csplit = 0U;
|
|
80036ac: 78fa ldrb r2, [r7, #3]
|
|
80036ae: 6879 ldr r1, [r7, #4]
|
|
80036b0: 4613 mov r3, r2
|
|
80036b2: 011b lsls r3, r3, #4
|
|
80036b4: 1a9b subs r3, r3, r2
|
|
80036b6: 009b lsls r3, r3, #2
|
|
80036b8: 440b add r3, r1
|
|
80036ba: 331b adds r3, #27
|
|
80036bc: 2200 movs r2, #0
|
|
80036be: 701a strb r2, [r3, #0]
|
|
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
|
|
80036c0: 78fb ldrb r3, [r7, #3]
|
|
80036c2: 015a lsls r2, r3, #5
|
|
80036c4: 693b ldr r3, [r7, #16]
|
|
80036c6: 4413 add r3, r2
|
|
80036c8: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80036cc: 685b ldr r3, [r3, #4]
|
|
80036ce: 78fa ldrb r2, [r7, #3]
|
|
80036d0: 0151 lsls r1, r2, #5
|
|
80036d2: 693a ldr r2, [r7, #16]
|
|
80036d4: 440a add r2, r1
|
|
80036d6: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80036da: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
80036de: 6053 str r3, [r2, #4]
|
|
80036e0: e0b5 b.n 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_NYET)
|
|
80036e2: 78fa ldrb r2, [r7, #3]
|
|
80036e4: 6879 ldr r1, [r7, #4]
|
|
80036e6: 4613 mov r3, r2
|
|
80036e8: 011b lsls r3, r3, #4
|
|
80036ea: 1a9b subs r3, r3, r2
|
|
80036ec: 009b lsls r3, r3, #2
|
|
80036ee: 440b add r3, r1
|
|
80036f0: 334d adds r3, #77 @ 0x4d
|
|
80036f2: 781b ldrb r3, [r3, #0]
|
|
80036f4: 2b05 cmp r3, #5
|
|
80036f6: d114 bne.n 8003722 <HCD_HC_OUT_IRQHandler+0x828>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
80036f8: 78fa ldrb r2, [r7, #3]
|
|
80036fa: 6879 ldr r1, [r7, #4]
|
|
80036fc: 4613 mov r3, r2
|
|
80036fe: 011b lsls r3, r3, #4
|
|
8003700: 1a9b subs r3, r3, r2
|
|
8003702: 009b lsls r3, r3, #2
|
|
8003704: 440b add r3, r1
|
|
8003706: 334d adds r3, #77 @ 0x4d
|
|
8003708: 2202 movs r2, #2
|
|
800370a: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
800370c: 78fa ldrb r2, [r7, #3]
|
|
800370e: 6879 ldr r1, [r7, #4]
|
|
8003710: 4613 mov r3, r2
|
|
8003712: 011b lsls r3, r3, #4
|
|
8003714: 1a9b subs r3, r3, r2
|
|
8003716: 009b lsls r3, r3, #2
|
|
8003718: 440b add r3, r1
|
|
800371a: 334c adds r3, #76 @ 0x4c
|
|
800371c: 2202 movs r2, #2
|
|
800371e: 701a strb r2, [r3, #0]
|
|
8003720: e095 b.n 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
else if (hhcd->hc[chnum].state == HC_STALL)
|
|
8003722: 78fa ldrb r2, [r7, #3]
|
|
8003724: 6879 ldr r1, [r7, #4]
|
|
8003726: 4613 mov r3, r2
|
|
8003728: 011b lsls r3, r3, #4
|
|
800372a: 1a9b subs r3, r3, r2
|
|
800372c: 009b lsls r3, r3, #2
|
|
800372e: 440b add r3, r1
|
|
8003730: 334d adds r3, #77 @ 0x4d
|
|
8003732: 781b ldrb r3, [r3, #0]
|
|
8003734: 2b06 cmp r3, #6
|
|
8003736: d114 bne.n 8003762 <HCD_HC_OUT_IRQHandler+0x868>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
8003738: 78fa ldrb r2, [r7, #3]
|
|
800373a: 6879 ldr r1, [r7, #4]
|
|
800373c: 4613 mov r3, r2
|
|
800373e: 011b lsls r3, r3, #4
|
|
8003740: 1a9b subs r3, r3, r2
|
|
8003742: 009b lsls r3, r3, #2
|
|
8003744: 440b add r3, r1
|
|
8003746: 334d adds r3, #77 @ 0x4d
|
|
8003748: 2202 movs r2, #2
|
|
800374a: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_STALL;
|
|
800374c: 78fa ldrb r2, [r7, #3]
|
|
800374e: 6879 ldr r1, [r7, #4]
|
|
8003750: 4613 mov r3, r2
|
|
8003752: 011b lsls r3, r3, #4
|
|
8003754: 1a9b subs r3, r3, r2
|
|
8003756: 009b lsls r3, r3, #2
|
|
8003758: 440b add r3, r1
|
|
800375a: 334c adds r3, #76 @ 0x4c
|
|
800375c: 2205 movs r2, #5
|
|
800375e: 701a strb r2, [r3, #0]
|
|
8003760: e075 b.n 800384e <HCD_HC_OUT_IRQHandler+0x954>
|
|
}
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
8003762: 78fa ldrb r2, [r7, #3]
|
|
8003764: 6879 ldr r1, [r7, #4]
|
|
8003766: 4613 mov r3, r2
|
|
8003768: 011b lsls r3, r3, #4
|
|
800376a: 1a9b subs r3, r3, r2
|
|
800376c: 009b lsls r3, r3, #2
|
|
800376e: 440b add r3, r1
|
|
8003770: 334d adds r3, #77 @ 0x4d
|
|
8003772: 781b ldrb r3, [r3, #0]
|
|
8003774: 2b07 cmp r3, #7
|
|
8003776: d00a beq.n 800378e <HCD_HC_OUT_IRQHandler+0x894>
|
|
(hhcd->hc[chnum].state == HC_DATATGLERR))
|
|
8003778: 78fa ldrb r2, [r7, #3]
|
|
800377a: 6879 ldr r1, [r7, #4]
|
|
800377c: 4613 mov r3, r2
|
|
800377e: 011b lsls r3, r3, #4
|
|
8003780: 1a9b subs r3, r3, r2
|
|
8003782: 009b lsls r3, r3, #2
|
|
8003784: 440b add r3, r1
|
|
8003786: 334d adds r3, #77 @ 0x4d
|
|
8003788: 781b ldrb r3, [r3, #0]
|
|
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
|
|
800378a: 2b09 cmp r3, #9
|
|
800378c: d170 bne.n 8003870 <HCD_HC_OUT_IRQHandler+0x976>
|
|
{
|
|
hhcd->hc[chnum].state = HC_HALTED;
|
|
800378e: 78fa ldrb r2, [r7, #3]
|
|
8003790: 6879 ldr r1, [r7, #4]
|
|
8003792: 4613 mov r3, r2
|
|
8003794: 011b lsls r3, r3, #4
|
|
8003796: 1a9b subs r3, r3, r2
|
|
8003798: 009b lsls r3, r3, #2
|
|
800379a: 440b add r3, r1
|
|
800379c: 334d adds r3, #77 @ 0x4d
|
|
800379e: 2202 movs r2, #2
|
|
80037a0: 701a strb r2, [r3, #0]
|
|
hhcd->hc[chnum].ErrCnt++;
|
|
80037a2: 78fa ldrb r2, [r7, #3]
|
|
80037a4: 6879 ldr r1, [r7, #4]
|
|
80037a6: 4613 mov r3, r2
|
|
80037a8: 011b lsls r3, r3, #4
|
|
80037aa: 1a9b subs r3, r3, r2
|
|
80037ac: 009b lsls r3, r3, #2
|
|
80037ae: 440b add r3, r1
|
|
80037b0: 3344 adds r3, #68 @ 0x44
|
|
80037b2: 681b ldr r3, [r3, #0]
|
|
80037b4: 1c59 adds r1, r3, #1
|
|
80037b6: 6878 ldr r0, [r7, #4]
|
|
80037b8: 4613 mov r3, r2
|
|
80037ba: 011b lsls r3, r3, #4
|
|
80037bc: 1a9b subs r3, r3, r2
|
|
80037be: 009b lsls r3, r3, #2
|
|
80037c0: 4403 add r3, r0
|
|
80037c2: 3344 adds r3, #68 @ 0x44
|
|
80037c4: 6019 str r1, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
80037c6: 78fa ldrb r2, [r7, #3]
|
|
80037c8: 6879 ldr r1, [r7, #4]
|
|
80037ca: 4613 mov r3, r2
|
|
80037cc: 011b lsls r3, r3, #4
|
|
80037ce: 1a9b subs r3, r3, r2
|
|
80037d0: 009b lsls r3, r3, #2
|
|
80037d2: 440b add r3, r1
|
|
80037d4: 3344 adds r3, #68 @ 0x44
|
|
80037d6: 681b ldr r3, [r3, #0]
|
|
80037d8: 2b02 cmp r3, #2
|
|
80037da: d914 bls.n 8003806 <HCD_HC_OUT_IRQHandler+0x90c>
|
|
{
|
|
hhcd->hc[chnum].ErrCnt = 0U;
|
|
80037dc: 78fa ldrb r2, [r7, #3]
|
|
80037de: 6879 ldr r1, [r7, #4]
|
|
80037e0: 4613 mov r3, r2
|
|
80037e2: 011b lsls r3, r3, #4
|
|
80037e4: 1a9b subs r3, r3, r2
|
|
80037e6: 009b lsls r3, r3, #2
|
|
80037e8: 440b add r3, r1
|
|
80037ea: 3344 adds r3, #68 @ 0x44
|
|
80037ec: 2200 movs r2, #0
|
|
80037ee: 601a str r2, [r3, #0]
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
80037f0: 78fa ldrb r2, [r7, #3]
|
|
80037f2: 6879 ldr r1, [r7, #4]
|
|
80037f4: 4613 mov r3, r2
|
|
80037f6: 011b lsls r3, r3, #4
|
|
80037f8: 1a9b subs r3, r3, r2
|
|
80037fa: 009b lsls r3, r3, #2
|
|
80037fc: 440b add r3, r1
|
|
80037fe: 334c adds r3, #76 @ 0x4c
|
|
8003800: 2204 movs r2, #4
|
|
8003802: 701a strb r2, [r3, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
8003804: e022 b.n 800384c <HCD_HC_OUT_IRQHandler+0x952>
|
|
}
|
|
else
|
|
{
|
|
hhcd->hc[chnum].urb_state = URB_NOTREADY;
|
|
8003806: 78fa ldrb r2, [r7, #3]
|
|
8003808: 6879 ldr r1, [r7, #4]
|
|
800380a: 4613 mov r3, r2
|
|
800380c: 011b lsls r3, r3, #4
|
|
800380e: 1a9b subs r3, r3, r2
|
|
8003810: 009b lsls r3, r3, #2
|
|
8003812: 440b add r3, r1
|
|
8003814: 334c adds r3, #76 @ 0x4c
|
|
8003816: 2202 movs r2, #2
|
|
8003818: 701a strb r2, [r3, #0]
|
|
|
|
/* re-activate the channel */
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
800381a: 78fb ldrb r3, [r7, #3]
|
|
800381c: 015a lsls r2, r3, #5
|
|
800381e: 693b ldr r3, [r7, #16]
|
|
8003820: 4413 add r3, r2
|
|
8003822: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003826: 681b ldr r3, [r3, #0]
|
|
8003828: 60fb str r3, [r7, #12]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
800382a: 68fb ldr r3, [r7, #12]
|
|
800382c: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
8003830: 60fb str r3, [r7, #12]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
8003832: 68fb ldr r3, [r7, #12]
|
|
8003834: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8003838: 60fb str r3, [r7, #12]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
800383a: 78fb ldrb r3, [r7, #3]
|
|
800383c: 015a lsls r2, r3, #5
|
|
800383e: 693b ldr r3, [r7, #16]
|
|
8003840: 4413 add r3, r2
|
|
8003842: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003846: 461a mov r2, r3
|
|
8003848: 68fb ldr r3, [r7, #12]
|
|
800384a: 6013 str r3, [r2, #0]
|
|
if (hhcd->hc[chnum].ErrCnt > 2U)
|
|
800384c: bf00 nop
|
|
}
|
|
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
#else
|
|
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
|
|
800384e: 78fa ldrb r2, [r7, #3]
|
|
8003850: 6879 ldr r1, [r7, #4]
|
|
8003852: 4613 mov r3, r2
|
|
8003854: 011b lsls r3, r3, #4
|
|
8003856: 1a9b subs r3, r3, r2
|
|
8003858: 009b lsls r3, r3, #2
|
|
800385a: 440b add r3, r1
|
|
800385c: 334c adds r3, #76 @ 0x4c
|
|
800385e: 781a ldrb r2, [r3, #0]
|
|
8003860: 78fb ldrb r3, [r7, #3]
|
|
8003862: 4619 mov r1, r3
|
|
8003864: 6878 ldr r0, [r7, #4]
|
|
8003866: f004 fa65 bl 8007d34 <HAL_HCD_HC_NotifyURBChange_Callback>
|
|
800386a: e002 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
else
|
|
{
|
|
return;
|
|
800386c: bf00 nop
|
|
800386e: e000 b.n 8003872 <HCD_HC_OUT_IRQHandler+0x978>
|
|
return;
|
|
8003870: bf00 nop
|
|
}
|
|
}
|
|
8003872: 3718 adds r7, #24
|
|
8003874: 46bd mov sp, r7
|
|
8003876: bd80 pop {r7, pc}
|
|
|
|
08003878 <HCD_RXQLVL_IRQHandler>:
|
|
* @brief Handle Rx Queue Level interrupt requests.
|
|
* @param hhcd HCD handle
|
|
* @retval none
|
|
*/
|
|
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8003878: b580 push {r7, lr}
|
|
800387a: b08a sub sp, #40 @ 0x28
|
|
800387c: af00 add r7, sp, #0
|
|
800387e: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8003880: 687b ldr r3, [r7, #4]
|
|
8003882: 681b ldr r3, [r3, #0]
|
|
8003884: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003886: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8003888: 623b str r3, [r7, #32]
|
|
uint32_t GrxstspReg;
|
|
uint32_t xferSizePktCnt;
|
|
uint32_t tmpreg;
|
|
uint32_t chnum;
|
|
|
|
GrxstspReg = hhcd->Instance->GRXSTSP;
|
|
800388a: 687b ldr r3, [r7, #4]
|
|
800388c: 681b ldr r3, [r3, #0]
|
|
800388e: 6a1b ldr r3, [r3, #32]
|
|
8003890: 61fb str r3, [r7, #28]
|
|
chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
|
|
8003892: 69fb ldr r3, [r7, #28]
|
|
8003894: f003 030f and.w r3, r3, #15
|
|
8003898: 61bb str r3, [r7, #24]
|
|
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
|
|
800389a: 69fb ldr r3, [r7, #28]
|
|
800389c: 0c5b lsrs r3, r3, #17
|
|
800389e: f003 030f and.w r3, r3, #15
|
|
80038a2: 617b str r3, [r7, #20]
|
|
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
|
|
80038a4: 69fb ldr r3, [r7, #28]
|
|
80038a6: 091b lsrs r3, r3, #4
|
|
80038a8: f3c3 030a ubfx r3, r3, #0, #11
|
|
80038ac: 613b str r3, [r7, #16]
|
|
|
|
switch (pktsts)
|
|
80038ae: 697b ldr r3, [r7, #20]
|
|
80038b0: 2b02 cmp r3, #2
|
|
80038b2: d004 beq.n 80038be <HCD_RXQLVL_IRQHandler+0x46>
|
|
80038b4: 697b ldr r3, [r7, #20]
|
|
80038b6: 2b05 cmp r3, #5
|
|
80038b8: f000 80b6 beq.w 8003a28 <HCD_RXQLVL_IRQHandler+0x1b0>
|
|
break;
|
|
|
|
case GRXSTS_PKTSTS_IN_XFER_COMP:
|
|
case GRXSTS_PKTSTS_CH_HALTED:
|
|
default:
|
|
break;
|
|
80038bc: e0b7 b.n 8003a2e <HCD_RXQLVL_IRQHandler+0x1b6>
|
|
if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
|
|
80038be: 693b ldr r3, [r7, #16]
|
|
80038c0: 2b00 cmp r3, #0
|
|
80038c2: f000 80b3 beq.w 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
80038c6: 6879 ldr r1, [r7, #4]
|
|
80038c8: 69ba ldr r2, [r7, #24]
|
|
80038ca: 4613 mov r3, r2
|
|
80038cc: 011b lsls r3, r3, #4
|
|
80038ce: 1a9b subs r3, r3, r2
|
|
80038d0: 009b lsls r3, r3, #2
|
|
80038d2: 440b add r3, r1
|
|
80038d4: 332c adds r3, #44 @ 0x2c
|
|
80038d6: 681b ldr r3, [r3, #0]
|
|
80038d8: 2b00 cmp r3, #0
|
|
80038da: f000 80a7 beq.w 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
|
|
80038de: 6879 ldr r1, [r7, #4]
|
|
80038e0: 69ba ldr r2, [r7, #24]
|
|
80038e2: 4613 mov r3, r2
|
|
80038e4: 011b lsls r3, r3, #4
|
|
80038e6: 1a9b subs r3, r3, r2
|
|
80038e8: 009b lsls r3, r3, #2
|
|
80038ea: 440b add r3, r1
|
|
80038ec: 3338 adds r3, #56 @ 0x38
|
|
80038ee: 681a ldr r2, [r3, #0]
|
|
80038f0: 693b ldr r3, [r7, #16]
|
|
80038f2: 18d1 adds r1, r2, r3
|
|
80038f4: 6878 ldr r0, [r7, #4]
|
|
80038f6: 69ba ldr r2, [r7, #24]
|
|
80038f8: 4613 mov r3, r2
|
|
80038fa: 011b lsls r3, r3, #4
|
|
80038fc: 1a9b subs r3, r3, r2
|
|
80038fe: 009b lsls r3, r3, #2
|
|
8003900: 4403 add r3, r0
|
|
8003902: 3334 adds r3, #52 @ 0x34
|
|
8003904: 681b ldr r3, [r3, #0]
|
|
8003906: 4299 cmp r1, r3
|
|
8003908: f200 8083 bhi.w 8003a12 <HCD_RXQLVL_IRQHandler+0x19a>
|
|
(void)USB_ReadPacket(hhcd->Instance,
|
|
800390c: 687b ldr r3, [r7, #4]
|
|
800390e: 6818 ldr r0, [r3, #0]
|
|
8003910: 6879 ldr r1, [r7, #4]
|
|
8003912: 69ba ldr r2, [r7, #24]
|
|
8003914: 4613 mov r3, r2
|
|
8003916: 011b lsls r3, r3, #4
|
|
8003918: 1a9b subs r3, r3, r2
|
|
800391a: 009b lsls r3, r3, #2
|
|
800391c: 440b add r3, r1
|
|
800391e: 332c adds r3, #44 @ 0x2c
|
|
8003920: 681b ldr r3, [r3, #0]
|
|
8003922: 693a ldr r2, [r7, #16]
|
|
8003924: b292 uxth r2, r2
|
|
8003926: 4619 mov r1, r3
|
|
8003928: f002 fd8a bl 8006440 <USB_ReadPacket>
|
|
hhcd->hc[chnum].xfer_buff += pktcnt;
|
|
800392c: 6879 ldr r1, [r7, #4]
|
|
800392e: 69ba ldr r2, [r7, #24]
|
|
8003930: 4613 mov r3, r2
|
|
8003932: 011b lsls r3, r3, #4
|
|
8003934: 1a9b subs r3, r3, r2
|
|
8003936: 009b lsls r3, r3, #2
|
|
8003938: 440b add r3, r1
|
|
800393a: 332c adds r3, #44 @ 0x2c
|
|
800393c: 681a ldr r2, [r3, #0]
|
|
800393e: 693b ldr r3, [r7, #16]
|
|
8003940: 18d1 adds r1, r2, r3
|
|
8003942: 6878 ldr r0, [r7, #4]
|
|
8003944: 69ba ldr r2, [r7, #24]
|
|
8003946: 4613 mov r3, r2
|
|
8003948: 011b lsls r3, r3, #4
|
|
800394a: 1a9b subs r3, r3, r2
|
|
800394c: 009b lsls r3, r3, #2
|
|
800394e: 4403 add r3, r0
|
|
8003950: 332c adds r3, #44 @ 0x2c
|
|
8003952: 6019 str r1, [r3, #0]
|
|
hhcd->hc[chnum].xfer_count += pktcnt;
|
|
8003954: 6879 ldr r1, [r7, #4]
|
|
8003956: 69ba ldr r2, [r7, #24]
|
|
8003958: 4613 mov r3, r2
|
|
800395a: 011b lsls r3, r3, #4
|
|
800395c: 1a9b subs r3, r3, r2
|
|
800395e: 009b lsls r3, r3, #2
|
|
8003960: 440b add r3, r1
|
|
8003962: 3338 adds r3, #56 @ 0x38
|
|
8003964: 681a ldr r2, [r3, #0]
|
|
8003966: 693b ldr r3, [r7, #16]
|
|
8003968: 18d1 adds r1, r2, r3
|
|
800396a: 6878 ldr r0, [r7, #4]
|
|
800396c: 69ba ldr r2, [r7, #24]
|
|
800396e: 4613 mov r3, r2
|
|
8003970: 011b lsls r3, r3, #4
|
|
8003972: 1a9b subs r3, r3, r2
|
|
8003974: 009b lsls r3, r3, #2
|
|
8003976: 4403 add r3, r0
|
|
8003978: 3338 adds r3, #56 @ 0x38
|
|
800397a: 6019 str r1, [r3, #0]
|
|
xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
|
|
800397c: 69bb ldr r3, [r7, #24]
|
|
800397e: 015a lsls r2, r3, #5
|
|
8003980: 6a3b ldr r3, [r7, #32]
|
|
8003982: 4413 add r3, r2
|
|
8003984: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8003988: 691b ldr r3, [r3, #16]
|
|
800398a: 0cdb lsrs r3, r3, #19
|
|
800398c: f3c3 0309 ubfx r3, r3, #0, #10
|
|
8003990: 60fb str r3, [r7, #12]
|
|
if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
|
|
8003992: 6879 ldr r1, [r7, #4]
|
|
8003994: 69ba ldr r2, [r7, #24]
|
|
8003996: 4613 mov r3, r2
|
|
8003998: 011b lsls r3, r3, #4
|
|
800399a: 1a9b subs r3, r3, r2
|
|
800399c: 009b lsls r3, r3, #2
|
|
800399e: 440b add r3, r1
|
|
80039a0: 3328 adds r3, #40 @ 0x28
|
|
80039a2: 881b ldrh r3, [r3, #0]
|
|
80039a4: 461a mov r2, r3
|
|
80039a6: 693b ldr r3, [r7, #16]
|
|
80039a8: 4293 cmp r3, r2
|
|
80039aa: d13f bne.n 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
80039ac: 68fb ldr r3, [r7, #12]
|
|
80039ae: 2b00 cmp r3, #0
|
|
80039b0: d03c beq.n 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
tmpreg = USBx_HC(chnum)->HCCHAR;
|
|
80039b2: 69bb ldr r3, [r7, #24]
|
|
80039b4: 015a lsls r2, r3, #5
|
|
80039b6: 6a3b ldr r3, [r7, #32]
|
|
80039b8: 4413 add r3, r2
|
|
80039ba: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80039be: 681b ldr r3, [r3, #0]
|
|
80039c0: 60bb str r3, [r7, #8]
|
|
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
|
|
80039c2: 68bb ldr r3, [r7, #8]
|
|
80039c4: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
|
|
80039c8: 60bb str r3, [r7, #8]
|
|
tmpreg |= USB_OTG_HCCHAR_CHENA;
|
|
80039ca: 68bb ldr r3, [r7, #8]
|
|
80039cc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80039d0: 60bb str r3, [r7, #8]
|
|
USBx_HC(chnum)->HCCHAR = tmpreg;
|
|
80039d2: 69bb ldr r3, [r7, #24]
|
|
80039d4: 015a lsls r2, r3, #5
|
|
80039d6: 6a3b ldr r3, [r7, #32]
|
|
80039d8: 4413 add r3, r2
|
|
80039da: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80039de: 461a mov r2, r3
|
|
80039e0: 68bb ldr r3, [r7, #8]
|
|
80039e2: 6013 str r3, [r2, #0]
|
|
hhcd->hc[chnum].toggle_in ^= 1U;
|
|
80039e4: 6879 ldr r1, [r7, #4]
|
|
80039e6: 69ba ldr r2, [r7, #24]
|
|
80039e8: 4613 mov r3, r2
|
|
80039ea: 011b lsls r3, r3, #4
|
|
80039ec: 1a9b subs r3, r3, r2
|
|
80039ee: 009b lsls r3, r3, #2
|
|
80039f0: 440b add r3, r1
|
|
80039f2: 333c adds r3, #60 @ 0x3c
|
|
80039f4: 781b ldrb r3, [r3, #0]
|
|
80039f6: f083 0301 eor.w r3, r3, #1
|
|
80039fa: b2d8 uxtb r0, r3
|
|
80039fc: 6879 ldr r1, [r7, #4]
|
|
80039fe: 69ba ldr r2, [r7, #24]
|
|
8003a00: 4613 mov r3, r2
|
|
8003a02: 011b lsls r3, r3, #4
|
|
8003a04: 1a9b subs r3, r3, r2
|
|
8003a06: 009b lsls r3, r3, #2
|
|
8003a08: 440b add r3, r1
|
|
8003a0a: 333c adds r3, #60 @ 0x3c
|
|
8003a0c: 4602 mov r2, r0
|
|
8003a0e: 701a strb r2, [r3, #0]
|
|
break;
|
|
8003a10: e00c b.n 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
hhcd->hc[chnum].urb_state = URB_ERROR;
|
|
8003a12: 6879 ldr r1, [r7, #4]
|
|
8003a14: 69ba ldr r2, [r7, #24]
|
|
8003a16: 4613 mov r3, r2
|
|
8003a18: 011b lsls r3, r3, #4
|
|
8003a1a: 1a9b subs r3, r3, r2
|
|
8003a1c: 009b lsls r3, r3, #2
|
|
8003a1e: 440b add r3, r1
|
|
8003a20: 334c adds r3, #76 @ 0x4c
|
|
8003a22: 2204 movs r2, #4
|
|
8003a24: 701a strb r2, [r3, #0]
|
|
break;
|
|
8003a26: e001 b.n 8003a2c <HCD_RXQLVL_IRQHandler+0x1b4>
|
|
break;
|
|
8003a28: bf00 nop
|
|
8003a2a: e000 b.n 8003a2e <HCD_RXQLVL_IRQHandler+0x1b6>
|
|
break;
|
|
8003a2c: bf00 nop
|
|
}
|
|
}
|
|
8003a2e: bf00 nop
|
|
8003a30: 3728 adds r7, #40 @ 0x28
|
|
8003a32: 46bd mov sp, r7
|
|
8003a34: bd80 pop {r7, pc}
|
|
|
|
08003a36 <HCD_Port_IRQHandler>:
|
|
* @brief Handle Host Port interrupt requests.
|
|
* @param hhcd HCD handle
|
|
* @retval None
|
|
*/
|
|
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8003a36: b580 push {r7, lr}
|
|
8003a38: b086 sub sp, #24
|
|
8003a3a: af00 add r7, sp, #0
|
|
8003a3c: 6078 str r0, [r7, #4]
|
|
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
|
|
8003a3e: 687b ldr r3, [r7, #4]
|
|
8003a40: 681b ldr r3, [r3, #0]
|
|
8003a42: 617b str r3, [r7, #20]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8003a44: 697b ldr r3, [r7, #20]
|
|
8003a46: 613b str r3, [r7, #16]
|
|
__IO uint32_t hprt0;
|
|
__IO uint32_t hprt0_dup;
|
|
|
|
/* Handle Host Port Interrupts */
|
|
hprt0 = USBx_HPRT0;
|
|
8003a48: 693b ldr r3, [r7, #16]
|
|
8003a4a: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8003a4e: 681b ldr r3, [r3, #0]
|
|
8003a50: 60fb str r3, [r7, #12]
|
|
hprt0_dup = USBx_HPRT0;
|
|
8003a52: 693b ldr r3, [r7, #16]
|
|
8003a54: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8003a58: 681b ldr r3, [r3, #0]
|
|
8003a5a: 60bb str r3, [r7, #8]
|
|
|
|
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
|
|
8003a5c: 68bb ldr r3, [r7, #8]
|
|
8003a5e: f023 032e bic.w r3, r3, #46 @ 0x2e
|
|
8003a62: 60bb str r3, [r7, #8]
|
|
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
|
|
|
|
/* Check whether Port Connect detected */
|
|
if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
|
|
8003a64: 68fb ldr r3, [r7, #12]
|
|
8003a66: f003 0302 and.w r3, r3, #2
|
|
8003a6a: 2b02 cmp r3, #2
|
|
8003a6c: d10b bne.n 8003a86 <HCD_Port_IRQHandler+0x50>
|
|
{
|
|
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
|
|
8003a6e: 68fb ldr r3, [r7, #12]
|
|
8003a70: f003 0301 and.w r3, r3, #1
|
|
8003a74: 2b01 cmp r3, #1
|
|
8003a76: d102 bne.n 8003a7e <HCD_Port_IRQHandler+0x48>
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->ConnectCallback(hhcd);
|
|
#else
|
|
HAL_HCD_Connect_Callback(hhcd);
|
|
8003a78: 6878 ldr r0, [r7, #4]
|
|
8003a7a: f004 f93f bl 8007cfc <HAL_HCD_Connect_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
hprt0_dup |= USB_OTG_HPRT_PCDET;
|
|
8003a7e: 68bb ldr r3, [r7, #8]
|
|
8003a80: f043 0302 orr.w r3, r3, #2
|
|
8003a84: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
/* Check whether Port Enable Changed */
|
|
if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
|
|
8003a86: 68fb ldr r3, [r7, #12]
|
|
8003a88: f003 0308 and.w r3, r3, #8
|
|
8003a8c: 2b08 cmp r3, #8
|
|
8003a8e: d132 bne.n 8003af6 <HCD_Port_IRQHandler+0xc0>
|
|
{
|
|
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
|
|
8003a90: 68bb ldr r3, [r7, #8]
|
|
8003a92: f043 0308 orr.w r3, r3, #8
|
|
8003a96: 60bb str r3, [r7, #8]
|
|
|
|
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
|
|
8003a98: 68fb ldr r3, [r7, #12]
|
|
8003a9a: f003 0304 and.w r3, r3, #4
|
|
8003a9e: 2b04 cmp r3, #4
|
|
8003aa0: d126 bne.n 8003af0 <HCD_Port_IRQHandler+0xba>
|
|
{
|
|
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
|
|
8003aa2: 687b ldr r3, [r7, #4]
|
|
8003aa4: 7a5b ldrb r3, [r3, #9]
|
|
8003aa6: 2b02 cmp r3, #2
|
|
8003aa8: d113 bne.n 8003ad2 <HCD_Port_IRQHandler+0x9c>
|
|
{
|
|
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
|
|
8003aaa: 68fb ldr r3, [r7, #12]
|
|
8003aac: f403 23c0 and.w r3, r3, #393216 @ 0x60000
|
|
8003ab0: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
|
|
8003ab4: d106 bne.n 8003ac4 <HCD_Port_IRQHandler+0x8e>
|
|
{
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
|
|
8003ab6: 687b ldr r3, [r7, #4]
|
|
8003ab8: 681b ldr r3, [r3, #0]
|
|
8003aba: 2102 movs r1, #2
|
|
8003abc: 4618 mov r0, r3
|
|
8003abe: f002 fd59 bl 8006574 <USB_InitFSLSPClkSel>
|
|
8003ac2: e011 b.n 8003ae8 <HCD_Port_IRQHandler+0xb2>
|
|
}
|
|
else
|
|
{
|
|
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
|
|
8003ac4: 687b ldr r3, [r7, #4]
|
|
8003ac6: 681b ldr r3, [r3, #0]
|
|
8003ac8: 2101 movs r1, #1
|
|
8003aca: 4618 mov r0, r3
|
|
8003acc: f002 fd52 bl 8006574 <USB_InitFSLSPClkSel>
|
|
8003ad0: e00a b.n 8003ae8 <HCD_Port_IRQHandler+0xb2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (hhcd->Init.speed == HCD_SPEED_FULL)
|
|
8003ad2: 687b ldr r3, [r7, #4]
|
|
8003ad4: 79db ldrb r3, [r3, #7]
|
|
8003ad6: 2b01 cmp r3, #1
|
|
8003ad8: d106 bne.n 8003ae8 <HCD_Port_IRQHandler+0xb2>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_60_MHZ;
|
|
8003ada: 693b ldr r3, [r7, #16]
|
|
8003adc: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8003ae0: 461a mov r2, r3
|
|
8003ae2: f64e 2360 movw r3, #60000 @ 0xea60
|
|
8003ae6: 6053 str r3, [r2, #4]
|
|
}
|
|
}
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->PortEnabledCallback(hhcd);
|
|
#else
|
|
HAL_HCD_PortEnabled_Callback(hhcd);
|
|
8003ae8: 6878 ldr r0, [r7, #4]
|
|
8003aea: f004 f935 bl 8007d58 <HAL_HCD_PortEnabled_Callback>
|
|
8003aee: e002 b.n 8003af6 <HCD_Port_IRQHandler+0xc0>
|
|
else
|
|
{
|
|
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
|
|
hhcd->PortDisabledCallback(hhcd);
|
|
#else
|
|
HAL_HCD_PortDisabled_Callback(hhcd);
|
|
8003af0: 6878 ldr r0, [r7, #4]
|
|
8003af2: f004 f93f bl 8007d74 <HAL_HCD_PortDisabled_Callback>
|
|
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
|
|
/* Check for an overcurrent */
|
|
if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
|
|
8003af6: 68fb ldr r3, [r7, #12]
|
|
8003af8: f003 0320 and.w r3, r3, #32
|
|
8003afc: 2b20 cmp r3, #32
|
|
8003afe: d103 bne.n 8003b08 <HCD_Port_IRQHandler+0xd2>
|
|
{
|
|
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
|
|
8003b00: 68bb ldr r3, [r7, #8]
|
|
8003b02: f043 0320 orr.w r3, r3, #32
|
|
8003b06: 60bb str r3, [r7, #8]
|
|
}
|
|
|
|
/* Clear Port Interrupts */
|
|
USBx_HPRT0 = hprt0_dup;
|
|
8003b08: 693b ldr r3, [r7, #16]
|
|
8003b0a: f503 6388 add.w r3, r3, #1088 @ 0x440
|
|
8003b0e: 461a mov r2, r3
|
|
8003b10: 68bb ldr r3, [r7, #8]
|
|
8003b12: 6013 str r3, [r2, #0]
|
|
}
|
|
8003b14: bf00 nop
|
|
8003b16: 3718 adds r7, #24
|
|
8003b18: 46bd mov sp, r7
|
|
8003b1a: bd80 pop {r7, pc}
|
|
|
|
08003b1c <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8003b1c: b580 push {r7, lr}
|
|
8003b1e: b084 sub sp, #16
|
|
8003b20: af00 add r7, sp, #0
|
|
8003b22: 6078 str r0, [r7, #4]
|
|
uint32_t freqrange;
|
|
uint32_t pclk1;
|
|
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8003b24: 687b ldr r3, [r7, #4]
|
|
8003b26: 2b00 cmp r3, #0
|
|
8003b28: d101 bne.n 8003b2e <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003b2a: 2301 movs r3, #1
|
|
8003b2c: e12b b.n 8003d86 <HAL_I2C_Init+0x26a>
|
|
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8003b2e: 687b ldr r3, [r7, #4]
|
|
8003b30: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8003b34: b2db uxtb r3, r3
|
|
8003b36: 2b00 cmp r3, #0
|
|
8003b38: d106 bne.n 8003b48 <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8003b3a: 687b ldr r3, [r7, #4]
|
|
8003b3c: 2200 movs r2, #0
|
|
8003b3e: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8003b42: 6878 ldr r0, [r7, #4]
|
|
8003b44: f7fd f930 bl 8000da8 <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8003b48: 687b ldr r3, [r7, #4]
|
|
8003b4a: 2224 movs r2, #36 @ 0x24
|
|
8003b4c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003b50: 687b ldr r3, [r7, #4]
|
|
8003b52: 681b ldr r3, [r3, #0]
|
|
8003b54: 681a ldr r2, [r3, #0]
|
|
8003b56: 687b ldr r3, [r7, #4]
|
|
8003b58: 681b ldr r3, [r3, #0]
|
|
8003b5a: f022 0201 bic.w r2, r2, #1
|
|
8003b5e: 601a str r2, [r3, #0]
|
|
|
|
/*Reset I2C*/
|
|
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
|
|
8003b60: 687b ldr r3, [r7, #4]
|
|
8003b62: 681b ldr r3, [r3, #0]
|
|
8003b64: 681a ldr r2, [r3, #0]
|
|
8003b66: 687b ldr r3, [r7, #4]
|
|
8003b68: 681b ldr r3, [r3, #0]
|
|
8003b6a: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8003b6e: 601a str r2, [r3, #0]
|
|
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
|
|
8003b70: 687b ldr r3, [r7, #4]
|
|
8003b72: 681b ldr r3, [r3, #0]
|
|
8003b74: 681a ldr r2, [r3, #0]
|
|
8003b76: 687b ldr r3, [r7, #4]
|
|
8003b78: 681b ldr r3, [r3, #0]
|
|
8003b7a: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8003b7e: 601a str r2, [r3, #0]
|
|
|
|
/* Get PCLK1 frequency */
|
|
pclk1 = HAL_RCC_GetPCLK1Freq();
|
|
8003b80: f001 f90c bl 8004d9c <HAL_RCC_GetPCLK1Freq>
|
|
8003b84: 60f8 str r0, [r7, #12]
|
|
|
|
/* Check the minimum allowed PCLK1 frequency */
|
|
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
|
|
8003b86: 687b ldr r3, [r7, #4]
|
|
8003b88: 685b ldr r3, [r3, #4]
|
|
8003b8a: 4a81 ldr r2, [pc, #516] @ (8003d90 <HAL_I2C_Init+0x274>)
|
|
8003b8c: 4293 cmp r3, r2
|
|
8003b8e: d807 bhi.n 8003ba0 <HAL_I2C_Init+0x84>
|
|
8003b90: 68fb ldr r3, [r7, #12]
|
|
8003b92: 4a80 ldr r2, [pc, #512] @ (8003d94 <HAL_I2C_Init+0x278>)
|
|
8003b94: 4293 cmp r3, r2
|
|
8003b96: bf94 ite ls
|
|
8003b98: 2301 movls r3, #1
|
|
8003b9a: 2300 movhi r3, #0
|
|
8003b9c: b2db uxtb r3, r3
|
|
8003b9e: e006 b.n 8003bae <HAL_I2C_Init+0x92>
|
|
8003ba0: 68fb ldr r3, [r7, #12]
|
|
8003ba2: 4a7d ldr r2, [pc, #500] @ (8003d98 <HAL_I2C_Init+0x27c>)
|
|
8003ba4: 4293 cmp r3, r2
|
|
8003ba6: bf94 ite ls
|
|
8003ba8: 2301 movls r3, #1
|
|
8003baa: 2300 movhi r3, #0
|
|
8003bac: b2db uxtb r3, r3
|
|
8003bae: 2b00 cmp r3, #0
|
|
8003bb0: d001 beq.n 8003bb6 <HAL_I2C_Init+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
8003bb2: 2301 movs r3, #1
|
|
8003bb4: e0e7 b.n 8003d86 <HAL_I2C_Init+0x26a>
|
|
}
|
|
|
|
/* Calculate frequency range */
|
|
freqrange = I2C_FREQRANGE(pclk1);
|
|
8003bb6: 68fb ldr r3, [r7, #12]
|
|
8003bb8: 4a78 ldr r2, [pc, #480] @ (8003d9c <HAL_I2C_Init+0x280>)
|
|
8003bba: fba2 2303 umull r2, r3, r2, r3
|
|
8003bbe: 0c9b lsrs r3, r3, #18
|
|
8003bc0: 60bb str r3, [r7, #8]
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
|
|
8003bc2: 687b ldr r3, [r7, #4]
|
|
8003bc4: 681b ldr r3, [r3, #0]
|
|
8003bc6: 685b ldr r3, [r3, #4]
|
|
8003bc8: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8003bcc: 687b ldr r3, [r7, #4]
|
|
8003bce: 681b ldr r3, [r3, #0]
|
|
8003bd0: 68ba ldr r2, [r7, #8]
|
|
8003bd2: 430a orrs r2, r1
|
|
8003bd4: 605a str r2, [r3, #4]
|
|
|
|
/*---------------------------- I2Cx TRISE Configuration --------------------*/
|
|
/* Configure I2Cx: Rise Time */
|
|
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
|
|
8003bd6: 687b ldr r3, [r7, #4]
|
|
8003bd8: 681b ldr r3, [r3, #0]
|
|
8003bda: 6a1b ldr r3, [r3, #32]
|
|
8003bdc: f023 013f bic.w r1, r3, #63 @ 0x3f
|
|
8003be0: 687b ldr r3, [r7, #4]
|
|
8003be2: 685b ldr r3, [r3, #4]
|
|
8003be4: 4a6a ldr r2, [pc, #424] @ (8003d90 <HAL_I2C_Init+0x274>)
|
|
8003be6: 4293 cmp r3, r2
|
|
8003be8: d802 bhi.n 8003bf0 <HAL_I2C_Init+0xd4>
|
|
8003bea: 68bb ldr r3, [r7, #8]
|
|
8003bec: 3301 adds r3, #1
|
|
8003bee: e009 b.n 8003c04 <HAL_I2C_Init+0xe8>
|
|
8003bf0: 68bb ldr r3, [r7, #8]
|
|
8003bf2: f44f 7296 mov.w r2, #300 @ 0x12c
|
|
8003bf6: fb02 f303 mul.w r3, r2, r3
|
|
8003bfa: 4a69 ldr r2, [pc, #420] @ (8003da0 <HAL_I2C_Init+0x284>)
|
|
8003bfc: fba2 2303 umull r2, r3, r2, r3
|
|
8003c00: 099b lsrs r3, r3, #6
|
|
8003c02: 3301 adds r3, #1
|
|
8003c04: 687a ldr r2, [r7, #4]
|
|
8003c06: 6812 ldr r2, [r2, #0]
|
|
8003c08: 430b orrs r3, r1
|
|
8003c0a: 6213 str r3, [r2, #32]
|
|
|
|
/*---------------------------- I2Cx CCR Configuration ----------------------*/
|
|
/* Configure I2Cx: Speed */
|
|
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
|
|
8003c0c: 687b ldr r3, [r7, #4]
|
|
8003c0e: 681b ldr r3, [r3, #0]
|
|
8003c10: 69db ldr r3, [r3, #28]
|
|
8003c12: f423 424f bic.w r2, r3, #52992 @ 0xcf00
|
|
8003c16: f022 02ff bic.w r2, r2, #255 @ 0xff
|
|
8003c1a: 687b ldr r3, [r7, #4]
|
|
8003c1c: 685b ldr r3, [r3, #4]
|
|
8003c1e: 495c ldr r1, [pc, #368] @ (8003d90 <HAL_I2C_Init+0x274>)
|
|
8003c20: 428b cmp r3, r1
|
|
8003c22: d819 bhi.n 8003c58 <HAL_I2C_Init+0x13c>
|
|
8003c24: 68fb ldr r3, [r7, #12]
|
|
8003c26: 1e59 subs r1, r3, #1
|
|
8003c28: 687b ldr r3, [r7, #4]
|
|
8003c2a: 685b ldr r3, [r3, #4]
|
|
8003c2c: 005b lsls r3, r3, #1
|
|
8003c2e: fbb1 f3f3 udiv r3, r1, r3
|
|
8003c32: 1c59 adds r1, r3, #1
|
|
8003c34: f640 73fc movw r3, #4092 @ 0xffc
|
|
8003c38: 400b ands r3, r1
|
|
8003c3a: 2b00 cmp r3, #0
|
|
8003c3c: d00a beq.n 8003c54 <HAL_I2C_Init+0x138>
|
|
8003c3e: 68fb ldr r3, [r7, #12]
|
|
8003c40: 1e59 subs r1, r3, #1
|
|
8003c42: 687b ldr r3, [r7, #4]
|
|
8003c44: 685b ldr r3, [r3, #4]
|
|
8003c46: 005b lsls r3, r3, #1
|
|
8003c48: fbb1 f3f3 udiv r3, r1, r3
|
|
8003c4c: 3301 adds r3, #1
|
|
8003c4e: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003c52: e051 b.n 8003cf8 <HAL_I2C_Init+0x1dc>
|
|
8003c54: 2304 movs r3, #4
|
|
8003c56: e04f b.n 8003cf8 <HAL_I2C_Init+0x1dc>
|
|
8003c58: 687b ldr r3, [r7, #4]
|
|
8003c5a: 689b ldr r3, [r3, #8]
|
|
8003c5c: 2b00 cmp r3, #0
|
|
8003c5e: d111 bne.n 8003c84 <HAL_I2C_Init+0x168>
|
|
8003c60: 68fb ldr r3, [r7, #12]
|
|
8003c62: 1e58 subs r0, r3, #1
|
|
8003c64: 687b ldr r3, [r7, #4]
|
|
8003c66: 6859 ldr r1, [r3, #4]
|
|
8003c68: 460b mov r3, r1
|
|
8003c6a: 005b lsls r3, r3, #1
|
|
8003c6c: 440b add r3, r1
|
|
8003c6e: fbb0 f3f3 udiv r3, r0, r3
|
|
8003c72: 3301 adds r3, #1
|
|
8003c74: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003c78: 2b00 cmp r3, #0
|
|
8003c7a: bf0c ite eq
|
|
8003c7c: 2301 moveq r3, #1
|
|
8003c7e: 2300 movne r3, #0
|
|
8003c80: b2db uxtb r3, r3
|
|
8003c82: e012 b.n 8003caa <HAL_I2C_Init+0x18e>
|
|
8003c84: 68fb ldr r3, [r7, #12]
|
|
8003c86: 1e58 subs r0, r3, #1
|
|
8003c88: 687b ldr r3, [r7, #4]
|
|
8003c8a: 6859 ldr r1, [r3, #4]
|
|
8003c8c: 460b mov r3, r1
|
|
8003c8e: 009b lsls r3, r3, #2
|
|
8003c90: 440b add r3, r1
|
|
8003c92: 0099 lsls r1, r3, #2
|
|
8003c94: 440b add r3, r1
|
|
8003c96: fbb0 f3f3 udiv r3, r0, r3
|
|
8003c9a: 3301 adds r3, #1
|
|
8003c9c: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003ca0: 2b00 cmp r3, #0
|
|
8003ca2: bf0c ite eq
|
|
8003ca4: 2301 moveq r3, #1
|
|
8003ca6: 2300 movne r3, #0
|
|
8003ca8: b2db uxtb r3, r3
|
|
8003caa: 2b00 cmp r3, #0
|
|
8003cac: d001 beq.n 8003cb2 <HAL_I2C_Init+0x196>
|
|
8003cae: 2301 movs r3, #1
|
|
8003cb0: e022 b.n 8003cf8 <HAL_I2C_Init+0x1dc>
|
|
8003cb2: 687b ldr r3, [r7, #4]
|
|
8003cb4: 689b ldr r3, [r3, #8]
|
|
8003cb6: 2b00 cmp r3, #0
|
|
8003cb8: d10e bne.n 8003cd8 <HAL_I2C_Init+0x1bc>
|
|
8003cba: 68fb ldr r3, [r7, #12]
|
|
8003cbc: 1e58 subs r0, r3, #1
|
|
8003cbe: 687b ldr r3, [r7, #4]
|
|
8003cc0: 6859 ldr r1, [r3, #4]
|
|
8003cc2: 460b mov r3, r1
|
|
8003cc4: 005b lsls r3, r3, #1
|
|
8003cc6: 440b add r3, r1
|
|
8003cc8: fbb0 f3f3 udiv r3, r0, r3
|
|
8003ccc: 3301 adds r3, #1
|
|
8003cce: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003cd2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8003cd6: e00f b.n 8003cf8 <HAL_I2C_Init+0x1dc>
|
|
8003cd8: 68fb ldr r3, [r7, #12]
|
|
8003cda: 1e58 subs r0, r3, #1
|
|
8003cdc: 687b ldr r3, [r7, #4]
|
|
8003cde: 6859 ldr r1, [r3, #4]
|
|
8003ce0: 460b mov r3, r1
|
|
8003ce2: 009b lsls r3, r3, #2
|
|
8003ce4: 440b add r3, r1
|
|
8003ce6: 0099 lsls r1, r3, #2
|
|
8003ce8: 440b add r3, r1
|
|
8003cea: fbb0 f3f3 udiv r3, r0, r3
|
|
8003cee: 3301 adds r3, #1
|
|
8003cf0: f3c3 030b ubfx r3, r3, #0, #12
|
|
8003cf4: f443 4340 orr.w r3, r3, #49152 @ 0xc000
|
|
8003cf8: 6879 ldr r1, [r7, #4]
|
|
8003cfa: 6809 ldr r1, [r1, #0]
|
|
8003cfc: 4313 orrs r3, r2
|
|
8003cfe: 61cb str r3, [r1, #28]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
|
|
8003d00: 687b ldr r3, [r7, #4]
|
|
8003d02: 681b ldr r3, [r3, #0]
|
|
8003d04: 681b ldr r3, [r3, #0]
|
|
8003d06: f023 01c0 bic.w r1, r3, #192 @ 0xc0
|
|
8003d0a: 687b ldr r3, [r7, #4]
|
|
8003d0c: 69da ldr r2, [r3, #28]
|
|
8003d0e: 687b ldr r3, [r7, #4]
|
|
8003d10: 6a1b ldr r3, [r3, #32]
|
|
8003d12: 431a orrs r2, r3
|
|
8003d14: 687b ldr r3, [r7, #4]
|
|
8003d16: 681b ldr r3, [r3, #0]
|
|
8003d18: 430a orrs r2, r1
|
|
8003d1a: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Configure I2Cx: Own Address1 and addressing mode */
|
|
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
|
|
8003d1c: 687b ldr r3, [r7, #4]
|
|
8003d1e: 681b ldr r3, [r3, #0]
|
|
8003d20: 689b ldr r3, [r3, #8]
|
|
8003d22: f423 4303 bic.w r3, r3, #33536 @ 0x8300
|
|
8003d26: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8003d2a: 687a ldr r2, [r7, #4]
|
|
8003d2c: 6911 ldr r1, [r2, #16]
|
|
8003d2e: 687a ldr r2, [r7, #4]
|
|
8003d30: 68d2 ldr r2, [r2, #12]
|
|
8003d32: 4311 orrs r1, r2
|
|
8003d34: 687a ldr r2, [r7, #4]
|
|
8003d36: 6812 ldr r2, [r2, #0]
|
|
8003d38: 430b orrs r3, r1
|
|
8003d3a: 6093 str r3, [r2, #8]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
|
|
8003d3c: 687b ldr r3, [r7, #4]
|
|
8003d3e: 681b ldr r3, [r3, #0]
|
|
8003d40: 68db ldr r3, [r3, #12]
|
|
8003d42: f023 01ff bic.w r1, r3, #255 @ 0xff
|
|
8003d46: 687b ldr r3, [r7, #4]
|
|
8003d48: 695a ldr r2, [r3, #20]
|
|
8003d4a: 687b ldr r3, [r7, #4]
|
|
8003d4c: 699b ldr r3, [r3, #24]
|
|
8003d4e: 431a orrs r2, r3
|
|
8003d50: 687b ldr r3, [r7, #4]
|
|
8003d52: 681b ldr r3, [r3, #0]
|
|
8003d54: 430a orrs r2, r1
|
|
8003d56: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003d58: 687b ldr r3, [r7, #4]
|
|
8003d5a: 681b ldr r3, [r3, #0]
|
|
8003d5c: 681a ldr r2, [r3, #0]
|
|
8003d5e: 687b ldr r3, [r7, #4]
|
|
8003d60: 681b ldr r3, [r3, #0]
|
|
8003d62: f042 0201 orr.w r2, r2, #1
|
|
8003d66: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8003d68: 687b ldr r3, [r7, #4]
|
|
8003d6a: 2200 movs r2, #0
|
|
8003d6c: 641a str r2, [r3, #64] @ 0x40
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003d6e: 687b ldr r3, [r7, #4]
|
|
8003d70: 2220 movs r2, #32
|
|
8003d72: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8003d76: 687b ldr r3, [r7, #4]
|
|
8003d78: 2200 movs r2, #0
|
|
8003d7a: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003d7c: 687b ldr r3, [r7, #4]
|
|
8003d7e: 2200 movs r2, #0
|
|
8003d80: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
|
|
return HAL_OK;
|
|
8003d84: 2300 movs r3, #0
|
|
}
|
|
8003d86: 4618 mov r0, r3
|
|
8003d88: 3710 adds r7, #16
|
|
8003d8a: 46bd mov sp, r7
|
|
8003d8c: bd80 pop {r7, pc}
|
|
8003d8e: bf00 nop
|
|
8003d90: 000186a0 .word 0x000186a0
|
|
8003d94: 001e847f .word 0x001e847f
|
|
8003d98: 003d08ff .word 0x003d08ff
|
|
8003d9c: 431bde83 .word 0x431bde83
|
|
8003da0: 10624dd3 .word 0x10624dd3
|
|
|
|
08003da4 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter new state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8003da4: b480 push {r7}
|
|
8003da6: b083 sub sp, #12
|
|
8003da8: af00 add r7, sp, #0
|
|
8003daa: 6078 str r0, [r7, #4]
|
|
8003dac: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003dae: 687b ldr r3, [r7, #4]
|
|
8003db0: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8003db4: b2db uxtb r3, r3
|
|
8003db6: 2b20 cmp r3, #32
|
|
8003db8: d129 bne.n 8003e0e <HAL_I2CEx_ConfigAnalogFilter+0x6a>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8003dba: 687b ldr r3, [r7, #4]
|
|
8003dbc: 2224 movs r2, #36 @ 0x24
|
|
8003dbe: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003dc2: 687b ldr r3, [r7, #4]
|
|
8003dc4: 681b ldr r3, [r3, #0]
|
|
8003dc6: 681a ldr r2, [r3, #0]
|
|
8003dc8: 687b ldr r3, [r7, #4]
|
|
8003dca: 681b ldr r3, [r3, #0]
|
|
8003dcc: f022 0201 bic.w r2, r2, #1
|
|
8003dd0: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
|
|
8003dd2: 687b ldr r3, [r7, #4]
|
|
8003dd4: 681b ldr r3, [r3, #0]
|
|
8003dd6: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8003dd8: 687b ldr r3, [r7, #4]
|
|
8003dda: 681b ldr r3, [r3, #0]
|
|
8003ddc: f022 0210 bic.w r2, r2, #16
|
|
8003de0: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Disable the analog filter */
|
|
hi2c->Instance->FLTR |= AnalogFilter;
|
|
8003de2: 687b ldr r3, [r7, #4]
|
|
8003de4: 681b ldr r3, [r3, #0]
|
|
8003de6: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
8003de8: 687b ldr r3, [r7, #4]
|
|
8003dea: 681b ldr r3, [r3, #0]
|
|
8003dec: 683a ldr r2, [r7, #0]
|
|
8003dee: 430a orrs r2, r1
|
|
8003df0: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003df2: 687b ldr r3, [r7, #4]
|
|
8003df4: 681b ldr r3, [r3, #0]
|
|
8003df6: 681a ldr r2, [r3, #0]
|
|
8003df8: 687b ldr r3, [r7, #4]
|
|
8003dfa: 681b ldr r3, [r3, #0]
|
|
8003dfc: f042 0201 orr.w r2, r2, #1
|
|
8003e00: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003e02: 687b ldr r3, [r7, #4]
|
|
8003e04: 2220 movs r2, #32
|
|
8003e06: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8003e0a: 2300 movs r3, #0
|
|
8003e0c: e000 b.n 8003e10 <HAL_I2CEx_ConfigAnalogFilter+0x6c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003e0e: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8003e10: 4618 mov r0, r3
|
|
8003e12: 370c adds r7, #12
|
|
8003e14: 46bd mov sp, r7
|
|
8003e16: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e1a: 4770 bx lr
|
|
|
|
08003e1c <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
8003e1c: b480 push {r7}
|
|
8003e1e: b085 sub sp, #20
|
|
8003e20: af00 add r7, sp, #0
|
|
8003e22: 6078 str r0, [r7, #4]
|
|
8003e24: 6039 str r1, [r7, #0]
|
|
uint16_t tmpreg = 0;
|
|
8003e26: 2300 movs r3, #0
|
|
8003e28: 81fb strh r3, [r7, #14]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003e2a: 687b ldr r3, [r7, #4]
|
|
8003e2c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8003e30: b2db uxtb r3, r3
|
|
8003e32: 2b20 cmp r3, #32
|
|
8003e34: d12a bne.n 8003e8c <HAL_I2CEx_ConfigDigitalFilter+0x70>
|
|
{
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8003e36: 687b ldr r3, [r7, #4]
|
|
8003e38: 2224 movs r2, #36 @ 0x24
|
|
8003e3a: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003e3e: 687b ldr r3, [r7, #4]
|
|
8003e40: 681b ldr r3, [r3, #0]
|
|
8003e42: 681a ldr r2, [r3, #0]
|
|
8003e44: 687b ldr r3, [r7, #4]
|
|
8003e46: 681b ldr r3, [r3, #0]
|
|
8003e48: f022 0201 bic.w r2, r2, #1
|
|
8003e4c: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->FLTR;
|
|
8003e4e: 687b ldr r3, [r7, #4]
|
|
8003e50: 681b ldr r3, [r3, #0]
|
|
8003e52: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003e54: 81fb strh r3, [r7, #14]
|
|
|
|
/* Reset I2Cx DNF bit [3:0] */
|
|
tmpreg &= ~(I2C_FLTR_DNF);
|
|
8003e56: 89fb ldrh r3, [r7, #14]
|
|
8003e58: f023 030f bic.w r3, r3, #15
|
|
8003e5c: 81fb strh r3, [r7, #14]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter;
|
|
8003e5e: 683b ldr r3, [r7, #0]
|
|
8003e60: b29a uxth r2, r3
|
|
8003e62: 89fb ldrh r3, [r7, #14]
|
|
8003e64: 4313 orrs r3, r2
|
|
8003e66: 81fb strh r3, [r7, #14]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->FLTR = tmpreg;
|
|
8003e68: 687b ldr r3, [r7, #4]
|
|
8003e6a: 681b ldr r3, [r3, #0]
|
|
8003e6c: 89fa ldrh r2, [r7, #14]
|
|
8003e6e: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003e70: 687b ldr r3, [r7, #4]
|
|
8003e72: 681b ldr r3, [r3, #0]
|
|
8003e74: 681a ldr r2, [r3, #0]
|
|
8003e76: 687b ldr r3, [r7, #4]
|
|
8003e78: 681b ldr r3, [r3, #0]
|
|
8003e7a: f042 0201 orr.w r2, r2, #1
|
|
8003e7e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003e80: 687b ldr r3, [r7, #4]
|
|
8003e82: 2220 movs r2, #32
|
|
8003e84: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
8003e88: 2300 movs r3, #0
|
|
8003e8a: e000 b.n 8003e8e <HAL_I2CEx_ConfigDigitalFilter+0x72>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003e8c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8003e8e: 4618 mov r0, r3
|
|
8003e90: 3714 adds r7, #20
|
|
8003e92: 46bd mov sp, r7
|
|
8003e94: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003e98: 4770 bx lr
|
|
|
|
08003e9a <HAL_LTDC_Init>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8003e9a: b580 push {r7, lr}
|
|
8003e9c: b084 sub sp, #16
|
|
8003e9e: af00 add r7, sp, #0
|
|
8003ea0: 6078 str r0, [r7, #4]
|
|
uint32_t tmp;
|
|
uint32_t tmp1;
|
|
|
|
/* Check the LTDC peripheral state */
|
|
if (hltdc == NULL)
|
|
8003ea2: 687b ldr r3, [r7, #4]
|
|
8003ea4: 2b00 cmp r3, #0
|
|
8003ea6: d101 bne.n 8003eac <HAL_LTDC_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8003ea8: 2301 movs r3, #1
|
|
8003eaa: e08f b.n 8003fcc <HAL_LTDC_Init+0x132>
|
|
}
|
|
/* Init the low level hardware */
|
|
hltdc->MspInitCallback(hltdc);
|
|
}
|
|
#else
|
|
if (hltdc->State == HAL_LTDC_STATE_RESET)
|
|
8003eac: 687b ldr r3, [r7, #4]
|
|
8003eae: f893 30a1 ldrb.w r3, [r3, #161] @ 0xa1
|
|
8003eb2: b2db uxtb r3, r3
|
|
8003eb4: 2b00 cmp r3, #0
|
|
8003eb6: d106 bne.n 8003ec6 <HAL_LTDC_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hltdc->Lock = HAL_UNLOCKED;
|
|
8003eb8: 687b ldr r3, [r7, #4]
|
|
8003eba: 2200 movs r2, #0
|
|
8003ebc: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
/* Init the low level hardware */
|
|
HAL_LTDC_MspInit(hltdc);
|
|
8003ec0: 6878 ldr r0, [r7, #4]
|
|
8003ec2: f7fc ffdb bl 8000e7c <HAL_LTDC_MspInit>
|
|
}
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
8003ec6: 687b ldr r3, [r7, #4]
|
|
8003ec8: 2202 movs r2, #2
|
|
8003eca: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Configure the HS, VS, DE and PC polarity */
|
|
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
|
|
8003ece: 687b ldr r3, [r7, #4]
|
|
8003ed0: 681b ldr r3, [r3, #0]
|
|
8003ed2: 699a ldr r2, [r3, #24]
|
|
8003ed4: 687b ldr r3, [r7, #4]
|
|
8003ed6: 681b ldr r3, [r3, #0]
|
|
8003ed8: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000
|
|
8003edc: 619a str r2, [r3, #24]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8003ede: 687b ldr r3, [r7, #4]
|
|
8003ee0: 681b ldr r3, [r3, #0]
|
|
8003ee2: 6999 ldr r1, [r3, #24]
|
|
8003ee4: 687b ldr r3, [r7, #4]
|
|
8003ee6: 685a ldr r2, [r3, #4]
|
|
8003ee8: 687b ldr r3, [r7, #4]
|
|
8003eea: 689b ldr r3, [r3, #8]
|
|
8003eec: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
8003eee: 687b ldr r3, [r7, #4]
|
|
8003ef0: 68db ldr r3, [r3, #12]
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8003ef2: 431a orrs r2, r3
|
|
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
|
|
8003ef4: 687b ldr r3, [r7, #4]
|
|
8003ef6: 691b ldr r3, [r3, #16]
|
|
8003ef8: 431a orrs r2, r3
|
|
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
|
|
8003efa: 687b ldr r3, [r7, #4]
|
|
8003efc: 681b ldr r3, [r3, #0]
|
|
8003efe: 430a orrs r2, r1
|
|
8003f00: 619a str r2, [r3, #24]
|
|
|
|
/* Set Synchronization size */
|
|
tmp = (hltdc->Init.HorizontalSync << 16U);
|
|
8003f02: 687b ldr r3, [r7, #4]
|
|
8003f04: 695b ldr r3, [r3, #20]
|
|
8003f06: 041b lsls r3, r3, #16
|
|
8003f08: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
|
|
8003f0a: 687b ldr r3, [r7, #4]
|
|
8003f0c: 6999 ldr r1, [r3, #24]
|
|
8003f0e: 687b ldr r3, [r7, #4]
|
|
8003f10: 681b ldr r3, [r3, #0]
|
|
8003f12: 68fa ldr r2, [r7, #12]
|
|
8003f14: 430a orrs r2, r1
|
|
8003f16: 609a str r2, [r3, #8]
|
|
|
|
/* Set Accumulated Back porch */
|
|
tmp = (hltdc->Init.AccumulatedHBP << 16U);
|
|
8003f18: 687b ldr r3, [r7, #4]
|
|
8003f1a: 69db ldr r3, [r3, #28]
|
|
8003f1c: 041b lsls r3, r3, #16
|
|
8003f1e: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
|
|
8003f20: 687b ldr r3, [r7, #4]
|
|
8003f22: 6a19 ldr r1, [r3, #32]
|
|
8003f24: 687b ldr r3, [r7, #4]
|
|
8003f26: 681b ldr r3, [r3, #0]
|
|
8003f28: 68fa ldr r2, [r7, #12]
|
|
8003f2a: 430a orrs r2, r1
|
|
8003f2c: 60da str r2, [r3, #12]
|
|
|
|
/* Set Accumulated Active Width */
|
|
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
|
|
8003f2e: 687b ldr r3, [r7, #4]
|
|
8003f30: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8003f32: 041b lsls r3, r3, #16
|
|
8003f34: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
|
|
8003f36: 687b ldr r3, [r7, #4]
|
|
8003f38: 6a99 ldr r1, [r3, #40] @ 0x28
|
|
8003f3a: 687b ldr r3, [r7, #4]
|
|
8003f3c: 681b ldr r3, [r3, #0]
|
|
8003f3e: 68fa ldr r2, [r7, #12]
|
|
8003f40: 430a orrs r2, r1
|
|
8003f42: 611a str r2, [r3, #16]
|
|
|
|
/* Set Total Width */
|
|
tmp = (hltdc->Init.TotalWidth << 16U);
|
|
8003f44: 687b ldr r3, [r7, #4]
|
|
8003f46: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003f48: 041b lsls r3, r3, #16
|
|
8003f4a: 60fb str r3, [r7, #12]
|
|
WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
|
|
8003f4c: 687b ldr r3, [r7, #4]
|
|
8003f4e: 6b19 ldr r1, [r3, #48] @ 0x30
|
|
8003f50: 687b ldr r3, [r7, #4]
|
|
8003f52: 681b ldr r3, [r3, #0]
|
|
8003f54: 68fa ldr r2, [r7, #12]
|
|
8003f56: 430a orrs r2, r1
|
|
8003f58: 615a str r2, [r3, #20]
|
|
|
|
/* Set the background color value */
|
|
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
|
|
8003f5a: 687b ldr r3, [r7, #4]
|
|
8003f5c: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
|
|
8003f60: 021b lsls r3, r3, #8
|
|
8003f62: 60fb str r3, [r7, #12]
|
|
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
|
|
8003f64: 687b ldr r3, [r7, #4]
|
|
8003f66: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
|
|
8003f6a: 041b lsls r3, r3, #16
|
|
8003f6c: 60bb str r3, [r7, #8]
|
|
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
|
|
8003f6e: 687b ldr r3, [r7, #4]
|
|
8003f70: 681b ldr r3, [r3, #0]
|
|
8003f72: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8003f74: 687b ldr r3, [r7, #4]
|
|
8003f76: 681b ldr r3, [r3, #0]
|
|
8003f78: f002 427f and.w r2, r2, #4278190080 @ 0xff000000
|
|
8003f7c: 62da str r2, [r3, #44] @ 0x2c
|
|
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
|
|
8003f7e: 687b ldr r3, [r7, #4]
|
|
8003f80: 681b ldr r3, [r3, #0]
|
|
8003f82: 6ad9 ldr r1, [r3, #44] @ 0x2c
|
|
8003f84: 68ba ldr r2, [r7, #8]
|
|
8003f86: 68fb ldr r3, [r7, #12]
|
|
8003f88: 4313 orrs r3, r2
|
|
8003f8a: 687a ldr r2, [r7, #4]
|
|
8003f8c: f892 2034 ldrb.w r2, [r2, #52] @ 0x34
|
|
8003f90: 431a orrs r2, r3
|
|
8003f92: 687b ldr r3, [r7, #4]
|
|
8003f94: 681b ldr r3, [r3, #0]
|
|
8003f96: 430a orrs r2, r1
|
|
8003f98: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Enable the Transfer Error and FIFO underrun interrupts */
|
|
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
|
|
8003f9a: 687b ldr r3, [r7, #4]
|
|
8003f9c: 681b ldr r3, [r3, #0]
|
|
8003f9e: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8003fa0: 687b ldr r3, [r7, #4]
|
|
8003fa2: 681b ldr r3, [r3, #0]
|
|
8003fa4: f042 0206 orr.w r2, r2, #6
|
|
8003fa8: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Enable LTDC by setting LTDCEN bit */
|
|
__HAL_LTDC_ENABLE(hltdc);
|
|
8003faa: 687b ldr r3, [r7, #4]
|
|
8003fac: 681b ldr r3, [r3, #0]
|
|
8003fae: 699a ldr r2, [r3, #24]
|
|
8003fb0: 687b ldr r3, [r7, #4]
|
|
8003fb2: 681b ldr r3, [r3, #0]
|
|
8003fb4: f042 0201 orr.w r2, r2, #1
|
|
8003fb8: 619a str r2, [r3, #24]
|
|
|
|
/* Initialize the error code */
|
|
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
|
|
8003fba: 687b ldr r3, [r7, #4]
|
|
8003fbc: 2200 movs r2, #0
|
|
8003fbe: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
8003fc2: 687b ldr r3, [r7, #4]
|
|
8003fc4: 2201 movs r2, #1
|
|
8003fc6: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
return HAL_OK;
|
|
8003fca: 2300 movs r3, #0
|
|
}
|
|
8003fcc: 4618 mov r0, r3
|
|
8003fce: 3710 adds r7, #16
|
|
8003fd0: 46bd mov sp, r7
|
|
8003fd2: bd80 pop {r7, pc}
|
|
|
|
08003fd4 <HAL_LTDC_IRQHandler>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval HAL status
|
|
*/
|
|
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8003fd4: b580 push {r7, lr}
|
|
8003fd6: b084 sub sp, #16
|
|
8003fd8: af00 add r7, sp, #0
|
|
8003fda: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
|
|
8003fdc: 687b ldr r3, [r7, #4]
|
|
8003fde: 681b ldr r3, [r3, #0]
|
|
8003fe0: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8003fe2: 60fb str r3, [r7, #12]
|
|
uint32_t itsources = READ_REG(hltdc->Instance->IER);
|
|
8003fe4: 687b ldr r3, [r7, #4]
|
|
8003fe6: 681b ldr r3, [r3, #0]
|
|
8003fe8: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003fea: 60bb str r3, [r7, #8]
|
|
|
|
/* Transfer Error Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
|
|
8003fec: 68fb ldr r3, [r7, #12]
|
|
8003fee: f003 0304 and.w r3, r3, #4
|
|
8003ff2: 2b00 cmp r3, #0
|
|
8003ff4: d023 beq.n 800403e <HAL_LTDC_IRQHandler+0x6a>
|
|
8003ff6: 68bb ldr r3, [r7, #8]
|
|
8003ff8: f003 0304 and.w r3, r3, #4
|
|
8003ffc: 2b00 cmp r3, #0
|
|
8003ffe: d01e beq.n 800403e <HAL_LTDC_IRQHandler+0x6a>
|
|
{
|
|
/* Disable the transfer Error interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
|
|
8004000: 687b ldr r3, [r7, #4]
|
|
8004002: 681b ldr r3, [r3, #0]
|
|
8004004: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8004006: 687b ldr r3, [r7, #4]
|
|
8004008: 681b ldr r3, [r3, #0]
|
|
800400a: f022 0204 bic.w r2, r2, #4
|
|
800400e: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the transfer error flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
|
|
8004010: 687b ldr r3, [r7, #4]
|
|
8004012: 681b ldr r3, [r3, #0]
|
|
8004014: 2204 movs r2, #4
|
|
8004016: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
|
|
8004018: 687b ldr r3, [r7, #4]
|
|
800401a: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
|
|
800401e: f043 0201 orr.w r2, r3, #1
|
|
8004022: 687b ldr r3, [r7, #4]
|
|
8004024: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
8004028: 687b ldr r3, [r7, #4]
|
|
800402a: 2204 movs r2, #4
|
|
800402c: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004030: 687b ldr r3, [r7, #4]
|
|
8004032: 2200 movs r2, #0
|
|
8004034: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
8004038: 6878 ldr r0, [r7, #4]
|
|
800403a: f000 f86f bl 800411c <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* FIFO underrun Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
|
|
800403e: 68fb ldr r3, [r7, #12]
|
|
8004040: f003 0302 and.w r3, r3, #2
|
|
8004044: 2b00 cmp r3, #0
|
|
8004046: d023 beq.n 8004090 <HAL_LTDC_IRQHandler+0xbc>
|
|
8004048: 68bb ldr r3, [r7, #8]
|
|
800404a: f003 0302 and.w r3, r3, #2
|
|
800404e: 2b00 cmp r3, #0
|
|
8004050: d01e beq.n 8004090 <HAL_LTDC_IRQHandler+0xbc>
|
|
{
|
|
/* Disable the FIFO underrun interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
|
|
8004052: 687b ldr r3, [r7, #4]
|
|
8004054: 681b ldr r3, [r3, #0]
|
|
8004056: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8004058: 687b ldr r3, [r7, #4]
|
|
800405a: 681b ldr r3, [r3, #0]
|
|
800405c: f022 0202 bic.w r2, r2, #2
|
|
8004060: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the FIFO underrun flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
|
|
8004062: 687b ldr r3, [r7, #4]
|
|
8004064: 681b ldr r3, [r3, #0]
|
|
8004066: 2202 movs r2, #2
|
|
8004068: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Update error code */
|
|
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
|
|
800406a: 687b ldr r3, [r7, #4]
|
|
800406c: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
|
|
8004070: f043 0202 orr.w r2, r3, #2
|
|
8004074: 687b ldr r3, [r7, #4]
|
|
8004076: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_ERROR;
|
|
800407a: 687b ldr r3, [r7, #4]
|
|
800407c: 2204 movs r2, #4
|
|
800407e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004082: 687b ldr r3, [r7, #4]
|
|
8004084: 2200 movs r2, #0
|
|
8004086: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
hltdc->ErrorCallback(hltdc);
|
|
#else
|
|
/* Call legacy error callback*/
|
|
HAL_LTDC_ErrorCallback(hltdc);
|
|
800408a: 6878 ldr r0, [r7, #4]
|
|
800408c: f000 f846 bl 800411c <HAL_LTDC_ErrorCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Line Interrupt management ************************************************/
|
|
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
|
|
8004090: 68fb ldr r3, [r7, #12]
|
|
8004092: f003 0301 and.w r3, r3, #1
|
|
8004096: 2b00 cmp r3, #0
|
|
8004098: d01b beq.n 80040d2 <HAL_LTDC_IRQHandler+0xfe>
|
|
800409a: 68bb ldr r3, [r7, #8]
|
|
800409c: f003 0301 and.w r3, r3, #1
|
|
80040a0: 2b00 cmp r3, #0
|
|
80040a2: d016 beq.n 80040d2 <HAL_LTDC_IRQHandler+0xfe>
|
|
{
|
|
/* Disable the Line interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
|
|
80040a4: 687b ldr r3, [r7, #4]
|
|
80040a6: 681b ldr r3, [r3, #0]
|
|
80040a8: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80040aa: 687b ldr r3, [r7, #4]
|
|
80040ac: 681b ldr r3, [r3, #0]
|
|
80040ae: f022 0201 bic.w r2, r2, #1
|
|
80040b2: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the Line interrupt flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
|
|
80040b4: 687b ldr r3, [r7, #4]
|
|
80040b6: 681b ldr r3, [r3, #0]
|
|
80040b8: 2201 movs r2, #1
|
|
80040ba: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
80040bc: 687b ldr r3, [r7, #4]
|
|
80040be: 2201 movs r2, #1
|
|
80040c0: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
80040c4: 687b ldr r3, [r7, #4]
|
|
80040c6: 2200 movs r2, #0
|
|
80040c8: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Line Event callback */
|
|
hltdc->LineEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Line Event callback */
|
|
HAL_LTDC_LineEventCallback(hltdc);
|
|
80040cc: 6878 ldr r0, [r7, #4]
|
|
80040ce: f000 f82f bl 8004130 <HAL_LTDC_LineEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Register reload Interrupt management ***************************************/
|
|
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
|
|
80040d2: 68fb ldr r3, [r7, #12]
|
|
80040d4: f003 0308 and.w r3, r3, #8
|
|
80040d8: 2b00 cmp r3, #0
|
|
80040da: d01b beq.n 8004114 <HAL_LTDC_IRQHandler+0x140>
|
|
80040dc: 68bb ldr r3, [r7, #8]
|
|
80040de: f003 0308 and.w r3, r3, #8
|
|
80040e2: 2b00 cmp r3, #0
|
|
80040e4: d016 beq.n 8004114 <HAL_LTDC_IRQHandler+0x140>
|
|
{
|
|
/* Disable the register reload interrupt */
|
|
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
|
|
80040e6: 687b ldr r3, [r7, #4]
|
|
80040e8: 681b ldr r3, [r3, #0]
|
|
80040ea: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80040ec: 687b ldr r3, [r7, #4]
|
|
80040ee: 681b ldr r3, [r3, #0]
|
|
80040f0: f022 0208 bic.w r2, r2, #8
|
|
80040f4: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Clear the register reload flag */
|
|
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
|
|
80040f6: 687b ldr r3, [r7, #4]
|
|
80040f8: 681b ldr r3, [r3, #0]
|
|
80040fa: 2208 movs r2, #8
|
|
80040fc: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change LTDC state */
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
80040fe: 687b ldr r3, [r7, #4]
|
|
8004100: 2201 movs r2, #1
|
|
8004102: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
8004106: 687b ldr r3, [r7, #4]
|
|
8004108: 2200 movs r2, #0
|
|
800410a: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
|
|
/*Call registered reload Event callback */
|
|
hltdc->ReloadEventCallback(hltdc);
|
|
#else
|
|
/*Call Legacy Reload Event callback */
|
|
HAL_LTDC_ReloadEventCallback(hltdc);
|
|
800410e: 6878 ldr r0, [r7, #4]
|
|
8004110: f000 f818 bl 8004144 <HAL_LTDC_ReloadEventCallback>
|
|
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
8004114: bf00 nop
|
|
8004116: 3710 adds r7, #16
|
|
8004118: 46bd mov sp, r7
|
|
800411a: bd80 pop {r7, pc}
|
|
|
|
0800411c <HAL_LTDC_ErrorCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
800411c: b480 push {r7}
|
|
800411e: b083 sub sp, #12
|
|
8004120: af00 add r7, sp, #0
|
|
8004122: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ErrorCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004124: bf00 nop
|
|
8004126: 370c adds r7, #12
|
|
8004128: 46bd mov sp, r7
|
|
800412a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800412e: 4770 bx lr
|
|
|
|
08004130 <HAL_LTDC_LineEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8004130: b480 push {r7}
|
|
8004132: b083 sub sp, #12
|
|
8004134: af00 add r7, sp, #0
|
|
8004136: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_LineEventCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8004138: bf00 nop
|
|
800413a: 370c adds r7, #12
|
|
800413c: 46bd mov sp, r7
|
|
800413e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004142: 4770 bx lr
|
|
|
|
08004144 <HAL_LTDC_ReloadEventCallback>:
|
|
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
|
|
* the configuration information for the LTDC.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
|
|
{
|
|
8004144: b480 push {r7}
|
|
8004146: b083 sub sp, #12
|
|
8004148: af00 add r7, sp, #0
|
|
800414a: 6078 str r0, [r7, #4]
|
|
UNUSED(hltdc);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800414c: bf00 nop
|
|
800414e: 370c adds r7, #12
|
|
8004150: 46bd mov sp, r7
|
|
8004152: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004156: 4770 bx lr
|
|
|
|
08004158 <HAL_LTDC_ConfigLayer>:
|
|
* This parameter can be one of the following values:
|
|
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
8004158: b5b0 push {r4, r5, r7, lr}
|
|
800415a: b084 sub sp, #16
|
|
800415c: af00 add r7, sp, #0
|
|
800415e: 60f8 str r0, [r7, #12]
|
|
8004160: 60b9 str r1, [r7, #8]
|
|
8004162: 607a str r2, [r7, #4]
|
|
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
|
|
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
|
|
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hltdc);
|
|
8004164: 68fb ldr r3, [r7, #12]
|
|
8004166: f893 30a0 ldrb.w r3, [r3, #160] @ 0xa0
|
|
800416a: 2b01 cmp r3, #1
|
|
800416c: d101 bne.n 8004172 <HAL_LTDC_ConfigLayer+0x1a>
|
|
800416e: 2302 movs r3, #2
|
|
8004170: e02c b.n 80041cc <HAL_LTDC_ConfigLayer+0x74>
|
|
8004172: 68fb ldr r3, [r7, #12]
|
|
8004174: 2201 movs r2, #1
|
|
8004176: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
|
|
/* Change LTDC peripheral state */
|
|
hltdc->State = HAL_LTDC_STATE_BUSY;
|
|
800417a: 68fb ldr r3, [r7, #12]
|
|
800417c: 2202 movs r2, #2
|
|
800417e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Copy new layer configuration into handle structure */
|
|
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
|
|
8004182: 68fa ldr r2, [r7, #12]
|
|
8004184: 687b ldr r3, [r7, #4]
|
|
8004186: 2134 movs r1, #52 @ 0x34
|
|
8004188: fb01 f303 mul.w r3, r1, r3
|
|
800418c: 4413 add r3, r2
|
|
800418e: f103 0238 add.w r2, r3, #56 @ 0x38
|
|
8004192: 68bb ldr r3, [r7, #8]
|
|
8004194: 4614 mov r4, r2
|
|
8004196: 461d mov r5, r3
|
|
8004198: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800419a: c40f stmia r4!, {r0, r1, r2, r3}
|
|
800419c: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
800419e: c40f stmia r4!, {r0, r1, r2, r3}
|
|
80041a0: cd0f ldmia r5!, {r0, r1, r2, r3}
|
|
80041a2: c40f stmia r4!, {r0, r1, r2, r3}
|
|
80041a4: 682b ldr r3, [r5, #0]
|
|
80041a6: 6023 str r3, [r4, #0]
|
|
|
|
/* Configure the LTDC Layer */
|
|
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
|
|
80041a8: 687a ldr r2, [r7, #4]
|
|
80041aa: 68b9 ldr r1, [r7, #8]
|
|
80041ac: 68f8 ldr r0, [r7, #12]
|
|
80041ae: f000 f811 bl 80041d4 <LTDC_SetConfig>
|
|
|
|
/* Set the Immediate Reload type */
|
|
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
|
|
80041b2: 68fb ldr r3, [r7, #12]
|
|
80041b4: 681b ldr r3, [r3, #0]
|
|
80041b6: 2201 movs r2, #1
|
|
80041b8: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
/* Initialize the LTDC state*/
|
|
hltdc->State = HAL_LTDC_STATE_READY;
|
|
80041ba: 68fb ldr r3, [r7, #12]
|
|
80041bc: 2201 movs r2, #1
|
|
80041be: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hltdc);
|
|
80041c2: 68fb ldr r3, [r7, #12]
|
|
80041c4: 2200 movs r2, #0
|
|
80041c6: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
|
|
|
|
return HAL_OK;
|
|
80041ca: 2300 movs r3, #0
|
|
}
|
|
80041cc: 4618 mov r0, r3
|
|
80041ce: 3710 adds r7, #16
|
|
80041d0: 46bd mov sp, r7
|
|
80041d2: bdb0 pop {r4, r5, r7, pc}
|
|
|
|
080041d4 <LTDC_SetConfig>:
|
|
* @param LayerIdx LTDC Layer index.
|
|
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
|
|
* @retval None
|
|
*/
|
|
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
|
|
{
|
|
80041d4: b480 push {r7}
|
|
80041d6: b089 sub sp, #36 @ 0x24
|
|
80041d8: af00 add r7, sp, #0
|
|
80041da: 60f8 str r0, [r7, #12]
|
|
80041dc: 60b9 str r1, [r7, #8]
|
|
80041de: 607a str r2, [r7, #4]
|
|
uint32_t tmp;
|
|
uint32_t tmp1;
|
|
uint32_t tmp2;
|
|
|
|
/* Configure the horizontal start and stop position */
|
|
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
|
|
80041e0: 68bb ldr r3, [r7, #8]
|
|
80041e2: 685a ldr r2, [r3, #4]
|
|
80041e4: 68fb ldr r3, [r7, #12]
|
|
80041e6: 681b ldr r3, [r3, #0]
|
|
80041e8: 68db ldr r3, [r3, #12]
|
|
80041ea: 0c1b lsrs r3, r3, #16
|
|
80041ec: f3c3 030b ubfx r3, r3, #0, #12
|
|
80041f0: 4413 add r3, r2
|
|
80041f2: 041b lsls r3, r3, #16
|
|
80041f4: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
|
|
80041f6: 68fb ldr r3, [r7, #12]
|
|
80041f8: 681b ldr r3, [r3, #0]
|
|
80041fa: 461a mov r2, r3
|
|
80041fc: 687b ldr r3, [r7, #4]
|
|
80041fe: 01db lsls r3, r3, #7
|
|
8004200: 4413 add r3, r2
|
|
8004202: 3384 adds r3, #132 @ 0x84
|
|
8004204: 685b ldr r3, [r3, #4]
|
|
8004206: 68fa ldr r2, [r7, #12]
|
|
8004208: 6812 ldr r2, [r2, #0]
|
|
800420a: 4611 mov r1, r2
|
|
800420c: 687a ldr r2, [r7, #4]
|
|
800420e: 01d2 lsls r2, r2, #7
|
|
8004210: 440a add r2, r1
|
|
8004212: 3284 adds r2, #132 @ 0x84
|
|
8004214: f403 4370 and.w r3, r3, #61440 @ 0xf000
|
|
8004218: 6053 str r3, [r2, #4]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
800421a: 68bb ldr r3, [r7, #8]
|
|
800421c: 681a ldr r2, [r3, #0]
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
800421e: 68fb ldr r3, [r7, #12]
|
|
8004220: 681b ldr r3, [r3, #0]
|
|
8004222: 68db ldr r3, [r3, #12]
|
|
8004224: 0c1b lsrs r3, r3, #16
|
|
8004226: f3c3 030b ubfx r3, r3, #0, #12
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
800422a: 4413 add r3, r2
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
800422c: 1c5a adds r2, r3, #1
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
800422e: 68fb ldr r3, [r7, #12]
|
|
8004230: 681b ldr r3, [r3, #0]
|
|
8004232: 4619 mov r1, r3
|
|
8004234: 687b ldr r3, [r7, #4]
|
|
8004236: 01db lsls r3, r3, #7
|
|
8004238: 440b add r3, r1
|
|
800423a: 3384 adds r3, #132 @ 0x84
|
|
800423c: 4619 mov r1, r3
|
|
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
|
|
800423e: 69fb ldr r3, [r7, #28]
|
|
8004240: 4313 orrs r3, r2
|
|
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
|
|
8004242: 604b str r3, [r1, #4]
|
|
|
|
/* Configure the vertical start and stop position */
|
|
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
|
|
8004244: 68bb ldr r3, [r7, #8]
|
|
8004246: 68da ldr r2, [r3, #12]
|
|
8004248: 68fb ldr r3, [r7, #12]
|
|
800424a: 681b ldr r3, [r3, #0]
|
|
800424c: 68db ldr r3, [r3, #12]
|
|
800424e: f3c3 030a ubfx r3, r3, #0, #11
|
|
8004252: 4413 add r3, r2
|
|
8004254: 041b lsls r3, r3, #16
|
|
8004256: 61fb str r3, [r7, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
|
|
8004258: 68fb ldr r3, [r7, #12]
|
|
800425a: 681b ldr r3, [r3, #0]
|
|
800425c: 461a mov r2, r3
|
|
800425e: 687b ldr r3, [r7, #4]
|
|
8004260: 01db lsls r3, r3, #7
|
|
8004262: 4413 add r3, r2
|
|
8004264: 3384 adds r3, #132 @ 0x84
|
|
8004266: 689b ldr r3, [r3, #8]
|
|
8004268: 68fa ldr r2, [r7, #12]
|
|
800426a: 6812 ldr r2, [r2, #0]
|
|
800426c: 4611 mov r1, r2
|
|
800426e: 687a ldr r2, [r7, #4]
|
|
8004270: 01d2 lsls r2, r2, #7
|
|
8004272: 440a add r2, r1
|
|
8004274: 3284 adds r2, #132 @ 0x84
|
|
8004276: f403 4370 and.w r3, r3, #61440 @ 0xf000
|
|
800427a: 6093 str r3, [r2, #8]
|
|
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
|
|
800427c: 68bb ldr r3, [r7, #8]
|
|
800427e: 689a ldr r2, [r3, #8]
|
|
8004280: 68fb ldr r3, [r7, #12]
|
|
8004282: 681b ldr r3, [r3, #0]
|
|
8004284: 68db ldr r3, [r3, #12]
|
|
8004286: f3c3 030a ubfx r3, r3, #0, #11
|
|
800428a: 4413 add r3, r2
|
|
800428c: 1c5a adds r2, r3, #1
|
|
800428e: 68fb ldr r3, [r7, #12]
|
|
8004290: 681b ldr r3, [r3, #0]
|
|
8004292: 4619 mov r1, r3
|
|
8004294: 687b ldr r3, [r7, #4]
|
|
8004296: 01db lsls r3, r3, #7
|
|
8004298: 440b add r3, r1
|
|
800429a: 3384 adds r3, #132 @ 0x84
|
|
800429c: 4619 mov r1, r3
|
|
800429e: 69fb ldr r3, [r7, #28]
|
|
80042a0: 4313 orrs r3, r2
|
|
80042a2: 608b str r3, [r1, #8]
|
|
|
|
/* Specifies the pixel format */
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
|
|
80042a4: 68fb ldr r3, [r7, #12]
|
|
80042a6: 681b ldr r3, [r3, #0]
|
|
80042a8: 461a mov r2, r3
|
|
80042aa: 687b ldr r3, [r7, #4]
|
|
80042ac: 01db lsls r3, r3, #7
|
|
80042ae: 4413 add r3, r2
|
|
80042b0: 3384 adds r3, #132 @ 0x84
|
|
80042b2: 691b ldr r3, [r3, #16]
|
|
80042b4: 68fa ldr r2, [r7, #12]
|
|
80042b6: 6812 ldr r2, [r2, #0]
|
|
80042b8: 4611 mov r1, r2
|
|
80042ba: 687a ldr r2, [r7, #4]
|
|
80042bc: 01d2 lsls r2, r2, #7
|
|
80042be: 440a add r2, r1
|
|
80042c0: 3284 adds r2, #132 @ 0x84
|
|
80042c2: f023 0307 bic.w r3, r3, #7
|
|
80042c6: 6113 str r3, [r2, #16]
|
|
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
|
|
80042c8: 68fb ldr r3, [r7, #12]
|
|
80042ca: 681b ldr r3, [r3, #0]
|
|
80042cc: 461a mov r2, r3
|
|
80042ce: 687b ldr r3, [r7, #4]
|
|
80042d0: 01db lsls r3, r3, #7
|
|
80042d2: 4413 add r3, r2
|
|
80042d4: 3384 adds r3, #132 @ 0x84
|
|
80042d6: 461a mov r2, r3
|
|
80042d8: 68bb ldr r3, [r7, #8]
|
|
80042da: 691b ldr r3, [r3, #16]
|
|
80042dc: 6113 str r3, [r2, #16]
|
|
|
|
/* Configure the default color values */
|
|
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
|
|
80042de: 68bb ldr r3, [r7, #8]
|
|
80042e0: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
|
|
80042e4: 021b lsls r3, r3, #8
|
|
80042e6: 61fb str r3, [r7, #28]
|
|
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
|
|
80042e8: 68bb ldr r3, [r7, #8]
|
|
80042ea: f893 3032 ldrb.w r3, [r3, #50] @ 0x32
|
|
80042ee: 041b lsls r3, r3, #16
|
|
80042f0: 61bb str r3, [r7, #24]
|
|
tmp2 = (pLayerCfg->Alpha0 << 24U);
|
|
80042f2: 68bb ldr r3, [r7, #8]
|
|
80042f4: 699b ldr r3, [r3, #24]
|
|
80042f6: 061b lsls r3, r3, #24
|
|
80042f8: 617b str r3, [r7, #20]
|
|
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2));
|
|
80042fa: 68bb ldr r3, [r7, #8]
|
|
80042fc: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
|
|
8004300: 461a mov r2, r3
|
|
8004302: 69fb ldr r3, [r7, #28]
|
|
8004304: 431a orrs r2, r3
|
|
8004306: 69bb ldr r3, [r7, #24]
|
|
8004308: 431a orrs r2, r3
|
|
800430a: 68fb ldr r3, [r7, #12]
|
|
800430c: 681b ldr r3, [r3, #0]
|
|
800430e: 4619 mov r1, r3
|
|
8004310: 687b ldr r3, [r7, #4]
|
|
8004312: 01db lsls r3, r3, #7
|
|
8004314: 440b add r3, r1
|
|
8004316: 3384 adds r3, #132 @ 0x84
|
|
8004318: 4619 mov r1, r3
|
|
800431a: 697b ldr r3, [r7, #20]
|
|
800431c: 4313 orrs r3, r2
|
|
800431e: 618b str r3, [r1, #24]
|
|
|
|
/* Specifies the constant alpha value */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
|
|
8004320: 68fb ldr r3, [r7, #12]
|
|
8004322: 681b ldr r3, [r3, #0]
|
|
8004324: 461a mov r2, r3
|
|
8004326: 687b ldr r3, [r7, #4]
|
|
8004328: 01db lsls r3, r3, #7
|
|
800432a: 4413 add r3, r2
|
|
800432c: 3384 adds r3, #132 @ 0x84
|
|
800432e: 695b ldr r3, [r3, #20]
|
|
8004330: 68fa ldr r2, [r7, #12]
|
|
8004332: 6812 ldr r2, [r2, #0]
|
|
8004334: 4611 mov r1, r2
|
|
8004336: 687a ldr r2, [r7, #4]
|
|
8004338: 01d2 lsls r2, r2, #7
|
|
800433a: 440a add r2, r1
|
|
800433c: 3284 adds r2, #132 @ 0x84
|
|
800433e: f023 03ff bic.w r3, r3, #255 @ 0xff
|
|
8004342: 6153 str r3, [r2, #20]
|
|
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
|
|
8004344: 68fb ldr r3, [r7, #12]
|
|
8004346: 681b ldr r3, [r3, #0]
|
|
8004348: 461a mov r2, r3
|
|
800434a: 687b ldr r3, [r7, #4]
|
|
800434c: 01db lsls r3, r3, #7
|
|
800434e: 4413 add r3, r2
|
|
8004350: 3384 adds r3, #132 @ 0x84
|
|
8004352: 461a mov r2, r3
|
|
8004354: 68bb ldr r3, [r7, #8]
|
|
8004356: 695b ldr r3, [r3, #20]
|
|
8004358: 6153 str r3, [r2, #20]
|
|
|
|
/* Specifies the blending factors */
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
|
|
800435a: 68fb ldr r3, [r7, #12]
|
|
800435c: 681b ldr r3, [r3, #0]
|
|
800435e: 461a mov r2, r3
|
|
8004360: 687b ldr r3, [r7, #4]
|
|
8004362: 01db lsls r3, r3, #7
|
|
8004364: 4413 add r3, r2
|
|
8004366: 3384 adds r3, #132 @ 0x84
|
|
8004368: 69db ldr r3, [r3, #28]
|
|
800436a: 68fa ldr r2, [r7, #12]
|
|
800436c: 6812 ldr r2, [r2, #0]
|
|
800436e: 4611 mov r1, r2
|
|
8004370: 687a ldr r2, [r7, #4]
|
|
8004372: 01d2 lsls r2, r2, #7
|
|
8004374: 440a add r2, r1
|
|
8004376: 3284 adds r2, #132 @ 0x84
|
|
8004378: f423 63e0 bic.w r3, r3, #1792 @ 0x700
|
|
800437c: f023 0307 bic.w r3, r3, #7
|
|
8004380: 61d3 str r3, [r2, #28]
|
|
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
|
|
8004382: 68bb ldr r3, [r7, #8]
|
|
8004384: 69da ldr r2, [r3, #28]
|
|
8004386: 68bb ldr r3, [r7, #8]
|
|
8004388: 6a1b ldr r3, [r3, #32]
|
|
800438a: 68f9 ldr r1, [r7, #12]
|
|
800438c: 6809 ldr r1, [r1, #0]
|
|
800438e: 4608 mov r0, r1
|
|
8004390: 6879 ldr r1, [r7, #4]
|
|
8004392: 01c9 lsls r1, r1, #7
|
|
8004394: 4401 add r1, r0
|
|
8004396: 3184 adds r1, #132 @ 0x84
|
|
8004398: 4313 orrs r3, r2
|
|
800439a: 61cb str r3, [r1, #28]
|
|
|
|
/* Configure the color frame buffer start address */
|
|
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress);
|
|
800439c: 68fb ldr r3, [r7, #12]
|
|
800439e: 681b ldr r3, [r3, #0]
|
|
80043a0: 461a mov r2, r3
|
|
80043a2: 687b ldr r3, [r7, #4]
|
|
80043a4: 01db lsls r3, r3, #7
|
|
80043a6: 4413 add r3, r2
|
|
80043a8: 3384 adds r3, #132 @ 0x84
|
|
80043aa: 461a mov r2, r3
|
|
80043ac: 68bb ldr r3, [r7, #8]
|
|
80043ae: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80043b0: 6293 str r3, [r2, #40] @ 0x28
|
|
|
|
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
|
|
80043b2: 68bb ldr r3, [r7, #8]
|
|
80043b4: 691b ldr r3, [r3, #16]
|
|
80043b6: 2b00 cmp r3, #0
|
|
80043b8: d102 bne.n 80043c0 <LTDC_SetConfig+0x1ec>
|
|
{
|
|
tmp = 4U;
|
|
80043ba: 2304 movs r3, #4
|
|
80043bc: 61fb str r3, [r7, #28]
|
|
80043be: e01b b.n 80043f8 <LTDC_SetConfig+0x224>
|
|
}
|
|
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
|
|
80043c0: 68bb ldr r3, [r7, #8]
|
|
80043c2: 691b ldr r3, [r3, #16]
|
|
80043c4: 2b01 cmp r3, #1
|
|
80043c6: d102 bne.n 80043ce <LTDC_SetConfig+0x1fa>
|
|
{
|
|
tmp = 3U;
|
|
80043c8: 2303 movs r3, #3
|
|
80043ca: 61fb str r3, [r7, #28]
|
|
80043cc: e014 b.n 80043f8 <LTDC_SetConfig+0x224>
|
|
}
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
80043ce: 68bb ldr r3, [r7, #8]
|
|
80043d0: 691b ldr r3, [r3, #16]
|
|
80043d2: 2b04 cmp r3, #4
|
|
80043d4: d00b beq.n 80043ee <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
80043d6: 68bb ldr r3, [r7, #8]
|
|
80043d8: 691b ldr r3, [r3, #16]
|
|
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
|
|
80043da: 2b02 cmp r3, #2
|
|
80043dc: d007 beq.n 80043ee <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
80043de: 68bb ldr r3, [r7, #8]
|
|
80043e0: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
|
|
80043e2: 2b03 cmp r3, #3
|
|
80043e4: d003 beq.n 80043ee <LTDC_SetConfig+0x21a>
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
|
|
80043e6: 68bb ldr r3, [r7, #8]
|
|
80043e8: 691b ldr r3, [r3, #16]
|
|
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
|
|
80043ea: 2b07 cmp r3, #7
|
|
80043ec: d102 bne.n 80043f4 <LTDC_SetConfig+0x220>
|
|
{
|
|
tmp = 2U;
|
|
80043ee: 2302 movs r3, #2
|
|
80043f0: 61fb str r3, [r7, #28]
|
|
80043f2: e001 b.n 80043f8 <LTDC_SetConfig+0x224>
|
|
}
|
|
else
|
|
{
|
|
tmp = 1U;
|
|
80043f4: 2301 movs r3, #1
|
|
80043f6: 61fb str r3, [r7, #28]
|
|
}
|
|
|
|
/* Configure the color frame buffer pitch in byte */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
|
|
80043f8: 68fb ldr r3, [r7, #12]
|
|
80043fa: 681b ldr r3, [r3, #0]
|
|
80043fc: 461a mov r2, r3
|
|
80043fe: 687b ldr r3, [r7, #4]
|
|
8004400: 01db lsls r3, r3, #7
|
|
8004402: 4413 add r3, r2
|
|
8004404: 3384 adds r3, #132 @ 0x84
|
|
8004406: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004408: 68fa ldr r2, [r7, #12]
|
|
800440a: 6812 ldr r2, [r2, #0]
|
|
800440c: 4611 mov r1, r2
|
|
800440e: 687a ldr r2, [r7, #4]
|
|
8004410: 01d2 lsls r2, r2, #7
|
|
8004412: 440a add r2, r1
|
|
8004414: 3284 adds r2, #132 @ 0x84
|
|
8004416: f003 23e0 and.w r3, r3, #3758153728 @ 0xe000e000
|
|
800441a: 62d3 str r3, [r2, #44] @ 0x2c
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
|
|
800441c: 68bb ldr r3, [r7, #8]
|
|
800441e: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8004420: 69fa ldr r2, [r7, #28]
|
|
8004422: fb02 f303 mul.w r3, r2, r3
|
|
8004426: 041a lsls r2, r3, #16
|
|
(((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
|
|
8004428: 68bb ldr r3, [r7, #8]
|
|
800442a: 6859 ldr r1, [r3, #4]
|
|
800442c: 68bb ldr r3, [r7, #8]
|
|
800442e: 681b ldr r3, [r3, #0]
|
|
8004430: 1acb subs r3, r1, r3
|
|
8004432: 69f9 ldr r1, [r7, #28]
|
|
8004434: fb01 f303 mul.w r3, r1, r3
|
|
8004438: 3303 adds r3, #3
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
|
|
800443a: 68f9 ldr r1, [r7, #12]
|
|
800443c: 6809 ldr r1, [r1, #0]
|
|
800443e: 4608 mov r0, r1
|
|
8004440: 6879 ldr r1, [r7, #4]
|
|
8004442: 01c9 lsls r1, r1, #7
|
|
8004444: 4401 add r1, r0
|
|
8004446: 3184 adds r1, #132 @ 0x84
|
|
8004448: 4313 orrs r3, r2
|
|
800444a: 62cb str r3, [r1, #44] @ 0x2c
|
|
/* Configure the frame buffer line number */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
|
|
800444c: 68fb ldr r3, [r7, #12]
|
|
800444e: 681b ldr r3, [r3, #0]
|
|
8004450: 461a mov r2, r3
|
|
8004452: 687b ldr r3, [r7, #4]
|
|
8004454: 01db lsls r3, r3, #7
|
|
8004456: 4413 add r3, r2
|
|
8004458: 3384 adds r3, #132 @ 0x84
|
|
800445a: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
800445c: 68fa ldr r2, [r7, #12]
|
|
800445e: 6812 ldr r2, [r2, #0]
|
|
8004460: 4611 mov r1, r2
|
|
8004462: 687a ldr r2, [r7, #4]
|
|
8004464: 01d2 lsls r2, r2, #7
|
|
8004466: 440a add r2, r1
|
|
8004468: 3284 adds r2, #132 @ 0x84
|
|
800446a: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
|
|
800446e: f023 0307 bic.w r3, r3, #7
|
|
8004472: 6313 str r3, [r2, #48] @ 0x30
|
|
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
|
|
8004474: 68fb ldr r3, [r7, #12]
|
|
8004476: 681b ldr r3, [r3, #0]
|
|
8004478: 461a mov r2, r3
|
|
800447a: 687b ldr r3, [r7, #4]
|
|
800447c: 01db lsls r3, r3, #7
|
|
800447e: 4413 add r3, r2
|
|
8004480: 3384 adds r3, #132 @ 0x84
|
|
8004482: 461a mov r2, r3
|
|
8004484: 68bb ldr r3, [r7, #8]
|
|
8004486: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004488: 6313 str r3, [r2, #48] @ 0x30
|
|
|
|
/* Enable LTDC_Layer by setting LEN bit */
|
|
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
|
|
800448a: 68fb ldr r3, [r7, #12]
|
|
800448c: 681b ldr r3, [r3, #0]
|
|
800448e: 461a mov r2, r3
|
|
8004490: 687b ldr r3, [r7, #4]
|
|
8004492: 01db lsls r3, r3, #7
|
|
8004494: 4413 add r3, r2
|
|
8004496: 3384 adds r3, #132 @ 0x84
|
|
8004498: 681b ldr r3, [r3, #0]
|
|
800449a: 68fa ldr r2, [r7, #12]
|
|
800449c: 6812 ldr r2, [r2, #0]
|
|
800449e: 4611 mov r1, r2
|
|
80044a0: 687a ldr r2, [r7, #4]
|
|
80044a2: 01d2 lsls r2, r2, #7
|
|
80044a4: 440a add r2, r1
|
|
80044a6: 3284 adds r2, #132 @ 0x84
|
|
80044a8: f043 0301 orr.w r3, r3, #1
|
|
80044ac: 6013 str r3, [r2, #0]
|
|
}
|
|
80044ae: bf00 nop
|
|
80044b0: 3724 adds r7, #36 @ 0x24
|
|
80044b2: 46bd mov sp, r7
|
|
80044b4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80044b8: 4770 bx lr
|
|
...
|
|
|
|
080044bc <HAL_RCC_OscConfig>:
|
|
* supported by this API. User should request a transition to HSE Off
|
|
* first and then HSE On or HSE Bypass.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
80044bc: b580 push {r7, lr}
|
|
80044be: b086 sub sp, #24
|
|
80044c0: af00 add r7, sp, #0
|
|
80044c2: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
uint32_t pll_config;
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
80044c4: 687b ldr r3, [r7, #4]
|
|
80044c6: 2b00 cmp r3, #0
|
|
80044c8: d101 bne.n 80044ce <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
80044ca: 2301 movs r3, #1
|
|
80044cc: e267 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
80044ce: 687b ldr r3, [r7, #4]
|
|
80044d0: 681b ldr r3, [r3, #0]
|
|
80044d2: f003 0301 and.w r3, r3, #1
|
|
80044d6: 2b00 cmp r3, #0
|
|
80044d8: d075 beq.n 80045c6 <HAL_RCC_OscConfig+0x10a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
|
|
80044da: 4b88 ldr r3, [pc, #544] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80044dc: 689b ldr r3, [r3, #8]
|
|
80044de: f003 030c and.w r3, r3, #12
|
|
80044e2: 2b04 cmp r3, #4
|
|
80044e4: d00c beq.n 8004500 <HAL_RCC_OscConfig+0x44>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80044e6: 4b85 ldr r3, [pc, #532] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80044e8: 689b ldr r3, [r3, #8]
|
|
80044ea: f003 030c and.w r3, r3, #12
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
|
|
80044ee: 2b08 cmp r3, #8
|
|
80044f0: d112 bne.n 8004518 <HAL_RCC_OscConfig+0x5c>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
|
|
80044f2: 4b82 ldr r3, [pc, #520] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80044f4: 685b ldr r3, [r3, #4]
|
|
80044f6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80044fa: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80044fe: d10b bne.n 8004518 <HAL_RCC_OscConfig+0x5c>
|
|
{
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8004500: 4b7e ldr r3, [pc, #504] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004502: 681b ldr r3, [r3, #0]
|
|
8004504: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004508: 2b00 cmp r3, #0
|
|
800450a: d05b beq.n 80045c4 <HAL_RCC_OscConfig+0x108>
|
|
800450c: 687b ldr r3, [r7, #4]
|
|
800450e: 685b ldr r3, [r3, #4]
|
|
8004510: 2b00 cmp r3, #0
|
|
8004512: d157 bne.n 80045c4 <HAL_RCC_OscConfig+0x108>
|
|
{
|
|
return HAL_ERROR;
|
|
8004514: 2301 movs r3, #1
|
|
8004516: e242 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8004518: 687b ldr r3, [r7, #4]
|
|
800451a: 685b ldr r3, [r3, #4]
|
|
800451c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8004520: d106 bne.n 8004530 <HAL_RCC_OscConfig+0x74>
|
|
8004522: 4b76 ldr r3, [pc, #472] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004524: 681b ldr r3, [r3, #0]
|
|
8004526: 4a75 ldr r2, [pc, #468] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004528: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800452c: 6013 str r3, [r2, #0]
|
|
800452e: e01d b.n 800456c <HAL_RCC_OscConfig+0xb0>
|
|
8004530: 687b ldr r3, [r7, #4]
|
|
8004532: 685b ldr r3, [r3, #4]
|
|
8004534: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8004538: d10c bne.n 8004554 <HAL_RCC_OscConfig+0x98>
|
|
800453a: 4b70 ldr r3, [pc, #448] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800453c: 681b ldr r3, [r3, #0]
|
|
800453e: 4a6f ldr r2, [pc, #444] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004540: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8004544: 6013 str r3, [r2, #0]
|
|
8004546: 4b6d ldr r3, [pc, #436] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004548: 681b ldr r3, [r3, #0]
|
|
800454a: 4a6c ldr r2, [pc, #432] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800454c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004550: 6013 str r3, [r2, #0]
|
|
8004552: e00b b.n 800456c <HAL_RCC_OscConfig+0xb0>
|
|
8004554: 4b69 ldr r3, [pc, #420] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004556: 681b ldr r3, [r3, #0]
|
|
8004558: 4a68 ldr r2, [pc, #416] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800455a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
800455e: 6013 str r3, [r2, #0]
|
|
8004560: 4b66 ldr r3, [pc, #408] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004562: 681b ldr r3, [r3, #0]
|
|
8004564: 4a65 ldr r2, [pc, #404] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004566: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
800456a: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
|
|
800456c: 687b ldr r3, [r7, #4]
|
|
800456e: 685b ldr r3, [r3, #4]
|
|
8004570: 2b00 cmp r3, #0
|
|
8004572: d013 beq.n 800459c <HAL_RCC_OscConfig+0xe0>
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004574: f7fd f832 bl 80015dc <HAL_GetTick>
|
|
8004578: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800457a: e008 b.n 800458e <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
800457c: f7fd f82e bl 80015dc <HAL_GetTick>
|
|
8004580: 4602 mov r2, r0
|
|
8004582: 693b ldr r3, [r7, #16]
|
|
8004584: 1ad3 subs r3, r2, r3
|
|
8004586: 2b64 cmp r3, #100 @ 0x64
|
|
8004588: d901 bls.n 800458e <HAL_RCC_OscConfig+0xd2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800458a: 2303 movs r3, #3
|
|
800458c: e207 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
800458e: 4b5b ldr r3, [pc, #364] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004590: 681b ldr r3, [r3, #0]
|
|
8004592: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004596: 2b00 cmp r3, #0
|
|
8004598: d0f0 beq.n 800457c <HAL_RCC_OscConfig+0xc0>
|
|
800459a: e014 b.n 80045c6 <HAL_RCC_OscConfig+0x10a>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
800459c: f7fd f81e bl 80015dc <HAL_GetTick>
|
|
80045a0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is bypassed or disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80045a2: e008 b.n 80045b6 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
80045a4: f7fd f81a bl 80015dc <HAL_GetTick>
|
|
80045a8: 4602 mov r2, r0
|
|
80045aa: 693b ldr r3, [r7, #16]
|
|
80045ac: 1ad3 subs r3, r2, r3
|
|
80045ae: 2b64 cmp r3, #100 @ 0x64
|
|
80045b0: d901 bls.n 80045b6 <HAL_RCC_OscConfig+0xfa>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80045b2: 2303 movs r3, #3
|
|
80045b4: e1f3 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
|
|
80045b6: 4b51 ldr r3, [pc, #324] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80045b8: 681b ldr r3, [r3, #0]
|
|
80045ba: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80045be: 2b00 cmp r3, #0
|
|
80045c0: d1f0 bne.n 80045a4 <HAL_RCC_OscConfig+0xe8>
|
|
80045c2: e000 b.n 80045c6 <HAL_RCC_OscConfig+0x10a>
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
80045c4: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
80045c6: 687b ldr r3, [r7, #4]
|
|
80045c8: 681b ldr r3, [r3, #0]
|
|
80045ca: f003 0302 and.w r3, r3, #2
|
|
80045ce: 2b00 cmp r3, #0
|
|
80045d0: d063 beq.n 800469a <HAL_RCC_OscConfig+0x1de>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
|
|
80045d2: 4b4a ldr r3, [pc, #296] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80045d4: 689b ldr r3, [r3, #8]
|
|
80045d6: f003 030c and.w r3, r3, #12
|
|
80045da: 2b00 cmp r3, #0
|
|
80045dc: d00b beq.n 80045f6 <HAL_RCC_OscConfig+0x13a>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
80045de: 4b47 ldr r3, [pc, #284] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80045e0: 689b ldr r3, [r3, #8]
|
|
80045e2: f003 030c and.w r3, r3, #12
|
|
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
|
|
80045e6: 2b08 cmp r3, #8
|
|
80045e8: d11c bne.n 8004624 <HAL_RCC_OscConfig+0x168>
|
|
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
|
|
80045ea: 4b44 ldr r3, [pc, #272] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80045ec: 685b ldr r3, [r3, #4]
|
|
80045ee: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80045f2: 2b00 cmp r3, #0
|
|
80045f4: d116 bne.n 8004624 <HAL_RCC_OscConfig+0x168>
|
|
{
|
|
/* When HSI is used as system clock it will not disabled */
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
80045f6: 4b41 ldr r3, [pc, #260] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80045f8: 681b ldr r3, [r3, #0]
|
|
80045fa: f003 0302 and.w r3, r3, #2
|
|
80045fe: 2b00 cmp r3, #0
|
|
8004600: d005 beq.n 800460e <HAL_RCC_OscConfig+0x152>
|
|
8004602: 687b ldr r3, [r7, #4]
|
|
8004604: 68db ldr r3, [r3, #12]
|
|
8004606: 2b01 cmp r3, #1
|
|
8004608: d001 beq.n 800460e <HAL_RCC_OscConfig+0x152>
|
|
{
|
|
return HAL_ERROR;
|
|
800460a: 2301 movs r3, #1
|
|
800460c: e1c7 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
800460e: 4b3b ldr r3, [pc, #236] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004610: 681b ldr r3, [r3, #0]
|
|
8004612: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004616: 687b ldr r3, [r7, #4]
|
|
8004618: 691b ldr r3, [r3, #16]
|
|
800461a: 00db lsls r3, r3, #3
|
|
800461c: 4937 ldr r1, [pc, #220] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800461e: 4313 orrs r3, r2
|
|
8004620: 600b str r3, [r1, #0]
|
|
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
|
|
8004622: e03a b.n 800469a <HAL_RCC_OscConfig+0x1de>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
|
|
8004624: 687b ldr r3, [r7, #4]
|
|
8004626: 68db ldr r3, [r3, #12]
|
|
8004628: 2b00 cmp r3, #0
|
|
800462a: d020 beq.n 800466e <HAL_RCC_OscConfig+0x1b2>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
800462c: 4b34 ldr r3, [pc, #208] @ (8004700 <HAL_RCC_OscConfig+0x244>)
|
|
800462e: 2201 movs r2, #1
|
|
8004630: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004632: f7fc ffd3 bl 80015dc <HAL_GetTick>
|
|
8004636: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004638: e008 b.n 800464c <HAL_RCC_OscConfig+0x190>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800463a: f7fc ffcf bl 80015dc <HAL_GetTick>
|
|
800463e: 4602 mov r2, r0
|
|
8004640: 693b ldr r3, [r7, #16]
|
|
8004642: 1ad3 subs r3, r2, r3
|
|
8004644: 2b02 cmp r3, #2
|
|
8004646: d901 bls.n 800464c <HAL_RCC_OscConfig+0x190>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004648: 2303 movs r3, #3
|
|
800464a: e1a8 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
800464c: 4b2b ldr r3, [pc, #172] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800464e: 681b ldr r3, [r3, #0]
|
|
8004650: f003 0302 and.w r3, r3, #2
|
|
8004654: 2b00 cmp r3, #0
|
|
8004656: d0f0 beq.n 800463a <HAL_RCC_OscConfig+0x17e>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8004658: 4b28 ldr r3, [pc, #160] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
800465a: 681b ldr r3, [r3, #0]
|
|
800465c: f023 02f8 bic.w r2, r3, #248 @ 0xf8
|
|
8004660: 687b ldr r3, [r7, #4]
|
|
8004662: 691b ldr r3, [r3, #16]
|
|
8004664: 00db lsls r3, r3, #3
|
|
8004666: 4925 ldr r1, [pc, #148] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004668: 4313 orrs r3, r2
|
|
800466a: 600b str r3, [r1, #0]
|
|
800466c: e015 b.n 800469a <HAL_RCC_OscConfig+0x1de>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
800466e: 4b24 ldr r3, [pc, #144] @ (8004700 <HAL_RCC_OscConfig+0x244>)
|
|
8004670: 2200 movs r2, #0
|
|
8004672: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004674: f7fc ffb2 bl 80015dc <HAL_GetTick>
|
|
8004678: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800467a: e008 b.n 800468e <HAL_RCC_OscConfig+0x1d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
800467c: f7fc ffae bl 80015dc <HAL_GetTick>
|
|
8004680: 4602 mov r2, r0
|
|
8004682: 693b ldr r3, [r7, #16]
|
|
8004684: 1ad3 subs r3, r2, r3
|
|
8004686: 2b02 cmp r3, #2
|
|
8004688: d901 bls.n 800468e <HAL_RCC_OscConfig+0x1d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800468a: 2303 movs r3, #3
|
|
800468c: e187 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
800468e: 4b1b ldr r3, [pc, #108] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
8004690: 681b ldr r3, [r3, #0]
|
|
8004692: f003 0302 and.w r3, r3, #2
|
|
8004696: 2b00 cmp r3, #0
|
|
8004698: d1f0 bne.n 800467c <HAL_RCC_OscConfig+0x1c0>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
800469a: 687b ldr r3, [r7, #4]
|
|
800469c: 681b ldr r3, [r3, #0]
|
|
800469e: f003 0308 and.w r3, r3, #8
|
|
80046a2: 2b00 cmp r3, #0
|
|
80046a4: d036 beq.n 8004714 <HAL_RCC_OscConfig+0x258>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
|
|
80046a6: 687b ldr r3, [r7, #4]
|
|
80046a8: 695b ldr r3, [r3, #20]
|
|
80046aa: 2b00 cmp r3, #0
|
|
80046ac: d016 beq.n 80046dc <HAL_RCC_OscConfig+0x220>
|
|
{
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
80046ae: 4b15 ldr r3, [pc, #84] @ (8004704 <HAL_RCC_OscConfig+0x248>)
|
|
80046b0: 2201 movs r2, #1
|
|
80046b2: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80046b4: f7fc ff92 bl 80015dc <HAL_GetTick>
|
|
80046b8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80046ba: e008 b.n 80046ce <HAL_RCC_OscConfig+0x212>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80046bc: f7fc ff8e bl 80015dc <HAL_GetTick>
|
|
80046c0: 4602 mov r2, r0
|
|
80046c2: 693b ldr r3, [r7, #16]
|
|
80046c4: 1ad3 subs r3, r2, r3
|
|
80046c6: 2b02 cmp r3, #2
|
|
80046c8: d901 bls.n 80046ce <HAL_RCC_OscConfig+0x212>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80046ca: 2303 movs r3, #3
|
|
80046cc: e167 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
80046ce: 4b0b ldr r3, [pc, #44] @ (80046fc <HAL_RCC_OscConfig+0x240>)
|
|
80046d0: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
80046d2: f003 0302 and.w r3, r3, #2
|
|
80046d6: 2b00 cmp r3, #0
|
|
80046d8: d0f0 beq.n 80046bc <HAL_RCC_OscConfig+0x200>
|
|
80046da: e01b b.n 8004714 <HAL_RCC_OscConfig+0x258>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
80046dc: 4b09 ldr r3, [pc, #36] @ (8004704 <HAL_RCC_OscConfig+0x248>)
|
|
80046de: 2200 movs r2, #0
|
|
80046e0: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80046e2: f7fc ff7b bl 80015dc <HAL_GetTick>
|
|
80046e6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
80046e8: e00e b.n 8004708 <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
80046ea: f7fc ff77 bl 80015dc <HAL_GetTick>
|
|
80046ee: 4602 mov r2, r0
|
|
80046f0: 693b ldr r3, [r7, #16]
|
|
80046f2: 1ad3 subs r3, r2, r3
|
|
80046f4: 2b02 cmp r3, #2
|
|
80046f6: d907 bls.n 8004708 <HAL_RCC_OscConfig+0x24c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80046f8: 2303 movs r3, #3
|
|
80046fa: e150 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
80046fc: 40023800 .word 0x40023800
|
|
8004700: 42470000 .word 0x42470000
|
|
8004704: 42470e80 .word 0x42470e80
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
8004708: 4b88 ldr r3, [pc, #544] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800470a: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800470c: f003 0302 and.w r3, r3, #2
|
|
8004710: 2b00 cmp r3, #0
|
|
8004712: d1ea bne.n 80046ea <HAL_RCC_OscConfig+0x22e>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8004714: 687b ldr r3, [r7, #4]
|
|
8004716: 681b ldr r3, [r3, #0]
|
|
8004718: f003 0304 and.w r3, r3, #4
|
|
800471c: 2b00 cmp r3, #0
|
|
800471e: f000 8097 beq.w 8004850 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8004722: 2300 movs r3, #0
|
|
8004724: 75fb strb r3, [r7, #23]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8004726: 4b81 ldr r3, [pc, #516] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004728: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800472a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800472e: 2b00 cmp r3, #0
|
|
8004730: d10f bne.n 8004752 <HAL_RCC_OscConfig+0x296>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8004732: 2300 movs r3, #0
|
|
8004734: 60bb str r3, [r7, #8]
|
|
8004736: 4b7d ldr r3, [pc, #500] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004738: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800473a: 4a7c ldr r2, [pc, #496] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800473c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004740: 6413 str r3, [r2, #64] @ 0x40
|
|
8004742: 4b7a ldr r3, [pc, #488] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004744: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004746: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
800474a: 60bb str r3, [r7, #8]
|
|
800474c: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
800474e: 2301 movs r3, #1
|
|
8004750: 75fb strb r3, [r7, #23]
|
|
}
|
|
|
|
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004752: 4b77 ldr r3, [pc, #476] @ (8004930 <HAL_RCC_OscConfig+0x474>)
|
|
8004754: 681b ldr r3, [r3, #0]
|
|
8004756: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800475a: 2b00 cmp r3, #0
|
|
800475c: d118 bne.n 8004790 <HAL_RCC_OscConfig+0x2d4>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
|
800475e: 4b74 ldr r3, [pc, #464] @ (8004930 <HAL_RCC_OscConfig+0x474>)
|
|
8004760: 681b ldr r3, [r3, #0]
|
|
8004762: 4a73 ldr r2, [pc, #460] @ (8004930 <HAL_RCC_OscConfig+0x474>)
|
|
8004764: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8004768: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
800476a: f7fc ff37 bl 80015dc <HAL_GetTick>
|
|
800476e: 6138 str r0, [r7, #16]
|
|
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004770: e008 b.n 8004784 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8004772: f7fc ff33 bl 80015dc <HAL_GetTick>
|
|
8004776: 4602 mov r2, r0
|
|
8004778: 693b ldr r3, [r7, #16]
|
|
800477a: 1ad3 subs r3, r2, r3
|
|
800477c: 2b02 cmp r3, #2
|
|
800477e: d901 bls.n 8004784 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004780: 2303 movs r3, #3
|
|
8004782: e10c b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
|
8004784: 4b6a ldr r3, [pc, #424] @ (8004930 <HAL_RCC_OscConfig+0x474>)
|
|
8004786: 681b ldr r3, [r3, #0]
|
|
8004788: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800478c: 2b00 cmp r3, #0
|
|
800478e: d0f0 beq.n 8004772 <HAL_RCC_OscConfig+0x2b6>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Set the new LSE configuration -----------------------------------------*/
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8004790: 687b ldr r3, [r7, #4]
|
|
8004792: 689b ldr r3, [r3, #8]
|
|
8004794: 2b01 cmp r3, #1
|
|
8004796: d106 bne.n 80047a6 <HAL_RCC_OscConfig+0x2ea>
|
|
8004798: 4b64 ldr r3, [pc, #400] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800479a: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800479c: 4a63 ldr r2, [pc, #396] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800479e: f043 0301 orr.w r3, r3, #1
|
|
80047a2: 6713 str r3, [r2, #112] @ 0x70
|
|
80047a4: e01c b.n 80047e0 <HAL_RCC_OscConfig+0x324>
|
|
80047a6: 687b ldr r3, [r7, #4]
|
|
80047a8: 689b ldr r3, [r3, #8]
|
|
80047aa: 2b05 cmp r3, #5
|
|
80047ac: d10c bne.n 80047c8 <HAL_RCC_OscConfig+0x30c>
|
|
80047ae: 4b5f ldr r3, [pc, #380] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047b0: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80047b2: 4a5e ldr r2, [pc, #376] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047b4: f043 0304 orr.w r3, r3, #4
|
|
80047b8: 6713 str r3, [r2, #112] @ 0x70
|
|
80047ba: 4b5c ldr r3, [pc, #368] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047bc: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80047be: 4a5b ldr r2, [pc, #364] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047c0: f043 0301 orr.w r3, r3, #1
|
|
80047c4: 6713 str r3, [r2, #112] @ 0x70
|
|
80047c6: e00b b.n 80047e0 <HAL_RCC_OscConfig+0x324>
|
|
80047c8: 4b58 ldr r3, [pc, #352] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047ca: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80047cc: 4a57 ldr r2, [pc, #348] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047ce: f023 0301 bic.w r3, r3, #1
|
|
80047d2: 6713 str r3, [r2, #112] @ 0x70
|
|
80047d4: 4b55 ldr r3, [pc, #340] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047d6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80047d8: 4a54 ldr r2, [pc, #336] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80047da: f023 0304 bic.w r3, r3, #4
|
|
80047de: 6713 str r3, [r2, #112] @ 0x70
|
|
/* Check the LSE State */
|
|
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
|
|
80047e0: 687b ldr r3, [r7, #4]
|
|
80047e2: 689b ldr r3, [r3, #8]
|
|
80047e4: 2b00 cmp r3, #0
|
|
80047e6: d015 beq.n 8004814 <HAL_RCC_OscConfig+0x358>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
80047e8: f7fc fef8 bl 80015dc <HAL_GetTick>
|
|
80047ec: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
80047ee: e00a b.n 8004806 <HAL_RCC_OscConfig+0x34a>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80047f0: f7fc fef4 bl 80015dc <HAL_GetTick>
|
|
80047f4: 4602 mov r2, r0
|
|
80047f6: 693b ldr r3, [r7, #16]
|
|
80047f8: 1ad3 subs r3, r2, r3
|
|
80047fa: f241 3288 movw r2, #5000 @ 0x1388
|
|
80047fe: 4293 cmp r3, r2
|
|
8004800: d901 bls.n 8004806 <HAL_RCC_OscConfig+0x34a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004802: 2303 movs r3, #3
|
|
8004804: e0cb b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8004806: 4b49 ldr r3, [pc, #292] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004808: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800480a: f003 0302 and.w r3, r3, #2
|
|
800480e: 2b00 cmp r3, #0
|
|
8004810: d0ee beq.n 80047f0 <HAL_RCC_OscConfig+0x334>
|
|
8004812: e014 b.n 800483e <HAL_RCC_OscConfig+0x382>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004814: f7fc fee2 bl 80015dc <HAL_GetTick>
|
|
8004818: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
800481a: e00a b.n 8004832 <HAL_RCC_OscConfig+0x376>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
800481c: f7fc fede bl 80015dc <HAL_GetTick>
|
|
8004820: 4602 mov r2, r0
|
|
8004822: 693b ldr r3, [r7, #16]
|
|
8004824: 1ad3 subs r3, r2, r3
|
|
8004826: f241 3288 movw r2, #5000 @ 0x1388
|
|
800482a: 4293 cmp r3, r2
|
|
800482c: d901 bls.n 8004832 <HAL_RCC_OscConfig+0x376>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800482e: 2303 movs r3, #3
|
|
8004830: e0b5 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
8004832: 4b3e ldr r3, [pc, #248] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004834: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004836: f003 0302 and.w r3, r3, #2
|
|
800483a: 2b00 cmp r3, #0
|
|
800483c: d1ee bne.n 800481c <HAL_RCC_OscConfig+0x360>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
800483e: 7dfb ldrb r3, [r7, #23]
|
|
8004840: 2b01 cmp r3, #1
|
|
8004842: d105 bne.n 8004850 <HAL_RCC_OscConfig+0x394>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8004844: 4b39 ldr r3, [pc, #228] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004846: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8004848: 4a38 ldr r2, [pc, #224] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800484a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
800484e: 6413 str r3, [r2, #64] @ 0x40
|
|
}
|
|
}
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
8004850: 687b ldr r3, [r7, #4]
|
|
8004852: 699b ldr r3, [r3, #24]
|
|
8004854: 2b00 cmp r3, #0
|
|
8004856: f000 80a1 beq.w 800499c <HAL_RCC_OscConfig+0x4e0>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
800485a: 4b34 ldr r3, [pc, #208] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
800485c: 689b ldr r3, [r3, #8]
|
|
800485e: f003 030c and.w r3, r3, #12
|
|
8004862: 2b08 cmp r3, #8
|
|
8004864: d05c beq.n 8004920 <HAL_RCC_OscConfig+0x464>
|
|
{
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
8004866: 687b ldr r3, [r7, #4]
|
|
8004868: 699b ldr r3, [r3, #24]
|
|
800486a: 2b02 cmp r3, #2
|
|
800486c: d141 bne.n 80048f2 <HAL_RCC_OscConfig+0x436>
|
|
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
|
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
800486e: 4b31 ldr r3, [pc, #196] @ (8004934 <HAL_RCC_OscConfig+0x478>)
|
|
8004870: 2200 movs r2, #0
|
|
8004872: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004874: f7fc feb2 bl 80015dc <HAL_GetTick>
|
|
8004878: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800487a: e008 b.n 800488e <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
800487c: f7fc feae bl 80015dc <HAL_GetTick>
|
|
8004880: 4602 mov r2, r0
|
|
8004882: 693b ldr r3, [r7, #16]
|
|
8004884: 1ad3 subs r3, r2, r3
|
|
8004886: 2b02 cmp r3, #2
|
|
8004888: d901 bls.n 800488e <HAL_RCC_OscConfig+0x3d2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800488a: 2303 movs r3, #3
|
|
800488c: e087 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
800488e: 4b27 ldr r3, [pc, #156] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004890: 681b ldr r3, [r3, #0]
|
|
8004892: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004896: 2b00 cmp r3, #0
|
|
8004898: d1f0 bne.n 800487c <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
|
|
800489a: 687b ldr r3, [r7, #4]
|
|
800489c: 69da ldr r2, [r3, #28]
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 6a1b ldr r3, [r3, #32]
|
|
80048a2: 431a orrs r2, r3
|
|
80048a4: 687b ldr r3, [r7, #4]
|
|
80048a6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80048a8: 019b lsls r3, r3, #6
|
|
80048aa: 431a orrs r2, r3
|
|
80048ac: 687b ldr r3, [r7, #4]
|
|
80048ae: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80048b0: 085b lsrs r3, r3, #1
|
|
80048b2: 3b01 subs r3, #1
|
|
80048b4: 041b lsls r3, r3, #16
|
|
80048b6: 431a orrs r2, r3
|
|
80048b8: 687b ldr r3, [r7, #4]
|
|
80048ba: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80048bc: 061b lsls r3, r3, #24
|
|
80048be: 491b ldr r1, [pc, #108] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80048c0: 4313 orrs r3, r2
|
|
80048c2: 604b str r3, [r1, #4]
|
|
RCC_OscInitStruct->PLL.PLLM | \
|
|
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
|
|
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
|
|
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
80048c4: 4b1b ldr r3, [pc, #108] @ (8004934 <HAL_RCC_OscConfig+0x478>)
|
|
80048c6: 2201 movs r2, #1
|
|
80048c8: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80048ca: f7fc fe87 bl 80015dc <HAL_GetTick>
|
|
80048ce: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80048d0: e008 b.n 80048e4 <HAL_RCC_OscConfig+0x428>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
80048d2: f7fc fe83 bl 80015dc <HAL_GetTick>
|
|
80048d6: 4602 mov r2, r0
|
|
80048d8: 693b ldr r3, [r7, #16]
|
|
80048da: 1ad3 subs r3, r2, r3
|
|
80048dc: 2b02 cmp r3, #2
|
|
80048de: d901 bls.n 80048e4 <HAL_RCC_OscConfig+0x428>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80048e0: 2303 movs r3, #3
|
|
80048e2: e05c b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
80048e4: 4b11 ldr r3, [pc, #68] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
80048e6: 681b ldr r3, [r3, #0]
|
|
80048e8: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80048ec: 2b00 cmp r3, #0
|
|
80048ee: d0f0 beq.n 80048d2 <HAL_RCC_OscConfig+0x416>
|
|
80048f0: e054 b.n 800499c <HAL_RCC_OscConfig+0x4e0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
80048f2: 4b10 ldr r3, [pc, #64] @ (8004934 <HAL_RCC_OscConfig+0x478>)
|
|
80048f4: 2200 movs r2, #0
|
|
80048f6: 601a str r2, [r3, #0]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
80048f8: f7fc fe70 bl 80015dc <HAL_GetTick>
|
|
80048fc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
80048fe: e008 b.n 8004912 <HAL_RCC_OscConfig+0x456>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8004900: f7fc fe6c bl 80015dc <HAL_GetTick>
|
|
8004904: 4602 mov r2, r0
|
|
8004906: 693b ldr r3, [r7, #16]
|
|
8004908: 1ad3 subs r3, r2, r3
|
|
800490a: 2b02 cmp r3, #2
|
|
800490c: d901 bls.n 8004912 <HAL_RCC_OscConfig+0x456>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800490e: 2303 movs r3, #3
|
|
8004910: e045 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
8004912: 4b06 ldr r3, [pc, #24] @ (800492c <HAL_RCC_OscConfig+0x470>)
|
|
8004914: 681b ldr r3, [r3, #0]
|
|
8004916: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
800491a: 2b00 cmp r3, #0
|
|
800491c: d1f0 bne.n 8004900 <HAL_RCC_OscConfig+0x444>
|
|
800491e: e03d b.n 800499c <HAL_RCC_OscConfig+0x4e0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check if there is a request to disable the PLL used as System clock source */
|
|
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
|
8004920: 687b ldr r3, [r7, #4]
|
|
8004922: 699b ldr r3, [r3, #24]
|
|
8004924: 2b01 cmp r3, #1
|
|
8004926: d107 bne.n 8004938 <HAL_RCC_OscConfig+0x47c>
|
|
{
|
|
return HAL_ERROR;
|
|
8004928: 2301 movs r3, #1
|
|
800492a: e038 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
800492c: 40023800 .word 0x40023800
|
|
8004930: 40007000 .word 0x40007000
|
|
8004934: 42470060 .word 0x42470060
|
|
}
|
|
else
|
|
{
|
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
|
pll_config = RCC->PLLCFGR;
|
|
8004938: 4b1b ldr r3, [pc, #108] @ (80049a8 <HAL_RCC_OscConfig+0x4ec>)
|
|
800493a: 685b ldr r3, [r3, #4]
|
|
800493c: 60fb str r3, [r7, #12]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
|
|
#else
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
800493e: 687b ldr r3, [r7, #4]
|
|
8004940: 699b ldr r3, [r3, #24]
|
|
8004942: 2b01 cmp r3, #1
|
|
8004944: d028 beq.n 8004998 <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8004946: 68fb ldr r3, [r7, #12]
|
|
8004948: f403 0280 and.w r2, r3, #4194304 @ 0x400000
|
|
800494c: 687b ldr r3, [r7, #4]
|
|
800494e: 69db ldr r3, [r3, #28]
|
|
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
|
|
8004950: 429a cmp r2, r3
|
|
8004952: d121 bne.n 8004998 <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004954: 68fb ldr r3, [r7, #12]
|
|
8004956: f003 023f and.w r2, r3, #63 @ 0x3f
|
|
800495a: 687b ldr r3, [r7, #4]
|
|
800495c: 6a1b ldr r3, [r3, #32]
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
800495e: 429a cmp r2, r3
|
|
8004960: d11a bne.n 8004998 <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004962: 68fa ldr r2, [r7, #12]
|
|
8004964: f647 73c0 movw r3, #32704 @ 0x7fc0
|
|
8004968: 4013 ands r3, r2
|
|
800496a: 687a ldr r2, [r7, #4]
|
|
800496c: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
800496e: 0192 lsls r2, r2, #6
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
|
|
8004970: 4293 cmp r3, r2
|
|
8004972: d111 bne.n 8004998 <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8004974: 68fb ldr r3, [r7, #12]
|
|
8004976: f403 3240 and.w r2, r3, #196608 @ 0x30000
|
|
800497a: 687b ldr r3, [r7, #4]
|
|
800497c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800497e: 085b lsrs r3, r3, #1
|
|
8004980: 3b01 subs r3, #1
|
|
8004982: 041b lsls r3, r3, #16
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
|
|
8004984: 429a cmp r2, r3
|
|
8004986: d107 bne.n 8004998 <HAL_RCC_OscConfig+0x4dc>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
|
|
8004988: 68fb ldr r3, [r7, #12]
|
|
800498a: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
|
|
800498e: 687b ldr r3, [r7, #4]
|
|
8004990: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8004992: 061b lsls r3, r3, #24
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
|
|
8004994: 429a cmp r2, r3
|
|
8004996: d001 beq.n 800499c <HAL_RCC_OscConfig+0x4e0>
|
|
#endif /* RCC_PLLCFGR_PLLR */
|
|
{
|
|
return HAL_ERROR;
|
|
8004998: 2301 movs r3, #1
|
|
800499a: e000 b.n 800499e <HAL_RCC_OscConfig+0x4e2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
800499c: 2300 movs r3, #0
|
|
}
|
|
800499e: 4618 mov r0, r3
|
|
80049a0: 3718 adds r7, #24
|
|
80049a2: 46bd mov sp, r7
|
|
80049a4: bd80 pop {r7, pc}
|
|
80049a6: bf00 nop
|
|
80049a8: 40023800 .word 0x40023800
|
|
|
|
080049ac <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
80049ac: b580 push {r7, lr}
|
|
80049ae: b084 sub sp, #16
|
|
80049b0: af00 add r7, sp, #0
|
|
80049b2: 6078 str r0, [r7, #4]
|
|
80049b4: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_ClkInitStruct == NULL)
|
|
80049b6: 687b ldr r3, [r7, #4]
|
|
80049b8: 2b00 cmp r3, #0
|
|
80049ba: d101 bne.n 80049c0 <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80049bc: 2301 movs r3, #1
|
|
80049be: e0cc b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
80049c0: 4b68 ldr r3, [pc, #416] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80049c2: 681b ldr r3, [r3, #0]
|
|
80049c4: f003 030f and.w r3, r3, #15
|
|
80049c8: 683a ldr r2, [r7, #0]
|
|
80049ca: 429a cmp r2, r3
|
|
80049cc: d90c bls.n 80049e8 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80049ce: 4b65 ldr r3, [pc, #404] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80049d0: 683a ldr r2, [r7, #0]
|
|
80049d2: b2d2 uxtb r2, r2
|
|
80049d4: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
80049d6: 4b63 ldr r3, [pc, #396] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
80049d8: 681b ldr r3, [r3, #0]
|
|
80049da: f003 030f and.w r3, r3, #15
|
|
80049de: 683a ldr r2, [r7, #0]
|
|
80049e0: 429a cmp r2, r3
|
|
80049e2: d001 beq.n 80049e8 <HAL_RCC_ClockConfig+0x3c>
|
|
{
|
|
return HAL_ERROR;
|
|
80049e4: 2301 movs r3, #1
|
|
80049e6: e0b8 b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
80049e8: 687b ldr r3, [r7, #4]
|
|
80049ea: 681b ldr r3, [r3, #0]
|
|
80049ec: f003 0302 and.w r3, r3, #2
|
|
80049f0: 2b00 cmp r3, #0
|
|
80049f2: d020 beq.n 8004a36 <HAL_RCC_ClockConfig+0x8a>
|
|
{
|
|
/* Set the highest APBx dividers in order to ensure that we do not go through
|
|
a non-spec phase whatever we decrease or increase HCLK. */
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80049f4: 687b ldr r3, [r7, #4]
|
|
80049f6: 681b ldr r3, [r3, #0]
|
|
80049f8: f003 0304 and.w r3, r3, #4
|
|
80049fc: 2b00 cmp r3, #0
|
|
80049fe: d005 beq.n 8004a0c <HAL_RCC_ClockConfig+0x60>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
|
|
8004a00: 4b59 ldr r3, [pc, #356] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a02: 689b ldr r3, [r3, #8]
|
|
8004a04: 4a58 ldr r2, [pc, #352] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a06: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
|
|
8004a0a: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004a0c: 687b ldr r3, [r7, #4]
|
|
8004a0e: 681b ldr r3, [r3, #0]
|
|
8004a10: f003 0308 and.w r3, r3, #8
|
|
8004a14: 2b00 cmp r3, #0
|
|
8004a16: d005 beq.n 8004a24 <HAL_RCC_ClockConfig+0x78>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
|
|
8004a18: 4b53 ldr r3, [pc, #332] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a1a: 689b ldr r3, [r3, #8]
|
|
8004a1c: 4a52 ldr r2, [pc, #328] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a1e: f443 4360 orr.w r3, r3, #57344 @ 0xe000
|
|
8004a22: 6093 str r3, [r2, #8]
|
|
}
|
|
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8004a24: 4b50 ldr r3, [pc, #320] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a26: 689b ldr r3, [r3, #8]
|
|
8004a28: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004a2c: 687b ldr r3, [r7, #4]
|
|
8004a2e: 689b ldr r3, [r3, #8]
|
|
8004a30: 494d ldr r1, [pc, #308] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a32: 4313 orrs r3, r2
|
|
8004a34: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8004a36: 687b ldr r3, [r7, #4]
|
|
8004a38: 681b ldr r3, [r3, #0]
|
|
8004a3a: f003 0301 and.w r3, r3, #1
|
|
8004a3e: 2b00 cmp r3, #0
|
|
8004a40: d044 beq.n 8004acc <HAL_RCC_ClockConfig+0x120>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8004a42: 687b ldr r3, [r7, #4]
|
|
8004a44: 685b ldr r3, [r3, #4]
|
|
8004a46: 2b01 cmp r3, #1
|
|
8004a48: d107 bne.n 8004a5a <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
8004a4a: 4b47 ldr r3, [pc, #284] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a4c: 681b ldr r3, [r3, #0]
|
|
8004a4e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004a52: 2b00 cmp r3, #0
|
|
8004a54: d119 bne.n 8004a8a <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a56: 2301 movs r3, #1
|
|
8004a58: e07f b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8004a5a: 687b ldr r3, [r7, #4]
|
|
8004a5c: 685b ldr r3, [r3, #4]
|
|
8004a5e: 2b02 cmp r3, #2
|
|
8004a60: d003 beq.n 8004a6a <HAL_RCC_ClockConfig+0xbe>
|
|
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
|
|
8004a62: 687b ldr r3, [r7, #4]
|
|
8004a64: 685b ldr r3, [r3, #4]
|
|
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
|
|
8004a66: 2b03 cmp r3, #3
|
|
8004a68: d107 bne.n 8004a7a <HAL_RCC_ClockConfig+0xce>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
8004a6a: 4b3f ldr r3, [pc, #252] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a6c: 681b ldr r3, [r3, #0]
|
|
8004a6e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004a72: 2b00 cmp r3, #0
|
|
8004a74: d109 bne.n 8004a8a <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a76: 2301 movs r3, #1
|
|
8004a78: e06f b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
8004a7a: 4b3b ldr r3, [pc, #236] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a7c: 681b ldr r3, [r3, #0]
|
|
8004a7e: f003 0302 and.w r3, r3, #2
|
|
8004a82: 2b00 cmp r3, #0
|
|
8004a84: d101 bne.n 8004a8a <HAL_RCC_ClockConfig+0xde>
|
|
{
|
|
return HAL_ERROR;
|
|
8004a86: 2301 movs r3, #1
|
|
8004a88: e067 b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
8004a8a: 4b37 ldr r3, [pc, #220] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a8c: 689b ldr r3, [r3, #8]
|
|
8004a8e: f023 0203 bic.w r2, r3, #3
|
|
8004a92: 687b ldr r3, [r7, #4]
|
|
8004a94: 685b ldr r3, [r3, #4]
|
|
8004a96: 4934 ldr r1, [pc, #208] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004a98: 4313 orrs r3, r2
|
|
8004a9a: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
8004a9c: f7fc fd9e bl 80015dc <HAL_GetTick>
|
|
8004aa0: 60f8 str r0, [r7, #12]
|
|
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8004aa2: e00a b.n 8004aba <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8004aa4: f7fc fd9a bl 80015dc <HAL_GetTick>
|
|
8004aa8: 4602 mov r2, r0
|
|
8004aaa: 68fb ldr r3, [r7, #12]
|
|
8004aac: 1ad3 subs r3, r2, r3
|
|
8004aae: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004ab2: 4293 cmp r3, r2
|
|
8004ab4: d901 bls.n 8004aba <HAL_RCC_ClockConfig+0x10e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8004ab6: 2303 movs r3, #3
|
|
8004ab8: e04f b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8004aba: 4b2b ldr r3, [pc, #172] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004abc: 689b ldr r3, [r3, #8]
|
|
8004abe: f003 020c and.w r2, r3, #12
|
|
8004ac2: 687b ldr r3, [r7, #4]
|
|
8004ac4: 685b ldr r3, [r3, #4]
|
|
8004ac6: 009b lsls r3, r3, #2
|
|
8004ac8: 429a cmp r2, r3
|
|
8004aca: d1eb bne.n 8004aa4 <HAL_RCC_ClockConfig+0xf8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
8004acc: 4b25 ldr r3, [pc, #148] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8004ace: 681b ldr r3, [r3, #0]
|
|
8004ad0: f003 030f and.w r3, r3, #15
|
|
8004ad4: 683a ldr r2, [r7, #0]
|
|
8004ad6: 429a cmp r2, r3
|
|
8004ad8: d20c bcs.n 8004af4 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8004ada: 4b22 ldr r3, [pc, #136] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8004adc: 683a ldr r2, [r7, #0]
|
|
8004ade: b2d2 uxtb r2, r2
|
|
8004ae0: 701a strb r2, [r3, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if (__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
8004ae2: 4b20 ldr r3, [pc, #128] @ (8004b64 <HAL_RCC_ClockConfig+0x1b8>)
|
|
8004ae4: 681b ldr r3, [r3, #0]
|
|
8004ae6: f003 030f and.w r3, r3, #15
|
|
8004aea: 683a ldr r2, [r7, #0]
|
|
8004aec: 429a cmp r2, r3
|
|
8004aee: d001 beq.n 8004af4 <HAL_RCC_ClockConfig+0x148>
|
|
{
|
|
return HAL_ERROR;
|
|
8004af0: 2301 movs r3, #1
|
|
8004af2: e032 b.n 8004b5a <HAL_RCC_ClockConfig+0x1ae>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
8004af4: 687b ldr r3, [r7, #4]
|
|
8004af6: 681b ldr r3, [r3, #0]
|
|
8004af8: f003 0304 and.w r3, r3, #4
|
|
8004afc: 2b00 cmp r3, #0
|
|
8004afe: d008 beq.n 8004b12 <HAL_RCC_ClockConfig+0x166>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8004b00: 4b19 ldr r3, [pc, #100] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004b02: 689b ldr r3, [r3, #8]
|
|
8004b04: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
|
|
8004b08: 687b ldr r3, [r7, #4]
|
|
8004b0a: 68db ldr r3, [r3, #12]
|
|
8004b0c: 4916 ldr r1, [pc, #88] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004b0e: 4313 orrs r3, r2
|
|
8004b10: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
8004b12: 687b ldr r3, [r7, #4]
|
|
8004b14: 681b ldr r3, [r3, #0]
|
|
8004b16: f003 0308 and.w r3, r3, #8
|
|
8004b1a: 2b00 cmp r3, #0
|
|
8004b1c: d009 beq.n 8004b32 <HAL_RCC_ClockConfig+0x186>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
8004b1e: 4b12 ldr r3, [pc, #72] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004b20: 689b ldr r3, [r3, #8]
|
|
8004b22: f423 4260 bic.w r2, r3, #57344 @ 0xe000
|
|
8004b26: 687b ldr r3, [r7, #4]
|
|
8004b28: 691b ldr r3, [r3, #16]
|
|
8004b2a: 00db lsls r3, r3, #3
|
|
8004b2c: 490e ldr r1, [pc, #56] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004b2e: 4313 orrs r3, r2
|
|
8004b30: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
|
|
8004b32: f000 f821 bl 8004b78 <HAL_RCC_GetSysClockFreq>
|
|
8004b36: 4602 mov r2, r0
|
|
8004b38: 4b0b ldr r3, [pc, #44] @ (8004b68 <HAL_RCC_ClockConfig+0x1bc>)
|
|
8004b3a: 689b ldr r3, [r3, #8]
|
|
8004b3c: 091b lsrs r3, r3, #4
|
|
8004b3e: f003 030f and.w r3, r3, #15
|
|
8004b42: 490a ldr r1, [pc, #40] @ (8004b6c <HAL_RCC_ClockConfig+0x1c0>)
|
|
8004b44: 5ccb ldrb r3, [r1, r3]
|
|
8004b46: fa22 f303 lsr.w r3, r2, r3
|
|
8004b4a: 4a09 ldr r2, [pc, #36] @ (8004b70 <HAL_RCC_ClockConfig+0x1c4>)
|
|
8004b4c: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings */
|
|
HAL_InitTick(uwTickPrio);
|
|
8004b4e: 4b09 ldr r3, [pc, #36] @ (8004b74 <HAL_RCC_ClockConfig+0x1c8>)
|
|
8004b50: 681b ldr r3, [r3, #0]
|
|
8004b52: 4618 mov r0, r3
|
|
8004b54: f7fc fc10 bl 8001378 <HAL_InitTick>
|
|
|
|
return HAL_OK;
|
|
8004b58: 2300 movs r3, #0
|
|
}
|
|
8004b5a: 4618 mov r0, r3
|
|
8004b5c: 3710 adds r7, #16
|
|
8004b5e: 46bd mov sp, r7
|
|
8004b60: bd80 pop {r7, pc}
|
|
8004b62: bf00 nop
|
|
8004b64: 40023c00 .word 0x40023c00
|
|
8004b68: 40023800 .word 0x40023800
|
|
8004b6c: 08007eac .word 0x08007eac
|
|
8004b70: 20000000 .word 0x20000000
|
|
8004b74: 20000004 .word 0x20000004
|
|
|
|
08004b78 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8004b78: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8004b7c: b094 sub sp, #80 @ 0x50
|
|
8004b7e: af00 add r7, sp, #0
|
|
uint32_t pllm = 0U;
|
|
8004b80: 2300 movs r3, #0
|
|
8004b82: 647b str r3, [r7, #68] @ 0x44
|
|
uint32_t pllvco = 0U;
|
|
8004b84: 2300 movs r3, #0
|
|
8004b86: 64fb str r3, [r7, #76] @ 0x4c
|
|
uint32_t pllp = 0U;
|
|
8004b88: 2300 movs r3, #0
|
|
8004b8a: 643b str r3, [r7, #64] @ 0x40
|
|
uint32_t sysclockfreq = 0U;
|
|
8004b8c: 2300 movs r3, #0
|
|
8004b8e: 64bb str r3, [r7, #72] @ 0x48
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
8004b90: 4b79 ldr r3, [pc, #484] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004b92: 689b ldr r3, [r3, #8]
|
|
8004b94: f003 030c and.w r3, r3, #12
|
|
8004b98: 2b08 cmp r3, #8
|
|
8004b9a: d00d beq.n 8004bb8 <HAL_RCC_GetSysClockFreq+0x40>
|
|
8004b9c: 2b08 cmp r3, #8
|
|
8004b9e: f200 80e1 bhi.w 8004d64 <HAL_RCC_GetSysClockFreq+0x1ec>
|
|
8004ba2: 2b00 cmp r3, #0
|
|
8004ba4: d002 beq.n 8004bac <HAL_RCC_GetSysClockFreq+0x34>
|
|
8004ba6: 2b04 cmp r3, #4
|
|
8004ba8: d003 beq.n 8004bb2 <HAL_RCC_GetSysClockFreq+0x3a>
|
|
8004baa: e0db b.n 8004d64 <HAL_RCC_GetSysClockFreq+0x1ec>
|
|
{
|
|
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004bac: 4b73 ldr r3, [pc, #460] @ (8004d7c <HAL_RCC_GetSysClockFreq+0x204>)
|
|
8004bae: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8004bb0: e0db b.n 8004d6a <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
8004bb2: 4b73 ldr r3, [pc, #460] @ (8004d80 <HAL_RCC_GetSysClockFreq+0x208>)
|
|
8004bb4: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8004bb6: e0d8 b.n 8004d6a <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
|
|
{
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
SYSCLK = PLL_VCO / PLLP */
|
|
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
8004bb8: 4b6f ldr r3, [pc, #444] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004bba: 685b ldr r3, [r3, #4]
|
|
8004bbc: f003 033f and.w r3, r3, #63 @ 0x3f
|
|
8004bc0: 647b str r3, [r7, #68] @ 0x44
|
|
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
8004bc2: 4b6d ldr r3, [pc, #436] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004bc4: 685b ldr r3, [r3, #4]
|
|
8004bc6: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8004bca: 2b00 cmp r3, #0
|
|
8004bcc: d063 beq.n 8004c96 <HAL_RCC_GetSysClockFreq+0x11e>
|
|
{
|
|
/* HSE used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004bce: 4b6a ldr r3, [pc, #424] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004bd0: 685b ldr r3, [r3, #4]
|
|
8004bd2: 099b lsrs r3, r3, #6
|
|
8004bd4: 2200 movs r2, #0
|
|
8004bd6: 63bb str r3, [r7, #56] @ 0x38
|
|
8004bd8: 63fa str r2, [r7, #60] @ 0x3c
|
|
8004bda: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8004bdc: f3c3 0308 ubfx r3, r3, #0, #9
|
|
8004be0: 633b str r3, [r7, #48] @ 0x30
|
|
8004be2: 2300 movs r3, #0
|
|
8004be4: 637b str r3, [r7, #52] @ 0x34
|
|
8004be6: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
|
|
8004bea: 4622 mov r2, r4
|
|
8004bec: 462b mov r3, r5
|
|
8004bee: f04f 0000 mov.w r0, #0
|
|
8004bf2: f04f 0100 mov.w r1, #0
|
|
8004bf6: 0159 lsls r1, r3, #5
|
|
8004bf8: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004bfc: 0150 lsls r0, r2, #5
|
|
8004bfe: 4602 mov r2, r0
|
|
8004c00: 460b mov r3, r1
|
|
8004c02: 4621 mov r1, r4
|
|
8004c04: 1a51 subs r1, r2, r1
|
|
8004c06: 6139 str r1, [r7, #16]
|
|
8004c08: 4629 mov r1, r5
|
|
8004c0a: eb63 0301 sbc.w r3, r3, r1
|
|
8004c0e: 617b str r3, [r7, #20]
|
|
8004c10: f04f 0200 mov.w r2, #0
|
|
8004c14: f04f 0300 mov.w r3, #0
|
|
8004c18: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
8004c1c: 4659 mov r1, fp
|
|
8004c1e: 018b lsls r3, r1, #6
|
|
8004c20: 4651 mov r1, sl
|
|
8004c22: ea43 6391 orr.w r3, r3, r1, lsr #26
|
|
8004c26: 4651 mov r1, sl
|
|
8004c28: 018a lsls r2, r1, #6
|
|
8004c2a: 4651 mov r1, sl
|
|
8004c2c: ebb2 0801 subs.w r8, r2, r1
|
|
8004c30: 4659 mov r1, fp
|
|
8004c32: eb63 0901 sbc.w r9, r3, r1
|
|
8004c36: f04f 0200 mov.w r2, #0
|
|
8004c3a: f04f 0300 mov.w r3, #0
|
|
8004c3e: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8004c42: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8004c46: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8004c4a: 4690 mov r8, r2
|
|
8004c4c: 4699 mov r9, r3
|
|
8004c4e: 4623 mov r3, r4
|
|
8004c50: eb18 0303 adds.w r3, r8, r3
|
|
8004c54: 60bb str r3, [r7, #8]
|
|
8004c56: 462b mov r3, r5
|
|
8004c58: eb49 0303 adc.w r3, r9, r3
|
|
8004c5c: 60fb str r3, [r7, #12]
|
|
8004c5e: f04f 0200 mov.w r2, #0
|
|
8004c62: f04f 0300 mov.w r3, #0
|
|
8004c66: e9d7 4502 ldrd r4, r5, [r7, #8]
|
|
8004c6a: 4629 mov r1, r5
|
|
8004c6c: 024b lsls r3, r1, #9
|
|
8004c6e: 4621 mov r1, r4
|
|
8004c70: ea43 53d1 orr.w r3, r3, r1, lsr #23
|
|
8004c74: 4621 mov r1, r4
|
|
8004c76: 024a lsls r2, r1, #9
|
|
8004c78: 4610 mov r0, r2
|
|
8004c7a: 4619 mov r1, r3
|
|
8004c7c: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8004c7e: 2200 movs r2, #0
|
|
8004c80: 62bb str r3, [r7, #40] @ 0x28
|
|
8004c82: 62fa str r2, [r7, #44] @ 0x2c
|
|
8004c84: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
8004c88: f7fb fab2 bl 80001f0 <__aeabi_uldivmod>
|
|
8004c8c: 4602 mov r2, r0
|
|
8004c8e: 460b mov r3, r1
|
|
8004c90: 4613 mov r3, r2
|
|
8004c92: 64fb str r3, [r7, #76] @ 0x4c
|
|
8004c94: e058 b.n 8004d48 <HAL_RCC_GetSysClockFreq+0x1d0>
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source */
|
|
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
|
|
8004c96: 4b38 ldr r3, [pc, #224] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004c98: 685b ldr r3, [r3, #4]
|
|
8004c9a: 099b lsrs r3, r3, #6
|
|
8004c9c: 2200 movs r2, #0
|
|
8004c9e: 4618 mov r0, r3
|
|
8004ca0: 4611 mov r1, r2
|
|
8004ca2: f3c0 0308 ubfx r3, r0, #0, #9
|
|
8004ca6: 623b str r3, [r7, #32]
|
|
8004ca8: 2300 movs r3, #0
|
|
8004caa: 627b str r3, [r7, #36] @ 0x24
|
|
8004cac: e9d7 8908 ldrd r8, r9, [r7, #32]
|
|
8004cb0: 4642 mov r2, r8
|
|
8004cb2: 464b mov r3, r9
|
|
8004cb4: f04f 0000 mov.w r0, #0
|
|
8004cb8: f04f 0100 mov.w r1, #0
|
|
8004cbc: 0159 lsls r1, r3, #5
|
|
8004cbe: ea41 61d2 orr.w r1, r1, r2, lsr #27
|
|
8004cc2: 0150 lsls r0, r2, #5
|
|
8004cc4: 4602 mov r2, r0
|
|
8004cc6: 460b mov r3, r1
|
|
8004cc8: 4641 mov r1, r8
|
|
8004cca: ebb2 0a01 subs.w sl, r2, r1
|
|
8004cce: 4649 mov r1, r9
|
|
8004cd0: eb63 0b01 sbc.w fp, r3, r1
|
|
8004cd4: f04f 0200 mov.w r2, #0
|
|
8004cd8: f04f 0300 mov.w r3, #0
|
|
8004cdc: ea4f 138b mov.w r3, fp, lsl #6
|
|
8004ce0: ea43 639a orr.w r3, r3, sl, lsr #26
|
|
8004ce4: ea4f 128a mov.w r2, sl, lsl #6
|
|
8004ce8: ebb2 040a subs.w r4, r2, sl
|
|
8004cec: eb63 050b sbc.w r5, r3, fp
|
|
8004cf0: f04f 0200 mov.w r2, #0
|
|
8004cf4: f04f 0300 mov.w r3, #0
|
|
8004cf8: 00eb lsls r3, r5, #3
|
|
8004cfa: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8004cfe: 00e2 lsls r2, r4, #3
|
|
8004d00: 4614 mov r4, r2
|
|
8004d02: 461d mov r5, r3
|
|
8004d04: 4643 mov r3, r8
|
|
8004d06: 18e3 adds r3, r4, r3
|
|
8004d08: 603b str r3, [r7, #0]
|
|
8004d0a: 464b mov r3, r9
|
|
8004d0c: eb45 0303 adc.w r3, r5, r3
|
|
8004d10: 607b str r3, [r7, #4]
|
|
8004d12: f04f 0200 mov.w r2, #0
|
|
8004d16: f04f 0300 mov.w r3, #0
|
|
8004d1a: e9d7 4500 ldrd r4, r5, [r7]
|
|
8004d1e: 4629 mov r1, r5
|
|
8004d20: 028b lsls r3, r1, #10
|
|
8004d22: 4621 mov r1, r4
|
|
8004d24: ea43 5391 orr.w r3, r3, r1, lsr #22
|
|
8004d28: 4621 mov r1, r4
|
|
8004d2a: 028a lsls r2, r1, #10
|
|
8004d2c: 4610 mov r0, r2
|
|
8004d2e: 4619 mov r1, r3
|
|
8004d30: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8004d32: 2200 movs r2, #0
|
|
8004d34: 61bb str r3, [r7, #24]
|
|
8004d36: 61fa str r2, [r7, #28]
|
|
8004d38: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8004d3c: f7fb fa58 bl 80001f0 <__aeabi_uldivmod>
|
|
8004d40: 4602 mov r2, r0
|
|
8004d42: 460b mov r3, r1
|
|
8004d44: 4613 mov r3, r2
|
|
8004d46: 64fb str r3, [r7, #76] @ 0x4c
|
|
}
|
|
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
|
|
8004d48: 4b0b ldr r3, [pc, #44] @ (8004d78 <HAL_RCC_GetSysClockFreq+0x200>)
|
|
8004d4a: 685b ldr r3, [r3, #4]
|
|
8004d4c: 0c1b lsrs r3, r3, #16
|
|
8004d4e: f003 0303 and.w r3, r3, #3
|
|
8004d52: 3301 adds r3, #1
|
|
8004d54: 005b lsls r3, r3, #1
|
|
8004d56: 643b str r3, [r7, #64] @ 0x40
|
|
|
|
sysclockfreq = pllvco / pllp;
|
|
8004d58: 6cfa ldr r2, [r7, #76] @ 0x4c
|
|
8004d5a: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8004d5c: fbb2 f3f3 udiv r3, r2, r3
|
|
8004d60: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8004d62: e002 b.n 8004d6a <HAL_RCC_GetSysClockFreq+0x1f2>
|
|
}
|
|
default:
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
8004d64: 4b05 ldr r3, [pc, #20] @ (8004d7c <HAL_RCC_GetSysClockFreq+0x204>)
|
|
8004d66: 64bb str r3, [r7, #72] @ 0x48
|
|
break;
|
|
8004d68: bf00 nop
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
8004d6a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
}
|
|
8004d6c: 4618 mov r0, r3
|
|
8004d6e: 3750 adds r7, #80 @ 0x50
|
|
8004d70: 46bd mov sp, r7
|
|
8004d72: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8004d76: bf00 nop
|
|
8004d78: 40023800 .word 0x40023800
|
|
8004d7c: 00f42400 .word 0x00f42400
|
|
8004d80: 007a1200 .word 0x007a1200
|
|
|
|
08004d84 <HAL_RCC_GetHCLKFreq>:
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8004d84: b480 push {r7}
|
|
8004d86: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8004d88: 4b03 ldr r3, [pc, #12] @ (8004d98 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8004d8a: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004d8c: 4618 mov r0, r3
|
|
8004d8e: 46bd mov sp, r7
|
|
8004d90: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004d94: 4770 bx lr
|
|
8004d96: bf00 nop
|
|
8004d98: 20000000 .word 0x20000000
|
|
|
|
08004d9c <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8004d9c: b580 push {r7, lr}
|
|
8004d9e: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
8004da0: f7ff fff0 bl 8004d84 <HAL_RCC_GetHCLKFreq>
|
|
8004da4: 4602 mov r2, r0
|
|
8004da6: 4b05 ldr r3, [pc, #20] @ (8004dbc <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
8004da8: 689b ldr r3, [r3, #8]
|
|
8004daa: 0a9b lsrs r3, r3, #10
|
|
8004dac: f003 0307 and.w r3, r3, #7
|
|
8004db0: 4903 ldr r1, [pc, #12] @ (8004dc0 <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8004db2: 5ccb ldrb r3, [r1, r3]
|
|
8004db4: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8004db8: 4618 mov r0, r3
|
|
8004dba: bd80 pop {r7, pc}
|
|
8004dbc: 40023800 .word 0x40023800
|
|
8004dc0: 08007ebc .word 0x08007ebc
|
|
|
|
08004dc4 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8004dc4: b580 push {r7, lr}
|
|
8004dc6: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
8004dc8: f7ff ffdc bl 8004d84 <HAL_RCC_GetHCLKFreq>
|
|
8004dcc: 4602 mov r2, r0
|
|
8004dce: 4b05 ldr r3, [pc, #20] @ (8004de4 <HAL_RCC_GetPCLK2Freq+0x20>)
|
|
8004dd0: 689b ldr r3, [r3, #8]
|
|
8004dd2: 0b5b lsrs r3, r3, #13
|
|
8004dd4: f003 0307 and.w r3, r3, #7
|
|
8004dd8: 4903 ldr r1, [pc, #12] @ (8004de8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8004dda: 5ccb ldrb r3, [r1, r3]
|
|
8004ddc: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8004de0: 4618 mov r0, r3
|
|
8004de2: bd80 pop {r7, pc}
|
|
8004de4: 40023800 .word 0x40023800
|
|
8004de8: 08007ebc .word 0x08007ebc
|
|
|
|
08004dec <HAL_RCC_GetClockConfig>:
|
|
* will be configured.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
8004dec: b480 push {r7}
|
|
8004dee: b083 sub sp, #12
|
|
8004df0: af00 add r7, sp, #0
|
|
8004df2: 6078 str r0, [r7, #4]
|
|
8004df4: 6039 str r1, [r7, #0]
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
8004df6: 687b ldr r3, [r7, #4]
|
|
8004df8: 220f movs r2, #15
|
|
8004dfa: 601a str r2, [r3, #0]
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
8004dfc: 4b12 ldr r3, [pc, #72] @ (8004e48 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8004dfe: 689b ldr r3, [r3, #8]
|
|
8004e00: f003 0203 and.w r2, r3, #3
|
|
8004e04: 687b ldr r3, [r7, #4]
|
|
8004e06: 605a str r2, [r3, #4]
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
8004e08: 4b0f ldr r3, [pc, #60] @ (8004e48 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8004e0a: 689b ldr r3, [r3, #8]
|
|
8004e0c: f003 02f0 and.w r2, r3, #240 @ 0xf0
|
|
8004e10: 687b ldr r3, [r7, #4]
|
|
8004e12: 609a str r2, [r3, #8]
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
8004e14: 4b0c ldr r3, [pc, #48] @ (8004e48 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8004e16: 689b ldr r3, [r3, #8]
|
|
8004e18: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
|
|
8004e1c: 687b ldr r3, [r7, #4]
|
|
8004e1e: 60da str r2, [r3, #12]
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
|
|
8004e20: 4b09 ldr r3, [pc, #36] @ (8004e48 <HAL_RCC_GetClockConfig+0x5c>)
|
|
8004e22: 689b ldr r3, [r3, #8]
|
|
8004e24: 08db lsrs r3, r3, #3
|
|
8004e26: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
|
|
8004e2a: 687b ldr r3, [r7, #4]
|
|
8004e2c: 611a str r2, [r3, #16]
|
|
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
8004e2e: 4b07 ldr r3, [pc, #28] @ (8004e4c <HAL_RCC_GetClockConfig+0x60>)
|
|
8004e30: 681b ldr r3, [r3, #0]
|
|
8004e32: f003 020f and.w r2, r3, #15
|
|
8004e36: 683b ldr r3, [r7, #0]
|
|
8004e38: 601a str r2, [r3, #0]
|
|
}
|
|
8004e3a: bf00 nop
|
|
8004e3c: 370c adds r7, #12
|
|
8004e3e: 46bd mov sp, r7
|
|
8004e40: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004e44: 4770 bx lr
|
|
8004e46: bf00 nop
|
|
8004e48: 40023800 .word 0x40023800
|
|
8004e4c: 40023c00 .word 0x40023c00
|
|
|
|
08004e50 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the backup registers) and RCC_BDCR register are set to their reset values.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8004e50: b580 push {r7, lr}
|
|
8004e52: b086 sub sp, #24
|
|
8004e54: af00 add r7, sp, #0
|
|
8004e56: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = 0U;
|
|
8004e58: 2300 movs r3, #0
|
|
8004e5a: 617b str r3, [r7, #20]
|
|
uint32_t tmpreg1 = 0U;
|
|
8004e5c: 2300 movs r3, #0
|
|
8004e5e: 613b str r3, [r7, #16]
|
|
|
|
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
|
|
/*----------------------- Common configuration SAI/I2S ---------------------*/
|
|
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
|
|
factor is common parameters for both peripherals */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
|
8004e60: 687b ldr r3, [r7, #4]
|
|
8004e62: 681b ldr r3, [r3, #0]
|
|
8004e64: f003 0301 and.w r3, r3, #1
|
|
8004e68: 2b00 cmp r3, #0
|
|
8004e6a: d10b bne.n 8004e84 <HAL_RCCEx_PeriphCLKConfig+0x34>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
|
|
8004e6c: 687b ldr r3, [r7, #4]
|
|
8004e6e: 681b ldr r3, [r3, #0]
|
|
8004e70: f003 0302 and.w r3, r3, #2
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
|
|
8004e74: 2b00 cmp r3, #0
|
|
8004e76: d105 bne.n 8004e84 <HAL_RCCEx_PeriphCLKConfig+0x34>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
|
|
8004e78: 687b ldr r3, [r7, #4]
|
|
8004e7a: 681b ldr r3, [r3, #0]
|
|
8004e7c: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
|
|
8004e80: 2b00 cmp r3, #0
|
|
8004e82: d075 beq.n 8004f70 <HAL_RCCEx_PeriphCLKConfig+0x120>
|
|
{
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
|
|
|
|
/* Disable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
8004e84: 4b91 ldr r3, [pc, #580] @ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|
8004e86: 2200 movs r2, #0
|
|
8004e88: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004e8a: f7fc fba7 bl 80015dc <HAL_GetTick>
|
|
8004e8e: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLI2S is disabled */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8004e90: e008 b.n 8004ea4 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8004e92: f7fc fba3 bl 80015dc <HAL_GetTick>
|
|
8004e96: 4602 mov r2, r0
|
|
8004e98: 697b ldr r3, [r7, #20]
|
|
8004e9a: 1ad3 subs r3, r2, r3
|
|
8004e9c: 2b02 cmp r3, #2
|
|
8004e9e: d901 bls.n 8004ea4 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004ea0: 2303 movs r3, #3
|
|
8004ea2: e189 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
8004ea4: 4b8a ldr r3, [pc, #552] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004ea6: 681b ldr r3, [r3, #0]
|
|
8004ea8: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004eac: 2b00 cmp r3, #0
|
|
8004eae: d1f0 bne.n 8004e92 <HAL_RCCEx_PeriphCLKConfig+0x42>
|
|
}
|
|
|
|
/*---------------------------- I2S configuration -------------------------*/
|
|
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
|
|
only for I2S configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
|
|
8004eb0: 687b ldr r3, [r7, #4]
|
|
8004eb2: 681b ldr r3, [r3, #0]
|
|
8004eb4: f003 0301 and.w r3, r3, #1
|
|
8004eb8: 2b00 cmp r3, #0
|
|
8004eba: d009 beq.n 8004ed0 <HAL_RCCEx_PeriphCLKConfig+0x80>
|
|
/* check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
|
|
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
|
|
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
|
|
8004ebc: 687b ldr r3, [r7, #4]
|
|
8004ebe: 685b ldr r3, [r3, #4]
|
|
8004ec0: 019a lsls r2, r3, #6
|
|
8004ec2: 687b ldr r3, [r7, #4]
|
|
8004ec4: 689b ldr r3, [r3, #8]
|
|
8004ec6: 071b lsls r3, r3, #28
|
|
8004ec8: 4981 ldr r1, [pc, #516] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004eca: 4313 orrs r3, r2
|
|
8004ecc: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
}
|
|
|
|
/*---------------------------- SAI configuration -------------------------*/
|
|
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
|
|
be added only for SAI configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
|
|
8004ed0: 687b ldr r3, [r7, #4]
|
|
8004ed2: 681b ldr r3, [r3, #0]
|
|
8004ed4: f003 0302 and.w r3, r3, #2
|
|
8004ed8: 2b00 cmp r3, #0
|
|
8004eda: d01f beq.n 8004f1c <HAL_RCCEx_PeriphCLKConfig+0xcc>
|
|
/* Check the PLLI2S division factors */
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
|
|
|
|
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
|
|
8004edc: 4b7c ldr r3, [pc, #496] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004ede: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004ee2: 0f1b lsrs r3, r3, #28
|
|
8004ee4: f003 0307 and.w r3, r3, #7
|
|
8004ee8: 613b str r3, [r7, #16]
|
|
/* Configure the PLLI2S division factors */
|
|
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
|
|
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
|
|
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
|
|
8004eea: 687b ldr r3, [r7, #4]
|
|
8004eec: 685b ldr r3, [r3, #4]
|
|
8004eee: 019a lsls r2, r3, #6
|
|
8004ef0: 687b ldr r3, [r7, #4]
|
|
8004ef2: 68db ldr r3, [r3, #12]
|
|
8004ef4: 061b lsls r3, r3, #24
|
|
8004ef6: 431a orrs r2, r3
|
|
8004ef8: 693b ldr r3, [r7, #16]
|
|
8004efa: 071b lsls r3, r3, #28
|
|
8004efc: 4974 ldr r1, [pc, #464] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004efe: 4313 orrs r3, r2
|
|
8004f00: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
|
|
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
|
|
8004f04: 4b72 ldr r3, [pc, #456] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004f06: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004f0a: f023 021f bic.w r2, r3, #31
|
|
8004f0e: 687b ldr r3, [r7, #4]
|
|
8004f10: 69db ldr r3, [r3, #28]
|
|
8004f12: 3b01 subs r3, #1
|
|
8004f14: 496e ldr r1, [pc, #440] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004f16: 4313 orrs r3, r2
|
|
8004f18: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*----------------- In Case of PLLI2S is just selected -----------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
|
|
8004f1c: 687b ldr r3, [r7, #4]
|
|
8004f1e: 681b ldr r3, [r3, #0]
|
|
8004f20: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004f24: 2b00 cmp r3, #0
|
|
8004f26: d00d beq.n 8004f44 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
/* Check for Parameters */
|
|
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
|
|
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
|
|
|
|
/* Configure the PLLI2S multiplication and division factors */
|
|
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
|
|
8004f28: 687b ldr r3, [r7, #4]
|
|
8004f2a: 685b ldr r3, [r3, #4]
|
|
8004f2c: 019a lsls r2, r3, #6
|
|
8004f2e: 687b ldr r3, [r7, #4]
|
|
8004f30: 68db ldr r3, [r3, #12]
|
|
8004f32: 061b lsls r3, r3, #24
|
|
8004f34: 431a orrs r2, r3
|
|
8004f36: 687b ldr r3, [r7, #4]
|
|
8004f38: 689b ldr r3, [r3, #8]
|
|
8004f3a: 071b lsls r3, r3, #28
|
|
8004f3c: 4964 ldr r1, [pc, #400] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004f3e: 4313 orrs r3, r2
|
|
8004f40: f8c1 3084 str.w r3, [r1, #132] @ 0x84
|
|
PeriphClkInit->PLLI2S.PLLI2SR);
|
|
}
|
|
|
|
/* Enable the PLLI2S */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
8004f44: 4b61 ldr r3, [pc, #388] @ (80050cc <HAL_RCCEx_PeriphCLKConfig+0x27c>)
|
|
8004f46: 2201 movs r2, #1
|
|
8004f48: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004f4a: f7fc fb47 bl 80015dc <HAL_GetTick>
|
|
8004f4e: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLI2S is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8004f50: e008 b.n 8004f64 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
|
|
8004f52: f7fc fb43 bl 80015dc <HAL_GetTick>
|
|
8004f56: 4602 mov r2, r0
|
|
8004f58: 697b ldr r3, [r7, #20]
|
|
8004f5a: 1ad3 subs r3, r2, r3
|
|
8004f5c: 2b02 cmp r3, #2
|
|
8004f5e: d901 bls.n 8004f64 <HAL_RCCEx_PeriphCLKConfig+0x114>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004f60: 2303 movs r3, #3
|
|
8004f62: e129 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
8004f64: 4b5a ldr r3, [pc, #360] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004f66: 681b ldr r3, [r3, #0]
|
|
8004f68: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004f6c: 2b00 cmp r3, #0
|
|
8004f6e: d0f0 beq.n 8004f52 <HAL_RCCEx_PeriphCLKConfig+0x102>
|
|
|
|
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
|
|
/*----------------------- Common configuration SAI/LTDC --------------------*/
|
|
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
|
|
factor is common parameters for both peripherals */
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
|
8004f70: 687b ldr r3, [r7, #4]
|
|
8004f72: 681b ldr r3, [r3, #0]
|
|
8004f74: f003 0304 and.w r3, r3, #4
|
|
8004f78: 2b00 cmp r3, #0
|
|
8004f7a: d105 bne.n 8004f88 <HAL_RCCEx_PeriphCLKConfig+0x138>
|
|
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
|
|
8004f7c: 687b ldr r3, [r7, #4]
|
|
8004f7e: 681b ldr r3, [r3, #0]
|
|
8004f80: f003 0308 and.w r3, r3, #8
|
|
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
|
|
8004f84: 2b00 cmp r3, #0
|
|
8004f86: d079 beq.n 800507c <HAL_RCCEx_PeriphCLKConfig+0x22c>
|
|
{
|
|
/* Check the PLLSAI division factors */
|
|
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
|
|
|
|
/* Disable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_DISABLE();
|
|
8004f88: 4b52 ldr r3, [pc, #328] @ (80050d4 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
|
8004f8a: 2200 movs r2, #0
|
|
8004f8c: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8004f8e: f7fc fb25 bl 80015dc <HAL_GetTick>
|
|
8004f92: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLSAI is disabled */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004f94: e008 b.n 8004fa8 <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
8004f96: f7fc fb21 bl 80015dc <HAL_GetTick>
|
|
8004f9a: 4602 mov r2, r0
|
|
8004f9c: 697b ldr r3, [r7, #20]
|
|
8004f9e: 1ad3 subs r3, r2, r3
|
|
8004fa0: 2b02 cmp r3, #2
|
|
8004fa2: d901 bls.n 8004fa8 <HAL_RCCEx_PeriphCLKConfig+0x158>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
8004fa4: 2303 movs r3, #3
|
|
8004fa6: e107 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
|
|
8004fa8: 4b49 ldr r3, [pc, #292] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004faa: 681b ldr r3, [r3, #0]
|
|
8004fac: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004fb0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
8004fb4: d0ef beq.n 8004f96 <HAL_RCCEx_PeriphCLKConfig+0x146>
|
|
}
|
|
|
|
/*---------------------------- SAI configuration -------------------------*/
|
|
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
|
|
be added only for SAI configuration */
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
|
|
8004fb6: 687b ldr r3, [r7, #4]
|
|
8004fb8: 681b ldr r3, [r3, #0]
|
|
8004fba: f003 0304 and.w r3, r3, #4
|
|
8004fbe: 2b00 cmp r3, #0
|
|
8004fc0: d020 beq.n 8005004 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
|
|
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
|
|
|
|
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
|
|
8004fc2: 4b43 ldr r3, [pc, #268] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004fc4: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004fc8: 0f1b lsrs r3, r3, #28
|
|
8004fca: f003 0307 and.w r3, r3, #7
|
|
8004fce: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
|
|
8004fd0: 687b ldr r3, [r7, #4]
|
|
8004fd2: 691b ldr r3, [r3, #16]
|
|
8004fd4: 019a lsls r2, r3, #6
|
|
8004fd6: 687b ldr r3, [r7, #4]
|
|
8004fd8: 695b ldr r3, [r3, #20]
|
|
8004fda: 061b lsls r3, r3, #24
|
|
8004fdc: 431a orrs r2, r3
|
|
8004fde: 693b ldr r3, [r7, #16]
|
|
8004fe0: 071b lsls r3, r3, #28
|
|
8004fe2: 493b ldr r1, [pc, #236] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004fe4: 4313 orrs r3, r2
|
|
8004fe6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
|
|
8004fea: 4b39 ldr r3, [pc, #228] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004fec: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
8004ff0: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
|
|
8004ff4: 687b ldr r3, [r7, #4]
|
|
8004ff6: 6a1b ldr r3, [r3, #32]
|
|
8004ff8: 3b01 subs r3, #1
|
|
8004ffa: 021b lsls r3, r3, #8
|
|
8004ffc: 4934 ldr r1, [pc, #208] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8004ffe: 4313 orrs r3, r2
|
|
8005000: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
|
|
/*---------------------------- LTDC configuration ------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
|
|
8005004: 687b ldr r3, [r7, #4]
|
|
8005006: 681b ldr r3, [r3, #0]
|
|
8005008: f003 0308 and.w r3, r3, #8
|
|
800500c: 2b00 cmp r3, #0
|
|
800500e: d01e beq.n 800504e <HAL_RCCEx_PeriphCLKConfig+0x1fe>
|
|
{
|
|
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
|
|
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
|
|
|
|
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
|
|
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
|
|
8005010: 4b2f ldr r3, [pc, #188] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005012: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005016: 0e1b lsrs r3, r3, #24
|
|
8005018: f003 030f and.w r3, r3, #15
|
|
800501c: 613b str r3, [r7, #16]
|
|
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
|
|
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
|
|
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
|
|
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
|
|
800501e: 687b ldr r3, [r7, #4]
|
|
8005020: 691b ldr r3, [r3, #16]
|
|
8005022: 019a lsls r2, r3, #6
|
|
8005024: 693b ldr r3, [r7, #16]
|
|
8005026: 061b lsls r3, r3, #24
|
|
8005028: 431a orrs r2, r3
|
|
800502a: 687b ldr r3, [r7, #4]
|
|
800502c: 699b ldr r3, [r3, #24]
|
|
800502e: 071b lsls r3, r3, #28
|
|
8005030: 4927 ldr r1, [pc, #156] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005032: 4313 orrs r3, r2
|
|
8005034: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
|
|
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
|
|
8005038: 4b25 ldr r3, [pc, #148] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800503a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
|
|
800503e: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8005042: 687b ldr r3, [r7, #4]
|
|
8005044: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005046: 4922 ldr r1, [pc, #136] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005048: 4313 orrs r3, r2
|
|
800504a: f8c1 308c str.w r3, [r1, #140] @ 0x8c
|
|
}
|
|
/* Enable PLLSAI Clock */
|
|
__HAL_RCC_PLLSAI_ENABLE();
|
|
800504e: 4b21 ldr r3, [pc, #132] @ (80050d4 <HAL_RCCEx_PeriphCLKConfig+0x284>)
|
|
8005050: 2201 movs r2, #1
|
|
8005052: 601a str r2, [r3, #0]
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
8005054: f7fc fac2 bl 80015dc <HAL_GetTick>
|
|
8005058: 6178 str r0, [r7, #20]
|
|
/* Wait till PLLSAI is ready */
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800505a: e008 b.n 800506e <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
|
|
800505c: f7fc fabe bl 80015dc <HAL_GetTick>
|
|
8005060: 4602 mov r2, r0
|
|
8005062: 697b ldr r3, [r7, #20]
|
|
8005064: 1ad3 subs r3, r2, r3
|
|
8005066: 2b02 cmp r3, #2
|
|
8005068: d901 bls.n 800506e <HAL_RCCEx_PeriphCLKConfig+0x21e>
|
|
{
|
|
/* return in case of Timeout detected */
|
|
return HAL_TIMEOUT;
|
|
800506a: 2303 movs r3, #3
|
|
800506c: e0a4 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
|
|
800506e: 4b18 ldr r3, [pc, #96] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005070: 681b ldr r3, [r3, #0]
|
|
8005072: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8005076: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
800507a: d1ef bne.n 800505c <HAL_RCCEx_PeriphCLKConfig+0x20c>
|
|
}
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- RTC configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
|
|
800507c: 687b ldr r3, [r7, #4]
|
|
800507e: 681b ldr r3, [r3, #0]
|
|
8005080: f003 0320 and.w r3, r3, #32
|
|
8005084: 2b00 cmp r3, #0
|
|
8005086: f000 808b beq.w 80051a0 <HAL_RCCEx_PeriphCLKConfig+0x350>
|
|
{
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock*/
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800508a: 2300 movs r3, #0
|
|
800508c: 60fb str r3, [r7, #12]
|
|
800508e: 4b10 ldr r3, [pc, #64] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005090: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005092: 4a0f ldr r2, [pc, #60] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
8005094: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8005098: 6413 str r3, [r2, #64] @ 0x40
|
|
800509a: 4b0d ldr r3, [pc, #52] @ (80050d0 <HAL_RCCEx_PeriphCLKConfig+0x280>)
|
|
800509c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800509e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80050a2: 60fb str r3, [r7, #12]
|
|
80050a4: 68fb ldr r3, [r7, #12]
|
|
|
|
/* Enable write access to Backup domain */
|
|
PWR->CR |= PWR_CR_DBP;
|
|
80050a6: 4b0c ldr r3, [pc, #48] @ (80050d8 <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
|
80050a8: 681b ldr r3, [r3, #0]
|
|
80050aa: 4a0b ldr r2, [pc, #44] @ (80050d8 <HAL_RCCEx_PeriphCLKConfig+0x288>)
|
|
80050ac: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80050b0: 6013 str r3, [r2, #0]
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
80050b2: f7fc fa93 bl 80015dc <HAL_GetTick>
|
|
80050b6: 6178 str r0, [r7, #20]
|
|
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
80050b8: e010 b.n 80050dc <HAL_RCCEx_PeriphCLKConfig+0x28c>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80050ba: f7fc fa8f bl 80015dc <HAL_GetTick>
|
|
80050be: 4602 mov r2, r0
|
|
80050c0: 697b ldr r3, [r7, #20]
|
|
80050c2: 1ad3 subs r3, r2, r3
|
|
80050c4: 2b02 cmp r3, #2
|
|
80050c6: d909 bls.n 80050dc <HAL_RCCEx_PeriphCLKConfig+0x28c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80050c8: 2303 movs r3, #3
|
|
80050ca: e075 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
80050cc: 42470068 .word 0x42470068
|
|
80050d0: 40023800 .word 0x40023800
|
|
80050d4: 42470070 .word 0x42470070
|
|
80050d8: 40007000 .word 0x40007000
|
|
while ((PWR->CR & PWR_CR_DBP) == RESET)
|
|
80050dc: 4b38 ldr r3, [pc, #224] @ (80051c0 <HAL_RCCEx_PeriphCLKConfig+0x370>)
|
|
80050de: 681b ldr r3, [r3, #0]
|
|
80050e0: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80050e4: 2b00 cmp r3, #0
|
|
80050e6: d0e8 beq.n 80050ba <HAL_RCCEx_PeriphCLKConfig+0x26a>
|
|
}
|
|
}
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
|
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
|
|
80050e8: 4b36 ldr r3, [pc, #216] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
80050ea: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80050ec: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80050f0: 613b str r3, [r7, #16]
|
|
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
|
|
80050f2: 693b ldr r3, [r7, #16]
|
|
80050f4: 2b00 cmp r3, #0
|
|
80050f6: d02f beq.n 8005158 <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
80050f8: 687b ldr r3, [r7, #4]
|
|
80050fa: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80050fc: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005100: 693a ldr r2, [r7, #16]
|
|
8005102: 429a cmp r2, r3
|
|
8005104: d028 beq.n 8005158 <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
|
|
8005106: 4b2f ldr r3, [pc, #188] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005108: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
800510a: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800510e: 613b str r3, [r7, #16]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8005110: 4b2d ldr r3, [pc, #180] @ (80051c8 <HAL_RCCEx_PeriphCLKConfig+0x378>)
|
|
8005112: 2201 movs r2, #1
|
|
8005114: 601a str r2, [r3, #0]
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8005116: 4b2c ldr r3, [pc, #176] @ (80051c8 <HAL_RCCEx_PeriphCLKConfig+0x378>)
|
|
8005118: 2200 movs r2, #0
|
|
800511a: 601a str r2, [r3, #0]
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpreg1;
|
|
800511c: 4a29 ldr r2, [pc, #164] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800511e: 693b ldr r3, [r7, #16]
|
|
8005120: 6713 str r3, [r2, #112] @ 0x70
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
|
|
8005122: 4b28 ldr r3, [pc, #160] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005124: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005126: f003 0301 and.w r3, r3, #1
|
|
800512a: 2b01 cmp r3, #1
|
|
800512c: d114 bne.n 8005158 <HAL_RCCEx_PeriphCLKConfig+0x308>
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
800512e: f7fc fa55 bl 80015dc <HAL_GetTick>
|
|
8005132: 6178 str r0, [r7, #20]
|
|
|
|
/* Wait till LSE is ready */
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
8005134: e00a b.n 800514c <HAL_RCCEx_PeriphCLKConfig+0x2fc>
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8005136: f7fc fa51 bl 80015dc <HAL_GetTick>
|
|
800513a: 4602 mov r2, r0
|
|
800513c: 697b ldr r3, [r7, #20]
|
|
800513e: 1ad3 subs r3, r2, r3
|
|
8005140: f241 3288 movw r2, #5000 @ 0x1388
|
|
8005144: 4293 cmp r3, r2
|
|
8005146: d901 bls.n 800514c <HAL_RCCEx_PeriphCLKConfig+0x2fc>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8005148: 2303 movs r3, #3
|
|
800514a: e035 b.n 80051b8 <HAL_RCCEx_PeriphCLKConfig+0x368>
|
|
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
800514c: 4b1d ldr r3, [pc, #116] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800514e: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8005150: f003 0302 and.w r3, r3, #2
|
|
8005154: 2b00 cmp r3, #0
|
|
8005156: d0ee beq.n 8005136 <HAL_RCCEx_PeriphCLKConfig+0x2e6>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
8005158: 687b ldr r3, [r7, #4]
|
|
800515a: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
800515c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005160: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8005164: d10d bne.n 8005182 <HAL_RCCEx_PeriphCLKConfig+0x332>
|
|
8005166: 4b17 ldr r3, [pc, #92] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005168: 689b ldr r3, [r3, #8]
|
|
800516a: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
|
|
800516e: 687b ldr r3, [r7, #4]
|
|
8005170: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005172: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
|
|
8005176: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
800517a: 4912 ldr r1, [pc, #72] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800517c: 4313 orrs r3, r2
|
|
800517e: 608b str r3, [r1, #8]
|
|
8005180: e005 b.n 800518e <HAL_RCCEx_PeriphCLKConfig+0x33e>
|
|
8005182: 4b10 ldr r3, [pc, #64] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005184: 689b ldr r3, [r3, #8]
|
|
8005186: 4a0f ldr r2, [pc, #60] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005188: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
|
|
800518c: 6093 str r3, [r2, #8]
|
|
800518e: 4b0d ldr r3, [pc, #52] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
8005190: 6f1a ldr r2, [r3, #112] @ 0x70
|
|
8005192: 687b ldr r3, [r7, #4]
|
|
8005194: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8005196: f3c3 030b ubfx r3, r3, #0, #12
|
|
800519a: 490a ldr r1, [pc, #40] @ (80051c4 <HAL_RCCEx_PeriphCLKConfig+0x374>)
|
|
800519c: 4313 orrs r3, r2
|
|
800519e: 670b str r3, [r1, #112] @ 0x70
|
|
}
|
|
/*--------------------------------------------------------------------------*/
|
|
|
|
/*---------------------------- TIM configuration ---------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
|
|
80051a0: 687b ldr r3, [r7, #4]
|
|
80051a2: 681b ldr r3, [r3, #0]
|
|
80051a4: f003 0310 and.w r3, r3, #16
|
|
80051a8: 2b00 cmp r3, #0
|
|
80051aa: d004 beq.n 80051b6 <HAL_RCCEx_PeriphCLKConfig+0x366>
|
|
{
|
|
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
|
|
80051ac: 687b ldr r3, [r7, #4]
|
|
80051ae: f893 202c ldrb.w r2, [r3, #44] @ 0x2c
|
|
80051b2: 4b06 ldr r3, [pc, #24] @ (80051cc <HAL_RCCEx_PeriphCLKConfig+0x37c>)
|
|
80051b4: 601a str r2, [r3, #0]
|
|
}
|
|
return HAL_OK;
|
|
80051b6: 2300 movs r3, #0
|
|
}
|
|
80051b8: 4618 mov r0, r3
|
|
80051ba: 3718 adds r7, #24
|
|
80051bc: 46bd mov sp, r7
|
|
80051be: bd80 pop {r7, pc}
|
|
80051c0: 40007000 .word 0x40007000
|
|
80051c4: 40023800 .word 0x40023800
|
|
80051c8: 42470e40 .word 0x42470e40
|
|
80051cc: 424711e0 .word 0x424711e0
|
|
|
|
080051d0 <HAL_SDRAM_Init>:
|
|
* the configuration information for SDRAM module.
|
|
* @param Timing Pointer to SDRAM control timing structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
|
|
{
|
|
80051d0: b580 push {r7, lr}
|
|
80051d2: b082 sub sp, #8
|
|
80051d4: af00 add r7, sp, #0
|
|
80051d6: 6078 str r0, [r7, #4]
|
|
80051d8: 6039 str r1, [r7, #0]
|
|
/* Check the SDRAM handle parameter */
|
|
if (hsdram == NULL)
|
|
80051da: 687b ldr r3, [r7, #4]
|
|
80051dc: 2b00 cmp r3, #0
|
|
80051de: d101 bne.n 80051e4 <HAL_SDRAM_Init+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
80051e0: 2301 movs r3, #1
|
|
80051e2: e025 b.n 8005230 <HAL_SDRAM_Init+0x60>
|
|
}
|
|
|
|
if (hsdram->State == HAL_SDRAM_STATE_RESET)
|
|
80051e4: 687b ldr r3, [r7, #4]
|
|
80051e6: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
|
|
80051ea: b2db uxtb r3, r3
|
|
80051ec: 2b00 cmp r3, #0
|
|
80051ee: d106 bne.n 80051fe <HAL_SDRAM_Init+0x2e>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hsdram->Lock = HAL_UNLOCKED;
|
|
80051f0: 687b ldr r3, [r7, #4]
|
|
80051f2: 2200 movs r2, #0
|
|
80051f4: f883 202d strb.w r2, [r3, #45] @ 0x2d
|
|
|
|
/* Init the low level hardware */
|
|
hsdram->MspInitCallback(hsdram);
|
|
#else
|
|
/* Initialize the low level hardware (MSP) */
|
|
HAL_SDRAM_MspInit(hsdram);
|
|
80051f8: 6878 ldr r0, [r7, #4]
|
|
80051fa: f7fc f8b3 bl 8001364 <HAL_SDRAM_MspInit>
|
|
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Initialize the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
80051fe: 687b ldr r3, [r7, #4]
|
|
8005200: 2202 movs r2, #2
|
|
8005202: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
/* Initialize SDRAM control Interface */
|
|
(void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
|
|
8005206: 687b ldr r3, [r7, #4]
|
|
8005208: 681a ldr r2, [r3, #0]
|
|
800520a: 687b ldr r3, [r7, #4]
|
|
800520c: 3304 adds r3, #4
|
|
800520e: 4619 mov r1, r3
|
|
8005210: 4610 mov r0, r2
|
|
8005212: f000 ffcd bl 80061b0 <FMC_SDRAM_Init>
|
|
|
|
/* Initialize SDRAM timing Interface */
|
|
(void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
|
|
8005216: 687b ldr r3, [r7, #4]
|
|
8005218: 6818 ldr r0, [r3, #0]
|
|
800521a: 687b ldr r3, [r7, #4]
|
|
800521c: 685b ldr r3, [r3, #4]
|
|
800521e: 461a mov r2, r3
|
|
8005220: 6839 ldr r1, [r7, #0]
|
|
8005222: f001 f822 bl 800626a <FMC_SDRAM_Timing_Init>
|
|
/* Update the SDRAM controller state */
|
|
hsdram->State = HAL_SDRAM_STATE_READY;
|
|
8005226: 687b ldr r3, [r7, #4]
|
|
8005228: 2201 movs r2, #1
|
|
800522a: f883 202c strb.w r2, [r3, #44] @ 0x2c
|
|
|
|
return HAL_OK;
|
|
800522e: 2300 movs r3, #0
|
|
}
|
|
8005230: 4618 mov r0, r3
|
|
8005232: 3708 adds r7, #8
|
|
8005234: 46bd mov sp, r7
|
|
8005236: bd80 pop {r7, pc}
|
|
|
|
08005238 <HAL_SPI_Init>:
|
|
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
|
|
* the configuration information for SPI module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
|
|
{
|
|
8005238: b580 push {r7, lr}
|
|
800523a: b082 sub sp, #8
|
|
800523c: af00 add r7, sp, #0
|
|
800523e: 6078 str r0, [r7, #4]
|
|
/* Check the SPI handle allocation */
|
|
if (hspi == NULL)
|
|
8005240: 687b ldr r3, [r7, #4]
|
|
8005242: 2b00 cmp r3, #0
|
|
8005244: d101 bne.n 800524a <HAL_SPI_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005246: 2301 movs r3, #1
|
|
8005248: e07b b.n 8005342 <HAL_SPI_Init+0x10a>
|
|
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
|
|
assert_param(IS_SPI_NSS(hspi->Init.NSS));
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
|
|
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
|
|
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
|
|
800524a: 687b ldr r3, [r7, #4]
|
|
800524c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800524e: 2b00 cmp r3, #0
|
|
8005250: d108 bne.n 8005264 <HAL_SPI_Init+0x2c>
|
|
{
|
|
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
|
|
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
|
|
|
|
if (hspi->Init.Mode == SPI_MODE_MASTER)
|
|
8005252: 687b ldr r3, [r7, #4]
|
|
8005254: 685b ldr r3, [r3, #4]
|
|
8005256: f5b3 7f82 cmp.w r3, #260 @ 0x104
|
|
800525a: d009 beq.n 8005270 <HAL_SPI_Init+0x38>
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
}
|
|
else
|
|
{
|
|
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
|
|
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
|
800525c: 687b ldr r3, [r7, #4]
|
|
800525e: 2200 movs r2, #0
|
|
8005260: 61da str r2, [r3, #28]
|
|
8005262: e005 b.n 8005270 <HAL_SPI_Init+0x38>
|
|
else
|
|
{
|
|
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
|
|
|
|
/* Force polarity and phase to TI protocaol requirements */
|
|
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
|
|
8005264: 687b ldr r3, [r7, #4]
|
|
8005266: 2200 movs r2, #0
|
|
8005268: 611a str r2, [r3, #16]
|
|
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
|
|
800526a: 687b ldr r3, [r7, #4]
|
|
800526c: 2200 movs r2, #0
|
|
800526e: 615a str r2, [r3, #20]
|
|
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
|
|
{
|
|
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
|
|
}
|
|
#else
|
|
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
|
8005270: 687b ldr r3, [r7, #4]
|
|
8005272: 2200 movs r2, #0
|
|
8005274: 629a str r2, [r3, #40] @ 0x28
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
if (hspi->State == HAL_SPI_STATE_RESET)
|
|
8005276: 687b ldr r3, [r7, #4]
|
|
8005278: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
|
|
800527c: b2db uxtb r3, r3
|
|
800527e: 2b00 cmp r3, #0
|
|
8005280: d106 bne.n 8005290 <HAL_SPI_Init+0x58>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hspi->Lock = HAL_UNLOCKED;
|
|
8005282: 687b ldr r3, [r7, #4]
|
|
8005284: 2200 movs r2, #0
|
|
8005286: f883 2050 strb.w r2, [r3, #80] @ 0x50
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
hspi->MspInitCallback(hspi);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
|
|
HAL_SPI_MspInit(hspi);
|
|
800528a: 6878 ldr r0, [r7, #4]
|
|
800528c: f7fb ff26 bl 80010dc <HAL_SPI_MspInit>
|
|
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hspi->State = HAL_SPI_STATE_BUSY;
|
|
8005290: 687b ldr r3, [r7, #4]
|
|
8005292: 2202 movs r2, #2
|
|
8005294: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
/* Disable the selected SPI peripheral */
|
|
__HAL_SPI_DISABLE(hspi);
|
|
8005298: 687b ldr r3, [r7, #4]
|
|
800529a: 681b ldr r3, [r3, #0]
|
|
800529c: 681a ldr r2, [r3, #0]
|
|
800529e: 687b ldr r3, [r7, #4]
|
|
80052a0: 681b ldr r3, [r3, #0]
|
|
80052a2: f022 0240 bic.w r2, r2, #64 @ 0x40
|
|
80052a6: 601a str r2, [r3, #0]
|
|
|
|
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
|
|
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
|
|
Communication speed, First bit and CRC calculation state */
|
|
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
|
|
80052a8: 687b ldr r3, [r7, #4]
|
|
80052aa: 685b ldr r3, [r3, #4]
|
|
80052ac: f403 7282 and.w r2, r3, #260 @ 0x104
|
|
80052b0: 687b ldr r3, [r7, #4]
|
|
80052b2: 689b ldr r3, [r3, #8]
|
|
80052b4: f403 4304 and.w r3, r3, #33792 @ 0x8400
|
|
80052b8: 431a orrs r2, r3
|
|
80052ba: 687b ldr r3, [r7, #4]
|
|
80052bc: 68db ldr r3, [r3, #12]
|
|
80052be: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
80052c2: 431a orrs r2, r3
|
|
80052c4: 687b ldr r3, [r7, #4]
|
|
80052c6: 691b ldr r3, [r3, #16]
|
|
80052c8: f003 0302 and.w r3, r3, #2
|
|
80052cc: 431a orrs r2, r3
|
|
80052ce: 687b ldr r3, [r7, #4]
|
|
80052d0: 695b ldr r3, [r3, #20]
|
|
80052d2: f003 0301 and.w r3, r3, #1
|
|
80052d6: 431a orrs r2, r3
|
|
80052d8: 687b ldr r3, [r7, #4]
|
|
80052da: 699b ldr r3, [r3, #24]
|
|
80052dc: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80052e0: 431a orrs r2, r3
|
|
80052e2: 687b ldr r3, [r7, #4]
|
|
80052e4: 69db ldr r3, [r3, #28]
|
|
80052e6: f003 0338 and.w r3, r3, #56 @ 0x38
|
|
80052ea: 431a orrs r2, r3
|
|
80052ec: 687b ldr r3, [r7, #4]
|
|
80052ee: 6a1b ldr r3, [r3, #32]
|
|
80052f0: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80052f4: ea42 0103 orr.w r1, r2, r3
|
|
80052f8: 687b ldr r3, [r7, #4]
|
|
80052fa: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80052fc: f403 5200 and.w r2, r3, #8192 @ 0x2000
|
|
8005300: 687b ldr r3, [r7, #4]
|
|
8005302: 681b ldr r3, [r3, #0]
|
|
8005304: 430a orrs r2, r1
|
|
8005306: 601a str r2, [r3, #0]
|
|
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
|
|
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
|
|
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
|
|
|
|
/* Configure : NSS management, TI Mode */
|
|
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
|
|
8005308: 687b ldr r3, [r7, #4]
|
|
800530a: 699b ldr r3, [r3, #24]
|
|
800530c: 0c1b lsrs r3, r3, #16
|
|
800530e: f003 0104 and.w r1, r3, #4
|
|
8005312: 687b ldr r3, [r7, #4]
|
|
8005314: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005316: f003 0210 and.w r2, r3, #16
|
|
800531a: 687b ldr r3, [r7, #4]
|
|
800531c: 681b ldr r3, [r3, #0]
|
|
800531e: 430a orrs r2, r1
|
|
8005320: 605a str r2, [r3, #4]
|
|
}
|
|
#endif /* USE_SPI_CRC */
|
|
|
|
#if defined(SPI_I2SCFGR_I2SMOD)
|
|
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
|
|
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
|
8005322: 687b ldr r3, [r7, #4]
|
|
8005324: 681b ldr r3, [r3, #0]
|
|
8005326: 69da ldr r2, [r3, #28]
|
|
8005328: 687b ldr r3, [r7, #4]
|
|
800532a: 681b ldr r3, [r3, #0]
|
|
800532c: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8005330: 61da str r2, [r3, #28]
|
|
#endif /* SPI_I2SCFGR_I2SMOD */
|
|
|
|
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
|
|
8005332: 687b ldr r3, [r7, #4]
|
|
8005334: 2200 movs r2, #0
|
|
8005336: 655a str r2, [r3, #84] @ 0x54
|
|
hspi->State = HAL_SPI_STATE_READY;
|
|
8005338: 687b ldr r3, [r7, #4]
|
|
800533a: 2201 movs r2, #1
|
|
800533c: f883 2051 strb.w r2, [r3, #81] @ 0x51
|
|
|
|
return HAL_OK;
|
|
8005340: 2300 movs r3, #0
|
|
}
|
|
8005342: 4618 mov r0, r3
|
|
8005344: 3708 adds r7, #8
|
|
8005346: 46bd mov sp, r7
|
|
8005348: bd80 pop {r7, pc}
|
|
|
|
0800534a <HAL_TIM_Base_Init>:
|
|
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
|
|
{
|
|
800534a: b580 push {r7, lr}
|
|
800534c: b082 sub sp, #8
|
|
800534e: af00 add r7, sp, #0
|
|
8005350: 6078 str r0, [r7, #4]
|
|
/* Check the TIM handle allocation */
|
|
if (htim == NULL)
|
|
8005352: 687b ldr r3, [r7, #4]
|
|
8005354: 2b00 cmp r3, #0
|
|
8005356: d101 bne.n 800535c <HAL_TIM_Base_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005358: 2301 movs r3, #1
|
|
800535a: e041 b.n 80053e0 <HAL_TIM_Base_Init+0x96>
|
|
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
|
|
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
|
|
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
|
|
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
|
|
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
800535c: 687b ldr r3, [r7, #4]
|
|
800535e: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
8005362: b2db uxtb r3, r3
|
|
8005364: 2b00 cmp r3, #0
|
|
8005366: d106 bne.n 8005376 <HAL_TIM_Base_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8005368: 687b ldr r3, [r7, #4]
|
|
800536a: 2200 movs r2, #0
|
|
800536c: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
}
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
htim->Base_MspInitCallback(htim);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, NVIC */
|
|
HAL_TIM_Base_MspInit(htim);
|
|
8005370: 6878 ldr r0, [r7, #4]
|
|
8005372: f7fb fefb bl 800116c <HAL_TIM_Base_MspInit>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005376: 687b ldr r3, [r7, #4]
|
|
8005378: 2202 movs r2, #2
|
|
800537a: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Set the Time Base configuration */
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
800537e: 687b ldr r3, [r7, #4]
|
|
8005380: 681a ldr r2, [r3, #0]
|
|
8005382: 687b ldr r3, [r7, #4]
|
|
8005384: 3304 adds r3, #4
|
|
8005386: 4619 mov r1, r3
|
|
8005388: 4610 mov r0, r2
|
|
800538a: f000 fa7d bl 8005888 <TIM_Base_SetConfig>
|
|
|
|
/* Initialize the DMA burst operation state */
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
800538e: 687b ldr r3, [r7, #4]
|
|
8005390: 2201 movs r2, #1
|
|
8005392: f883 2046 strb.w r2, [r3, #70] @ 0x46
|
|
|
|
/* Initialize the TIM channels state */
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8005396: 687b ldr r3, [r7, #4]
|
|
8005398: 2201 movs r2, #1
|
|
800539a: f883 203e strb.w r2, [r3, #62] @ 0x3e
|
|
800539e: 687b ldr r3, [r7, #4]
|
|
80053a0: 2201 movs r2, #1
|
|
80053a2: f883 203f strb.w r2, [r3, #63] @ 0x3f
|
|
80053a6: 687b ldr r3, [r7, #4]
|
|
80053a8: 2201 movs r2, #1
|
|
80053aa: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
80053ae: 687b ldr r3, [r7, #4]
|
|
80053b0: 2201 movs r2, #1
|
|
80053b2: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
80053b6: 687b ldr r3, [r7, #4]
|
|
80053b8: 2201 movs r2, #1
|
|
80053ba: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
80053be: 687b ldr r3, [r7, #4]
|
|
80053c0: 2201 movs r2, #1
|
|
80053c2: f883 2043 strb.w r2, [r3, #67] @ 0x43
|
|
80053c6: 687b ldr r3, [r7, #4]
|
|
80053c8: 2201 movs r2, #1
|
|
80053ca: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
80053ce: 687b ldr r3, [r7, #4]
|
|
80053d0: 2201 movs r2, #1
|
|
80053d2: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
|
|
/* Initialize the TIM state*/
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80053d6: 687b ldr r3, [r7, #4]
|
|
80053d8: 2201 movs r2, #1
|
|
80053da: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
return HAL_OK;
|
|
80053de: 2300 movs r3, #0
|
|
}
|
|
80053e0: 4618 mov r0, r3
|
|
80053e2: 3708 adds r7, #8
|
|
80053e4: 46bd mov sp, r7
|
|
80053e6: bd80 pop {r7, pc}
|
|
|
|
080053e8 <HAL_TIM_Base_Start_IT>:
|
|
* @brief Starts the TIM Base generation in interrupt mode.
|
|
* @param htim TIM Base handle
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
|
|
{
|
|
80053e8: b480 push {r7}
|
|
80053ea: b085 sub sp, #20
|
|
80053ec: af00 add r7, sp, #0
|
|
80053ee: 6078 str r0, [r7, #4]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_INSTANCE(htim->Instance));
|
|
|
|
/* Check the TIM state */
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
80053f0: 687b ldr r3, [r7, #4]
|
|
80053f2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
|
|
80053f6: b2db uxtb r3, r3
|
|
80053f8: 2b01 cmp r3, #1
|
|
80053fa: d001 beq.n 8005400 <HAL_TIM_Base_Start_IT+0x18>
|
|
{
|
|
return HAL_ERROR;
|
|
80053fc: 2301 movs r3, #1
|
|
80053fe: e04e b.n 800549e <HAL_TIM_Base_Start_IT+0xb6>
|
|
}
|
|
|
|
/* Set the TIM state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005400: 687b ldr r3, [r7, #4]
|
|
8005402: 2202 movs r2, #2
|
|
8005404: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Enable the TIM Update interrupt */
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
8005408: 687b ldr r3, [r7, #4]
|
|
800540a: 681b ldr r3, [r3, #0]
|
|
800540c: 68da ldr r2, [r3, #12]
|
|
800540e: 687b ldr r3, [r7, #4]
|
|
8005410: 681b ldr r3, [r3, #0]
|
|
8005412: f042 0201 orr.w r2, r2, #1
|
|
8005416: 60da str r2, [r3, #12]
|
|
|
|
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005418: 687b ldr r3, [r7, #4]
|
|
800541a: 681b ldr r3, [r3, #0]
|
|
800541c: 4a23 ldr r2, [pc, #140] @ (80054ac <HAL_TIM_Base_Start_IT+0xc4>)
|
|
800541e: 4293 cmp r3, r2
|
|
8005420: d022 beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
8005422: 687b ldr r3, [r7, #4]
|
|
8005424: 681b ldr r3, [r3, #0]
|
|
8005426: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
800542a: d01d beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
800542c: 687b ldr r3, [r7, #4]
|
|
800542e: 681b ldr r3, [r3, #0]
|
|
8005430: 4a1f ldr r2, [pc, #124] @ (80054b0 <HAL_TIM_Base_Start_IT+0xc8>)
|
|
8005432: 4293 cmp r3, r2
|
|
8005434: d018 beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
8005436: 687b ldr r3, [r7, #4]
|
|
8005438: 681b ldr r3, [r3, #0]
|
|
800543a: 4a1e ldr r2, [pc, #120] @ (80054b4 <HAL_TIM_Base_Start_IT+0xcc>)
|
|
800543c: 4293 cmp r3, r2
|
|
800543e: d013 beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
8005440: 687b ldr r3, [r7, #4]
|
|
8005442: 681b ldr r3, [r3, #0]
|
|
8005444: 4a1c ldr r2, [pc, #112] @ (80054b8 <HAL_TIM_Base_Start_IT+0xd0>)
|
|
8005446: 4293 cmp r3, r2
|
|
8005448: d00e beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
800544a: 687b ldr r3, [r7, #4]
|
|
800544c: 681b ldr r3, [r3, #0]
|
|
800544e: 4a1b ldr r2, [pc, #108] @ (80054bc <HAL_TIM_Base_Start_IT+0xd4>)
|
|
8005450: 4293 cmp r3, r2
|
|
8005452: d009 beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
8005454: 687b ldr r3, [r7, #4]
|
|
8005456: 681b ldr r3, [r3, #0]
|
|
8005458: 4a19 ldr r2, [pc, #100] @ (80054c0 <HAL_TIM_Base_Start_IT+0xd8>)
|
|
800545a: 4293 cmp r3, r2
|
|
800545c: d004 beq.n 8005468 <HAL_TIM_Base_Start_IT+0x80>
|
|
800545e: 687b ldr r3, [r7, #4]
|
|
8005460: 681b ldr r3, [r3, #0]
|
|
8005462: 4a18 ldr r2, [pc, #96] @ (80054c4 <HAL_TIM_Base_Start_IT+0xdc>)
|
|
8005464: 4293 cmp r3, r2
|
|
8005466: d111 bne.n 800548c <HAL_TIM_Base_Start_IT+0xa4>
|
|
{
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8005468: 687b ldr r3, [r7, #4]
|
|
800546a: 681b ldr r3, [r3, #0]
|
|
800546c: 689b ldr r3, [r3, #8]
|
|
800546e: f003 0307 and.w r3, r3, #7
|
|
8005472: 60fb str r3, [r7, #12]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8005474: 68fb ldr r3, [r7, #12]
|
|
8005476: 2b06 cmp r3, #6
|
|
8005478: d010 beq.n 800549c <HAL_TIM_Base_Start_IT+0xb4>
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800547a: 687b ldr r3, [r7, #4]
|
|
800547c: 681b ldr r3, [r3, #0]
|
|
800547e: 681a ldr r2, [r3, #0]
|
|
8005480: 687b ldr r3, [r7, #4]
|
|
8005482: 681b ldr r3, [r3, #0]
|
|
8005484: f042 0201 orr.w r2, r2, #1
|
|
8005488: 601a str r2, [r3, #0]
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800548a: e007 b.n 800549c <HAL_TIM_Base_Start_IT+0xb4>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
__HAL_TIM_ENABLE(htim);
|
|
800548c: 687b ldr r3, [r7, #4]
|
|
800548e: 681b ldr r3, [r3, #0]
|
|
8005490: 681a ldr r2, [r3, #0]
|
|
8005492: 687b ldr r3, [r7, #4]
|
|
8005494: 681b ldr r3, [r3, #0]
|
|
8005496: f042 0201 orr.w r2, r2, #1
|
|
800549a: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Return function status */
|
|
return HAL_OK;
|
|
800549c: 2300 movs r3, #0
|
|
}
|
|
800549e: 4618 mov r0, r3
|
|
80054a0: 3714 adds r7, #20
|
|
80054a2: 46bd mov sp, r7
|
|
80054a4: f85d 7b04 ldr.w r7, [sp], #4
|
|
80054a8: 4770 bx lr
|
|
80054aa: bf00 nop
|
|
80054ac: 40010000 .word 0x40010000
|
|
80054b0: 40000400 .word 0x40000400
|
|
80054b4: 40000800 .word 0x40000800
|
|
80054b8: 40000c00 .word 0x40000c00
|
|
80054bc: 40010400 .word 0x40010400
|
|
80054c0: 40014000 .word 0x40014000
|
|
80054c4: 40001800 .word 0x40001800
|
|
|
|
080054c8 <HAL_TIM_IRQHandler>:
|
|
* @brief This function handles TIM interrupts requests.
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
|
{
|
|
80054c8: b580 push {r7, lr}
|
|
80054ca: b084 sub sp, #16
|
|
80054cc: af00 add r7, sp, #0
|
|
80054ce: 6078 str r0, [r7, #4]
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
80054d0: 687b ldr r3, [r7, #4]
|
|
80054d2: 681b ldr r3, [r3, #0]
|
|
80054d4: 68db ldr r3, [r3, #12]
|
|
80054d6: 60fb str r3, [r7, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
80054d8: 687b ldr r3, [r7, #4]
|
|
80054da: 681b ldr r3, [r3, #0]
|
|
80054dc: 691b ldr r3, [r3, #16]
|
|
80054de: 60bb str r3, [r7, #8]
|
|
|
|
/* Capture compare 1 event */
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
80054e0: 68bb ldr r3, [r7, #8]
|
|
80054e2: f003 0302 and.w r3, r3, #2
|
|
80054e6: 2b00 cmp r3, #0
|
|
80054e8: d020 beq.n 800552c <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
80054ea: 68fb ldr r3, [r7, #12]
|
|
80054ec: f003 0302 and.w r3, r3, #2
|
|
80054f0: 2b00 cmp r3, #0
|
|
80054f2: d01b beq.n 800552c <HAL_TIM_IRQHandler+0x64>
|
|
{
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
80054f4: 687b ldr r3, [r7, #4]
|
|
80054f6: 681b ldr r3, [r3, #0]
|
|
80054f8: f06f 0202 mvn.w r2, #2
|
|
80054fc: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
80054fe: 687b ldr r3, [r7, #4]
|
|
8005500: 2201 movs r2, #1
|
|
8005502: 771a strb r2, [r3, #28]
|
|
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
8005504: 687b ldr r3, [r7, #4]
|
|
8005506: 681b ldr r3, [r3, #0]
|
|
8005508: 699b ldr r3, [r3, #24]
|
|
800550a: f003 0303 and.w r3, r3, #3
|
|
800550e: 2b00 cmp r3, #0
|
|
8005510: d003 beq.n 800551a <HAL_TIM_IRQHandler+0x52>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8005512: 6878 ldr r0, [r7, #4]
|
|
8005514: f000 f999 bl 800584a <HAL_TIM_IC_CaptureCallback>
|
|
8005518: e005 b.n 8005526 <HAL_TIM_IRQHandler+0x5e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
800551a: 6878 ldr r0, [r7, #4]
|
|
800551c: f000 f98b bl 8005836 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005520: 6878 ldr r0, [r7, #4]
|
|
8005522: f000 f99c bl 800585e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005526: 687b ldr r3, [r7, #4]
|
|
8005528: 2200 movs r2, #0
|
|
800552a: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
}
|
|
/* Capture compare 2 event */
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
800552c: 68bb ldr r3, [r7, #8]
|
|
800552e: f003 0304 and.w r3, r3, #4
|
|
8005532: 2b00 cmp r3, #0
|
|
8005534: d020 beq.n 8005578 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8005536: 68fb ldr r3, [r7, #12]
|
|
8005538: f003 0304 and.w r3, r3, #4
|
|
800553c: 2b00 cmp r3, #0
|
|
800553e: d01b beq.n 8005578 <HAL_TIM_IRQHandler+0xb0>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8005540: 687b ldr r3, [r7, #4]
|
|
8005542: 681b ldr r3, [r3, #0]
|
|
8005544: f06f 0204 mvn.w r2, #4
|
|
8005548: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
800554a: 687b ldr r3, [r7, #4]
|
|
800554c: 2202 movs r2, #2
|
|
800554e: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8005550: 687b ldr r3, [r7, #4]
|
|
8005552: 681b ldr r3, [r3, #0]
|
|
8005554: 699b ldr r3, [r3, #24]
|
|
8005556: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800555a: 2b00 cmp r3, #0
|
|
800555c: d003 beq.n 8005566 <HAL_TIM_IRQHandler+0x9e>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
800555e: 6878 ldr r0, [r7, #4]
|
|
8005560: f000 f973 bl 800584a <HAL_TIM_IC_CaptureCallback>
|
|
8005564: e005 b.n 8005572 <HAL_TIM_IRQHandler+0xaa>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8005566: 6878 ldr r0, [r7, #4]
|
|
8005568: f000 f965 bl 8005836 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
800556c: 6878 ldr r0, [r7, #4]
|
|
800556e: f000 f976 bl 800585e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8005572: 687b ldr r3, [r7, #4]
|
|
8005574: 2200 movs r2, #0
|
|
8005576: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 3 event */
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8005578: 68bb ldr r3, [r7, #8]
|
|
800557a: f003 0308 and.w r3, r3, #8
|
|
800557e: 2b00 cmp r3, #0
|
|
8005580: d020 beq.n 80055c4 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8005582: 68fb ldr r3, [r7, #12]
|
|
8005584: f003 0308 and.w r3, r3, #8
|
|
8005588: 2b00 cmp r3, #0
|
|
800558a: d01b beq.n 80055c4 <HAL_TIM_IRQHandler+0xfc>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
800558c: 687b ldr r3, [r7, #4]
|
|
800558e: 681b ldr r3, [r3, #0]
|
|
8005590: f06f 0208 mvn.w r2, #8
|
|
8005594: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8005596: 687b ldr r3, [r7, #4]
|
|
8005598: 2204 movs r2, #4
|
|
800559a: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
800559c: 687b ldr r3, [r7, #4]
|
|
800559e: 681b ldr r3, [r3, #0]
|
|
80055a0: 69db ldr r3, [r3, #28]
|
|
80055a2: f003 0303 and.w r3, r3, #3
|
|
80055a6: 2b00 cmp r3, #0
|
|
80055a8: d003 beq.n 80055b2 <HAL_TIM_IRQHandler+0xea>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80055aa: 6878 ldr r0, [r7, #4]
|
|
80055ac: f000 f94d bl 800584a <HAL_TIM_IC_CaptureCallback>
|
|
80055b0: e005 b.n 80055be <HAL_TIM_IRQHandler+0xf6>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80055b2: 6878 ldr r0, [r7, #4]
|
|
80055b4: f000 f93f bl 8005836 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
80055b8: 6878 ldr r0, [r7, #4]
|
|
80055ba: f000 f950 bl 800585e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
80055be: 687b ldr r3, [r7, #4]
|
|
80055c0: 2200 movs r2, #0
|
|
80055c2: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* Capture compare 4 event */
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
80055c4: 68bb ldr r3, [r7, #8]
|
|
80055c6: f003 0310 and.w r3, r3, #16
|
|
80055ca: 2b00 cmp r3, #0
|
|
80055cc: d020 beq.n 8005610 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
80055ce: 68fb ldr r3, [r7, #12]
|
|
80055d0: f003 0310 and.w r3, r3, #16
|
|
80055d4: 2b00 cmp r3, #0
|
|
80055d6: d01b beq.n 8005610 <HAL_TIM_IRQHandler+0x148>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
80055d8: 687b ldr r3, [r7, #4]
|
|
80055da: 681b ldr r3, [r3, #0]
|
|
80055dc: f06f 0210 mvn.w r2, #16
|
|
80055e0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
80055e2: 687b ldr r3, [r7, #4]
|
|
80055e4: 2208 movs r2, #8
|
|
80055e6: 771a strb r2, [r3, #28]
|
|
/* Input capture event */
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
80055e8: 687b ldr r3, [r7, #4]
|
|
80055ea: 681b ldr r3, [r3, #0]
|
|
80055ec: 69db ldr r3, [r3, #28]
|
|
80055ee: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
80055f2: 2b00 cmp r3, #0
|
|
80055f4: d003 beq.n 80055fe <HAL_TIM_IRQHandler+0x136>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->IC_CaptureCallback(htim);
|
|
#else
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
80055f6: 6878 ldr r0, [r7, #4]
|
|
80055f8: f000 f927 bl 800584a <HAL_TIM_IC_CaptureCallback>
|
|
80055fc: e005 b.n 800560a <HAL_TIM_IRQHandler+0x142>
|
|
{
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->OC_DelayElapsedCallback(htim);
|
|
htim->PWM_PulseFinishedCallback(htim);
|
|
#else
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
80055fe: 6878 ldr r0, [r7, #4]
|
|
8005600: f000 f919 bl 8005836 <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8005604: 6878 ldr r0, [r7, #4]
|
|
8005606: f000 f92a bl 800585e <HAL_TIM_PWM_PulseFinishedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
800560a: 687b ldr r3, [r7, #4]
|
|
800560c: 2200 movs r2, #0
|
|
800560e: 771a strb r2, [r3, #28]
|
|
}
|
|
}
|
|
/* TIM Update event */
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
8005610: 68bb ldr r3, [r7, #8]
|
|
8005612: f003 0301 and.w r3, r3, #1
|
|
8005616: 2b00 cmp r3, #0
|
|
8005618: d00c beq.n 8005634 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
800561a: 68fb ldr r3, [r7, #12]
|
|
800561c: f003 0301 and.w r3, r3, #1
|
|
8005620: 2b00 cmp r3, #0
|
|
8005622: d007 beq.n 8005634 <HAL_TIM_IRQHandler+0x16c>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8005624: 687b ldr r3, [r7, #4]
|
|
8005626: 681b ldr r3, [r3, #0]
|
|
8005628: f06f 0201 mvn.w r2, #1
|
|
800562c: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->PeriodElapsedCallback(htim);
|
|
#else
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
800562e: 6878 ldr r0, [r7, #4]
|
|
8005630: f7fb fb2c bl 8000c8c <HAL_TIM_PeriodElapsedCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Break input event */
|
|
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
|
8005634: 68bb ldr r3, [r7, #8]
|
|
8005636: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
800563a: 2b00 cmp r3, #0
|
|
800563c: d00c beq.n 8005658 <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
800563e: 68fb ldr r3, [r7, #12]
|
|
8005640: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005644: 2b00 cmp r3, #0
|
|
8005646: d007 beq.n 8005658 <HAL_TIM_IRQHandler+0x190>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
|
|
8005648: 687b ldr r3, [r7, #4]
|
|
800564a: 681b ldr r3, [r3, #0]
|
|
800564c: f06f 0280 mvn.w r2, #128 @ 0x80
|
|
8005650: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->BreakCallback(htim);
|
|
#else
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8005652: 6878 ldr r0, [r7, #4]
|
|
8005654: f000 fade bl 8005c14 <HAL_TIMEx_BreakCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM Trigger detection event */
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
8005658: 68bb ldr r3, [r7, #8]
|
|
800565a: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800565e: 2b00 cmp r3, #0
|
|
8005660: d00c beq.n 800567c <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8005662: 68fb ldr r3, [r7, #12]
|
|
8005664: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005668: 2b00 cmp r3, #0
|
|
800566a: d007 beq.n 800567c <HAL_TIM_IRQHandler+0x1b4>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
800566c: 687b ldr r3, [r7, #4]
|
|
800566e: 681b ldr r3, [r3, #0]
|
|
8005670: f06f 0240 mvn.w r2, #64 @ 0x40
|
|
8005674: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->TriggerCallback(htim);
|
|
#else
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8005676: 6878 ldr r0, [r7, #4]
|
|
8005678: f000 f8fb bl 8005872 <HAL_TIM_TriggerCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
/* TIM commutation event */
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
800567c: 68bb ldr r3, [r7, #8]
|
|
800567e: f003 0320 and.w r3, r3, #32
|
|
8005682: 2b00 cmp r3, #0
|
|
8005684: d00c beq.n 80056a0 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
8005686: 68fb ldr r3, [r7, #12]
|
|
8005688: f003 0320 and.w r3, r3, #32
|
|
800568c: 2b00 cmp r3, #0
|
|
800568e: d007 beq.n 80056a0 <HAL_TIM_IRQHandler+0x1d8>
|
|
{
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8005690: 687b ldr r3, [r7, #4]
|
|
8005692: 681b ldr r3, [r3, #0]
|
|
8005694: f06f 0220 mvn.w r2, #32
|
|
8005698: 611a str r2, [r3, #16]
|
|
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
|
htim->CommutationCallback(htim);
|
|
#else
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
800569a: 6878 ldr r0, [r7, #4]
|
|
800569c: f000 fab0 bl 8005c00 <HAL_TIMEx_CommutCallback>
|
|
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
|
|
}
|
|
}
|
|
}
|
|
80056a0: bf00 nop
|
|
80056a2: 3710 adds r7, #16
|
|
80056a4: 46bd mov sp, r7
|
|
80056a6: bd80 pop {r7, pc}
|
|
|
|
080056a8 <HAL_TIM_ConfigClockSource>:
|
|
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
|
|
* contains the clock source information for the TIM peripheral.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
|
|
{
|
|
80056a8: b580 push {r7, lr}
|
|
80056aa: b084 sub sp, #16
|
|
80056ac: af00 add r7, sp, #0
|
|
80056ae: 6078 str r0, [r7, #4]
|
|
80056b0: 6039 str r1, [r7, #0]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80056b2: 2300 movs r3, #0
|
|
80056b4: 73fb strb r3, [r7, #15]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(htim);
|
|
80056b6: 687b ldr r3, [r7, #4]
|
|
80056b8: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
80056bc: 2b01 cmp r3, #1
|
|
80056be: d101 bne.n 80056c4 <HAL_TIM_ConfigClockSource+0x1c>
|
|
80056c0: 2302 movs r3, #2
|
|
80056c2: e0b4 b.n 800582e <HAL_TIM_ConfigClockSource+0x186>
|
|
80056c4: 687b ldr r3, [r7, #4]
|
|
80056c6: 2201 movs r2, #1
|
|
80056c8: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80056cc: 687b ldr r3, [r7, #4]
|
|
80056ce: 2202 movs r2, #2
|
|
80056d0: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
|
|
|
|
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80056d4: 687b ldr r3, [r7, #4]
|
|
80056d6: 681b ldr r3, [r3, #0]
|
|
80056d8: 689b ldr r3, [r3, #8]
|
|
80056da: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
|
|
80056dc: 68bb ldr r3, [r7, #8]
|
|
80056de: f023 0377 bic.w r3, r3, #119 @ 0x77
|
|
80056e2: 60bb str r3, [r7, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
80056e4: 68bb ldr r3, [r7, #8]
|
|
80056e6: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
80056ea: 60bb str r3, [r7, #8]
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80056ec: 687b ldr r3, [r7, #4]
|
|
80056ee: 681b ldr r3, [r3, #0]
|
|
80056f0: 68ba ldr r2, [r7, #8]
|
|
80056f2: 609a str r2, [r3, #8]
|
|
|
|
switch (sClockSourceConfig->ClockSource)
|
|
80056f4: 683b ldr r3, [r7, #0]
|
|
80056f6: 681b ldr r3, [r3, #0]
|
|
80056f8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
80056fc: d03e beq.n 800577c <HAL_TIM_ConfigClockSource+0xd4>
|
|
80056fe: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
|
|
8005702: f200 8087 bhi.w 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005706: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800570a: f000 8086 beq.w 800581a <HAL_TIM_ConfigClockSource+0x172>
|
|
800570e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005712: d87f bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005714: 2b70 cmp r3, #112 @ 0x70
|
|
8005716: d01a beq.n 800574e <HAL_TIM_ConfigClockSource+0xa6>
|
|
8005718: 2b70 cmp r3, #112 @ 0x70
|
|
800571a: d87b bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
800571c: 2b60 cmp r3, #96 @ 0x60
|
|
800571e: d050 beq.n 80057c2 <HAL_TIM_ConfigClockSource+0x11a>
|
|
8005720: 2b60 cmp r3, #96 @ 0x60
|
|
8005722: d877 bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005724: 2b50 cmp r3, #80 @ 0x50
|
|
8005726: d03c beq.n 80057a2 <HAL_TIM_ConfigClockSource+0xfa>
|
|
8005728: 2b50 cmp r3, #80 @ 0x50
|
|
800572a: d873 bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
800572c: 2b40 cmp r3, #64 @ 0x40
|
|
800572e: d058 beq.n 80057e2 <HAL_TIM_ConfigClockSource+0x13a>
|
|
8005730: 2b40 cmp r3, #64 @ 0x40
|
|
8005732: d86f bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005734: 2b30 cmp r3, #48 @ 0x30
|
|
8005736: d064 beq.n 8005802 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005738: 2b30 cmp r3, #48 @ 0x30
|
|
800573a: d86b bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
800573c: 2b20 cmp r3, #32
|
|
800573e: d060 beq.n 8005802 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005740: 2b20 cmp r3, #32
|
|
8005742: d867 bhi.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
8005744: 2b00 cmp r3, #0
|
|
8005746: d05c beq.n 8005802 <HAL_TIM_ConfigClockSource+0x15a>
|
|
8005748: 2b10 cmp r3, #16
|
|
800574a: d05a beq.n 8005802 <HAL_TIM_ConfigClockSource+0x15a>
|
|
800574c: e062 b.n 8005814 <HAL_TIM_ConfigClockSource+0x16c>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800574e: 687b ldr r3, [r7, #4]
|
|
8005750: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005752: 683b ldr r3, [r7, #0]
|
|
8005754: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005756: 683b ldr r3, [r7, #0]
|
|
8005758: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
800575a: 683b ldr r3, [r7, #0]
|
|
800575c: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800575e: f000 f9b3 bl 8005ac8 <TIM_ETR_SetConfig>
|
|
|
|
/* Select the External clock mode1 and the ETRF trigger */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005762: 687b ldr r3, [r7, #4]
|
|
8005764: 681b ldr r3, [r3, #0]
|
|
8005766: 689b ldr r3, [r3, #8]
|
|
8005768: 60bb str r3, [r7, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
800576a: 68bb ldr r3, [r7, #8]
|
|
800576c: f043 0377 orr.w r3, r3, #119 @ 0x77
|
|
8005770: 60bb str r3, [r7, #8]
|
|
/* Write to TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005772: 687b ldr r3, [r7, #4]
|
|
8005774: 681b ldr r3, [r3, #0]
|
|
8005776: 68ba ldr r2, [r7, #8]
|
|
8005778: 609a str r2, [r3, #8]
|
|
break;
|
|
800577a: e04f b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
/* Configure the ETR Clock source */
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800577c: 687b ldr r3, [r7, #4]
|
|
800577e: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPrescaler,
|
|
8005780: 683b ldr r3, [r7, #0]
|
|
8005782: 6899 ldr r1, [r3, #8]
|
|
sClockSourceConfig->ClockPolarity,
|
|
8005784: 683b ldr r3, [r7, #0]
|
|
8005786: 685a ldr r2, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8005788: 683b ldr r3, [r7, #0]
|
|
800578a: 68db ldr r3, [r3, #12]
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
800578c: f000 f99c bl 8005ac8 <TIM_ETR_SetConfig>
|
|
/* Enable the External clock mode2 */
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
8005790: 687b ldr r3, [r7, #4]
|
|
8005792: 681b ldr r3, [r3, #0]
|
|
8005794: 689a ldr r2, [r3, #8]
|
|
8005796: 687b ldr r3, [r7, #4]
|
|
8005798: 681b ldr r3, [r3, #0]
|
|
800579a: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
800579e: 609a str r2, [r3, #8]
|
|
break;
|
|
80057a0: e03c b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057a2: 687b ldr r3, [r7, #4]
|
|
80057a4: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057a6: 683b ldr r3, [r7, #0]
|
|
80057a8: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057aa: 683b ldr r3, [r7, #0]
|
|
80057ac: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057ae: 461a mov r2, r3
|
|
80057b0: f000 f910 bl 80059d4 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
|
|
80057b4: 687b ldr r3, [r7, #4]
|
|
80057b6: 681b ldr r3, [r3, #0]
|
|
80057b8: 2150 movs r1, #80 @ 0x50
|
|
80057ba: 4618 mov r0, r3
|
|
80057bc: f000 f969 bl 8005a92 <TIM_ITRx_SetConfig>
|
|
break;
|
|
80057c0: e02c b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI2 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80057c2: 687b ldr r3, [r7, #4]
|
|
80057c4: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057c6: 683b ldr r3, [r7, #0]
|
|
80057c8: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057ca: 683b ldr r3, [r7, #0]
|
|
80057cc: 68db ldr r3, [r3, #12]
|
|
TIM_TI2_ConfigInputStage(htim->Instance,
|
|
80057ce: 461a mov r2, r3
|
|
80057d0: f000 f92f bl 8005a32 <TIM_TI2_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
|
|
80057d4: 687b ldr r3, [r7, #4]
|
|
80057d6: 681b ldr r3, [r3, #0]
|
|
80057d8: 2160 movs r1, #96 @ 0x60
|
|
80057da: 4618 mov r0, r3
|
|
80057dc: f000 f959 bl 8005a92 <TIM_ITRx_SetConfig>
|
|
break;
|
|
80057e0: e01c b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
|
|
/* Check TI1 input conditioning related parameters */
|
|
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
|
|
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
|
|
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057e2: 687b ldr r3, [r7, #4]
|
|
80057e4: 6818 ldr r0, [r3, #0]
|
|
sClockSourceConfig->ClockPolarity,
|
|
80057e6: 683b ldr r3, [r7, #0]
|
|
80057e8: 6859 ldr r1, [r3, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80057ea: 683b ldr r3, [r7, #0]
|
|
80057ec: 68db ldr r3, [r3, #12]
|
|
TIM_TI1_ConfigInputStage(htim->Instance,
|
|
80057ee: 461a mov r2, r3
|
|
80057f0: f000 f8f0 bl 80059d4 <TIM_TI1_ConfigInputStage>
|
|
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
|
|
80057f4: 687b ldr r3, [r7, #4]
|
|
80057f6: 681b ldr r3, [r3, #0]
|
|
80057f8: 2140 movs r1, #64 @ 0x40
|
|
80057fa: 4618 mov r0, r3
|
|
80057fc: f000 f949 bl 8005a92 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005800: e00c b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
case TIM_CLOCKSOURCE_ITR3:
|
|
{
|
|
/* Check whether or not the timer instance supports internal trigger input */
|
|
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
|
|
|
|
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
|
|
8005802: 687b ldr r3, [r7, #4]
|
|
8005804: 681a ldr r2, [r3, #0]
|
|
8005806: 683b ldr r3, [r7, #0]
|
|
8005808: 681b ldr r3, [r3, #0]
|
|
800580a: 4619 mov r1, r3
|
|
800580c: 4610 mov r0, r2
|
|
800580e: f000 f940 bl 8005a92 <TIM_ITRx_SetConfig>
|
|
break;
|
|
8005812: e003 b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
}
|
|
|
|
default:
|
|
status = HAL_ERROR;
|
|
8005814: 2301 movs r3, #1
|
|
8005816: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8005818: e000 b.n 800581c <HAL_TIM_ConfigClockSource+0x174>
|
|
break;
|
|
800581a: bf00 nop
|
|
}
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800581c: 687b ldr r3, [r7, #4]
|
|
800581e: 2201 movs r2, #1
|
|
8005820: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005824: 687b ldr r3, [r7, #4]
|
|
8005826: 2200 movs r2, #0
|
|
8005828: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return status;
|
|
800582c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800582e: 4618 mov r0, r3
|
|
8005830: 3710 adds r7, #16
|
|
8005832: 46bd mov sp, r7
|
|
8005834: bd80 pop {r7, pc}
|
|
|
|
08005836 <HAL_TIM_OC_DelayElapsedCallback>:
|
|
* @brief Output Compare callback in non-blocking mode
|
|
* @param htim TIM OC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005836: b480 push {r7}
|
|
8005838: b083 sub sp, #12
|
|
800583a: af00 add r7, sp, #0
|
|
800583c: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800583e: bf00 nop
|
|
8005840: 370c adds r7, #12
|
|
8005842: 46bd mov sp, r7
|
|
8005844: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005848: 4770 bx lr
|
|
|
|
0800584a <HAL_TIM_IC_CaptureCallback>:
|
|
* @brief Input Capture callback in non-blocking mode
|
|
* @param htim TIM IC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800584a: b480 push {r7}
|
|
800584c: b083 sub sp, #12
|
|
800584e: af00 add r7, sp, #0
|
|
8005850: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005852: bf00 nop
|
|
8005854: 370c adds r7, #12
|
|
8005856: 46bd mov sp, r7
|
|
8005858: f85d 7b04 ldr.w r7, [sp], #4
|
|
800585c: 4770 bx lr
|
|
|
|
0800585e <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
* @brief PWM Pulse finished callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
800585e: b480 push {r7}
|
|
8005860: b083 sub sp, #12
|
|
8005862: af00 add r7, sp, #0
|
|
8005864: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005866: bf00 nop
|
|
8005868: 370c adds r7, #12
|
|
800586a: 46bd mov sp, r7
|
|
800586c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005870: 4770 bx lr
|
|
|
|
08005872 <HAL_TIM_TriggerCallback>:
|
|
* @brief Hall Trigger detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005872: b480 push {r7}
|
|
8005874: b083 sub sp, #12
|
|
8005876: af00 add r7, sp, #0
|
|
8005878: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIM_TriggerCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
800587a: bf00 nop
|
|
800587c: 370c adds r7, #12
|
|
800587e: 46bd mov sp, r7
|
|
8005880: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005884: 4770 bx lr
|
|
...
|
|
|
|
08005888 <TIM_Base_SetConfig>:
|
|
* @param TIMx TIM peripheral
|
|
* @param Structure TIM Base configuration structure
|
|
* @retval None
|
|
*/
|
|
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
|
|
{
|
|
8005888: b480 push {r7}
|
|
800588a: b085 sub sp, #20
|
|
800588c: af00 add r7, sp, #0
|
|
800588e: 6078 str r0, [r7, #4]
|
|
8005890: 6039 str r1, [r7, #0]
|
|
uint32_t tmpcr1;
|
|
tmpcr1 = TIMx->CR1;
|
|
8005892: 687b ldr r3, [r7, #4]
|
|
8005894: 681b ldr r3, [r3, #0]
|
|
8005896: 60fb str r3, [r7, #12]
|
|
|
|
/* Set TIM Time Base Unit parameters ---------------------------------------*/
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8005898: 687b ldr r3, [r7, #4]
|
|
800589a: 4a43 ldr r2, [pc, #268] @ (80059a8 <TIM_Base_SetConfig+0x120>)
|
|
800589c: 4293 cmp r3, r2
|
|
800589e: d013 beq.n 80058c8 <TIM_Base_SetConfig+0x40>
|
|
80058a0: 687b ldr r3, [r7, #4]
|
|
80058a2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80058a6: d00f beq.n 80058c8 <TIM_Base_SetConfig+0x40>
|
|
80058a8: 687b ldr r3, [r7, #4]
|
|
80058aa: 4a40 ldr r2, [pc, #256] @ (80059ac <TIM_Base_SetConfig+0x124>)
|
|
80058ac: 4293 cmp r3, r2
|
|
80058ae: d00b beq.n 80058c8 <TIM_Base_SetConfig+0x40>
|
|
80058b0: 687b ldr r3, [r7, #4]
|
|
80058b2: 4a3f ldr r2, [pc, #252] @ (80059b0 <TIM_Base_SetConfig+0x128>)
|
|
80058b4: 4293 cmp r3, r2
|
|
80058b6: d007 beq.n 80058c8 <TIM_Base_SetConfig+0x40>
|
|
80058b8: 687b ldr r3, [r7, #4]
|
|
80058ba: 4a3e ldr r2, [pc, #248] @ (80059b4 <TIM_Base_SetConfig+0x12c>)
|
|
80058bc: 4293 cmp r3, r2
|
|
80058be: d003 beq.n 80058c8 <TIM_Base_SetConfig+0x40>
|
|
80058c0: 687b ldr r3, [r7, #4]
|
|
80058c2: 4a3d ldr r2, [pc, #244] @ (80059b8 <TIM_Base_SetConfig+0x130>)
|
|
80058c4: 4293 cmp r3, r2
|
|
80058c6: d108 bne.n 80058da <TIM_Base_SetConfig+0x52>
|
|
{
|
|
/* Select the Counter Mode */
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
80058c8: 68fb ldr r3, [r7, #12]
|
|
80058ca: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
80058ce: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= Structure->CounterMode;
|
|
80058d0: 683b ldr r3, [r7, #0]
|
|
80058d2: 685b ldr r3, [r3, #4]
|
|
80058d4: 68fa ldr r2, [r7, #12]
|
|
80058d6: 4313 orrs r3, r2
|
|
80058d8: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
80058da: 687b ldr r3, [r7, #4]
|
|
80058dc: 4a32 ldr r2, [pc, #200] @ (80059a8 <TIM_Base_SetConfig+0x120>)
|
|
80058de: 4293 cmp r3, r2
|
|
80058e0: d02b beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
80058e2: 687b ldr r3, [r7, #4]
|
|
80058e4: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
80058e8: d027 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
80058ea: 687b ldr r3, [r7, #4]
|
|
80058ec: 4a2f ldr r2, [pc, #188] @ (80059ac <TIM_Base_SetConfig+0x124>)
|
|
80058ee: 4293 cmp r3, r2
|
|
80058f0: d023 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
80058f2: 687b ldr r3, [r7, #4]
|
|
80058f4: 4a2e ldr r2, [pc, #184] @ (80059b0 <TIM_Base_SetConfig+0x128>)
|
|
80058f6: 4293 cmp r3, r2
|
|
80058f8: d01f beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
80058fa: 687b ldr r3, [r7, #4]
|
|
80058fc: 4a2d ldr r2, [pc, #180] @ (80059b4 <TIM_Base_SetConfig+0x12c>)
|
|
80058fe: 4293 cmp r3, r2
|
|
8005900: d01b beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
8005902: 687b ldr r3, [r7, #4]
|
|
8005904: 4a2c ldr r2, [pc, #176] @ (80059b8 <TIM_Base_SetConfig+0x130>)
|
|
8005906: 4293 cmp r3, r2
|
|
8005908: d017 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
800590a: 687b ldr r3, [r7, #4]
|
|
800590c: 4a2b ldr r2, [pc, #172] @ (80059bc <TIM_Base_SetConfig+0x134>)
|
|
800590e: 4293 cmp r3, r2
|
|
8005910: d013 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
8005912: 687b ldr r3, [r7, #4]
|
|
8005914: 4a2a ldr r2, [pc, #168] @ (80059c0 <TIM_Base_SetConfig+0x138>)
|
|
8005916: 4293 cmp r3, r2
|
|
8005918: d00f beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
800591a: 687b ldr r3, [r7, #4]
|
|
800591c: 4a29 ldr r2, [pc, #164] @ (80059c4 <TIM_Base_SetConfig+0x13c>)
|
|
800591e: 4293 cmp r3, r2
|
|
8005920: d00b beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
8005922: 687b ldr r3, [r7, #4]
|
|
8005924: 4a28 ldr r2, [pc, #160] @ (80059c8 <TIM_Base_SetConfig+0x140>)
|
|
8005926: 4293 cmp r3, r2
|
|
8005928: d007 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
800592a: 687b ldr r3, [r7, #4]
|
|
800592c: 4a27 ldr r2, [pc, #156] @ (80059cc <TIM_Base_SetConfig+0x144>)
|
|
800592e: 4293 cmp r3, r2
|
|
8005930: d003 beq.n 800593a <TIM_Base_SetConfig+0xb2>
|
|
8005932: 687b ldr r3, [r7, #4]
|
|
8005934: 4a26 ldr r2, [pc, #152] @ (80059d0 <TIM_Base_SetConfig+0x148>)
|
|
8005936: 4293 cmp r3, r2
|
|
8005938: d108 bne.n 800594c <TIM_Base_SetConfig+0xc4>
|
|
{
|
|
/* Set the clock division */
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
800593a: 68fb ldr r3, [r7, #12]
|
|
800593c: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8005940: 60fb str r3, [r7, #12]
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8005942: 683b ldr r3, [r7, #0]
|
|
8005944: 68db ldr r3, [r3, #12]
|
|
8005946: 68fa ldr r2, [r7, #12]
|
|
8005948: 4313 orrs r3, r2
|
|
800594a: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
/* Set the auto-reload preload */
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
800594c: 68fb ldr r3, [r7, #12]
|
|
800594e: f023 0280 bic.w r2, r3, #128 @ 0x80
|
|
8005952: 683b ldr r3, [r7, #0]
|
|
8005954: 695b ldr r3, [r3, #20]
|
|
8005956: 4313 orrs r3, r2
|
|
8005958: 60fb str r3, [r7, #12]
|
|
|
|
/* Set the Autoreload value */
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
800595a: 683b ldr r3, [r7, #0]
|
|
800595c: 689a ldr r2, [r3, #8]
|
|
800595e: 687b ldr r3, [r7, #4]
|
|
8005960: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Set the Prescaler value */
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8005962: 683b ldr r3, [r7, #0]
|
|
8005964: 681a ldr r2, [r3, #0]
|
|
8005966: 687b ldr r3, [r7, #4]
|
|
8005968: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
800596a: 687b ldr r3, [r7, #4]
|
|
800596c: 4a0e ldr r2, [pc, #56] @ (80059a8 <TIM_Base_SetConfig+0x120>)
|
|
800596e: 4293 cmp r3, r2
|
|
8005970: d003 beq.n 800597a <TIM_Base_SetConfig+0xf2>
|
|
8005972: 687b ldr r3, [r7, #4]
|
|
8005974: 4a10 ldr r2, [pc, #64] @ (80059b8 <TIM_Base_SetConfig+0x130>)
|
|
8005976: 4293 cmp r3, r2
|
|
8005978: d103 bne.n 8005982 <TIM_Base_SetConfig+0xfa>
|
|
{
|
|
/* Set the Repetition Counter value */
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
800597a: 683b ldr r3, [r7, #0]
|
|
800597c: 691a ldr r2, [r3, #16]
|
|
800597e: 687b ldr r3, [r7, #4]
|
|
8005980: 631a str r2, [r3, #48] @ 0x30
|
|
}
|
|
|
|
/* Disable Update Event (UEV) with Update Generation (UG)
|
|
by changing Update Request Source (URS) to avoid Update flag (UIF) */
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
8005982: 687b ldr r3, [r7, #4]
|
|
8005984: 681b ldr r3, [r3, #0]
|
|
8005986: f043 0204 orr.w r2, r3, #4
|
|
800598a: 687b ldr r3, [r7, #4]
|
|
800598c: 601a str r2, [r3, #0]
|
|
|
|
/* Generate an update event to reload the Prescaler
|
|
and the repetition counter (only for advanced timer) value immediately */
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
800598e: 687b ldr r3, [r7, #4]
|
|
8005990: 2201 movs r2, #1
|
|
8005992: 615a str r2, [r3, #20]
|
|
|
|
TIMx->CR1 = tmpcr1;
|
|
8005994: 687b ldr r3, [r7, #4]
|
|
8005996: 68fa ldr r2, [r7, #12]
|
|
8005998: 601a str r2, [r3, #0]
|
|
}
|
|
800599a: bf00 nop
|
|
800599c: 3714 adds r7, #20
|
|
800599e: 46bd mov sp, r7
|
|
80059a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80059a4: 4770 bx lr
|
|
80059a6: bf00 nop
|
|
80059a8: 40010000 .word 0x40010000
|
|
80059ac: 40000400 .word 0x40000400
|
|
80059b0: 40000800 .word 0x40000800
|
|
80059b4: 40000c00 .word 0x40000c00
|
|
80059b8: 40010400 .word 0x40010400
|
|
80059bc: 40014000 .word 0x40014000
|
|
80059c0: 40014400 .word 0x40014400
|
|
80059c4: 40014800 .word 0x40014800
|
|
80059c8: 40001800 .word 0x40001800
|
|
80059cc: 40001c00 .word 0x40001c00
|
|
80059d0: 40002000 .word 0x40002000
|
|
|
|
080059d4 <TIM_TI1_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
80059d4: b480 push {r7}
|
|
80059d6: b087 sub sp, #28
|
|
80059d8: af00 add r7, sp, #0
|
|
80059da: 60f8 str r0, [r7, #12]
|
|
80059dc: 60b9 str r1, [r7, #8]
|
|
80059de: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
80059e0: 68fb ldr r3, [r7, #12]
|
|
80059e2: 6a1b ldr r3, [r3, #32]
|
|
80059e4: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80059e6: 68fb ldr r3, [r7, #12]
|
|
80059e8: 6a1b ldr r3, [r3, #32]
|
|
80059ea: f023 0201 bic.w r2, r3, #1
|
|
80059ee: 68fb ldr r3, [r7, #12]
|
|
80059f0: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
80059f2: 68fb ldr r3, [r7, #12]
|
|
80059f4: 699b ldr r3, [r3, #24]
|
|
80059f6: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
80059f8: 693b ldr r3, [r7, #16]
|
|
80059fa: f023 03f0 bic.w r3, r3, #240 @ 0xf0
|
|
80059fe: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8005a00: 687b ldr r3, [r7, #4]
|
|
8005a02: 011b lsls r3, r3, #4
|
|
8005a04: 693a ldr r2, [r7, #16]
|
|
8005a06: 4313 orrs r3, r2
|
|
8005a08: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC1E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
8005a0a: 697b ldr r3, [r7, #20]
|
|
8005a0c: f023 030a bic.w r3, r3, #10
|
|
8005a10: 617b str r3, [r7, #20]
|
|
tmpccer |= TIM_ICPolarity;
|
|
8005a12: 697a ldr r2, [r7, #20]
|
|
8005a14: 68bb ldr r3, [r7, #8]
|
|
8005a16: 4313 orrs r3, r2
|
|
8005a18: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
8005a1a: 68fb ldr r3, [r7, #12]
|
|
8005a1c: 693a ldr r2, [r7, #16]
|
|
8005a1e: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8005a20: 68fb ldr r3, [r7, #12]
|
|
8005a22: 697a ldr r2, [r7, #20]
|
|
8005a24: 621a str r2, [r3, #32]
|
|
}
|
|
8005a26: bf00 nop
|
|
8005a28: 371c adds r7, #28
|
|
8005a2a: 46bd mov sp, r7
|
|
8005a2c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a30: 4770 bx lr
|
|
|
|
08005a32 <TIM_TI2_ConfigInputStage>:
|
|
* @param TIM_ICFilter Specifies the Input Capture Filter.
|
|
* This parameter must be a value between 0x00 and 0x0F.
|
|
* @retval None
|
|
*/
|
|
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
|
|
{
|
|
8005a32: b480 push {r7}
|
|
8005a34: b087 sub sp, #28
|
|
8005a36: af00 add r7, sp, #0
|
|
8005a38: 60f8 str r0, [r7, #12]
|
|
8005a3a: 60b9 str r1, [r7, #8]
|
|
8005a3c: 607a str r2, [r7, #4]
|
|
uint32_t tmpccmr1;
|
|
uint32_t tmpccer;
|
|
|
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
|
tmpccer = TIMx->CCER;
|
|
8005a3e: 68fb ldr r3, [r7, #12]
|
|
8005a40: 6a1b ldr r3, [r3, #32]
|
|
8005a42: 617b str r3, [r7, #20]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8005a44: 68fb ldr r3, [r7, #12]
|
|
8005a46: 6a1b ldr r3, [r3, #32]
|
|
8005a48: f023 0210 bic.w r2, r3, #16
|
|
8005a4c: 68fb ldr r3, [r7, #12]
|
|
8005a4e: 621a str r2, [r3, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8005a50: 68fb ldr r3, [r7, #12]
|
|
8005a52: 699b ldr r3, [r3, #24]
|
|
8005a54: 613b str r3, [r7, #16]
|
|
|
|
/* Set the filter */
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
8005a56: 693b ldr r3, [r7, #16]
|
|
8005a58: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
8005a5c: 613b str r3, [r7, #16]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
8005a5e: 687b ldr r3, [r7, #4]
|
|
8005a60: 031b lsls r3, r3, #12
|
|
8005a62: 693a ldr r2, [r7, #16]
|
|
8005a64: 4313 orrs r3, r2
|
|
8005a66: 613b str r3, [r7, #16]
|
|
|
|
/* Select the Polarity and set the CC2E Bit */
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
8005a68: 697b ldr r3, [r7, #20]
|
|
8005a6a: f023 03a0 bic.w r3, r3, #160 @ 0xa0
|
|
8005a6e: 617b str r3, [r7, #20]
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8005a70: 68bb ldr r3, [r7, #8]
|
|
8005a72: 011b lsls r3, r3, #4
|
|
8005a74: 697a ldr r2, [r7, #20]
|
|
8005a76: 4313 orrs r3, r2
|
|
8005a78: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx CCMR1 and CCER registers */
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
8005a7a: 68fb ldr r3, [r7, #12]
|
|
8005a7c: 693a ldr r2, [r7, #16]
|
|
8005a7e: 619a str r2, [r3, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8005a80: 68fb ldr r3, [r7, #12]
|
|
8005a82: 697a ldr r2, [r7, #20]
|
|
8005a84: 621a str r2, [r3, #32]
|
|
}
|
|
8005a86: bf00 nop
|
|
8005a88: 371c adds r7, #28
|
|
8005a8a: 46bd mov sp, r7
|
|
8005a8c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005a90: 4770 bx lr
|
|
|
|
08005a92 <TIM_ITRx_SetConfig>:
|
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
|
* @arg TIM_TS_ETRF: External Trigger input
|
|
* @retval None
|
|
*/
|
|
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
|
|
{
|
|
8005a92: b480 push {r7}
|
|
8005a94: b085 sub sp, #20
|
|
8005a96: af00 add r7, sp, #0
|
|
8005a98: 6078 str r0, [r7, #4]
|
|
8005a9a: 6039 str r1, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005a9c: 687b ldr r3, [r7, #4]
|
|
8005a9e: 689b ldr r3, [r3, #8]
|
|
8005aa0: 60fb str r3, [r7, #12]
|
|
/* Reset the TS Bits */
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8005aa2: 68fb ldr r3, [r7, #12]
|
|
8005aa4: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005aa8: 60fb str r3, [r7, #12]
|
|
/* Set the Input Trigger source and the slave mode*/
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8005aaa: 683a ldr r2, [r7, #0]
|
|
8005aac: 68fb ldr r3, [r7, #12]
|
|
8005aae: 4313 orrs r3, r2
|
|
8005ab0: f043 0307 orr.w r3, r3, #7
|
|
8005ab4: 60fb str r3, [r7, #12]
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005ab6: 687b ldr r3, [r7, #4]
|
|
8005ab8: 68fa ldr r2, [r7, #12]
|
|
8005aba: 609a str r2, [r3, #8]
|
|
}
|
|
8005abc: bf00 nop
|
|
8005abe: 3714 adds r7, #20
|
|
8005ac0: 46bd mov sp, r7
|
|
8005ac2: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005ac6: 4770 bx lr
|
|
|
|
08005ac8 <TIM_ETR_SetConfig>:
|
|
* This parameter must be a value between 0x00 and 0x0F
|
|
* @retval None
|
|
*/
|
|
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
|
|
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
|
|
{
|
|
8005ac8: b480 push {r7}
|
|
8005aca: b087 sub sp, #28
|
|
8005acc: af00 add r7, sp, #0
|
|
8005ace: 60f8 str r0, [r7, #12]
|
|
8005ad0: 60b9 str r1, [r7, #8]
|
|
8005ad2: 607a str r2, [r7, #4]
|
|
8005ad4: 603b str r3, [r7, #0]
|
|
uint32_t tmpsmcr;
|
|
|
|
tmpsmcr = TIMx->SMCR;
|
|
8005ad6: 68fb ldr r3, [r7, #12]
|
|
8005ad8: 689b ldr r3, [r3, #8]
|
|
8005ada: 617b str r3, [r7, #20]
|
|
|
|
/* Reset the ETR Bits */
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8005adc: 697b ldr r3, [r7, #20]
|
|
8005ade: f423 437f bic.w r3, r3, #65280 @ 0xff00
|
|
8005ae2: 617b str r3, [r7, #20]
|
|
|
|
/* Set the Prescaler, the Filter value and the Polarity */
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8005ae4: 683b ldr r3, [r7, #0]
|
|
8005ae6: 021a lsls r2, r3, #8
|
|
8005ae8: 687b ldr r3, [r7, #4]
|
|
8005aea: 431a orrs r2, r3
|
|
8005aec: 68bb ldr r3, [r7, #8]
|
|
8005aee: 4313 orrs r3, r2
|
|
8005af0: 697a ldr r2, [r7, #20]
|
|
8005af2: 4313 orrs r3, r2
|
|
8005af4: 617b str r3, [r7, #20]
|
|
|
|
/* Write to TIMx SMCR */
|
|
TIMx->SMCR = tmpsmcr;
|
|
8005af6: 68fb ldr r3, [r7, #12]
|
|
8005af8: 697a ldr r2, [r7, #20]
|
|
8005afa: 609a str r2, [r3, #8]
|
|
}
|
|
8005afc: bf00 nop
|
|
8005afe: 371c adds r7, #28
|
|
8005b00: 46bd mov sp, r7
|
|
8005b02: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005b06: 4770 bx lr
|
|
|
|
08005b08 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8005b08: b480 push {r7}
|
|
8005b0a: b085 sub sp, #20
|
|
8005b0c: af00 add r7, sp, #0
|
|
8005b0e: 6078 str r0, [r7, #4]
|
|
8005b10: 6039 str r1, [r7, #0]
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8005b12: 687b ldr r3, [r7, #4]
|
|
8005b14: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
|
|
8005b18: 2b01 cmp r3, #1
|
|
8005b1a: d101 bne.n 8005b20 <HAL_TIMEx_MasterConfigSynchronization+0x18>
|
|
8005b1c: 2302 movs r3, #2
|
|
8005b1e: e05a b.n 8005bd6 <HAL_TIMEx_MasterConfigSynchronization+0xce>
|
|
8005b20: 687b ldr r3, [r7, #4]
|
|
8005b22: 2201 movs r2, #1
|
|
8005b24: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8005b28: 687b ldr r3, [r7, #4]
|
|
8005b2a: 2202 movs r2, #2
|
|
8005b2c: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
8005b30: 687b ldr r3, [r7, #4]
|
|
8005b32: 681b ldr r3, [r3, #0]
|
|
8005b34: 685b ldr r3, [r3, #4]
|
|
8005b36: 60fb str r3, [r7, #12]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8005b38: 687b ldr r3, [r7, #4]
|
|
8005b3a: 681b ldr r3, [r3, #0]
|
|
8005b3c: 689b ldr r3, [r3, #8]
|
|
8005b3e: 60bb str r3, [r7, #8]
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
8005b40: 68fb ldr r3, [r7, #12]
|
|
8005b42: f023 0370 bic.w r3, r3, #112 @ 0x70
|
|
8005b46: 60fb str r3, [r7, #12]
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
8005b48: 683b ldr r3, [r7, #0]
|
|
8005b4a: 681b ldr r3, [r3, #0]
|
|
8005b4c: 68fa ldr r2, [r7, #12]
|
|
8005b4e: 4313 orrs r3, r2
|
|
8005b50: 60fb str r3, [r7, #12]
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
8005b52: 687b ldr r3, [r7, #4]
|
|
8005b54: 681b ldr r3, [r3, #0]
|
|
8005b56: 68fa ldr r2, [r7, #12]
|
|
8005b58: 605a str r2, [r3, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8005b5a: 687b ldr r3, [r7, #4]
|
|
8005b5c: 681b ldr r3, [r3, #0]
|
|
8005b5e: 4a21 ldr r2, [pc, #132] @ (8005be4 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
|
|
8005b60: 4293 cmp r3, r2
|
|
8005b62: d022 beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b64: 687b ldr r3, [r7, #4]
|
|
8005b66: 681b ldr r3, [r3, #0]
|
|
8005b68: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8005b6c: d01d beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b6e: 687b ldr r3, [r7, #4]
|
|
8005b70: 681b ldr r3, [r3, #0]
|
|
8005b72: 4a1d ldr r2, [pc, #116] @ (8005be8 <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
|
|
8005b74: 4293 cmp r3, r2
|
|
8005b76: d018 beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b78: 687b ldr r3, [r7, #4]
|
|
8005b7a: 681b ldr r3, [r3, #0]
|
|
8005b7c: 4a1b ldr r2, [pc, #108] @ (8005bec <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
|
|
8005b7e: 4293 cmp r3, r2
|
|
8005b80: d013 beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b82: 687b ldr r3, [r7, #4]
|
|
8005b84: 681b ldr r3, [r3, #0]
|
|
8005b86: 4a1a ldr r2, [pc, #104] @ (8005bf0 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
|
|
8005b88: 4293 cmp r3, r2
|
|
8005b8a: d00e beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b8c: 687b ldr r3, [r7, #4]
|
|
8005b8e: 681b ldr r3, [r3, #0]
|
|
8005b90: 4a18 ldr r2, [pc, #96] @ (8005bf4 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
|
|
8005b92: 4293 cmp r3, r2
|
|
8005b94: d009 beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005b96: 687b ldr r3, [r7, #4]
|
|
8005b98: 681b ldr r3, [r3, #0]
|
|
8005b9a: 4a17 ldr r2, [pc, #92] @ (8005bf8 <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
|
|
8005b9c: 4293 cmp r3, r2
|
|
8005b9e: d004 beq.n 8005baa <HAL_TIMEx_MasterConfigSynchronization+0xa2>
|
|
8005ba0: 687b ldr r3, [r7, #4]
|
|
8005ba2: 681b ldr r3, [r3, #0]
|
|
8005ba4: 4a15 ldr r2, [pc, #84] @ (8005bfc <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
|
|
8005ba6: 4293 cmp r3, r2
|
|
8005ba8: d10c bne.n 8005bc4 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
8005baa: 68bb ldr r3, [r7, #8]
|
|
8005bac: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005bb0: 60bb str r3, [r7, #8]
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
8005bb2: 683b ldr r3, [r7, #0]
|
|
8005bb4: 685b ldr r3, [r3, #4]
|
|
8005bb6: 68ba ldr r2, [r7, #8]
|
|
8005bb8: 4313 orrs r3, r2
|
|
8005bba: 60bb str r3, [r7, #8]
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8005bbc: 687b ldr r3, [r7, #4]
|
|
8005bbe: 681b ldr r3, [r3, #0]
|
|
8005bc0: 68ba ldr r2, [r7, #8]
|
|
8005bc2: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8005bc4: 687b ldr r3, [r7, #4]
|
|
8005bc6: 2201 movs r2, #1
|
|
8005bc8: f883 203d strb.w r2, [r3, #61] @ 0x3d
|
|
|
|
__HAL_UNLOCK(htim);
|
|
8005bcc: 687b ldr r3, [r7, #4]
|
|
8005bce: 2200 movs r2, #0
|
|
8005bd0: f883 203c strb.w r2, [r3, #60] @ 0x3c
|
|
|
|
return HAL_OK;
|
|
8005bd4: 2300 movs r3, #0
|
|
}
|
|
8005bd6: 4618 mov r0, r3
|
|
8005bd8: 3714 adds r7, #20
|
|
8005bda: 46bd mov sp, r7
|
|
8005bdc: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005be0: 4770 bx lr
|
|
8005be2: bf00 nop
|
|
8005be4: 40010000 .word 0x40010000
|
|
8005be8: 40000400 .word 0x40000400
|
|
8005bec: 40000800 .word 0x40000800
|
|
8005bf0: 40000c00 .word 0x40000c00
|
|
8005bf4: 40010400 .word 0x40010400
|
|
8005bf8: 40014000 .word 0x40014000
|
|
8005bfc: 40001800 .word 0x40001800
|
|
|
|
08005c00 <HAL_TIMEx_CommutCallback>:
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005c00: b480 push {r7}
|
|
8005c02: b083 sub sp, #12
|
|
8005c04: af00 add r7, sp, #0
|
|
8005c06: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_CommutCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005c08: bf00 nop
|
|
8005c0a: 370c adds r7, #12
|
|
8005c0c: 46bd mov sp, r7
|
|
8005c0e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c12: 4770 bx lr
|
|
|
|
08005c14 <HAL_TIMEx_BreakCallback>:
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
{
|
|
8005c14: b480 push {r7}
|
|
8005c16: b083 sub sp, #12
|
|
8005c18: af00 add r7, sp, #0
|
|
8005c1a: 6078 str r0, [r7, #4]
|
|
UNUSED(htim);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_TIMEx_BreakCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
8005c1c: bf00 nop
|
|
8005c1e: 370c adds r7, #12
|
|
8005c20: 46bd mov sp, r7
|
|
8005c22: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005c26: 4770 bx lr
|
|
|
|
08005c28 <HAL_UART_Init>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8005c28: b580 push {r7, lr}
|
|
8005c2a: b082 sub sp, #8
|
|
8005c2c: af00 add r7, sp, #0
|
|
8005c2e: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8005c30: 687b ldr r3, [r7, #4]
|
|
8005c32: 2b00 cmp r3, #0
|
|
8005c34: d101 bne.n 8005c3a <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8005c36: 2301 movs r3, #1
|
|
8005c38: e042 b.n 8005cc0 <HAL_UART_Init+0x98>
|
|
assert_param(IS_UART_INSTANCE(huart->Instance));
|
|
}
|
|
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
|
|
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8005c3a: 687b ldr r3, [r7, #4]
|
|
8005c3c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8005c40: b2db uxtb r3, r3
|
|
8005c42: 2b00 cmp r3, #0
|
|
8005c44: d106 bne.n 8005c54 <HAL_UART_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8005c46: 687b ldr r3, [r7, #4]
|
|
8005c48: 2200 movs r2, #0
|
|
8005c4a: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8005c4e: 6878 ldr r0, [r7, #4]
|
|
8005c50: f7fb faae bl 80011b0 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005c54: 687b ldr r3, [r7, #4]
|
|
8005c56: 2224 movs r2, #36 @ 0x24
|
|
8005c58: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the peripheral */
|
|
__HAL_UART_DISABLE(huart);
|
|
8005c5c: 687b ldr r3, [r7, #4]
|
|
8005c5e: 681b ldr r3, [r3, #0]
|
|
8005c60: 68da ldr r2, [r3, #12]
|
|
8005c62: 687b ldr r3, [r7, #4]
|
|
8005c64: 681b ldr r3, [r3, #0]
|
|
8005c66: f422 5200 bic.w r2, r2, #8192 @ 0x2000
|
|
8005c6a: 60da str r2, [r3, #12]
|
|
|
|
/* Set the UART Communication parameters */
|
|
UART_SetConfig(huart);
|
|
8005c6c: 6878 ldr r0, [r7, #4]
|
|
8005c6e: f000 f82b bl 8005cc8 <UART_SetConfig>
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8005c72: 687b ldr r3, [r7, #4]
|
|
8005c74: 681b ldr r3, [r3, #0]
|
|
8005c76: 691a ldr r2, [r3, #16]
|
|
8005c78: 687b ldr r3, [r7, #4]
|
|
8005c7a: 681b ldr r3, [r3, #0]
|
|
8005c7c: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8005c80: 611a str r2, [r3, #16]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8005c82: 687b ldr r3, [r7, #4]
|
|
8005c84: 681b ldr r3, [r3, #0]
|
|
8005c86: 695a ldr r2, [r3, #20]
|
|
8005c88: 687b ldr r3, [r7, #4]
|
|
8005c8a: 681b ldr r3, [r3, #0]
|
|
8005c8c: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8005c90: 615a str r2, [r3, #20]
|
|
|
|
/* Enable the peripheral */
|
|
__HAL_UART_ENABLE(huart);
|
|
8005c92: 687b ldr r3, [r7, #4]
|
|
8005c94: 681b ldr r3, [r3, #0]
|
|
8005c96: 68da ldr r2, [r3, #12]
|
|
8005c98: 687b ldr r3, [r7, #4]
|
|
8005c9a: 681b ldr r3, [r3, #0]
|
|
8005c9c: f442 5200 orr.w r2, r2, #8192 @ 0x2000
|
|
8005ca0: 60da str r2, [r3, #12]
|
|
|
|
/* Initialize the UART state */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005ca2: 687b ldr r3, [r7, #4]
|
|
8005ca4: 2200 movs r2, #0
|
|
8005ca6: 645a str r2, [r3, #68] @ 0x44
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005ca8: 687b ldr r3, [r7, #4]
|
|
8005caa: 2220 movs r2, #32
|
|
8005cac: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005cb0: 687b ldr r3, [r7, #4]
|
|
8005cb2: 2220 movs r2, #32
|
|
8005cb4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005cb8: 687b ldr r3, [r7, #4]
|
|
8005cba: 2200 movs r2, #0
|
|
8005cbc: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
return HAL_OK;
|
|
8005cbe: 2300 movs r3, #0
|
|
}
|
|
8005cc0: 4618 mov r0, r3
|
|
8005cc2: 3708 adds r7, #8
|
|
8005cc4: 46bd mov sp, r7
|
|
8005cc6: bd80 pop {r7, pc}
|
|
|
|
08005cc8 <UART_SetConfig>:
|
|
* @param huart Pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005cc8: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8005ccc: b0c0 sub sp, #256 @ 0x100
|
|
8005cce: af00 add r7, sp, #0
|
|
8005cd0: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
|
|
assert_param(IS_UART_MODE(huart->Init.Mode));
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits
|
|
according to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8005cd4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005cd8: 681b ldr r3, [r3, #0]
|
|
8005cda: 691b ldr r3, [r3, #16]
|
|
8005cdc: f423 5040 bic.w r0, r3, #12288 @ 0x3000
|
|
8005ce0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005ce4: 68d9 ldr r1, [r3, #12]
|
|
8005ce6: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005cea: 681a ldr r2, [r3, #0]
|
|
8005cec: ea40 0301 orr.w r3, r0, r1
|
|
8005cf0: 6113 str r3, [r2, #16]
|
|
Set the M bits according to huart->Init.WordLength value
|
|
Set PCE and PS bits according to huart->Init.Parity value
|
|
Set TE and RE bits according to huart->Init.Mode value
|
|
Set OVER8 bit according to huart->Init.OverSampling value */
|
|
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
|
|
8005cf2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005cf6: 689a ldr r2, [r3, #8]
|
|
8005cf8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005cfc: 691b ldr r3, [r3, #16]
|
|
8005cfe: 431a orrs r2, r3
|
|
8005d00: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d04: 695b ldr r3, [r3, #20]
|
|
8005d06: 431a orrs r2, r3
|
|
8005d08: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d0c: 69db ldr r3, [r3, #28]
|
|
8005d0e: 4313 orrs r3, r2
|
|
8005d10: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
|
|
MODIFY_REG(huart->Instance->CR1,
|
|
8005d14: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d18: 681b ldr r3, [r3, #0]
|
|
8005d1a: 68db ldr r3, [r3, #12]
|
|
8005d1c: f423 4116 bic.w r1, r3, #38400 @ 0x9600
|
|
8005d20: f021 010c bic.w r1, r1, #12
|
|
8005d24: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d28: 681a ldr r2, [r3, #0]
|
|
8005d2a: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
|
|
8005d2e: 430b orrs r3, r1
|
|
8005d30: 60d3 str r3, [r2, #12]
|
|
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
|
tmpreg);
|
|
|
|
/*-------------------------- USART CR3 Configuration -----------------------*/
|
|
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
|
|
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
|
|
8005d32: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d36: 681b ldr r3, [r3, #0]
|
|
8005d38: 695b ldr r3, [r3, #20]
|
|
8005d3a: f423 7040 bic.w r0, r3, #768 @ 0x300
|
|
8005d3e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d42: 6999 ldr r1, [r3, #24]
|
|
8005d44: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d48: 681a ldr r2, [r3, #0]
|
|
8005d4a: ea40 0301 orr.w r3, r0, r1
|
|
8005d4e: 6153 str r3, [r2, #20]
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#elif defined(USART6)
|
|
if ((huart->Instance == USART1) || (huart->Instance == USART6))
|
|
8005d50: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d54: 681a ldr r2, [r3, #0]
|
|
8005d56: 4b8f ldr r3, [pc, #572] @ (8005f94 <UART_SetConfig+0x2cc>)
|
|
8005d58: 429a cmp r2, r3
|
|
8005d5a: d005 beq.n 8005d68 <UART_SetConfig+0xa0>
|
|
8005d5c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d60: 681a ldr r2, [r3, #0]
|
|
8005d62: 4b8d ldr r3, [pc, #564] @ (8005f98 <UART_SetConfig+0x2d0>)
|
|
8005d64: 429a cmp r2, r3
|
|
8005d66: d104 bne.n 8005d72 <UART_SetConfig+0xaa>
|
|
{
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005d68: f7ff f82c bl 8004dc4 <HAL_RCC_GetPCLK2Freq>
|
|
8005d6c: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
8005d70: e003 b.n 8005d7a <UART_SetConfig+0xb2>
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
}
|
|
#endif /* USART6 */
|
|
else
|
|
{
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005d72: f7ff f813 bl 8004d9c <HAL_RCC_GetPCLK1Freq>
|
|
8005d76: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
|
|
}
|
|
/*-------------------------- USART BRR Configuration ---------------------*/
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8005d7a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005d7e: 69db ldr r3, [r3, #28]
|
|
8005d80: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8005d84: f040 810c bne.w 8005fa0 <UART_SetConfig+0x2d8>
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
|
|
8005d88: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005d8c: 2200 movs r2, #0
|
|
8005d8e: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
|
|
8005d92: f8c7 20ec str.w r2, [r7, #236] @ 0xec
|
|
8005d96: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
|
|
8005d9a: 4622 mov r2, r4
|
|
8005d9c: 462b mov r3, r5
|
|
8005d9e: 1891 adds r1, r2, r2
|
|
8005da0: 65b9 str r1, [r7, #88] @ 0x58
|
|
8005da2: 415b adcs r3, r3
|
|
8005da4: 65fb str r3, [r7, #92] @ 0x5c
|
|
8005da6: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
|
|
8005daa: 4621 mov r1, r4
|
|
8005dac: eb12 0801 adds.w r8, r2, r1
|
|
8005db0: 4629 mov r1, r5
|
|
8005db2: eb43 0901 adc.w r9, r3, r1
|
|
8005db6: f04f 0200 mov.w r2, #0
|
|
8005dba: f04f 0300 mov.w r3, #0
|
|
8005dbe: ea4f 03c9 mov.w r3, r9, lsl #3
|
|
8005dc2: ea43 7358 orr.w r3, r3, r8, lsr #29
|
|
8005dc6: ea4f 02c8 mov.w r2, r8, lsl #3
|
|
8005dca: 4690 mov r8, r2
|
|
8005dcc: 4699 mov r9, r3
|
|
8005dce: 4623 mov r3, r4
|
|
8005dd0: eb18 0303 adds.w r3, r8, r3
|
|
8005dd4: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
8005dd8: 462b mov r3, r5
|
|
8005dda: eb49 0303 adc.w r3, r9, r3
|
|
8005dde: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
8005de2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005de6: 685b ldr r3, [r3, #4]
|
|
8005de8: 2200 movs r2, #0
|
|
8005dea: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
8005dee: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
|
|
8005df2: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
|
|
8005df6: 460b mov r3, r1
|
|
8005df8: 18db adds r3, r3, r3
|
|
8005dfa: 653b str r3, [r7, #80] @ 0x50
|
|
8005dfc: 4613 mov r3, r2
|
|
8005dfe: eb42 0303 adc.w r3, r2, r3
|
|
8005e02: 657b str r3, [r7, #84] @ 0x54
|
|
8005e04: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
|
|
8005e08: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
|
|
8005e0c: f7fa f9f0 bl 80001f0 <__aeabi_uldivmod>
|
|
8005e10: 4602 mov r2, r0
|
|
8005e12: 460b mov r3, r1
|
|
8005e14: 4b61 ldr r3, [pc, #388] @ (8005f9c <UART_SetConfig+0x2d4>)
|
|
8005e16: fba3 2302 umull r2, r3, r3, r2
|
|
8005e1a: 095b lsrs r3, r3, #5
|
|
8005e1c: 011c lsls r4, r3, #4
|
|
8005e1e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005e22: 2200 movs r2, #0
|
|
8005e24: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8005e28: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
|
|
8005e2c: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
|
|
8005e30: 4642 mov r2, r8
|
|
8005e32: 464b mov r3, r9
|
|
8005e34: 1891 adds r1, r2, r2
|
|
8005e36: 64b9 str r1, [r7, #72] @ 0x48
|
|
8005e38: 415b adcs r3, r3
|
|
8005e3a: 64fb str r3, [r7, #76] @ 0x4c
|
|
8005e3c: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
|
|
8005e40: 4641 mov r1, r8
|
|
8005e42: eb12 0a01 adds.w sl, r2, r1
|
|
8005e46: 4649 mov r1, r9
|
|
8005e48: eb43 0b01 adc.w fp, r3, r1
|
|
8005e4c: f04f 0200 mov.w r2, #0
|
|
8005e50: f04f 0300 mov.w r3, #0
|
|
8005e54: ea4f 03cb mov.w r3, fp, lsl #3
|
|
8005e58: ea43 735a orr.w r3, r3, sl, lsr #29
|
|
8005e5c: ea4f 02ca mov.w r2, sl, lsl #3
|
|
8005e60: 4692 mov sl, r2
|
|
8005e62: 469b mov fp, r3
|
|
8005e64: 4643 mov r3, r8
|
|
8005e66: eb1a 0303 adds.w r3, sl, r3
|
|
8005e6a: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
8005e6e: 464b mov r3, r9
|
|
8005e70: eb4b 0303 adc.w r3, fp, r3
|
|
8005e74: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
|
|
8005e78: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005e7c: 685b ldr r3, [r3, #4]
|
|
8005e7e: 2200 movs r2, #0
|
|
8005e80: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
8005e84: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
|
|
8005e88: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
|
|
8005e8c: 460b mov r3, r1
|
|
8005e8e: 18db adds r3, r3, r3
|
|
8005e90: 643b str r3, [r7, #64] @ 0x40
|
|
8005e92: 4613 mov r3, r2
|
|
8005e94: eb42 0303 adc.w r3, r2, r3
|
|
8005e98: 647b str r3, [r7, #68] @ 0x44
|
|
8005e9a: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
|
|
8005e9e: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
|
|
8005ea2: f7fa f9a5 bl 80001f0 <__aeabi_uldivmod>
|
|
8005ea6: 4602 mov r2, r0
|
|
8005ea8: 460b mov r3, r1
|
|
8005eaa: 4611 mov r1, r2
|
|
8005eac: 4b3b ldr r3, [pc, #236] @ (8005f9c <UART_SetConfig+0x2d4>)
|
|
8005eae: fba3 2301 umull r2, r3, r3, r1
|
|
8005eb2: 095b lsrs r3, r3, #5
|
|
8005eb4: 2264 movs r2, #100 @ 0x64
|
|
8005eb6: fb02 f303 mul.w r3, r2, r3
|
|
8005eba: 1acb subs r3, r1, r3
|
|
8005ebc: 00db lsls r3, r3, #3
|
|
8005ebe: f103 0232 add.w r2, r3, #50 @ 0x32
|
|
8005ec2: 4b36 ldr r3, [pc, #216] @ (8005f9c <UART_SetConfig+0x2d4>)
|
|
8005ec4: fba3 2302 umull r2, r3, r3, r2
|
|
8005ec8: 095b lsrs r3, r3, #5
|
|
8005eca: 005b lsls r3, r3, #1
|
|
8005ecc: f403 73f8 and.w r3, r3, #496 @ 0x1f0
|
|
8005ed0: 441c add r4, r3
|
|
8005ed2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005ed6: 2200 movs r2, #0
|
|
8005ed8: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8005edc: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
|
|
8005ee0: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
|
|
8005ee4: 4642 mov r2, r8
|
|
8005ee6: 464b mov r3, r9
|
|
8005ee8: 1891 adds r1, r2, r2
|
|
8005eea: 63b9 str r1, [r7, #56] @ 0x38
|
|
8005eec: 415b adcs r3, r3
|
|
8005eee: 63fb str r3, [r7, #60] @ 0x3c
|
|
8005ef0: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
|
|
8005ef4: 4641 mov r1, r8
|
|
8005ef6: 1851 adds r1, r2, r1
|
|
8005ef8: 6339 str r1, [r7, #48] @ 0x30
|
|
8005efa: 4649 mov r1, r9
|
|
8005efc: 414b adcs r3, r1
|
|
8005efe: 637b str r3, [r7, #52] @ 0x34
|
|
8005f00: f04f 0200 mov.w r2, #0
|
|
8005f04: f04f 0300 mov.w r3, #0
|
|
8005f08: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
|
|
8005f0c: 4659 mov r1, fp
|
|
8005f0e: 00cb lsls r3, r1, #3
|
|
8005f10: 4651 mov r1, sl
|
|
8005f12: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8005f16: 4651 mov r1, sl
|
|
8005f18: 00ca lsls r2, r1, #3
|
|
8005f1a: 4610 mov r0, r2
|
|
8005f1c: 4619 mov r1, r3
|
|
8005f1e: 4603 mov r3, r0
|
|
8005f20: 4642 mov r2, r8
|
|
8005f22: 189b adds r3, r3, r2
|
|
8005f24: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
8005f28: 464b mov r3, r9
|
|
8005f2a: 460a mov r2, r1
|
|
8005f2c: eb42 0303 adc.w r3, r2, r3
|
|
8005f30: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
8005f34: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005f38: 685b ldr r3, [r3, #4]
|
|
8005f3a: 2200 movs r2, #0
|
|
8005f3c: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
8005f40: f8c7 20ac str.w r2, [r7, #172] @ 0xac
|
|
8005f44: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
|
|
8005f48: 460b mov r3, r1
|
|
8005f4a: 18db adds r3, r3, r3
|
|
8005f4c: 62bb str r3, [r7, #40] @ 0x28
|
|
8005f4e: 4613 mov r3, r2
|
|
8005f50: eb42 0303 adc.w r3, r2, r3
|
|
8005f54: 62fb str r3, [r7, #44] @ 0x2c
|
|
8005f56: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
|
|
8005f5a: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
|
|
8005f5e: f7fa f947 bl 80001f0 <__aeabi_uldivmod>
|
|
8005f62: 4602 mov r2, r0
|
|
8005f64: 460b mov r3, r1
|
|
8005f66: 4b0d ldr r3, [pc, #52] @ (8005f9c <UART_SetConfig+0x2d4>)
|
|
8005f68: fba3 1302 umull r1, r3, r3, r2
|
|
8005f6c: 095b lsrs r3, r3, #5
|
|
8005f6e: 2164 movs r1, #100 @ 0x64
|
|
8005f70: fb01 f303 mul.w r3, r1, r3
|
|
8005f74: 1ad3 subs r3, r2, r3
|
|
8005f76: 00db lsls r3, r3, #3
|
|
8005f78: 3332 adds r3, #50 @ 0x32
|
|
8005f7a: 4a08 ldr r2, [pc, #32] @ (8005f9c <UART_SetConfig+0x2d4>)
|
|
8005f7c: fba2 2303 umull r2, r3, r2, r3
|
|
8005f80: 095b lsrs r3, r3, #5
|
|
8005f82: f003 0207 and.w r2, r3, #7
|
|
8005f86: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005f8a: 681b ldr r3, [r3, #0]
|
|
8005f8c: 4422 add r2, r4
|
|
8005f8e: 609a str r2, [r3, #8]
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
}
|
|
}
|
|
8005f90: e106 b.n 80061a0 <UART_SetConfig+0x4d8>
|
|
8005f92: bf00 nop
|
|
8005f94: 40011000 .word 0x40011000
|
|
8005f98: 40011400 .word 0x40011400
|
|
8005f9c: 51eb851f .word 0x51eb851f
|
|
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
|
|
8005fa0: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8005fa4: 2200 movs r2, #0
|
|
8005fa6: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
8005faa: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
|
|
8005fae: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
|
|
8005fb2: 4642 mov r2, r8
|
|
8005fb4: 464b mov r3, r9
|
|
8005fb6: 1891 adds r1, r2, r2
|
|
8005fb8: 6239 str r1, [r7, #32]
|
|
8005fba: 415b adcs r3, r3
|
|
8005fbc: 627b str r3, [r7, #36] @ 0x24
|
|
8005fbe: e9d7 2308 ldrd r2, r3, [r7, #32]
|
|
8005fc2: 4641 mov r1, r8
|
|
8005fc4: 1854 adds r4, r2, r1
|
|
8005fc6: 4649 mov r1, r9
|
|
8005fc8: eb43 0501 adc.w r5, r3, r1
|
|
8005fcc: f04f 0200 mov.w r2, #0
|
|
8005fd0: f04f 0300 mov.w r3, #0
|
|
8005fd4: 00eb lsls r3, r5, #3
|
|
8005fd6: ea43 7354 orr.w r3, r3, r4, lsr #29
|
|
8005fda: 00e2 lsls r2, r4, #3
|
|
8005fdc: 4614 mov r4, r2
|
|
8005fde: 461d mov r5, r3
|
|
8005fe0: 4643 mov r3, r8
|
|
8005fe2: 18e3 adds r3, r4, r3
|
|
8005fe4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
8005fe8: 464b mov r3, r9
|
|
8005fea: eb45 0303 adc.w r3, r5, r3
|
|
8005fee: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
8005ff2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8005ff6: 685b ldr r3, [r3, #4]
|
|
8005ff8: 2200 movs r2, #0
|
|
8005ffa: f8c7 3090 str.w r3, [r7, #144] @ 0x90
|
|
8005ffe: f8c7 2094 str.w r2, [r7, #148] @ 0x94
|
|
8006002: f04f 0200 mov.w r2, #0
|
|
8006006: f04f 0300 mov.w r3, #0
|
|
800600a: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
|
|
800600e: 4629 mov r1, r5
|
|
8006010: 008b lsls r3, r1, #2
|
|
8006012: 4621 mov r1, r4
|
|
8006014: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8006018: 4621 mov r1, r4
|
|
800601a: 008a lsls r2, r1, #2
|
|
800601c: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
|
|
8006020: f7fa f8e6 bl 80001f0 <__aeabi_uldivmod>
|
|
8006024: 4602 mov r2, r0
|
|
8006026: 460b mov r3, r1
|
|
8006028: 4b60 ldr r3, [pc, #384] @ (80061ac <UART_SetConfig+0x4e4>)
|
|
800602a: fba3 2302 umull r2, r3, r3, r2
|
|
800602e: 095b lsrs r3, r3, #5
|
|
8006030: 011c lsls r4, r3, #4
|
|
8006032: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
8006036: 2200 movs r2, #0
|
|
8006038: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
800603c: f8c7 208c str.w r2, [r7, #140] @ 0x8c
|
|
8006040: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
|
|
8006044: 4642 mov r2, r8
|
|
8006046: 464b mov r3, r9
|
|
8006048: 1891 adds r1, r2, r2
|
|
800604a: 61b9 str r1, [r7, #24]
|
|
800604c: 415b adcs r3, r3
|
|
800604e: 61fb str r3, [r7, #28]
|
|
8006050: e9d7 2306 ldrd r2, r3, [r7, #24]
|
|
8006054: 4641 mov r1, r8
|
|
8006056: 1851 adds r1, r2, r1
|
|
8006058: 6139 str r1, [r7, #16]
|
|
800605a: 4649 mov r1, r9
|
|
800605c: 414b adcs r3, r1
|
|
800605e: 617b str r3, [r7, #20]
|
|
8006060: f04f 0200 mov.w r2, #0
|
|
8006064: f04f 0300 mov.w r3, #0
|
|
8006068: e9d7 ab04 ldrd sl, fp, [r7, #16]
|
|
800606c: 4659 mov r1, fp
|
|
800606e: 00cb lsls r3, r1, #3
|
|
8006070: 4651 mov r1, sl
|
|
8006072: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
8006076: 4651 mov r1, sl
|
|
8006078: 00ca lsls r2, r1, #3
|
|
800607a: 4610 mov r0, r2
|
|
800607c: 4619 mov r1, r3
|
|
800607e: 4603 mov r3, r0
|
|
8006080: 4642 mov r2, r8
|
|
8006082: 189b adds r3, r3, r2
|
|
8006084: f8c7 3080 str.w r3, [r7, #128] @ 0x80
|
|
8006088: 464b mov r3, r9
|
|
800608a: 460a mov r2, r1
|
|
800608c: eb42 0303 adc.w r3, r2, r3
|
|
8006090: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
8006094: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006098: 685b ldr r3, [r3, #4]
|
|
800609a: 2200 movs r2, #0
|
|
800609c: 67bb str r3, [r7, #120] @ 0x78
|
|
800609e: 67fa str r2, [r7, #124] @ 0x7c
|
|
80060a0: f04f 0200 mov.w r2, #0
|
|
80060a4: f04f 0300 mov.w r3, #0
|
|
80060a8: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
|
|
80060ac: 4649 mov r1, r9
|
|
80060ae: 008b lsls r3, r1, #2
|
|
80060b0: 4641 mov r1, r8
|
|
80060b2: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
80060b6: 4641 mov r1, r8
|
|
80060b8: 008a lsls r2, r1, #2
|
|
80060ba: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
|
|
80060be: f7fa f897 bl 80001f0 <__aeabi_uldivmod>
|
|
80060c2: 4602 mov r2, r0
|
|
80060c4: 460b mov r3, r1
|
|
80060c6: 4611 mov r1, r2
|
|
80060c8: 4b38 ldr r3, [pc, #224] @ (80061ac <UART_SetConfig+0x4e4>)
|
|
80060ca: fba3 2301 umull r2, r3, r3, r1
|
|
80060ce: 095b lsrs r3, r3, #5
|
|
80060d0: 2264 movs r2, #100 @ 0x64
|
|
80060d2: fb02 f303 mul.w r3, r2, r3
|
|
80060d6: 1acb subs r3, r1, r3
|
|
80060d8: 011b lsls r3, r3, #4
|
|
80060da: 3332 adds r3, #50 @ 0x32
|
|
80060dc: 4a33 ldr r2, [pc, #204] @ (80061ac <UART_SetConfig+0x4e4>)
|
|
80060de: fba2 2303 umull r2, r3, r2, r3
|
|
80060e2: 095b lsrs r3, r3, #5
|
|
80060e4: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80060e8: 441c add r4, r3
|
|
80060ea: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
|
|
80060ee: 2200 movs r2, #0
|
|
80060f0: 673b str r3, [r7, #112] @ 0x70
|
|
80060f2: 677a str r2, [r7, #116] @ 0x74
|
|
80060f4: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
|
|
80060f8: 4642 mov r2, r8
|
|
80060fa: 464b mov r3, r9
|
|
80060fc: 1891 adds r1, r2, r2
|
|
80060fe: 60b9 str r1, [r7, #8]
|
|
8006100: 415b adcs r3, r3
|
|
8006102: 60fb str r3, [r7, #12]
|
|
8006104: e9d7 2302 ldrd r2, r3, [r7, #8]
|
|
8006108: 4641 mov r1, r8
|
|
800610a: 1851 adds r1, r2, r1
|
|
800610c: 6039 str r1, [r7, #0]
|
|
800610e: 4649 mov r1, r9
|
|
8006110: 414b adcs r3, r1
|
|
8006112: 607b str r3, [r7, #4]
|
|
8006114: f04f 0200 mov.w r2, #0
|
|
8006118: f04f 0300 mov.w r3, #0
|
|
800611c: e9d7 ab00 ldrd sl, fp, [r7]
|
|
8006120: 4659 mov r1, fp
|
|
8006122: 00cb lsls r3, r1, #3
|
|
8006124: 4651 mov r1, sl
|
|
8006126: ea43 7351 orr.w r3, r3, r1, lsr #29
|
|
800612a: 4651 mov r1, sl
|
|
800612c: 00ca lsls r2, r1, #3
|
|
800612e: 4610 mov r0, r2
|
|
8006130: 4619 mov r1, r3
|
|
8006132: 4603 mov r3, r0
|
|
8006134: 4642 mov r2, r8
|
|
8006136: 189b adds r3, r3, r2
|
|
8006138: 66bb str r3, [r7, #104] @ 0x68
|
|
800613a: 464b mov r3, r9
|
|
800613c: 460a mov r2, r1
|
|
800613e: eb42 0303 adc.w r3, r2, r3
|
|
8006142: 66fb str r3, [r7, #108] @ 0x6c
|
|
8006144: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
8006148: 685b ldr r3, [r3, #4]
|
|
800614a: 2200 movs r2, #0
|
|
800614c: 663b str r3, [r7, #96] @ 0x60
|
|
800614e: 667a str r2, [r7, #100] @ 0x64
|
|
8006150: f04f 0200 mov.w r2, #0
|
|
8006154: f04f 0300 mov.w r3, #0
|
|
8006158: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
|
|
800615c: 4649 mov r1, r9
|
|
800615e: 008b lsls r3, r1, #2
|
|
8006160: 4641 mov r1, r8
|
|
8006162: ea43 7391 orr.w r3, r3, r1, lsr #30
|
|
8006166: 4641 mov r1, r8
|
|
8006168: 008a lsls r2, r1, #2
|
|
800616a: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
|
|
800616e: f7fa f83f bl 80001f0 <__aeabi_uldivmod>
|
|
8006172: 4602 mov r2, r0
|
|
8006174: 460b mov r3, r1
|
|
8006176: 4b0d ldr r3, [pc, #52] @ (80061ac <UART_SetConfig+0x4e4>)
|
|
8006178: fba3 1302 umull r1, r3, r3, r2
|
|
800617c: 095b lsrs r3, r3, #5
|
|
800617e: 2164 movs r1, #100 @ 0x64
|
|
8006180: fb01 f303 mul.w r3, r1, r3
|
|
8006184: 1ad3 subs r3, r2, r3
|
|
8006186: 011b lsls r3, r3, #4
|
|
8006188: 3332 adds r3, #50 @ 0x32
|
|
800618a: 4a08 ldr r2, [pc, #32] @ (80061ac <UART_SetConfig+0x4e4>)
|
|
800618c: fba2 2303 umull r2, r3, r2, r3
|
|
8006190: 095b lsrs r3, r3, #5
|
|
8006192: f003 020f and.w r2, r3, #15
|
|
8006196: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
|
|
800619a: 681b ldr r3, [r3, #0]
|
|
800619c: 4422 add r2, r4
|
|
800619e: 609a str r2, [r3, #8]
|
|
}
|
|
80061a0: bf00 nop
|
|
80061a2: f507 7780 add.w r7, r7, #256 @ 0x100
|
|
80061a6: 46bd mov sp, r7
|
|
80061a8: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
80061ac: 51eb851f .word 0x51eb851f
|
|
|
|
080061b0 <FMC_SDRAM_Init>:
|
|
* @param Device Pointer to SDRAM device instance
|
|
* @param Init Pointer to SDRAM Initialization structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
|
|
{
|
|
80061b0: b480 push {r7}
|
|
80061b2: b083 sub sp, #12
|
|
80061b4: af00 add r7, sp, #0
|
|
80061b6: 6078 str r0, [r7, #4]
|
|
80061b8: 6039 str r1, [r7, #0]
|
|
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
|
|
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
|
|
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
|
|
|
|
/* Set SDRAM bank configuration parameters */
|
|
if (Init->SDBank == FMC_SDRAM_BANK1)
|
|
80061ba: 683b ldr r3, [r7, #0]
|
|
80061bc: 681b ldr r3, [r3, #0]
|
|
80061be: 2b00 cmp r3, #0
|
|
80061c0: d123 bne.n 800620a <FMC_SDRAM_Init+0x5a>
|
|
{
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
|
|
80061c2: 687b ldr r3, [r7, #4]
|
|
80061c4: 681b ldr r3, [r3, #0]
|
|
80061c6: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
80061ca: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
80061ce: 683a ldr r2, [r7, #0]
|
|
80061d0: 6851 ldr r1, [r2, #4]
|
|
80061d2: 683a ldr r2, [r7, #0]
|
|
80061d4: 6892 ldr r2, [r2, #8]
|
|
80061d6: 4311 orrs r1, r2
|
|
80061d8: 683a ldr r2, [r7, #0]
|
|
80061da: 68d2 ldr r2, [r2, #12]
|
|
80061dc: 4311 orrs r1, r2
|
|
80061de: 683a ldr r2, [r7, #0]
|
|
80061e0: 6912 ldr r2, [r2, #16]
|
|
80061e2: 4311 orrs r1, r2
|
|
80061e4: 683a ldr r2, [r7, #0]
|
|
80061e6: 6952 ldr r2, [r2, #20]
|
|
80061e8: 4311 orrs r1, r2
|
|
80061ea: 683a ldr r2, [r7, #0]
|
|
80061ec: 6992 ldr r2, [r2, #24]
|
|
80061ee: 4311 orrs r1, r2
|
|
80061f0: 683a ldr r2, [r7, #0]
|
|
80061f2: 69d2 ldr r2, [r2, #28]
|
|
80061f4: 4311 orrs r1, r2
|
|
80061f6: 683a ldr r2, [r7, #0]
|
|
80061f8: 6a12 ldr r2, [r2, #32]
|
|
80061fa: 4311 orrs r1, r2
|
|
80061fc: 683a ldr r2, [r7, #0]
|
|
80061fe: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
8006200: 430a orrs r2, r1
|
|
8006202: 431a orrs r2, r3
|
|
8006204: 687b ldr r3, [r7, #4]
|
|
8006206: 601a str r2, [r3, #0]
|
|
8006208: e028 b.n 800625c <FMC_SDRAM_Init+0xac>
|
|
Init->ReadBurst |
|
|
Init->ReadPipeDelay));
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
|
|
800620a: 687b ldr r3, [r7, #4]
|
|
800620c: 681b ldr r3, [r3, #0]
|
|
800620e: f423 42f8 bic.w r2, r3, #31744 @ 0x7c00
|
|
8006212: 683b ldr r3, [r7, #0]
|
|
8006214: 69d9 ldr r1, [r3, #28]
|
|
8006216: 683b ldr r3, [r7, #0]
|
|
8006218: 6a1b ldr r3, [r3, #32]
|
|
800621a: 4319 orrs r1, r3
|
|
800621c: 683b ldr r3, [r7, #0]
|
|
800621e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006220: 430b orrs r3, r1
|
|
8006222: 431a orrs r2, r3
|
|
8006224: 687b ldr r3, [r7, #4]
|
|
8006226: 601a str r2, [r3, #0]
|
|
FMC_SDCR1_RPIPE,
|
|
(Init->SDClockPeriod |
|
|
Init->ReadBurst |
|
|
Init->ReadPipeDelay));
|
|
|
|
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
|
|
8006228: 687b ldr r3, [r7, #4]
|
|
800622a: 685b ldr r3, [r3, #4]
|
|
800622c: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
|
|
8006230: f023 037f bic.w r3, r3, #127 @ 0x7f
|
|
8006234: 683a ldr r2, [r7, #0]
|
|
8006236: 6851 ldr r1, [r2, #4]
|
|
8006238: 683a ldr r2, [r7, #0]
|
|
800623a: 6892 ldr r2, [r2, #8]
|
|
800623c: 4311 orrs r1, r2
|
|
800623e: 683a ldr r2, [r7, #0]
|
|
8006240: 68d2 ldr r2, [r2, #12]
|
|
8006242: 4311 orrs r1, r2
|
|
8006244: 683a ldr r2, [r7, #0]
|
|
8006246: 6912 ldr r2, [r2, #16]
|
|
8006248: 4311 orrs r1, r2
|
|
800624a: 683a ldr r2, [r7, #0]
|
|
800624c: 6952 ldr r2, [r2, #20]
|
|
800624e: 4311 orrs r1, r2
|
|
8006250: 683a ldr r2, [r7, #0]
|
|
8006252: 6992 ldr r2, [r2, #24]
|
|
8006254: 430a orrs r2, r1
|
|
8006256: 431a orrs r2, r3
|
|
8006258: 687b ldr r3, [r7, #4]
|
|
800625a: 605a str r2, [r3, #4]
|
|
Init->InternalBankNumber |
|
|
Init->CASLatency |
|
|
Init->WriteProtection));
|
|
}
|
|
|
|
return HAL_OK;
|
|
800625c: 2300 movs r3, #0
|
|
}
|
|
800625e: 4618 mov r0, r3
|
|
8006260: 370c adds r7, #12
|
|
8006262: 46bd mov sp, r7
|
|
8006264: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006268: 4770 bx lr
|
|
|
|
0800626a <FMC_SDRAM_Timing_Init>:
|
|
* @param Bank SDRAM bank number
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
|
|
const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
|
|
{
|
|
800626a: b480 push {r7}
|
|
800626c: b085 sub sp, #20
|
|
800626e: af00 add r7, sp, #0
|
|
8006270: 60f8 str r0, [r7, #12]
|
|
8006272: 60b9 str r1, [r7, #8]
|
|
8006274: 607a str r2, [r7, #4]
|
|
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
|
|
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
|
|
assert_param(IS_FMC_SDRAM_BANK(Bank));
|
|
|
|
/* Set SDRAM device timing parameters */
|
|
if (Bank == FMC_SDRAM_BANK1)
|
|
8006276: 687b ldr r3, [r7, #4]
|
|
8006278: 2b00 cmp r3, #0
|
|
800627a: d128 bne.n 80062ce <FMC_SDRAM_Timing_Init+0x64>
|
|
{
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
|
|
800627c: 68fb ldr r3, [r7, #12]
|
|
800627e: 689b ldr r3, [r3, #8]
|
|
8006280: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
|
|
8006284: 68bb ldr r3, [r7, #8]
|
|
8006286: 681b ldr r3, [r3, #0]
|
|
8006288: 1e59 subs r1, r3, #1
|
|
800628a: 68bb ldr r3, [r7, #8]
|
|
800628c: 685b ldr r3, [r3, #4]
|
|
800628e: 3b01 subs r3, #1
|
|
8006290: 011b lsls r3, r3, #4
|
|
8006292: 4319 orrs r1, r3
|
|
8006294: 68bb ldr r3, [r7, #8]
|
|
8006296: 689b ldr r3, [r3, #8]
|
|
8006298: 3b01 subs r3, #1
|
|
800629a: 021b lsls r3, r3, #8
|
|
800629c: 4319 orrs r1, r3
|
|
800629e: 68bb ldr r3, [r7, #8]
|
|
80062a0: 68db ldr r3, [r3, #12]
|
|
80062a2: 3b01 subs r3, #1
|
|
80062a4: 031b lsls r3, r3, #12
|
|
80062a6: 4319 orrs r1, r3
|
|
80062a8: 68bb ldr r3, [r7, #8]
|
|
80062aa: 691b ldr r3, [r3, #16]
|
|
80062ac: 3b01 subs r3, #1
|
|
80062ae: 041b lsls r3, r3, #16
|
|
80062b0: 4319 orrs r1, r3
|
|
80062b2: 68bb ldr r3, [r7, #8]
|
|
80062b4: 695b ldr r3, [r3, #20]
|
|
80062b6: 3b01 subs r3, #1
|
|
80062b8: 051b lsls r3, r3, #20
|
|
80062ba: 4319 orrs r1, r3
|
|
80062bc: 68bb ldr r3, [r7, #8]
|
|
80062be: 699b ldr r3, [r3, #24]
|
|
80062c0: 3b01 subs r3, #1
|
|
80062c2: 061b lsls r3, r3, #24
|
|
80062c4: 430b orrs r3, r1
|
|
80062c6: 431a orrs r2, r3
|
|
80062c8: 68fb ldr r3, [r7, #12]
|
|
80062ca: 609a str r2, [r3, #8]
|
|
80062cc: e02f b.n 800632e <FMC_SDRAM_Timing_Init+0xc4>
|
|
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
|
|
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
|
|
}
|
|
else /* FMC_Bank2_SDRAM */
|
|
{
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
|
|
80062ce: 68fb ldr r3, [r7, #12]
|
|
80062d0: 689b ldr r3, [r3, #8]
|
|
80062d2: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
|
|
80062d6: f423 4370 bic.w r3, r3, #61440 @ 0xf000
|
|
80062da: 68ba ldr r2, [r7, #8]
|
|
80062dc: 68d2 ldr r2, [r2, #12]
|
|
80062de: 3a01 subs r2, #1
|
|
80062e0: 0311 lsls r1, r2, #12
|
|
80062e2: 68ba ldr r2, [r7, #8]
|
|
80062e4: 6952 ldr r2, [r2, #20]
|
|
80062e6: 3a01 subs r2, #1
|
|
80062e8: 0512 lsls r2, r2, #20
|
|
80062ea: 430a orrs r2, r1
|
|
80062ec: 431a orrs r2, r3
|
|
80062ee: 68fb ldr r3, [r7, #12]
|
|
80062f0: 609a str r2, [r3, #8]
|
|
FMC_SDTR1_TRC |
|
|
FMC_SDTR1_TRP,
|
|
(((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
|
|
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
|
|
|
|
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
|
|
80062f2: 68fb ldr r3, [r7, #12]
|
|
80062f4: 68db ldr r3, [r3, #12]
|
|
80062f6: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
|
|
80062fa: 68bb ldr r3, [r7, #8]
|
|
80062fc: 681b ldr r3, [r3, #0]
|
|
80062fe: 1e59 subs r1, r3, #1
|
|
8006300: 68bb ldr r3, [r7, #8]
|
|
8006302: 685b ldr r3, [r3, #4]
|
|
8006304: 3b01 subs r3, #1
|
|
8006306: 011b lsls r3, r3, #4
|
|
8006308: 4319 orrs r1, r3
|
|
800630a: 68bb ldr r3, [r7, #8]
|
|
800630c: 689b ldr r3, [r3, #8]
|
|
800630e: 3b01 subs r3, #1
|
|
8006310: 021b lsls r3, r3, #8
|
|
8006312: 4319 orrs r1, r3
|
|
8006314: 68bb ldr r3, [r7, #8]
|
|
8006316: 691b ldr r3, [r3, #16]
|
|
8006318: 3b01 subs r3, #1
|
|
800631a: 041b lsls r3, r3, #16
|
|
800631c: 4319 orrs r1, r3
|
|
800631e: 68bb ldr r3, [r7, #8]
|
|
8006320: 699b ldr r3, [r3, #24]
|
|
8006322: 3b01 subs r3, #1
|
|
8006324: 061b lsls r3, r3, #24
|
|
8006326: 430b orrs r3, r1
|
|
8006328: 431a orrs r2, r3
|
|
800632a: 68fb ldr r3, [r7, #12]
|
|
800632c: 60da str r2, [r3, #12]
|
|
(((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
|
|
(((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
|
|
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
|
|
}
|
|
|
|
return HAL_OK;
|
|
800632e: 2300 movs r3, #0
|
|
}
|
|
8006330: 4618 mov r0, r3
|
|
8006332: 3714 adds r7, #20
|
|
8006334: 46bd mov sp, r7
|
|
8006336: f85d 7b04 ldr.w r7, [sp], #4
|
|
800633a: 4770 bx lr
|
|
|
|
0800633c <USB_EnableGlobalInt>:
|
|
* Enables the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800633c: b480 push {r7}
|
|
800633e: b083 sub sp, #12
|
|
8006340: af00 add r7, sp, #0
|
|
8006342: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
|
|
8006344: 687b ldr r3, [r7, #4]
|
|
8006346: 689b ldr r3, [r3, #8]
|
|
8006348: f043 0201 orr.w r2, r3, #1
|
|
800634c: 687b ldr r3, [r7, #4]
|
|
800634e: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8006350: 2300 movs r3, #0
|
|
}
|
|
8006352: 4618 mov r0, r3
|
|
8006354: 370c adds r7, #12
|
|
8006356: 46bd mov sp, r7
|
|
8006358: f85d 7b04 ldr.w r7, [sp], #4
|
|
800635c: 4770 bx lr
|
|
|
|
0800635e <USB_DisableGlobalInt>:
|
|
* Disable the controller's Global Int in the AHB Config reg
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
800635e: b480 push {r7}
|
|
8006360: b083 sub sp, #12
|
|
8006362: af00 add r7, sp, #0
|
|
8006364: 6078 str r0, [r7, #4]
|
|
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
|
|
8006366: 687b ldr r3, [r7, #4]
|
|
8006368: 689b ldr r3, [r3, #8]
|
|
800636a: f023 0201 bic.w r2, r3, #1
|
|
800636e: 687b ldr r3, [r7, #4]
|
|
8006370: 609a str r2, [r3, #8]
|
|
return HAL_OK;
|
|
8006372: 2300 movs r3, #0
|
|
}
|
|
8006374: 4618 mov r0, r3
|
|
8006376: 370c adds r7, #12
|
|
8006378: 46bd mov sp, r7
|
|
800637a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800637e: 4770 bx lr
|
|
|
|
08006380 <USB_FlushTxFifo>:
|
|
* This parameter can be a value from 1 to 15
|
|
15 means Flush all Tx FIFOs
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
|
|
{
|
|
8006380: b480 push {r7}
|
|
8006382: b085 sub sp, #20
|
|
8006384: af00 add r7, sp, #0
|
|
8006386: 6078 str r0, [r7, #4]
|
|
8006388: 6039 str r1, [r7, #0]
|
|
__IO uint32_t count = 0U;
|
|
800638a: 2300 movs r3, #0
|
|
800638c: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
800638e: 68fb ldr r3, [r7, #12]
|
|
8006390: 3301 adds r3, #1
|
|
8006392: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
8006394: 68fb ldr r3, [r7, #12]
|
|
8006396: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
800639a: d901 bls.n 80063a0 <USB_FlushTxFifo+0x20>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800639c: 2303 movs r3, #3
|
|
800639e: e01b b.n 80063d8 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
80063a0: 687b ldr r3, [r7, #4]
|
|
80063a2: 691b ldr r3, [r3, #16]
|
|
80063a4: 2b00 cmp r3, #0
|
|
80063a6: daf2 bge.n 800638e <USB_FlushTxFifo+0xe>
|
|
|
|
/* Flush TX Fifo */
|
|
count = 0U;
|
|
80063a8: 2300 movs r3, #0
|
|
80063aa: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
|
|
80063ac: 683b ldr r3, [r7, #0]
|
|
80063ae: 019b lsls r3, r3, #6
|
|
80063b0: f043 0220 orr.w r2, r3, #32
|
|
80063b4: 687b ldr r3, [r7, #4]
|
|
80063b6: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
80063b8: 68fb ldr r3, [r7, #12]
|
|
80063ba: 3301 adds r3, #1
|
|
80063bc: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80063be: 68fb ldr r3, [r7, #12]
|
|
80063c0: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80063c4: d901 bls.n 80063ca <USB_FlushTxFifo+0x4a>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80063c6: 2303 movs r3, #3
|
|
80063c8: e006 b.n 80063d8 <USB_FlushTxFifo+0x58>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
|
|
80063ca: 687b ldr r3, [r7, #4]
|
|
80063cc: 691b ldr r3, [r3, #16]
|
|
80063ce: f003 0320 and.w r3, r3, #32
|
|
80063d2: 2b20 cmp r3, #32
|
|
80063d4: d0f0 beq.n 80063b8 <USB_FlushTxFifo+0x38>
|
|
|
|
return HAL_OK;
|
|
80063d6: 2300 movs r3, #0
|
|
}
|
|
80063d8: 4618 mov r0, r3
|
|
80063da: 3714 adds r7, #20
|
|
80063dc: 46bd mov sp, r7
|
|
80063de: f85d 7b04 ldr.w r7, [sp], #4
|
|
80063e2: 4770 bx lr
|
|
|
|
080063e4 <USB_FlushRxFifo>:
|
|
* @brief USB_FlushRxFifo Flush Rx FIFO
|
|
* @param USBx Selected device
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80063e4: b480 push {r7}
|
|
80063e6: b085 sub sp, #20
|
|
80063e8: af00 add r7, sp, #0
|
|
80063ea: 6078 str r0, [r7, #4]
|
|
__IO uint32_t count = 0U;
|
|
80063ec: 2300 movs r3, #0
|
|
80063ee: 60fb str r3, [r7, #12]
|
|
|
|
/* Wait for AHB master IDLE state. */
|
|
do
|
|
{
|
|
count++;
|
|
80063f0: 68fb ldr r3, [r7, #12]
|
|
80063f2: 3301 adds r3, #1
|
|
80063f4: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
80063f6: 68fb ldr r3, [r7, #12]
|
|
80063f8: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
80063fc: d901 bls.n 8006402 <USB_FlushRxFifo+0x1e>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80063fe: 2303 movs r3, #3
|
|
8006400: e018 b.n 8006434 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
|
|
8006402: 687b ldr r3, [r7, #4]
|
|
8006404: 691b ldr r3, [r3, #16]
|
|
8006406: 2b00 cmp r3, #0
|
|
8006408: daf2 bge.n 80063f0 <USB_FlushRxFifo+0xc>
|
|
|
|
/* Flush RX Fifo */
|
|
count = 0U;
|
|
800640a: 2300 movs r3, #0
|
|
800640c: 60fb str r3, [r7, #12]
|
|
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
|
|
800640e: 687b ldr r3, [r7, #4]
|
|
8006410: 2210 movs r2, #16
|
|
8006412: 611a str r2, [r3, #16]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006414: 68fb ldr r3, [r7, #12]
|
|
8006416: 3301 adds r3, #1
|
|
8006418: 60fb str r3, [r7, #12]
|
|
|
|
if (count > HAL_USB_TIMEOUT)
|
|
800641a: 68fb ldr r3, [r7, #12]
|
|
800641c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
|
|
8006420: d901 bls.n 8006426 <USB_FlushRxFifo+0x42>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8006422: 2303 movs r3, #3
|
|
8006424: e006 b.n 8006434 <USB_FlushRxFifo+0x50>
|
|
}
|
|
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
|
|
8006426: 687b ldr r3, [r7, #4]
|
|
8006428: 691b ldr r3, [r3, #16]
|
|
800642a: f003 0310 and.w r3, r3, #16
|
|
800642e: 2b10 cmp r3, #16
|
|
8006430: d0f0 beq.n 8006414 <USB_FlushRxFifo+0x30>
|
|
|
|
return HAL_OK;
|
|
8006432: 2300 movs r3, #0
|
|
}
|
|
8006434: 4618 mov r0, r3
|
|
8006436: 3714 adds r7, #20
|
|
8006438: 46bd mov sp, r7
|
|
800643a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800643e: 4770 bx lr
|
|
|
|
08006440 <USB_ReadPacket>:
|
|
* @param dest source pointer
|
|
* @param len Number of bytes to read
|
|
* @retval pointer to destination buffer
|
|
*/
|
|
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
|
|
{
|
|
8006440: b480 push {r7}
|
|
8006442: b08b sub sp, #44 @ 0x2c
|
|
8006444: af00 add r7, sp, #0
|
|
8006446: 60f8 str r0, [r7, #12]
|
|
8006448: 60b9 str r1, [r7, #8]
|
|
800644a: 4613 mov r3, r2
|
|
800644c: 80fb strh r3, [r7, #6]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800644e: 68fb ldr r3, [r7, #12]
|
|
8006450: 61bb str r3, [r7, #24]
|
|
uint8_t *pDest = dest;
|
|
8006452: 68bb ldr r3, [r7, #8]
|
|
8006454: 627b str r3, [r7, #36] @ 0x24
|
|
uint32_t pData;
|
|
uint32_t i;
|
|
uint32_t count32b = (uint32_t)len >> 2U;
|
|
8006456: 88fb ldrh r3, [r7, #6]
|
|
8006458: 089b lsrs r3, r3, #2
|
|
800645a: b29b uxth r3, r3
|
|
800645c: 617b str r3, [r7, #20]
|
|
uint16_t remaining_bytes = len % 4U;
|
|
800645e: 88fb ldrh r3, [r7, #6]
|
|
8006460: f003 0303 and.w r3, r3, #3
|
|
8006464: 83fb strh r3, [r7, #30]
|
|
|
|
for (i = 0U; i < count32b; i++)
|
|
8006466: 2300 movs r3, #0
|
|
8006468: 623b str r3, [r7, #32]
|
|
800646a: e014 b.n 8006496 <USB_ReadPacket+0x56>
|
|
{
|
|
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
|
|
800646c: 69bb ldr r3, [r7, #24]
|
|
800646e: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
8006472: 681a ldr r2, [r3, #0]
|
|
8006474: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006476: 601a str r2, [r3, #0]
|
|
pDest++;
|
|
8006478: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800647a: 3301 adds r3, #1
|
|
800647c: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
800647e: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006480: 3301 adds r3, #1
|
|
8006482: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
8006484: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006486: 3301 adds r3, #1
|
|
8006488: 627b str r3, [r7, #36] @ 0x24
|
|
pDest++;
|
|
800648a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800648c: 3301 adds r3, #1
|
|
800648e: 627b str r3, [r7, #36] @ 0x24
|
|
for (i = 0U; i < count32b; i++)
|
|
8006490: 6a3b ldr r3, [r7, #32]
|
|
8006492: 3301 adds r3, #1
|
|
8006494: 623b str r3, [r7, #32]
|
|
8006496: 6a3a ldr r2, [r7, #32]
|
|
8006498: 697b ldr r3, [r7, #20]
|
|
800649a: 429a cmp r2, r3
|
|
800649c: d3e6 bcc.n 800646c <USB_ReadPacket+0x2c>
|
|
}
|
|
|
|
/* When Number of data is not word aligned, read the remaining byte */
|
|
if (remaining_bytes != 0U)
|
|
800649e: 8bfb ldrh r3, [r7, #30]
|
|
80064a0: 2b00 cmp r3, #0
|
|
80064a2: d01e beq.n 80064e2 <USB_ReadPacket+0xa2>
|
|
{
|
|
i = 0U;
|
|
80064a4: 2300 movs r3, #0
|
|
80064a6: 623b str r3, [r7, #32]
|
|
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
|
|
80064a8: 69bb ldr r3, [r7, #24]
|
|
80064aa: f503 5380 add.w r3, r3, #4096 @ 0x1000
|
|
80064ae: 461a mov r2, r3
|
|
80064b0: f107 0310 add.w r3, r7, #16
|
|
80064b4: 6812 ldr r2, [r2, #0]
|
|
80064b6: 601a str r2, [r3, #0]
|
|
|
|
do
|
|
{
|
|
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
|
|
80064b8: 693a ldr r2, [r7, #16]
|
|
80064ba: 6a3b ldr r3, [r7, #32]
|
|
80064bc: b2db uxtb r3, r3
|
|
80064be: 00db lsls r3, r3, #3
|
|
80064c0: fa22 f303 lsr.w r3, r2, r3
|
|
80064c4: b2da uxtb r2, r3
|
|
80064c6: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80064c8: 701a strb r2, [r3, #0]
|
|
i++;
|
|
80064ca: 6a3b ldr r3, [r7, #32]
|
|
80064cc: 3301 adds r3, #1
|
|
80064ce: 623b str r3, [r7, #32]
|
|
pDest++;
|
|
80064d0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
80064d2: 3301 adds r3, #1
|
|
80064d4: 627b str r3, [r7, #36] @ 0x24
|
|
remaining_bytes--;
|
|
80064d6: 8bfb ldrh r3, [r7, #30]
|
|
80064d8: 3b01 subs r3, #1
|
|
80064da: 83fb strh r3, [r7, #30]
|
|
} while (remaining_bytes != 0U);
|
|
80064dc: 8bfb ldrh r3, [r7, #30]
|
|
80064de: 2b00 cmp r3, #0
|
|
80064e0: d1ea bne.n 80064b8 <USB_ReadPacket+0x78>
|
|
}
|
|
|
|
return ((void *)pDest);
|
|
80064e2: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
}
|
|
80064e4: 4618 mov r0, r3
|
|
80064e6: 372c adds r7, #44 @ 0x2c
|
|
80064e8: 46bd mov sp, r7
|
|
80064ea: f85d 7b04 ldr.w r7, [sp], #4
|
|
80064ee: 4770 bx lr
|
|
|
|
080064f0 <USB_ReadInterrupts>:
|
|
* @brief USB_ReadInterrupts: return the global USB interrupt status
|
|
* @param USBx Selected device
|
|
* @retval USB Global Interrupt status
|
|
*/
|
|
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
|
|
{
|
|
80064f0: b480 push {r7}
|
|
80064f2: b085 sub sp, #20
|
|
80064f4: af00 add r7, sp, #0
|
|
80064f6: 6078 str r0, [r7, #4]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx->GINTSTS;
|
|
80064f8: 687b ldr r3, [r7, #4]
|
|
80064fa: 695b ldr r3, [r3, #20]
|
|
80064fc: 60fb str r3, [r7, #12]
|
|
tmpreg &= USBx->GINTMSK;
|
|
80064fe: 687b ldr r3, [r7, #4]
|
|
8006500: 699b ldr r3, [r3, #24]
|
|
8006502: 68fa ldr r2, [r7, #12]
|
|
8006504: 4013 ands r3, r2
|
|
8006506: 60fb str r3, [r7, #12]
|
|
|
|
return tmpreg;
|
|
8006508: 68fb ldr r3, [r7, #12]
|
|
}
|
|
800650a: 4618 mov r0, r3
|
|
800650c: 3714 adds r7, #20
|
|
800650e: 46bd mov sp, r7
|
|
8006510: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006514: 4770 bx lr
|
|
|
|
08006516 <USB_ReadChInterrupts>:
|
|
* @param USBx Selected device
|
|
* @param chnum Channel number
|
|
* @retval USB Channel Interrupt status
|
|
*/
|
|
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
|
|
{
|
|
8006516: b480 push {r7}
|
|
8006518: b085 sub sp, #20
|
|
800651a: af00 add r7, sp, #0
|
|
800651c: 6078 str r0, [r7, #4]
|
|
800651e: 460b mov r3, r1
|
|
8006520: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006522: 687b ldr r3, [r7, #4]
|
|
8006524: 60fb str r3, [r7, #12]
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = USBx_HC(chnum)->HCINT;
|
|
8006526: 78fb ldrb r3, [r7, #3]
|
|
8006528: 015a lsls r2, r3, #5
|
|
800652a: 68fb ldr r3, [r7, #12]
|
|
800652c: 4413 add r3, r2
|
|
800652e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006532: 689b ldr r3, [r3, #8]
|
|
8006534: 60bb str r3, [r7, #8]
|
|
tmpreg &= USBx_HC(chnum)->HCINTMSK;
|
|
8006536: 78fb ldrb r3, [r7, #3]
|
|
8006538: 015a lsls r2, r3, #5
|
|
800653a: 68fb ldr r3, [r7, #12]
|
|
800653c: 4413 add r3, r2
|
|
800653e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006542: 68db ldr r3, [r3, #12]
|
|
8006544: 68ba ldr r2, [r7, #8]
|
|
8006546: 4013 ands r3, r2
|
|
8006548: 60bb str r3, [r7, #8]
|
|
|
|
return tmpreg;
|
|
800654a: 68bb ldr r3, [r7, #8]
|
|
}
|
|
800654c: 4618 mov r0, r3
|
|
800654e: 3714 adds r7, #20
|
|
8006550: 46bd mov sp, r7
|
|
8006552: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006556: 4770 bx lr
|
|
|
|
08006558 <USB_GetMode>:
|
|
* This parameter can be one of these values:
|
|
* 1 : Host
|
|
* 0 : Device
|
|
*/
|
|
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006558: b480 push {r7}
|
|
800655a: b083 sub sp, #12
|
|
800655c: af00 add r7, sp, #0
|
|
800655e: 6078 str r0, [r7, #4]
|
|
return ((USBx->GINTSTS) & 0x1U);
|
|
8006560: 687b ldr r3, [r7, #4]
|
|
8006562: 695b ldr r3, [r3, #20]
|
|
8006564: f003 0301 and.w r3, r3, #1
|
|
}
|
|
8006568: 4618 mov r0, r3
|
|
800656a: 370c adds r7, #12
|
|
800656c: 46bd mov sp, r7
|
|
800656e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006572: 4770 bx lr
|
|
|
|
08006574 <USB_InitFSLSPClkSel>:
|
|
* HCFG_48_MHZ : Full Speed 48 MHz Clock
|
|
* HCFG_6_MHZ : Low Speed 6 MHz Clock
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
|
|
{
|
|
8006574: b480 push {r7}
|
|
8006576: b085 sub sp, #20
|
|
8006578: af00 add r7, sp, #0
|
|
800657a: 6078 str r0, [r7, #4]
|
|
800657c: 460b mov r3, r1
|
|
800657e: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
8006580: 687b ldr r3, [r7, #4]
|
|
8006582: 60fb str r3, [r7, #12]
|
|
|
|
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
|
|
8006584: 68fb ldr r3, [r7, #12]
|
|
8006586: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800658a: 681b ldr r3, [r3, #0]
|
|
800658c: 68fa ldr r2, [r7, #12]
|
|
800658e: f502 6280 add.w r2, r2, #1024 @ 0x400
|
|
8006592: f023 0303 bic.w r3, r3, #3
|
|
8006596: 6013 str r3, [r2, #0]
|
|
USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
|
|
8006598: 68fb ldr r3, [r7, #12]
|
|
800659a: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
800659e: 681a ldr r2, [r3, #0]
|
|
80065a0: 78fb ldrb r3, [r7, #3]
|
|
80065a2: f003 0303 and.w r3, r3, #3
|
|
80065a6: 68f9 ldr r1, [r7, #12]
|
|
80065a8: f501 6180 add.w r1, r1, #1024 @ 0x400
|
|
80065ac: 4313 orrs r3, r2
|
|
80065ae: 600b str r3, [r1, #0]
|
|
|
|
if (freq == HCFG_48_MHZ)
|
|
80065b0: 78fb ldrb r3, [r7, #3]
|
|
80065b2: 2b01 cmp r3, #1
|
|
80065b4: d107 bne.n 80065c6 <USB_InitFSLSPClkSel+0x52>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_48_MHZ;
|
|
80065b6: 68fb ldr r3, [r7, #12]
|
|
80065b8: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80065bc: 461a mov r2, r3
|
|
80065be: f64b 3380 movw r3, #48000 @ 0xbb80
|
|
80065c2: 6053 str r3, [r2, #4]
|
|
80065c4: e00c b.n 80065e0 <USB_InitFSLSPClkSel+0x6c>
|
|
}
|
|
else if (freq == HCFG_6_MHZ)
|
|
80065c6: 78fb ldrb r3, [r7, #3]
|
|
80065c8: 2b02 cmp r3, #2
|
|
80065ca: d107 bne.n 80065dc <USB_InitFSLSPClkSel+0x68>
|
|
{
|
|
USBx_HOST->HFIR = HFIR_6_MHZ;
|
|
80065cc: 68fb ldr r3, [r7, #12]
|
|
80065ce: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80065d2: 461a mov r2, r3
|
|
80065d4: f241 7370 movw r3, #6000 @ 0x1770
|
|
80065d8: 6053 str r3, [r2, #4]
|
|
80065da: e001 b.n 80065e0 <USB_InitFSLSPClkSel+0x6c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
80065dc: 2301 movs r3, #1
|
|
80065de: e000 b.n 80065e2 <USB_InitFSLSPClkSel+0x6e>
|
|
}
|
|
|
|
return HAL_OK;
|
|
80065e0: 2300 movs r3, #0
|
|
}
|
|
80065e2: 4618 mov r0, r3
|
|
80065e4: 3714 adds r7, #20
|
|
80065e6: 46bd mov sp, r7
|
|
80065e8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80065ec: 4770 bx lr
|
|
|
|
080065ee <USB_HC_ReadInterrupt>:
|
|
* @brief Read all host channel interrupts status
|
|
* @param USBx Selected device
|
|
* @retval HAL state
|
|
*/
|
|
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
80065ee: b480 push {r7}
|
|
80065f0: b085 sub sp, #20
|
|
80065f2: af00 add r7, sp, #0
|
|
80065f4: 6078 str r0, [r7, #4]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
80065f6: 687b ldr r3, [r7, #4]
|
|
80065f8: 60fb str r3, [r7, #12]
|
|
|
|
return ((USBx_HOST->HAINT) & 0xFFFFU);
|
|
80065fa: 68fb ldr r3, [r7, #12]
|
|
80065fc: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8006600: 695b ldr r3, [r3, #20]
|
|
8006602: b29b uxth r3, r3
|
|
}
|
|
8006604: 4618 mov r0, r3
|
|
8006606: 3714 adds r7, #20
|
|
8006608: 46bd mov sp, r7
|
|
800660a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800660e: 4770 bx lr
|
|
|
|
08006610 <USB_HC_Halt>:
|
|
* @param hc_num Host Channel number
|
|
* This parameter can be a value from 1 to 15
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
|
|
{
|
|
8006610: b480 push {r7}
|
|
8006612: b089 sub sp, #36 @ 0x24
|
|
8006614: af00 add r7, sp, #0
|
|
8006616: 6078 str r0, [r7, #4]
|
|
8006618: 460b mov r3, r1
|
|
800661a: 70fb strb r3, [r7, #3]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800661c: 687b ldr r3, [r7, #4]
|
|
800661e: 61fb str r3, [r7, #28]
|
|
uint32_t hcnum = (uint32_t)hc_num;
|
|
8006620: 78fb ldrb r3, [r7, #3]
|
|
8006622: 61bb str r3, [r7, #24]
|
|
__IO uint32_t count = 0U;
|
|
8006624: 2300 movs r3, #0
|
|
8006626: 60bb str r3, [r7, #8]
|
|
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
|
|
8006628: 69bb ldr r3, [r7, #24]
|
|
800662a: 015a lsls r2, r3, #5
|
|
800662c: 69fb ldr r3, [r7, #28]
|
|
800662e: 4413 add r3, r2
|
|
8006630: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006634: 681b ldr r3, [r3, #0]
|
|
8006636: 0c9b lsrs r3, r3, #18
|
|
8006638: f003 0303 and.w r3, r3, #3
|
|
800663c: 617b str r3, [r7, #20]
|
|
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
|
|
800663e: 69bb ldr r3, [r7, #24]
|
|
8006640: 015a lsls r2, r3, #5
|
|
8006642: 69fb ldr r3, [r7, #28]
|
|
8006644: 4413 add r3, r2
|
|
8006646: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800664a: 681b ldr r3, [r3, #0]
|
|
800664c: 0fdb lsrs r3, r3, #31
|
|
800664e: f003 0301 and.w r3, r3, #1
|
|
8006652: 613b str r3, [r7, #16]
|
|
uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
|
|
8006654: 69bb ldr r3, [r7, #24]
|
|
8006656: 015a lsls r2, r3, #5
|
|
8006658: 69fb ldr r3, [r7, #28]
|
|
800665a: 4413 add r3, r2
|
|
800665c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006660: 685b ldr r3, [r3, #4]
|
|
8006662: 0fdb lsrs r3, r3, #31
|
|
8006664: f003 0301 and.w r3, r3, #1
|
|
8006668: 60fb str r3, [r7, #12]
|
|
|
|
/* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
|
|
At the end of the next uframe/frame (in the worst case), the core generates a channel halted
|
|
and disables the channel automatically. */
|
|
|
|
if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
|
|
800666a: 687b ldr r3, [r7, #4]
|
|
800666c: 689b ldr r3, [r3, #8]
|
|
800666e: f003 0320 and.w r3, r3, #32
|
|
8006672: 2b20 cmp r3, #32
|
|
8006674: d10d bne.n 8006692 <USB_HC_Halt+0x82>
|
|
8006676: 68fb ldr r3, [r7, #12]
|
|
8006678: 2b00 cmp r3, #0
|
|
800667a: d10a bne.n 8006692 <USB_HC_Halt+0x82>
|
|
800667c: 693b ldr r3, [r7, #16]
|
|
800667e: 2b00 cmp r3, #0
|
|
8006680: d005 beq.n 800668e <USB_HC_Halt+0x7e>
|
|
((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
|
|
8006682: 697b ldr r3, [r7, #20]
|
|
8006684: 2b01 cmp r3, #1
|
|
8006686: d002 beq.n 800668e <USB_HC_Halt+0x7e>
|
|
8006688: 697b ldr r3, [r7, #20]
|
|
800668a: 2b03 cmp r3, #3
|
|
800668c: d101 bne.n 8006692 <USB_HC_Halt+0x82>
|
|
{
|
|
return HAL_OK;
|
|
800668e: 2300 movs r3, #0
|
|
8006690: e0d8 b.n 8006844 <USB_HC_Halt+0x234>
|
|
}
|
|
|
|
/* Check for space in the request queue to issue the halt. */
|
|
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
|
|
8006692: 697b ldr r3, [r7, #20]
|
|
8006694: 2b00 cmp r3, #0
|
|
8006696: d002 beq.n 800669e <USB_HC_Halt+0x8e>
|
|
8006698: 697b ldr r3, [r7, #20]
|
|
800669a: 2b02 cmp r3, #2
|
|
800669c: d173 bne.n 8006786 <USB_HC_Halt+0x176>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
|
800669e: 69bb ldr r3, [r7, #24]
|
|
80066a0: 015a lsls r2, r3, #5
|
|
80066a2: 69fb ldr r3, [r7, #28]
|
|
80066a4: 4413 add r3, r2
|
|
80066a6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80066aa: 681b ldr r3, [r3, #0]
|
|
80066ac: 69ba ldr r2, [r7, #24]
|
|
80066ae: 0151 lsls r1, r2, #5
|
|
80066b0: 69fa ldr r2, [r7, #28]
|
|
80066b2: 440a add r2, r1
|
|
80066b4: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80066b8: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80066bc: 6013 str r3, [r2, #0]
|
|
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
80066be: 687b ldr r3, [r7, #4]
|
|
80066c0: 689b ldr r3, [r3, #8]
|
|
80066c2: f003 0320 and.w r3, r3, #32
|
|
80066c6: 2b00 cmp r3, #0
|
|
80066c8: d14a bne.n 8006760 <USB_HC_Halt+0x150>
|
|
{
|
|
if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
|
|
80066ca: 687b ldr r3, [r7, #4]
|
|
80066cc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80066ce: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
80066d2: 2b00 cmp r3, #0
|
|
80066d4: d133 bne.n 800673e <USB_HC_Halt+0x12e>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
|
80066d6: 69bb ldr r3, [r7, #24]
|
|
80066d8: 015a lsls r2, r3, #5
|
|
80066da: 69fb ldr r3, [r7, #28]
|
|
80066dc: 4413 add r3, r2
|
|
80066de: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80066e2: 681b ldr r3, [r3, #0]
|
|
80066e4: 69ba ldr r2, [r7, #24]
|
|
80066e6: 0151 lsls r1, r2, #5
|
|
80066e8: 69fa ldr r2, [r7, #28]
|
|
80066ea: 440a add r2, r1
|
|
80066ec: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80066f0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80066f4: 6013 str r3, [r2, #0]
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
80066f6: 69bb ldr r3, [r7, #24]
|
|
80066f8: 015a lsls r2, r3, #5
|
|
80066fa: 69fb ldr r3, [r7, #28]
|
|
80066fc: 4413 add r3, r2
|
|
80066fe: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006702: 681b ldr r3, [r3, #0]
|
|
8006704: 69ba ldr r2, [r7, #24]
|
|
8006706: 0151 lsls r1, r2, #5
|
|
8006708: 69fa ldr r2, [r7, #28]
|
|
800670a: 440a add r2, r1
|
|
800670c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8006710: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8006714: 6013 str r3, [r2, #0]
|
|
do
|
|
{
|
|
count++;
|
|
8006716: 68bb ldr r3, [r7, #8]
|
|
8006718: 3301 adds r3, #1
|
|
800671a: 60bb str r3, [r7, #8]
|
|
|
|
if (count > 1000U)
|
|
800671c: 68bb ldr r3, [r7, #8]
|
|
800671e: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8006722: d82e bhi.n 8006782 <USB_HC_Halt+0x172>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8006724: 69bb ldr r3, [r7, #24]
|
|
8006726: 015a lsls r2, r3, #5
|
|
8006728: 69fb ldr r3, [r7, #28]
|
|
800672a: 4413 add r3, r2
|
|
800672c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006730: 681b ldr r3, [r3, #0]
|
|
8006732: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006736: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800673a: d0ec beq.n 8006716 <USB_HC_Halt+0x106>
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
800673c: e081 b.n 8006842 <USB_HC_Halt+0x232>
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
800673e: 69bb ldr r3, [r7, #24]
|
|
8006740: 015a lsls r2, r3, #5
|
|
8006742: 69fb ldr r3, [r7, #28]
|
|
8006744: 4413 add r3, r2
|
|
8006746: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800674a: 681b ldr r3, [r3, #0]
|
|
800674c: 69ba ldr r2, [r7, #24]
|
|
800674e: 0151 lsls r1, r2, #5
|
|
8006750: 69fa ldr r2, [r7, #28]
|
|
8006752: 440a add r2, r1
|
|
8006754: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8006758: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800675c: 6013 str r3, [r2, #0]
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
800675e: e070 b.n 8006842 <USB_HC_Halt+0x232>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
8006760: 69bb ldr r3, [r7, #24]
|
|
8006762: 015a lsls r2, r3, #5
|
|
8006764: 69fb ldr r3, [r7, #28]
|
|
8006766: 4413 add r3, r2
|
|
8006768: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800676c: 681b ldr r3, [r3, #0]
|
|
800676e: 69ba ldr r2, [r7, #24]
|
|
8006770: 0151 lsls r1, r2, #5
|
|
8006772: 69fa ldr r2, [r7, #28]
|
|
8006774: 440a add r2, r1
|
|
8006776: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
800677a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800677e: 6013 str r3, [r2, #0]
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8006780: e05f b.n 8006842 <USB_HC_Halt+0x232>
|
|
break;
|
|
8006782: bf00 nop
|
|
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
|
|
8006784: e05d b.n 8006842 <USB_HC_Halt+0x232>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
|
|
8006786: 69bb ldr r3, [r7, #24]
|
|
8006788: 015a lsls r2, r3, #5
|
|
800678a: 69fb ldr r3, [r7, #28]
|
|
800678c: 4413 add r3, r2
|
|
800678e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006792: 681b ldr r3, [r3, #0]
|
|
8006794: 69ba ldr r2, [r7, #24]
|
|
8006796: 0151 lsls r1, r2, #5
|
|
8006798: 69fa ldr r2, [r7, #28]
|
|
800679a: 440a add r2, r1
|
|
800679c: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80067a0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80067a4: 6013 str r3, [r2, #0]
|
|
|
|
if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
|
|
80067a6: 69fb ldr r3, [r7, #28]
|
|
80067a8: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
80067ac: 691b ldr r3, [r3, #16]
|
|
80067ae: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
80067b2: 2b00 cmp r3, #0
|
|
80067b4: d133 bne.n 800681e <USB_HC_Halt+0x20e>
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
|
|
80067b6: 69bb ldr r3, [r7, #24]
|
|
80067b8: 015a lsls r2, r3, #5
|
|
80067ba: 69fb ldr r3, [r7, #28]
|
|
80067bc: 4413 add r3, r2
|
|
80067be: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80067c2: 681b ldr r3, [r3, #0]
|
|
80067c4: 69ba ldr r2, [r7, #24]
|
|
80067c6: 0151 lsls r1, r2, #5
|
|
80067c8: 69fa ldr r2, [r7, #28]
|
|
80067ca: 440a add r2, r1
|
|
80067cc: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80067d0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80067d4: 6013 str r3, [r2, #0]
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
80067d6: 69bb ldr r3, [r7, #24]
|
|
80067d8: 015a lsls r2, r3, #5
|
|
80067da: 69fb ldr r3, [r7, #28]
|
|
80067dc: 4413 add r3, r2
|
|
80067de: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80067e2: 681b ldr r3, [r3, #0]
|
|
80067e4: 69ba ldr r2, [r7, #24]
|
|
80067e6: 0151 lsls r1, r2, #5
|
|
80067e8: 69fa ldr r2, [r7, #28]
|
|
80067ea: 440a add r2, r1
|
|
80067ec: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
80067f0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80067f4: 6013 str r3, [r2, #0]
|
|
do
|
|
{
|
|
count++;
|
|
80067f6: 68bb ldr r3, [r7, #8]
|
|
80067f8: 3301 adds r3, #1
|
|
80067fa: 60bb str r3, [r7, #8]
|
|
|
|
if (count > 1000U)
|
|
80067fc: 68bb ldr r3, [r7, #8]
|
|
80067fe: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8006802: d81d bhi.n 8006840 <USB_HC_Halt+0x230>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8006804: 69bb ldr r3, [r7, #24]
|
|
8006806: 015a lsls r2, r3, #5
|
|
8006808: 69fb ldr r3, [r7, #28]
|
|
800680a: 4413 add r3, r2
|
|
800680c: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006810: 681b ldr r3, [r3, #0]
|
|
8006812: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006816: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800681a: d0ec beq.n 80067f6 <USB_HC_Halt+0x1e6>
|
|
800681c: e011 b.n 8006842 <USB_HC_Halt+0x232>
|
|
}
|
|
else
|
|
{
|
|
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
|
|
800681e: 69bb ldr r3, [r7, #24]
|
|
8006820: 015a lsls r2, r3, #5
|
|
8006822: 69fb ldr r3, [r7, #28]
|
|
8006824: 4413 add r3, r2
|
|
8006826: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800682a: 681b ldr r3, [r3, #0]
|
|
800682c: 69ba ldr r2, [r7, #24]
|
|
800682e: 0151 lsls r1, r2, #5
|
|
8006830: 69fa ldr r2, [r7, #28]
|
|
8006832: 440a add r2, r1
|
|
8006834: f502 62a0 add.w r2, r2, #1280 @ 0x500
|
|
8006838: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
800683c: 6013 str r3, [r2, #0]
|
|
800683e: e000 b.n 8006842 <USB_HC_Halt+0x232>
|
|
break;
|
|
8006840: bf00 nop
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
8006842: 2300 movs r3, #0
|
|
}
|
|
8006844: 4618 mov r0, r3
|
|
8006846: 3724 adds r7, #36 @ 0x24
|
|
8006848: 46bd mov sp, r7
|
|
800684a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800684e: 4770 bx lr
|
|
|
|
08006850 <USB_StopHost>:
|
|
* @brief Stop Host Core
|
|
* @param USBx Selected device
|
|
* @retval HAL state
|
|
*/
|
|
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
|
|
{
|
|
8006850: b580 push {r7, lr}
|
|
8006852: b088 sub sp, #32
|
|
8006854: af00 add r7, sp, #0
|
|
8006856: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8006858: 2300 movs r3, #0
|
|
800685a: 77fb strb r3, [r7, #31]
|
|
uint32_t USBx_BASE = (uint32_t)USBx;
|
|
800685c: 687b ldr r3, [r7, #4]
|
|
800685e: 617b str r3, [r7, #20]
|
|
__IO uint32_t count = 0U;
|
|
8006860: 2300 movs r3, #0
|
|
8006862: 60fb str r3, [r7, #12]
|
|
uint32_t value;
|
|
uint32_t i;
|
|
|
|
(void)USB_DisableGlobalInt(USBx);
|
|
8006864: 6878 ldr r0, [r7, #4]
|
|
8006866: f7ff fd7a bl 800635e <USB_DisableGlobalInt>
|
|
|
|
/* Flush USB FIFO */
|
|
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
|
|
800686a: 2110 movs r1, #16
|
|
800686c: 6878 ldr r0, [r7, #4]
|
|
800686e: f7ff fd87 bl 8006380 <USB_FlushTxFifo>
|
|
8006872: 4603 mov r3, r0
|
|
8006874: 2b00 cmp r3, #0
|
|
8006876: d001 beq.n 800687c <USB_StopHost+0x2c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006878: 2301 movs r3, #1
|
|
800687a: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if (USB_FlushRxFifo(USBx) != HAL_OK)
|
|
800687c: 6878 ldr r0, [r7, #4]
|
|
800687e: f7ff fdb1 bl 80063e4 <USB_FlushRxFifo>
|
|
8006882: 4603 mov r3, r0
|
|
8006884: 2b00 cmp r3, #0
|
|
8006886: d001 beq.n 800688c <USB_StopHost+0x3c>
|
|
{
|
|
ret = HAL_ERROR;
|
|
8006888: 2301 movs r3, #1
|
|
800688a: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
/* Flush out any leftover queued requests. */
|
|
for (i = 0U; i <= 15U; i++)
|
|
800688c: 2300 movs r3, #0
|
|
800688e: 61bb str r3, [r7, #24]
|
|
8006890: e01f b.n 80068d2 <USB_StopHost+0x82>
|
|
{
|
|
value = USBx_HC(i)->HCCHAR;
|
|
8006892: 69bb ldr r3, [r7, #24]
|
|
8006894: 015a lsls r2, r3, #5
|
|
8006896: 697b ldr r3, [r7, #20]
|
|
8006898: 4413 add r3, r2
|
|
800689a: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
800689e: 681b ldr r3, [r3, #0]
|
|
80068a0: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHDIS;
|
|
80068a2: 693b ldr r3, [r7, #16]
|
|
80068a4: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80068a8: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_CHENA;
|
|
80068aa: 693b ldr r3, [r7, #16]
|
|
80068ac: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
80068b0: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_EPDIR;
|
|
80068b2: 693b ldr r3, [r7, #16]
|
|
80068b4: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
80068b8: 613b str r3, [r7, #16]
|
|
USBx_HC(i)->HCCHAR = value;
|
|
80068ba: 69bb ldr r3, [r7, #24]
|
|
80068bc: 015a lsls r2, r3, #5
|
|
80068be: 697b ldr r3, [r7, #20]
|
|
80068c0: 4413 add r3, r2
|
|
80068c2: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80068c6: 461a mov r2, r3
|
|
80068c8: 693b ldr r3, [r7, #16]
|
|
80068ca: 6013 str r3, [r2, #0]
|
|
for (i = 0U; i <= 15U; i++)
|
|
80068cc: 69bb ldr r3, [r7, #24]
|
|
80068ce: 3301 adds r3, #1
|
|
80068d0: 61bb str r3, [r7, #24]
|
|
80068d2: 69bb ldr r3, [r7, #24]
|
|
80068d4: 2b0f cmp r3, #15
|
|
80068d6: d9dc bls.n 8006892 <USB_StopHost+0x42>
|
|
}
|
|
|
|
/* Halt all channels to put them into a known state. */
|
|
for (i = 0U; i <= 15U; i++)
|
|
80068d8: 2300 movs r3, #0
|
|
80068da: 61bb str r3, [r7, #24]
|
|
80068dc: e034 b.n 8006948 <USB_StopHost+0xf8>
|
|
{
|
|
value = USBx_HC(i)->HCCHAR;
|
|
80068de: 69bb ldr r3, [r7, #24]
|
|
80068e0: 015a lsls r2, r3, #5
|
|
80068e2: 697b ldr r3, [r7, #20]
|
|
80068e4: 4413 add r3, r2
|
|
80068e6: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
80068ea: 681b ldr r3, [r3, #0]
|
|
80068ec: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHDIS;
|
|
80068ee: 693b ldr r3, [r7, #16]
|
|
80068f0: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
|
|
80068f4: 613b str r3, [r7, #16]
|
|
value |= USB_OTG_HCCHAR_CHENA;
|
|
80068f6: 693b ldr r3, [r7, #16]
|
|
80068f8: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
80068fc: 613b str r3, [r7, #16]
|
|
value &= ~USB_OTG_HCCHAR_EPDIR;
|
|
80068fe: 693b ldr r3, [r7, #16]
|
|
8006900: f423 4300 bic.w r3, r3, #32768 @ 0x8000
|
|
8006904: 613b str r3, [r7, #16]
|
|
USBx_HC(i)->HCCHAR = value;
|
|
8006906: 69bb ldr r3, [r7, #24]
|
|
8006908: 015a lsls r2, r3, #5
|
|
800690a: 697b ldr r3, [r7, #20]
|
|
800690c: 4413 add r3, r2
|
|
800690e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006912: 461a mov r2, r3
|
|
8006914: 693b ldr r3, [r7, #16]
|
|
8006916: 6013 str r3, [r2, #0]
|
|
|
|
do
|
|
{
|
|
count++;
|
|
8006918: 68fb ldr r3, [r7, #12]
|
|
800691a: 3301 adds r3, #1
|
|
800691c: 60fb str r3, [r7, #12]
|
|
|
|
if (count > 1000U)
|
|
800691e: 68fb ldr r3, [r7, #12]
|
|
8006920: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
|
|
8006924: d80c bhi.n 8006940 <USB_StopHost+0xf0>
|
|
{
|
|
break;
|
|
}
|
|
} while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
|
|
8006926: 69bb ldr r3, [r7, #24]
|
|
8006928: 015a lsls r2, r3, #5
|
|
800692a: 697b ldr r3, [r7, #20]
|
|
800692c: 4413 add r3, r2
|
|
800692e: f503 63a0 add.w r3, r3, #1280 @ 0x500
|
|
8006932: 681b ldr r3, [r3, #0]
|
|
8006934: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
|
|
8006938: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
|
|
800693c: d0ec beq.n 8006918 <USB_StopHost+0xc8>
|
|
800693e: e000 b.n 8006942 <USB_StopHost+0xf2>
|
|
break;
|
|
8006940: bf00 nop
|
|
for (i = 0U; i <= 15U; i++)
|
|
8006942: 69bb ldr r3, [r7, #24]
|
|
8006944: 3301 adds r3, #1
|
|
8006946: 61bb str r3, [r7, #24]
|
|
8006948: 69bb ldr r3, [r7, #24]
|
|
800694a: 2b0f cmp r3, #15
|
|
800694c: d9c7 bls.n 80068de <USB_StopHost+0x8e>
|
|
}
|
|
|
|
/* Clear any pending Host interrupts */
|
|
USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK;
|
|
800694e: 697b ldr r3, [r7, #20]
|
|
8006950: f503 6380 add.w r3, r3, #1024 @ 0x400
|
|
8006954: 461a mov r2, r3
|
|
8006956: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
800695a: 6153 str r3, [r2, #20]
|
|
USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
|
|
800695c: 687b ldr r3, [r7, #4]
|
|
800695e: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8006962: 615a str r2, [r3, #20]
|
|
|
|
(void)USB_EnableGlobalInt(USBx);
|
|
8006964: 6878 ldr r0, [r7, #4]
|
|
8006966: f7ff fce9 bl 800633c <USB_EnableGlobalInt>
|
|
|
|
return ret;
|
|
800696a: 7ffb ldrb r3, [r7, #31]
|
|
}
|
|
800696c: 4618 mov r0, r3
|
|
800696e: 3720 adds r7, #32
|
|
8006970: 46bd mov sp, r7
|
|
8006972: bd80 pop {r7, pc}
|
|
|
|
08006974 <USBH_LL_IncTimer>:
|
|
* Increment Host Timer tick
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_IncTimer(USBH_HandleTypeDef *phost)
|
|
{
|
|
8006974: b580 push {r7, lr}
|
|
8006976: b082 sub sp, #8
|
|
8006978: af00 add r7, sp, #0
|
|
800697a: 6078 str r0, [r7, #4]
|
|
phost->Timer++;
|
|
800697c: 687b ldr r3, [r7, #4]
|
|
800697e: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
|
|
8006982: 1c5a adds r2, r3, #1
|
|
8006984: 687b ldr r3, [r7, #4]
|
|
8006986: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4
|
|
USBH_HandleSof(phost);
|
|
800698a: 6878 ldr r0, [r7, #4]
|
|
800698c: f000 f804 bl 8006998 <USBH_HandleSof>
|
|
}
|
|
8006990: bf00 nop
|
|
8006992: 3708 adds r7, #8
|
|
8006994: 46bd mov sp, r7
|
|
8006996: bd80 pop {r7, pc}
|
|
|
|
08006998 <USBH_HandleSof>:
|
|
* Call SOF process
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
static void USBH_HandleSof(USBH_HandleTypeDef *phost)
|
|
{
|
|
8006998: b580 push {r7, lr}
|
|
800699a: b082 sub sp, #8
|
|
800699c: af00 add r7, sp, #0
|
|
800699e: 6078 str r0, [r7, #4]
|
|
if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL))
|
|
80069a0: 687b ldr r3, [r7, #4]
|
|
80069a2: 781b ldrb r3, [r3, #0]
|
|
80069a4: b2db uxtb r3, r3
|
|
80069a6: 2b0b cmp r3, #11
|
|
80069a8: d10a bne.n 80069c0 <USBH_HandleSof+0x28>
|
|
80069aa: 687b ldr r3, [r7, #4]
|
|
80069ac: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80069b0: 2b00 cmp r3, #0
|
|
80069b2: d005 beq.n 80069c0 <USBH_HandleSof+0x28>
|
|
{
|
|
phost->pActiveClass->SOFProcess(phost);
|
|
80069b4: 687b ldr r3, [r7, #4]
|
|
80069b6: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
|
|
80069ba: 699b ldr r3, [r3, #24]
|
|
80069bc: 6878 ldr r0, [r7, #4]
|
|
80069be: 4798 blx r3
|
|
}
|
|
}
|
|
80069c0: bf00 nop
|
|
80069c2: 3708 adds r7, #8
|
|
80069c4: 46bd mov sp, r7
|
|
80069c6: bd80 pop {r7, pc}
|
|
|
|
080069c8 <USBH_LL_PortEnabled>:
|
|
* Port Enabled
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost)
|
|
{
|
|
80069c8: b580 push {r7, lr}
|
|
80069ca: b082 sub sp, #8
|
|
80069cc: af00 add r7, sp, #0
|
|
80069ce: 6078 str r0, [r7, #4]
|
|
phost->device.PortEnabled = 1U;
|
|
80069d0: 687b ldr r3, [r7, #4]
|
|
80069d2: 2201 movs r2, #1
|
|
80069d4: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
80069d8: 2300 movs r3, #0
|
|
80069da: 2200 movs r2, #0
|
|
80069dc: 2101 movs r1, #1
|
|
80069de: 6878 ldr r0, [r7, #4]
|
|
80069e0: f000 f85b bl 8006a9a <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return;
|
|
80069e4: bf00 nop
|
|
}
|
|
80069e6: 3708 adds r7, #8
|
|
80069e8: 46bd mov sp, r7
|
|
80069ea: bd80 pop {r7, pc}
|
|
|
|
080069ec <USBH_LL_PortDisabled>:
|
|
* Port Disabled
|
|
* @param phost: Host Handle
|
|
* @retval None
|
|
*/
|
|
void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost)
|
|
{
|
|
80069ec: b480 push {r7}
|
|
80069ee: b083 sub sp, #12
|
|
80069f0: af00 add r7, sp, #0
|
|
80069f2: 6078 str r0, [r7, #4]
|
|
phost->device.PortEnabled = 0U;
|
|
80069f4: 687b ldr r3, [r7, #4]
|
|
80069f6: 2200 movs r2, #0
|
|
80069f8: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
phost->device.is_disconnected = 1U;
|
|
80069fc: 687b ldr r3, [r7, #4]
|
|
80069fe: 2201 movs r2, #1
|
|
8006a00: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
|
|
return;
|
|
8006a04: bf00 nop
|
|
}
|
|
8006a06: 370c adds r7, #12
|
|
8006a08: 46bd mov sp, r7
|
|
8006a0a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006a0e: 4770 bx lr
|
|
|
|
08006a10 <USBH_LL_Connect>:
|
|
* Handle USB Host connection event
|
|
* @param phost: Host Handle
|
|
* @retval USBH_Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost)
|
|
{
|
|
8006a10: b580 push {r7, lr}
|
|
8006a12: b082 sub sp, #8
|
|
8006a14: af00 add r7, sp, #0
|
|
8006a16: 6078 str r0, [r7, #4]
|
|
phost->device.is_connected = 1U;
|
|
8006a18: 687b ldr r3, [r7, #4]
|
|
8006a1a: 2201 movs r2, #1
|
|
8006a1c: f883 2320 strb.w r2, [r3, #800] @ 0x320
|
|
phost->device.is_disconnected = 0U;
|
|
8006a20: 687b ldr r3, [r7, #4]
|
|
8006a22: 2200 movs r2, #0
|
|
8006a24: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
phost->device.is_ReEnumerated = 0U;
|
|
8006a28: 687b ldr r3, [r7, #4]
|
|
8006a2a: 2200 movs r2, #0
|
|
8006a2c: f883 2322 strb.w r2, [r3, #802] @ 0x322
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8006a30: 2300 movs r3, #0
|
|
8006a32: 2200 movs r2, #0
|
|
8006a34: 2101 movs r1, #1
|
|
8006a36: 6878 ldr r0, [r7, #4]
|
|
8006a38: f000 f82f bl 8006a9a <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
8006a3c: 2300 movs r3, #0
|
|
}
|
|
8006a3e: 4618 mov r0, r3
|
|
8006a40: 3708 adds r7, #8
|
|
8006a42: 46bd mov sp, r7
|
|
8006a44: bd80 pop {r7, pc}
|
|
|
|
08006a46 <USBH_LL_Disconnect>:
|
|
* Handle USB Host disconnection event
|
|
* @param phost: Host Handle
|
|
* @retval USBH_Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost)
|
|
{
|
|
8006a46: b580 push {r7, lr}
|
|
8006a48: b082 sub sp, #8
|
|
8006a4a: af00 add r7, sp, #0
|
|
8006a4c: 6078 str r0, [r7, #4]
|
|
/* update device connection states */
|
|
phost->device.is_disconnected = 1U;
|
|
8006a4e: 687b ldr r3, [r7, #4]
|
|
8006a50: 2201 movs r2, #1
|
|
8006a52: f883 2321 strb.w r2, [r3, #801] @ 0x321
|
|
phost->device.is_connected = 0U;
|
|
8006a56: 687b ldr r3, [r7, #4]
|
|
8006a58: 2200 movs r2, #0
|
|
8006a5a: f883 2320 strb.w r2, [r3, #800] @ 0x320
|
|
phost->device.PortEnabled = 0U;
|
|
8006a5e: 687b ldr r3, [r7, #4]
|
|
8006a60: 2200 movs r2, #0
|
|
8006a62: f883 2323 strb.w r2, [r3, #803] @ 0x323
|
|
|
|
/* Stop Host */
|
|
(void)USBH_LL_Stop(phost);
|
|
8006a66: 6878 ldr r0, [r7, #4]
|
|
8006a68: f001 f992 bl 8007d90 <USBH_LL_Stop>
|
|
|
|
/* FRee Control Pipes */
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
|
|
8006a6c: 687b ldr r3, [r7, #4]
|
|
8006a6e: 791b ldrb r3, [r3, #4]
|
|
8006a70: 4619 mov r1, r3
|
|
8006a72: 6878 ldr r0, [r7, #4]
|
|
8006a74: f000 f847 bl 8006b06 <USBH_FreePipe>
|
|
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
|
|
8006a78: 687b ldr r3, [r7, #4]
|
|
8006a7a: 795b ldrb r3, [r3, #5]
|
|
8006a7c: 4619 mov r1, r3
|
|
8006a7e: 6878 ldr r0, [r7, #4]
|
|
8006a80: f000 f841 bl 8006b06 <USBH_FreePipe>
|
|
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8006a84: 2300 movs r3, #0
|
|
8006a86: 2200 movs r2, #0
|
|
8006a88: 2101 movs r1, #1
|
|
8006a8a: 6878 ldr r0, [r7, #4]
|
|
8006a8c: f000 f805 bl 8006a9a <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
8006a90: 2300 movs r3, #0
|
|
}
|
|
8006a92: 4618 mov r0, r3
|
|
8006a94: 3708 adds r7, #8
|
|
8006a96: 46bd mov sp, r7
|
|
8006a98: bd80 pop {r7, pc}
|
|
|
|
08006a9a <USBH_OS_PutMessage>:
|
|
* @param timeout message event timeout
|
|
* @param priority message event priority
|
|
* @retval None
|
|
*/
|
|
void USBH_OS_PutMessage(USBH_HandleTypeDef *phost, USBH_OSEventTypeDef message, uint32_t timeout, uint32_t priority)
|
|
{
|
|
8006a9a: b580 push {r7, lr}
|
|
8006a9c: b086 sub sp, #24
|
|
8006a9e: af00 add r7, sp, #0
|
|
8006aa0: 60f8 str r0, [r7, #12]
|
|
8006aa2: 607a str r2, [r7, #4]
|
|
8006aa4: 603b str r3, [r7, #0]
|
|
8006aa6: 460b mov r3, r1
|
|
8006aa8: 72fb strb r3, [r7, #11]
|
|
phost->os_msg = (uint32_t)message;
|
|
8006aaa: 7afa ldrb r2, [r7, #11]
|
|
8006aac: 68fb ldr r3, [r7, #12]
|
|
8006aae: f8c3 23e0 str.w r2, [r3, #992] @ 0x3e0
|
|
|
|
#if (osCMSIS < 0x20000U)
|
|
UNUSED(priority);
|
|
|
|
/* Calculate the number of available spaces */
|
|
uint32_t available_spaces = MSGQUEUE_OBJECTS - osMessageWaiting(phost->os_event);
|
|
8006ab2: 68fb ldr r3, [r7, #12]
|
|
8006ab4: f8d3 33d8 ldr.w r3, [r3, #984] @ 0x3d8
|
|
8006ab8: 4618 mov r0, r3
|
|
8006aba: f000 f895 bl 8006be8 <osMessageWaiting>
|
|
8006abe: 4603 mov r3, r0
|
|
8006ac0: f1c3 0310 rsb r3, r3, #16
|
|
8006ac4: 617b str r3, [r7, #20]
|
|
|
|
if (available_spaces != 0U)
|
|
8006ac6: 697b ldr r3, [r7, #20]
|
|
8006ac8: 2b00 cmp r3, #0
|
|
8006aca: d009 beq.n 8006ae0 <USBH_OS_PutMessage+0x46>
|
|
{
|
|
(void)osMessagePut(phost->os_event, phost->os_msg, timeout);
|
|
8006acc: 68fb ldr r3, [r7, #12]
|
|
8006ace: f8d3 03d8 ldr.w r0, [r3, #984] @ 0x3d8
|
|
8006ad2: 68fb ldr r3, [r7, #12]
|
|
8006ad4: f8d3 33e0 ldr.w r3, [r3, #992] @ 0x3e0
|
|
8006ad8: 687a ldr r2, [r7, #4]
|
|
8006ada: 4619 mov r1, r3
|
|
8006adc: f000 f844 bl 8006b68 <osMessagePut>
|
|
if (osMessageQueueGetSpace(phost->os_event) != 0U)
|
|
{
|
|
(void)osMessageQueuePut(phost->os_event, &phost->os_msg, priority, timeout);
|
|
}
|
|
#endif /* (osCMSIS < 0x20000U) */
|
|
}
|
|
8006ae0: bf00 nop
|
|
8006ae2: 3718 adds r7, #24
|
|
8006ae4: 46bd mov sp, r7
|
|
8006ae6: bd80 pop {r7, pc}
|
|
|
|
08006ae8 <USBH_LL_NotifyURBChange>:
|
|
* Notify URB state Change
|
|
* @param phost: Host handle
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost)
|
|
{
|
|
8006ae8: b580 push {r7, lr}
|
|
8006aea: b082 sub sp, #8
|
|
8006aec: af00 add r7, sp, #0
|
|
8006aee: 6078 str r0, [r7, #4]
|
|
#if (USBH_USE_OS == 1U)
|
|
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
|
|
8006af0: 2300 movs r3, #0
|
|
8006af2: 2200 movs r2, #0
|
|
8006af4: 2101 movs r1, #1
|
|
8006af6: 6878 ldr r0, [r7, #4]
|
|
8006af8: f7ff ffcf bl 8006a9a <USBH_OS_PutMessage>
|
|
#endif /* (USBH_USE_OS == 1U) */
|
|
|
|
return USBH_OK;
|
|
8006afc: 2300 movs r3, #0
|
|
}
|
|
8006afe: 4618 mov r0, r3
|
|
8006b00: 3708 adds r7, #8
|
|
8006b02: 46bd mov sp, r7
|
|
8006b04: bd80 pop {r7, pc}
|
|
|
|
08006b06 <USBH_FreePipe>:
|
|
* @param phost: Host Handle
|
|
* @param idx: Pipe number to be freed
|
|
* @retval USBH Status
|
|
*/
|
|
USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx)
|
|
{
|
|
8006b06: b480 push {r7}
|
|
8006b08: b083 sub sp, #12
|
|
8006b0a: af00 add r7, sp, #0
|
|
8006b0c: 6078 str r0, [r7, #4]
|
|
8006b0e: 460b mov r3, r1
|
|
8006b10: 70fb strb r3, [r7, #3]
|
|
if (idx < USBH_MAX_PIPES_NBR)
|
|
8006b12: 78fb ldrb r3, [r7, #3]
|
|
8006b14: 2b0f cmp r3, #15
|
|
8006b16: d80d bhi.n 8006b34 <USBH_FreePipe+0x2e>
|
|
{
|
|
phost->Pipes[idx] &= 0x7FFFU;
|
|
8006b18: 78fb ldrb r3, [r7, #3]
|
|
8006b1a: 687a ldr r2, [r7, #4]
|
|
8006b1c: 33e0 adds r3, #224 @ 0xe0
|
|
8006b1e: 009b lsls r3, r3, #2
|
|
8006b20: 4413 add r3, r2
|
|
8006b22: 685a ldr r2, [r3, #4]
|
|
8006b24: 78fb ldrb r3, [r7, #3]
|
|
8006b26: f3c2 020e ubfx r2, r2, #0, #15
|
|
8006b2a: 6879 ldr r1, [r7, #4]
|
|
8006b2c: 33e0 adds r3, #224 @ 0xe0
|
|
8006b2e: 009b lsls r3, r3, #2
|
|
8006b30: 440b add r3, r1
|
|
8006b32: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
return USBH_OK;
|
|
8006b34: 2300 movs r3, #0
|
|
}
|
|
8006b36: 4618 mov r0, r3
|
|
8006b38: 370c adds r7, #12
|
|
8006b3a: 46bd mov sp, r7
|
|
8006b3c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b40: 4770 bx lr
|
|
|
|
08006b42 <inHandlerMode>:
|
|
#endif
|
|
|
|
|
|
/* Determine whether we are in thread mode or handler mode. */
|
|
static int inHandlerMode (void)
|
|
{
|
|
8006b42: b480 push {r7}
|
|
8006b44: b083 sub sp, #12
|
|
8006b46: af00 add r7, sp, #0
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
|
8006b48: f3ef 8305 mrs r3, IPSR
|
|
8006b4c: 607b str r3, [r7, #4]
|
|
return(result);
|
|
8006b4e: 687b ldr r3, [r7, #4]
|
|
return __get_IPSR() != 0;
|
|
8006b50: 2b00 cmp r3, #0
|
|
8006b52: bf14 ite ne
|
|
8006b54: 2301 movne r3, #1
|
|
8006b56: 2300 moveq r3, #0
|
|
8006b58: b2db uxtb r3, r3
|
|
}
|
|
8006b5a: 4618 mov r0, r3
|
|
8006b5c: 370c adds r7, #12
|
|
8006b5e: 46bd mov sp, r7
|
|
8006b60: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006b64: 4770 bx lr
|
|
...
|
|
|
|
08006b68 <osMessagePut>:
|
|
* @param millisec timeout value or 0 in case of no time-out.
|
|
* @retval status code that indicates the execution status of the function.
|
|
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
|
|
*/
|
|
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
|
|
{
|
|
8006b68: b580 push {r7, lr}
|
|
8006b6a: b086 sub sp, #24
|
|
8006b6c: af00 add r7, sp, #0
|
|
8006b6e: 60f8 str r0, [r7, #12]
|
|
8006b70: 60b9 str r1, [r7, #8]
|
|
8006b72: 607a str r2, [r7, #4]
|
|
portBASE_TYPE taskWoken = pdFALSE;
|
|
8006b74: 2300 movs r3, #0
|
|
8006b76: 613b str r3, [r7, #16]
|
|
TickType_t ticks;
|
|
|
|
ticks = millisec / portTICK_PERIOD_MS;
|
|
8006b78: 687b ldr r3, [r7, #4]
|
|
8006b7a: 617b str r3, [r7, #20]
|
|
if (ticks == 0) {
|
|
8006b7c: 697b ldr r3, [r7, #20]
|
|
8006b7e: 2b00 cmp r3, #0
|
|
8006b80: d101 bne.n 8006b86 <osMessagePut+0x1e>
|
|
ticks = 1;
|
|
8006b82: 2301 movs r3, #1
|
|
8006b84: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
if (inHandlerMode()) {
|
|
8006b86: f7ff ffdc bl 8006b42 <inHandlerMode>
|
|
8006b8a: 4603 mov r3, r0
|
|
8006b8c: 2b00 cmp r3, #0
|
|
8006b8e: d018 beq.n 8006bc2 <osMessagePut+0x5a>
|
|
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
|
|
8006b90: f107 0210 add.w r2, r7, #16
|
|
8006b94: f107 0108 add.w r1, r7, #8
|
|
8006b98: 2300 movs r3, #0
|
|
8006b9a: 68f8 ldr r0, [r7, #12]
|
|
8006b9c: f000 f9c4 bl 8006f28 <xQueueGenericSendFromISR>
|
|
8006ba0: 4603 mov r3, r0
|
|
8006ba2: 2b01 cmp r3, #1
|
|
8006ba4: d001 beq.n 8006baa <osMessagePut+0x42>
|
|
return osErrorOS;
|
|
8006ba6: 23ff movs r3, #255 @ 0xff
|
|
8006ba8: e018 b.n 8006bdc <osMessagePut+0x74>
|
|
}
|
|
portEND_SWITCHING_ISR(taskWoken);
|
|
8006baa: 693b ldr r3, [r7, #16]
|
|
8006bac: 2b00 cmp r3, #0
|
|
8006bae: d014 beq.n 8006bda <osMessagePut+0x72>
|
|
8006bb0: 4b0c ldr r3, [pc, #48] @ (8006be4 <osMessagePut+0x7c>)
|
|
8006bb2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8006bb6: 601a str r2, [r3, #0]
|
|
8006bb8: f3bf 8f4f dsb sy
|
|
8006bbc: f3bf 8f6f isb sy
|
|
8006bc0: e00b b.n 8006bda <osMessagePut+0x72>
|
|
}
|
|
else {
|
|
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
|
|
8006bc2: f107 0108 add.w r1, r7, #8
|
|
8006bc6: 2300 movs r3, #0
|
|
8006bc8: 697a ldr r2, [r7, #20]
|
|
8006bca: 68f8 ldr r0, [r7, #12]
|
|
8006bcc: f000 f8aa bl 8006d24 <xQueueGenericSend>
|
|
8006bd0: 4603 mov r3, r0
|
|
8006bd2: 2b01 cmp r3, #1
|
|
8006bd4: d001 beq.n 8006bda <osMessagePut+0x72>
|
|
return osErrorOS;
|
|
8006bd6: 23ff movs r3, #255 @ 0xff
|
|
8006bd8: e000 b.n 8006bdc <osMessagePut+0x74>
|
|
}
|
|
}
|
|
|
|
return osOK;
|
|
8006bda: 2300 movs r3, #0
|
|
}
|
|
8006bdc: 4618 mov r0, r3
|
|
8006bde: 3718 adds r7, #24
|
|
8006be0: 46bd mov sp, r7
|
|
8006be2: bd80 pop {r7, pc}
|
|
8006be4: e000ed04 .word 0xe000ed04
|
|
|
|
08006be8 <osMessageWaiting>:
|
|
* @brief Get the number of messaged stored in a queue.
|
|
* @param queue_id message queue ID obtained with \ref osMessageCreate.
|
|
* @retval number of messages stored in a queue.
|
|
*/
|
|
uint32_t osMessageWaiting(osMessageQId queue_id)
|
|
{
|
|
8006be8: b580 push {r7, lr}
|
|
8006bea: b082 sub sp, #8
|
|
8006bec: af00 add r7, sp, #0
|
|
8006bee: 6078 str r0, [r7, #4]
|
|
if (inHandlerMode()) {
|
|
8006bf0: f7ff ffa7 bl 8006b42 <inHandlerMode>
|
|
8006bf4: 4603 mov r3, r0
|
|
8006bf6: 2b00 cmp r3, #0
|
|
8006bf8: d004 beq.n 8006c04 <osMessageWaiting+0x1c>
|
|
return uxQueueMessagesWaitingFromISR(queue_id);
|
|
8006bfa: 6878 ldr r0, [r7, #4]
|
|
8006bfc: f000 fa51 bl 80070a2 <uxQueueMessagesWaitingFromISR>
|
|
8006c00: 4603 mov r3, r0
|
|
8006c02: e003 b.n 8006c0c <osMessageWaiting+0x24>
|
|
}
|
|
else
|
|
{
|
|
return uxQueueMessagesWaiting(queue_id);
|
|
8006c04: 6878 ldr r0, [r7, #4]
|
|
8006c06: f000 fa2d bl 8007064 <uxQueueMessagesWaiting>
|
|
8006c0a: 4603 mov r3, r0
|
|
}
|
|
}
|
|
8006c0c: 4618 mov r0, r3
|
|
8006c0e: 3708 adds r7, #8
|
|
8006c10: 46bd mov sp, r7
|
|
8006c12: bd80 pop {r7, pc}
|
|
|
|
08006c14 <vListInsertEnd>:
|
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
8006c14: b480 push {r7}
|
|
8006c16: b085 sub sp, #20
|
|
8006c18: af00 add r7, sp, #0
|
|
8006c1a: 6078 str r0, [r7, #4]
|
|
8006c1c: 6039 str r1, [r7, #0]
|
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
|
8006c1e: 687b ldr r3, [r7, #4]
|
|
8006c20: 685b ldr r3, [r3, #4]
|
|
8006c22: 60fb str r3, [r7, #12]
|
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
|
|
|
/* Insert a new list item into pxList, but rather than sort the list,
|
|
makes the new list item the last item to be removed by a call to
|
|
listGET_OWNER_OF_NEXT_ENTRY(). */
|
|
pxNewListItem->pxNext = pxIndex;
|
|
8006c24: 683b ldr r3, [r7, #0]
|
|
8006c26: 68fa ldr r2, [r7, #12]
|
|
8006c28: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
|
8006c2a: 68fb ldr r3, [r7, #12]
|
|
8006c2c: 689a ldr r2, [r3, #8]
|
|
8006c2e: 683b ldr r3, [r7, #0]
|
|
8006c30: 609a str r2, [r3, #8]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
|
8006c32: 68fb ldr r3, [r7, #12]
|
|
8006c34: 689b ldr r3, [r3, #8]
|
|
8006c36: 683a ldr r2, [r7, #0]
|
|
8006c38: 605a str r2, [r3, #4]
|
|
pxIndex->pxPrevious = pxNewListItem;
|
|
8006c3a: 68fb ldr r3, [r7, #12]
|
|
8006c3c: 683a ldr r2, [r7, #0]
|
|
8006c3e: 609a str r2, [r3, #8]
|
|
|
|
/* Remember which list the item is in. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
8006c40: 683b ldr r3, [r7, #0]
|
|
8006c42: 687a ldr r2, [r7, #4]
|
|
8006c44: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
8006c46: 687b ldr r3, [r7, #4]
|
|
8006c48: 681b ldr r3, [r3, #0]
|
|
8006c4a: 1c5a adds r2, r3, #1
|
|
8006c4c: 687b ldr r3, [r7, #4]
|
|
8006c4e: 601a str r2, [r3, #0]
|
|
}
|
|
8006c50: bf00 nop
|
|
8006c52: 3714 adds r7, #20
|
|
8006c54: 46bd mov sp, r7
|
|
8006c56: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006c5a: 4770 bx lr
|
|
|
|
08006c5c <vListInsert>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
|
|
{
|
|
8006c5c: b480 push {r7}
|
|
8006c5e: b085 sub sp, #20
|
|
8006c60: af00 add r7, sp, #0
|
|
8006c62: 6078 str r0, [r7, #4]
|
|
8006c64: 6039 str r1, [r7, #0]
|
|
ListItem_t *pxIterator;
|
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
|
8006c66: 683b ldr r3, [r7, #0]
|
|
8006c68: 681b ldr r3, [r3, #0]
|
|
8006c6a: 60bb str r3, [r7, #8]
|
|
new list item should be placed after it. This ensures that TCBs which are
|
|
stored in ready lists (all of which have the same xItemValue value) get a
|
|
share of the CPU. However, if the xItemValue is the same as the back marker
|
|
the iteration loop below will not end. Therefore the value is checked
|
|
first, and the algorithm slightly modified if necessary. */
|
|
if( xValueOfInsertion == portMAX_DELAY )
|
|
8006c6c: 68bb ldr r3, [r7, #8]
|
|
8006c6e: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8006c72: d103 bne.n 8006c7c <vListInsert+0x20>
|
|
{
|
|
pxIterator = pxList->xListEnd.pxPrevious;
|
|
8006c74: 687b ldr r3, [r7, #4]
|
|
8006c76: 691b ldr r3, [r3, #16]
|
|
8006c78: 60fb str r3, [r7, #12]
|
|
8006c7a: e00c b.n 8006c96 <vListInsert+0x3a>
|
|
4) Using a queue or semaphore before it has been initialised or
|
|
before the scheduler has been started (are interrupts firing
|
|
before vTaskStartScheduler() has been called?).
|
|
**********************************************************************/
|
|
|
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
|
8006c7c: 687b ldr r3, [r7, #4]
|
|
8006c7e: 3308 adds r3, #8
|
|
8006c80: 60fb str r3, [r7, #12]
|
|
8006c82: e002 b.n 8006c8a <vListInsert+0x2e>
|
|
8006c84: 68fb ldr r3, [r7, #12]
|
|
8006c86: 685b ldr r3, [r3, #4]
|
|
8006c88: 60fb str r3, [r7, #12]
|
|
8006c8a: 68fb ldr r3, [r7, #12]
|
|
8006c8c: 685b ldr r3, [r3, #4]
|
|
8006c8e: 681b ldr r3, [r3, #0]
|
|
8006c90: 68ba ldr r2, [r7, #8]
|
|
8006c92: 429a cmp r2, r3
|
|
8006c94: d2f6 bcs.n 8006c84 <vListInsert+0x28>
|
|
/* There is nothing to do here, just iterating to the wanted
|
|
insertion position. */
|
|
}
|
|
}
|
|
|
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
|
8006c96: 68fb ldr r3, [r7, #12]
|
|
8006c98: 685a ldr r2, [r3, #4]
|
|
8006c9a: 683b ldr r3, [r7, #0]
|
|
8006c9c: 605a str r2, [r3, #4]
|
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
|
8006c9e: 683b ldr r3, [r7, #0]
|
|
8006ca0: 685b ldr r3, [r3, #4]
|
|
8006ca2: 683a ldr r2, [r7, #0]
|
|
8006ca4: 609a str r2, [r3, #8]
|
|
pxNewListItem->pxPrevious = pxIterator;
|
|
8006ca6: 683b ldr r3, [r7, #0]
|
|
8006ca8: 68fa ldr r2, [r7, #12]
|
|
8006caa: 609a str r2, [r3, #8]
|
|
pxIterator->pxNext = pxNewListItem;
|
|
8006cac: 68fb ldr r3, [r7, #12]
|
|
8006cae: 683a ldr r2, [r7, #0]
|
|
8006cb0: 605a str r2, [r3, #4]
|
|
|
|
/* Remember which list the item is in. This allows fast removal of the
|
|
item later. */
|
|
pxNewListItem->pxContainer = pxList;
|
|
8006cb2: 683b ldr r3, [r7, #0]
|
|
8006cb4: 687a ldr r2, [r7, #4]
|
|
8006cb6: 611a str r2, [r3, #16]
|
|
|
|
( pxList->uxNumberOfItems )++;
|
|
8006cb8: 687b ldr r3, [r7, #4]
|
|
8006cba: 681b ldr r3, [r3, #0]
|
|
8006cbc: 1c5a adds r2, r3, #1
|
|
8006cbe: 687b ldr r3, [r7, #4]
|
|
8006cc0: 601a str r2, [r3, #0]
|
|
}
|
|
8006cc2: bf00 nop
|
|
8006cc4: 3714 adds r7, #20
|
|
8006cc6: 46bd mov sp, r7
|
|
8006cc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006ccc: 4770 bx lr
|
|
|
|
08006cce <uxListRemove>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
|
{
|
|
8006cce: b480 push {r7}
|
|
8006cd0: b085 sub sp, #20
|
|
8006cd2: af00 add r7, sp, #0
|
|
8006cd4: 6078 str r0, [r7, #4]
|
|
/* The list item knows which list it is in. Obtain the list from the list
|
|
item. */
|
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
|
8006cd6: 687b ldr r3, [r7, #4]
|
|
8006cd8: 691b ldr r3, [r3, #16]
|
|
8006cda: 60fb str r3, [r7, #12]
|
|
|
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
|
8006cdc: 687b ldr r3, [r7, #4]
|
|
8006cde: 685b ldr r3, [r3, #4]
|
|
8006ce0: 687a ldr r2, [r7, #4]
|
|
8006ce2: 6892 ldr r2, [r2, #8]
|
|
8006ce4: 609a str r2, [r3, #8]
|
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
|
8006ce6: 687b ldr r3, [r7, #4]
|
|
8006ce8: 689b ldr r3, [r3, #8]
|
|
8006cea: 687a ldr r2, [r7, #4]
|
|
8006cec: 6852 ldr r2, [r2, #4]
|
|
8006cee: 605a str r2, [r3, #4]
|
|
|
|
/* Only used during decision coverage testing. */
|
|
mtCOVERAGE_TEST_DELAY();
|
|
|
|
/* Make sure the index is left pointing to a valid item. */
|
|
if( pxList->pxIndex == pxItemToRemove )
|
|
8006cf0: 68fb ldr r3, [r7, #12]
|
|
8006cf2: 685b ldr r3, [r3, #4]
|
|
8006cf4: 687a ldr r2, [r7, #4]
|
|
8006cf6: 429a cmp r2, r3
|
|
8006cf8: d103 bne.n 8006d02 <uxListRemove+0x34>
|
|
{
|
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
|
8006cfa: 687b ldr r3, [r7, #4]
|
|
8006cfc: 689a ldr r2, [r3, #8]
|
|
8006cfe: 68fb ldr r3, [r7, #12]
|
|
8006d00: 605a str r2, [r3, #4]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
pxItemToRemove->pxContainer = NULL;
|
|
8006d02: 687b ldr r3, [r7, #4]
|
|
8006d04: 2200 movs r2, #0
|
|
8006d06: 611a str r2, [r3, #16]
|
|
( pxList->uxNumberOfItems )--;
|
|
8006d08: 68fb ldr r3, [r7, #12]
|
|
8006d0a: 681b ldr r3, [r3, #0]
|
|
8006d0c: 1e5a subs r2, r3, #1
|
|
8006d0e: 68fb ldr r3, [r7, #12]
|
|
8006d10: 601a str r2, [r3, #0]
|
|
|
|
return pxList->uxNumberOfItems;
|
|
8006d12: 68fb ldr r3, [r7, #12]
|
|
8006d14: 681b ldr r3, [r3, #0]
|
|
}
|
|
8006d16: 4618 mov r0, r3
|
|
8006d18: 3714 adds r7, #20
|
|
8006d1a: 46bd mov sp, r7
|
|
8006d1c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8006d20: 4770 bx lr
|
|
...
|
|
|
|
08006d24 <xQueueGenericSend>:
|
|
|
|
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
|
|
{
|
|
8006d24: b580 push {r7, lr}
|
|
8006d26: b08e sub sp, #56 @ 0x38
|
|
8006d28: af00 add r7, sp, #0
|
|
8006d2a: 60f8 str r0, [r7, #12]
|
|
8006d2c: 60b9 str r1, [r7, #8]
|
|
8006d2e: 607a str r2, [r7, #4]
|
|
8006d30: 603b str r3, [r7, #0]
|
|
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
|
|
8006d32: 2300 movs r3, #0
|
|
8006d34: 637b str r3, [r7, #52] @ 0x34
|
|
TimeOut_t xTimeOut;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8006d36: 68fb ldr r3, [r7, #12]
|
|
8006d38: 633b str r3, [r7, #48] @ 0x30
|
|
|
|
configASSERT( pxQueue );
|
|
8006d3a: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006d3c: 2b00 cmp r3, #0
|
|
8006d3e: d10b bne.n 8006d58 <xQueueGenericSend+0x34>
|
|
|
|
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
8006d40: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006d44: f383 8811 msr BASEPRI, r3
|
|
8006d48: f3bf 8f6f isb sy
|
|
8006d4c: f3bf 8f4f dsb sy
|
|
8006d50: 62bb str r3, [r7, #40] @ 0x28
|
|
" msr basepri, %0 \n" \
|
|
" isb \n" \
|
|
" dsb \n" \
|
|
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
}
|
|
8006d52: bf00 nop
|
|
8006d54: bf00 nop
|
|
8006d56: e7fd b.n 8006d54 <xQueueGenericSend+0x30>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
8006d58: 68bb ldr r3, [r7, #8]
|
|
8006d5a: 2b00 cmp r3, #0
|
|
8006d5c: d103 bne.n 8006d66 <xQueueGenericSend+0x42>
|
|
8006d5e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006d60: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006d62: 2b00 cmp r3, #0
|
|
8006d64: d101 bne.n 8006d6a <xQueueGenericSend+0x46>
|
|
8006d66: 2301 movs r3, #1
|
|
8006d68: e000 b.n 8006d6c <xQueueGenericSend+0x48>
|
|
8006d6a: 2300 movs r3, #0
|
|
8006d6c: 2b00 cmp r3, #0
|
|
8006d6e: d10b bne.n 8006d88 <xQueueGenericSend+0x64>
|
|
__asm volatile
|
|
8006d70: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006d74: f383 8811 msr BASEPRI, r3
|
|
8006d78: f3bf 8f6f isb sy
|
|
8006d7c: f3bf 8f4f dsb sy
|
|
8006d80: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8006d82: bf00 nop
|
|
8006d84: bf00 nop
|
|
8006d86: e7fd b.n 8006d84 <xQueueGenericSend+0x60>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
8006d88: 683b ldr r3, [r7, #0]
|
|
8006d8a: 2b02 cmp r3, #2
|
|
8006d8c: d103 bne.n 8006d96 <xQueueGenericSend+0x72>
|
|
8006d8e: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006d90: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006d92: 2b01 cmp r3, #1
|
|
8006d94: d101 bne.n 8006d9a <xQueueGenericSend+0x76>
|
|
8006d96: 2301 movs r3, #1
|
|
8006d98: e000 b.n 8006d9c <xQueueGenericSend+0x78>
|
|
8006d9a: 2300 movs r3, #0
|
|
8006d9c: 2b00 cmp r3, #0
|
|
8006d9e: d10b bne.n 8006db8 <xQueueGenericSend+0x94>
|
|
__asm volatile
|
|
8006da0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006da4: f383 8811 msr BASEPRI, r3
|
|
8006da8: f3bf 8f6f isb sy
|
|
8006dac: f3bf 8f4f dsb sy
|
|
8006db0: 623b str r3, [r7, #32]
|
|
}
|
|
8006db2: bf00 nop
|
|
8006db4: bf00 nop
|
|
8006db6: e7fd b.n 8006db4 <xQueueGenericSend+0x90>
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
{
|
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
|
8006db8: f000 fd7e bl 80078b8 <xTaskGetSchedulerState>
|
|
8006dbc: 4603 mov r3, r0
|
|
8006dbe: 2b00 cmp r3, #0
|
|
8006dc0: d102 bne.n 8006dc8 <xQueueGenericSend+0xa4>
|
|
8006dc2: 687b ldr r3, [r7, #4]
|
|
8006dc4: 2b00 cmp r3, #0
|
|
8006dc6: d101 bne.n 8006dcc <xQueueGenericSend+0xa8>
|
|
8006dc8: 2301 movs r3, #1
|
|
8006dca: e000 b.n 8006dce <xQueueGenericSend+0xaa>
|
|
8006dcc: 2300 movs r3, #0
|
|
8006dce: 2b00 cmp r3, #0
|
|
8006dd0: d10b bne.n 8006dea <xQueueGenericSend+0xc6>
|
|
__asm volatile
|
|
8006dd2: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006dd6: f383 8811 msr BASEPRI, r3
|
|
8006dda: f3bf 8f6f isb sy
|
|
8006dde: f3bf 8f4f dsb sy
|
|
8006de2: 61fb str r3, [r7, #28]
|
|
}
|
|
8006de4: bf00 nop
|
|
8006de6: bf00 nop
|
|
8006de8: e7fd b.n 8006de6 <xQueueGenericSend+0xc2>
|
|
/*lint -save -e904 This function relaxes the coding standard somewhat to
|
|
allow return statements within the function itself. This is done in the
|
|
interest of execution time efficiency. */
|
|
for( ;; )
|
|
{
|
|
taskENTER_CRITICAL();
|
|
8006dea: f000 fe85 bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
/* Is there room on the queue now? The running task must be the
|
|
highest priority task wanting to access the queue. If the head item
|
|
in the queue is to be overwritten then it does not matter if the
|
|
queue is full. */
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
8006dee: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006df0: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8006df2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006df4: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006df6: 429a cmp r2, r3
|
|
8006df8: d302 bcc.n 8006e00 <xQueueGenericSend+0xdc>
|
|
8006dfa: 683b ldr r3, [r7, #0]
|
|
8006dfc: 2b02 cmp r3, #2
|
|
8006dfe: d129 bne.n 8006e54 <xQueueGenericSend+0x130>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
8006e00: 683a ldr r2, [r7, #0]
|
|
8006e02: 68b9 ldr r1, [r7, #8]
|
|
8006e04: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8006e06: f000 f96b bl 80070e0 <prvCopyDataToQueue>
|
|
8006e0a: 62f8 str r0, [r7, #44] @ 0x2c
|
|
|
|
/* If there was a task waiting for data to arrive on the
|
|
queue then unblock it now. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
8006e0c: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006e0e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8006e10: 2b00 cmp r3, #0
|
|
8006e12: d010 beq.n 8006e36 <xQueueGenericSend+0x112>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8006e14: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006e16: 3324 adds r3, #36 @ 0x24
|
|
8006e18: 4618 mov r0, r3
|
|
8006e1a: f000 fc43 bl 80076a4 <xTaskRemoveFromEventList>
|
|
8006e1e: 4603 mov r3, r0
|
|
8006e20: 2b00 cmp r3, #0
|
|
8006e22: d013 beq.n 8006e4c <xQueueGenericSend+0x128>
|
|
{
|
|
/* The unblocked task has a priority higher than
|
|
our own so yield immediately. Yes it is ok to do
|
|
this from within the critical section - the kernel
|
|
takes care of that. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8006e24: 4b3f ldr r3, [pc, #252] @ (8006f24 <xQueueGenericSend+0x200>)
|
|
8006e26: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8006e2a: 601a str r2, [r3, #0]
|
|
8006e2c: f3bf 8f4f dsb sy
|
|
8006e30: f3bf 8f6f isb sy
|
|
8006e34: e00a b.n 8006e4c <xQueueGenericSend+0x128>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else if( xYieldRequired != pdFALSE )
|
|
8006e36: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8006e38: 2b00 cmp r3, #0
|
|
8006e3a: d007 beq.n 8006e4c <xQueueGenericSend+0x128>
|
|
{
|
|
/* This path is a special case that will only get
|
|
executed if the task was holding multiple mutexes and
|
|
the mutexes were given back in an order that is
|
|
different to that in which they were taken. */
|
|
queueYIELD_IF_USING_PREEMPTION();
|
|
8006e3c: 4b39 ldr r3, [pc, #228] @ (8006f24 <xQueueGenericSend+0x200>)
|
|
8006e3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8006e42: 601a str r2, [r3, #0]
|
|
8006e44: f3bf 8f4f dsb sy
|
|
8006e48: f3bf 8f6f isb sy
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
taskEXIT_CRITICAL();
|
|
8006e4c: f000 fe86 bl 8007b5c <vPortExitCritical>
|
|
return pdPASS;
|
|
8006e50: 2301 movs r3, #1
|
|
8006e52: e063 b.n 8006f1c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else
|
|
{
|
|
if( xTicksToWait == ( TickType_t ) 0 )
|
|
8006e54: 687b ldr r3, [r7, #4]
|
|
8006e56: 2b00 cmp r3, #0
|
|
8006e58: d103 bne.n 8006e62 <xQueueGenericSend+0x13e>
|
|
{
|
|
/* The queue was full and no block time is specified (or
|
|
the block time has expired) so leave now. */
|
|
taskEXIT_CRITICAL();
|
|
8006e5a: f000 fe7f bl 8007b5c <vPortExitCritical>
|
|
|
|
/* Return to the original privilege level before exiting
|
|
the function. */
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
8006e5e: 2300 movs r3, #0
|
|
8006e60: e05c b.n 8006f1c <xQueueGenericSend+0x1f8>
|
|
}
|
|
else if( xEntryTimeSet == pdFALSE )
|
|
8006e62: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006e64: 2b00 cmp r3, #0
|
|
8006e66: d106 bne.n 8006e76 <xQueueGenericSend+0x152>
|
|
{
|
|
/* The queue was full and a block time was specified so
|
|
configure the timeout structure. */
|
|
vTaskInternalSetTimeOutState( &xTimeOut );
|
|
8006e68: f107 0314 add.w r3, r7, #20
|
|
8006e6c: 4618 mov r0, r3
|
|
8006e6e: f000 fc7d bl 800776c <vTaskInternalSetTimeOutState>
|
|
xEntryTimeSet = pdTRUE;
|
|
8006e72: 2301 movs r3, #1
|
|
8006e74: 637b str r3, [r7, #52] @ 0x34
|
|
/* Entry time was already set. */
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8006e76: f000 fe71 bl 8007b5c <vPortExitCritical>
|
|
|
|
/* Interrupts and other tasks can send to and receive from the queue
|
|
now the critical section has been exited. */
|
|
|
|
vTaskSuspendAll();
|
|
8006e7a: f000 fa05 bl 8007288 <vTaskSuspendAll>
|
|
prvLockQueue( pxQueue );
|
|
8006e7e: f000 fe3b bl 8007af8 <vPortEnterCritical>
|
|
8006e82: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006e84: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8006e88: b25b sxtb r3, r3
|
|
8006e8a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8006e8e: d103 bne.n 8006e98 <xQueueGenericSend+0x174>
|
|
8006e90: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006e92: 2200 movs r2, #0
|
|
8006e94: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
8006e98: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006e9a: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8006e9e: b25b sxtb r3, r3
|
|
8006ea0: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8006ea4: d103 bne.n 8006eae <xQueueGenericSend+0x18a>
|
|
8006ea6: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006ea8: 2200 movs r2, #0
|
|
8006eaa: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
8006eae: f000 fe55 bl 8007b5c <vPortExitCritical>
|
|
|
|
/* Update the timeout state to see if it has expired yet. */
|
|
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
|
|
8006eb2: 1d3a adds r2, r7, #4
|
|
8006eb4: f107 0314 add.w r3, r7, #20
|
|
8006eb8: 4611 mov r1, r2
|
|
8006eba: 4618 mov r0, r3
|
|
8006ebc: f000 fc6c bl 8007798 <xTaskCheckForTimeOut>
|
|
8006ec0: 4603 mov r3, r0
|
|
8006ec2: 2b00 cmp r3, #0
|
|
8006ec4: d124 bne.n 8006f10 <xQueueGenericSend+0x1ec>
|
|
{
|
|
if( prvIsQueueFull( pxQueue ) != pdFALSE )
|
|
8006ec6: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8006ec8: f000 f9c6 bl 8007258 <prvIsQueueFull>
|
|
8006ecc: 4603 mov r3, r0
|
|
8006ece: 2b00 cmp r3, #0
|
|
8006ed0: d018 beq.n 8006f04 <xQueueGenericSend+0x1e0>
|
|
{
|
|
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
|
|
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
|
|
8006ed2: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006ed4: 3310 adds r3, #16
|
|
8006ed6: 687a ldr r2, [r7, #4]
|
|
8006ed8: 4611 mov r1, r2
|
|
8006eda: 4618 mov r0, r3
|
|
8006edc: f000 fbbc bl 8007658 <vTaskPlaceOnEventList>
|
|
/* Unlocking the queue means queue events can effect the
|
|
event list. It is possible that interrupts occurring now
|
|
remove this task from the event list again - but as the
|
|
scheduler is suspended the task will go onto the pending
|
|
ready last instead of the actual ready list. */
|
|
prvUnlockQueue( pxQueue );
|
|
8006ee0: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8006ee2: f000 f967 bl 80071b4 <prvUnlockQueue>
|
|
/* Resuming the scheduler will move tasks from the pending
|
|
ready list into the ready list - so it is feasible that this
|
|
task is already in a ready list before it yields - in which
|
|
case the yield will not cause a context switch unless there
|
|
is also a higher priority task in the pending ready list. */
|
|
if( xTaskResumeAll() == pdFALSE )
|
|
8006ee6: f000 f9dd bl 80072a4 <xTaskResumeAll>
|
|
8006eea: 4603 mov r3, r0
|
|
8006eec: 2b00 cmp r3, #0
|
|
8006eee: f47f af7c bne.w 8006dea <xQueueGenericSend+0xc6>
|
|
{
|
|
portYIELD_WITHIN_API();
|
|
8006ef2: 4b0c ldr r3, [pc, #48] @ (8006f24 <xQueueGenericSend+0x200>)
|
|
8006ef4: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8006ef8: 601a str r2, [r3, #0]
|
|
8006efa: f3bf 8f4f dsb sy
|
|
8006efe: f3bf 8f6f isb sy
|
|
8006f02: e772 b.n 8006dea <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Try again. */
|
|
prvUnlockQueue( pxQueue );
|
|
8006f04: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8006f06: f000 f955 bl 80071b4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8006f0a: f000 f9cb bl 80072a4 <xTaskResumeAll>
|
|
8006f0e: e76c b.n 8006dea <xQueueGenericSend+0xc6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* The timeout has expired. */
|
|
prvUnlockQueue( pxQueue );
|
|
8006f10: 6b38 ldr r0, [r7, #48] @ 0x30
|
|
8006f12: f000 f94f bl 80071b4 <prvUnlockQueue>
|
|
( void ) xTaskResumeAll();
|
|
8006f16: f000 f9c5 bl 80072a4 <xTaskResumeAll>
|
|
|
|
traceQUEUE_SEND_FAILED( pxQueue );
|
|
return errQUEUE_FULL;
|
|
8006f1a: 2300 movs r3, #0
|
|
}
|
|
} /*lint -restore */
|
|
}
|
|
8006f1c: 4618 mov r0, r3
|
|
8006f1e: 3738 adds r7, #56 @ 0x38
|
|
8006f20: 46bd mov sp, r7
|
|
8006f22: bd80 pop {r7, pc}
|
|
8006f24: e000ed04 .word 0xe000ed04
|
|
|
|
08006f28 <xQueueGenericSendFromISR>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
|
|
{
|
|
8006f28: b580 push {r7, lr}
|
|
8006f2a: b090 sub sp, #64 @ 0x40
|
|
8006f2c: af00 add r7, sp, #0
|
|
8006f2e: 60f8 str r0, [r7, #12]
|
|
8006f30: 60b9 str r1, [r7, #8]
|
|
8006f32: 607a str r2, [r7, #4]
|
|
8006f34: 603b str r3, [r7, #0]
|
|
BaseType_t xReturn;
|
|
UBaseType_t uxSavedInterruptStatus;
|
|
Queue_t * const pxQueue = xQueue;
|
|
8006f36: 68fb ldr r3, [r7, #12]
|
|
8006f38: 63bb str r3, [r7, #56] @ 0x38
|
|
|
|
configASSERT( pxQueue );
|
|
8006f3a: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006f3c: 2b00 cmp r3, #0
|
|
8006f3e: d10b bne.n 8006f58 <xQueueGenericSendFromISR+0x30>
|
|
__asm volatile
|
|
8006f40: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006f44: f383 8811 msr BASEPRI, r3
|
|
8006f48: f3bf 8f6f isb sy
|
|
8006f4c: f3bf 8f4f dsb sy
|
|
8006f50: 62bb str r3, [r7, #40] @ 0x28
|
|
}
|
|
8006f52: bf00 nop
|
|
8006f54: bf00 nop
|
|
8006f56: e7fd b.n 8006f54 <xQueueGenericSendFromISR+0x2c>
|
|
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
|
|
8006f58: 68bb ldr r3, [r7, #8]
|
|
8006f5a: 2b00 cmp r3, #0
|
|
8006f5c: d103 bne.n 8006f66 <xQueueGenericSendFromISR+0x3e>
|
|
8006f5e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006f60: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8006f62: 2b00 cmp r3, #0
|
|
8006f64: d101 bne.n 8006f6a <xQueueGenericSendFromISR+0x42>
|
|
8006f66: 2301 movs r3, #1
|
|
8006f68: e000 b.n 8006f6c <xQueueGenericSendFromISR+0x44>
|
|
8006f6a: 2300 movs r3, #0
|
|
8006f6c: 2b00 cmp r3, #0
|
|
8006f6e: d10b bne.n 8006f88 <xQueueGenericSendFromISR+0x60>
|
|
__asm volatile
|
|
8006f70: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006f74: f383 8811 msr BASEPRI, r3
|
|
8006f78: f3bf 8f6f isb sy
|
|
8006f7c: f3bf 8f4f dsb sy
|
|
8006f80: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
8006f82: bf00 nop
|
|
8006f84: bf00 nop
|
|
8006f86: e7fd b.n 8006f84 <xQueueGenericSendFromISR+0x5c>
|
|
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
|
|
8006f88: 683b ldr r3, [r7, #0]
|
|
8006f8a: 2b02 cmp r3, #2
|
|
8006f8c: d103 bne.n 8006f96 <xQueueGenericSendFromISR+0x6e>
|
|
8006f8e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006f90: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006f92: 2b01 cmp r3, #1
|
|
8006f94: d101 bne.n 8006f9a <xQueueGenericSendFromISR+0x72>
|
|
8006f96: 2301 movs r3, #1
|
|
8006f98: e000 b.n 8006f9c <xQueueGenericSendFromISR+0x74>
|
|
8006f9a: 2300 movs r3, #0
|
|
8006f9c: 2b00 cmp r3, #0
|
|
8006f9e: d10b bne.n 8006fb8 <xQueueGenericSendFromISR+0x90>
|
|
__asm volatile
|
|
8006fa0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006fa4: f383 8811 msr BASEPRI, r3
|
|
8006fa8: f3bf 8f6f isb sy
|
|
8006fac: f3bf 8f4f dsb sy
|
|
8006fb0: 623b str r3, [r7, #32]
|
|
}
|
|
8006fb2: bf00 nop
|
|
8006fb4: bf00 nop
|
|
8006fb6: e7fd b.n 8006fb4 <xQueueGenericSendFromISR+0x8c>
|
|
that have been assigned a priority at or (logically) below the maximum
|
|
system call interrupt priority. FreeRTOS maintains a separate interrupt
|
|
safe API to ensure interrupt entry is as fast and as simple as possible.
|
|
More information (albeit Cortex-M specific) is provided on the following
|
|
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
|
|
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
|
|
8006fb8: f000 fe50 bl 8007c5c <vPortValidateInterruptPriority>
|
|
|
|
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
|
|
{
|
|
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
|
|
|
|
__asm volatile
|
|
8006fbc: f3ef 8211 mrs r2, BASEPRI
|
|
8006fc0: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8006fc4: f383 8811 msr BASEPRI, r3
|
|
8006fc8: f3bf 8f6f isb sy
|
|
8006fcc: f3bf 8f4f dsb sy
|
|
8006fd0: 61fa str r2, [r7, #28]
|
|
8006fd2: 61bb str r3, [r7, #24]
|
|
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
|
|
);
|
|
|
|
/* This return will not be reached but is necessary to prevent compiler
|
|
warnings. */
|
|
return ulOriginalBASEPRI;
|
|
8006fd4: 69fb ldr r3, [r7, #28]
|
|
/* Similar to xQueueGenericSend, except without blocking if there is no room
|
|
in the queue. Also don't directly wake a task that was blocked on a queue
|
|
read, instead return a flag to say whether a context switch is required or
|
|
not (i.e. has a task with a higher priority than us been woken by this
|
|
post). */
|
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
|
8006fd6: 637b str r3, [r7, #52] @ 0x34
|
|
{
|
|
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
|
|
8006fd8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006fda: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8006fdc: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006fde: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8006fe0: 429a cmp r2, r3
|
|
8006fe2: d302 bcc.n 8006fea <xQueueGenericSendFromISR+0xc2>
|
|
8006fe4: 683b ldr r3, [r7, #0]
|
|
8006fe6: 2b02 cmp r3, #2
|
|
8006fe8: d12f bne.n 800704a <xQueueGenericSendFromISR+0x122>
|
|
{
|
|
const int8_t cTxLock = pxQueue->cTxLock;
|
|
8006fea: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006fec: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
8006ff0: f887 3033 strb.w r3, [r7, #51] @ 0x33
|
|
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
8006ff4: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006ff6: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8006ff8: 62fb str r3, [r7, #44] @ 0x2c
|
|
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
|
|
semaphore or mutex. That means prvCopyDataToQueue() cannot result
|
|
in a task disinheriting a priority and prvCopyDataToQueue() can be
|
|
called here even though the disinherit function does not check if
|
|
the scheduler is suspended before accessing the ready lists. */
|
|
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
|
|
8006ffa: 683a ldr r2, [r7, #0]
|
|
8006ffc: 68b9 ldr r1, [r7, #8]
|
|
8006ffe: 6bb8 ldr r0, [r7, #56] @ 0x38
|
|
8007000: f000 f86e bl 80070e0 <prvCopyDataToQueue>
|
|
|
|
/* The event list is not altered if the queue is locked. This will
|
|
be done when the queue is unlocked later. */
|
|
if( cTxLock == queueUNLOCKED )
|
|
8007004: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33
|
|
8007008: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800700c: d112 bne.n 8007034 <xQueueGenericSendFromISR+0x10c>
|
|
}
|
|
}
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
800700e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007010: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8007012: 2b00 cmp r3, #0
|
|
8007014: d016 beq.n 8007044 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
8007016: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007018: 3324 adds r3, #36 @ 0x24
|
|
800701a: 4618 mov r0, r3
|
|
800701c: f000 fb42 bl 80076a4 <xTaskRemoveFromEventList>
|
|
8007020: 4603 mov r3, r0
|
|
8007022: 2b00 cmp r3, #0
|
|
8007024: d00e beq.n 8007044 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
/* The task waiting has a higher priority so record that a
|
|
context switch is required. */
|
|
if( pxHigherPriorityTaskWoken != NULL )
|
|
8007026: 687b ldr r3, [r7, #4]
|
|
8007028: 2b00 cmp r3, #0
|
|
800702a: d00b beq.n 8007044 <xQueueGenericSendFromISR+0x11c>
|
|
{
|
|
*pxHigherPriorityTaskWoken = pdTRUE;
|
|
800702c: 687b ldr r3, [r7, #4]
|
|
800702e: 2201 movs r2, #1
|
|
8007030: 601a str r2, [r3, #0]
|
|
8007032: e007 b.n 8007044 <xQueueGenericSendFromISR+0x11c>
|
|
}
|
|
else
|
|
{
|
|
/* Increment the lock count so the task that unlocks the queue
|
|
knows that data was posted while it was locked. */
|
|
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
|
|
8007034: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
|
|
8007038: 3301 adds r3, #1
|
|
800703a: b2db uxtb r3, r3
|
|
800703c: b25a sxtb r2, r3
|
|
800703e: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8007040: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
|
|
xReturn = pdPASS;
|
|
8007044: 2301 movs r3, #1
|
|
8007046: 63fb str r3, [r7, #60] @ 0x3c
|
|
{
|
|
8007048: e001 b.n 800704e <xQueueGenericSendFromISR+0x126>
|
|
}
|
|
else
|
|
{
|
|
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
|
|
xReturn = errQUEUE_FULL;
|
|
800704a: 2300 movs r3, #0
|
|
800704c: 63fb str r3, [r7, #60] @ 0x3c
|
|
800704e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8007050: 617b str r3, [r7, #20]
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
|
|
{
|
|
__asm volatile
|
|
8007052: 697b ldr r3, [r7, #20]
|
|
8007054: f383 8811 msr BASEPRI, r3
|
|
(
|
|
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
|
|
);
|
|
}
|
|
8007058: bf00 nop
|
|
}
|
|
}
|
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
|
|
|
return xReturn;
|
|
800705a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
}
|
|
800705c: 4618 mov r0, r3
|
|
800705e: 3740 adds r7, #64 @ 0x40
|
|
8007060: 46bd mov sp, r7
|
|
8007062: bd80 pop {r7, pc}
|
|
|
|
08007064 <uxQueueMessagesWaiting>:
|
|
return xReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
|
|
{
|
|
8007064: b580 push {r7, lr}
|
|
8007066: b084 sub sp, #16
|
|
8007068: af00 add r7, sp, #0
|
|
800706a: 6078 str r0, [r7, #4]
|
|
UBaseType_t uxReturn;
|
|
|
|
configASSERT( xQueue );
|
|
800706c: 687b ldr r3, [r7, #4]
|
|
800706e: 2b00 cmp r3, #0
|
|
8007070: d10b bne.n 800708a <uxQueueMessagesWaiting+0x26>
|
|
__asm volatile
|
|
8007072: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007076: f383 8811 msr BASEPRI, r3
|
|
800707a: f3bf 8f6f isb sy
|
|
800707e: f3bf 8f4f dsb sy
|
|
8007082: 60bb str r3, [r7, #8]
|
|
}
|
|
8007084: bf00 nop
|
|
8007086: bf00 nop
|
|
8007088: e7fd b.n 8007086 <uxQueueMessagesWaiting+0x22>
|
|
|
|
taskENTER_CRITICAL();
|
|
800708a: f000 fd35 bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
|
|
800708e: 687b ldr r3, [r7, #4]
|
|
8007090: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8007092: 60fb str r3, [r7, #12]
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8007094: f000 fd62 bl 8007b5c <vPortExitCritical>
|
|
|
|
return uxReturn;
|
|
8007098: 68fb ldr r3, [r7, #12]
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
800709a: 4618 mov r0, r3
|
|
800709c: 3710 adds r7, #16
|
|
800709e: 46bd mov sp, r7
|
|
80070a0: bd80 pop {r7, pc}
|
|
|
|
080070a2 <uxQueueMessagesWaitingFromISR>:
|
|
return uxReturn;
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
|
|
{
|
|
80070a2: b480 push {r7}
|
|
80070a4: b087 sub sp, #28
|
|
80070a6: af00 add r7, sp, #0
|
|
80070a8: 6078 str r0, [r7, #4]
|
|
UBaseType_t uxReturn;
|
|
Queue_t * const pxQueue = xQueue;
|
|
80070aa: 687b ldr r3, [r7, #4]
|
|
80070ac: 617b str r3, [r7, #20]
|
|
|
|
configASSERT( pxQueue );
|
|
80070ae: 697b ldr r3, [r7, #20]
|
|
80070b0: 2b00 cmp r3, #0
|
|
80070b2: d10b bne.n 80070cc <uxQueueMessagesWaitingFromISR+0x2a>
|
|
__asm volatile
|
|
80070b4: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80070b8: f383 8811 msr BASEPRI, r3
|
|
80070bc: f3bf 8f6f isb sy
|
|
80070c0: f3bf 8f4f dsb sy
|
|
80070c4: 60fb str r3, [r7, #12]
|
|
}
|
|
80070c6: bf00 nop
|
|
80070c8: bf00 nop
|
|
80070ca: e7fd b.n 80070c8 <uxQueueMessagesWaitingFromISR+0x26>
|
|
uxReturn = pxQueue->uxMessagesWaiting;
|
|
80070cc: 697b ldr r3, [r7, #20]
|
|
80070ce: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80070d0: 613b str r3, [r7, #16]
|
|
|
|
return uxReturn;
|
|
80070d2: 693b ldr r3, [r7, #16]
|
|
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
|
|
80070d4: 4618 mov r0, r3
|
|
80070d6: 371c adds r7, #28
|
|
80070d8: 46bd mov sp, r7
|
|
80070da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80070de: 4770 bx lr
|
|
|
|
080070e0 <prvCopyDataToQueue>:
|
|
|
|
#endif /* configUSE_MUTEXES */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
|
|
{
|
|
80070e0: b580 push {r7, lr}
|
|
80070e2: b086 sub sp, #24
|
|
80070e4: af00 add r7, sp, #0
|
|
80070e6: 60f8 str r0, [r7, #12]
|
|
80070e8: 60b9 str r1, [r7, #8]
|
|
80070ea: 607a str r2, [r7, #4]
|
|
BaseType_t xReturn = pdFALSE;
|
|
80070ec: 2300 movs r3, #0
|
|
80070ee: 617b str r3, [r7, #20]
|
|
UBaseType_t uxMessagesWaiting;
|
|
|
|
/* This function is called from a critical section. */
|
|
|
|
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
|
|
80070f0: 68fb ldr r3, [r7, #12]
|
|
80070f2: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80070f4: 613b str r3, [r7, #16]
|
|
|
|
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
|
|
80070f6: 68fb ldr r3, [r7, #12]
|
|
80070f8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80070fa: 2b00 cmp r3, #0
|
|
80070fc: d10d bne.n 800711a <prvCopyDataToQueue+0x3a>
|
|
{
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
{
|
|
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
|
|
80070fe: 68fb ldr r3, [r7, #12]
|
|
8007100: 681b ldr r3, [r3, #0]
|
|
8007102: 2b00 cmp r3, #0
|
|
8007104: d14d bne.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* The mutex is no longer being held. */
|
|
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
|
|
8007106: 68fb ldr r3, [r7, #12]
|
|
8007108: 689b ldr r3, [r3, #8]
|
|
800710a: 4618 mov r0, r3
|
|
800710c: f000 fbf2 bl 80078f4 <xTaskPriorityDisinherit>
|
|
8007110: 6178 str r0, [r7, #20]
|
|
pxQueue->u.xSemaphore.xMutexHolder = NULL;
|
|
8007112: 68fb ldr r3, [r7, #12]
|
|
8007114: 2200 movs r2, #0
|
|
8007116: 609a str r2, [r3, #8]
|
|
8007118: e043 b.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
#endif /* configUSE_MUTEXES */
|
|
}
|
|
else if( xPosition == queueSEND_TO_BACK )
|
|
800711a: 687b ldr r3, [r7, #4]
|
|
800711c: 2b00 cmp r3, #0
|
|
800711e: d119 bne.n 8007154 <prvCopyDataToQueue+0x74>
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
|
|
8007120: 68fb ldr r3, [r7, #12]
|
|
8007122: 6858 ldr r0, [r3, #4]
|
|
8007124: 68fb ldr r3, [r7, #12]
|
|
8007126: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007128: 461a mov r2, r3
|
|
800712a: 68b9 ldr r1, [r7, #8]
|
|
800712c: f000 fea4 bl 8007e78 <memcpy>
|
|
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
|
|
8007130: 68fb ldr r3, [r7, #12]
|
|
8007132: 685a ldr r2, [r3, #4]
|
|
8007134: 68fb ldr r3, [r7, #12]
|
|
8007136: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007138: 441a add r2, r3
|
|
800713a: 68fb ldr r3, [r7, #12]
|
|
800713c: 605a str r2, [r3, #4]
|
|
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
800713e: 68fb ldr r3, [r7, #12]
|
|
8007140: 685a ldr r2, [r3, #4]
|
|
8007142: 68fb ldr r3, [r7, #12]
|
|
8007144: 689b ldr r3, [r3, #8]
|
|
8007146: 429a cmp r2, r3
|
|
8007148: d32b bcc.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
pxQueue->pcWriteTo = pxQueue->pcHead;
|
|
800714a: 68fb ldr r3, [r7, #12]
|
|
800714c: 681a ldr r2, [r3, #0]
|
|
800714e: 68fb ldr r3, [r7, #12]
|
|
8007150: 605a str r2, [r3, #4]
|
|
8007152: e026 b.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
else
|
|
{
|
|
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
|
|
8007154: 68fb ldr r3, [r7, #12]
|
|
8007156: 68d8 ldr r0, [r3, #12]
|
|
8007158: 68fb ldr r3, [r7, #12]
|
|
800715a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800715c: 461a mov r2, r3
|
|
800715e: 68b9 ldr r1, [r7, #8]
|
|
8007160: f000 fe8a bl 8007e78 <memcpy>
|
|
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
|
|
8007164: 68fb ldr r3, [r7, #12]
|
|
8007166: 68da ldr r2, [r3, #12]
|
|
8007168: 68fb ldr r3, [r7, #12]
|
|
800716a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800716c: 425b negs r3, r3
|
|
800716e: 441a add r2, r3
|
|
8007170: 68fb ldr r3, [r7, #12]
|
|
8007172: 60da str r2, [r3, #12]
|
|
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
|
|
8007174: 68fb ldr r3, [r7, #12]
|
|
8007176: 68da ldr r2, [r3, #12]
|
|
8007178: 68fb ldr r3, [r7, #12]
|
|
800717a: 681b ldr r3, [r3, #0]
|
|
800717c: 429a cmp r2, r3
|
|
800717e: d207 bcs.n 8007190 <prvCopyDataToQueue+0xb0>
|
|
{
|
|
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
|
|
8007180: 68fb ldr r3, [r7, #12]
|
|
8007182: 689a ldr r2, [r3, #8]
|
|
8007184: 68fb ldr r3, [r7, #12]
|
|
8007186: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8007188: 425b negs r3, r3
|
|
800718a: 441a add r2, r3
|
|
800718c: 68fb ldr r3, [r7, #12]
|
|
800718e: 60da str r2, [r3, #12]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
if( xPosition == queueOVERWRITE )
|
|
8007190: 687b ldr r3, [r7, #4]
|
|
8007192: 2b02 cmp r3, #2
|
|
8007194: d105 bne.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
|
|
8007196: 693b ldr r3, [r7, #16]
|
|
8007198: 2b00 cmp r3, #0
|
|
800719a: d002 beq.n 80071a2 <prvCopyDataToQueue+0xc2>
|
|
{
|
|
/* An item is not being added but overwritten, so subtract
|
|
one from the recorded number of items in the queue so when
|
|
one is added again below the number of recorded items remains
|
|
correct. */
|
|
--uxMessagesWaiting;
|
|
800719c: 693b ldr r3, [r7, #16]
|
|
800719e: 3b01 subs r3, #1
|
|
80071a0: 613b str r3, [r7, #16]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
|
|
80071a2: 693b ldr r3, [r7, #16]
|
|
80071a4: 1c5a adds r2, r3, #1
|
|
80071a6: 68fb ldr r3, [r7, #12]
|
|
80071a8: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
return xReturn;
|
|
80071aa: 697b ldr r3, [r7, #20]
|
|
}
|
|
80071ac: 4618 mov r0, r3
|
|
80071ae: 3718 adds r7, #24
|
|
80071b0: 46bd mov sp, r7
|
|
80071b2: bd80 pop {r7, pc}
|
|
|
|
080071b4 <prvUnlockQueue>:
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvUnlockQueue( Queue_t * const pxQueue )
|
|
{
|
|
80071b4: b580 push {r7, lr}
|
|
80071b6: b084 sub sp, #16
|
|
80071b8: af00 add r7, sp, #0
|
|
80071ba: 6078 str r0, [r7, #4]
|
|
|
|
/* The lock counts contains the number of extra data items placed or
|
|
removed from the queue while the queue was locked. When a queue is
|
|
locked items can be added or removed, but the event lists cannot be
|
|
updated. */
|
|
taskENTER_CRITICAL();
|
|
80071bc: f000 fc9c bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
int8_t cTxLock = pxQueue->cTxLock;
|
|
80071c0: 687b ldr r3, [r7, #4]
|
|
80071c2: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
|
|
80071c6: 73fb strb r3, [r7, #15]
|
|
|
|
/* See if data was added to the queue while it was locked. */
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
80071c8: e011 b.n 80071ee <prvUnlockQueue+0x3a>
|
|
}
|
|
#else /* configUSE_QUEUE_SETS */
|
|
{
|
|
/* Tasks that are removed from the event list will get added to
|
|
the pending ready list as the scheduler is still suspended. */
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
|
|
80071ca: 687b ldr r3, [r7, #4]
|
|
80071cc: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
80071ce: 2b00 cmp r3, #0
|
|
80071d0: d012 beq.n 80071f8 <prvUnlockQueue+0x44>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
|
|
80071d2: 687b ldr r3, [r7, #4]
|
|
80071d4: 3324 adds r3, #36 @ 0x24
|
|
80071d6: 4618 mov r0, r3
|
|
80071d8: f000 fa64 bl 80076a4 <xTaskRemoveFromEventList>
|
|
80071dc: 4603 mov r3, r0
|
|
80071de: 2b00 cmp r3, #0
|
|
80071e0: d001 beq.n 80071e6 <prvUnlockQueue+0x32>
|
|
{
|
|
/* The task waiting has a higher priority so record that
|
|
a context switch is required. */
|
|
vTaskMissedYield();
|
|
80071e2: f000 fb3d bl 8007860 <vTaskMissedYield>
|
|
break;
|
|
}
|
|
}
|
|
#endif /* configUSE_QUEUE_SETS */
|
|
|
|
--cTxLock;
|
|
80071e6: 7bfb ldrb r3, [r7, #15]
|
|
80071e8: 3b01 subs r3, #1
|
|
80071ea: b2db uxtb r3, r3
|
|
80071ec: 73fb strb r3, [r7, #15]
|
|
while( cTxLock > queueLOCKED_UNMODIFIED )
|
|
80071ee: f997 300f ldrsb.w r3, [r7, #15]
|
|
80071f2: 2b00 cmp r3, #0
|
|
80071f4: dce9 bgt.n 80071ca <prvUnlockQueue+0x16>
|
|
80071f6: e000 b.n 80071fa <prvUnlockQueue+0x46>
|
|
break;
|
|
80071f8: bf00 nop
|
|
}
|
|
|
|
pxQueue->cTxLock = queueUNLOCKED;
|
|
80071fa: 687b ldr r3, [r7, #4]
|
|
80071fc: 22ff movs r2, #255 @ 0xff
|
|
80071fe: f883 2045 strb.w r2, [r3, #69] @ 0x45
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
8007202: f000 fcab bl 8007b5c <vPortExitCritical>
|
|
|
|
/* Do the same for the Rx lock. */
|
|
taskENTER_CRITICAL();
|
|
8007206: f000 fc77 bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
int8_t cRxLock = pxQueue->cRxLock;
|
|
800720a: 687b ldr r3, [r7, #4]
|
|
800720c: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
|
|
8007210: 73bb strb r3, [r7, #14]
|
|
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
8007212: e011 b.n 8007238 <prvUnlockQueue+0x84>
|
|
{
|
|
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
|
|
8007214: 687b ldr r3, [r7, #4]
|
|
8007216: 691b ldr r3, [r3, #16]
|
|
8007218: 2b00 cmp r3, #0
|
|
800721a: d012 beq.n 8007242 <prvUnlockQueue+0x8e>
|
|
{
|
|
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
|
|
800721c: 687b ldr r3, [r7, #4]
|
|
800721e: 3310 adds r3, #16
|
|
8007220: 4618 mov r0, r3
|
|
8007222: f000 fa3f bl 80076a4 <xTaskRemoveFromEventList>
|
|
8007226: 4603 mov r3, r0
|
|
8007228: 2b00 cmp r3, #0
|
|
800722a: d001 beq.n 8007230 <prvUnlockQueue+0x7c>
|
|
{
|
|
vTaskMissedYield();
|
|
800722c: f000 fb18 bl 8007860 <vTaskMissedYield>
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
--cRxLock;
|
|
8007230: 7bbb ldrb r3, [r7, #14]
|
|
8007232: 3b01 subs r3, #1
|
|
8007234: b2db uxtb r3, r3
|
|
8007236: 73bb strb r3, [r7, #14]
|
|
while( cRxLock > queueLOCKED_UNMODIFIED )
|
|
8007238: f997 300e ldrsb.w r3, [r7, #14]
|
|
800723c: 2b00 cmp r3, #0
|
|
800723e: dce9 bgt.n 8007214 <prvUnlockQueue+0x60>
|
|
8007240: e000 b.n 8007244 <prvUnlockQueue+0x90>
|
|
}
|
|
else
|
|
{
|
|
break;
|
|
8007242: bf00 nop
|
|
}
|
|
}
|
|
|
|
pxQueue->cRxLock = queueUNLOCKED;
|
|
8007244: 687b ldr r3, [r7, #4]
|
|
8007246: 22ff movs r2, #255 @ 0xff
|
|
8007248: f883 2044 strb.w r2, [r3, #68] @ 0x44
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800724c: f000 fc86 bl 8007b5c <vPortExitCritical>
|
|
}
|
|
8007250: bf00 nop
|
|
8007252: 3710 adds r7, #16
|
|
8007254: 46bd mov sp, r7
|
|
8007256: bd80 pop {r7, pc}
|
|
|
|
08007258 <prvIsQueueFull>:
|
|
return xReturn;
|
|
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
|
|
{
|
|
8007258: b580 push {r7, lr}
|
|
800725a: b084 sub sp, #16
|
|
800725c: af00 add r7, sp, #0
|
|
800725e: 6078 str r0, [r7, #4]
|
|
BaseType_t xReturn;
|
|
|
|
taskENTER_CRITICAL();
|
|
8007260: f000 fc4a bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
|
|
8007264: 687b ldr r3, [r7, #4]
|
|
8007266: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8007268: 687b ldr r3, [r7, #4]
|
|
800726a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800726c: 429a cmp r2, r3
|
|
800726e: d102 bne.n 8007276 <prvIsQueueFull+0x1e>
|
|
{
|
|
xReturn = pdTRUE;
|
|
8007270: 2301 movs r3, #1
|
|
8007272: 60fb str r3, [r7, #12]
|
|
8007274: e001 b.n 800727a <prvIsQueueFull+0x22>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
8007276: 2300 movs r3, #0
|
|
8007278: 60fb str r3, [r7, #12]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800727a: f000 fc6f bl 8007b5c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800727e: 68fb ldr r3, [r7, #12]
|
|
}
|
|
8007280: 4618 mov r0, r3
|
|
8007282: 3710 adds r7, #16
|
|
8007284: 46bd mov sp, r7
|
|
8007286: bd80 pop {r7, pc}
|
|
|
|
08007288 <vTaskSuspendAll>:
|
|
vPortEndScheduler();
|
|
}
|
|
/*----------------------------------------------------------*/
|
|
|
|
void vTaskSuspendAll( void )
|
|
{
|
|
8007288: b480 push {r7}
|
|
800728a: af00 add r7, sp, #0
|
|
do not otherwise exhibit real time behaviour. */
|
|
portSOFTWARE_BARRIER();
|
|
|
|
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
|
|
is used to allow calls to vTaskSuspendAll() to nest. */
|
|
++uxSchedulerSuspended;
|
|
800728c: 4b04 ldr r3, [pc, #16] @ (80072a0 <vTaskSuspendAll+0x18>)
|
|
800728e: 681b ldr r3, [r3, #0]
|
|
8007290: 3301 adds r3, #1
|
|
8007292: 4a03 ldr r2, [pc, #12] @ (80072a0 <vTaskSuspendAll+0x18>)
|
|
8007294: 6013 str r3, [r2, #0]
|
|
|
|
/* Enforces ordering for ports and optimised compilers that may otherwise place
|
|
the above increment elsewhere. */
|
|
portMEMORY_BARRIER();
|
|
}
|
|
8007296: bf00 nop
|
|
8007298: 46bd mov sp, r7
|
|
800729a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800729e: 4770 bx lr
|
|
80072a0: 200003bc .word 0x200003bc
|
|
|
|
080072a4 <xTaskResumeAll>:
|
|
|
|
#endif /* configUSE_TICKLESS_IDLE */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskResumeAll( void )
|
|
{
|
|
80072a4: b580 push {r7, lr}
|
|
80072a6: b084 sub sp, #16
|
|
80072a8: af00 add r7, sp, #0
|
|
TCB_t *pxTCB = NULL;
|
|
80072aa: 2300 movs r3, #0
|
|
80072ac: 60fb str r3, [r7, #12]
|
|
BaseType_t xAlreadyYielded = pdFALSE;
|
|
80072ae: 2300 movs r3, #0
|
|
80072b0: 60bb str r3, [r7, #8]
|
|
|
|
/* If uxSchedulerSuspended is zero then this function does not match a
|
|
previous call to vTaskSuspendAll(). */
|
|
configASSERT( uxSchedulerSuspended );
|
|
80072b2: 4b42 ldr r3, [pc, #264] @ (80073bc <xTaskResumeAll+0x118>)
|
|
80072b4: 681b ldr r3, [r3, #0]
|
|
80072b6: 2b00 cmp r3, #0
|
|
80072b8: d10b bne.n 80072d2 <xTaskResumeAll+0x2e>
|
|
__asm volatile
|
|
80072ba: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80072be: f383 8811 msr BASEPRI, r3
|
|
80072c2: f3bf 8f6f isb sy
|
|
80072c6: f3bf 8f4f dsb sy
|
|
80072ca: 603b str r3, [r7, #0]
|
|
}
|
|
80072cc: bf00 nop
|
|
80072ce: bf00 nop
|
|
80072d0: e7fd b.n 80072ce <xTaskResumeAll+0x2a>
|
|
/* It is possible that an ISR caused a task to be removed from an event
|
|
list while the scheduler was suspended. If this was the case then the
|
|
removed task will have been added to the xPendingReadyList. Once the
|
|
scheduler has been resumed it is safe to move all the pending ready
|
|
tasks from this list into their appropriate ready list. */
|
|
taskENTER_CRITICAL();
|
|
80072d2: f000 fc11 bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
--uxSchedulerSuspended;
|
|
80072d6: 4b39 ldr r3, [pc, #228] @ (80073bc <xTaskResumeAll+0x118>)
|
|
80072d8: 681b ldr r3, [r3, #0]
|
|
80072da: 3b01 subs r3, #1
|
|
80072dc: 4a37 ldr r2, [pc, #220] @ (80073bc <xTaskResumeAll+0x118>)
|
|
80072de: 6013 str r3, [r2, #0]
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
80072e0: 4b36 ldr r3, [pc, #216] @ (80073bc <xTaskResumeAll+0x118>)
|
|
80072e2: 681b ldr r3, [r3, #0]
|
|
80072e4: 2b00 cmp r3, #0
|
|
80072e6: d161 bne.n 80073ac <xTaskResumeAll+0x108>
|
|
{
|
|
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
|
|
80072e8: 4b35 ldr r3, [pc, #212] @ (80073c0 <xTaskResumeAll+0x11c>)
|
|
80072ea: 681b ldr r3, [r3, #0]
|
|
80072ec: 2b00 cmp r3, #0
|
|
80072ee: d05d beq.n 80073ac <xTaskResumeAll+0x108>
|
|
{
|
|
/* Move any readied tasks from the pending list into the
|
|
appropriate ready list. */
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
80072f0: e02e b.n 8007350 <xTaskResumeAll+0xac>
|
|
{
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
80072f2: 4b34 ldr r3, [pc, #208] @ (80073c4 <xTaskResumeAll+0x120>)
|
|
80072f4: 68db ldr r3, [r3, #12]
|
|
80072f6: 68db ldr r3, [r3, #12]
|
|
80072f8: 60fb str r3, [r7, #12]
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
80072fa: 68fb ldr r3, [r7, #12]
|
|
80072fc: 3318 adds r3, #24
|
|
80072fe: 4618 mov r0, r3
|
|
8007300: f7ff fce5 bl 8006cce <uxListRemove>
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
8007304: 68fb ldr r3, [r7, #12]
|
|
8007306: 3304 adds r3, #4
|
|
8007308: 4618 mov r0, r3
|
|
800730a: f7ff fce0 bl 8006cce <uxListRemove>
|
|
prvAddTaskToReadyList( pxTCB );
|
|
800730e: 68fb ldr r3, [r7, #12]
|
|
8007310: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007312: 2201 movs r2, #1
|
|
8007314: 409a lsls r2, r3
|
|
8007316: 4b2c ldr r3, [pc, #176] @ (80073c8 <xTaskResumeAll+0x124>)
|
|
8007318: 681b ldr r3, [r3, #0]
|
|
800731a: 4313 orrs r3, r2
|
|
800731c: 4a2a ldr r2, [pc, #168] @ (80073c8 <xTaskResumeAll+0x124>)
|
|
800731e: 6013 str r3, [r2, #0]
|
|
8007320: 68fb ldr r3, [r7, #12]
|
|
8007322: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8007324: 4613 mov r3, r2
|
|
8007326: 009b lsls r3, r3, #2
|
|
8007328: 4413 add r3, r2
|
|
800732a: 009b lsls r3, r3, #2
|
|
800732c: 4a27 ldr r2, [pc, #156] @ (80073cc <xTaskResumeAll+0x128>)
|
|
800732e: 441a add r2, r3
|
|
8007330: 68fb ldr r3, [r7, #12]
|
|
8007332: 3304 adds r3, #4
|
|
8007334: 4619 mov r1, r3
|
|
8007336: 4610 mov r0, r2
|
|
8007338: f7ff fc6c bl 8006c14 <vListInsertEnd>
|
|
|
|
/* If the moved task has a priority higher than the current
|
|
task then a yield must be performed. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
800733c: 68fb ldr r3, [r7, #12]
|
|
800733e: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8007340: 4b23 ldr r3, [pc, #140] @ (80073d0 <xTaskResumeAll+0x12c>)
|
|
8007342: 681b ldr r3, [r3, #0]
|
|
8007344: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007346: 429a cmp r2, r3
|
|
8007348: d302 bcc.n 8007350 <xTaskResumeAll+0xac>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
800734a: 4b22 ldr r3, [pc, #136] @ (80073d4 <xTaskResumeAll+0x130>)
|
|
800734c: 2201 movs r2, #1
|
|
800734e: 601a str r2, [r3, #0]
|
|
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
|
|
8007350: 4b1c ldr r3, [pc, #112] @ (80073c4 <xTaskResumeAll+0x120>)
|
|
8007352: 681b ldr r3, [r3, #0]
|
|
8007354: 2b00 cmp r3, #0
|
|
8007356: d1cc bne.n 80072f2 <xTaskResumeAll+0x4e>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( pxTCB != NULL )
|
|
8007358: 68fb ldr r3, [r7, #12]
|
|
800735a: 2b00 cmp r3, #0
|
|
800735c: d001 beq.n 8007362 <xTaskResumeAll+0xbe>
|
|
which may have prevented the next unblock time from being
|
|
re-calculated, in which case re-calculate it now. Mainly
|
|
important for low power tickless implementations, where
|
|
this can prevent an unnecessary exit from low power
|
|
state. */
|
|
prvResetNextTaskUnblockTime();
|
|
800735e: f000 fa8b bl 8007878 <prvResetNextTaskUnblockTime>
|
|
/* If any ticks occurred while the scheduler was suspended then
|
|
they should be processed now. This ensures the tick count does
|
|
not slip, and that any delayed tasks are resumed at the correct
|
|
time. */
|
|
{
|
|
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
|
|
8007362: 4b1d ldr r3, [pc, #116] @ (80073d8 <xTaskResumeAll+0x134>)
|
|
8007364: 681b ldr r3, [r3, #0]
|
|
8007366: 607b str r3, [r7, #4]
|
|
|
|
if( xPendedCounts > ( TickType_t ) 0U )
|
|
8007368: 687b ldr r3, [r7, #4]
|
|
800736a: 2b00 cmp r3, #0
|
|
800736c: d010 beq.n 8007390 <xTaskResumeAll+0xec>
|
|
{
|
|
do
|
|
{
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
800736e: f000 f837 bl 80073e0 <xTaskIncrementTick>
|
|
8007372: 4603 mov r3, r0
|
|
8007374: 2b00 cmp r3, #0
|
|
8007376: d002 beq.n 800737e <xTaskResumeAll+0xda>
|
|
{
|
|
xYieldPending = pdTRUE;
|
|
8007378: 4b16 ldr r3, [pc, #88] @ (80073d4 <xTaskResumeAll+0x130>)
|
|
800737a: 2201 movs r2, #1
|
|
800737c: 601a str r2, [r3, #0]
|
|
}
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
--xPendedCounts;
|
|
800737e: 687b ldr r3, [r7, #4]
|
|
8007380: 3b01 subs r3, #1
|
|
8007382: 607b str r3, [r7, #4]
|
|
} while( xPendedCounts > ( TickType_t ) 0U );
|
|
8007384: 687b ldr r3, [r7, #4]
|
|
8007386: 2b00 cmp r3, #0
|
|
8007388: d1f1 bne.n 800736e <xTaskResumeAll+0xca>
|
|
|
|
xPendedTicks = 0;
|
|
800738a: 4b13 ldr r3, [pc, #76] @ (80073d8 <xTaskResumeAll+0x134>)
|
|
800738c: 2200 movs r2, #0
|
|
800738e: 601a str r2, [r3, #0]
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
|
|
if( xYieldPending != pdFALSE )
|
|
8007390: 4b10 ldr r3, [pc, #64] @ (80073d4 <xTaskResumeAll+0x130>)
|
|
8007392: 681b ldr r3, [r3, #0]
|
|
8007394: 2b00 cmp r3, #0
|
|
8007396: d009 beq.n 80073ac <xTaskResumeAll+0x108>
|
|
{
|
|
#if( configUSE_PREEMPTION != 0 )
|
|
{
|
|
xAlreadyYielded = pdTRUE;
|
|
8007398: 2301 movs r3, #1
|
|
800739a: 60bb str r3, [r7, #8]
|
|
}
|
|
#endif
|
|
taskYIELD_IF_USING_PREEMPTION();
|
|
800739c: 4b0f ldr r3, [pc, #60] @ (80073dc <xTaskResumeAll+0x138>)
|
|
800739e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
80073a2: 601a str r2, [r3, #0]
|
|
80073a4: f3bf 8f4f dsb sy
|
|
80073a8: f3bf 8f6f isb sy
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
80073ac: f000 fbd6 bl 8007b5c <vPortExitCritical>
|
|
|
|
return xAlreadyYielded;
|
|
80073b0: 68bb ldr r3, [r7, #8]
|
|
}
|
|
80073b2: 4618 mov r0, r3
|
|
80073b4: 3710 adds r7, #16
|
|
80073b6: 46bd mov sp, r7
|
|
80073b8: bd80 pop {r7, pc}
|
|
80073ba: bf00 nop
|
|
80073bc: 200003bc .word 0x200003bc
|
|
80073c0: 2000039c .word 0x2000039c
|
|
80073c4: 20000374 .word 0x20000374
|
|
80073c8: 200003a4 .word 0x200003a4
|
|
80073cc: 200002e0 .word 0x200002e0
|
|
80073d0: 200002dc .word 0x200002dc
|
|
80073d4: 200003b0 .word 0x200003b0
|
|
80073d8: 200003ac .word 0x200003ac
|
|
80073dc: e000ed04 .word 0xe000ed04
|
|
|
|
080073e0 <xTaskIncrementTick>:
|
|
|
|
#endif /* INCLUDE_xTaskAbortDelay */
|
|
/*----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskIncrementTick( void )
|
|
{
|
|
80073e0: b580 push {r7, lr}
|
|
80073e2: b086 sub sp, #24
|
|
80073e4: af00 add r7, sp, #0
|
|
TCB_t * pxTCB;
|
|
TickType_t xItemValue;
|
|
BaseType_t xSwitchRequired = pdFALSE;
|
|
80073e6: 2300 movs r3, #0
|
|
80073e8: 617b str r3, [r7, #20]
|
|
|
|
/* Called by the portable layer each time a tick interrupt occurs.
|
|
Increments the tick then checks to see if the new tick value will cause any
|
|
tasks to be unblocked. */
|
|
traceTASK_INCREMENT_TICK( xTickCount );
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
80073ea: 4b4f ldr r3, [pc, #316] @ (8007528 <xTaskIncrementTick+0x148>)
|
|
80073ec: 681b ldr r3, [r3, #0]
|
|
80073ee: 2b00 cmp r3, #0
|
|
80073f0: f040 808f bne.w 8007512 <xTaskIncrementTick+0x132>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this
|
|
block. */
|
|
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
|
|
80073f4: 4b4d ldr r3, [pc, #308] @ (800752c <xTaskIncrementTick+0x14c>)
|
|
80073f6: 681b ldr r3, [r3, #0]
|
|
80073f8: 3301 adds r3, #1
|
|
80073fa: 613b str r3, [r7, #16]
|
|
|
|
/* Increment the RTOS tick, switching the delayed and overflowed
|
|
delayed lists if it wraps to 0. */
|
|
xTickCount = xConstTickCount;
|
|
80073fc: 4a4b ldr r2, [pc, #300] @ (800752c <xTaskIncrementTick+0x14c>)
|
|
80073fe: 693b ldr r3, [r7, #16]
|
|
8007400: 6013 str r3, [r2, #0]
|
|
|
|
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
|
|
8007402: 693b ldr r3, [r7, #16]
|
|
8007404: 2b00 cmp r3, #0
|
|
8007406: d121 bne.n 800744c <xTaskIncrementTick+0x6c>
|
|
{
|
|
taskSWITCH_DELAYED_LISTS();
|
|
8007408: 4b49 ldr r3, [pc, #292] @ (8007530 <xTaskIncrementTick+0x150>)
|
|
800740a: 681b ldr r3, [r3, #0]
|
|
800740c: 681b ldr r3, [r3, #0]
|
|
800740e: 2b00 cmp r3, #0
|
|
8007410: d00b beq.n 800742a <xTaskIncrementTick+0x4a>
|
|
__asm volatile
|
|
8007412: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007416: f383 8811 msr BASEPRI, r3
|
|
800741a: f3bf 8f6f isb sy
|
|
800741e: f3bf 8f4f dsb sy
|
|
8007422: 603b str r3, [r7, #0]
|
|
}
|
|
8007424: bf00 nop
|
|
8007426: bf00 nop
|
|
8007428: e7fd b.n 8007426 <xTaskIncrementTick+0x46>
|
|
800742a: 4b41 ldr r3, [pc, #260] @ (8007530 <xTaskIncrementTick+0x150>)
|
|
800742c: 681b ldr r3, [r3, #0]
|
|
800742e: 60fb str r3, [r7, #12]
|
|
8007430: 4b40 ldr r3, [pc, #256] @ (8007534 <xTaskIncrementTick+0x154>)
|
|
8007432: 681b ldr r3, [r3, #0]
|
|
8007434: 4a3e ldr r2, [pc, #248] @ (8007530 <xTaskIncrementTick+0x150>)
|
|
8007436: 6013 str r3, [r2, #0]
|
|
8007438: 4a3e ldr r2, [pc, #248] @ (8007534 <xTaskIncrementTick+0x154>)
|
|
800743a: 68fb ldr r3, [r7, #12]
|
|
800743c: 6013 str r3, [r2, #0]
|
|
800743e: 4b3e ldr r3, [pc, #248] @ (8007538 <xTaskIncrementTick+0x158>)
|
|
8007440: 681b ldr r3, [r3, #0]
|
|
8007442: 3301 adds r3, #1
|
|
8007444: 4a3c ldr r2, [pc, #240] @ (8007538 <xTaskIncrementTick+0x158>)
|
|
8007446: 6013 str r3, [r2, #0]
|
|
8007448: f000 fa16 bl 8007878 <prvResetNextTaskUnblockTime>
|
|
|
|
/* See if this tick has made a timeout expire. Tasks are stored in
|
|
the queue in the order of their wake time - meaning once one task
|
|
has been found whose block time has not expired there is no need to
|
|
look any further down the list. */
|
|
if( xConstTickCount >= xNextTaskUnblockTime )
|
|
800744c: 4b3b ldr r3, [pc, #236] @ (800753c <xTaskIncrementTick+0x15c>)
|
|
800744e: 681b ldr r3, [r3, #0]
|
|
8007450: 693a ldr r2, [r7, #16]
|
|
8007452: 429a cmp r2, r3
|
|
8007454: d348 bcc.n 80074e8 <xTaskIncrementTick+0x108>
|
|
{
|
|
for( ;; )
|
|
{
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
8007456: 4b36 ldr r3, [pc, #216] @ (8007530 <xTaskIncrementTick+0x150>)
|
|
8007458: 681b ldr r3, [r3, #0]
|
|
800745a: 681b ldr r3, [r3, #0]
|
|
800745c: 2b00 cmp r3, #0
|
|
800745e: d104 bne.n 800746a <xTaskIncrementTick+0x8a>
|
|
/* The delayed list is empty. Set xNextTaskUnblockTime
|
|
to the maximum possible value so it is extremely
|
|
unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass
|
|
next time through. */
|
|
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
8007460: 4b36 ldr r3, [pc, #216] @ (800753c <xTaskIncrementTick+0x15c>)
|
|
8007462: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8007466: 601a str r2, [r3, #0]
|
|
break;
|
|
8007468: e03e b.n 80074e8 <xTaskIncrementTick+0x108>
|
|
{
|
|
/* The delayed list is not empty, get the value of the
|
|
item at the head of the delayed list. This is the time
|
|
at which the task at the head of the delayed list must
|
|
be removed from the Blocked state. */
|
|
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
800746a: 4b31 ldr r3, [pc, #196] @ (8007530 <xTaskIncrementTick+0x150>)
|
|
800746c: 681b ldr r3, [r3, #0]
|
|
800746e: 68db ldr r3, [r3, #12]
|
|
8007470: 68db ldr r3, [r3, #12]
|
|
8007472: 60bb str r3, [r7, #8]
|
|
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
|
|
8007474: 68bb ldr r3, [r7, #8]
|
|
8007476: 685b ldr r3, [r3, #4]
|
|
8007478: 607b str r3, [r7, #4]
|
|
|
|
if( xConstTickCount < xItemValue )
|
|
800747a: 693a ldr r2, [r7, #16]
|
|
800747c: 687b ldr r3, [r7, #4]
|
|
800747e: 429a cmp r2, r3
|
|
8007480: d203 bcs.n 800748a <xTaskIncrementTick+0xaa>
|
|
/* It is not time to unblock this item yet, but the
|
|
item value is the time at which the task at the head
|
|
of the blocked list must be removed from the Blocked
|
|
state - so record the item value in
|
|
xNextTaskUnblockTime. */
|
|
xNextTaskUnblockTime = xItemValue;
|
|
8007482: 4a2e ldr r2, [pc, #184] @ (800753c <xTaskIncrementTick+0x15c>)
|
|
8007484: 687b ldr r3, [r7, #4]
|
|
8007486: 6013 str r3, [r2, #0]
|
|
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
|
|
8007488: e02e b.n 80074e8 <xTaskIncrementTick+0x108>
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* It is time to remove the item from the Blocked state. */
|
|
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
|
|
800748a: 68bb ldr r3, [r7, #8]
|
|
800748c: 3304 adds r3, #4
|
|
800748e: 4618 mov r0, r3
|
|
8007490: f7ff fc1d bl 8006cce <uxListRemove>
|
|
|
|
/* Is the task waiting on an event also? If so remove
|
|
it from the event list. */
|
|
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
|
|
8007494: 68bb ldr r3, [r7, #8]
|
|
8007496: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8007498: 2b00 cmp r3, #0
|
|
800749a: d004 beq.n 80074a6 <xTaskIncrementTick+0xc6>
|
|
{
|
|
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
|
|
800749c: 68bb ldr r3, [r7, #8]
|
|
800749e: 3318 adds r3, #24
|
|
80074a0: 4618 mov r0, r3
|
|
80074a2: f7ff fc14 bl 8006cce <uxListRemove>
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
/* Place the unblocked task into the appropriate ready
|
|
list. */
|
|
prvAddTaskToReadyList( pxTCB );
|
|
80074a6: 68bb ldr r3, [r7, #8]
|
|
80074a8: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80074aa: 2201 movs r2, #1
|
|
80074ac: 409a lsls r2, r3
|
|
80074ae: 4b24 ldr r3, [pc, #144] @ (8007540 <xTaskIncrementTick+0x160>)
|
|
80074b0: 681b ldr r3, [r3, #0]
|
|
80074b2: 4313 orrs r3, r2
|
|
80074b4: 4a22 ldr r2, [pc, #136] @ (8007540 <xTaskIncrementTick+0x160>)
|
|
80074b6: 6013 str r3, [r2, #0]
|
|
80074b8: 68bb ldr r3, [r7, #8]
|
|
80074ba: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80074bc: 4613 mov r3, r2
|
|
80074be: 009b lsls r3, r3, #2
|
|
80074c0: 4413 add r3, r2
|
|
80074c2: 009b lsls r3, r3, #2
|
|
80074c4: 4a1f ldr r2, [pc, #124] @ (8007544 <xTaskIncrementTick+0x164>)
|
|
80074c6: 441a add r2, r3
|
|
80074c8: 68bb ldr r3, [r7, #8]
|
|
80074ca: 3304 adds r3, #4
|
|
80074cc: 4619 mov r1, r3
|
|
80074ce: 4610 mov r0, r2
|
|
80074d0: f7ff fba0 bl 8006c14 <vListInsertEnd>
|
|
{
|
|
/* Preemption is on, but a context switch should
|
|
only be performed if the unblocked task has a
|
|
priority that is equal to or higher than the
|
|
currently executing task. */
|
|
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
|
|
80074d4: 68bb ldr r3, [r7, #8]
|
|
80074d6: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80074d8: 4b1b ldr r3, [pc, #108] @ (8007548 <xTaskIncrementTick+0x168>)
|
|
80074da: 681b ldr r3, [r3, #0]
|
|
80074dc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80074de: 429a cmp r2, r3
|
|
80074e0: d3b9 bcc.n 8007456 <xTaskIncrementTick+0x76>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
80074e2: 2301 movs r3, #1
|
|
80074e4: 617b str r3, [r7, #20]
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
80074e6: e7b6 b.n 8007456 <xTaskIncrementTick+0x76>
|
|
/* Tasks of equal priority to the currently running task will share
|
|
processing time (time slice) if preemption is on, and the application
|
|
writer has not explicitly turned time slicing off. */
|
|
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
|
|
{
|
|
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
|
|
80074e8: 4b17 ldr r3, [pc, #92] @ (8007548 <xTaskIncrementTick+0x168>)
|
|
80074ea: 681b ldr r3, [r3, #0]
|
|
80074ec: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80074ee: 4915 ldr r1, [pc, #84] @ (8007544 <xTaskIncrementTick+0x164>)
|
|
80074f0: 4613 mov r3, r2
|
|
80074f2: 009b lsls r3, r3, #2
|
|
80074f4: 4413 add r3, r2
|
|
80074f6: 009b lsls r3, r3, #2
|
|
80074f8: 440b add r3, r1
|
|
80074fa: 681b ldr r3, [r3, #0]
|
|
80074fc: 2b01 cmp r3, #1
|
|
80074fe: d901 bls.n 8007504 <xTaskIncrementTick+0x124>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
8007500: 2301 movs r3, #1
|
|
8007502: 617b str r3, [r7, #20]
|
|
}
|
|
#endif /* configUSE_TICK_HOOK */
|
|
|
|
#if ( configUSE_PREEMPTION == 1 )
|
|
{
|
|
if( xYieldPending != pdFALSE )
|
|
8007504: 4b11 ldr r3, [pc, #68] @ (800754c <xTaskIncrementTick+0x16c>)
|
|
8007506: 681b ldr r3, [r3, #0]
|
|
8007508: 2b00 cmp r3, #0
|
|
800750a: d007 beq.n 800751c <xTaskIncrementTick+0x13c>
|
|
{
|
|
xSwitchRequired = pdTRUE;
|
|
800750c: 2301 movs r3, #1
|
|
800750e: 617b str r3, [r7, #20]
|
|
8007510: e004 b.n 800751c <xTaskIncrementTick+0x13c>
|
|
}
|
|
#endif /* configUSE_PREEMPTION */
|
|
}
|
|
else
|
|
{
|
|
++xPendedTicks;
|
|
8007512: 4b0f ldr r3, [pc, #60] @ (8007550 <xTaskIncrementTick+0x170>)
|
|
8007514: 681b ldr r3, [r3, #0]
|
|
8007516: 3301 adds r3, #1
|
|
8007518: 4a0d ldr r2, [pc, #52] @ (8007550 <xTaskIncrementTick+0x170>)
|
|
800751a: 6013 str r3, [r2, #0]
|
|
vApplicationTickHook();
|
|
}
|
|
#endif
|
|
}
|
|
|
|
return xSwitchRequired;
|
|
800751c: 697b ldr r3, [r7, #20]
|
|
}
|
|
800751e: 4618 mov r0, r3
|
|
8007520: 3718 adds r7, #24
|
|
8007522: 46bd mov sp, r7
|
|
8007524: bd80 pop {r7, pc}
|
|
8007526: bf00 nop
|
|
8007528: 200003bc .word 0x200003bc
|
|
800752c: 200003a0 .word 0x200003a0
|
|
8007530: 2000036c .word 0x2000036c
|
|
8007534: 20000370 .word 0x20000370
|
|
8007538: 200003b4 .word 0x200003b4
|
|
800753c: 200003b8 .word 0x200003b8
|
|
8007540: 200003a4 .word 0x200003a4
|
|
8007544: 200002e0 .word 0x200002e0
|
|
8007548: 200002dc .word 0x200002dc
|
|
800754c: 200003b0 .word 0x200003b0
|
|
8007550: 200003ac .word 0x200003ac
|
|
|
|
08007554 <vTaskSwitchContext>:
|
|
|
|
#endif /* configUSE_APPLICATION_TASK_TAG */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskSwitchContext( void )
|
|
{
|
|
8007554: b580 push {r7, lr}
|
|
8007556: b088 sub sp, #32
|
|
8007558: af00 add r7, sp, #0
|
|
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
|
|
800755a: 4b3a ldr r3, [pc, #232] @ (8007644 <vTaskSwitchContext+0xf0>)
|
|
800755c: 681b ldr r3, [r3, #0]
|
|
800755e: 2b00 cmp r3, #0
|
|
8007560: d003 beq.n 800756a <vTaskSwitchContext+0x16>
|
|
{
|
|
/* The scheduler is currently suspended - do not allow a context
|
|
switch. */
|
|
xYieldPending = pdTRUE;
|
|
8007562: 4b39 ldr r3, [pc, #228] @ (8007648 <vTaskSwitchContext+0xf4>)
|
|
8007564: 2201 movs r2, #1
|
|
8007566: 601a str r2, [r3, #0]
|
|
for additional information. */
|
|
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
|
|
}
|
|
#endif /* configUSE_NEWLIB_REENTRANT */
|
|
}
|
|
}
|
|
8007568: e067 b.n 800763a <vTaskSwitchContext+0xe6>
|
|
xYieldPending = pdFALSE;
|
|
800756a: 4b37 ldr r3, [pc, #220] @ (8007648 <vTaskSwitchContext+0xf4>)
|
|
800756c: 2200 movs r2, #0
|
|
800756e: 601a str r2, [r3, #0]
|
|
taskCHECK_FOR_STACK_OVERFLOW();
|
|
8007570: 4b36 ldr r3, [pc, #216] @ (800764c <vTaskSwitchContext+0xf8>)
|
|
8007572: 681b ldr r3, [r3, #0]
|
|
8007574: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8007576: 61fb str r3, [r7, #28]
|
|
8007578: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5
|
|
800757c: 61bb str r3, [r7, #24]
|
|
800757e: 69fb ldr r3, [r7, #28]
|
|
8007580: 681b ldr r3, [r3, #0]
|
|
8007582: 69ba ldr r2, [r7, #24]
|
|
8007584: 429a cmp r2, r3
|
|
8007586: d111 bne.n 80075ac <vTaskSwitchContext+0x58>
|
|
8007588: 69fb ldr r3, [r7, #28]
|
|
800758a: 3304 adds r3, #4
|
|
800758c: 681b ldr r3, [r3, #0]
|
|
800758e: 69ba ldr r2, [r7, #24]
|
|
8007590: 429a cmp r2, r3
|
|
8007592: d10b bne.n 80075ac <vTaskSwitchContext+0x58>
|
|
8007594: 69fb ldr r3, [r7, #28]
|
|
8007596: 3308 adds r3, #8
|
|
8007598: 681b ldr r3, [r3, #0]
|
|
800759a: 69ba ldr r2, [r7, #24]
|
|
800759c: 429a cmp r2, r3
|
|
800759e: d105 bne.n 80075ac <vTaskSwitchContext+0x58>
|
|
80075a0: 69fb ldr r3, [r7, #28]
|
|
80075a2: 330c adds r3, #12
|
|
80075a4: 681b ldr r3, [r3, #0]
|
|
80075a6: 69ba ldr r2, [r7, #24]
|
|
80075a8: 429a cmp r2, r3
|
|
80075aa: d008 beq.n 80075be <vTaskSwitchContext+0x6a>
|
|
80075ac: 4b27 ldr r3, [pc, #156] @ (800764c <vTaskSwitchContext+0xf8>)
|
|
80075ae: 681a ldr r2, [r3, #0]
|
|
80075b0: 4b26 ldr r3, [pc, #152] @ (800764c <vTaskSwitchContext+0xf8>)
|
|
80075b2: 681b ldr r3, [r3, #0]
|
|
80075b4: 3334 adds r3, #52 @ 0x34
|
|
80075b6: 4619 mov r1, r3
|
|
80075b8: 4610 mov r0, r2
|
|
80075ba: f7f8 ffaf bl 800051c <vApplicationStackOverflowHook>
|
|
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
80075be: 4b24 ldr r3, [pc, #144] @ (8007650 <vTaskSwitchContext+0xfc>)
|
|
80075c0: 681b ldr r3, [r3, #0]
|
|
80075c2: 60fb str r3, [r7, #12]
|
|
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
|
|
80075c4: 68fb ldr r3, [r7, #12]
|
|
80075c6: fab3 f383 clz r3, r3
|
|
80075ca: 72fb strb r3, [r7, #11]
|
|
return ucReturn;
|
|
80075cc: 7afb ldrb r3, [r7, #11]
|
|
80075ce: f1c3 031f rsb r3, r3, #31
|
|
80075d2: 617b str r3, [r7, #20]
|
|
80075d4: 491f ldr r1, [pc, #124] @ (8007654 <vTaskSwitchContext+0x100>)
|
|
80075d6: 697a ldr r2, [r7, #20]
|
|
80075d8: 4613 mov r3, r2
|
|
80075da: 009b lsls r3, r3, #2
|
|
80075dc: 4413 add r3, r2
|
|
80075de: 009b lsls r3, r3, #2
|
|
80075e0: 440b add r3, r1
|
|
80075e2: 681b ldr r3, [r3, #0]
|
|
80075e4: 2b00 cmp r3, #0
|
|
80075e6: d10b bne.n 8007600 <vTaskSwitchContext+0xac>
|
|
__asm volatile
|
|
80075e8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80075ec: f383 8811 msr BASEPRI, r3
|
|
80075f0: f3bf 8f6f isb sy
|
|
80075f4: f3bf 8f4f dsb sy
|
|
80075f8: 607b str r3, [r7, #4]
|
|
}
|
|
80075fa: bf00 nop
|
|
80075fc: bf00 nop
|
|
80075fe: e7fd b.n 80075fc <vTaskSwitchContext+0xa8>
|
|
8007600: 697a ldr r2, [r7, #20]
|
|
8007602: 4613 mov r3, r2
|
|
8007604: 009b lsls r3, r3, #2
|
|
8007606: 4413 add r3, r2
|
|
8007608: 009b lsls r3, r3, #2
|
|
800760a: 4a12 ldr r2, [pc, #72] @ (8007654 <vTaskSwitchContext+0x100>)
|
|
800760c: 4413 add r3, r2
|
|
800760e: 613b str r3, [r7, #16]
|
|
8007610: 693b ldr r3, [r7, #16]
|
|
8007612: 685b ldr r3, [r3, #4]
|
|
8007614: 685a ldr r2, [r3, #4]
|
|
8007616: 693b ldr r3, [r7, #16]
|
|
8007618: 605a str r2, [r3, #4]
|
|
800761a: 693b ldr r3, [r7, #16]
|
|
800761c: 685a ldr r2, [r3, #4]
|
|
800761e: 693b ldr r3, [r7, #16]
|
|
8007620: 3308 adds r3, #8
|
|
8007622: 429a cmp r2, r3
|
|
8007624: d104 bne.n 8007630 <vTaskSwitchContext+0xdc>
|
|
8007626: 693b ldr r3, [r7, #16]
|
|
8007628: 685b ldr r3, [r3, #4]
|
|
800762a: 685a ldr r2, [r3, #4]
|
|
800762c: 693b ldr r3, [r7, #16]
|
|
800762e: 605a str r2, [r3, #4]
|
|
8007630: 693b ldr r3, [r7, #16]
|
|
8007632: 685b ldr r3, [r3, #4]
|
|
8007634: 68db ldr r3, [r3, #12]
|
|
8007636: 4a05 ldr r2, [pc, #20] @ (800764c <vTaskSwitchContext+0xf8>)
|
|
8007638: 6013 str r3, [r2, #0]
|
|
}
|
|
800763a: bf00 nop
|
|
800763c: 3720 adds r7, #32
|
|
800763e: 46bd mov sp, r7
|
|
8007640: bd80 pop {r7, pc}
|
|
8007642: bf00 nop
|
|
8007644: 200003bc .word 0x200003bc
|
|
8007648: 200003b0 .word 0x200003b0
|
|
800764c: 200002dc .word 0x200002dc
|
|
8007650: 200003a4 .word 0x200003a4
|
|
8007654: 200002e0 .word 0x200002e0
|
|
|
|
08007658 <vTaskPlaceOnEventList>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
|
|
{
|
|
8007658: b580 push {r7, lr}
|
|
800765a: b084 sub sp, #16
|
|
800765c: af00 add r7, sp, #0
|
|
800765e: 6078 str r0, [r7, #4]
|
|
8007660: 6039 str r1, [r7, #0]
|
|
configASSERT( pxEventList );
|
|
8007662: 687b ldr r3, [r7, #4]
|
|
8007664: 2b00 cmp r3, #0
|
|
8007666: d10b bne.n 8007680 <vTaskPlaceOnEventList+0x28>
|
|
__asm volatile
|
|
8007668: f04f 0350 mov.w r3, #80 @ 0x50
|
|
800766c: f383 8811 msr BASEPRI, r3
|
|
8007670: f3bf 8f6f isb sy
|
|
8007674: f3bf 8f4f dsb sy
|
|
8007678: 60fb str r3, [r7, #12]
|
|
}
|
|
800767a: bf00 nop
|
|
800767c: bf00 nop
|
|
800767e: e7fd b.n 800767c <vTaskPlaceOnEventList+0x24>
|
|
|
|
/* Place the event list item of the TCB in the appropriate event list.
|
|
This is placed in the list in priority order so the highest priority task
|
|
is the first to be woken by the event. The queue that contains the event
|
|
list is locked, preventing simultaneous access from interrupts. */
|
|
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
|
|
8007680: 4b07 ldr r3, [pc, #28] @ (80076a0 <vTaskPlaceOnEventList+0x48>)
|
|
8007682: 681b ldr r3, [r3, #0]
|
|
8007684: 3318 adds r3, #24
|
|
8007686: 4619 mov r1, r3
|
|
8007688: 6878 ldr r0, [r7, #4]
|
|
800768a: f7ff fae7 bl 8006c5c <vListInsert>
|
|
|
|
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
|
|
800768e: 2101 movs r1, #1
|
|
8007690: 6838 ldr r0, [r7, #0]
|
|
8007692: f000 f9b7 bl 8007a04 <prvAddCurrentTaskToDelayedList>
|
|
}
|
|
8007696: bf00 nop
|
|
8007698: 3710 adds r7, #16
|
|
800769a: 46bd mov sp, r7
|
|
800769c: bd80 pop {r7, pc}
|
|
800769e: bf00 nop
|
|
80076a0: 200002dc .word 0x200002dc
|
|
|
|
080076a4 <xTaskRemoveFromEventList>:
|
|
|
|
#endif /* configUSE_TIMERS */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
|
|
{
|
|
80076a4: b580 push {r7, lr}
|
|
80076a6: b086 sub sp, #24
|
|
80076a8: af00 add r7, sp, #0
|
|
80076aa: 6078 str r0, [r7, #4]
|
|
get called - the lock count on the queue will get modified instead. This
|
|
means exclusive access to the event list is guaranteed here.
|
|
|
|
This function assumes that a check has already been made to ensure that
|
|
pxEventList is not empty. */
|
|
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
80076ac: 687b ldr r3, [r7, #4]
|
|
80076ae: 68db ldr r3, [r3, #12]
|
|
80076b0: 68db ldr r3, [r3, #12]
|
|
80076b2: 613b str r3, [r7, #16]
|
|
configASSERT( pxUnblockedTCB );
|
|
80076b4: 693b ldr r3, [r7, #16]
|
|
80076b6: 2b00 cmp r3, #0
|
|
80076b8: d10b bne.n 80076d2 <xTaskRemoveFromEventList+0x2e>
|
|
__asm volatile
|
|
80076ba: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80076be: f383 8811 msr BASEPRI, r3
|
|
80076c2: f3bf 8f6f isb sy
|
|
80076c6: f3bf 8f4f dsb sy
|
|
80076ca: 60fb str r3, [r7, #12]
|
|
}
|
|
80076cc: bf00 nop
|
|
80076ce: bf00 nop
|
|
80076d0: e7fd b.n 80076ce <xTaskRemoveFromEventList+0x2a>
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
|
|
80076d2: 693b ldr r3, [r7, #16]
|
|
80076d4: 3318 adds r3, #24
|
|
80076d6: 4618 mov r0, r3
|
|
80076d8: f7ff faf9 bl 8006cce <uxListRemove>
|
|
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
80076dc: 4b1d ldr r3, [pc, #116] @ (8007754 <xTaskRemoveFromEventList+0xb0>)
|
|
80076de: 681b ldr r3, [r3, #0]
|
|
80076e0: 2b00 cmp r3, #0
|
|
80076e2: d11c bne.n 800771e <xTaskRemoveFromEventList+0x7a>
|
|
{
|
|
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
|
|
80076e4: 693b ldr r3, [r7, #16]
|
|
80076e6: 3304 adds r3, #4
|
|
80076e8: 4618 mov r0, r3
|
|
80076ea: f7ff faf0 bl 8006cce <uxListRemove>
|
|
prvAddTaskToReadyList( pxUnblockedTCB );
|
|
80076ee: 693b ldr r3, [r7, #16]
|
|
80076f0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80076f2: 2201 movs r2, #1
|
|
80076f4: 409a lsls r2, r3
|
|
80076f6: 4b18 ldr r3, [pc, #96] @ (8007758 <xTaskRemoveFromEventList+0xb4>)
|
|
80076f8: 681b ldr r3, [r3, #0]
|
|
80076fa: 4313 orrs r3, r2
|
|
80076fc: 4a16 ldr r2, [pc, #88] @ (8007758 <xTaskRemoveFromEventList+0xb4>)
|
|
80076fe: 6013 str r3, [r2, #0]
|
|
8007700: 693b ldr r3, [r7, #16]
|
|
8007702: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8007704: 4613 mov r3, r2
|
|
8007706: 009b lsls r3, r3, #2
|
|
8007708: 4413 add r3, r2
|
|
800770a: 009b lsls r3, r3, #2
|
|
800770c: 4a13 ldr r2, [pc, #76] @ (800775c <xTaskRemoveFromEventList+0xb8>)
|
|
800770e: 441a add r2, r3
|
|
8007710: 693b ldr r3, [r7, #16]
|
|
8007712: 3304 adds r3, #4
|
|
8007714: 4619 mov r1, r3
|
|
8007716: 4610 mov r0, r2
|
|
8007718: f7ff fa7c bl 8006c14 <vListInsertEnd>
|
|
800771c: e005 b.n 800772a <xTaskRemoveFromEventList+0x86>
|
|
}
|
|
else
|
|
{
|
|
/* The delayed and ready lists cannot be accessed, so hold this task
|
|
pending until the scheduler is resumed. */
|
|
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
|
|
800771e: 693b ldr r3, [r7, #16]
|
|
8007720: 3318 adds r3, #24
|
|
8007722: 4619 mov r1, r3
|
|
8007724: 480e ldr r0, [pc, #56] @ (8007760 <xTaskRemoveFromEventList+0xbc>)
|
|
8007726: f7ff fa75 bl 8006c14 <vListInsertEnd>
|
|
}
|
|
|
|
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
|
|
800772a: 693b ldr r3, [r7, #16]
|
|
800772c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800772e: 4b0d ldr r3, [pc, #52] @ (8007764 <xTaskRemoveFromEventList+0xc0>)
|
|
8007730: 681b ldr r3, [r3, #0]
|
|
8007732: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007734: 429a cmp r2, r3
|
|
8007736: d905 bls.n 8007744 <xTaskRemoveFromEventList+0xa0>
|
|
{
|
|
/* Return true if the task removed from the event list has a higher
|
|
priority than the calling task. This allows the calling task to know if
|
|
it should force a context switch now. */
|
|
xReturn = pdTRUE;
|
|
8007738: 2301 movs r3, #1
|
|
800773a: 617b str r3, [r7, #20]
|
|
|
|
/* Mark that a yield is pending in case the user is not using the
|
|
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
|
|
xYieldPending = pdTRUE;
|
|
800773c: 4b0a ldr r3, [pc, #40] @ (8007768 <xTaskRemoveFromEventList+0xc4>)
|
|
800773e: 2201 movs r2, #1
|
|
8007740: 601a str r2, [r3, #0]
|
|
8007742: e001 b.n 8007748 <xTaskRemoveFromEventList+0xa4>
|
|
}
|
|
else
|
|
{
|
|
xReturn = pdFALSE;
|
|
8007744: 2300 movs r3, #0
|
|
8007746: 617b str r3, [r7, #20]
|
|
}
|
|
|
|
return xReturn;
|
|
8007748: 697b ldr r3, [r7, #20]
|
|
}
|
|
800774a: 4618 mov r0, r3
|
|
800774c: 3718 adds r7, #24
|
|
800774e: 46bd mov sp, r7
|
|
8007750: bd80 pop {r7, pc}
|
|
8007752: bf00 nop
|
|
8007754: 200003bc .word 0x200003bc
|
|
8007758: 200003a4 .word 0x200003a4
|
|
800775c: 200002e0 .word 0x200002e0
|
|
8007760: 20000374 .word 0x20000374
|
|
8007764: 200002dc .word 0x200002dc
|
|
8007768: 200003b0 .word 0x200003b0
|
|
|
|
0800776c <vTaskInternalSetTimeOutState>:
|
|
taskEXIT_CRITICAL();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
|
|
{
|
|
800776c: b480 push {r7}
|
|
800776e: b083 sub sp, #12
|
|
8007770: af00 add r7, sp, #0
|
|
8007772: 6078 str r0, [r7, #4]
|
|
/* For internal use only as it does not use a critical section. */
|
|
pxTimeOut->xOverflowCount = xNumOfOverflows;
|
|
8007774: 4b06 ldr r3, [pc, #24] @ (8007790 <vTaskInternalSetTimeOutState+0x24>)
|
|
8007776: 681a ldr r2, [r3, #0]
|
|
8007778: 687b ldr r3, [r7, #4]
|
|
800777a: 601a str r2, [r3, #0]
|
|
pxTimeOut->xTimeOnEntering = xTickCount;
|
|
800777c: 4b05 ldr r3, [pc, #20] @ (8007794 <vTaskInternalSetTimeOutState+0x28>)
|
|
800777e: 681a ldr r2, [r3, #0]
|
|
8007780: 687b ldr r3, [r7, #4]
|
|
8007782: 605a str r2, [r3, #4]
|
|
}
|
|
8007784: bf00 nop
|
|
8007786: 370c adds r7, #12
|
|
8007788: 46bd mov sp, r7
|
|
800778a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800778e: 4770 bx lr
|
|
8007790: 200003b4 .word 0x200003b4
|
|
8007794: 200003a0 .word 0x200003a0
|
|
|
|
08007798 <xTaskCheckForTimeOut>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
|
|
{
|
|
8007798: b580 push {r7, lr}
|
|
800779a: b088 sub sp, #32
|
|
800779c: af00 add r7, sp, #0
|
|
800779e: 6078 str r0, [r7, #4]
|
|
80077a0: 6039 str r1, [r7, #0]
|
|
BaseType_t xReturn;
|
|
|
|
configASSERT( pxTimeOut );
|
|
80077a2: 687b ldr r3, [r7, #4]
|
|
80077a4: 2b00 cmp r3, #0
|
|
80077a6: d10b bne.n 80077c0 <xTaskCheckForTimeOut+0x28>
|
|
__asm volatile
|
|
80077a8: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80077ac: f383 8811 msr BASEPRI, r3
|
|
80077b0: f3bf 8f6f isb sy
|
|
80077b4: f3bf 8f4f dsb sy
|
|
80077b8: 613b str r3, [r7, #16]
|
|
}
|
|
80077ba: bf00 nop
|
|
80077bc: bf00 nop
|
|
80077be: e7fd b.n 80077bc <xTaskCheckForTimeOut+0x24>
|
|
configASSERT( pxTicksToWait );
|
|
80077c0: 683b ldr r3, [r7, #0]
|
|
80077c2: 2b00 cmp r3, #0
|
|
80077c4: d10b bne.n 80077de <xTaskCheckForTimeOut+0x46>
|
|
__asm volatile
|
|
80077c6: f04f 0350 mov.w r3, #80 @ 0x50
|
|
80077ca: f383 8811 msr BASEPRI, r3
|
|
80077ce: f3bf 8f6f isb sy
|
|
80077d2: f3bf 8f4f dsb sy
|
|
80077d6: 60fb str r3, [r7, #12]
|
|
}
|
|
80077d8: bf00 nop
|
|
80077da: bf00 nop
|
|
80077dc: e7fd b.n 80077da <xTaskCheckForTimeOut+0x42>
|
|
|
|
taskENTER_CRITICAL();
|
|
80077de: f000 f98b bl 8007af8 <vPortEnterCritical>
|
|
{
|
|
/* Minor optimisation. The tick count cannot change in this block. */
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
80077e2: 4b1d ldr r3, [pc, #116] @ (8007858 <xTaskCheckForTimeOut+0xc0>)
|
|
80077e4: 681b ldr r3, [r3, #0]
|
|
80077e6: 61bb str r3, [r7, #24]
|
|
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
|
|
80077e8: 687b ldr r3, [r7, #4]
|
|
80077ea: 685b ldr r3, [r3, #4]
|
|
80077ec: 69ba ldr r2, [r7, #24]
|
|
80077ee: 1ad3 subs r3, r2, r3
|
|
80077f0: 617b str r3, [r7, #20]
|
|
}
|
|
else
|
|
#endif
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
if( *pxTicksToWait == portMAX_DELAY )
|
|
80077f2: 683b ldr r3, [r7, #0]
|
|
80077f4: 681b ldr r3, [r3, #0]
|
|
80077f6: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80077fa: d102 bne.n 8007802 <xTaskCheckForTimeOut+0x6a>
|
|
{
|
|
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
|
|
specified is the maximum block time then the task should block
|
|
indefinitely, and therefore never time out. */
|
|
xReturn = pdFALSE;
|
|
80077fc: 2300 movs r3, #0
|
|
80077fe: 61fb str r3, [r7, #28]
|
|
8007800: e023 b.n 800784a <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
#endif
|
|
|
|
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
|
|
8007802: 687b ldr r3, [r7, #4]
|
|
8007804: 681a ldr r2, [r3, #0]
|
|
8007806: 4b15 ldr r3, [pc, #84] @ (800785c <xTaskCheckForTimeOut+0xc4>)
|
|
8007808: 681b ldr r3, [r3, #0]
|
|
800780a: 429a cmp r2, r3
|
|
800780c: d007 beq.n 800781e <xTaskCheckForTimeOut+0x86>
|
|
800780e: 687b ldr r3, [r7, #4]
|
|
8007810: 685b ldr r3, [r3, #4]
|
|
8007812: 69ba ldr r2, [r7, #24]
|
|
8007814: 429a cmp r2, r3
|
|
8007816: d302 bcc.n 800781e <xTaskCheckForTimeOut+0x86>
|
|
/* The tick count is greater than the time at which
|
|
vTaskSetTimeout() was called, but has also overflowed since
|
|
vTaskSetTimeOut() was called. It must have wrapped all the way
|
|
around and gone past again. This passed since vTaskSetTimeout()
|
|
was called. */
|
|
xReturn = pdTRUE;
|
|
8007818: 2301 movs r3, #1
|
|
800781a: 61fb str r3, [r7, #28]
|
|
800781c: e015 b.n 800784a <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
|
|
800781e: 683b ldr r3, [r7, #0]
|
|
8007820: 681b ldr r3, [r3, #0]
|
|
8007822: 697a ldr r2, [r7, #20]
|
|
8007824: 429a cmp r2, r3
|
|
8007826: d20b bcs.n 8007840 <xTaskCheckForTimeOut+0xa8>
|
|
{
|
|
/* Not a genuine timeout. Adjust parameters for time remaining. */
|
|
*pxTicksToWait -= xElapsedTime;
|
|
8007828: 683b ldr r3, [r7, #0]
|
|
800782a: 681a ldr r2, [r3, #0]
|
|
800782c: 697b ldr r3, [r7, #20]
|
|
800782e: 1ad2 subs r2, r2, r3
|
|
8007830: 683b ldr r3, [r7, #0]
|
|
8007832: 601a str r2, [r3, #0]
|
|
vTaskInternalSetTimeOutState( pxTimeOut );
|
|
8007834: 6878 ldr r0, [r7, #4]
|
|
8007836: f7ff ff99 bl 800776c <vTaskInternalSetTimeOutState>
|
|
xReturn = pdFALSE;
|
|
800783a: 2300 movs r3, #0
|
|
800783c: 61fb str r3, [r7, #28]
|
|
800783e: e004 b.n 800784a <xTaskCheckForTimeOut+0xb2>
|
|
}
|
|
else
|
|
{
|
|
*pxTicksToWait = 0;
|
|
8007840: 683b ldr r3, [r7, #0]
|
|
8007842: 2200 movs r2, #0
|
|
8007844: 601a str r2, [r3, #0]
|
|
xReturn = pdTRUE;
|
|
8007846: 2301 movs r3, #1
|
|
8007848: 61fb str r3, [r7, #28]
|
|
}
|
|
}
|
|
taskEXIT_CRITICAL();
|
|
800784a: f000 f987 bl 8007b5c <vPortExitCritical>
|
|
|
|
return xReturn;
|
|
800784e: 69fb ldr r3, [r7, #28]
|
|
}
|
|
8007850: 4618 mov r0, r3
|
|
8007852: 3720 adds r7, #32
|
|
8007854: 46bd mov sp, r7
|
|
8007856: bd80 pop {r7, pc}
|
|
8007858: 200003a0 .word 0x200003a0
|
|
800785c: 200003b4 .word 0x200003b4
|
|
|
|
08007860 <vTaskMissedYield>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vTaskMissedYield( void )
|
|
{
|
|
8007860: b480 push {r7}
|
|
8007862: af00 add r7, sp, #0
|
|
xYieldPending = pdTRUE;
|
|
8007864: 4b03 ldr r3, [pc, #12] @ (8007874 <vTaskMissedYield+0x14>)
|
|
8007866: 2201 movs r2, #1
|
|
8007868: 601a str r2, [r3, #0]
|
|
}
|
|
800786a: bf00 nop
|
|
800786c: 46bd mov sp, r7
|
|
800786e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007872: 4770 bx lr
|
|
8007874: 200003b0 .word 0x200003b0
|
|
|
|
08007878 <prvResetNextTaskUnblockTime>:
|
|
|
|
#endif /* INCLUDE_vTaskDelete */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvResetNextTaskUnblockTime( void )
|
|
{
|
|
8007878: b480 push {r7}
|
|
800787a: b083 sub sp, #12
|
|
800787c: af00 add r7, sp, #0
|
|
TCB_t *pxTCB;
|
|
|
|
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
|
|
800787e: 4b0c ldr r3, [pc, #48] @ (80078b0 <prvResetNextTaskUnblockTime+0x38>)
|
|
8007880: 681b ldr r3, [r3, #0]
|
|
8007882: 681b ldr r3, [r3, #0]
|
|
8007884: 2b00 cmp r3, #0
|
|
8007886: d104 bne.n 8007892 <prvResetNextTaskUnblockTime+0x1a>
|
|
{
|
|
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
|
|
the maximum possible value so it is extremely unlikely that the
|
|
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
|
|
there is an item in the delayed list. */
|
|
xNextTaskUnblockTime = portMAX_DELAY;
|
|
8007888: 4b0a ldr r3, [pc, #40] @ (80078b4 <prvResetNextTaskUnblockTime+0x3c>)
|
|
800788a: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
800788e: 601a str r2, [r3, #0]
|
|
which the task at the head of the delayed list should be removed
|
|
from the Blocked state. */
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
}
|
|
}
|
|
8007890: e008 b.n 80078a4 <prvResetNextTaskUnblockTime+0x2c>
|
|
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
|
|
8007892: 4b07 ldr r3, [pc, #28] @ (80078b0 <prvResetNextTaskUnblockTime+0x38>)
|
|
8007894: 681b ldr r3, [r3, #0]
|
|
8007896: 68db ldr r3, [r3, #12]
|
|
8007898: 68db ldr r3, [r3, #12]
|
|
800789a: 607b str r3, [r7, #4]
|
|
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
|
|
800789c: 687b ldr r3, [r7, #4]
|
|
800789e: 685b ldr r3, [r3, #4]
|
|
80078a0: 4a04 ldr r2, [pc, #16] @ (80078b4 <prvResetNextTaskUnblockTime+0x3c>)
|
|
80078a2: 6013 str r3, [r2, #0]
|
|
}
|
|
80078a4: bf00 nop
|
|
80078a6: 370c adds r7, #12
|
|
80078a8: 46bd mov sp, r7
|
|
80078aa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80078ae: 4770 bx lr
|
|
80078b0: 2000036c .word 0x2000036c
|
|
80078b4: 200003b8 .word 0x200003b8
|
|
|
|
080078b8 <xTaskGetSchedulerState>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
|
|
|
BaseType_t xTaskGetSchedulerState( void )
|
|
{
|
|
80078b8: b480 push {r7}
|
|
80078ba: b083 sub sp, #12
|
|
80078bc: af00 add r7, sp, #0
|
|
BaseType_t xReturn;
|
|
|
|
if( xSchedulerRunning == pdFALSE )
|
|
80078be: 4b0b ldr r3, [pc, #44] @ (80078ec <xTaskGetSchedulerState+0x34>)
|
|
80078c0: 681b ldr r3, [r3, #0]
|
|
80078c2: 2b00 cmp r3, #0
|
|
80078c4: d102 bne.n 80078cc <xTaskGetSchedulerState+0x14>
|
|
{
|
|
xReturn = taskSCHEDULER_NOT_STARTED;
|
|
80078c6: 2301 movs r3, #1
|
|
80078c8: 607b str r3, [r7, #4]
|
|
80078ca: e008 b.n 80078de <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
|
|
80078cc: 4b08 ldr r3, [pc, #32] @ (80078f0 <xTaskGetSchedulerState+0x38>)
|
|
80078ce: 681b ldr r3, [r3, #0]
|
|
80078d0: 2b00 cmp r3, #0
|
|
80078d2: d102 bne.n 80078da <xTaskGetSchedulerState+0x22>
|
|
{
|
|
xReturn = taskSCHEDULER_RUNNING;
|
|
80078d4: 2302 movs r3, #2
|
|
80078d6: 607b str r3, [r7, #4]
|
|
80078d8: e001 b.n 80078de <xTaskGetSchedulerState+0x26>
|
|
}
|
|
else
|
|
{
|
|
xReturn = taskSCHEDULER_SUSPENDED;
|
|
80078da: 2300 movs r3, #0
|
|
80078dc: 607b str r3, [r7, #4]
|
|
}
|
|
}
|
|
|
|
return xReturn;
|
|
80078de: 687b ldr r3, [r7, #4]
|
|
}
|
|
80078e0: 4618 mov r0, r3
|
|
80078e2: 370c adds r7, #12
|
|
80078e4: 46bd mov sp, r7
|
|
80078e6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80078ea: 4770 bx lr
|
|
80078ec: 200003a8 .word 0x200003a8
|
|
80078f0: 200003bc .word 0x200003bc
|
|
|
|
080078f4 <xTaskPriorityDisinherit>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_MUTEXES == 1 )
|
|
|
|
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
|
|
{
|
|
80078f4: b580 push {r7, lr}
|
|
80078f6: b086 sub sp, #24
|
|
80078f8: af00 add r7, sp, #0
|
|
80078fa: 6078 str r0, [r7, #4]
|
|
TCB_t * const pxTCB = pxMutexHolder;
|
|
80078fc: 687b ldr r3, [r7, #4]
|
|
80078fe: 613b str r3, [r7, #16]
|
|
BaseType_t xReturn = pdFALSE;
|
|
8007900: 2300 movs r3, #0
|
|
8007902: 617b str r3, [r7, #20]
|
|
|
|
if( pxMutexHolder != NULL )
|
|
8007904: 687b ldr r3, [r7, #4]
|
|
8007906: 2b00 cmp r3, #0
|
|
8007908: d070 beq.n 80079ec <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* A task can only have an inherited priority if it holds the mutex.
|
|
If the mutex is held by a task then it cannot be given from an
|
|
interrupt, and if a mutex is given by the holding task then it must
|
|
be the running state task. */
|
|
configASSERT( pxTCB == pxCurrentTCB );
|
|
800790a: 4b3b ldr r3, [pc, #236] @ (80079f8 <xTaskPriorityDisinherit+0x104>)
|
|
800790c: 681b ldr r3, [r3, #0]
|
|
800790e: 693a ldr r2, [r7, #16]
|
|
8007910: 429a cmp r2, r3
|
|
8007912: d00b beq.n 800792c <xTaskPriorityDisinherit+0x38>
|
|
__asm volatile
|
|
8007914: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007918: f383 8811 msr BASEPRI, r3
|
|
800791c: f3bf 8f6f isb sy
|
|
8007920: f3bf 8f4f dsb sy
|
|
8007924: 60fb str r3, [r7, #12]
|
|
}
|
|
8007926: bf00 nop
|
|
8007928: bf00 nop
|
|
800792a: e7fd b.n 8007928 <xTaskPriorityDisinherit+0x34>
|
|
configASSERT( pxTCB->uxMutexesHeld );
|
|
800792c: 693b ldr r3, [r7, #16]
|
|
800792e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8007930: 2b00 cmp r3, #0
|
|
8007932: d10b bne.n 800794c <xTaskPriorityDisinherit+0x58>
|
|
__asm volatile
|
|
8007934: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007938: f383 8811 msr BASEPRI, r3
|
|
800793c: f3bf 8f6f isb sy
|
|
8007940: f3bf 8f4f dsb sy
|
|
8007944: 60bb str r3, [r7, #8]
|
|
}
|
|
8007946: bf00 nop
|
|
8007948: bf00 nop
|
|
800794a: e7fd b.n 8007948 <xTaskPriorityDisinherit+0x54>
|
|
( pxTCB->uxMutexesHeld )--;
|
|
800794c: 693b ldr r3, [r7, #16]
|
|
800794e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8007950: 1e5a subs r2, r3, #1
|
|
8007952: 693b ldr r3, [r7, #16]
|
|
8007954: 649a str r2, [r3, #72] @ 0x48
|
|
|
|
/* Has the holder of the mutex inherited the priority of another
|
|
task? */
|
|
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
|
|
8007956: 693b ldr r3, [r7, #16]
|
|
8007958: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800795a: 693b ldr r3, [r7, #16]
|
|
800795c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800795e: 429a cmp r2, r3
|
|
8007960: d044 beq.n 80079ec <xTaskPriorityDisinherit+0xf8>
|
|
{
|
|
/* Only disinherit if no other mutexes are held. */
|
|
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
|
|
8007962: 693b ldr r3, [r7, #16]
|
|
8007964: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8007966: 2b00 cmp r3, #0
|
|
8007968: d140 bne.n 80079ec <xTaskPriorityDisinherit+0xf8>
|
|
/* A task can only have an inherited priority if it holds
|
|
the mutex. If the mutex is held by a task then it cannot be
|
|
given from an interrupt, and if a mutex is given by the
|
|
holding task then it must be the running state task. Remove
|
|
the holding task from the ready/delayed list. */
|
|
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
800796a: 693b ldr r3, [r7, #16]
|
|
800796c: 3304 adds r3, #4
|
|
800796e: 4618 mov r0, r3
|
|
8007970: f7ff f9ad bl 8006cce <uxListRemove>
|
|
8007974: 4603 mov r3, r0
|
|
8007976: 2b00 cmp r3, #0
|
|
8007978: d115 bne.n 80079a6 <xTaskPriorityDisinherit+0xb2>
|
|
{
|
|
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
|
|
800797a: 693b ldr r3, [r7, #16]
|
|
800797c: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
800797e: 491f ldr r1, [pc, #124] @ (80079fc <xTaskPriorityDisinherit+0x108>)
|
|
8007980: 4613 mov r3, r2
|
|
8007982: 009b lsls r3, r3, #2
|
|
8007984: 4413 add r3, r2
|
|
8007986: 009b lsls r3, r3, #2
|
|
8007988: 440b add r3, r1
|
|
800798a: 681b ldr r3, [r3, #0]
|
|
800798c: 2b00 cmp r3, #0
|
|
800798e: d10a bne.n 80079a6 <xTaskPriorityDisinherit+0xb2>
|
|
8007990: 693b ldr r3, [r7, #16]
|
|
8007992: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007994: 2201 movs r2, #1
|
|
8007996: fa02 f303 lsl.w r3, r2, r3
|
|
800799a: 43da mvns r2, r3
|
|
800799c: 4b18 ldr r3, [pc, #96] @ (8007a00 <xTaskPriorityDisinherit+0x10c>)
|
|
800799e: 681b ldr r3, [r3, #0]
|
|
80079a0: 4013 ands r3, r2
|
|
80079a2: 4a17 ldr r2, [pc, #92] @ (8007a00 <xTaskPriorityDisinherit+0x10c>)
|
|
80079a4: 6013 str r3, [r2, #0]
|
|
}
|
|
|
|
/* Disinherit the priority before adding the task into the
|
|
new ready list. */
|
|
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
|
|
pxTCB->uxPriority = pxTCB->uxBasePriority;
|
|
80079a6: 693b ldr r3, [r7, #16]
|
|
80079a8: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80079aa: 693b ldr r3, [r7, #16]
|
|
80079ac: 62da str r2, [r3, #44] @ 0x2c
|
|
|
|
/* Reset the event list item value. It cannot be in use for
|
|
any other purpose if this task is running, and it must be
|
|
running to give back the mutex. */
|
|
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
|
|
80079ae: 693b ldr r3, [r7, #16]
|
|
80079b0: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80079b2: f1c3 0207 rsb r2, r3, #7
|
|
80079b6: 693b ldr r3, [r7, #16]
|
|
80079b8: 619a str r2, [r3, #24]
|
|
prvAddTaskToReadyList( pxTCB );
|
|
80079ba: 693b ldr r3, [r7, #16]
|
|
80079bc: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
80079be: 2201 movs r2, #1
|
|
80079c0: 409a lsls r2, r3
|
|
80079c2: 4b0f ldr r3, [pc, #60] @ (8007a00 <xTaskPriorityDisinherit+0x10c>)
|
|
80079c4: 681b ldr r3, [r3, #0]
|
|
80079c6: 4313 orrs r3, r2
|
|
80079c8: 4a0d ldr r2, [pc, #52] @ (8007a00 <xTaskPriorityDisinherit+0x10c>)
|
|
80079ca: 6013 str r3, [r2, #0]
|
|
80079cc: 693b ldr r3, [r7, #16]
|
|
80079ce: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
80079d0: 4613 mov r3, r2
|
|
80079d2: 009b lsls r3, r3, #2
|
|
80079d4: 4413 add r3, r2
|
|
80079d6: 009b lsls r3, r3, #2
|
|
80079d8: 4a08 ldr r2, [pc, #32] @ (80079fc <xTaskPriorityDisinherit+0x108>)
|
|
80079da: 441a add r2, r3
|
|
80079dc: 693b ldr r3, [r7, #16]
|
|
80079de: 3304 adds r3, #4
|
|
80079e0: 4619 mov r1, r3
|
|
80079e2: 4610 mov r0, r2
|
|
80079e4: f7ff f916 bl 8006c14 <vListInsertEnd>
|
|
in an order different to that in which they were taken.
|
|
If a context switch did not occur when the first mutex was
|
|
returned, even if a task was waiting on it, then a context
|
|
switch should occur when the last mutex is returned whether
|
|
a task is waiting on it or not. */
|
|
xReturn = pdTRUE;
|
|
80079e8: 2301 movs r3, #1
|
|
80079ea: 617b str r3, [r7, #20]
|
|
else
|
|
{
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
return xReturn;
|
|
80079ec: 697b ldr r3, [r7, #20]
|
|
}
|
|
80079ee: 4618 mov r0, r3
|
|
80079f0: 3718 adds r7, #24
|
|
80079f2: 46bd mov sp, r7
|
|
80079f4: bd80 pop {r7, pc}
|
|
80079f6: bf00 nop
|
|
80079f8: 200002dc .word 0x200002dc
|
|
80079fc: 200002e0 .word 0x200002e0
|
|
8007a00: 200003a4 .word 0x200003a4
|
|
|
|
08007a04 <prvAddCurrentTaskToDelayedList>:
|
|
|
|
#endif
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
|
|
{
|
|
8007a04: b580 push {r7, lr}
|
|
8007a06: b084 sub sp, #16
|
|
8007a08: af00 add r7, sp, #0
|
|
8007a0a: 6078 str r0, [r7, #4]
|
|
8007a0c: 6039 str r1, [r7, #0]
|
|
TickType_t xTimeToWake;
|
|
const TickType_t xConstTickCount = xTickCount;
|
|
8007a0e: 4b29 ldr r3, [pc, #164] @ (8007ab4 <prvAddCurrentTaskToDelayedList+0xb0>)
|
|
8007a10: 681b ldr r3, [r3, #0]
|
|
8007a12: 60fb str r3, [r7, #12]
|
|
}
|
|
#endif
|
|
|
|
/* Remove the task from the ready list before adding it to the blocked list
|
|
as the same list item is used for both lists. */
|
|
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
|
|
8007a14: 4b28 ldr r3, [pc, #160] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a16: 681b ldr r3, [r3, #0]
|
|
8007a18: 3304 adds r3, #4
|
|
8007a1a: 4618 mov r0, r3
|
|
8007a1c: f7ff f957 bl 8006cce <uxListRemove>
|
|
8007a20: 4603 mov r3, r0
|
|
8007a22: 2b00 cmp r3, #0
|
|
8007a24: d10b bne.n 8007a3e <prvAddCurrentTaskToDelayedList+0x3a>
|
|
{
|
|
/* The current task must be in a ready list, so there is no need to
|
|
check, and the port reset macro can be called directly. */
|
|
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
|
|
8007a26: 4b24 ldr r3, [pc, #144] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a28: 681b ldr r3, [r3, #0]
|
|
8007a2a: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8007a2c: 2201 movs r2, #1
|
|
8007a2e: fa02 f303 lsl.w r3, r2, r3
|
|
8007a32: 43da mvns r2, r3
|
|
8007a34: 4b21 ldr r3, [pc, #132] @ (8007abc <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
8007a36: 681b ldr r3, [r3, #0]
|
|
8007a38: 4013 ands r3, r2
|
|
8007a3a: 4a20 ldr r2, [pc, #128] @ (8007abc <prvAddCurrentTaskToDelayedList+0xb8>)
|
|
8007a3c: 6013 str r3, [r2, #0]
|
|
mtCOVERAGE_TEST_MARKER();
|
|
}
|
|
|
|
#if ( INCLUDE_vTaskSuspend == 1 )
|
|
{
|
|
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
|
|
8007a3e: 687b ldr r3, [r7, #4]
|
|
8007a40: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8007a44: d10a bne.n 8007a5c <prvAddCurrentTaskToDelayedList+0x58>
|
|
8007a46: 683b ldr r3, [r7, #0]
|
|
8007a48: 2b00 cmp r3, #0
|
|
8007a4a: d007 beq.n 8007a5c <prvAddCurrentTaskToDelayedList+0x58>
|
|
{
|
|
/* Add the task to the suspended task list instead of a delayed task
|
|
list to ensure it is not woken by a timing event. It will block
|
|
indefinitely. */
|
|
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
8007a4c: 4b1a ldr r3, [pc, #104] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a4e: 681b ldr r3, [r3, #0]
|
|
8007a50: 3304 adds r3, #4
|
|
8007a52: 4619 mov r1, r3
|
|
8007a54: 481a ldr r0, [pc, #104] @ (8007ac0 <prvAddCurrentTaskToDelayedList+0xbc>)
|
|
8007a56: f7ff f8dd bl 8006c14 <vListInsertEnd>
|
|
|
|
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
|
|
( void ) xCanBlockIndefinitely;
|
|
}
|
|
#endif /* INCLUDE_vTaskSuspend */
|
|
}
|
|
8007a5a: e026 b.n 8007aaa <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xTimeToWake = xConstTickCount + xTicksToWait;
|
|
8007a5c: 68fa ldr r2, [r7, #12]
|
|
8007a5e: 687b ldr r3, [r7, #4]
|
|
8007a60: 4413 add r3, r2
|
|
8007a62: 60bb str r3, [r7, #8]
|
|
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
|
|
8007a64: 4b14 ldr r3, [pc, #80] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a66: 681b ldr r3, [r3, #0]
|
|
8007a68: 68ba ldr r2, [r7, #8]
|
|
8007a6a: 605a str r2, [r3, #4]
|
|
if( xTimeToWake < xConstTickCount )
|
|
8007a6c: 68ba ldr r2, [r7, #8]
|
|
8007a6e: 68fb ldr r3, [r7, #12]
|
|
8007a70: 429a cmp r2, r3
|
|
8007a72: d209 bcs.n 8007a88 <prvAddCurrentTaskToDelayedList+0x84>
|
|
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
8007a74: 4b13 ldr r3, [pc, #76] @ (8007ac4 <prvAddCurrentTaskToDelayedList+0xc0>)
|
|
8007a76: 681a ldr r2, [r3, #0]
|
|
8007a78: 4b0f ldr r3, [pc, #60] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a7a: 681b ldr r3, [r3, #0]
|
|
8007a7c: 3304 adds r3, #4
|
|
8007a7e: 4619 mov r1, r3
|
|
8007a80: 4610 mov r0, r2
|
|
8007a82: f7ff f8eb bl 8006c5c <vListInsert>
|
|
}
|
|
8007a86: e010 b.n 8007aaa <prvAddCurrentTaskToDelayedList+0xa6>
|
|
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
|
|
8007a88: 4b0f ldr r3, [pc, #60] @ (8007ac8 <prvAddCurrentTaskToDelayedList+0xc4>)
|
|
8007a8a: 681a ldr r2, [r3, #0]
|
|
8007a8c: 4b0a ldr r3, [pc, #40] @ (8007ab8 <prvAddCurrentTaskToDelayedList+0xb4>)
|
|
8007a8e: 681b ldr r3, [r3, #0]
|
|
8007a90: 3304 adds r3, #4
|
|
8007a92: 4619 mov r1, r3
|
|
8007a94: 4610 mov r0, r2
|
|
8007a96: f7ff f8e1 bl 8006c5c <vListInsert>
|
|
if( xTimeToWake < xNextTaskUnblockTime )
|
|
8007a9a: 4b0c ldr r3, [pc, #48] @ (8007acc <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
8007a9c: 681b ldr r3, [r3, #0]
|
|
8007a9e: 68ba ldr r2, [r7, #8]
|
|
8007aa0: 429a cmp r2, r3
|
|
8007aa2: d202 bcs.n 8007aaa <prvAddCurrentTaskToDelayedList+0xa6>
|
|
xNextTaskUnblockTime = xTimeToWake;
|
|
8007aa4: 4a09 ldr r2, [pc, #36] @ (8007acc <prvAddCurrentTaskToDelayedList+0xc8>)
|
|
8007aa6: 68bb ldr r3, [r7, #8]
|
|
8007aa8: 6013 str r3, [r2, #0]
|
|
}
|
|
8007aaa: bf00 nop
|
|
8007aac: 3710 adds r7, #16
|
|
8007aae: 46bd mov sp, r7
|
|
8007ab0: bd80 pop {r7, pc}
|
|
8007ab2: bf00 nop
|
|
8007ab4: 200003a0 .word 0x200003a0
|
|
8007ab8: 200002dc .word 0x200002dc
|
|
8007abc: 200003a4 .word 0x200003a4
|
|
8007ac0: 20000388 .word 0x20000388
|
|
8007ac4: 20000370 .word 0x20000370
|
|
8007ac8: 2000036c .word 0x2000036c
|
|
8007acc: 200003b8 .word 0x200003b8
|
|
|
|
08007ad0 <SVC_Handler>:
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortSVCHandler( void )
|
|
{
|
|
__asm volatile (
|
|
8007ad0: 4b07 ldr r3, [pc, #28] @ (8007af0 <pxCurrentTCBConst2>)
|
|
8007ad2: 6819 ldr r1, [r3, #0]
|
|
8007ad4: 6808 ldr r0, [r1, #0]
|
|
8007ad6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8007ada: f380 8809 msr PSP, r0
|
|
8007ade: f3bf 8f6f isb sy
|
|
8007ae2: f04f 0000 mov.w r0, #0
|
|
8007ae6: f380 8811 msr BASEPRI, r0
|
|
8007aea: 4770 bx lr
|
|
8007aec: f3af 8000 nop.w
|
|
|
|
08007af0 <pxCurrentTCBConst2>:
|
|
8007af0: 200002dc .word 0x200002dc
|
|
" bx r14 \n"
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
|
|
);
|
|
}
|
|
8007af4: bf00 nop
|
|
8007af6: bf00 nop
|
|
|
|
08007af8 <vPortEnterCritical>:
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
8007af8: b480 push {r7}
|
|
8007afa: b083 sub sp, #12
|
|
8007afc: af00 add r7, sp, #0
|
|
__asm volatile
|
|
8007afe: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007b02: f383 8811 msr BASEPRI, r3
|
|
8007b06: f3bf 8f6f isb sy
|
|
8007b0a: f3bf 8f4f dsb sy
|
|
8007b0e: 607b str r3, [r7, #4]
|
|
}
|
|
8007b10: bf00 nop
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
8007b12: 4b10 ldr r3, [pc, #64] @ (8007b54 <vPortEnterCritical+0x5c>)
|
|
8007b14: 681b ldr r3, [r3, #0]
|
|
8007b16: 3301 adds r3, #1
|
|
8007b18: 4a0e ldr r2, [pc, #56] @ (8007b54 <vPortEnterCritical+0x5c>)
|
|
8007b1a: 6013 str r3, [r2, #0]
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
assert() if it is being called from an interrupt context. Only API
|
|
functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
the critical nesting count is 1 to protect against recursive calls if the
|
|
assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
8007b1c: 4b0d ldr r3, [pc, #52] @ (8007b54 <vPortEnterCritical+0x5c>)
|
|
8007b1e: 681b ldr r3, [r3, #0]
|
|
8007b20: 2b01 cmp r3, #1
|
|
8007b22: d110 bne.n 8007b46 <vPortEnterCritical+0x4e>
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
8007b24: 4b0c ldr r3, [pc, #48] @ (8007b58 <vPortEnterCritical+0x60>)
|
|
8007b26: 681b ldr r3, [r3, #0]
|
|
8007b28: b2db uxtb r3, r3
|
|
8007b2a: 2b00 cmp r3, #0
|
|
8007b2c: d00b beq.n 8007b46 <vPortEnterCritical+0x4e>
|
|
__asm volatile
|
|
8007b2e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007b32: f383 8811 msr BASEPRI, r3
|
|
8007b36: f3bf 8f6f isb sy
|
|
8007b3a: f3bf 8f4f dsb sy
|
|
8007b3e: 603b str r3, [r7, #0]
|
|
}
|
|
8007b40: bf00 nop
|
|
8007b42: bf00 nop
|
|
8007b44: e7fd b.n 8007b42 <vPortEnterCritical+0x4a>
|
|
}
|
|
}
|
|
8007b46: bf00 nop
|
|
8007b48: 370c adds r7, #12
|
|
8007b4a: 46bd mov sp, r7
|
|
8007b4c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007b50: 4770 bx lr
|
|
8007b52: bf00 nop
|
|
8007b54: 2000000c .word 0x2000000c
|
|
8007b58: e000ed04 .word 0xe000ed04
|
|
|
|
08007b5c <vPortExitCritical>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
8007b5c: b480 push {r7}
|
|
8007b5e: b083 sub sp, #12
|
|
8007b60: af00 add r7, sp, #0
|
|
configASSERT( uxCriticalNesting );
|
|
8007b62: 4b12 ldr r3, [pc, #72] @ (8007bac <vPortExitCritical+0x50>)
|
|
8007b64: 681b ldr r3, [r3, #0]
|
|
8007b66: 2b00 cmp r3, #0
|
|
8007b68: d10b bne.n 8007b82 <vPortExitCritical+0x26>
|
|
__asm volatile
|
|
8007b6a: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007b6e: f383 8811 msr BASEPRI, r3
|
|
8007b72: f3bf 8f6f isb sy
|
|
8007b76: f3bf 8f4f dsb sy
|
|
8007b7a: 607b str r3, [r7, #4]
|
|
}
|
|
8007b7c: bf00 nop
|
|
8007b7e: bf00 nop
|
|
8007b80: e7fd b.n 8007b7e <vPortExitCritical+0x22>
|
|
uxCriticalNesting--;
|
|
8007b82: 4b0a ldr r3, [pc, #40] @ (8007bac <vPortExitCritical+0x50>)
|
|
8007b84: 681b ldr r3, [r3, #0]
|
|
8007b86: 3b01 subs r3, #1
|
|
8007b88: 4a08 ldr r2, [pc, #32] @ (8007bac <vPortExitCritical+0x50>)
|
|
8007b8a: 6013 str r3, [r2, #0]
|
|
if( uxCriticalNesting == 0 )
|
|
8007b8c: 4b07 ldr r3, [pc, #28] @ (8007bac <vPortExitCritical+0x50>)
|
|
8007b8e: 681b ldr r3, [r3, #0]
|
|
8007b90: 2b00 cmp r3, #0
|
|
8007b92: d105 bne.n 8007ba0 <vPortExitCritical+0x44>
|
|
8007b94: 2300 movs r3, #0
|
|
8007b96: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
8007b98: 683b ldr r3, [r7, #0]
|
|
8007b9a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8007b9e: bf00 nop
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
}
|
|
8007ba0: bf00 nop
|
|
8007ba2: 370c adds r7, #12
|
|
8007ba4: 46bd mov sp, r7
|
|
8007ba6: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007baa: 4770 bx lr
|
|
8007bac: 2000000c .word 0x2000000c
|
|
|
|
08007bb0 <PendSV_Handler>:
|
|
|
|
void xPortPendSVHandler( void )
|
|
{
|
|
/* This is a naked function. */
|
|
|
|
__asm volatile
|
|
8007bb0: f3ef 8009 mrs r0, PSP
|
|
8007bb4: f3bf 8f6f isb sy
|
|
8007bb8: 4b15 ldr r3, [pc, #84] @ (8007c10 <pxCurrentTCBConst>)
|
|
8007bba: 681a ldr r2, [r3, #0]
|
|
8007bbc: f01e 0f10 tst.w lr, #16
|
|
8007bc0: bf08 it eq
|
|
8007bc2: ed20 8a10 vstmdbeq r0!, {s16-s31}
|
|
8007bc6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8007bca: 6010 str r0, [r2, #0]
|
|
8007bcc: e92d 0009 stmdb sp!, {r0, r3}
|
|
8007bd0: f04f 0050 mov.w r0, #80 @ 0x50
|
|
8007bd4: f380 8811 msr BASEPRI, r0
|
|
8007bd8: f3bf 8f4f dsb sy
|
|
8007bdc: f3bf 8f6f isb sy
|
|
8007be0: f7ff fcb8 bl 8007554 <vTaskSwitchContext>
|
|
8007be4: f04f 0000 mov.w r0, #0
|
|
8007be8: f380 8811 msr BASEPRI, r0
|
|
8007bec: bc09 pop {r0, r3}
|
|
8007bee: 6819 ldr r1, [r3, #0]
|
|
8007bf0: 6808 ldr r0, [r1, #0]
|
|
8007bf2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8007bf6: f01e 0f10 tst.w lr, #16
|
|
8007bfa: bf08 it eq
|
|
8007bfc: ecb0 8a10 vldmiaeq r0!, {s16-s31}
|
|
8007c00: f380 8809 msr PSP, r0
|
|
8007c04: f3bf 8f6f isb sy
|
|
8007c08: 4770 bx lr
|
|
8007c0a: bf00 nop
|
|
8007c0c: f3af 8000 nop.w
|
|
|
|
08007c10 <pxCurrentTCBConst>:
|
|
8007c10: 200002dc .word 0x200002dc
|
|
" \n"
|
|
" .align 4 \n"
|
|
"pxCurrentTCBConst: .word pxCurrentTCB \n"
|
|
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
|
|
);
|
|
}
|
|
8007c14: bf00 nop
|
|
8007c16: bf00 nop
|
|
|
|
08007c18 <SysTick_Handler>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
8007c18: b580 push {r7, lr}
|
|
8007c1a: b082 sub sp, #8
|
|
8007c1c: af00 add r7, sp, #0
|
|
__asm volatile
|
|
8007c1e: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007c22: f383 8811 msr BASEPRI, r3
|
|
8007c26: f3bf 8f6f isb sy
|
|
8007c2a: f3bf 8f4f dsb sy
|
|
8007c2e: 607b str r3, [r7, #4]
|
|
}
|
|
8007c30: bf00 nop
|
|
save and then restore the interrupt mask value as its value is already
|
|
known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
8007c32: f7ff fbd5 bl 80073e0 <xTaskIncrementTick>
|
|
8007c36: 4603 mov r3, r0
|
|
8007c38: 2b00 cmp r3, #0
|
|
8007c3a: d003 beq.n 8007c44 <SysTick_Handler+0x2c>
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
8007c3c: 4b06 ldr r3, [pc, #24] @ (8007c58 <SysTick_Handler+0x40>)
|
|
8007c3e: f04f 5280 mov.w r2, #268435456 @ 0x10000000
|
|
8007c42: 601a str r2, [r3, #0]
|
|
8007c44: 2300 movs r3, #0
|
|
8007c46: 603b str r3, [r7, #0]
|
|
__asm volatile
|
|
8007c48: 683b ldr r3, [r7, #0]
|
|
8007c4a: f383 8811 msr BASEPRI, r3
|
|
}
|
|
8007c4e: bf00 nop
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
8007c50: bf00 nop
|
|
8007c52: 3708 adds r7, #8
|
|
8007c54: 46bd mov sp, r7
|
|
8007c56: bd80 pop {r7, pc}
|
|
8007c58: e000ed04 .word 0xe000ed04
|
|
|
|
08007c5c <vPortValidateInterruptPriority>:
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
8007c5c: b480 push {r7}
|
|
8007c5e: b085 sub sp, #20
|
|
8007c60: af00 add r7, sp, #0
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
|
|
8007c62: f3ef 8305 mrs r3, IPSR
|
|
8007c66: 60fb str r3, [r7, #12]
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
8007c68: 68fb ldr r3, [r7, #12]
|
|
8007c6a: 2b0f cmp r3, #15
|
|
8007c6c: d915 bls.n 8007c9a <vPortValidateInterruptPriority+0x3e>
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
8007c6e: 4a18 ldr r2, [pc, #96] @ (8007cd0 <vPortValidateInterruptPriority+0x74>)
|
|
8007c70: 68fb ldr r3, [r7, #12]
|
|
8007c72: 4413 add r3, r2
|
|
8007c74: 781b ldrb r3, [r3, #0]
|
|
8007c76: 72fb strb r3, [r7, #11]
|
|
interrupt entry is as fast and simple as possible.
|
|
|
|
The following links provide detailed information:
|
|
http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
http://www.freertos.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
8007c78: 4b16 ldr r3, [pc, #88] @ (8007cd4 <vPortValidateInterruptPriority+0x78>)
|
|
8007c7a: 781b ldrb r3, [r3, #0]
|
|
8007c7c: 7afa ldrb r2, [r7, #11]
|
|
8007c7e: 429a cmp r2, r3
|
|
8007c80: d20b bcs.n 8007c9a <vPortValidateInterruptPriority+0x3e>
|
|
__asm volatile
|
|
8007c82: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007c86: f383 8811 msr BASEPRI, r3
|
|
8007c8a: f3bf 8f6f isb sy
|
|
8007c8e: f3bf 8f4f dsb sy
|
|
8007c92: 607b str r3, [r7, #4]
|
|
}
|
|
8007c94: bf00 nop
|
|
8007c96: bf00 nop
|
|
8007c98: e7fd b.n 8007c96 <vPortValidateInterruptPriority+0x3a>
|
|
configuration then the correct setting can be achieved on all Cortex-M
|
|
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
scheduler. Note however that some vendor specific peripheral libraries
|
|
assume a non-zero priority group setting, in which cases using a value
|
|
of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
8007c9a: 4b0f ldr r3, [pc, #60] @ (8007cd8 <vPortValidateInterruptPriority+0x7c>)
|
|
8007c9c: 681b ldr r3, [r3, #0]
|
|
8007c9e: f403 62e0 and.w r2, r3, #1792 @ 0x700
|
|
8007ca2: 4b0e ldr r3, [pc, #56] @ (8007cdc <vPortValidateInterruptPriority+0x80>)
|
|
8007ca4: 681b ldr r3, [r3, #0]
|
|
8007ca6: 429a cmp r2, r3
|
|
8007ca8: d90b bls.n 8007cc2 <vPortValidateInterruptPriority+0x66>
|
|
__asm volatile
|
|
8007caa: f04f 0350 mov.w r3, #80 @ 0x50
|
|
8007cae: f383 8811 msr BASEPRI, r3
|
|
8007cb2: f3bf 8f6f isb sy
|
|
8007cb6: f3bf 8f4f dsb sy
|
|
8007cba: 603b str r3, [r7, #0]
|
|
}
|
|
8007cbc: bf00 nop
|
|
8007cbe: bf00 nop
|
|
8007cc0: e7fd b.n 8007cbe <vPortValidateInterruptPriority+0x62>
|
|
}
|
|
8007cc2: bf00 nop
|
|
8007cc4: 3714 adds r7, #20
|
|
8007cc6: 46bd mov sp, r7
|
|
8007cc8: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007ccc: 4770 bx lr
|
|
8007cce: bf00 nop
|
|
8007cd0: e000e3f0 .word 0xe000e3f0
|
|
8007cd4: 200003c0 .word 0x200003c0
|
|
8007cd8: e000ed0c .word 0xe000ed0c
|
|
8007cdc: 200003c4 .word 0x200003c4
|
|
|
|
08007ce0 <HAL_HCD_SOF_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8007ce0: b580 push {r7, lr}
|
|
8007ce2: b082 sub sp, #8
|
|
8007ce4: af00 add r7, sp, #0
|
|
8007ce6: 6078 str r0, [r7, #4]
|
|
USBH_LL_IncTimer(hhcd->pData);
|
|
8007ce8: 687b ldr r3, [r7, #4]
|
|
8007cea: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007cee: 4618 mov r0, r3
|
|
8007cf0: f7fe fe40 bl 8006974 <USBH_LL_IncTimer>
|
|
}
|
|
8007cf4: bf00 nop
|
|
8007cf6: 3708 adds r7, #8
|
|
8007cf8: 46bd mov sp, r7
|
|
8007cfa: bd80 pop {r7, pc}
|
|
|
|
08007cfc <HAL_HCD_Connect_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8007cfc: b580 push {r7, lr}
|
|
8007cfe: b082 sub sp, #8
|
|
8007d00: af00 add r7, sp, #0
|
|
8007d02: 6078 str r0, [r7, #4]
|
|
USBH_LL_Connect(hhcd->pData);
|
|
8007d04: 687b ldr r3, [r7, #4]
|
|
8007d06: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007d0a: 4618 mov r0, r3
|
|
8007d0c: f7fe fe80 bl 8006a10 <USBH_LL_Connect>
|
|
}
|
|
8007d10: bf00 nop
|
|
8007d12: 3708 adds r7, #8
|
|
8007d14: 46bd mov sp, r7
|
|
8007d16: bd80 pop {r7, pc}
|
|
|
|
08007d18 <HAL_HCD_Disconnect_Callback>:
|
|
* @brief SOF callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8007d18: b580 push {r7, lr}
|
|
8007d1a: b082 sub sp, #8
|
|
8007d1c: af00 add r7, sp, #0
|
|
8007d1e: 6078 str r0, [r7, #4]
|
|
USBH_LL_Disconnect(hhcd->pData);
|
|
8007d20: 687b ldr r3, [r7, #4]
|
|
8007d22: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007d26: 4618 mov r0, r3
|
|
8007d28: f7fe fe8d bl 8006a46 <USBH_LL_Disconnect>
|
|
}
|
|
8007d2c: bf00 nop
|
|
8007d2e: 3708 adds r7, #8
|
|
8007d30: 46bd mov sp, r7
|
|
8007d32: bd80 pop {r7, pc}
|
|
|
|
08007d34 <HAL_HCD_HC_NotifyURBChange_Callback>:
|
|
* @param chnum: channel number
|
|
* @param urb_state: state
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
|
|
{
|
|
8007d34: b580 push {r7, lr}
|
|
8007d36: b082 sub sp, #8
|
|
8007d38: af00 add r7, sp, #0
|
|
8007d3a: 6078 str r0, [r7, #4]
|
|
8007d3c: 460b mov r3, r1
|
|
8007d3e: 70fb strb r3, [r7, #3]
|
|
8007d40: 4613 mov r3, r2
|
|
8007d42: 70bb strb r3, [r7, #2]
|
|
/* To be used with OS to sync URB state with the global state machine */
|
|
#if (USBH_USE_OS == 1)
|
|
USBH_LL_NotifyURBChange(hhcd->pData);
|
|
8007d44: 687b ldr r3, [r7, #4]
|
|
8007d46: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007d4a: 4618 mov r0, r3
|
|
8007d4c: f7fe fecc bl 8006ae8 <USBH_LL_NotifyURBChange>
|
|
#endif
|
|
}
|
|
8007d50: bf00 nop
|
|
8007d52: 3708 adds r7, #8
|
|
8007d54: 46bd mov sp, r7
|
|
8007d56: bd80 pop {r7, pc}
|
|
|
|
08007d58 <HAL_HCD_PortEnabled_Callback>:
|
|
* @brief Port Port Enabled callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8007d58: b580 push {r7, lr}
|
|
8007d5a: b082 sub sp, #8
|
|
8007d5c: af00 add r7, sp, #0
|
|
8007d5e: 6078 str r0, [r7, #4]
|
|
USBH_LL_PortEnabled(hhcd->pData);
|
|
8007d60: 687b ldr r3, [r7, #4]
|
|
8007d62: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007d66: 4618 mov r0, r3
|
|
8007d68: f7fe fe2e bl 80069c8 <USBH_LL_PortEnabled>
|
|
}
|
|
8007d6c: bf00 nop
|
|
8007d6e: 3708 adds r7, #8
|
|
8007d70: 46bd mov sp, r7
|
|
8007d72: bd80 pop {r7, pc}
|
|
|
|
08007d74 <HAL_HCD_PortDisabled_Callback>:
|
|
* @brief Port Port Disabled callback.
|
|
* @param hhcd: HCD handle
|
|
* @retval None
|
|
*/
|
|
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
|
|
{
|
|
8007d74: b580 push {r7, lr}
|
|
8007d76: b082 sub sp, #8
|
|
8007d78: af00 add r7, sp, #0
|
|
8007d7a: 6078 str r0, [r7, #4]
|
|
USBH_LL_PortDisabled(hhcd->pData);
|
|
8007d7c: 687b ldr r3, [r7, #4]
|
|
8007d7e: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
|
|
8007d82: 4618 mov r0, r3
|
|
8007d84: f7fe fe32 bl 80069ec <USBH_LL_PortDisabled>
|
|
}
|
|
8007d88: bf00 nop
|
|
8007d8a: 3708 adds r7, #8
|
|
8007d8c: 46bd mov sp, r7
|
|
8007d8e: bd80 pop {r7, pc}
|
|
|
|
08007d90 <USBH_LL_Stop>:
|
|
* @brief Stop the low level portion of the host driver.
|
|
* @param phost: Host handle
|
|
* @retval USBH status
|
|
*/
|
|
USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost)
|
|
{
|
|
8007d90: b580 push {r7, lr}
|
|
8007d92: b084 sub sp, #16
|
|
8007d94: af00 add r7, sp, #0
|
|
8007d96: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef hal_status = HAL_OK;
|
|
8007d98: 2300 movs r3, #0
|
|
8007d9a: 73fb strb r3, [r7, #15]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
8007d9c: 2300 movs r3, #0
|
|
8007d9e: 73bb strb r3, [r7, #14]
|
|
|
|
hal_status = HAL_HCD_Stop(phost->pData);
|
|
8007da0: 687b ldr r3, [r7, #4]
|
|
8007da2: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
|
|
8007da6: 4618 mov r0, r3
|
|
8007da8: f7fa fa21 bl 80021ee <HAL_HCD_Stop>
|
|
8007dac: 4603 mov r3, r0
|
|
8007dae: 73fb strb r3, [r7, #15]
|
|
|
|
usb_status = USBH_Get_USB_Status(hal_status);
|
|
8007db0: 7bfb ldrb r3, [r7, #15]
|
|
8007db2: 4618 mov r0, r3
|
|
8007db4: f000 f808 bl 8007dc8 <USBH_Get_USB_Status>
|
|
8007db8: 4603 mov r3, r0
|
|
8007dba: 73bb strb r3, [r7, #14]
|
|
|
|
return usb_status;
|
|
8007dbc: 7bbb ldrb r3, [r7, #14]
|
|
}
|
|
8007dbe: 4618 mov r0, r3
|
|
8007dc0: 3710 adds r7, #16
|
|
8007dc2: 46bd mov sp, r7
|
|
8007dc4: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08007dc8 <USBH_Get_USB_Status>:
|
|
* @brief Returns the USB status depending on the HAL status:
|
|
* @param hal_status: HAL status
|
|
* @retval USB status
|
|
*/
|
|
USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status)
|
|
{
|
|
8007dc8: b480 push {r7}
|
|
8007dca: b085 sub sp, #20
|
|
8007dcc: af00 add r7, sp, #0
|
|
8007dce: 4603 mov r3, r0
|
|
8007dd0: 71fb strb r3, [r7, #7]
|
|
USBH_StatusTypeDef usb_status = USBH_OK;
|
|
8007dd2: 2300 movs r3, #0
|
|
8007dd4: 73fb strb r3, [r7, #15]
|
|
|
|
switch (hal_status)
|
|
8007dd6: 79fb ldrb r3, [r7, #7]
|
|
8007dd8: 2b03 cmp r3, #3
|
|
8007dda: d817 bhi.n 8007e0c <USBH_Get_USB_Status+0x44>
|
|
8007ddc: a201 add r2, pc, #4 @ (adr r2, 8007de4 <USBH_Get_USB_Status+0x1c>)
|
|
8007dde: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8007de2: bf00 nop
|
|
8007de4: 08007df5 .word 0x08007df5
|
|
8007de8: 08007dfb .word 0x08007dfb
|
|
8007dec: 08007e01 .word 0x08007e01
|
|
8007df0: 08007e07 .word 0x08007e07
|
|
{
|
|
case HAL_OK :
|
|
usb_status = USBH_OK;
|
|
8007df4: 2300 movs r3, #0
|
|
8007df6: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007df8: e00b b.n 8007e12 <USBH_Get_USB_Status+0x4a>
|
|
case HAL_ERROR :
|
|
usb_status = USBH_FAIL;
|
|
8007dfa: 2302 movs r3, #2
|
|
8007dfc: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007dfe: e008 b.n 8007e12 <USBH_Get_USB_Status+0x4a>
|
|
case HAL_BUSY :
|
|
usb_status = USBH_BUSY;
|
|
8007e00: 2301 movs r3, #1
|
|
8007e02: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007e04: e005 b.n 8007e12 <USBH_Get_USB_Status+0x4a>
|
|
case HAL_TIMEOUT :
|
|
usb_status = USBH_FAIL;
|
|
8007e06: 2302 movs r3, #2
|
|
8007e08: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007e0a: e002 b.n 8007e12 <USBH_Get_USB_Status+0x4a>
|
|
default :
|
|
usb_status = USBH_FAIL;
|
|
8007e0c: 2302 movs r3, #2
|
|
8007e0e: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8007e10: bf00 nop
|
|
}
|
|
return usb_status;
|
|
8007e12: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8007e14: 4618 mov r0, r3
|
|
8007e16: 3714 adds r7, #20
|
|
8007e18: 46bd mov sp, r7
|
|
8007e1a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8007e1e: 4770 bx lr
|
|
|
|
08007e20 <memset>:
|
|
8007e20: 4402 add r2, r0
|
|
8007e22: 4603 mov r3, r0
|
|
8007e24: 4293 cmp r3, r2
|
|
8007e26: d100 bne.n 8007e2a <memset+0xa>
|
|
8007e28: 4770 bx lr
|
|
8007e2a: f803 1b01 strb.w r1, [r3], #1
|
|
8007e2e: e7f9 b.n 8007e24 <memset+0x4>
|
|
|
|
08007e30 <__libc_init_array>:
|
|
8007e30: b570 push {r4, r5, r6, lr}
|
|
8007e32: 4d0d ldr r5, [pc, #52] @ (8007e68 <__libc_init_array+0x38>)
|
|
8007e34: 4c0d ldr r4, [pc, #52] @ (8007e6c <__libc_init_array+0x3c>)
|
|
8007e36: 1b64 subs r4, r4, r5
|
|
8007e38: 10a4 asrs r4, r4, #2
|
|
8007e3a: 2600 movs r6, #0
|
|
8007e3c: 42a6 cmp r6, r4
|
|
8007e3e: d109 bne.n 8007e54 <__libc_init_array+0x24>
|
|
8007e40: 4d0b ldr r5, [pc, #44] @ (8007e70 <__libc_init_array+0x40>)
|
|
8007e42: 4c0c ldr r4, [pc, #48] @ (8007e74 <__libc_init_array+0x44>)
|
|
8007e44: f000 f826 bl 8007e94 <_init>
|
|
8007e48: 1b64 subs r4, r4, r5
|
|
8007e4a: 10a4 asrs r4, r4, #2
|
|
8007e4c: 2600 movs r6, #0
|
|
8007e4e: 42a6 cmp r6, r4
|
|
8007e50: d105 bne.n 8007e5e <__libc_init_array+0x2e>
|
|
8007e52: bd70 pop {r4, r5, r6, pc}
|
|
8007e54: f855 3b04 ldr.w r3, [r5], #4
|
|
8007e58: 4798 blx r3
|
|
8007e5a: 3601 adds r6, #1
|
|
8007e5c: e7ee b.n 8007e3c <__libc_init_array+0xc>
|
|
8007e5e: f855 3b04 ldr.w r3, [r5], #4
|
|
8007e62: 4798 blx r3
|
|
8007e64: 3601 adds r6, #1
|
|
8007e66: e7f2 b.n 8007e4e <__libc_init_array+0x1e>
|
|
8007e68: 08007ecc .word 0x08007ecc
|
|
8007e6c: 08007ecc .word 0x08007ecc
|
|
8007e70: 08007ecc .word 0x08007ecc
|
|
8007e74: 08007ed0 .word 0x08007ed0
|
|
|
|
08007e78 <memcpy>:
|
|
8007e78: 440a add r2, r1
|
|
8007e7a: 4291 cmp r1, r2
|
|
8007e7c: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
8007e80: d100 bne.n 8007e84 <memcpy+0xc>
|
|
8007e82: 4770 bx lr
|
|
8007e84: b510 push {r4, lr}
|
|
8007e86: f811 4b01 ldrb.w r4, [r1], #1
|
|
8007e8a: f803 4f01 strb.w r4, [r3, #1]!
|
|
8007e8e: 4291 cmp r1, r2
|
|
8007e90: d1f9 bne.n 8007e86 <memcpy+0xe>
|
|
8007e92: bd10 pop {r4, pc}
|
|
|
|
08007e94 <_init>:
|
|
8007e94: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007e96: bf00 nop
|
|
8007e98: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8007e9a: bc08 pop {r3}
|
|
8007e9c: 469e mov lr, r3
|
|
8007e9e: 4770 bx lr
|
|
|
|
08007ea0 <_fini>:
|
|
8007ea0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8007ea2: bf00 nop
|
|
8007ea4: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8007ea6: bc08 pop {r3}
|
|
8007ea8: 469e mov lr, r3
|
|
8007eaa: 4770 bx lr
|