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e698ea0bd96867c8a98cdd04a6a76775d227c147
STMRepo/TrafficLightsPlus/Debug/TrafficLightsPlus.list
jazz (gitea) 1dc8fb80f1 fix traffic lights
2025-09-20 15:00:09 -05:00

21014 lines
772 KiB
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TrafficLightsPlus.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001ac 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00007d6c 080001b0 080001b0 000011b0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08007f1c 08007f1c 00008f1c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08007f34 08007f34 00009010 2**0
CONTENTS, READONLY
4 .ARM 00000008 08007f34 08007f34 00008f34 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08007f3c 08007f3c 00009010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08007f3c 08007f3c 00008f3c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08007f40 08007f40 00008f40 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000010 20000000 08007f44 00009000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .ccmram 00000000 10000000 10000000 00009010 2**0
CONTENTS
10 .bss 00000798 20000010 20000010 00009010 2**2
ALLOC
11 ._user_heap_stack 00000600 200007a8 200007a8 00009010 2**0
ALLOC
12 .ARM.attributes 00000030 00000000 00000000 00009010 2**0
CONTENTS, READONLY
13 .debug_info 00024fcd 00000000 00000000 00009040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 00004e45 00000000 00000000 0002e00d 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00002090 00000000 00000000 00032e58 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 00001956 00000000 00000000 00034ee8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 00028e32 00000000 00000000 0003683e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 00025434 00000000 00000000 0005f670 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 000f41e1 00000000 00000000 00084aa4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .comment 00000043 00000000 00000000 00178c85 2**0
CONTENTS, READONLY
21 .debug_frame 00008bf0 00000000 00000000 00178cc8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_line_str 00000051 00000000 00000000 001818b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001b0 <__do_global_dtors_aux>:
80001b0: b510 push {r4, lr}
80001b2: 4c05 ldr r4, [pc, #20] @ (80001c8 <__do_global_dtors_aux+0x18>)
80001b4: 7823 ldrb r3, [r4, #0]
80001b6: b933 cbnz r3, 80001c6 <__do_global_dtors_aux+0x16>
80001b8: 4b04 ldr r3, [pc, #16] @ (80001cc <__do_global_dtors_aux+0x1c>)
80001ba: b113 cbz r3, 80001c2 <__do_global_dtors_aux+0x12>
80001bc: 4804 ldr r0, [pc, #16] @ (80001d0 <__do_global_dtors_aux+0x20>)
80001be: f3af 8000 nop.w
80001c2: 2301 movs r3, #1
80001c4: 7023 strb r3, [r4, #0]
80001c6: bd10 pop {r4, pc}
80001c8: 20000010 .word 0x20000010
80001cc: 00000000 .word 0x00000000
80001d0: 08007f04 .word 0x08007f04
080001d4 <frame_dummy>:
80001d4: b508 push {r3, lr}
80001d6: 4b03 ldr r3, [pc, #12] @ (80001e4 <frame_dummy+0x10>)
80001d8: b11b cbz r3, 80001e2 <frame_dummy+0xe>
80001da: 4903 ldr r1, [pc, #12] @ (80001e8 <frame_dummy+0x14>)
80001dc: 4803 ldr r0, [pc, #12] @ (80001ec <frame_dummy+0x18>)
80001de: f3af 8000 nop.w
80001e2: bd08 pop {r3, pc}
80001e4: 00000000 .word 0x00000000
80001e8: 20000014 .word 0x20000014
80001ec: 08007f04 .word 0x08007f04
080001f0 <__aeabi_uldivmod>:
80001f0: b953 cbnz r3, 8000208 <__aeabi_uldivmod+0x18>
80001f2: b94a cbnz r2, 8000208 <__aeabi_uldivmod+0x18>
80001f4: 2900 cmp r1, #0
80001f6: bf08 it eq
80001f8: 2800 cmpeq r0, #0
80001fa: bf1c itt ne
80001fc: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
8000200: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
8000204: f000 b988 b.w 8000518 <__aeabi_idiv0>
8000208: f1ad 0c08 sub.w ip, sp, #8
800020c: e96d ce04 strd ip, lr, [sp, #-16]!
8000210: f000 f806 bl 8000220 <__udivmoddi4>
8000214: f8dd e004 ldr.w lr, [sp, #4]
8000218: e9dd 2302 ldrd r2, r3, [sp, #8]
800021c: b004 add sp, #16
800021e: 4770 bx lr
08000220 <__udivmoddi4>:
8000220: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000224: 9d08 ldr r5, [sp, #32]
8000226: 468e mov lr, r1
8000228: 4604 mov r4, r0
800022a: 4688 mov r8, r1
800022c: 2b00 cmp r3, #0
800022e: d14a bne.n 80002c6 <__udivmoddi4+0xa6>
8000230: 428a cmp r2, r1
8000232: 4617 mov r7, r2
8000234: d962 bls.n 80002fc <__udivmoddi4+0xdc>
8000236: fab2 f682 clz r6, r2
800023a: b14e cbz r6, 8000250 <__udivmoddi4+0x30>
800023c: f1c6 0320 rsb r3, r6, #32
8000240: fa01 f806 lsl.w r8, r1, r6
8000244: fa20 f303 lsr.w r3, r0, r3
8000248: 40b7 lsls r7, r6
800024a: ea43 0808 orr.w r8, r3, r8
800024e: 40b4 lsls r4, r6
8000250: ea4f 4e17 mov.w lr, r7, lsr #16
8000254: fa1f fc87 uxth.w ip, r7
8000258: fbb8 f1fe udiv r1, r8, lr
800025c: 0c23 lsrs r3, r4, #16
800025e: fb0e 8811 mls r8, lr, r1, r8
8000262: ea43 4308 orr.w r3, r3, r8, lsl #16
8000266: fb01 f20c mul.w r2, r1, ip
800026a: 429a cmp r2, r3
800026c: d909 bls.n 8000282 <__udivmoddi4+0x62>
800026e: 18fb adds r3, r7, r3
8000270: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
8000274: f080 80ea bcs.w 800044c <__udivmoddi4+0x22c>
8000278: 429a cmp r2, r3
800027a: f240 80e7 bls.w 800044c <__udivmoddi4+0x22c>
800027e: 3902 subs r1, #2
8000280: 443b add r3, r7
8000282: 1a9a subs r2, r3, r2
8000284: b2a3 uxth r3, r4
8000286: fbb2 f0fe udiv r0, r2, lr
800028a: fb0e 2210 mls r2, lr, r0, r2
800028e: ea43 4302 orr.w r3, r3, r2, lsl #16
8000292: fb00 fc0c mul.w ip, r0, ip
8000296: 459c cmp ip, r3
8000298: d909 bls.n 80002ae <__udivmoddi4+0x8e>
800029a: 18fb adds r3, r7, r3
800029c: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
80002a0: f080 80d6 bcs.w 8000450 <__udivmoddi4+0x230>
80002a4: 459c cmp ip, r3
80002a6: f240 80d3 bls.w 8000450 <__udivmoddi4+0x230>
80002aa: 443b add r3, r7
80002ac: 3802 subs r0, #2
80002ae: ea40 4001 orr.w r0, r0, r1, lsl #16
80002b2: eba3 030c sub.w r3, r3, ip
80002b6: 2100 movs r1, #0
80002b8: b11d cbz r5, 80002c2 <__udivmoddi4+0xa2>
80002ba: 40f3 lsrs r3, r6
80002bc: 2200 movs r2, #0
80002be: e9c5 3200 strd r3, r2, [r5]
80002c2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c6: 428b cmp r3, r1
80002c8: d905 bls.n 80002d6 <__udivmoddi4+0xb6>
80002ca: b10d cbz r5, 80002d0 <__udivmoddi4+0xb0>
80002cc: e9c5 0100 strd r0, r1, [r5]
80002d0: 2100 movs r1, #0
80002d2: 4608 mov r0, r1
80002d4: e7f5 b.n 80002c2 <__udivmoddi4+0xa2>
80002d6: fab3 f183 clz r1, r3
80002da: 2900 cmp r1, #0
80002dc: d146 bne.n 800036c <__udivmoddi4+0x14c>
80002de: 4573 cmp r3, lr
80002e0: d302 bcc.n 80002e8 <__udivmoddi4+0xc8>
80002e2: 4282 cmp r2, r0
80002e4: f200 8105 bhi.w 80004f2 <__udivmoddi4+0x2d2>
80002e8: 1a84 subs r4, r0, r2
80002ea: eb6e 0203 sbc.w r2, lr, r3
80002ee: 2001 movs r0, #1
80002f0: 4690 mov r8, r2
80002f2: 2d00 cmp r5, #0
80002f4: d0e5 beq.n 80002c2 <__udivmoddi4+0xa2>
80002f6: e9c5 4800 strd r4, r8, [r5]
80002fa: e7e2 b.n 80002c2 <__udivmoddi4+0xa2>
80002fc: 2a00 cmp r2, #0
80002fe: f000 8090 beq.w 8000422 <__udivmoddi4+0x202>
8000302: fab2 f682 clz r6, r2
8000306: 2e00 cmp r6, #0
8000308: f040 80a4 bne.w 8000454 <__udivmoddi4+0x234>
800030c: 1a8a subs r2, r1, r2
800030e: 0c03 lsrs r3, r0, #16
8000310: ea4f 4e17 mov.w lr, r7, lsr #16
8000314: b280 uxth r0, r0
8000316: b2bc uxth r4, r7
8000318: 2101 movs r1, #1
800031a: fbb2 fcfe udiv ip, r2, lr
800031e: fb0e 221c mls r2, lr, ip, r2
8000322: ea43 4302 orr.w r3, r3, r2, lsl #16
8000326: fb04 f20c mul.w r2, r4, ip
800032a: 429a cmp r2, r3
800032c: d907 bls.n 800033e <__udivmoddi4+0x11e>
800032e: 18fb adds r3, r7, r3
8000330: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
8000334: d202 bcs.n 800033c <__udivmoddi4+0x11c>
8000336: 429a cmp r2, r3
8000338: f200 80e0 bhi.w 80004fc <__udivmoddi4+0x2dc>
800033c: 46c4 mov ip, r8
800033e: 1a9b subs r3, r3, r2
8000340: fbb3 f2fe udiv r2, r3, lr
8000344: fb0e 3312 mls r3, lr, r2, r3
8000348: ea40 4303 orr.w r3, r0, r3, lsl #16
800034c: fb02 f404 mul.w r4, r2, r4
8000350: 429c cmp r4, r3
8000352: d907 bls.n 8000364 <__udivmoddi4+0x144>
8000354: 18fb adds r3, r7, r3
8000356: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
800035a: d202 bcs.n 8000362 <__udivmoddi4+0x142>
800035c: 429c cmp r4, r3
800035e: f200 80ca bhi.w 80004f6 <__udivmoddi4+0x2d6>
8000362: 4602 mov r2, r0
8000364: 1b1b subs r3, r3, r4
8000366: ea42 400c orr.w r0, r2, ip, lsl #16
800036a: e7a5 b.n 80002b8 <__udivmoddi4+0x98>
800036c: f1c1 0620 rsb r6, r1, #32
8000370: 408b lsls r3, r1
8000372: fa22 f706 lsr.w r7, r2, r6
8000376: 431f orrs r7, r3
8000378: fa0e f401 lsl.w r4, lr, r1
800037c: fa20 f306 lsr.w r3, r0, r6
8000380: fa2e fe06 lsr.w lr, lr, r6
8000384: ea4f 4917 mov.w r9, r7, lsr #16
8000388: 4323 orrs r3, r4
800038a: fa00 f801 lsl.w r8, r0, r1
800038e: fa1f fc87 uxth.w ip, r7
8000392: fbbe f0f9 udiv r0, lr, r9
8000396: 0c1c lsrs r4, r3, #16
8000398: fb09 ee10 mls lr, r9, r0, lr
800039c: ea44 440e orr.w r4, r4, lr, lsl #16
80003a0: fb00 fe0c mul.w lr, r0, ip
80003a4: 45a6 cmp lr, r4
80003a6: fa02 f201 lsl.w r2, r2, r1
80003aa: d909 bls.n 80003c0 <__udivmoddi4+0x1a0>
80003ac: 193c adds r4, r7, r4
80003ae: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
80003b2: f080 809c bcs.w 80004ee <__udivmoddi4+0x2ce>
80003b6: 45a6 cmp lr, r4
80003b8: f240 8099 bls.w 80004ee <__udivmoddi4+0x2ce>
80003bc: 3802 subs r0, #2
80003be: 443c add r4, r7
80003c0: eba4 040e sub.w r4, r4, lr
80003c4: fa1f fe83 uxth.w lr, r3
80003c8: fbb4 f3f9 udiv r3, r4, r9
80003cc: fb09 4413 mls r4, r9, r3, r4
80003d0: ea4e 4404 orr.w r4, lr, r4, lsl #16
80003d4: fb03 fc0c mul.w ip, r3, ip
80003d8: 45a4 cmp ip, r4
80003da: d908 bls.n 80003ee <__udivmoddi4+0x1ce>
80003dc: 193c adds r4, r7, r4
80003de: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
80003e2: f080 8082 bcs.w 80004ea <__udivmoddi4+0x2ca>
80003e6: 45a4 cmp ip, r4
80003e8: d97f bls.n 80004ea <__udivmoddi4+0x2ca>
80003ea: 3b02 subs r3, #2
80003ec: 443c add r4, r7
80003ee: ea43 4000 orr.w r0, r3, r0, lsl #16
80003f2: eba4 040c sub.w r4, r4, ip
80003f6: fba0 ec02 umull lr, ip, r0, r2
80003fa: 4564 cmp r4, ip
80003fc: 4673 mov r3, lr
80003fe: 46e1 mov r9, ip
8000400: d362 bcc.n 80004c8 <__udivmoddi4+0x2a8>
8000402: d05f beq.n 80004c4 <__udivmoddi4+0x2a4>
8000404: b15d cbz r5, 800041e <__udivmoddi4+0x1fe>
8000406: ebb8 0203 subs.w r2, r8, r3
800040a: eb64 0409 sbc.w r4, r4, r9
800040e: fa04 f606 lsl.w r6, r4, r6
8000412: fa22 f301 lsr.w r3, r2, r1
8000416: 431e orrs r6, r3
8000418: 40cc lsrs r4, r1
800041a: e9c5 6400 strd r6, r4, [r5]
800041e: 2100 movs r1, #0
8000420: e74f b.n 80002c2 <__udivmoddi4+0xa2>
8000422: fbb1 fcf2 udiv ip, r1, r2
8000426: 0c01 lsrs r1, r0, #16
8000428: ea41 410e orr.w r1, r1, lr, lsl #16
800042c: b280 uxth r0, r0
800042e: ea40 4201 orr.w r2, r0, r1, lsl #16
8000432: 463b mov r3, r7
8000434: 4638 mov r0, r7
8000436: 463c mov r4, r7
8000438: 46b8 mov r8, r7
800043a: 46be mov lr, r7
800043c: 2620 movs r6, #32
800043e: fbb1 f1f7 udiv r1, r1, r7
8000442: eba2 0208 sub.w r2, r2, r8
8000446: ea41 410c orr.w r1, r1, ip, lsl #16
800044a: e766 b.n 800031a <__udivmoddi4+0xfa>
800044c: 4601 mov r1, r0
800044e: e718 b.n 8000282 <__udivmoddi4+0x62>
8000450: 4610 mov r0, r2
8000452: e72c b.n 80002ae <__udivmoddi4+0x8e>
8000454: f1c6 0220 rsb r2, r6, #32
8000458: fa2e f302 lsr.w r3, lr, r2
800045c: 40b7 lsls r7, r6
800045e: 40b1 lsls r1, r6
8000460: fa20 f202 lsr.w r2, r0, r2
8000464: ea4f 4e17 mov.w lr, r7, lsr #16
8000468: 430a orrs r2, r1
800046a: fbb3 f8fe udiv r8, r3, lr
800046e: b2bc uxth r4, r7
8000470: fb0e 3318 mls r3, lr, r8, r3
8000474: 0c11 lsrs r1, r2, #16
8000476: ea41 4103 orr.w r1, r1, r3, lsl #16
800047a: fb08 f904 mul.w r9, r8, r4
800047e: 40b0 lsls r0, r6
8000480: 4589 cmp r9, r1
8000482: ea4f 4310 mov.w r3, r0, lsr #16
8000486: b280 uxth r0, r0
8000488: d93e bls.n 8000508 <__udivmoddi4+0x2e8>
800048a: 1879 adds r1, r7, r1
800048c: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
8000490: d201 bcs.n 8000496 <__udivmoddi4+0x276>
8000492: 4589 cmp r9, r1
8000494: d81f bhi.n 80004d6 <__udivmoddi4+0x2b6>
8000496: eba1 0109 sub.w r1, r1, r9
800049a: fbb1 f9fe udiv r9, r1, lr
800049e: fb09 f804 mul.w r8, r9, r4
80004a2: fb0e 1119 mls r1, lr, r9, r1
80004a6: b292 uxth r2, r2
80004a8: ea42 4201 orr.w r2, r2, r1, lsl #16
80004ac: 4542 cmp r2, r8
80004ae: d229 bcs.n 8000504 <__udivmoddi4+0x2e4>
80004b0: 18ba adds r2, r7, r2
80004b2: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
80004b6: d2c4 bcs.n 8000442 <__udivmoddi4+0x222>
80004b8: 4542 cmp r2, r8
80004ba: d2c2 bcs.n 8000442 <__udivmoddi4+0x222>
80004bc: f1a9 0102 sub.w r1, r9, #2
80004c0: 443a add r2, r7
80004c2: e7be b.n 8000442 <__udivmoddi4+0x222>
80004c4: 45f0 cmp r8, lr
80004c6: d29d bcs.n 8000404 <__udivmoddi4+0x1e4>
80004c8: ebbe 0302 subs.w r3, lr, r2
80004cc: eb6c 0c07 sbc.w ip, ip, r7
80004d0: 3801 subs r0, #1
80004d2: 46e1 mov r9, ip
80004d4: e796 b.n 8000404 <__udivmoddi4+0x1e4>
80004d6: eba7 0909 sub.w r9, r7, r9
80004da: 4449 add r1, r9
80004dc: f1a8 0c02 sub.w ip, r8, #2
80004e0: fbb1 f9fe udiv r9, r1, lr
80004e4: fb09 f804 mul.w r8, r9, r4
80004e8: e7db b.n 80004a2 <__udivmoddi4+0x282>
80004ea: 4673 mov r3, lr
80004ec: e77f b.n 80003ee <__udivmoddi4+0x1ce>
80004ee: 4650 mov r0, sl
80004f0: e766 b.n 80003c0 <__udivmoddi4+0x1a0>
80004f2: 4608 mov r0, r1
80004f4: e6fd b.n 80002f2 <__udivmoddi4+0xd2>
80004f6: 443b add r3, r7
80004f8: 3a02 subs r2, #2
80004fa: e733 b.n 8000364 <__udivmoddi4+0x144>
80004fc: f1ac 0c02 sub.w ip, ip, #2
8000500: 443b add r3, r7
8000502: e71c b.n 800033e <__udivmoddi4+0x11e>
8000504: 4649 mov r1, r9
8000506: e79c b.n 8000442 <__udivmoddi4+0x222>
8000508: eba1 0109 sub.w r1, r1, r9
800050c: 46c4 mov ip, r8
800050e: fbb1 f9fe udiv r9, r1, lr
8000512: fb09 f804 mul.w r8, r9, r4
8000516: e7c4 b.n 80004a2 <__udivmoddi4+0x282>
08000518 <__aeabi_idiv0>:
8000518: 4770 bx lr
800051a: bf00 nop
0800051c <breadboard>:
#define G_Prt GreenLight_GPIO_Port
// HAL_GPIO_WritePin(LED_EXT_GPIO_Port, LED_EXT_Pin, GPIO_PIN_RESET);
void
breadboard(int traffSPD)
{
800051c: b580 push {r7, lr}
800051e: b082 sub sp, #8
8000520: af00 add r7, sp, #0
8000522: 6078 str r0, [r7, #4]
HAL_GPIO_WritePin(YellowLight_GPIO_Port, GreenLight_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GreenLight_GPIO_Port, GreenLight_Pin, GPIO_PIN_SET);
HAL_Delay(traffSPD);
*/
HAL_GPIO_TogglePin(R_Prt, R_Pin);
8000524: 2104 movs r1, #4
8000526: 4813 ldr r0, [pc, #76] @ (8000574 <breadboard+0x58>)
8000528: f001 fd69 bl 8001ffe <HAL_GPIO_TogglePin>
HAL_Delay(traffSPD);
800052c: 687b ldr r3, [r7, #4]
800052e: 4618 mov r0, r3
8000530: f001 f892 bl 8001658 <HAL_Delay>
HAL_GPIO_TogglePin(R_Prt, R_Pin);
8000534: 2104 movs r1, #4
8000536: 480f ldr r0, [pc, #60] @ (8000574 <breadboard+0x58>)
8000538: f001 fd61 bl 8001ffe <HAL_GPIO_TogglePin>
HAL_GPIO_TogglePin(Y_Prt, Y_Pin);
800053c: 2108 movs r1, #8
800053e: 480d ldr r0, [pc, #52] @ (8000574 <breadboard+0x58>)
8000540: f001 fd5d bl 8001ffe <HAL_GPIO_TogglePin>
HAL_Delay(traffSPD);
8000544: 687b ldr r3, [r7, #4]
8000546: 4618 mov r0, r3
8000548: f001 f886 bl 8001658 <HAL_Delay>
HAL_GPIO_TogglePin(Y_Prt, Y_Pin);
800054c: 2108 movs r1, #8
800054e: 4809 ldr r0, [pc, #36] @ (8000574 <breadboard+0x58>)
8000550: f001 fd55 bl 8001ffe <HAL_GPIO_TogglePin>
HAL_GPIO_TogglePin(G_Prt, G_Pin);
8000554: 2110 movs r1, #16
8000556: 4807 ldr r0, [pc, #28] @ (8000574 <breadboard+0x58>)
8000558: f001 fd51 bl 8001ffe <HAL_GPIO_TogglePin>
HAL_Delay(traffSPD);
800055c: 687b ldr r3, [r7, #4]
800055e: 4618 mov r0, r3
8000560: f001 f87a bl 8001658 <HAL_Delay>
HAL_GPIO_TogglePin(G_Prt, G_Pin);
8000564: 2110 movs r1, #16
8000566: 4803 ldr r0, [pc, #12] @ (8000574 <breadboard+0x58>)
8000568: f001 fd49 bl 8001ffe <HAL_GPIO_TogglePin>
// Walk signal
// Light dimmer
}
800056c: bf00 nop
800056e: 3708 adds r7, #8
8000570: 46bd mov sp, r7
8000572: bd80 pop {r7, pc}
8000574: 40021000 .word 0x40021000
08000578 <vApplicationStackOverflowHook>:
}
/* USER CODE END 2 */
/* USER CODE BEGIN 4 */
__weak void vApplicationStackOverflowHook(xTaskHandle xTask, signed char *pcTaskName)
{
8000578: b480 push {r7}
800057a: b083 sub sp, #12
800057c: af00 add r7, sp, #0
800057e: 6078 str r0, [r7, #4]
8000580: 6039 str r1, [r7, #0]
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook function is
called if a stack overflow is detected. */
}
8000582: bf00 nop
8000584: 370c adds r7, #12
8000586: 46bd mov sp, r7
8000588: f85d 7b04 ldr.w r7, [sp], #4
800058c: 4770 bx lr
0800058e <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800058e: b580 push {r7, lr}
8000590: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000592: f001 f81f bl 80015d4 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000596: f000 f817 bl 80005c8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
800059a: f000 fa85 bl 8000aa8 <MX_GPIO_Init>
MX_CRC_Init();
800059e: f000 f87d bl 800069c <MX_CRC_Init>
MX_DMA2D_Init();
80005a2: f000 f88f bl 80006c4 <MX_DMA2D_Init>
MX_FMC_Init();
80005a6: f000 fa2f bl 8000a08 <MX_FMC_Init>
MX_I2C3_Init();
80005aa: f000 f8bd bl 8000728 <MX_I2C3_Init>
MX_LTDC_Init();
80005ae: f000 f8fb bl 80007a8 <MX_LTDC_Init>
MX_SPI5_Init();
80005b2: f000 f979 bl 80008a8 <MX_SPI5_Init>
MX_TIM1_Init();
80005b6: f000 f9ad bl 8000914 <MX_TIM1_Init>
MX_USART1_UART_Init();
80005ba: f000 f9fb bl 80009b4 <MX_USART1_UART_Init>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
breadboard(333);
80005be: f240 104d movw r0, #333 @ 0x14d
80005c2: f7ff ffab bl 800051c <breadboard>
80005c6: e7fa b.n 80005be <main+0x30>
080005c8 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80005c8: b580 push {r7, lr}
80005ca: b094 sub sp, #80 @ 0x50
80005cc: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80005ce: f107 0320 add.w r3, r7, #32
80005d2: 2230 movs r2, #48 @ 0x30
80005d4: 2100 movs r1, #0
80005d6: 4618 mov r0, r3
80005d8: f007 fc5a bl 8007e90 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80005dc: f107 030c add.w r3, r7, #12
80005e0: 2200 movs r2, #0
80005e2: 601a str r2, [r3, #0]
80005e4: 605a str r2, [r3, #4]
80005e6: 609a str r2, [r3, #8]
80005e8: 60da str r2, [r3, #12]
80005ea: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80005ec: 2300 movs r3, #0
80005ee: 60bb str r3, [r7, #8]
80005f0: 4b28 ldr r3, [pc, #160] @ (8000694 <SystemClock_Config+0xcc>)
80005f2: 6c1b ldr r3, [r3, #64] @ 0x40
80005f4: 4a27 ldr r2, [pc, #156] @ (8000694 <SystemClock_Config+0xcc>)
80005f6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80005fa: 6413 str r3, [r2, #64] @ 0x40
80005fc: 4b25 ldr r3, [pc, #148] @ (8000694 <SystemClock_Config+0xcc>)
80005fe: 6c1b ldr r3, [r3, #64] @ 0x40
8000600: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000604: 60bb str r3, [r7, #8]
8000606: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
8000608: 2300 movs r3, #0
800060a: 607b str r3, [r7, #4]
800060c: 4b22 ldr r3, [pc, #136] @ (8000698 <SystemClock_Config+0xd0>)
800060e: 681b ldr r3, [r3, #0]
8000610: f423 4340 bic.w r3, r3, #49152 @ 0xc000
8000614: 4a20 ldr r2, [pc, #128] @ (8000698 <SystemClock_Config+0xd0>)
8000616: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800061a: 6013 str r3, [r2, #0]
800061c: 4b1e ldr r3, [pc, #120] @ (8000698 <SystemClock_Config+0xd0>)
800061e: 681b ldr r3, [r3, #0]
8000620: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000624: 607b str r3, [r7, #4]
8000626: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
8000628: 2301 movs r3, #1
800062a: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
800062c: f44f 3380 mov.w r3, #65536 @ 0x10000
8000630: 627b str r3, [r7, #36] @ 0x24
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000632: 2302 movs r3, #2
8000634: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
8000636: f44f 0380 mov.w r3, #4194304 @ 0x400000
800063a: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLM = 4;
800063c: 2304 movs r3, #4
800063e: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLN = 72;
8000640: 2348 movs r3, #72 @ 0x48
8000642: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
8000644: 2302 movs r3, #2
8000646: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLQ = 3;
8000648: 2303 movs r3, #3
800064a: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800064c: f107 0320 add.w r3, r7, #32
8000650: 4618 mov r0, r3
8000652: f003 ff65 bl 8004520 <HAL_RCC_OscConfig>
8000656: 4603 mov r3, r0
8000658: 2b00 cmp r3, #0
800065a: d001 beq.n 8000660 <SystemClock_Config+0x98>
{
Error_Handler();
800065c: f000 fb5a bl 8000d14 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8000660: 230f movs r3, #15
8000662: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000664: 2302 movs r3, #2
8000666: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000668: 2300 movs r3, #0
800066a: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800066c: f44f 5380 mov.w r3, #4096 @ 0x1000
8000670: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000672: 2300 movs r3, #0
8000674: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8000676: f107 030c add.w r3, r7, #12
800067a: 2102 movs r1, #2
800067c: 4618 mov r0, r3
800067e: f004 f9c7 bl 8004a10 <HAL_RCC_ClockConfig>
8000682: 4603 mov r3, r0
8000684: 2b00 cmp r3, #0
8000686: d001 beq.n 800068c <SystemClock_Config+0xc4>
{
Error_Handler();
8000688: f000 fb44 bl 8000d14 <Error_Handler>
}
}
800068c: bf00 nop
800068e: 3750 adds r7, #80 @ 0x50
8000690: 46bd mov sp, r7
8000692: bd80 pop {r7, pc}
8000694: 40023800 .word 0x40023800
8000698: 40007000 .word 0x40007000
0800069c <MX_CRC_Init>:
* @brief CRC Initialization Function
* @param None
* @retval None
*/
static void MX_CRC_Init(void)
{
800069c: b580 push {r7, lr}
800069e: af00 add r7, sp, #0
/* USER CODE END CRC_Init 0 */
/* USER CODE BEGIN CRC_Init 1 */
/* USER CODE END CRC_Init 1 */
hcrc.Instance = CRC;
80006a0: 4b06 ldr r3, [pc, #24] @ (80006bc <MX_CRC_Init+0x20>)
80006a2: 4a07 ldr r2, [pc, #28] @ (80006c0 <MX_CRC_Init+0x24>)
80006a4: 601a str r2, [r3, #0]
if (HAL_CRC_Init(&hcrc) != HAL_OK)
80006a6: 4805 ldr r0, [pc, #20] @ (80006bc <MX_CRC_Init+0x20>)
80006a8: f001 f8dc bl 8001864 <HAL_CRC_Init>
80006ac: 4603 mov r3, r0
80006ae: 2b00 cmp r3, #0
80006b0: d001 beq.n 80006b6 <MX_CRC_Init+0x1a>
{
Error_Handler();
80006b2: f000 fb2f bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN CRC_Init 2 */
/* USER CODE END CRC_Init 2 */
}
80006b6: bf00 nop
80006b8: bd80 pop {r7, pc}
80006ba: bf00 nop
80006bc: 2000002c .word 0x2000002c
80006c0: 40023000 .word 0x40023000
080006c4 <MX_DMA2D_Init>:
* @brief DMA2D Initialization Function
* @param None
* @retval None
*/
static void MX_DMA2D_Init(void)
{
80006c4: b580 push {r7, lr}
80006c6: af00 add r7, sp, #0
/* USER CODE END DMA2D_Init 0 */
/* USER CODE BEGIN DMA2D_Init 1 */
/* USER CODE END DMA2D_Init 1 */
hdma2d.Instance = DMA2D;
80006c8: 4b15 ldr r3, [pc, #84] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006ca: 4a16 ldr r2, [pc, #88] @ (8000724 <MX_DMA2D_Init+0x60>)
80006cc: 601a str r2, [r3, #0]
hdma2d.Init.Mode = DMA2D_M2M;
80006ce: 4b14 ldr r3, [pc, #80] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006d0: 2200 movs r2, #0
80006d2: 605a str r2, [r3, #4]
hdma2d.Init.ColorMode = DMA2D_OUTPUT_ARGB8888;
80006d4: 4b12 ldr r3, [pc, #72] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006d6: 2200 movs r2, #0
80006d8: 609a str r2, [r3, #8]
hdma2d.Init.OutputOffset = 0;
80006da: 4b11 ldr r3, [pc, #68] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006dc: 2200 movs r2, #0
80006de: 60da str r2, [r3, #12]
hdma2d.LayerCfg[1].InputOffset = 0;
80006e0: 4b0f ldr r3, [pc, #60] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006e2: 2200 movs r2, #0
80006e4: 629a str r2, [r3, #40] @ 0x28
hdma2d.LayerCfg[1].InputColorMode = DMA2D_INPUT_ARGB8888;
80006e6: 4b0e ldr r3, [pc, #56] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006e8: 2200 movs r2, #0
80006ea: 62da str r2, [r3, #44] @ 0x2c
hdma2d.LayerCfg[1].AlphaMode = DMA2D_NO_MODIF_ALPHA;
80006ec: 4b0c ldr r3, [pc, #48] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006ee: 2200 movs r2, #0
80006f0: 631a str r2, [r3, #48] @ 0x30
hdma2d.LayerCfg[1].InputAlpha = 0;
80006f2: 4b0b ldr r3, [pc, #44] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006f4: 2200 movs r2, #0
80006f6: 635a str r2, [r3, #52] @ 0x34
if (HAL_DMA2D_Init(&hdma2d) != HAL_OK)
80006f8: 4809 ldr r0, [pc, #36] @ (8000720 <MX_DMA2D_Init+0x5c>)
80006fa: f001 f8cf bl 800189c <HAL_DMA2D_Init>
80006fe: 4603 mov r3, r0
8000700: 2b00 cmp r3, #0
8000702: d001 beq.n 8000708 <MX_DMA2D_Init+0x44>
{
Error_Handler();
8000704: f000 fb06 bl 8000d14 <Error_Handler>
}
if (HAL_DMA2D_ConfigLayer(&hdma2d, 1) != HAL_OK)
8000708: 2101 movs r1, #1
800070a: 4805 ldr r0, [pc, #20] @ (8000720 <MX_DMA2D_Init+0x5c>)
800070c: f001 fa20 bl 8001b50 <HAL_DMA2D_ConfigLayer>
8000710: 4603 mov r3, r0
8000712: 2b00 cmp r3, #0
8000714: d001 beq.n 800071a <MX_DMA2D_Init+0x56>
{
Error_Handler();
8000716: f000 fafd bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN DMA2D_Init 2 */
/* USER CODE END DMA2D_Init 2 */
}
800071a: bf00 nop
800071c: bd80 pop {r7, pc}
800071e: bf00 nop
8000720: 20000034 .word 0x20000034
8000724: 4002b000 .word 0x4002b000
08000728 <MX_I2C3_Init>:
* @brief I2C3 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C3_Init(void)
{
8000728: b580 push {r7, lr}
800072a: af00 add r7, sp, #0
/* USER CODE END I2C3_Init 0 */
/* USER CODE BEGIN I2C3_Init 1 */
/* USER CODE END I2C3_Init 1 */
hi2c3.Instance = I2C3;
800072c: 4b1b ldr r3, [pc, #108] @ (800079c <MX_I2C3_Init+0x74>)
800072e: 4a1c ldr r2, [pc, #112] @ (80007a0 <MX_I2C3_Init+0x78>)
8000730: 601a str r2, [r3, #0]
hi2c3.Init.ClockSpeed = 100000;
8000732: 4b1a ldr r3, [pc, #104] @ (800079c <MX_I2C3_Init+0x74>)
8000734: 4a1b ldr r2, [pc, #108] @ (80007a4 <MX_I2C3_Init+0x7c>)
8000736: 605a str r2, [r3, #4]
hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2;
8000738: 4b18 ldr r3, [pc, #96] @ (800079c <MX_I2C3_Init+0x74>)
800073a: 2200 movs r2, #0
800073c: 609a str r2, [r3, #8]
hi2c3.Init.OwnAddress1 = 0;
800073e: 4b17 ldr r3, [pc, #92] @ (800079c <MX_I2C3_Init+0x74>)
8000740: 2200 movs r2, #0
8000742: 60da str r2, [r3, #12]
hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8000744: 4b15 ldr r3, [pc, #84] @ (800079c <MX_I2C3_Init+0x74>)
8000746: f44f 4280 mov.w r2, #16384 @ 0x4000
800074a: 611a str r2, [r3, #16]
hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
800074c: 4b13 ldr r3, [pc, #76] @ (800079c <MX_I2C3_Init+0x74>)
800074e: 2200 movs r2, #0
8000750: 615a str r2, [r3, #20]
hi2c3.Init.OwnAddress2 = 0;
8000752: 4b12 ldr r3, [pc, #72] @ (800079c <MX_I2C3_Init+0x74>)
8000754: 2200 movs r2, #0
8000756: 619a str r2, [r3, #24]
hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
8000758: 4b10 ldr r3, [pc, #64] @ (800079c <MX_I2C3_Init+0x74>)
800075a: 2200 movs r2, #0
800075c: 61da str r2, [r3, #28]
hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
800075e: 4b0f ldr r3, [pc, #60] @ (800079c <MX_I2C3_Init+0x74>)
8000760: 2200 movs r2, #0
8000762: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c3) != HAL_OK)
8000764: 480d ldr r0, [pc, #52] @ (800079c <MX_I2C3_Init+0x74>)
8000766: f003 fa0b bl 8003b80 <HAL_I2C_Init>
800076a: 4603 mov r3, r0
800076c: 2b00 cmp r3, #0
800076e: d001 beq.n 8000774 <MX_I2C3_Init+0x4c>
{
Error_Handler();
8000770: f000 fad0 bl 8000d14 <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c3, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
8000774: 2100 movs r1, #0
8000776: 4809 ldr r0, [pc, #36] @ (800079c <MX_I2C3_Init+0x74>)
8000778: f003 fb46 bl 8003e08 <HAL_I2CEx_ConfigAnalogFilter>
800077c: 4603 mov r3, r0
800077e: 2b00 cmp r3, #0
8000780: d001 beq.n 8000786 <MX_I2C3_Init+0x5e>
{
Error_Handler();
8000782: f000 fac7 bl 8000d14 <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c3, 0) != HAL_OK)
8000786: 2100 movs r1, #0
8000788: 4804 ldr r0, [pc, #16] @ (800079c <MX_I2C3_Init+0x74>)
800078a: f003 fb79 bl 8003e80 <HAL_I2CEx_ConfigDigitalFilter>
800078e: 4603 mov r3, r0
8000790: 2b00 cmp r3, #0
8000792: d001 beq.n 8000798 <MX_I2C3_Init+0x70>
{
Error_Handler();
8000794: f000 fabe bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN I2C3_Init 2 */
/* USER CODE END I2C3_Init 2 */
}
8000798: bf00 nop
800079a: bd80 pop {r7, pc}
800079c: 20000074 .word 0x20000074
80007a0: 40005c00 .word 0x40005c00
80007a4: 000186a0 .word 0x000186a0
080007a8 <MX_LTDC_Init>:
* @brief LTDC Initialization Function
* @param None
* @retval None
*/
static void MX_LTDC_Init(void)
{
80007a8: b580 push {r7, lr}
80007aa: b08e sub sp, #56 @ 0x38
80007ac: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_Init 0 */
/* USER CODE END LTDC_Init 0 */
LTDC_LayerCfgTypeDef pLayerCfg = {0};
80007ae: 1d3b adds r3, r7, #4
80007b0: 2234 movs r2, #52 @ 0x34
80007b2: 2100 movs r1, #0
80007b4: 4618 mov r0, r3
80007b6: f007 fb6b bl 8007e90 <memset>
/* USER CODE BEGIN LTDC_Init 1 */
/* USER CODE END LTDC_Init 1 */
hltdc.Instance = LTDC;
80007ba: 4b39 ldr r3, [pc, #228] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007bc: 4a39 ldr r2, [pc, #228] @ (80008a4 <MX_LTDC_Init+0xfc>)
80007be: 601a str r2, [r3, #0]
hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
80007c0: 4b37 ldr r3, [pc, #220] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007c2: 2200 movs r2, #0
80007c4: 605a str r2, [r3, #4]
hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
80007c6: 4b36 ldr r3, [pc, #216] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007c8: 2200 movs r2, #0
80007ca: 609a str r2, [r3, #8]
hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
80007cc: 4b34 ldr r3, [pc, #208] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007ce: 2200 movs r2, #0
80007d0: 60da str r2, [r3, #12]
hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
80007d2: 4b33 ldr r3, [pc, #204] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007d4: 2200 movs r2, #0
80007d6: 611a str r2, [r3, #16]
hltdc.Init.HorizontalSync = 9;
80007d8: 4b31 ldr r3, [pc, #196] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007da: 2209 movs r2, #9
80007dc: 615a str r2, [r3, #20]
hltdc.Init.VerticalSync = 1;
80007de: 4b30 ldr r3, [pc, #192] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007e0: 2201 movs r2, #1
80007e2: 619a str r2, [r3, #24]
hltdc.Init.AccumulatedHBP = 29;
80007e4: 4b2e ldr r3, [pc, #184] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007e6: 221d movs r2, #29
80007e8: 61da str r2, [r3, #28]
hltdc.Init.AccumulatedVBP = 3;
80007ea: 4b2d ldr r3, [pc, #180] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007ec: 2203 movs r2, #3
80007ee: 621a str r2, [r3, #32]
hltdc.Init.AccumulatedActiveW = 269;
80007f0: 4b2b ldr r3, [pc, #172] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007f2: f240 120d movw r2, #269 @ 0x10d
80007f6: 625a str r2, [r3, #36] @ 0x24
hltdc.Init.AccumulatedActiveH = 323;
80007f8: 4b29 ldr r3, [pc, #164] @ (80008a0 <MX_LTDC_Init+0xf8>)
80007fa: f240 1243 movw r2, #323 @ 0x143
80007fe: 629a str r2, [r3, #40] @ 0x28
hltdc.Init.TotalWidth = 279;
8000800: 4b27 ldr r3, [pc, #156] @ (80008a0 <MX_LTDC_Init+0xf8>)
8000802: f240 1217 movw r2, #279 @ 0x117
8000806: 62da str r2, [r3, #44] @ 0x2c
hltdc.Init.TotalHeigh = 327;
8000808: 4b25 ldr r3, [pc, #148] @ (80008a0 <MX_LTDC_Init+0xf8>)
800080a: f240 1247 movw r2, #327 @ 0x147
800080e: 631a str r2, [r3, #48] @ 0x30
hltdc.Init.Backcolor.Blue = 0;
8000810: 4b23 ldr r3, [pc, #140] @ (80008a0 <MX_LTDC_Init+0xf8>)
8000812: 2200 movs r2, #0
8000814: f883 2034 strb.w r2, [r3, #52] @ 0x34
hltdc.Init.Backcolor.Green = 0;
8000818: 4b21 ldr r3, [pc, #132] @ (80008a0 <MX_LTDC_Init+0xf8>)
800081a: 2200 movs r2, #0
800081c: f883 2035 strb.w r2, [r3, #53] @ 0x35
hltdc.Init.Backcolor.Red = 0;
8000820: 4b1f ldr r3, [pc, #124] @ (80008a0 <MX_LTDC_Init+0xf8>)
8000822: 2200 movs r2, #0
8000824: f883 2036 strb.w r2, [r3, #54] @ 0x36
if (HAL_LTDC_Init(&hltdc) != HAL_OK)
8000828: 481d ldr r0, [pc, #116] @ (80008a0 <MX_LTDC_Init+0xf8>)
800082a: f003 fb68 bl 8003efe <HAL_LTDC_Init>
800082e: 4603 mov r3, r0
8000830: 2b00 cmp r3, #0
8000832: d001 beq.n 8000838 <MX_LTDC_Init+0x90>
{
Error_Handler();
8000834: f000 fa6e bl 8000d14 <Error_Handler>
}
pLayerCfg.WindowX0 = 0;
8000838: 2300 movs r3, #0
800083a: 607b str r3, [r7, #4]
pLayerCfg.WindowX1 = 240;
800083c: 23f0 movs r3, #240 @ 0xf0
800083e: 60bb str r3, [r7, #8]
pLayerCfg.WindowY0 = 0;
8000840: 2300 movs r3, #0
8000842: 60fb str r3, [r7, #12]
pLayerCfg.WindowY1 = 320;
8000844: f44f 73a0 mov.w r3, #320 @ 0x140
8000848: 613b str r3, [r7, #16]
pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB565;
800084a: 2302 movs r3, #2
800084c: 617b str r3, [r7, #20]
pLayerCfg.Alpha = 255;
800084e: 23ff movs r3, #255 @ 0xff
8000850: 61bb str r3, [r7, #24]
pLayerCfg.Alpha0 = 0;
8000852: 2300 movs r3, #0
8000854: 61fb str r3, [r7, #28]
pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA;
8000856: f44f 63c0 mov.w r3, #1536 @ 0x600
800085a: 623b str r3, [r7, #32]
pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA;
800085c: 2307 movs r3, #7
800085e: 627b str r3, [r7, #36] @ 0x24
pLayerCfg.FBStartAdress = 0xD0000000;
8000860: f04f 4350 mov.w r3, #3489660928 @ 0xd0000000
8000864: 62bb str r3, [r7, #40] @ 0x28
pLayerCfg.ImageWidth = 240;
8000866: 23f0 movs r3, #240 @ 0xf0
8000868: 62fb str r3, [r7, #44] @ 0x2c
pLayerCfg.ImageHeight = 320;
800086a: f44f 73a0 mov.w r3, #320 @ 0x140
800086e: 633b str r3, [r7, #48] @ 0x30
pLayerCfg.Backcolor.Blue = 0;
8000870: 2300 movs r3, #0
8000872: f887 3034 strb.w r3, [r7, #52] @ 0x34
pLayerCfg.Backcolor.Green = 0;
8000876: 2300 movs r3, #0
8000878: f887 3035 strb.w r3, [r7, #53] @ 0x35
pLayerCfg.Backcolor.Red = 0;
800087c: 2300 movs r3, #0
800087e: f887 3036 strb.w r3, [r7, #54] @ 0x36
if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
8000882: 1d3b adds r3, r7, #4
8000884: 2200 movs r2, #0
8000886: 4619 mov r1, r3
8000888: 4805 ldr r0, [pc, #20] @ (80008a0 <MX_LTDC_Init+0xf8>)
800088a: f003 fc97 bl 80041bc <HAL_LTDC_ConfigLayer>
800088e: 4603 mov r3, r0
8000890: 2b00 cmp r3, #0
8000892: d001 beq.n 8000898 <MX_LTDC_Init+0xf0>
{
Error_Handler();
8000894: f000 fa3e bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN LTDC_Init 2 */
/* USER CODE END LTDC_Init 2 */
}
8000898: bf00 nop
800089a: 3738 adds r7, #56 @ 0x38
800089c: 46bd mov sp, r7
800089e: bd80 pop {r7, pc}
80008a0: 200000c8 .word 0x200000c8
80008a4: 40016800 .word 0x40016800
080008a8 <MX_SPI5_Init>:
* @brief SPI5 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI5_Init(void)
{
80008a8: b580 push {r7, lr}
80008aa: af00 add r7, sp, #0
/* USER CODE BEGIN SPI5_Init 1 */
/* USER CODE END SPI5_Init 1 */
/* SPI5 parameter configuration*/
hspi5.Instance = SPI5;
80008ac: 4b17 ldr r3, [pc, #92] @ (800090c <MX_SPI5_Init+0x64>)
80008ae: 4a18 ldr r2, [pc, #96] @ (8000910 <MX_SPI5_Init+0x68>)
80008b0: 601a str r2, [r3, #0]
hspi5.Init.Mode = SPI_MODE_MASTER;
80008b2: 4b16 ldr r3, [pc, #88] @ (800090c <MX_SPI5_Init+0x64>)
80008b4: f44f 7282 mov.w r2, #260 @ 0x104
80008b8: 605a str r2, [r3, #4]
hspi5.Init.Direction = SPI_DIRECTION_2LINES;
80008ba: 4b14 ldr r3, [pc, #80] @ (800090c <MX_SPI5_Init+0x64>)
80008bc: 2200 movs r2, #0
80008be: 609a str r2, [r3, #8]
hspi5.Init.DataSize = SPI_DATASIZE_8BIT;
80008c0: 4b12 ldr r3, [pc, #72] @ (800090c <MX_SPI5_Init+0x64>)
80008c2: 2200 movs r2, #0
80008c4: 60da str r2, [r3, #12]
hspi5.Init.CLKPolarity = SPI_POLARITY_LOW;
80008c6: 4b11 ldr r3, [pc, #68] @ (800090c <MX_SPI5_Init+0x64>)
80008c8: 2200 movs r2, #0
80008ca: 611a str r2, [r3, #16]
hspi5.Init.CLKPhase = SPI_PHASE_1EDGE;
80008cc: 4b0f ldr r3, [pc, #60] @ (800090c <MX_SPI5_Init+0x64>)
80008ce: 2200 movs r2, #0
80008d0: 615a str r2, [r3, #20]
hspi5.Init.NSS = SPI_NSS_SOFT;
80008d2: 4b0e ldr r3, [pc, #56] @ (800090c <MX_SPI5_Init+0x64>)
80008d4: f44f 7200 mov.w r2, #512 @ 0x200
80008d8: 619a str r2, [r3, #24]
hspi5.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
80008da: 4b0c ldr r3, [pc, #48] @ (800090c <MX_SPI5_Init+0x64>)
80008dc: 2218 movs r2, #24
80008de: 61da str r2, [r3, #28]
hspi5.Init.FirstBit = SPI_FIRSTBIT_MSB;
80008e0: 4b0a ldr r3, [pc, #40] @ (800090c <MX_SPI5_Init+0x64>)
80008e2: 2200 movs r2, #0
80008e4: 621a str r2, [r3, #32]
hspi5.Init.TIMode = SPI_TIMODE_DISABLE;
80008e6: 4b09 ldr r3, [pc, #36] @ (800090c <MX_SPI5_Init+0x64>)
80008e8: 2200 movs r2, #0
80008ea: 625a str r2, [r3, #36] @ 0x24
hspi5.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80008ec: 4b07 ldr r3, [pc, #28] @ (800090c <MX_SPI5_Init+0x64>)
80008ee: 2200 movs r2, #0
80008f0: 629a str r2, [r3, #40] @ 0x28
hspi5.Init.CRCPolynomial = 10;
80008f2: 4b06 ldr r3, [pc, #24] @ (800090c <MX_SPI5_Init+0x64>)
80008f4: 220a movs r2, #10
80008f6: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi5) != HAL_OK)
80008f8: 4804 ldr r0, [pc, #16] @ (800090c <MX_SPI5_Init+0x64>)
80008fa: f004 fccf bl 800529c <HAL_SPI_Init>
80008fe: 4603 mov r3, r0
8000900: 2b00 cmp r3, #0
8000902: d001 beq.n 8000908 <MX_SPI5_Init+0x60>
{
Error_Handler();
8000904: f000 fa06 bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN SPI5_Init 2 */
/* USER CODE END SPI5_Init 2 */
}
8000908: bf00 nop
800090a: bd80 pop {r7, pc}
800090c: 20000170 .word 0x20000170
8000910: 40015000 .word 0x40015000
08000914 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000914: b580 push {r7, lr}
8000916: b086 sub sp, #24
8000918: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800091a: f107 0308 add.w r3, r7, #8
800091e: 2200 movs r2, #0
8000920: 601a str r2, [r3, #0]
8000922: 605a str r2, [r3, #4]
8000924: 609a str r2, [r3, #8]
8000926: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000928: 463b mov r3, r7
800092a: 2200 movs r2, #0
800092c: 601a str r2, [r3, #0]
800092e: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000930: 4b1e ldr r3, [pc, #120] @ (80009ac <MX_TIM1_Init+0x98>)
8000932: 4a1f ldr r2, [pc, #124] @ (80009b0 <MX_TIM1_Init+0x9c>)
8000934: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
8000936: 4b1d ldr r3, [pc, #116] @ (80009ac <MX_TIM1_Init+0x98>)
8000938: 2200 movs r2, #0
800093a: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
800093c: 4b1b ldr r3, [pc, #108] @ (80009ac <MX_TIM1_Init+0x98>)
800093e: 2200 movs r2, #0
8000940: 609a str r2, [r3, #8]
htim1.Init.Period = 65535;
8000942: 4b1a ldr r3, [pc, #104] @ (80009ac <MX_TIM1_Init+0x98>)
8000944: f64f 72ff movw r2, #65535 @ 0xffff
8000948: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800094a: 4b18 ldr r3, [pc, #96] @ (80009ac <MX_TIM1_Init+0x98>)
800094c: 2200 movs r2, #0
800094e: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000950: 4b16 ldr r3, [pc, #88] @ (80009ac <MX_TIM1_Init+0x98>)
8000952: 2200 movs r2, #0
8000954: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000956: 4b15 ldr r3, [pc, #84] @ (80009ac <MX_TIM1_Init+0x98>)
8000958: 2200 movs r2, #0
800095a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
800095c: 4813 ldr r0, [pc, #76] @ (80009ac <MX_TIM1_Init+0x98>)
800095e: f004 fd26 bl 80053ae <HAL_TIM_Base_Init>
8000962: 4603 mov r3, r0
8000964: 2b00 cmp r3, #0
8000966: d001 beq.n 800096c <MX_TIM1_Init+0x58>
{
Error_Handler();
8000968: f000 f9d4 bl 8000d14 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
800096c: f44f 5380 mov.w r3, #4096 @ 0x1000
8000970: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8000972: f107 0308 add.w r3, r7, #8
8000976: 4619 mov r1, r3
8000978: 480c ldr r0, [pc, #48] @ (80009ac <MX_TIM1_Init+0x98>)
800097a: f004 fec7 bl 800570c <HAL_TIM_ConfigClockSource>
800097e: 4603 mov r3, r0
8000980: 2b00 cmp r3, #0
8000982: d001 beq.n 8000988 <MX_TIM1_Init+0x74>
{
Error_Handler();
8000984: f000 f9c6 bl 8000d14 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000988: 2300 movs r3, #0
800098a: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
800098c: 2300 movs r3, #0
800098e: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000990: 463b mov r3, r7
8000992: 4619 mov r1, r3
8000994: 4805 ldr r0, [pc, #20] @ (80009ac <MX_TIM1_Init+0x98>)
8000996: f005 f8e9 bl 8005b6c <HAL_TIMEx_MasterConfigSynchronization>
800099a: 4603 mov r3, r0
800099c: 2b00 cmp r3, #0
800099e: d001 beq.n 80009a4 <MX_TIM1_Init+0x90>
{
Error_Handler();
80009a0: f000 f9b8 bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
80009a4: bf00 nop
80009a6: 3718 adds r7, #24
80009a8: 46bd mov sp, r7
80009aa: bd80 pop {r7, pc}
80009ac: 200001c8 .word 0x200001c8
80009b0: 40010000 .word 0x40010000
080009b4 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
80009b4: b580 push {r7, lr}
80009b6: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
80009b8: 4b11 ldr r3, [pc, #68] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009ba: 4a12 ldr r2, [pc, #72] @ (8000a04 <MX_USART1_UART_Init+0x50>)
80009bc: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80009be: 4b10 ldr r3, [pc, #64] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009c0: f44f 32e1 mov.w r2, #115200 @ 0x1c200
80009c4: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
80009c6: 4b0e ldr r3, [pc, #56] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009c8: 2200 movs r2, #0
80009ca: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
80009cc: 4b0c ldr r3, [pc, #48] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009ce: 2200 movs r2, #0
80009d0: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
80009d2: 4b0b ldr r3, [pc, #44] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009d4: 2200 movs r2, #0
80009d6: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
80009d8: 4b09 ldr r3, [pc, #36] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009da: 220c movs r2, #12
80009dc: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80009de: 4b08 ldr r3, [pc, #32] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009e0: 2200 movs r2, #0
80009e2: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80009e4: 4b06 ldr r3, [pc, #24] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009e6: 2200 movs r2, #0
80009e8: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
80009ea: 4805 ldr r0, [pc, #20] @ (8000a00 <MX_USART1_UART_Init+0x4c>)
80009ec: f005 f94e bl 8005c8c <HAL_UART_Init>
80009f0: 4603 mov r3, r0
80009f2: 2b00 cmp r3, #0
80009f4: d001 beq.n 80009fa <MX_USART1_UART_Init+0x46>
{
Error_Handler();
80009f6: f000 f98d bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
80009fa: bf00 nop
80009fc: bd80 pop {r7, pc}
80009fe: bf00 nop
8000a00: 20000210 .word 0x20000210
8000a04: 40011000 .word 0x40011000
08000a08 <MX_FMC_Init>:
/* FMC initialization function */
static void MX_FMC_Init(void)
{
8000a08: b580 push {r7, lr}
8000a0a: b088 sub sp, #32
8000a0c: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
8000a0e: 1d3b adds r3, r7, #4
8000a10: 2200 movs r2, #0
8000a12: 601a str r2, [r3, #0]
8000a14: 605a str r2, [r3, #4]
8000a16: 609a str r2, [r3, #8]
8000a18: 60da str r2, [r3, #12]
8000a1a: 611a str r2, [r3, #16]
8000a1c: 615a str r2, [r3, #20]
8000a1e: 619a str r2, [r3, #24]
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
8000a20: 4b1f ldr r3, [pc, #124] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a22: 4a20 ldr r2, [pc, #128] @ (8000aa4 <MX_FMC_Init+0x9c>)
8000a24: 601a str r2, [r3, #0]
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK2;
8000a26: 4b1e ldr r3, [pc, #120] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a28: 2201 movs r2, #1
8000a2a: 605a str r2, [r3, #4]
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
8000a2c: 4b1c ldr r3, [pc, #112] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a2e: 2200 movs r2, #0
8000a30: 609a str r2, [r3, #8]
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
8000a32: 4b1b ldr r3, [pc, #108] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a34: 2204 movs r2, #4
8000a36: 60da str r2, [r3, #12]
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
8000a38: 4b19 ldr r3, [pc, #100] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a3a: 2210 movs r2, #16
8000a3c: 611a str r2, [r3, #16]
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
8000a3e: 4b18 ldr r3, [pc, #96] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a40: 2240 movs r2, #64 @ 0x40
8000a42: 615a str r2, [r3, #20]
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
8000a44: 4b16 ldr r3, [pc, #88] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a46: f44f 72c0 mov.w r2, #384 @ 0x180
8000a4a: 619a str r2, [r3, #24]
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
8000a4c: 4b14 ldr r3, [pc, #80] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a4e: 2200 movs r2, #0
8000a50: 61da str r2, [r3, #28]
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
8000a52: 4b13 ldr r3, [pc, #76] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a54: f44f 6200 mov.w r2, #2048 @ 0x800
8000a58: 621a str r2, [r3, #32]
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
8000a5a: 4b11 ldr r3, [pc, #68] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a5c: 2200 movs r2, #0
8000a5e: 625a str r2, [r3, #36] @ 0x24
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
8000a60: 4b0f ldr r3, [pc, #60] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a62: f44f 5200 mov.w r2, #8192 @ 0x2000
8000a66: 629a str r2, [r3, #40] @ 0x28
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
8000a68: 2302 movs r3, #2
8000a6a: 607b str r3, [r7, #4]
SdramTiming.ExitSelfRefreshDelay = 7;
8000a6c: 2307 movs r3, #7
8000a6e: 60bb str r3, [r7, #8]
SdramTiming.SelfRefreshTime = 4;
8000a70: 2304 movs r3, #4
8000a72: 60fb str r3, [r7, #12]
SdramTiming.RowCycleDelay = 7;
8000a74: 2307 movs r3, #7
8000a76: 613b str r3, [r7, #16]
SdramTiming.WriteRecoveryTime = 3;
8000a78: 2303 movs r3, #3
8000a7a: 617b str r3, [r7, #20]
SdramTiming.RPDelay = 2;
8000a7c: 2302 movs r3, #2
8000a7e: 61bb str r3, [r7, #24]
SdramTiming.RCDDelay = 2;
8000a80: 2302 movs r3, #2
8000a82: 61fb str r3, [r7, #28]
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
8000a84: 1d3b adds r3, r7, #4
8000a86: 4619 mov r1, r3
8000a88: 4805 ldr r0, [pc, #20] @ (8000aa0 <MX_FMC_Init+0x98>)
8000a8a: f004 fbd3 bl 8005234 <HAL_SDRAM_Init>
8000a8e: 4603 mov r3, r0
8000a90: 2b00 cmp r3, #0
8000a92: d001 beq.n 8000a98 <MX_FMC_Init+0x90>
{
Error_Handler( );
8000a94: f000 f93e bl 8000d14 <Error_Handler>
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
8000a98: bf00 nop
8000a9a: 3720 adds r7, #32
8000a9c: 46bd mov sp, r7
8000a9e: bd80 pop {r7, pc}
8000aa0: 20000258 .word 0x20000258
8000aa4: a0000140 .word 0xa0000140
08000aa8 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000aa8: b580 push {r7, lr}
8000aaa: b08e sub sp, #56 @ 0x38
8000aac: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000aae: f107 0324 add.w r3, r7, #36 @ 0x24
8000ab2: 2200 movs r2, #0
8000ab4: 601a str r2, [r3, #0]
8000ab6: 605a str r2, [r3, #4]
8000ab8: 609a str r2, [r3, #8]
8000aba: 60da str r2, [r3, #12]
8000abc: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
8000abe: 2300 movs r3, #0
8000ac0: 623b str r3, [r7, #32]
8000ac2: 4b84 ldr r3, [pc, #528] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000ac4: 6b1b ldr r3, [r3, #48] @ 0x30
8000ac6: 4a83 ldr r2, [pc, #524] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000ac8: f043 0310 orr.w r3, r3, #16
8000acc: 6313 str r3, [r2, #48] @ 0x30
8000ace: 4b81 ldr r3, [pc, #516] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000ad0: 6b1b ldr r3, [r3, #48] @ 0x30
8000ad2: f003 0310 and.w r3, r3, #16
8000ad6: 623b str r3, [r7, #32]
8000ad8: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000ada: 2300 movs r3, #0
8000adc: 61fb str r3, [r7, #28]
8000ade: 4b7d ldr r3, [pc, #500] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000ae0: 6b1b ldr r3, [r3, #48] @ 0x30
8000ae2: 4a7c ldr r2, [pc, #496] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000ae4: f043 0304 orr.w r3, r3, #4
8000ae8: 6313 str r3, [r2, #48] @ 0x30
8000aea: 4b7a ldr r3, [pc, #488] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000aec: 6b1b ldr r3, [r3, #48] @ 0x30
8000aee: f003 0304 and.w r3, r3, #4
8000af2: 61fb str r3, [r7, #28]
8000af4: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000af6: 2300 movs r3, #0
8000af8: 61bb str r3, [r7, #24]
8000afa: 4b76 ldr r3, [pc, #472] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000afc: 6b1b ldr r3, [r3, #48] @ 0x30
8000afe: 4a75 ldr r2, [pc, #468] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b00: f043 0320 orr.w r3, r3, #32
8000b04: 6313 str r3, [r2, #48] @ 0x30
8000b06: 4b73 ldr r3, [pc, #460] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b08: 6b1b ldr r3, [r3, #48] @ 0x30
8000b0a: f003 0320 and.w r3, r3, #32
8000b0e: 61bb str r3, [r7, #24]
8000b10: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOH_CLK_ENABLE();
8000b12: 2300 movs r3, #0
8000b14: 617b str r3, [r7, #20]
8000b16: 4b6f ldr r3, [pc, #444] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b18: 6b1b ldr r3, [r3, #48] @ 0x30
8000b1a: 4a6e ldr r2, [pc, #440] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b1c: f043 0380 orr.w r3, r3, #128 @ 0x80
8000b20: 6313 str r3, [r2, #48] @ 0x30
8000b22: 4b6c ldr r3, [pc, #432] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b24: 6b1b ldr r3, [r3, #48] @ 0x30
8000b26: f003 0380 and.w r3, r3, #128 @ 0x80
8000b2a: 617b str r3, [r7, #20]
8000b2c: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000b2e: 2300 movs r3, #0
8000b30: 613b str r3, [r7, #16]
8000b32: 4b68 ldr r3, [pc, #416] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b34: 6b1b ldr r3, [r3, #48] @ 0x30
8000b36: 4a67 ldr r2, [pc, #412] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b38: f043 0301 orr.w r3, r3, #1
8000b3c: 6313 str r3, [r2, #48] @ 0x30
8000b3e: 4b65 ldr r3, [pc, #404] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b40: 6b1b ldr r3, [r3, #48] @ 0x30
8000b42: f003 0301 and.w r3, r3, #1
8000b46: 613b str r3, [r7, #16]
8000b48: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000b4a: 2300 movs r3, #0
8000b4c: 60fb str r3, [r7, #12]
8000b4e: 4b61 ldr r3, [pc, #388] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b50: 6b1b ldr r3, [r3, #48] @ 0x30
8000b52: 4a60 ldr r2, [pc, #384] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b54: f043 0302 orr.w r3, r3, #2
8000b58: 6313 str r3, [r2, #48] @ 0x30
8000b5a: 4b5e ldr r3, [pc, #376] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b5c: 6b1b ldr r3, [r3, #48] @ 0x30
8000b5e: f003 0302 and.w r3, r3, #2
8000b62: 60fb str r3, [r7, #12]
8000b64: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000b66: 2300 movs r3, #0
8000b68: 60bb str r3, [r7, #8]
8000b6a: 4b5a ldr r3, [pc, #360] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b6c: 6b1b ldr r3, [r3, #48] @ 0x30
8000b6e: 4a59 ldr r2, [pc, #356] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b70: f043 0340 orr.w r3, r3, #64 @ 0x40
8000b74: 6313 str r3, [r2, #48] @ 0x30
8000b76: 4b57 ldr r3, [pc, #348] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b78: 6b1b ldr r3, [r3, #48] @ 0x30
8000b7a: f003 0340 and.w r3, r3, #64 @ 0x40
8000b7e: 60bb str r3, [r7, #8]
8000b80: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000b82: 2300 movs r3, #0
8000b84: 607b str r3, [r7, #4]
8000b86: 4b53 ldr r3, [pc, #332] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b88: 6b1b ldr r3, [r3, #48] @ 0x30
8000b8a: 4a52 ldr r2, [pc, #328] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b8c: f043 0308 orr.w r3, r3, #8
8000b90: 6313 str r3, [r2, #48] @ 0x30
8000b92: 4b50 ldr r3, [pc, #320] @ (8000cd4 <MX_GPIO_Init+0x22c>)
8000b94: 6b1b ldr r3, [r3, #48] @ 0x30
8000b96: f003 0308 and.w r3, r3, #8
8000b9a: 607b str r3, [r7, #4]
8000b9c: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOE, RedLight_Pin|YellowLight_Pin|GreenLight_Pin, GPIO_PIN_RESET);
8000b9e: 2200 movs r2, #0
8000ba0: 211c movs r1, #28
8000ba2: 484d ldr r0, [pc, #308] @ (8000cd8 <MX_GPIO_Init+0x230>)
8000ba4: f001 fa12 bl 8001fcc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin, GPIO_PIN_RESET);
8000ba8: 2200 movs r2, #0
8000baa: 2116 movs r1, #22
8000bac: 484b ldr r0, [pc, #300] @ (8000cdc <MX_GPIO_Init+0x234>)
8000bae: f001 fa0d bl 8001fcc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(ACP_RST_GPIO_Port, ACP_RST_Pin, GPIO_PIN_RESET);
8000bb2: 2200 movs r2, #0
8000bb4: 2180 movs r1, #128 @ 0x80
8000bb6: 484a ldr r0, [pc, #296] @ (8000ce0 <MX_GPIO_Init+0x238>)
8000bb8: f001 fa08 bl 8001fcc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, RDX_Pin|WRX_DCX_Pin, GPIO_PIN_RESET);
8000bbc: 2200 movs r2, #0
8000bbe: f44f 5140 mov.w r1, #12288 @ 0x3000
8000bc2: 4848 ldr r0, [pc, #288] @ (8000ce4 <MX_GPIO_Init+0x23c>)
8000bc4: f001 fa02 bl 8001fcc <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOG, LD3_Pin|LD4_Pin, GPIO_PIN_RESET);
8000bc8: 2200 movs r2, #0
8000bca: f44f 41c0 mov.w r1, #24576 @ 0x6000
8000bce: 4846 ldr r0, [pc, #280] @ (8000ce8 <MX_GPIO_Init+0x240>)
8000bd0: f001 f9fc bl 8001fcc <HAL_GPIO_WritePin>
/*Configure GPIO pins : RedLight_Pin YellowLight_Pin GreenLight_Pin */
GPIO_InitStruct.Pin = RedLight_Pin|YellowLight_Pin|GreenLight_Pin;
8000bd4: 231c movs r3, #28
8000bd6: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000bd8: 2301 movs r3, #1
8000bda: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bdc: 2300 movs r3, #0
8000bde: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000be0: 2300 movs r3, #0
8000be2: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8000be4: f107 0324 add.w r3, r7, #36 @ 0x24
8000be8: 4619 mov r1, r3
8000bea: 483b ldr r0, [pc, #236] @ (8000cd8 <MX_GPIO_Init+0x230>)
8000bec: f001 f842 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pins : NCS_MEMS_SPI_Pin CSX_Pin OTG_FS_PSO_Pin */
GPIO_InitStruct.Pin = NCS_MEMS_SPI_Pin|CSX_Pin|OTG_FS_PSO_Pin;
8000bf0: 2316 movs r3, #22
8000bf2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000bf4: 2301 movs r3, #1
8000bf6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000bf8: 2300 movs r3, #0
8000bfa: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000bfc: 2300 movs r3, #0
8000bfe: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000c00: f107 0324 add.w r3, r7, #36 @ 0x24
8000c04: 4619 mov r1, r3
8000c06: 4835 ldr r0, [pc, #212] @ (8000cdc <MX_GPIO_Init+0x234>)
8000c08: f001 f834 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pins : B1_Pin MEMS_INT1_Pin MEMS_INT2_Pin TP_INT1_Pin */
GPIO_InitStruct.Pin = B1_Pin|MEMS_INT1_Pin|MEMS_INT2_Pin|TP_INT1_Pin;
8000c0c: f248 0307 movw r3, #32775 @ 0x8007
8000c10: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8000c12: f44f 1390 mov.w r3, #1179648 @ 0x120000
8000c16: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c18: 2300 movs r3, #0
8000c1a: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000c1c: f107 0324 add.w r3, r7, #36 @ 0x24
8000c20: 4619 mov r1, r3
8000c22: 482f ldr r0, [pc, #188] @ (8000ce0 <MX_GPIO_Init+0x238>)
8000c24: f001 f826 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pin : ACP_RST_Pin */
GPIO_InitStruct.Pin = ACP_RST_Pin;
8000c28: 2380 movs r3, #128 @ 0x80
8000c2a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c2c: 2301 movs r3, #1
8000c2e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c30: 2300 movs r3, #0
8000c32: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c34: 2300 movs r3, #0
8000c36: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(ACP_RST_GPIO_Port, &GPIO_InitStruct);
8000c38: f107 0324 add.w r3, r7, #36 @ 0x24
8000c3c: 4619 mov r1, r3
8000c3e: 4828 ldr r0, [pc, #160] @ (8000ce0 <MX_GPIO_Init+0x238>)
8000c40: f001 f818 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pin : OTG_FS_OC_Pin */
GPIO_InitStruct.Pin = OTG_FS_OC_Pin;
8000c44: 2320 movs r3, #32
8000c46: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_EVT_RISING;
8000c48: f44f 1390 mov.w r3, #1179648 @ 0x120000
8000c4c: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c4e: 2300 movs r3, #0
8000c50: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(OTG_FS_OC_GPIO_Port, &GPIO_InitStruct);
8000c52: f107 0324 add.w r3, r7, #36 @ 0x24
8000c56: 4619 mov r1, r3
8000c58: 4820 ldr r0, [pc, #128] @ (8000cdc <MX_GPIO_Init+0x234>)
8000c5a: f001 f80b bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pin : BOOT1_Pin */
GPIO_InitStruct.Pin = BOOT1_Pin;
8000c5e: 2304 movs r3, #4
8000c60: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000c62: 2300 movs r3, #0
8000c64: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c66: 2300 movs r3, #0
8000c68: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(BOOT1_GPIO_Port, &GPIO_InitStruct);
8000c6a: f107 0324 add.w r3, r7, #36 @ 0x24
8000c6e: 4619 mov r1, r3
8000c70: 481e ldr r0, [pc, #120] @ (8000cec <MX_GPIO_Init+0x244>)
8000c72: f000 ffff bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pin : TE_Pin */
GPIO_InitStruct.Pin = TE_Pin;
8000c76: f44f 6300 mov.w r3, #2048 @ 0x800
8000c7a: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000c7c: 2300 movs r3, #0
8000c7e: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c80: 2300 movs r3, #0
8000c82: 62fb str r3, [r7, #44] @ 0x2c
HAL_GPIO_Init(TE_GPIO_Port, &GPIO_InitStruct);
8000c84: f107 0324 add.w r3, r7, #36 @ 0x24
8000c88: 4619 mov r1, r3
8000c8a: 4816 ldr r0, [pc, #88] @ (8000ce4 <MX_GPIO_Init+0x23c>)
8000c8c: f000 fff2 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pins : RDX_Pin WRX_DCX_Pin */
GPIO_InitStruct.Pin = RDX_Pin|WRX_DCX_Pin;
8000c90: f44f 5340 mov.w r3, #12288 @ 0x3000
8000c94: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000c96: 2301 movs r3, #1
8000c98: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000c9a: 2300 movs r3, #0
8000c9c: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000c9e: 2300 movs r3, #0
8000ca0: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8000ca2: f107 0324 add.w r3, r7, #36 @ 0x24
8000ca6: 4619 mov r1, r3
8000ca8: 480e ldr r0, [pc, #56] @ (8000ce4 <MX_GPIO_Init+0x23c>)
8000caa: f000 ffe3 bl 8001c74 <HAL_GPIO_Init>
/*Configure GPIO pins : LD3_Pin LD4_Pin */
GPIO_InitStruct.Pin = LD3_Pin|LD4_Pin;
8000cae: f44f 43c0 mov.w r3, #24576 @ 0x6000
8000cb2: 627b str r3, [r7, #36] @ 0x24
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000cb4: 2301 movs r3, #1
8000cb6: 62bb str r3, [r7, #40] @ 0x28
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000cb8: 2300 movs r3, #0
8000cba: 62fb str r3, [r7, #44] @ 0x2c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000cbc: 2300 movs r3, #0
8000cbe: 633b str r3, [r7, #48] @ 0x30
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8000cc0: f107 0324 add.w r3, r7, #36 @ 0x24
8000cc4: 4619 mov r1, r3
8000cc6: 4808 ldr r0, [pc, #32] @ (8000ce8 <MX_GPIO_Init+0x240>)
8000cc8: f000 ffd4 bl 8001c74 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000ccc: bf00 nop
8000cce: 3738 adds r7, #56 @ 0x38
8000cd0: 46bd mov sp, r7
8000cd2: bd80 pop {r7, pc}
8000cd4: 40023800 .word 0x40023800
8000cd8: 40021000 .word 0x40021000
8000cdc: 40020800 .word 0x40020800
8000ce0: 40020000 .word 0x40020000
8000ce4: 40020c00 .word 0x40020c00
8000ce8: 40021800 .word 0x40021800
8000cec: 40020400 .word 0x40020400
08000cf0 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8000cf0: b580 push {r7, lr}
8000cf2: b082 sub sp, #8
8000cf4: af00 add r7, sp, #0
8000cf6: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM6)
8000cf8: 687b ldr r3, [r7, #4]
8000cfa: 681b ldr r3, [r3, #0]
8000cfc: 4a04 ldr r2, [pc, #16] @ (8000d10 <HAL_TIM_PeriodElapsedCallback+0x20>)
8000cfe: 4293 cmp r3, r2
8000d00: d101 bne.n 8000d06 <HAL_TIM_PeriodElapsedCallback+0x16>
{
HAL_IncTick();
8000d02: f000 fc89 bl 8001618 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8000d06: bf00 nop
8000d08: 3708 adds r7, #8
8000d0a: 46bd mov sp, r7
8000d0c: bd80 pop {r7, pc}
8000d0e: bf00 nop
8000d10: 40001000 .word 0x40001000
08000d14 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000d14: b480 push {r7}
8000d16: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000d18: b672 cpsid i
}
8000d1a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000d1c: bf00 nop
8000d1e: e7fd b.n 8000d1c <Error_Handler+0x8>
08000d20 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000d20: b580 push {r7, lr}
8000d22: b082 sub sp, #8
8000d24: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000d26: 2300 movs r3, #0
8000d28: 607b str r3, [r7, #4]
8000d2a: 4b12 ldr r3, [pc, #72] @ (8000d74 <HAL_MspInit+0x54>)
8000d2c: 6c5b ldr r3, [r3, #68] @ 0x44
8000d2e: 4a11 ldr r2, [pc, #68] @ (8000d74 <HAL_MspInit+0x54>)
8000d30: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8000d34: 6453 str r3, [r2, #68] @ 0x44
8000d36: 4b0f ldr r3, [pc, #60] @ (8000d74 <HAL_MspInit+0x54>)
8000d38: 6c5b ldr r3, [r3, #68] @ 0x44
8000d3a: f403 4380 and.w r3, r3, #16384 @ 0x4000
8000d3e: 607b str r3, [r7, #4]
8000d40: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8000d42: 2300 movs r3, #0
8000d44: 603b str r3, [r7, #0]
8000d46: 4b0b ldr r3, [pc, #44] @ (8000d74 <HAL_MspInit+0x54>)
8000d48: 6c1b ldr r3, [r3, #64] @ 0x40
8000d4a: 4a0a ldr r2, [pc, #40] @ (8000d74 <HAL_MspInit+0x54>)
8000d4c: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8000d50: 6413 str r3, [r2, #64] @ 0x40
8000d52: 4b08 ldr r3, [pc, #32] @ (8000d74 <HAL_MspInit+0x54>)
8000d54: 6c1b ldr r3, [r3, #64] @ 0x40
8000d56: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8000d5a: 603b str r3, [r7, #0]
8000d5c: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
8000d5e: 2200 movs r2, #0
8000d60: 210f movs r1, #15
8000d62: f06f 0001 mvn.w r0, #1
8000d66: f000 fd53 bl 8001810 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000d6a: bf00 nop
8000d6c: 3708 adds r7, #8
8000d6e: 46bd mov sp, r7
8000d70: bd80 pop {r7, pc}
8000d72: bf00 nop
8000d74: 40023800 .word 0x40023800
08000d78 <HAL_CRC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcrc: CRC handle pointer
* @retval None
*/
void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc)
{
8000d78: b480 push {r7}
8000d7a: b085 sub sp, #20
8000d7c: af00 add r7, sp, #0
8000d7e: 6078 str r0, [r7, #4]
if(hcrc->Instance==CRC)
8000d80: 687b ldr r3, [r7, #4]
8000d82: 681b ldr r3, [r3, #0]
8000d84: 4a0b ldr r2, [pc, #44] @ (8000db4 <HAL_CRC_MspInit+0x3c>)
8000d86: 4293 cmp r3, r2
8000d88: d10d bne.n 8000da6 <HAL_CRC_MspInit+0x2e>
{
/* USER CODE BEGIN CRC_MspInit 0 */
/* USER CODE END CRC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CRC_CLK_ENABLE();
8000d8a: 2300 movs r3, #0
8000d8c: 60fb str r3, [r7, #12]
8000d8e: 4b0a ldr r3, [pc, #40] @ (8000db8 <HAL_CRC_MspInit+0x40>)
8000d90: 6b1b ldr r3, [r3, #48] @ 0x30
8000d92: 4a09 ldr r2, [pc, #36] @ (8000db8 <HAL_CRC_MspInit+0x40>)
8000d94: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8000d98: 6313 str r3, [r2, #48] @ 0x30
8000d9a: 4b07 ldr r3, [pc, #28] @ (8000db8 <HAL_CRC_MspInit+0x40>)
8000d9c: 6b1b ldr r3, [r3, #48] @ 0x30
8000d9e: f403 5380 and.w r3, r3, #4096 @ 0x1000
8000da2: 60fb str r3, [r7, #12]
8000da4: 68fb ldr r3, [r7, #12]
/* USER CODE END CRC_MspInit 1 */
}
}
8000da6: bf00 nop
8000da8: 3714 adds r7, #20
8000daa: 46bd mov sp, r7
8000dac: f85d 7b04 ldr.w r7, [sp], #4
8000db0: 4770 bx lr
8000db2: bf00 nop
8000db4: 40023000 .word 0x40023000
8000db8: 40023800 .word 0x40023800
08000dbc <HAL_DMA2D_MspInit>:
* This function configures the hardware resources used in this example
* @param hdma2d: DMA2D handle pointer
* @retval None
*/
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
{
8000dbc: b580 push {r7, lr}
8000dbe: b084 sub sp, #16
8000dc0: af00 add r7, sp, #0
8000dc2: 6078 str r0, [r7, #4]
if(hdma2d->Instance==DMA2D)
8000dc4: 687b ldr r3, [r7, #4]
8000dc6: 681b ldr r3, [r3, #0]
8000dc8: 4a0e ldr r2, [pc, #56] @ (8000e04 <HAL_DMA2D_MspInit+0x48>)
8000dca: 4293 cmp r3, r2
8000dcc: d115 bne.n 8000dfa <HAL_DMA2D_MspInit+0x3e>
{
/* USER CODE BEGIN DMA2D_MspInit 0 */
/* USER CODE END DMA2D_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DMA2D_CLK_ENABLE();
8000dce: 2300 movs r3, #0
8000dd0: 60fb str r3, [r7, #12]
8000dd2: 4b0d ldr r3, [pc, #52] @ (8000e08 <HAL_DMA2D_MspInit+0x4c>)
8000dd4: 6b1b ldr r3, [r3, #48] @ 0x30
8000dd6: 4a0c ldr r2, [pc, #48] @ (8000e08 <HAL_DMA2D_MspInit+0x4c>)
8000dd8: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8000ddc: 6313 str r3, [r2, #48] @ 0x30
8000dde: 4b0a ldr r3, [pc, #40] @ (8000e08 <HAL_DMA2D_MspInit+0x4c>)
8000de0: 6b1b ldr r3, [r3, #48] @ 0x30
8000de2: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8000de6: 60fb str r3, [r7, #12]
8000de8: 68fb ldr r3, [r7, #12]
/* DMA2D interrupt Init */
HAL_NVIC_SetPriority(DMA2D_IRQn, 5, 0);
8000dea: 2200 movs r2, #0
8000dec: 2105 movs r1, #5
8000dee: 205a movs r0, #90 @ 0x5a
8000df0: f000 fd0e bl 8001810 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA2D_IRQn);
8000df4: 205a movs r0, #90 @ 0x5a
8000df6: f000 fd27 bl 8001848 <HAL_NVIC_EnableIRQ>
/* USER CODE END DMA2D_MspInit 1 */
}
}
8000dfa: bf00 nop
8000dfc: 3710 adds r7, #16
8000dfe: 46bd mov sp, r7
8000e00: bd80 pop {r7, pc}
8000e02: bf00 nop
8000e04: 4002b000 .word 0x4002b000
8000e08: 40023800 .word 0x40023800
08000e0c <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8000e0c: b580 push {r7, lr}
8000e0e: b08a sub sp, #40 @ 0x28
8000e10: af00 add r7, sp, #0
8000e12: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000e14: f107 0314 add.w r3, r7, #20
8000e18: 2200 movs r2, #0
8000e1a: 601a str r2, [r3, #0]
8000e1c: 605a str r2, [r3, #4]
8000e1e: 609a str r2, [r3, #8]
8000e20: 60da str r2, [r3, #12]
8000e22: 611a str r2, [r3, #16]
if(hi2c->Instance==I2C3)
8000e24: 687b ldr r3, [r7, #4]
8000e26: 681b ldr r3, [r3, #0]
8000e28: 4a29 ldr r2, [pc, #164] @ (8000ed0 <HAL_I2C_MspInit+0xc4>)
8000e2a: 4293 cmp r3, r2
8000e2c: d14b bne.n 8000ec6 <HAL_I2C_MspInit+0xba>
{
/* USER CODE BEGIN I2C3_MspInit 0 */
/* USER CODE END I2C3_MspInit 0 */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000e2e: 2300 movs r3, #0
8000e30: 613b str r3, [r7, #16]
8000e32: 4b28 ldr r3, [pc, #160] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e34: 6b1b ldr r3, [r3, #48] @ 0x30
8000e36: 4a27 ldr r2, [pc, #156] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e38: f043 0304 orr.w r3, r3, #4
8000e3c: 6313 str r3, [r2, #48] @ 0x30
8000e3e: 4b25 ldr r3, [pc, #148] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e40: 6b1b ldr r3, [r3, #48] @ 0x30
8000e42: f003 0304 and.w r3, r3, #4
8000e46: 613b str r3, [r7, #16]
8000e48: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000e4a: 2300 movs r3, #0
8000e4c: 60fb str r3, [r7, #12]
8000e4e: 4b21 ldr r3, [pc, #132] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e50: 6b1b ldr r3, [r3, #48] @ 0x30
8000e52: 4a20 ldr r2, [pc, #128] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e54: f043 0301 orr.w r3, r3, #1
8000e58: 6313 str r3, [r2, #48] @ 0x30
8000e5a: 4b1e ldr r3, [pc, #120] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000e5c: 6b1b ldr r3, [r3, #48] @ 0x30
8000e5e: f003 0301 and.w r3, r3, #1
8000e62: 60fb str r3, [r7, #12]
8000e64: 68fb ldr r3, [r7, #12]
/**I2C3 GPIO Configuration
PC9 ------> I2C3_SDA
PA8 ------> I2C3_SCL
*/
GPIO_InitStruct.Pin = I2C3_SDA_Pin;
8000e66: f44f 7300 mov.w r3, #512 @ 0x200
8000e6a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000e6c: 2312 movs r3, #18
8000e6e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000e70: 2301 movs r3, #1
8000e72: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e74: 2300 movs r3, #0
8000e76: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000e78: 2304 movs r3, #4
8000e7a: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(I2C3_SDA_GPIO_Port, &GPIO_InitStruct);
8000e7c: f107 0314 add.w r3, r7, #20
8000e80: 4619 mov r1, r3
8000e82: 4815 ldr r0, [pc, #84] @ (8000ed8 <HAL_I2C_MspInit+0xcc>)
8000e84: f000 fef6 bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = I2C3_SCL_Pin;
8000e88: f44f 7380 mov.w r3, #256 @ 0x100
8000e8c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
8000e8e: 2312 movs r3, #18
8000e90: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000e92: 2301 movs r3, #1
8000e94: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000e96: 2300 movs r3, #0
8000e98: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;
8000e9a: 2304 movs r3, #4
8000e9c: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(I2C3_SCL_GPIO_Port, &GPIO_InitStruct);
8000e9e: f107 0314 add.w r3, r7, #20
8000ea2: 4619 mov r1, r3
8000ea4: 480d ldr r0, [pc, #52] @ (8000edc <HAL_I2C_MspInit+0xd0>)
8000ea6: f000 fee5 bl 8001c74 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C3_CLK_ENABLE();
8000eaa: 2300 movs r3, #0
8000eac: 60bb str r3, [r7, #8]
8000eae: 4b09 ldr r3, [pc, #36] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000eb0: 6c1b ldr r3, [r3, #64] @ 0x40
8000eb2: 4a08 ldr r2, [pc, #32] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000eb4: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8000eb8: 6413 str r3, [r2, #64] @ 0x40
8000eba: 4b06 ldr r3, [pc, #24] @ (8000ed4 <HAL_I2C_MspInit+0xc8>)
8000ebc: 6c1b ldr r3, [r3, #64] @ 0x40
8000ebe: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8000ec2: 60bb str r3, [r7, #8]
8000ec4: 68bb ldr r3, [r7, #8]
/* USER CODE END I2C3_MspInit 1 */
}
}
8000ec6: bf00 nop
8000ec8: 3728 adds r7, #40 @ 0x28
8000eca: 46bd mov sp, r7
8000ecc: bd80 pop {r7, pc}
8000ece: bf00 nop
8000ed0: 40005c00 .word 0x40005c00
8000ed4: 40023800 .word 0x40023800
8000ed8: 40020800 .word 0x40020800
8000edc: 40020000 .word 0x40020000
08000ee0 <HAL_LTDC_MspInit>:
* This function configures the hardware resources used in this example
* @param hltdc: LTDC handle pointer
* @retval None
*/
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
{
8000ee0: b580 push {r7, lr}
8000ee2: b09a sub sp, #104 @ 0x68
8000ee4: af00 add r7, sp, #0
8000ee6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000ee8: f107 0354 add.w r3, r7, #84 @ 0x54
8000eec: 2200 movs r2, #0
8000eee: 601a str r2, [r3, #0]
8000ef0: 605a str r2, [r3, #4]
8000ef2: 609a str r2, [r3, #8]
8000ef4: 60da str r2, [r3, #12]
8000ef6: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8000ef8: f107 0324 add.w r3, r7, #36 @ 0x24
8000efc: 2230 movs r2, #48 @ 0x30
8000efe: 2100 movs r1, #0
8000f00: 4618 mov r0, r3
8000f02: f006 ffc5 bl 8007e90 <memset>
if(hltdc->Instance==LTDC)
8000f06: 687b ldr r3, [r7, #4]
8000f08: 681b ldr r3, [r3, #0]
8000f0a: 4a85 ldr r2, [pc, #532] @ (8001120 <HAL_LTDC_MspInit+0x240>)
8000f0c: 4293 cmp r3, r2
8000f0e: f040 8102 bne.w 8001116 <HAL_LTDC_MspInit+0x236>
/* USER CODE END LTDC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
8000f12: 2308 movs r3, #8
8000f14: 627b str r3, [r7, #36] @ 0x24
PeriphClkInitStruct.PLLSAI.PLLSAIN = 50;
8000f16: 2332 movs r3, #50 @ 0x32
8000f18: 637b str r3, [r7, #52] @ 0x34
PeriphClkInitStruct.PLLSAI.PLLSAIR = 2;
8000f1a: 2302 movs r3, #2
8000f1c: 63fb str r3, [r7, #60] @ 0x3c
PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_2;
8000f1e: 2300 movs r3, #0
8000f20: 64bb str r3, [r7, #72] @ 0x48
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8000f22: f107 0324 add.w r3, r7, #36 @ 0x24
8000f26: 4618 mov r0, r3
8000f28: f003 ffc4 bl 8004eb4 <HAL_RCCEx_PeriphCLKConfig>
8000f2c: 4603 mov r3, r0
8000f2e: 2b00 cmp r3, #0
8000f30: d001 beq.n 8000f36 <HAL_LTDC_MspInit+0x56>
{
Error_Handler();
8000f32: f7ff feef bl 8000d14 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_LTDC_CLK_ENABLE();
8000f36: 2300 movs r3, #0
8000f38: 623b str r3, [r7, #32]
8000f3a: 4b7a ldr r3, [pc, #488] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f3c: 6c5b ldr r3, [r3, #68] @ 0x44
8000f3e: 4a79 ldr r2, [pc, #484] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f40: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8000f44: 6453 str r3, [r2, #68] @ 0x44
8000f46: 4b77 ldr r3, [pc, #476] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f48: 6c5b ldr r3, [r3, #68] @ 0x44
8000f4a: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8000f4e: 623b str r3, [r7, #32]
8000f50: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOF_CLK_ENABLE();
8000f52: 2300 movs r3, #0
8000f54: 61fb str r3, [r7, #28]
8000f56: 4b73 ldr r3, [pc, #460] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f58: 6b1b ldr r3, [r3, #48] @ 0x30
8000f5a: 4a72 ldr r2, [pc, #456] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f5c: f043 0320 orr.w r3, r3, #32
8000f60: 6313 str r3, [r2, #48] @ 0x30
8000f62: 4b70 ldr r3, [pc, #448] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f64: 6b1b ldr r3, [r3, #48] @ 0x30
8000f66: f003 0320 and.w r3, r3, #32
8000f6a: 61fb str r3, [r7, #28]
8000f6c: 69fb ldr r3, [r7, #28]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000f6e: 2300 movs r3, #0
8000f70: 61bb str r3, [r7, #24]
8000f72: 4b6c ldr r3, [pc, #432] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f74: 6b1b ldr r3, [r3, #48] @ 0x30
8000f76: 4a6b ldr r2, [pc, #428] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f78: f043 0301 orr.w r3, r3, #1
8000f7c: 6313 str r3, [r2, #48] @ 0x30
8000f7e: 4b69 ldr r3, [pc, #420] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f80: 6b1b ldr r3, [r3, #48] @ 0x30
8000f82: f003 0301 and.w r3, r3, #1
8000f86: 61bb str r3, [r7, #24]
8000f88: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000f8a: 2300 movs r3, #0
8000f8c: 617b str r3, [r7, #20]
8000f8e: 4b65 ldr r3, [pc, #404] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f90: 6b1b ldr r3, [r3, #48] @ 0x30
8000f92: 4a64 ldr r2, [pc, #400] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f94: f043 0302 orr.w r3, r3, #2
8000f98: 6313 str r3, [r2, #48] @ 0x30
8000f9a: 4b62 ldr r3, [pc, #392] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000f9c: 6b1b ldr r3, [r3, #48] @ 0x30
8000f9e: f003 0302 and.w r3, r3, #2
8000fa2: 617b str r3, [r7, #20]
8000fa4: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOG_CLK_ENABLE();
8000fa6: 2300 movs r3, #0
8000fa8: 613b str r3, [r7, #16]
8000faa: 4b5e ldr r3, [pc, #376] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fac: 6b1b ldr r3, [r3, #48] @ 0x30
8000fae: 4a5d ldr r2, [pc, #372] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fb0: f043 0340 orr.w r3, r3, #64 @ 0x40
8000fb4: 6313 str r3, [r2, #48] @ 0x30
8000fb6: 4b5b ldr r3, [pc, #364] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fb8: 6b1b ldr r3, [r3, #48] @ 0x30
8000fba: f003 0340 and.w r3, r3, #64 @ 0x40
8000fbe: 613b str r3, [r7, #16]
8000fc0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8000fc2: 2300 movs r3, #0
8000fc4: 60fb str r3, [r7, #12]
8000fc6: 4b57 ldr r3, [pc, #348] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fc8: 6b1b ldr r3, [r3, #48] @ 0x30
8000fca: 4a56 ldr r2, [pc, #344] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fcc: f043 0304 orr.w r3, r3, #4
8000fd0: 6313 str r3, [r2, #48] @ 0x30
8000fd2: 4b54 ldr r3, [pc, #336] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fd4: 6b1b ldr r3, [r3, #48] @ 0x30
8000fd6: f003 0304 and.w r3, r3, #4
8000fda: 60fb str r3, [r7, #12]
8000fdc: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000fde: 2300 movs r3, #0
8000fe0: 60bb str r3, [r7, #8]
8000fe2: 4b50 ldr r3, [pc, #320] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fe4: 6b1b ldr r3, [r3, #48] @ 0x30
8000fe6: 4a4f ldr r2, [pc, #316] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000fe8: f043 0308 orr.w r3, r3, #8
8000fec: 6313 str r3, [r2, #48] @ 0x30
8000fee: 4b4d ldr r3, [pc, #308] @ (8001124 <HAL_LTDC_MspInit+0x244>)
8000ff0: 6b1b ldr r3, [r3, #48] @ 0x30
8000ff2: f003 0308 and.w r3, r3, #8
8000ff6: 60bb str r3, [r7, #8]
8000ff8: 68bb ldr r3, [r7, #8]
PG11 ------> LTDC_B3
PG12 ------> LTDC_B4
PB8 ------> LTDC_B6
PB9 ------> LTDC_B7
*/
GPIO_InitStruct.Pin = ENABLE_Pin;
8000ffa: f44f 6380 mov.w r3, #1024 @ 0x400
8000ffe: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001000: 2302 movs r3, #2
8001002: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001004: 2300 movs r3, #0
8001006: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001008: 2300 movs r3, #0
800100a: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
800100c: 230e movs r3, #14
800100e: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(ENABLE_GPIO_Port, &GPIO_InitStruct);
8001010: f107 0354 add.w r3, r7, #84 @ 0x54
8001014: 4619 mov r1, r3
8001016: 4844 ldr r0, [pc, #272] @ (8001128 <HAL_LTDC_MspInit+0x248>)
8001018: f000 fe2c bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = B5_Pin|VSYNC_Pin|G2_Pin|R4_Pin
800101c: f641 0358 movw r3, #6232 @ 0x1858
8001020: 657b str r3, [r7, #84] @ 0x54
|R5_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001022: 2302 movs r3, #2
8001024: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001026: 2300 movs r3, #0
8001028: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800102a: 2300 movs r3, #0
800102c: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
800102e: 230e movs r3, #14
8001030: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001032: f107 0354 add.w r3, r7, #84 @ 0x54
8001036: 4619 mov r1, r3
8001038: 483c ldr r0, [pc, #240] @ (800112c <HAL_LTDC_MspInit+0x24c>)
800103a: f000 fe1b bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = R3_Pin|R6_Pin;
800103e: 2303 movs r3, #3
8001040: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001042: 2302 movs r3, #2
8001044: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001046: 2300 movs r3, #0
8001048: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800104a: 2300 movs r3, #0
800104c: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
800104e: 2309 movs r3, #9
8001050: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001052: f107 0354 add.w r3, r7, #84 @ 0x54
8001056: 4619 mov r1, r3
8001058: 4835 ldr r0, [pc, #212] @ (8001130 <HAL_LTDC_MspInit+0x250>)
800105a: f000 fe0b bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G4_Pin|G5_Pin|B6_Pin|B7_Pin;
800105e: f44f 6370 mov.w r3, #3840 @ 0xf00
8001062: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001064: 2302 movs r3, #2
8001066: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001068: 2300 movs r3, #0
800106a: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800106c: 2300 movs r3, #0
800106e: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8001070: 230e movs r3, #14
8001072: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001074: f107 0354 add.w r3, r7, #84 @ 0x54
8001078: 4619 mov r1, r3
800107a: 482d ldr r0, [pc, #180] @ (8001130 <HAL_LTDC_MspInit+0x250>)
800107c: f000 fdfa bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = R7_Pin|DOTCLK_Pin|B3_Pin;
8001080: f44f 630c mov.w r3, #2240 @ 0x8c0
8001084: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001086: 2302 movs r3, #2
8001088: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
800108a: 2300 movs r3, #0
800108c: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
800108e: 2300 movs r3, #0
8001090: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
8001092: 230e movs r3, #14
8001094: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001096: f107 0354 add.w r3, r7, #84 @ 0x54
800109a: 4619 mov r1, r3
800109c: 4825 ldr r0, [pc, #148] @ (8001134 <HAL_LTDC_MspInit+0x254>)
800109e: f000 fde9 bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = HSYNC_Pin|G6_Pin|R2_Pin;
80010a2: f44f 6398 mov.w r3, #1216 @ 0x4c0
80010a6: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010a8: 2302 movs r3, #2
80010aa: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010ac: 2300 movs r3, #0
80010ae: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010b0: 2300 movs r3, #0
80010b2: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80010b4: 230e movs r3, #14
80010b6: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80010b8: f107 0354 add.w r3, r7, #84 @ 0x54
80010bc: 4619 mov r1, r3
80010be: 481e ldr r0, [pc, #120] @ (8001138 <HAL_LTDC_MspInit+0x258>)
80010c0: f000 fdd8 bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G7_Pin|B2_Pin;
80010c4: 2348 movs r3, #72 @ 0x48
80010c6: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010c8: 2302 movs r3, #2
80010ca: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010cc: 2300 movs r3, #0
80010ce: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010d0: 2300 movs r3, #0
80010d2: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
80010d4: 230e movs r3, #14
80010d6: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80010d8: f107 0354 add.w r3, r7, #84 @ 0x54
80010dc: 4619 mov r1, r3
80010de: 4817 ldr r0, [pc, #92] @ (800113c <HAL_LTDC_MspInit+0x25c>)
80010e0: f000 fdc8 bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = G3_Pin|B4_Pin;
80010e4: f44f 53a0 mov.w r3, #5120 @ 0x1400
80010e8: 657b str r3, [r7, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80010ea: 2302 movs r3, #2
80010ec: 65bb str r3, [r7, #88] @ 0x58
GPIO_InitStruct.Pull = GPIO_NOPULL;
80010ee: 2300 movs r3, #0
80010f0: 65fb str r3, [r7, #92] @ 0x5c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80010f2: 2300 movs r3, #0
80010f4: 663b str r3, [r7, #96] @ 0x60
GPIO_InitStruct.Alternate = GPIO_AF9_LTDC;
80010f6: 2309 movs r3, #9
80010f8: 667b str r3, [r7, #100] @ 0x64
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
80010fa: f107 0354 add.w r3, r7, #84 @ 0x54
80010fe: 4619 mov r1, r3
8001100: 480c ldr r0, [pc, #48] @ (8001134 <HAL_LTDC_MspInit+0x254>)
8001102: f000 fdb7 bl 8001c74 <HAL_GPIO_Init>
/* LTDC interrupt Init */
HAL_NVIC_SetPriority(LTDC_IRQn, 5, 0);
8001106: 2200 movs r2, #0
8001108: 2105 movs r1, #5
800110a: 2058 movs r0, #88 @ 0x58
800110c: f000 fb80 bl 8001810 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(LTDC_IRQn);
8001110: 2058 movs r0, #88 @ 0x58
8001112: f000 fb99 bl 8001848 <HAL_NVIC_EnableIRQ>
/* USER CODE END LTDC_MspInit 1 */
}
}
8001116: bf00 nop
8001118: 3768 adds r7, #104 @ 0x68
800111a: 46bd mov sp, r7
800111c: bd80 pop {r7, pc}
800111e: bf00 nop
8001120: 40016800 .word 0x40016800
8001124: 40023800 .word 0x40023800
8001128: 40021400 .word 0x40021400
800112c: 40020000 .word 0x40020000
8001130: 40020400 .word 0x40020400
8001134: 40021800 .word 0x40021800
8001138: 40020800 .word 0x40020800
800113c: 40020c00 .word 0x40020c00
08001140 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001140: b580 push {r7, lr}
8001142: b08a sub sp, #40 @ 0x28
8001144: af00 add r7, sp, #0
8001146: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001148: f107 0314 add.w r3, r7, #20
800114c: 2200 movs r2, #0
800114e: 601a str r2, [r3, #0]
8001150: 605a str r2, [r3, #4]
8001152: 609a str r2, [r3, #8]
8001154: 60da str r2, [r3, #12]
8001156: 611a str r2, [r3, #16]
if(hspi->Instance==SPI5)
8001158: 687b ldr r3, [r7, #4]
800115a: 681b ldr r3, [r3, #0]
800115c: 4a19 ldr r2, [pc, #100] @ (80011c4 <HAL_SPI_MspInit+0x84>)
800115e: 4293 cmp r3, r2
8001160: d12c bne.n 80011bc <HAL_SPI_MspInit+0x7c>
{
/* USER CODE BEGIN SPI5_MspInit 0 */
/* USER CODE END SPI5_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_SPI5_CLK_ENABLE();
8001162: 2300 movs r3, #0
8001164: 613b str r3, [r7, #16]
8001166: 4b18 ldr r3, [pc, #96] @ (80011c8 <HAL_SPI_MspInit+0x88>)
8001168: 6c5b ldr r3, [r3, #68] @ 0x44
800116a: 4a17 ldr r2, [pc, #92] @ (80011c8 <HAL_SPI_MspInit+0x88>)
800116c: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8001170: 6453 str r3, [r2, #68] @ 0x44
8001172: 4b15 ldr r3, [pc, #84] @ (80011c8 <HAL_SPI_MspInit+0x88>)
8001174: 6c5b ldr r3, [r3, #68] @ 0x44
8001176: f403 1380 and.w r3, r3, #1048576 @ 0x100000
800117a: 613b str r3, [r7, #16]
800117c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOF_CLK_ENABLE();
800117e: 2300 movs r3, #0
8001180: 60fb str r3, [r7, #12]
8001182: 4b11 ldr r3, [pc, #68] @ (80011c8 <HAL_SPI_MspInit+0x88>)
8001184: 6b1b ldr r3, [r3, #48] @ 0x30
8001186: 4a10 ldr r2, [pc, #64] @ (80011c8 <HAL_SPI_MspInit+0x88>)
8001188: f043 0320 orr.w r3, r3, #32
800118c: 6313 str r3, [r2, #48] @ 0x30
800118e: 4b0e ldr r3, [pc, #56] @ (80011c8 <HAL_SPI_MspInit+0x88>)
8001190: 6b1b ldr r3, [r3, #48] @ 0x30
8001192: f003 0320 and.w r3, r3, #32
8001196: 60fb str r3, [r7, #12]
8001198: 68fb ldr r3, [r7, #12]
/**SPI5 GPIO Configuration
PF7 ------> SPI5_SCK
PF8 ------> SPI5_MISO
PF9 ------> SPI5_MOSI
*/
GPIO_InitStruct.Pin = SPI5_SCK_Pin|SPI5_MISO_Pin|SPI5_MOSI_Pin;
800119a: f44f 7360 mov.w r3, #896 @ 0x380
800119e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80011a0: 2302 movs r3, #2
80011a2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80011a4: 2300 movs r3, #0
80011a6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80011a8: 2300 movs r3, #0
80011aa: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
80011ac: 2305 movs r3, #5
80011ae: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80011b0: f107 0314 add.w r3, r7, #20
80011b4: 4619 mov r1, r3
80011b6: 4805 ldr r0, [pc, #20] @ (80011cc <HAL_SPI_MspInit+0x8c>)
80011b8: f000 fd5c bl 8001c74 <HAL_GPIO_Init>
/* USER CODE END SPI5_MspInit 1 */
}
}
80011bc: bf00 nop
80011be: 3728 adds r7, #40 @ 0x28
80011c0: 46bd mov sp, r7
80011c2: bd80 pop {r7, pc}
80011c4: 40015000 .word 0x40015000
80011c8: 40023800 .word 0x40023800
80011cc: 40021400 .word 0x40021400
080011d0 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
80011d0: b480 push {r7}
80011d2: b085 sub sp, #20
80011d4: af00 add r7, sp, #0
80011d6: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
80011d8: 687b ldr r3, [r7, #4]
80011da: 681b ldr r3, [r3, #0]
80011dc: 4a0b ldr r2, [pc, #44] @ (800120c <HAL_TIM_Base_MspInit+0x3c>)
80011de: 4293 cmp r3, r2
80011e0: d10d bne.n 80011fe <HAL_TIM_Base_MspInit+0x2e>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
80011e2: 2300 movs r3, #0
80011e4: 60fb str r3, [r7, #12]
80011e6: 4b0a ldr r3, [pc, #40] @ (8001210 <HAL_TIM_Base_MspInit+0x40>)
80011e8: 6c5b ldr r3, [r3, #68] @ 0x44
80011ea: 4a09 ldr r2, [pc, #36] @ (8001210 <HAL_TIM_Base_MspInit+0x40>)
80011ec: f043 0301 orr.w r3, r3, #1
80011f0: 6453 str r3, [r2, #68] @ 0x44
80011f2: 4b07 ldr r3, [pc, #28] @ (8001210 <HAL_TIM_Base_MspInit+0x40>)
80011f4: 6c5b ldr r3, [r3, #68] @ 0x44
80011f6: f003 0301 and.w r3, r3, #1
80011fa: 60fb str r3, [r7, #12]
80011fc: 68fb ldr r3, [r7, #12]
/* USER CODE END TIM1_MspInit 1 */
}
}
80011fe: bf00 nop
8001200: 3714 adds r7, #20
8001202: 46bd mov sp, r7
8001204: f85d 7b04 ldr.w r7, [sp], #4
8001208: 4770 bx lr
800120a: bf00 nop
800120c: 40010000 .word 0x40010000
8001210: 40023800 .word 0x40023800
08001214 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001214: b580 push {r7, lr}
8001216: b08a sub sp, #40 @ 0x28
8001218: af00 add r7, sp, #0
800121a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800121c: f107 0314 add.w r3, r7, #20
8001220: 2200 movs r2, #0
8001222: 601a str r2, [r3, #0]
8001224: 605a str r2, [r3, #4]
8001226: 609a str r2, [r3, #8]
8001228: 60da str r2, [r3, #12]
800122a: 611a str r2, [r3, #16]
if(huart->Instance==USART1)
800122c: 687b ldr r3, [r7, #4]
800122e: 681b ldr r3, [r3, #0]
8001230: 4a19 ldr r2, [pc, #100] @ (8001298 <HAL_UART_MspInit+0x84>)
8001232: 4293 cmp r3, r2
8001234: d12c bne.n 8001290 <HAL_UART_MspInit+0x7c>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001236: 2300 movs r3, #0
8001238: 613b str r3, [r7, #16]
800123a: 4b18 ldr r3, [pc, #96] @ (800129c <HAL_UART_MspInit+0x88>)
800123c: 6c5b ldr r3, [r3, #68] @ 0x44
800123e: 4a17 ldr r2, [pc, #92] @ (800129c <HAL_UART_MspInit+0x88>)
8001240: f043 0310 orr.w r3, r3, #16
8001244: 6453 str r3, [r2, #68] @ 0x44
8001246: 4b15 ldr r3, [pc, #84] @ (800129c <HAL_UART_MspInit+0x88>)
8001248: 6c5b ldr r3, [r3, #68] @ 0x44
800124a: f003 0310 and.w r3, r3, #16
800124e: 613b str r3, [r7, #16]
8001250: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001252: 2300 movs r3, #0
8001254: 60fb str r3, [r7, #12]
8001256: 4b11 ldr r3, [pc, #68] @ (800129c <HAL_UART_MspInit+0x88>)
8001258: 6b1b ldr r3, [r3, #48] @ 0x30
800125a: 4a10 ldr r2, [pc, #64] @ (800129c <HAL_UART_MspInit+0x88>)
800125c: f043 0301 orr.w r3, r3, #1
8001260: 6313 str r3, [r2, #48] @ 0x30
8001262: 4b0e ldr r3, [pc, #56] @ (800129c <HAL_UART_MspInit+0x88>)
8001264: 6b1b ldr r3, [r3, #48] @ 0x30
8001266: f003 0301 and.w r3, r3, #1
800126a: 60fb str r3, [r7, #12]
800126c: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin;
800126e: f44f 63c0 mov.w r3, #1536 @ 0x600
8001272: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001274: 2302 movs r3, #2
8001276: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001278: 2300 movs r3, #0
800127a: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800127c: 2303 movs r3, #3
800127e: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001280: 2307 movs r3, #7
8001282: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001284: f107 0314 add.w r3, r7, #20
8001288: 4619 mov r1, r3
800128a: 4805 ldr r0, [pc, #20] @ (80012a0 <HAL_UART_MspInit+0x8c>)
800128c: f000 fcf2 bl 8001c74 <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
8001290: bf00 nop
8001292: 3728 adds r7, #40 @ 0x28
8001294: 46bd mov sp, r7
8001296: bd80 pop {r7, pc}
8001298: 40011000 .word 0x40011000
800129c: 40023800 .word 0x40023800
80012a0: 40020000 .word 0x40020000
080012a4 <HAL_FMC_MspInit>:
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
80012a4: b580 push {r7, lr}
80012a6: b086 sub sp, #24
80012a8: af00 add r7, sp, #0
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
80012aa: 1d3b adds r3, r7, #4
80012ac: 2200 movs r2, #0
80012ae: 601a str r2, [r3, #0]
80012b0: 605a str r2, [r3, #4]
80012b2: 609a str r2, [r3, #8]
80012b4: 60da str r2, [r3, #12]
80012b6: 611a str r2, [r3, #16]
if (FMC_Initialized) {
80012b8: 4b3b ldr r3, [pc, #236] @ (80013a8 <HAL_FMC_MspInit+0x104>)
80012ba: 681b ldr r3, [r3, #0]
80012bc: 2b00 cmp r3, #0
80012be: d16f bne.n 80013a0 <HAL_FMC_MspInit+0xfc>
return;
}
FMC_Initialized = 1;
80012c0: 4b39 ldr r3, [pc, #228] @ (80013a8 <HAL_FMC_MspInit+0x104>)
80012c2: 2201 movs r2, #1
80012c4: 601a str r2, [r3, #0]
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
80012c6: 2300 movs r3, #0
80012c8: 603b str r3, [r7, #0]
80012ca: 4b38 ldr r3, [pc, #224] @ (80013ac <HAL_FMC_MspInit+0x108>)
80012cc: 6b9b ldr r3, [r3, #56] @ 0x38
80012ce: 4a37 ldr r2, [pc, #220] @ (80013ac <HAL_FMC_MspInit+0x108>)
80012d0: f043 0301 orr.w r3, r3, #1
80012d4: 6393 str r3, [r2, #56] @ 0x38
80012d6: 4b35 ldr r3, [pc, #212] @ (80013ac <HAL_FMC_MspInit+0x108>)
80012d8: 6b9b ldr r3, [r3, #56] @ 0x38
80012da: f003 0301 and.w r3, r3, #1
80012de: 603b str r3, [r7, #0]
80012e0: 683b ldr r3, [r7, #0]
PB5 ------> FMC_SDCKE1
PB6 ------> FMC_SDNE1
PE0 ------> FMC_NBL0
PE1 ------> FMC_NBL1
*/
GPIO_InitStruct.Pin = A0_Pin|A1_Pin|A2_Pin|A3_Pin
80012e2: f64f 033f movw r3, #63551 @ 0xf83f
80012e6: 607b str r3, [r7, #4]
|A4_Pin|A5_Pin|SDNRAS_Pin|A6_Pin
|A7_Pin|A8_Pin|A9_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80012e8: 2302 movs r3, #2
80012ea: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80012ec: 2300 movs r3, #0
80012ee: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80012f0: 2303 movs r3, #3
80012f2: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
80012f4: 230c movs r3, #12
80012f6: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
80012f8: 1d3b adds r3, r7, #4
80012fa: 4619 mov r1, r3
80012fc: 482c ldr r0, [pc, #176] @ (80013b0 <HAL_FMC_MspInit+0x10c>)
80012fe: f000 fcb9 bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SDNWE_Pin;
8001302: 2301 movs r3, #1
8001304: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001306: 2302 movs r3, #2
8001308: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800130a: 2300 movs r3, #0
800130c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800130e: 2303 movs r3, #3
8001310: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001312: 230c movs r3, #12
8001314: 617b str r3, [r7, #20]
HAL_GPIO_Init(SDNWE_GPIO_Port, &GPIO_InitStruct);
8001316: 1d3b adds r3, r7, #4
8001318: 4619 mov r1, r3
800131a: 4826 ldr r0, [pc, #152] @ (80013b4 <HAL_FMC_MspInit+0x110>)
800131c: f000 fcaa bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = A10_Pin|A11_Pin|BA0_Pin|BA1_Pin
8001320: f248 1333 movw r3, #33075 @ 0x8133
8001324: 607b str r3, [r7, #4]
|SDCLK_Pin|SDNCAS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001326: 2302 movs r3, #2
8001328: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800132a: 2300 movs r3, #0
800132c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800132e: 2303 movs r3, #3
8001330: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001332: 230c movs r3, #12
8001334: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
8001336: 1d3b adds r3, r7, #4
8001338: 4619 mov r1, r3
800133a: 481f ldr r0, [pc, #124] @ (80013b8 <HAL_FMC_MspInit+0x114>)
800133c: f000 fc9a bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = D4_Pin|D5_Pin|D6_Pin|D7_Pin
8001340: f64f 7383 movw r3, #65411 @ 0xff83
8001344: 607b str r3, [r7, #4]
|D8_Pin|D9_Pin|D10_Pin|D11_Pin
|D12_Pin|NBL0_Pin|NBL1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001346: 2302 movs r3, #2
8001348: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800134a: 2300 movs r3, #0
800134c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800134e: 2303 movs r3, #3
8001350: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001352: 230c movs r3, #12
8001354: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
8001356: 1d3b adds r3, r7, #4
8001358: 4619 mov r1, r3
800135a: 4818 ldr r0, [pc, #96] @ (80013bc <HAL_FMC_MspInit+0x118>)
800135c: f000 fc8a bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = D13_Pin|D14_Pin|D15_Pin|D0_Pin
8001360: f24c 7303 movw r3, #50947 @ 0xc703
8001364: 607b str r3, [r7, #4]
|D1_Pin|D2_Pin|D3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001366: 2302 movs r3, #2
8001368: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800136a: 2300 movs r3, #0
800136c: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800136e: 2303 movs r3, #3
8001370: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001372: 230c movs r3, #12
8001374: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
8001376: 1d3b adds r3, r7, #4
8001378: 4619 mov r1, r3
800137a: 4811 ldr r0, [pc, #68] @ (80013c0 <HAL_FMC_MspInit+0x11c>)
800137c: f000 fc7a bl 8001c74 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SDCKE1_Pin|SDNE1_Pin;
8001380: 2360 movs r3, #96 @ 0x60
8001382: 607b str r3, [r7, #4]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001384: 2302 movs r3, #2
8001386: 60bb str r3, [r7, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001388: 2300 movs r3, #0
800138a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800138c: 2303 movs r3, #3
800138e: 613b str r3, [r7, #16]
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
8001390: 230c movs r3, #12
8001392: 617b str r3, [r7, #20]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001394: 1d3b adds r3, r7, #4
8001396: 4619 mov r1, r3
8001398: 480a ldr r0, [pc, #40] @ (80013c4 <HAL_FMC_MspInit+0x120>)
800139a: f000 fc6b bl 8001c74 <HAL_GPIO_Init>
800139e: e000 b.n 80013a2 <HAL_FMC_MspInit+0xfe>
return;
80013a0: bf00 nop
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
80013a2: 3718 adds r7, #24
80013a4: 46bd mov sp, r7
80013a6: bd80 pop {r7, pc}
80013a8: 2000028c .word 0x2000028c
80013ac: 40023800 .word 0x40023800
80013b0: 40021400 .word 0x40021400
80013b4: 40020800 .word 0x40020800
80013b8: 40021800 .word 0x40021800
80013bc: 40021000 .word 0x40021000
80013c0: 40020c00 .word 0x40020c00
80013c4: 40020400 .word 0x40020400
080013c8 <HAL_SDRAM_MspInit>:
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
80013c8: b580 push {r7, lr}
80013ca: b082 sub sp, #8
80013cc: af00 add r7, sp, #0
80013ce: 6078 str r0, [r7, #4]
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
80013d0: f7ff ff68 bl 80012a4 <HAL_FMC_MspInit>
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
80013d4: bf00 nop
80013d6: 3708 adds r7, #8
80013d8: 46bd mov sp, r7
80013da: bd80 pop {r7, pc}
080013dc <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80013dc: b580 push {r7, lr}
80013de: b08e sub sp, #56 @ 0x38
80013e0: af00 add r7, sp, #0
80013e2: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
80013e4: 2300 movs r3, #0
80013e6: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
80013e8: 2300 movs r3, #0
80013ea: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
80013ec: 2300 movs r3, #0
80013ee: 60fb str r3, [r7, #12]
80013f0: 4b33 ldr r3, [pc, #204] @ (80014c0 <HAL_InitTick+0xe4>)
80013f2: 6c1b ldr r3, [r3, #64] @ 0x40
80013f4: 4a32 ldr r2, [pc, #200] @ (80014c0 <HAL_InitTick+0xe4>)
80013f6: f043 0310 orr.w r3, r3, #16
80013fa: 6413 str r3, [r2, #64] @ 0x40
80013fc: 4b30 ldr r3, [pc, #192] @ (80014c0 <HAL_InitTick+0xe4>)
80013fe: 6c1b ldr r3, [r3, #64] @ 0x40
8001400: f003 0310 and.w r3, r3, #16
8001404: 60fb str r3, [r7, #12]
8001406: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001408: f107 0210 add.w r2, r7, #16
800140c: f107 0314 add.w r3, r7, #20
8001410: 4611 mov r1, r2
8001412: 4618 mov r0, r3
8001414: f003 fd1c bl 8004e50 <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
8001418: 6a3b ldr r3, [r7, #32]
800141a: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM6 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
800141c: 6afb ldr r3, [r7, #44] @ 0x2c
800141e: 2b00 cmp r3, #0
8001420: d103 bne.n 800142a <HAL_InitTick+0x4e>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
8001422: f003 fced bl 8004e00 <HAL_RCC_GetPCLK1Freq>
8001426: 6378 str r0, [r7, #52] @ 0x34
8001428: e004 b.n 8001434 <HAL_InitTick+0x58>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
800142a: f003 fce9 bl 8004e00 <HAL_RCC_GetPCLK1Freq>
800142e: 4603 mov r3, r0
8001430: 005b lsls r3, r3, #1
8001432: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8001434: 6b7b ldr r3, [r7, #52] @ 0x34
8001436: 4a23 ldr r2, [pc, #140] @ (80014c4 <HAL_InitTick+0xe8>)
8001438: fba2 2303 umull r2, r3, r2, r3
800143c: 0c9b lsrs r3, r3, #18
800143e: 3b01 subs r3, #1
8001440: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM6 */
htim6.Instance = TIM6;
8001442: 4b21 ldr r3, [pc, #132] @ (80014c8 <HAL_InitTick+0xec>)
8001444: 4a21 ldr r2, [pc, #132] @ (80014cc <HAL_InitTick+0xf0>)
8001446: 601a str r2, [r3, #0]
* Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
* Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
* ClockDivision = 0
* Counter direction = Up
*/
htim6.Init.Period = (1000000U / 1000U) - 1U;
8001448: 4b1f ldr r3, [pc, #124] @ (80014c8 <HAL_InitTick+0xec>)
800144a: f240 32e7 movw r2, #999 @ 0x3e7
800144e: 60da str r2, [r3, #12]
htim6.Init.Prescaler = uwPrescalerValue;
8001450: 4a1d ldr r2, [pc, #116] @ (80014c8 <HAL_InitTick+0xec>)
8001452: 6abb ldr r3, [r7, #40] @ 0x28
8001454: 6053 str r3, [r2, #4]
htim6.Init.ClockDivision = 0;
8001456: 4b1c ldr r3, [pc, #112] @ (80014c8 <HAL_InitTick+0xec>)
8001458: 2200 movs r2, #0
800145a: 611a str r2, [r3, #16]
htim6.Init.CounterMode = TIM_COUNTERMODE_UP;
800145c: 4b1a ldr r3, [pc, #104] @ (80014c8 <HAL_InitTick+0xec>)
800145e: 2200 movs r2, #0
8001460: 609a str r2, [r3, #8]
htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001462: 4b19 ldr r3, [pc, #100] @ (80014c8 <HAL_InitTick+0xec>)
8001464: 2200 movs r2, #0
8001466: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim6);
8001468: 4817 ldr r0, [pc, #92] @ (80014c8 <HAL_InitTick+0xec>)
800146a: f003 ffa0 bl 80053ae <HAL_TIM_Base_Init>
800146e: 4603 mov r3, r0
8001470: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001474: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
8001478: 2b00 cmp r3, #0
800147a: d11b bne.n 80014b4 <HAL_InitTick+0xd8>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim6);
800147c: 4812 ldr r0, [pc, #72] @ (80014c8 <HAL_InitTick+0xec>)
800147e: f003 ffe5 bl 800544c <HAL_TIM_Base_Start_IT>
8001482: 4603 mov r3, r0
8001484: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
8001488: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
800148c: 2b00 cmp r3, #0
800148e: d111 bne.n 80014b4 <HAL_InitTick+0xd8>
{
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
8001490: 2036 movs r0, #54 @ 0x36
8001492: f000 f9d9 bl 8001848 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001496: 687b ldr r3, [r7, #4]
8001498: 2b0f cmp r3, #15
800149a: d808 bhi.n 80014ae <HAL_InitTick+0xd2>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U);
800149c: 2200 movs r2, #0
800149e: 6879 ldr r1, [r7, #4]
80014a0: 2036 movs r0, #54 @ 0x36
80014a2: f000 f9b5 bl 8001810 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80014a6: 4a0a ldr r2, [pc, #40] @ (80014d0 <HAL_InitTick+0xf4>)
80014a8: 687b ldr r3, [r7, #4]
80014aa: 6013 str r3, [r2, #0]
80014ac: e002 b.n 80014b4 <HAL_InitTick+0xd8>
}
else
{
status = HAL_ERROR;
80014ae: 2301 movs r3, #1
80014b0: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
80014b4: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
80014b8: 4618 mov r0, r3
80014ba: 3738 adds r7, #56 @ 0x38
80014bc: 46bd mov sp, r7
80014be: bd80 pop {r7, pc}
80014c0: 40023800 .word 0x40023800
80014c4: 431bde83 .word 0x431bde83
80014c8: 20000290 .word 0x20000290
80014cc: 40001000 .word 0x40001000
80014d0: 20000004 .word 0x20000004
080014d4 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80014d4: b480 push {r7}
80014d6: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80014d8: bf00 nop
80014da: e7fd b.n 80014d8 <NMI_Handler+0x4>
080014dc <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80014dc: b480 push {r7}
80014de: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80014e0: bf00 nop
80014e2: e7fd b.n 80014e0 <HardFault_Handler+0x4>
080014e4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80014e4: b480 push {r7}
80014e6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80014e8: bf00 nop
80014ea: e7fd b.n 80014e8 <MemManage_Handler+0x4>
080014ec <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80014ec: b480 push {r7}
80014ee: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80014f0: bf00 nop
80014f2: e7fd b.n 80014f0 <BusFault_Handler+0x4>
080014f4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80014f4: b480 push {r7}
80014f6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80014f8: bf00 nop
80014fa: e7fd b.n 80014f8 <UsageFault_Handler+0x4>
080014fc <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80014fc: b480 push {r7}
80014fe: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001500: bf00 nop
8001502: 46bd mov sp, r7
8001504: f85d 7b04 ldr.w r7, [sp], #4
8001508: 4770 bx lr
...
0800150c <TIM6_DAC_IRQHandler>:
/**
* @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.
*/
void TIM6_DAC_IRQHandler(void)
{
800150c: b580 push {r7, lr}
800150e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM6_DAC_IRQn 0 */
/* USER CODE END TIM6_DAC_IRQn 0 */
HAL_TIM_IRQHandler(&htim6);
8001510: 4802 ldr r0, [pc, #8] @ (800151c <TIM6_DAC_IRQHandler+0x10>)
8001512: f004 f80b bl 800552c <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM6_DAC_IRQn 1 */
/* USER CODE END TIM6_DAC_IRQn 1 */
}
8001516: bf00 nop
8001518: bd80 pop {r7, pc}
800151a: bf00 nop
800151c: 20000290 .word 0x20000290
08001520 <OTG_HS_IRQHandler>:
/**
* @brief This function handles USB On The Go HS global interrupt.
*/
void OTG_HS_IRQHandler(void)
{
8001520: b580 push {r7, lr}
8001522: af00 add r7, sp, #0
/* USER CODE BEGIN OTG_HS_IRQn 0 */
/* USER CODE END OTG_HS_IRQn 0 */
HAL_HCD_IRQHandler(&hhcd_USB_OTG_HS);
8001524: 4802 ldr r0, [pc, #8] @ (8001530 <OTG_HS_IRQHandler+0x10>)
8001526: f000 fd84 bl 8002032 <HAL_HCD_IRQHandler>
/* USER CODE BEGIN OTG_HS_IRQn 1 */
/* USER CODE END OTG_HS_IRQn 1 */
}
800152a: bf00 nop
800152c: bd80 pop {r7, pc}
800152e: bf00 nop
8001530: 200003c8 .word 0x200003c8
08001534 <LTDC_IRQHandler>:
/**
* @brief This function handles LTDC global interrupt.
*/
void LTDC_IRQHandler(void)
{
8001534: b580 push {r7, lr}
8001536: af00 add r7, sp, #0
/* USER CODE BEGIN LTDC_IRQn 0 */
/* USER CODE END LTDC_IRQn 0 */
HAL_LTDC_IRQHandler(&hltdc);
8001538: 4802 ldr r0, [pc, #8] @ (8001544 <LTDC_IRQHandler+0x10>)
800153a: f002 fd7d bl 8004038 <HAL_LTDC_IRQHandler>
/* USER CODE BEGIN LTDC_IRQn 1 */
/* USER CODE END LTDC_IRQn 1 */
}
800153e: bf00 nop
8001540: bd80 pop {r7, pc}
8001542: bf00 nop
8001544: 200000c8 .word 0x200000c8
08001548 <DMA2D_IRQHandler>:
/**
* @brief This function handles DMA2D global interrupt.
*/
void DMA2D_IRQHandler(void)
{
8001548: b580 push {r7, lr}
800154a: af00 add r7, sp, #0
/* USER CODE BEGIN DMA2D_IRQn 0 */
/* USER CODE END DMA2D_IRQn 0 */
HAL_DMA2D_IRQHandler(&hdma2d);
800154c: 4802 ldr r0, [pc, #8] @ (8001558 <DMA2D_IRQHandler+0x10>)
800154e: f000 f9ee bl 800192e <HAL_DMA2D_IRQHandler>
/* USER CODE BEGIN DMA2D_IRQn 1 */
/* USER CODE END DMA2D_IRQn 1 */
}
8001552: bf00 nop
8001554: bd80 pop {r7, pc}
8001556: bf00 nop
8001558: 20000034 .word 0x20000034
0800155c <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
800155c: b480 push {r7}
800155e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001560: 4b06 ldr r3, [pc, #24] @ (800157c <SystemInit+0x20>)
8001562: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8001566: 4a05 ldr r2, [pc, #20] @ (800157c <SystemInit+0x20>)
8001568: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
800156c: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001570: bf00 nop
8001572: 46bd mov sp, r7
8001574: f85d 7b04 ldr.w r7, [sp], #4
8001578: 4770 bx lr
800157a: bf00 nop
800157c: e000ed00 .word 0xe000ed00
08001580 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001580: f8df d034 ldr.w sp, [pc, #52] @ 80015b8 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001584: f7ff ffea bl 800155c <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001588: 480c ldr r0, [pc, #48] @ (80015bc <LoopFillZerobss+0x12>)
ldr r1, =_edata
800158a: 490d ldr r1, [pc, #52] @ (80015c0 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
800158c: 4a0d ldr r2, [pc, #52] @ (80015c4 <LoopFillZerobss+0x1a>)
movs r3, #0
800158e: 2300 movs r3, #0
b LoopCopyDataInit
8001590: e002 b.n 8001598 <LoopCopyDataInit>
08001592 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001592: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001594: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001596: 3304 adds r3, #4
08001598 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001598: 18c4 adds r4, r0, r3
cmp r4, r1
800159a: 428c cmp r4, r1
bcc CopyDataInit
800159c: d3f9 bcc.n 8001592 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800159e: 4a0a ldr r2, [pc, #40] @ (80015c8 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
80015a0: 4c0a ldr r4, [pc, #40] @ (80015cc <LoopFillZerobss+0x22>)
movs r3, #0
80015a2: 2300 movs r3, #0
b LoopFillZerobss
80015a4: e001 b.n 80015aa <LoopFillZerobss>
080015a6 <FillZerobss>:
FillZerobss:
str r3, [r2]
80015a6: 6013 str r3, [r2, #0]
adds r2, r2, #4
80015a8: 3204 adds r2, #4
080015aa <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80015aa: 42a2 cmp r2, r4
bcc FillZerobss
80015ac: d3fb bcc.n 80015a6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80015ae: f006 fc77 bl 8007ea0 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80015b2: f7fe ffec bl 800058e <main>
bx lr
80015b6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
80015b8: 20030000 .word 0x20030000
ldr r0, =_sdata
80015bc: 20000000 .word 0x20000000
ldr r1, =_edata
80015c0: 20000010 .word 0x20000010
ldr r2, =_sidata
80015c4: 08007f44 .word 0x08007f44
ldr r2, =_sbss
80015c8: 20000010 .word 0x20000010
ldr r4, =_ebss
80015cc: 200007a8 .word 0x200007a8
080015d0 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80015d0: e7fe b.n 80015d0 <ADC_IRQHandler>
...
080015d4 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80015d4: b580 push {r7, lr}
80015d6: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
80015d8: 4b0e ldr r3, [pc, #56] @ (8001614 <HAL_Init+0x40>)
80015da: 681b ldr r3, [r3, #0]
80015dc: 4a0d ldr r2, [pc, #52] @ (8001614 <HAL_Init+0x40>)
80015de: f443 7300 orr.w r3, r3, #512 @ 0x200
80015e2: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
80015e4: 4b0b ldr r3, [pc, #44] @ (8001614 <HAL_Init+0x40>)
80015e6: 681b ldr r3, [r3, #0]
80015e8: 4a0a ldr r2, [pc, #40] @ (8001614 <HAL_Init+0x40>)
80015ea: f443 6380 orr.w r3, r3, #1024 @ 0x400
80015ee: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80015f0: 4b08 ldr r3, [pc, #32] @ (8001614 <HAL_Init+0x40>)
80015f2: 681b ldr r3, [r3, #0]
80015f4: 4a07 ldr r2, [pc, #28] @ (8001614 <HAL_Init+0x40>)
80015f6: f443 7380 orr.w r3, r3, #256 @ 0x100
80015fa: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80015fc: 2003 movs r0, #3
80015fe: f000 f8fc bl 80017fa <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001602: 2000 movs r0, #0
8001604: f7ff feea bl 80013dc <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001608: f7ff fb8a bl 8000d20 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800160c: 2300 movs r3, #0
}
800160e: 4618 mov r0, r3
8001610: bd80 pop {r7, pc}
8001612: bf00 nop
8001614: 40023c00 .word 0x40023c00
08001618 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001618: b480 push {r7}
800161a: af00 add r7, sp, #0
uwTick += uwTickFreq;
800161c: 4b06 ldr r3, [pc, #24] @ (8001638 <HAL_IncTick+0x20>)
800161e: 781b ldrb r3, [r3, #0]
8001620: 461a mov r2, r3
8001622: 4b06 ldr r3, [pc, #24] @ (800163c <HAL_IncTick+0x24>)
8001624: 681b ldr r3, [r3, #0]
8001626: 4413 add r3, r2
8001628: 4a04 ldr r2, [pc, #16] @ (800163c <HAL_IncTick+0x24>)
800162a: 6013 str r3, [r2, #0]
}
800162c: bf00 nop
800162e: 46bd mov sp, r7
8001630: f85d 7b04 ldr.w r7, [sp], #4
8001634: 4770 bx lr
8001636: bf00 nop
8001638: 20000008 .word 0x20000008
800163c: 200002d8 .word 0x200002d8
08001640 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001640: b480 push {r7}
8001642: af00 add r7, sp, #0
return uwTick;
8001644: 4b03 ldr r3, [pc, #12] @ (8001654 <HAL_GetTick+0x14>)
8001646: 681b ldr r3, [r3, #0]
}
8001648: 4618 mov r0, r3
800164a: 46bd mov sp, r7
800164c: f85d 7b04 ldr.w r7, [sp], #4
8001650: 4770 bx lr
8001652: bf00 nop
8001654: 200002d8 .word 0x200002d8
08001658 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001658: b580 push {r7, lr}
800165a: b084 sub sp, #16
800165c: af00 add r7, sp, #0
800165e: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001660: f7ff ffee bl 8001640 <HAL_GetTick>
8001664: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001666: 687b ldr r3, [r7, #4]
8001668: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
800166a: 68fb ldr r3, [r7, #12]
800166c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8001670: d005 beq.n 800167e <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001672: 4b0a ldr r3, [pc, #40] @ (800169c <HAL_Delay+0x44>)
8001674: 781b ldrb r3, [r3, #0]
8001676: 461a mov r2, r3
8001678: 68fb ldr r3, [r7, #12]
800167a: 4413 add r3, r2
800167c: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
800167e: bf00 nop
8001680: f7ff ffde bl 8001640 <HAL_GetTick>
8001684: 4602 mov r2, r0
8001686: 68bb ldr r3, [r7, #8]
8001688: 1ad3 subs r3, r2, r3
800168a: 68fa ldr r2, [r7, #12]
800168c: 429a cmp r2, r3
800168e: d8f7 bhi.n 8001680 <HAL_Delay+0x28>
{
}
}
8001690: bf00 nop
8001692: bf00 nop
8001694: 3710 adds r7, #16
8001696: 46bd mov sp, r7
8001698: bd80 pop {r7, pc}
800169a: bf00 nop
800169c: 20000008 .word 0x20000008
080016a0 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80016a0: b480 push {r7}
80016a2: b085 sub sp, #20
80016a4: af00 add r7, sp, #0
80016a6: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80016a8: 687b ldr r3, [r7, #4]
80016aa: f003 0307 and.w r3, r3, #7
80016ae: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
80016b0: 4b0c ldr r3, [pc, #48] @ (80016e4 <__NVIC_SetPriorityGrouping+0x44>)
80016b2: 68db ldr r3, [r3, #12]
80016b4: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
80016b6: 68ba ldr r2, [r7, #8]
80016b8: f64f 03ff movw r3, #63743 @ 0xf8ff
80016bc: 4013 ands r3, r2
80016be: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
80016c0: 68fb ldr r3, [r7, #12]
80016c2: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
80016c4: 68bb ldr r3, [r7, #8]
80016c6: 4313 orrs r3, r2
reg_value = (reg_value |
80016c8: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
80016cc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80016d0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
80016d2: 4a04 ldr r2, [pc, #16] @ (80016e4 <__NVIC_SetPriorityGrouping+0x44>)
80016d4: 68bb ldr r3, [r7, #8]
80016d6: 60d3 str r3, [r2, #12]
}
80016d8: bf00 nop
80016da: 3714 adds r7, #20
80016dc: 46bd mov sp, r7
80016de: f85d 7b04 ldr.w r7, [sp], #4
80016e2: 4770 bx lr
80016e4: e000ed00 .word 0xe000ed00
080016e8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
80016e8: b480 push {r7}
80016ea: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80016ec: 4b04 ldr r3, [pc, #16] @ (8001700 <__NVIC_GetPriorityGrouping+0x18>)
80016ee: 68db ldr r3, [r3, #12]
80016f0: 0a1b lsrs r3, r3, #8
80016f2: f003 0307 and.w r3, r3, #7
}
80016f6: 4618 mov r0, r3
80016f8: 46bd mov sp, r7
80016fa: f85d 7b04 ldr.w r7, [sp], #4
80016fe: 4770 bx lr
8001700: e000ed00 .word 0xe000ed00
08001704 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001704: b480 push {r7}
8001706: b083 sub sp, #12
8001708: af00 add r7, sp, #0
800170a: 4603 mov r3, r0
800170c: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800170e: f997 3007 ldrsb.w r3, [r7, #7]
8001712: 2b00 cmp r3, #0
8001714: db0b blt.n 800172e <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8001716: 79fb ldrb r3, [r7, #7]
8001718: f003 021f and.w r2, r3, #31
800171c: 4907 ldr r1, [pc, #28] @ (800173c <__NVIC_EnableIRQ+0x38>)
800171e: f997 3007 ldrsb.w r3, [r7, #7]
8001722: 095b lsrs r3, r3, #5
8001724: 2001 movs r0, #1
8001726: fa00 f202 lsl.w r2, r0, r2
800172a: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
800172e: bf00 nop
8001730: 370c adds r7, #12
8001732: 46bd mov sp, r7
8001734: f85d 7b04 ldr.w r7, [sp], #4
8001738: 4770 bx lr
800173a: bf00 nop
800173c: e000e100 .word 0xe000e100
08001740 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8001740: b480 push {r7}
8001742: b083 sub sp, #12
8001744: af00 add r7, sp, #0
8001746: 4603 mov r3, r0
8001748: 6039 str r1, [r7, #0]
800174a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
800174c: f997 3007 ldrsb.w r3, [r7, #7]
8001750: 2b00 cmp r3, #0
8001752: db0a blt.n 800176a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001754: 683b ldr r3, [r7, #0]
8001756: b2da uxtb r2, r3
8001758: 490c ldr r1, [pc, #48] @ (800178c <__NVIC_SetPriority+0x4c>)
800175a: f997 3007 ldrsb.w r3, [r7, #7]
800175e: 0112 lsls r2, r2, #4
8001760: b2d2 uxtb r2, r2
8001762: 440b add r3, r1
8001764: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001768: e00a b.n 8001780 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800176a: 683b ldr r3, [r7, #0]
800176c: b2da uxtb r2, r3
800176e: 4908 ldr r1, [pc, #32] @ (8001790 <__NVIC_SetPriority+0x50>)
8001770: 79fb ldrb r3, [r7, #7]
8001772: f003 030f and.w r3, r3, #15
8001776: 3b04 subs r3, #4
8001778: 0112 lsls r2, r2, #4
800177a: b2d2 uxtb r2, r2
800177c: 440b add r3, r1
800177e: 761a strb r2, [r3, #24]
}
8001780: bf00 nop
8001782: 370c adds r7, #12
8001784: 46bd mov sp, r7
8001786: f85d 7b04 ldr.w r7, [sp], #4
800178a: 4770 bx lr
800178c: e000e100 .word 0xe000e100
8001790: e000ed00 .word 0xe000ed00
08001794 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001794: b480 push {r7}
8001796: b089 sub sp, #36 @ 0x24
8001798: af00 add r7, sp, #0
800179a: 60f8 str r0, [r7, #12]
800179c: 60b9 str r1, [r7, #8]
800179e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80017a0: 68fb ldr r3, [r7, #12]
80017a2: f003 0307 and.w r3, r3, #7
80017a6: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80017a8: 69fb ldr r3, [r7, #28]
80017aa: f1c3 0307 rsb r3, r3, #7
80017ae: 2b04 cmp r3, #4
80017b0: bf28 it cs
80017b2: 2304 movcs r3, #4
80017b4: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80017b6: 69fb ldr r3, [r7, #28]
80017b8: 3304 adds r3, #4
80017ba: 2b06 cmp r3, #6
80017bc: d902 bls.n 80017c4 <NVIC_EncodePriority+0x30>
80017be: 69fb ldr r3, [r7, #28]
80017c0: 3b03 subs r3, #3
80017c2: e000 b.n 80017c6 <NVIC_EncodePriority+0x32>
80017c4: 2300 movs r3, #0
80017c6: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80017c8: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80017cc: 69bb ldr r3, [r7, #24]
80017ce: fa02 f303 lsl.w r3, r2, r3
80017d2: 43da mvns r2, r3
80017d4: 68bb ldr r3, [r7, #8]
80017d6: 401a ands r2, r3
80017d8: 697b ldr r3, [r7, #20]
80017da: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80017dc: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
80017e0: 697b ldr r3, [r7, #20]
80017e2: fa01 f303 lsl.w r3, r1, r3
80017e6: 43d9 mvns r1, r3
80017e8: 687b ldr r3, [r7, #4]
80017ea: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80017ec: 4313 orrs r3, r2
);
}
80017ee: 4618 mov r0, r3
80017f0: 3724 adds r7, #36 @ 0x24
80017f2: 46bd mov sp, r7
80017f4: f85d 7b04 ldr.w r7, [sp], #4
80017f8: 4770 bx lr
080017fa <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80017fa: b580 push {r7, lr}
80017fc: b082 sub sp, #8
80017fe: af00 add r7, sp, #0
8001800: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8001802: 6878 ldr r0, [r7, #4]
8001804: f7ff ff4c bl 80016a0 <__NVIC_SetPriorityGrouping>
}
8001808: bf00 nop
800180a: 3708 adds r7, #8
800180c: 46bd mov sp, r7
800180e: bd80 pop {r7, pc}
08001810 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001810: b580 push {r7, lr}
8001812: b086 sub sp, #24
8001814: af00 add r7, sp, #0
8001816: 4603 mov r3, r0
8001818: 60b9 str r1, [r7, #8]
800181a: 607a str r2, [r7, #4]
800181c: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
800181e: 2300 movs r3, #0
8001820: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001822: f7ff ff61 bl 80016e8 <__NVIC_GetPriorityGrouping>
8001826: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001828: 687a ldr r2, [r7, #4]
800182a: 68b9 ldr r1, [r7, #8]
800182c: 6978 ldr r0, [r7, #20]
800182e: f7ff ffb1 bl 8001794 <NVIC_EncodePriority>
8001832: 4602 mov r2, r0
8001834: f997 300f ldrsb.w r3, [r7, #15]
8001838: 4611 mov r1, r2
800183a: 4618 mov r0, r3
800183c: f7ff ff80 bl 8001740 <__NVIC_SetPriority>
}
8001840: bf00 nop
8001842: 3718 adds r7, #24
8001844: 46bd mov sp, r7
8001846: bd80 pop {r7, pc}
08001848 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001848: b580 push {r7, lr}
800184a: b082 sub sp, #8
800184c: af00 add r7, sp, #0
800184e: 4603 mov r3, r0
8001850: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001852: f997 3007 ldrsb.w r3, [r7, #7]
8001856: 4618 mov r0, r3
8001858: f7ff ff54 bl 8001704 <__NVIC_EnableIRQ>
}
800185c: bf00 nop
800185e: 3708 adds r7, #8
8001860: 46bd mov sp, r7
8001862: bd80 pop {r7, pc}
08001864 <HAL_CRC_Init>:
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
8001864: b580 push {r7, lr}
8001866: b082 sub sp, #8
8001868: af00 add r7, sp, #0
800186a: 6078 str r0, [r7, #4]
/* Check the CRC handle allocation */
if (hcrc == NULL)
800186c: 687b ldr r3, [r7, #4]
800186e: 2b00 cmp r3, #0
8001870: d101 bne.n 8001876 <HAL_CRC_Init+0x12>
{
return HAL_ERROR;
8001872: 2301 movs r3, #1
8001874: e00e b.n 8001894 <HAL_CRC_Init+0x30>
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if (hcrc->State == HAL_CRC_STATE_RESET)
8001876: 687b ldr r3, [r7, #4]
8001878: 795b ldrb r3, [r3, #5]
800187a: b2db uxtb r3, r3
800187c: 2b00 cmp r3, #0
800187e: d105 bne.n 800188c <HAL_CRC_Init+0x28>
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
8001880: 687b ldr r3, [r7, #4]
8001882: 2200 movs r2, #0
8001884: 711a strb r2, [r3, #4]
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
8001886: 6878 ldr r0, [r7, #4]
8001888: f7ff fa76 bl 8000d78 <HAL_CRC_MspInit>
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
800188c: 687b ldr r3, [r7, #4]
800188e: 2201 movs r2, #1
8001890: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
8001892: 2300 movs r3, #0
}
8001894: 4618 mov r0, r3
8001896: 3708 adds r7, #8
8001898: 46bd mov sp, r7
800189a: bd80 pop {r7, pc}
0800189c <HAL_DMA2D_Init>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
{
800189c: b580 push {r7, lr}
800189e: b082 sub sp, #8
80018a0: af00 add r7, sp, #0
80018a2: 6078 str r0, [r7, #4]
/* Check the DMA2D peripheral state */
if (hdma2d == NULL)
80018a4: 687b ldr r3, [r7, #4]
80018a6: 2b00 cmp r3, #0
80018a8: d101 bne.n 80018ae <HAL_DMA2D_Init+0x12>
{
return HAL_ERROR;
80018aa: 2301 movs r3, #1
80018ac: e03b b.n 8001926 <HAL_DMA2D_Init+0x8a>
/* Init the low level hardware */
hdma2d->MspInitCallback(hdma2d);
}
#else
if (hdma2d->State == HAL_DMA2D_STATE_RESET)
80018ae: 687b ldr r3, [r7, #4]
80018b0: f893 3039 ldrb.w r3, [r3, #57] @ 0x39
80018b4: b2db uxtb r3, r3
80018b6: 2b00 cmp r3, #0
80018b8: d106 bne.n 80018c8 <HAL_DMA2D_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hdma2d->Lock = HAL_UNLOCKED;
80018ba: 687b ldr r3, [r7, #4]
80018bc: 2200 movs r2, #0
80018be: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Init the low level hardware */
HAL_DMA2D_MspInit(hdma2d);
80018c2: 6878 ldr r0, [r7, #4]
80018c4: f7ff fa7a bl 8000dbc <HAL_DMA2D_MspInit>
}
#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
80018c8: 687b ldr r3, [r7, #4]
80018ca: 2202 movs r2, #2
80018cc: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* DMA2D CR register configuration -------------------------------------------*/
MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
80018d0: 687b ldr r3, [r7, #4]
80018d2: 681b ldr r3, [r3, #0]
80018d4: 681b ldr r3, [r3, #0]
80018d6: f423 3140 bic.w r1, r3, #196608 @ 0x30000
80018da: 687b ldr r3, [r7, #4]
80018dc: 685a ldr r2, [r3, #4]
80018de: 687b ldr r3, [r7, #4]
80018e0: 681b ldr r3, [r3, #0]
80018e2: 430a orrs r2, r1
80018e4: 601a str r2, [r3, #0]
/* DMA2D OPFCCR register configuration ---------------------------------------*/
MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
80018e6: 687b ldr r3, [r7, #4]
80018e8: 681b ldr r3, [r3, #0]
80018ea: 6b5b ldr r3, [r3, #52] @ 0x34
80018ec: f023 0107 bic.w r1, r3, #7
80018f0: 687b ldr r3, [r7, #4]
80018f2: 689a ldr r2, [r3, #8]
80018f4: 687b ldr r3, [r7, #4]
80018f6: 681b ldr r3, [r3, #0]
80018f8: 430a orrs r2, r1
80018fa: 635a str r2, [r3, #52] @ 0x34
/* DMA2D OOR register configuration ------------------------------------------*/
MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
80018fc: 687b ldr r3, [r7, #4]
80018fe: 681b ldr r3, [r3, #0]
8001900: 6c1b ldr r3, [r3, #64] @ 0x40
8001902: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8001906: f023 033f bic.w r3, r3, #63 @ 0x3f
800190a: 687a ldr r2, [r7, #4]
800190c: 68d1 ldr r1, [r2, #12]
800190e: 687a ldr r2, [r7, #4]
8001910: 6812 ldr r2, [r2, #0]
8001912: 430b orrs r3, r1
8001914: 6413 str r3, [r2, #64] @ 0x40
/* Update error code */
hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
8001916: 687b ldr r3, [r7, #4]
8001918: 2200 movs r2, #0
800191a: 63da str r2, [r3, #60] @ 0x3c
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
800191c: 687b ldr r3, [r7, #4]
800191e: 2201 movs r2, #1
8001920: f883 2039 strb.w r2, [r3, #57] @ 0x39
return HAL_OK;
8001924: 2300 movs r3, #0
}
8001926: 4618 mov r0, r3
8001928: 3708 adds r7, #8
800192a: 46bd mov sp, r7
800192c: bd80 pop {r7, pc}
0800192e <HAL_DMA2D_IRQHandler>:
* @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
{
800192e: b580 push {r7, lr}
8001930: b084 sub sp, #16
8001932: af00 add r7, sp, #0
8001934: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
8001936: 687b ldr r3, [r7, #4]
8001938: 681b ldr r3, [r3, #0]
800193a: 685b ldr r3, [r3, #4]
800193c: 60fb str r3, [r7, #12]
uint32_t crflags = READ_REG(hdma2d->Instance->CR);
800193e: 687b ldr r3, [r7, #4]
8001940: 681b ldr r3, [r3, #0]
8001942: 681b ldr r3, [r3, #0]
8001944: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if ((isrflags & DMA2D_FLAG_TE) != 0U)
8001946: 68fb ldr r3, [r7, #12]
8001948: f003 0301 and.w r3, r3, #1
800194c: 2b00 cmp r3, #0
800194e: d026 beq.n 800199e <HAL_DMA2D_IRQHandler+0x70>
{
if ((crflags & DMA2D_IT_TE) != 0U)
8001950: 68bb ldr r3, [r7, #8]
8001952: f403 7380 and.w r3, r3, #256 @ 0x100
8001956: 2b00 cmp r3, #0
8001958: d021 beq.n 800199e <HAL_DMA2D_IRQHandler+0x70>
{
/* Disable the transfer Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
800195a: 687b ldr r3, [r7, #4]
800195c: 681b ldr r3, [r3, #0]
800195e: 681a ldr r2, [r3, #0]
8001960: 687b ldr r3, [r7, #4]
8001962: 681b ldr r3, [r3, #0]
8001964: f422 7280 bic.w r2, r2, #256 @ 0x100
8001968: 601a str r2, [r3, #0]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
800196a: 687b ldr r3, [r7, #4]
800196c: 6bdb ldr r3, [r3, #60] @ 0x3c
800196e: f043 0201 orr.w r2, r3, #1
8001972: 687b ldr r3, [r7, #4]
8001974: 63da str r2, [r3, #60] @ 0x3c
/* Clear the transfer error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
8001976: 687b ldr r3, [r7, #4]
8001978: 681b ldr r3, [r3, #0]
800197a: 2201 movs r2, #1
800197c: 609a str r2, [r3, #8]
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
800197e: 687b ldr r3, [r7, #4]
8001980: 2204 movs r2, #4
8001982: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001986: 687b ldr r3, [r7, #4]
8001988: 2200 movs r2, #0
800198a: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (hdma2d->XferErrorCallback != NULL)
800198e: 687b ldr r3, [r7, #4]
8001990: 695b ldr r3, [r3, #20]
8001992: 2b00 cmp r3, #0
8001994: d003 beq.n 800199e <HAL_DMA2D_IRQHandler+0x70>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
8001996: 687b ldr r3, [r7, #4]
8001998: 695b ldr r3, [r3, #20]
800199a: 6878 ldr r0, [r7, #4]
800199c: 4798 blx r3
}
}
}
/* Configuration Error Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_CE) != 0U)
800199e: 68fb ldr r3, [r7, #12]
80019a0: f003 0320 and.w r3, r3, #32
80019a4: 2b00 cmp r3, #0
80019a6: d026 beq.n 80019f6 <HAL_DMA2D_IRQHandler+0xc8>
{
if ((crflags & DMA2D_IT_CE) != 0U)
80019a8: 68bb ldr r3, [r7, #8]
80019aa: f403 5300 and.w r3, r3, #8192 @ 0x2000
80019ae: 2b00 cmp r3, #0
80019b0: d021 beq.n 80019f6 <HAL_DMA2D_IRQHandler+0xc8>
{
/* Disable the Configuration Error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
80019b2: 687b ldr r3, [r7, #4]
80019b4: 681b ldr r3, [r3, #0]
80019b6: 681a ldr r2, [r3, #0]
80019b8: 687b ldr r3, [r7, #4]
80019ba: 681b ldr r3, [r3, #0]
80019bc: f422 5200 bic.w r2, r2, #8192 @ 0x2000
80019c0: 601a str r2, [r3, #0]
/* Clear the Configuration error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
80019c2: 687b ldr r3, [r7, #4]
80019c4: 681b ldr r3, [r3, #0]
80019c6: 2220 movs r2, #32
80019c8: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
80019ca: 687b ldr r3, [r7, #4]
80019cc: 6bdb ldr r3, [r3, #60] @ 0x3c
80019ce: f043 0202 orr.w r2, r3, #2
80019d2: 687b ldr r3, [r7, #4]
80019d4: 63da str r2, [r3, #60] @ 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
80019d6: 687b ldr r3, [r7, #4]
80019d8: 2204 movs r2, #4
80019da: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
80019de: 687b ldr r3, [r7, #4]
80019e0: 2200 movs r2, #0
80019e2: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (hdma2d->XferErrorCallback != NULL)
80019e6: 687b ldr r3, [r7, #4]
80019e8: 695b ldr r3, [r3, #20]
80019ea: 2b00 cmp r3, #0
80019ec: d003 beq.n 80019f6 <HAL_DMA2D_IRQHandler+0xc8>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
80019ee: 687b ldr r3, [r7, #4]
80019f0: 695b ldr r3, [r3, #20]
80019f2: 6878 ldr r0, [r7, #4]
80019f4: 4798 blx r3
}
}
}
/* CLUT access Error Interrupt management ***********************************/
if ((isrflags & DMA2D_FLAG_CAE) != 0U)
80019f6: 68fb ldr r3, [r7, #12]
80019f8: f003 0308 and.w r3, r3, #8
80019fc: 2b00 cmp r3, #0
80019fe: d026 beq.n 8001a4e <HAL_DMA2D_IRQHandler+0x120>
{
if ((crflags & DMA2D_IT_CAE) != 0U)
8001a00: 68bb ldr r3, [r7, #8]
8001a02: f403 6300 and.w r3, r3, #2048 @ 0x800
8001a06: 2b00 cmp r3, #0
8001a08: d021 beq.n 8001a4e <HAL_DMA2D_IRQHandler+0x120>
{
/* Disable the CLUT access error interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
8001a0a: 687b ldr r3, [r7, #4]
8001a0c: 681b ldr r3, [r3, #0]
8001a0e: 681a ldr r2, [r3, #0]
8001a10: 687b ldr r3, [r7, #4]
8001a12: 681b ldr r3, [r3, #0]
8001a14: f422 6200 bic.w r2, r2, #2048 @ 0x800
8001a18: 601a str r2, [r3, #0]
/* Clear the CLUT access error flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 681b ldr r3, [r3, #0]
8001a1e: 2208 movs r2, #8
8001a20: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
8001a22: 687b ldr r3, [r7, #4]
8001a24: 6bdb ldr r3, [r3, #60] @ 0x3c
8001a26: f043 0204 orr.w r2, r3, #4
8001a2a: 687b ldr r3, [r7, #4]
8001a2c: 63da str r2, [r3, #60] @ 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_ERROR;
8001a2e: 687b ldr r3, [r7, #4]
8001a30: 2204 movs r2, #4
8001a32: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001a36: 687b ldr r3, [r7, #4]
8001a38: 2200 movs r2, #0
8001a3a: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (hdma2d->XferErrorCallback != NULL)
8001a3e: 687b ldr r3, [r7, #4]
8001a40: 695b ldr r3, [r3, #20]
8001a42: 2b00 cmp r3, #0
8001a44: d003 beq.n 8001a4e <HAL_DMA2D_IRQHandler+0x120>
{
/* Transfer error Callback */
hdma2d->XferErrorCallback(hdma2d);
8001a46: 687b ldr r3, [r7, #4]
8001a48: 695b ldr r3, [r3, #20]
8001a4a: 6878 ldr r0, [r7, #4]
8001a4c: 4798 blx r3
}
}
}
/* Transfer watermark Interrupt management **********************************/
if ((isrflags & DMA2D_FLAG_TW) != 0U)
8001a4e: 68fb ldr r3, [r7, #12]
8001a50: f003 0304 and.w r3, r3, #4
8001a54: 2b00 cmp r3, #0
8001a56: d013 beq.n 8001a80 <HAL_DMA2D_IRQHandler+0x152>
{
if ((crflags & DMA2D_IT_TW) != 0U)
8001a58: 68bb ldr r3, [r7, #8]
8001a5a: f403 6380 and.w r3, r3, #1024 @ 0x400
8001a5e: 2b00 cmp r3, #0
8001a60: d00e beq.n 8001a80 <HAL_DMA2D_IRQHandler+0x152>
{
/* Disable the transfer watermark interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
8001a62: 687b ldr r3, [r7, #4]
8001a64: 681b ldr r3, [r3, #0]
8001a66: 681a ldr r2, [r3, #0]
8001a68: 687b ldr r3, [r7, #4]
8001a6a: 681b ldr r3, [r3, #0]
8001a6c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8001a70: 601a str r2, [r3, #0]
/* Clear the transfer watermark flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
8001a72: 687b ldr r3, [r7, #4]
8001a74: 681b ldr r3, [r3, #0]
8001a76: 2204 movs r2, #4
8001a78: 609a str r2, [r3, #8]
/* Transfer watermark Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->LineEventCallback(hdma2d);
#else
HAL_DMA2D_LineEventCallback(hdma2d);
8001a7a: 6878 ldr r0, [r7, #4]
8001a7c: f000 f853 bl 8001b26 <HAL_DMA2D_LineEventCallback>
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
/* Transfer Complete Interrupt management ************************************/
if ((isrflags & DMA2D_FLAG_TC) != 0U)
8001a80: 68fb ldr r3, [r7, #12]
8001a82: f003 0302 and.w r3, r3, #2
8001a86: 2b00 cmp r3, #0
8001a88: d024 beq.n 8001ad4 <HAL_DMA2D_IRQHandler+0x1a6>
{
if ((crflags & DMA2D_IT_TC) != 0U)
8001a8a: 68bb ldr r3, [r7, #8]
8001a8c: f403 7300 and.w r3, r3, #512 @ 0x200
8001a90: 2b00 cmp r3, #0
8001a92: d01f beq.n 8001ad4 <HAL_DMA2D_IRQHandler+0x1a6>
{
/* Disable the transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
8001a94: 687b ldr r3, [r7, #4]
8001a96: 681b ldr r3, [r3, #0]
8001a98: 681a ldr r2, [r3, #0]
8001a9a: 687b ldr r3, [r7, #4]
8001a9c: 681b ldr r3, [r3, #0]
8001a9e: f422 7200 bic.w r2, r2, #512 @ 0x200
8001aa2: 601a str r2, [r3, #0]
/* Clear the transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
8001aa4: 687b ldr r3, [r7, #4]
8001aa6: 681b ldr r3, [r3, #0]
8001aa8: 2202 movs r2, #2
8001aaa: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
8001aac: 687b ldr r3, [r7, #4]
8001aae: 6bda ldr r2, [r3, #60] @ 0x3c
8001ab0: 687b ldr r3, [r7, #4]
8001ab2: 63da str r2, [r3, #60] @ 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8001ab4: 687b ldr r3, [r7, #4]
8001ab6: 2201 movs r2, #1
8001ab8: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001abc: 687b ldr r3, [r7, #4]
8001abe: 2200 movs r2, #0
8001ac0: f883 2038 strb.w r2, [r3, #56] @ 0x38
if (hdma2d->XferCpltCallback != NULL)
8001ac4: 687b ldr r3, [r7, #4]
8001ac6: 691b ldr r3, [r3, #16]
8001ac8: 2b00 cmp r3, #0
8001aca: d003 beq.n 8001ad4 <HAL_DMA2D_IRQHandler+0x1a6>
{
/* Transfer complete Callback */
hdma2d->XferCpltCallback(hdma2d);
8001acc: 687b ldr r3, [r7, #4]
8001ace: 691b ldr r3, [r3, #16]
8001ad0: 6878 ldr r0, [r7, #4]
8001ad2: 4798 blx r3
}
}
}
/* CLUT Transfer Complete Interrupt management ******************************/
if ((isrflags & DMA2D_FLAG_CTC) != 0U)
8001ad4: 68fb ldr r3, [r7, #12]
8001ad6: f003 0310 and.w r3, r3, #16
8001ada: 2b00 cmp r3, #0
8001adc: d01f beq.n 8001b1e <HAL_DMA2D_IRQHandler+0x1f0>
{
if ((crflags & DMA2D_IT_CTC) != 0U)
8001ade: 68bb ldr r3, [r7, #8]
8001ae0: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001ae4: 2b00 cmp r3, #0
8001ae6: d01a beq.n 8001b1e <HAL_DMA2D_IRQHandler+0x1f0>
{
/* Disable the CLUT transfer complete interrupt */
__HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
8001ae8: 687b ldr r3, [r7, #4]
8001aea: 681b ldr r3, [r3, #0]
8001aec: 681a ldr r2, [r3, #0]
8001aee: 687b ldr r3, [r7, #4]
8001af0: 681b ldr r3, [r3, #0]
8001af2: f422 5280 bic.w r2, r2, #4096 @ 0x1000
8001af6: 601a str r2, [r3, #0]
/* Clear the CLUT transfer complete flag */
__HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
8001af8: 687b ldr r3, [r7, #4]
8001afa: 681b ldr r3, [r3, #0]
8001afc: 2210 movs r2, #16
8001afe: 609a str r2, [r3, #8]
/* Update error code */
hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
8001b00: 687b ldr r3, [r7, #4]
8001b02: 6bda ldr r2, [r3, #60] @ 0x3c
8001b04: 687b ldr r3, [r7, #4]
8001b06: 63da str r2, [r3, #60] @ 0x3c
/* Change DMA2D state */
hdma2d->State = HAL_DMA2D_STATE_READY;
8001b08: 687b ldr r3, [r7, #4]
8001b0a: 2201 movs r2, #1
8001b0c: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process Unlocked */
__HAL_UNLOCK(hdma2d);
8001b10: 687b ldr r3, [r7, #4]
8001b12: 2200 movs r2, #0
8001b14: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* CLUT Transfer complete Callback */
#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
hdma2d->CLUTLoadingCpltCallback(hdma2d);
#else
HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
8001b18: 6878 ldr r0, [r7, #4]
8001b1a: f000 f80e bl 8001b3a <HAL_DMA2D_CLUTLoadingCpltCallback>
#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
}
}
}
8001b1e: bf00 nop
8001b20: 3710 adds r7, #16
8001b22: 46bd mov sp, r7
8001b24: bd80 pop {r7, pc}
08001b26 <HAL_DMA2D_LineEventCallback>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
{
8001b26: b480 push {r7}
8001b28: b083 sub sp, #12
8001b2a: af00 add r7, sp, #0
8001b2c: 6078 str r0, [r7, #4]
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_LineEventCallback can be implemented in the user file.
*/
}
8001b2e: bf00 nop
8001b30: 370c adds r7, #12
8001b32: 46bd mov sp, r7
8001b34: f85d 7b04 ldr.w r7, [sp], #4
8001b38: 4770 bx lr
08001b3a <HAL_DMA2D_CLUTLoadingCpltCallback>:
* @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
{
8001b3a: b480 push {r7}
8001b3c: b083 sub sp, #12
8001b3e: af00 add r7, sp, #0
8001b40: 6078 str r0, [r7, #4]
UNUSED(hdma2d);
/* NOTE : This function should not be modified; when the callback is needed,
the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
*/
}
8001b42: bf00 nop
8001b44: 370c adds r7, #12
8001b46: 46bd mov sp, r7
8001b48: f85d 7b04 ldr.w r7, [sp], #4
8001b4c: 4770 bx lr
...
08001b50 <HAL_DMA2D_ConfigLayer>:
* This parameter can be one of the following values:
* DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
{
8001b50: b480 push {r7}
8001b52: b087 sub sp, #28
8001b54: af00 add r7, sp, #0
8001b56: 6078 str r0, [r7, #4]
8001b58: 6039 str r1, [r7, #0]
uint32_t regValue;
/* Check the parameters */
assert_param(IS_DMA2D_LAYER(LayerIdx));
assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
if (hdma2d->Init.Mode != DMA2D_R2M)
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 685b ldr r3, [r3, #4]
8001b5e: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
}
}
/* Process locked */
__HAL_LOCK(hdma2d);
8001b62: 687b ldr r3, [r7, #4]
8001b64: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8001b68: 2b01 cmp r3, #1
8001b6a: d101 bne.n 8001b70 <HAL_DMA2D_ConfigLayer+0x20>
8001b6c: 2302 movs r3, #2
8001b6e: e079 b.n 8001c64 <HAL_DMA2D_ConfigLayer+0x114>
8001b70: 687b ldr r3, [r7, #4]
8001b72: 2201 movs r2, #1
8001b74: f883 2038 strb.w r2, [r3, #56] @ 0x38
/* Change DMA2D peripheral state */
hdma2d->State = HAL_DMA2D_STATE_BUSY;
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 2202 movs r2, #2
8001b7c: f883 2039 strb.w r2, [r3, #57] @ 0x39
pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
8001b80: 683b ldr r3, [r7, #0]
8001b82: 011b lsls r3, r3, #4
8001b84: 3318 adds r3, #24
8001b86: 687a ldr r2, [r7, #4]
8001b88: 4413 add r3, r2
8001b8a: 613b str r3, [r7, #16]
/* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
8001b8c: 693b ldr r3, [r7, #16]
8001b8e: 685a ldr r2, [r3, #4]
8001b90: 693b ldr r3, [r7, #16]
8001b92: 689b ldr r3, [r3, #8]
8001b94: 041b lsls r3, r3, #16
8001b96: 4313 orrs r3, r2
8001b98: 617b str r3, [r7, #20]
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
8001b9a: 4b35 ldr r3, [pc, #212] @ (8001c70 <HAL_DMA2D_ConfigLayer+0x120>)
8001b9c: 60fb str r3, [r7, #12]
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001b9e: 693b ldr r3, [r7, #16]
8001ba0: 685b ldr r3, [r3, #4]
8001ba2: 2b0a cmp r3, #10
8001ba4: d003 beq.n 8001bae <HAL_DMA2D_ConfigLayer+0x5e>
8001ba6: 693b ldr r3, [r7, #16]
8001ba8: 685b ldr r3, [r3, #4]
8001baa: 2b09 cmp r3, #9
8001bac: d107 bne.n 8001bbe <HAL_DMA2D_ConfigLayer+0x6e>
{
regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
8001bae: 693b ldr r3, [r7, #16]
8001bb0: 68db ldr r3, [r3, #12]
8001bb2: f003 437f and.w r3, r3, #4278190080 @ 0xff000000
8001bb6: 697a ldr r2, [r7, #20]
8001bb8: 4313 orrs r3, r2
8001bba: 617b str r3, [r7, #20]
8001bbc: e005 b.n 8001bca <HAL_DMA2D_ConfigLayer+0x7a>
}
else
{
regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
8001bbe: 693b ldr r3, [r7, #16]
8001bc0: 68db ldr r3, [r3, #12]
8001bc2: 061b lsls r3, r3, #24
8001bc4: 697a ldr r2, [r7, #20]
8001bc6: 4313 orrs r3, r2
8001bc8: 617b str r3, [r7, #20]
}
/* Configure the background DMA2D layer */
if (LayerIdx == DMA2D_BACKGROUND_LAYER)
8001bca: 683b ldr r3, [r7, #0]
8001bcc: 2b00 cmp r3, #0
8001bce: d120 bne.n 8001c12 <HAL_DMA2D_ConfigLayer+0xc2>
{
/* Write DMA2D BGPFCCR register */
MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
8001bd0: 687b ldr r3, [r7, #4]
8001bd2: 681b ldr r3, [r3, #0]
8001bd4: 6a5a ldr r2, [r3, #36] @ 0x24
8001bd6: 68fb ldr r3, [r7, #12]
8001bd8: 43db mvns r3, r3
8001bda: ea02 0103 and.w r1, r2, r3
8001bde: 687b ldr r3, [r7, #4]
8001be0: 681b ldr r3, [r3, #0]
8001be2: 697a ldr r2, [r7, #20]
8001be4: 430a orrs r2, r1
8001be6: 625a str r2, [r3, #36] @ 0x24
/* DMA2D BGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
8001be8: 687b ldr r3, [r7, #4]
8001bea: 681b ldr r3, [r3, #0]
8001bec: 693a ldr r2, [r7, #16]
8001bee: 6812 ldr r2, [r2, #0]
8001bf0: 619a str r2, [r3, #24]
/* DMA2D BGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001bf2: 693b ldr r3, [r7, #16]
8001bf4: 685b ldr r3, [r3, #4]
8001bf6: 2b0a cmp r3, #10
8001bf8: d003 beq.n 8001c02 <HAL_DMA2D_ConfigLayer+0xb2>
8001bfa: 693b ldr r3, [r7, #16]
8001bfc: 685b ldr r3, [r3, #4]
8001bfe: 2b09 cmp r3, #9
8001c00: d127 bne.n 8001c52 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
8001c02: 693b ldr r3, [r7, #16]
8001c04: 68da ldr r2, [r3, #12]
8001c06: 687b ldr r3, [r7, #4]
8001c08: 681b ldr r3, [r3, #0]
8001c0a: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
8001c0e: 629a str r2, [r3, #40] @ 0x28
8001c10: e01f b.n 8001c52 <HAL_DMA2D_ConfigLayer+0x102>
else
{
/* Write DMA2D FGPFCCR register */
MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
8001c12: 687b ldr r3, [r7, #4]
8001c14: 681b ldr r3, [r3, #0]
8001c16: 69da ldr r2, [r3, #28]
8001c18: 68fb ldr r3, [r7, #12]
8001c1a: 43db mvns r3, r3
8001c1c: ea02 0103 and.w r1, r2, r3
8001c20: 687b ldr r3, [r7, #4]
8001c22: 681b ldr r3, [r3, #0]
8001c24: 697a ldr r2, [r7, #20]
8001c26: 430a orrs r2, r1
8001c28: 61da str r2, [r3, #28]
/* DMA2D FGOR register configuration -------------------------------------*/
WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 681b ldr r3, [r3, #0]
8001c2e: 693a ldr r2, [r7, #16]
8001c30: 6812 ldr r2, [r2, #0]
8001c32: 611a str r2, [r3, #16]
/* DMA2D FGCOLR register configuration -------------------------------------*/
if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
8001c34: 693b ldr r3, [r7, #16]
8001c36: 685b ldr r3, [r3, #4]
8001c38: 2b0a cmp r3, #10
8001c3a: d003 beq.n 8001c44 <HAL_DMA2D_ConfigLayer+0xf4>
8001c3c: 693b ldr r3, [r7, #16]
8001c3e: 685b ldr r3, [r3, #4]
8001c40: 2b09 cmp r3, #9
8001c42: d106 bne.n 8001c52 <HAL_DMA2D_ConfigLayer+0x102>
{
WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
8001c44: 693b ldr r3, [r7, #16]
8001c46: 68da ldr r2, [r3, #12]
8001c48: 687b ldr r3, [r7, #4]
8001c4a: 681b ldr r3, [r3, #0]
8001c4c: f022 427f bic.w r2, r2, #4278190080 @ 0xff000000
8001c50: 621a str r2, [r3, #32]
DMA2D_FGCOLR_RED));
}
}
/* Initialize the DMA2D state*/
hdma2d->State = HAL_DMA2D_STATE_READY;
8001c52: 687b ldr r3, [r7, #4]
8001c54: 2201 movs r2, #1
8001c56: f883 2039 strb.w r2, [r3, #57] @ 0x39
/* Process unlocked */
__HAL_UNLOCK(hdma2d);
8001c5a: 687b ldr r3, [r7, #4]
8001c5c: 2200 movs r2, #0
8001c5e: f883 2038 strb.w r2, [r3, #56] @ 0x38
return HAL_OK;
8001c62: 2300 movs r3, #0
}
8001c64: 4618 mov r0, r3
8001c66: 371c adds r7, #28
8001c68: 46bd mov sp, r7
8001c6a: f85d 7b04 ldr.w r7, [sp], #4
8001c6e: 4770 bx lr
8001c70: ff03000f .word 0xff03000f
08001c74 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001c74: b480 push {r7}
8001c76: b089 sub sp, #36 @ 0x24
8001c78: af00 add r7, sp, #0
8001c7a: 6078 str r0, [r7, #4]
8001c7c: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8001c7e: 2300 movs r3, #0
8001c80: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8001c82: 2300 movs r3, #0
8001c84: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001c86: 2300 movs r3, #0
8001c88: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8001c8a: 2300 movs r3, #0
8001c8c: 61fb str r3, [r7, #28]
8001c8e: e177 b.n 8001f80 <HAL_GPIO_Init+0x30c>
{
/* Get the IO position */
ioposition = 0x01U << position;
8001c90: 2201 movs r2, #1
8001c92: 69fb ldr r3, [r7, #28]
8001c94: fa02 f303 lsl.w r3, r2, r3
8001c98: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001c9a: 683b ldr r3, [r7, #0]
8001c9c: 681b ldr r3, [r3, #0]
8001c9e: 697a ldr r2, [r7, #20]
8001ca0: 4013 ands r3, r2
8001ca2: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8001ca4: 693a ldr r2, [r7, #16]
8001ca6: 697b ldr r3, [r7, #20]
8001ca8: 429a cmp r2, r3
8001caa: f040 8166 bne.w 8001f7a <HAL_GPIO_Init+0x306>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001cae: 683b ldr r3, [r7, #0]
8001cb0: 685b ldr r3, [r3, #4]
8001cb2: f003 0303 and.w r3, r3, #3
8001cb6: 2b01 cmp r3, #1
8001cb8: d005 beq.n 8001cc6 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001cba: 683b ldr r3, [r7, #0]
8001cbc: 685b ldr r3, [r3, #4]
8001cbe: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8001cc2: 2b02 cmp r3, #2
8001cc4: d130 bne.n 8001d28 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001cc6: 687b ldr r3, [r7, #4]
8001cc8: 689b ldr r3, [r3, #8]
8001cca: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8001ccc: 69fb ldr r3, [r7, #28]
8001cce: 005b lsls r3, r3, #1
8001cd0: 2203 movs r2, #3
8001cd2: fa02 f303 lsl.w r3, r2, r3
8001cd6: 43db mvns r3, r3
8001cd8: 69ba ldr r2, [r7, #24]
8001cda: 4013 ands r3, r2
8001cdc: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8001cde: 683b ldr r3, [r7, #0]
8001ce0: 68da ldr r2, [r3, #12]
8001ce2: 69fb ldr r3, [r7, #28]
8001ce4: 005b lsls r3, r3, #1
8001ce6: fa02 f303 lsl.w r3, r2, r3
8001cea: 69ba ldr r2, [r7, #24]
8001cec: 4313 orrs r3, r2
8001cee: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8001cf0: 687b ldr r3, [r7, #4]
8001cf2: 69ba ldr r2, [r7, #24]
8001cf4: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001cf6: 687b ldr r3, [r7, #4]
8001cf8: 685b ldr r3, [r3, #4]
8001cfa: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8001cfc: 2201 movs r2, #1
8001cfe: 69fb ldr r3, [r7, #28]
8001d00: fa02 f303 lsl.w r3, r2, r3
8001d04: 43db mvns r3, r3
8001d06: 69ba ldr r2, [r7, #24]
8001d08: 4013 ands r3, r2
8001d0a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001d0c: 683b ldr r3, [r7, #0]
8001d0e: 685b ldr r3, [r3, #4]
8001d10: 091b lsrs r3, r3, #4
8001d12: f003 0201 and.w r2, r3, #1
8001d16: 69fb ldr r3, [r7, #28]
8001d18: fa02 f303 lsl.w r3, r2, r3
8001d1c: 69ba ldr r2, [r7, #24]
8001d1e: 4313 orrs r3, r2
8001d20: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8001d22: 687b ldr r3, [r7, #4]
8001d24: 69ba ldr r2, [r7, #24]
8001d26: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001d28: 683b ldr r3, [r7, #0]
8001d2a: 685b ldr r3, [r3, #4]
8001d2c: f003 0303 and.w r3, r3, #3
8001d30: 2b03 cmp r3, #3
8001d32: d017 beq.n 8001d64 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001d34: 687b ldr r3, [r7, #4]
8001d36: 68db ldr r3, [r3, #12]
8001d38: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8001d3a: 69fb ldr r3, [r7, #28]
8001d3c: 005b lsls r3, r3, #1
8001d3e: 2203 movs r2, #3
8001d40: fa02 f303 lsl.w r3, r2, r3
8001d44: 43db mvns r3, r3
8001d46: 69ba ldr r2, [r7, #24]
8001d48: 4013 ands r3, r2
8001d4a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001d4c: 683b ldr r3, [r7, #0]
8001d4e: 689a ldr r2, [r3, #8]
8001d50: 69fb ldr r3, [r7, #28]
8001d52: 005b lsls r3, r3, #1
8001d54: fa02 f303 lsl.w r3, r2, r3
8001d58: 69ba ldr r2, [r7, #24]
8001d5a: 4313 orrs r3, r2
8001d5c: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8001d5e: 687b ldr r3, [r7, #4]
8001d60: 69ba ldr r2, [r7, #24]
8001d62: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001d64: 683b ldr r3, [r7, #0]
8001d66: 685b ldr r3, [r3, #4]
8001d68: f003 0303 and.w r3, r3, #3
8001d6c: 2b02 cmp r3, #2
8001d6e: d123 bne.n 8001db8 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001d70: 69fb ldr r3, [r7, #28]
8001d72: 08da lsrs r2, r3, #3
8001d74: 687b ldr r3, [r7, #4]
8001d76: 3208 adds r2, #8
8001d78: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001d7c: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8001d7e: 69fb ldr r3, [r7, #28]
8001d80: f003 0307 and.w r3, r3, #7
8001d84: 009b lsls r3, r3, #2
8001d86: 220f movs r2, #15
8001d88: fa02 f303 lsl.w r3, r2, r3
8001d8c: 43db mvns r3, r3
8001d8e: 69ba ldr r2, [r7, #24]
8001d90: 4013 ands r3, r2
8001d92: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8001d94: 683b ldr r3, [r7, #0]
8001d96: 691a ldr r2, [r3, #16]
8001d98: 69fb ldr r3, [r7, #28]
8001d9a: f003 0307 and.w r3, r3, #7
8001d9e: 009b lsls r3, r3, #2
8001da0: fa02 f303 lsl.w r3, r2, r3
8001da4: 69ba ldr r2, [r7, #24]
8001da6: 4313 orrs r3, r2
8001da8: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8001daa: 69fb ldr r3, [r7, #28]
8001dac: 08da lsrs r2, r3, #3
8001dae: 687b ldr r3, [r7, #4]
8001db0: 3208 adds r2, #8
8001db2: 69b9 ldr r1, [r7, #24]
8001db4: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001db8: 687b ldr r3, [r7, #4]
8001dba: 681b ldr r3, [r3, #0]
8001dbc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8001dbe: 69fb ldr r3, [r7, #28]
8001dc0: 005b lsls r3, r3, #1
8001dc2: 2203 movs r2, #3
8001dc4: fa02 f303 lsl.w r3, r2, r3
8001dc8: 43db mvns r3, r3
8001dca: 69ba ldr r2, [r7, #24]
8001dcc: 4013 ands r3, r2
8001dce: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001dd0: 683b ldr r3, [r7, #0]
8001dd2: 685b ldr r3, [r3, #4]
8001dd4: f003 0203 and.w r2, r3, #3
8001dd8: 69fb ldr r3, [r7, #28]
8001dda: 005b lsls r3, r3, #1
8001ddc: fa02 f303 lsl.w r3, r2, r3
8001de0: 69ba ldr r2, [r7, #24]
8001de2: 4313 orrs r3, r2
8001de4: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001de6: 687b ldr r3, [r7, #4]
8001de8: 69ba ldr r2, [r7, #24]
8001dea: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001dec: 683b ldr r3, [r7, #0]
8001dee: 685b ldr r3, [r3, #4]
8001df0: f403 3340 and.w r3, r3, #196608 @ 0x30000
8001df4: 2b00 cmp r3, #0
8001df6: f000 80c0 beq.w 8001f7a <HAL_GPIO_Init+0x306>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001dfa: 2300 movs r3, #0
8001dfc: 60fb str r3, [r7, #12]
8001dfe: 4b66 ldr r3, [pc, #408] @ (8001f98 <HAL_GPIO_Init+0x324>)
8001e00: 6c5b ldr r3, [r3, #68] @ 0x44
8001e02: 4a65 ldr r2, [pc, #404] @ (8001f98 <HAL_GPIO_Init+0x324>)
8001e04: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001e08: 6453 str r3, [r2, #68] @ 0x44
8001e0a: 4b63 ldr r3, [pc, #396] @ (8001f98 <HAL_GPIO_Init+0x324>)
8001e0c: 6c5b ldr r3, [r3, #68] @ 0x44
8001e0e: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001e12: 60fb str r3, [r7, #12]
8001e14: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8001e16: 4a61 ldr r2, [pc, #388] @ (8001f9c <HAL_GPIO_Init+0x328>)
8001e18: 69fb ldr r3, [r7, #28]
8001e1a: 089b lsrs r3, r3, #2
8001e1c: 3302 adds r3, #2
8001e1e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001e22: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8001e24: 69fb ldr r3, [r7, #28]
8001e26: f003 0303 and.w r3, r3, #3
8001e2a: 009b lsls r3, r3, #2
8001e2c: 220f movs r2, #15
8001e2e: fa02 f303 lsl.w r3, r2, r3
8001e32: 43db mvns r3, r3
8001e34: 69ba ldr r2, [r7, #24]
8001e36: 4013 ands r3, r2
8001e38: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8001e3a: 687b ldr r3, [r7, #4]
8001e3c: 4a58 ldr r2, [pc, #352] @ (8001fa0 <HAL_GPIO_Init+0x32c>)
8001e3e: 4293 cmp r3, r2
8001e40: d037 beq.n 8001eb2 <HAL_GPIO_Init+0x23e>
8001e42: 687b ldr r3, [r7, #4]
8001e44: 4a57 ldr r2, [pc, #348] @ (8001fa4 <HAL_GPIO_Init+0x330>)
8001e46: 4293 cmp r3, r2
8001e48: d031 beq.n 8001eae <HAL_GPIO_Init+0x23a>
8001e4a: 687b ldr r3, [r7, #4]
8001e4c: 4a56 ldr r2, [pc, #344] @ (8001fa8 <HAL_GPIO_Init+0x334>)
8001e4e: 4293 cmp r3, r2
8001e50: d02b beq.n 8001eaa <HAL_GPIO_Init+0x236>
8001e52: 687b ldr r3, [r7, #4]
8001e54: 4a55 ldr r2, [pc, #340] @ (8001fac <HAL_GPIO_Init+0x338>)
8001e56: 4293 cmp r3, r2
8001e58: d025 beq.n 8001ea6 <HAL_GPIO_Init+0x232>
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 4a54 ldr r2, [pc, #336] @ (8001fb0 <HAL_GPIO_Init+0x33c>)
8001e5e: 4293 cmp r3, r2
8001e60: d01f beq.n 8001ea2 <HAL_GPIO_Init+0x22e>
8001e62: 687b ldr r3, [r7, #4]
8001e64: 4a53 ldr r2, [pc, #332] @ (8001fb4 <HAL_GPIO_Init+0x340>)
8001e66: 4293 cmp r3, r2
8001e68: d019 beq.n 8001e9e <HAL_GPIO_Init+0x22a>
8001e6a: 687b ldr r3, [r7, #4]
8001e6c: 4a52 ldr r2, [pc, #328] @ (8001fb8 <HAL_GPIO_Init+0x344>)
8001e6e: 4293 cmp r3, r2
8001e70: d013 beq.n 8001e9a <HAL_GPIO_Init+0x226>
8001e72: 687b ldr r3, [r7, #4]
8001e74: 4a51 ldr r2, [pc, #324] @ (8001fbc <HAL_GPIO_Init+0x348>)
8001e76: 4293 cmp r3, r2
8001e78: d00d beq.n 8001e96 <HAL_GPIO_Init+0x222>
8001e7a: 687b ldr r3, [r7, #4]
8001e7c: 4a50 ldr r2, [pc, #320] @ (8001fc0 <HAL_GPIO_Init+0x34c>)
8001e7e: 4293 cmp r3, r2
8001e80: d007 beq.n 8001e92 <HAL_GPIO_Init+0x21e>
8001e82: 687b ldr r3, [r7, #4]
8001e84: 4a4f ldr r2, [pc, #316] @ (8001fc4 <HAL_GPIO_Init+0x350>)
8001e86: 4293 cmp r3, r2
8001e88: d101 bne.n 8001e8e <HAL_GPIO_Init+0x21a>
8001e8a: 2309 movs r3, #9
8001e8c: e012 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001e8e: 230a movs r3, #10
8001e90: e010 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001e92: 2308 movs r3, #8
8001e94: e00e b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001e96: 2307 movs r3, #7
8001e98: e00c b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001e9a: 2306 movs r3, #6
8001e9c: e00a b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001e9e: 2305 movs r3, #5
8001ea0: e008 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001ea2: 2304 movs r3, #4
8001ea4: e006 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001ea6: 2303 movs r3, #3
8001ea8: e004 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001eaa: 2302 movs r3, #2
8001eac: e002 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001eae: 2301 movs r3, #1
8001eb0: e000 b.n 8001eb4 <HAL_GPIO_Init+0x240>
8001eb2: 2300 movs r3, #0
8001eb4: 69fa ldr r2, [r7, #28]
8001eb6: f002 0203 and.w r2, r2, #3
8001eba: 0092 lsls r2, r2, #2
8001ebc: 4093 lsls r3, r2
8001ebe: 69ba ldr r2, [r7, #24]
8001ec0: 4313 orrs r3, r2
8001ec2: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001ec4: 4935 ldr r1, [pc, #212] @ (8001f9c <HAL_GPIO_Init+0x328>)
8001ec6: 69fb ldr r3, [r7, #28]
8001ec8: 089b lsrs r3, r3, #2
8001eca: 3302 adds r3, #2
8001ecc: 69ba ldr r2, [r7, #24]
8001ece: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001ed2: 4b3d ldr r3, [pc, #244] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001ed4: 689b ldr r3, [r3, #8]
8001ed6: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001ed8: 693b ldr r3, [r7, #16]
8001eda: 43db mvns r3, r3
8001edc: 69ba ldr r2, [r7, #24]
8001ede: 4013 ands r3, r2
8001ee0: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001ee2: 683b ldr r3, [r7, #0]
8001ee4: 685b ldr r3, [r3, #4]
8001ee6: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8001eea: 2b00 cmp r3, #0
8001eec: d003 beq.n 8001ef6 <HAL_GPIO_Init+0x282>
{
temp |= iocurrent;
8001eee: 69ba ldr r2, [r7, #24]
8001ef0: 693b ldr r3, [r7, #16]
8001ef2: 4313 orrs r3, r2
8001ef4: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001ef6: 4a34 ldr r2, [pc, #208] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001ef8: 69bb ldr r3, [r7, #24]
8001efa: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001efc: 4b32 ldr r3, [pc, #200] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001efe: 68db ldr r3, [r3, #12]
8001f00: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f02: 693b ldr r3, [r7, #16]
8001f04: 43db mvns r3, r3
8001f06: 69ba ldr r2, [r7, #24]
8001f08: 4013 ands r3, r2
8001f0a: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001f0c: 683b ldr r3, [r7, #0]
8001f0e: 685b ldr r3, [r3, #4]
8001f10: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8001f14: 2b00 cmp r3, #0
8001f16: d003 beq.n 8001f20 <HAL_GPIO_Init+0x2ac>
{
temp |= iocurrent;
8001f18: 69ba ldr r2, [r7, #24]
8001f1a: 693b ldr r3, [r7, #16]
8001f1c: 4313 orrs r3, r2
8001f1e: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8001f20: 4a29 ldr r2, [pc, #164] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001f22: 69bb ldr r3, [r7, #24]
8001f24: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8001f26: 4b28 ldr r3, [pc, #160] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001f28: 685b ldr r3, [r3, #4]
8001f2a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f2c: 693b ldr r3, [r7, #16]
8001f2e: 43db mvns r3, r3
8001f30: 69ba ldr r2, [r7, #24]
8001f32: 4013 ands r3, r2
8001f34: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001f36: 683b ldr r3, [r7, #0]
8001f38: 685b ldr r3, [r3, #4]
8001f3a: f403 3300 and.w r3, r3, #131072 @ 0x20000
8001f3e: 2b00 cmp r3, #0
8001f40: d003 beq.n 8001f4a <HAL_GPIO_Init+0x2d6>
{
temp |= iocurrent;
8001f42: 69ba ldr r2, [r7, #24]
8001f44: 693b ldr r3, [r7, #16]
8001f46: 4313 orrs r3, r2
8001f48: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8001f4a: 4a1f ldr r2, [pc, #124] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001f4c: 69bb ldr r3, [r7, #24]
8001f4e: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001f50: 4b1d ldr r3, [pc, #116] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001f52: 681b ldr r3, [r3, #0]
8001f54: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001f56: 693b ldr r3, [r7, #16]
8001f58: 43db mvns r3, r3
8001f5a: 69ba ldr r2, [r7, #24]
8001f5c: 4013 ands r3, r2
8001f5e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8001f60: 683b ldr r3, [r7, #0]
8001f62: 685b ldr r3, [r3, #4]
8001f64: f403 3380 and.w r3, r3, #65536 @ 0x10000
8001f68: 2b00 cmp r3, #0
8001f6a: d003 beq.n 8001f74 <HAL_GPIO_Init+0x300>
{
temp |= iocurrent;
8001f6c: 69ba ldr r2, [r7, #24]
8001f6e: 693b ldr r3, [r7, #16]
8001f70: 4313 orrs r3, r2
8001f72: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001f74: 4a14 ldr r2, [pc, #80] @ (8001fc8 <HAL_GPIO_Init+0x354>)
8001f76: 69bb ldr r3, [r7, #24]
8001f78: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8001f7a: 69fb ldr r3, [r7, #28]
8001f7c: 3301 adds r3, #1
8001f7e: 61fb str r3, [r7, #28]
8001f80: 69fb ldr r3, [r7, #28]
8001f82: 2b0f cmp r3, #15
8001f84: f67f ae84 bls.w 8001c90 <HAL_GPIO_Init+0x1c>
}
}
}
}
8001f88: bf00 nop
8001f8a: bf00 nop
8001f8c: 3724 adds r7, #36 @ 0x24
8001f8e: 46bd mov sp, r7
8001f90: f85d 7b04 ldr.w r7, [sp], #4
8001f94: 4770 bx lr
8001f96: bf00 nop
8001f98: 40023800 .word 0x40023800
8001f9c: 40013800 .word 0x40013800
8001fa0: 40020000 .word 0x40020000
8001fa4: 40020400 .word 0x40020400
8001fa8: 40020800 .word 0x40020800
8001fac: 40020c00 .word 0x40020c00
8001fb0: 40021000 .word 0x40021000
8001fb4: 40021400 .word 0x40021400
8001fb8: 40021800 .word 0x40021800
8001fbc: 40021c00 .word 0x40021c00
8001fc0: 40022000 .word 0x40022000
8001fc4: 40022400 .word 0x40022400
8001fc8: 40013c00 .word 0x40013c00
08001fcc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001fcc: b480 push {r7}
8001fce: b083 sub sp, #12
8001fd0: af00 add r7, sp, #0
8001fd2: 6078 str r0, [r7, #4]
8001fd4: 460b mov r3, r1
8001fd6: 807b strh r3, [r7, #2]
8001fd8: 4613 mov r3, r2
8001fda: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001fdc: 787b ldrb r3, [r7, #1]
8001fde: 2b00 cmp r3, #0
8001fe0: d003 beq.n 8001fea <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001fe2: 887a ldrh r2, [r7, #2]
8001fe4: 687b ldr r3, [r7, #4]
8001fe6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001fe8: e003 b.n 8001ff2 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8001fea: 887b ldrh r3, [r7, #2]
8001fec: 041a lsls r2, r3, #16
8001fee: 687b ldr r3, [r7, #4]
8001ff0: 619a str r2, [r3, #24]
}
8001ff2: bf00 nop
8001ff4: 370c adds r7, #12
8001ff6: 46bd mov sp, r7
8001ff8: f85d 7b04 ldr.w r7, [sp], #4
8001ffc: 4770 bx lr
08001ffe <HAL_GPIO_TogglePin>:
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001ffe: b480 push {r7}
8002000: b085 sub sp, #20
8002002: af00 add r7, sp, #0
8002004: 6078 str r0, [r7, #4]
8002006: 460b mov r3, r1
8002008: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
800200a: 687b ldr r3, [r7, #4]
800200c: 695b ldr r3, [r3, #20]
800200e: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
8002010: 887a ldrh r2, [r7, #2]
8002012: 68fb ldr r3, [r7, #12]
8002014: 4013 ands r3, r2
8002016: 041a lsls r2, r3, #16
8002018: 68fb ldr r3, [r7, #12]
800201a: 43d9 mvns r1, r3
800201c: 887b ldrh r3, [r7, #2]
800201e: 400b ands r3, r1
8002020: 431a orrs r2, r3
8002022: 687b ldr r3, [r7, #4]
8002024: 619a str r2, [r3, #24]
}
8002026: bf00 nop
8002028: 3714 adds r7, #20
800202a: 46bd mov sp, r7
800202c: f85d 7b04 ldr.w r7, [sp], #4
8002030: 4770 bx lr
08002032 <HAL_HCD_IRQHandler>:
* @brief Handle HCD interrupt request.
* @param hhcd HCD handle
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
8002032: b580 push {r7, lr}
8002034: b086 sub sp, #24
8002036: af00 add r7, sp, #0
8002038: 6078 str r0, [r7, #4]
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
800203a: 687b ldr r3, [r7, #4]
800203c: 681b ldr r3, [r3, #0]
800203e: 613b str r3, [r7, #16]
uint32_t USBx_BASE = (uint32_t)USBx;
8002040: 693b ldr r3, [r7, #16]
8002042: 60fb str r3, [r7, #12]
uint32_t i;
uint32_t interrupt;
/* Ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
8002044: 687b ldr r3, [r7, #4]
8002046: 681b ldr r3, [r3, #0]
8002048: 4618 mov r0, r3
800204a: f004 fab7 bl 80065bc <USB_GetMode>
800204e: 4603 mov r3, r0
8002050: 2b01 cmp r3, #1
8002052: f040 80fb bne.w 800224c <HAL_HCD_IRQHandler+0x21a>
{
/* Avoid spurious interrupt */
if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
8002056: 687b ldr r3, [r7, #4]
8002058: 681b ldr r3, [r3, #0]
800205a: 4618 mov r0, r3
800205c: f004 fa7a bl 8006554 <USB_ReadInterrupts>
8002060: 4603 mov r3, r0
8002062: 2b00 cmp r3, #0
8002064: f000 80f1 beq.w 800224a <HAL_HCD_IRQHandler+0x218>
{
return;
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
8002068: 687b ldr r3, [r7, #4]
800206a: 681b ldr r3, [r3, #0]
800206c: 4618 mov r0, r3
800206e: f004 fa71 bl 8006554 <USB_ReadInterrupts>
8002072: 4603 mov r3, r0
8002074: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8002078: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
800207c: d104 bne.n 8002088 <HAL_HCD_IRQHandler+0x56>
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
800207e: 687b ldr r3, [r7, #4]
8002080: 681b ldr r3, [r3, #0]
8002082: f44f 1200 mov.w r2, #2097152 @ 0x200000
8002086: 615a str r2, [r3, #20]
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
8002088: 687b ldr r3, [r7, #4]
800208a: 681b ldr r3, [r3, #0]
800208c: 4618 mov r0, r3
800208e: f004 fa61 bl 8006554 <USB_ReadInterrupts>
8002092: 4603 mov r3, r0
8002094: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8002098: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800209c: d104 bne.n 80020a8 <HAL_HCD_IRQHandler+0x76>
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR);
800209e: 687b ldr r3, [r7, #4]
80020a0: 681b ldr r3, [r3, #0]
80020a2: f44f 1280 mov.w r2, #1048576 @ 0x100000
80020a6: 615a str r2, [r3, #20]
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE))
80020a8: 687b ldr r3, [r7, #4]
80020aa: 681b ldr r3, [r3, #0]
80020ac: 4618 mov r0, r3
80020ae: f004 fa51 bl 8006554 <USB_ReadInterrupts>
80020b2: 4603 mov r3, r0
80020b4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80020b8: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
80020bc: d104 bne.n 80020c8 <HAL_HCD_IRQHandler+0x96>
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
80020be: 687b ldr r3, [r7, #4]
80020c0: 681b ldr r3, [r3, #0]
80020c2: f04f 6280 mov.w r2, #67108864 @ 0x4000000
80020c6: 615a str r2, [r3, #20]
}
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
80020c8: 687b ldr r3, [r7, #4]
80020ca: 681b ldr r3, [r3, #0]
80020cc: 4618 mov r0, r3
80020ce: f004 fa41 bl 8006554 <USB_ReadInterrupts>
80020d2: 4603 mov r3, r0
80020d4: f003 0302 and.w r3, r3, #2
80020d8: 2b02 cmp r3, #2
80020da: d103 bne.n 80020e4 <HAL_HCD_IRQHandler+0xb2>
{
/* Incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
80020dc: 687b ldr r3, [r7, #4]
80020de: 681b ldr r3, [r3, #0]
80020e0: 2202 movs r2, #2
80020e2: 615a str r2, [r3, #20]
}
/* Handle Host Disconnect Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
80020e4: 687b ldr r3, [r7, #4]
80020e6: 681b ldr r3, [r3, #0]
80020e8: 4618 mov r0, r3
80020ea: f004 fa33 bl 8006554 <USB_ReadInterrupts>
80020ee: 4603 mov r3, r0
80020f0: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80020f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80020f8: d120 bne.n 800213c <HAL_HCD_IRQHandler+0x10a>
{
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
80020fa: 687b ldr r3, [r7, #4]
80020fc: 681b ldr r3, [r3, #0]
80020fe: f04f 5200 mov.w r2, #536870912 @ 0x20000000
8002102: 615a str r2, [r3, #20]
if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
8002104: 68fb ldr r3, [r7, #12]
8002106: f503 6388 add.w r3, r3, #1088 @ 0x440
800210a: 681b ldr r3, [r3, #0]
800210c: f003 0301 and.w r3, r3, #1
8002110: 2b00 cmp r3, #0
8002112: d113 bne.n 800213c <HAL_HCD_IRQHandler+0x10a>
{
/* Flush USB Fifo */
(void)USB_FlushTxFifo(USBx, 0x10U);
8002114: 2110 movs r1, #16
8002116: 6938 ldr r0, [r7, #16]
8002118: f004 f964 bl 80063e4 <USB_FlushTxFifo>
(void)USB_FlushRxFifo(USBx);
800211c: 6938 ldr r0, [r7, #16]
800211e: f004 f993 bl 8006448 <USB_FlushRxFifo>
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
8002122: 687b ldr r3, [r7, #4]
8002124: 7a5b ldrb r3, [r3, #9]
8002126: 2b02 cmp r3, #2
8002128: d105 bne.n 8002136 <HAL_HCD_IRQHandler+0x104>
{
/* Restore FS Clock */
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
800212a: 687b ldr r3, [r7, #4]
800212c: 681b ldr r3, [r3, #0]
800212e: 2101 movs r1, #1
8002130: 4618 mov r0, r3
8002132: f004 fa51 bl 80065d8 <USB_InitFSLSPClkSel>
/* Handle Host Port Disconnect Interrupt */
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->DisconnectCallback(hhcd);
#else
HAL_HCD_Disconnect_Callback(hhcd);
8002136: 6878 ldr r0, [r7, #4]
8002138: f005 fe26 bl 8007d88 <HAL_HCD_Disconnect_Callback>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Handle Host Port Interrupts */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
800213c: 687b ldr r3, [r7, #4]
800213e: 681b ldr r3, [r3, #0]
8002140: 4618 mov r0, r3
8002142: f004 fa07 bl 8006554 <USB_ReadInterrupts>
8002146: 4603 mov r3, r0
8002148: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
800214c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8002150: d102 bne.n 8002158 <HAL_HCD_IRQHandler+0x126>
{
HCD_Port_IRQHandler(hhcd);
8002152: 6878 ldr r0, [r7, #4]
8002154: f001 fca1 bl 8003a9a <HCD_Port_IRQHandler>
}
/* Handle Host SOF Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
8002158: 687b ldr r3, [r7, #4]
800215a: 681b ldr r3, [r3, #0]
800215c: 4618 mov r0, r3
800215e: f004 f9f9 bl 8006554 <USB_ReadInterrupts>
8002162: 4603 mov r3, r0
8002164: f003 0308 and.w r3, r3, #8
8002168: 2b08 cmp r3, #8
800216a: d106 bne.n 800217a <HAL_HCD_IRQHandler+0x148>
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->SOFCallback(hhcd);
#else
HAL_HCD_SOF_Callback(hhcd);
800216c: 6878 ldr r0, [r7, #4]
800216e: f005 fdef bl 8007d50 <HAL_HCD_SOF_Callback>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
8002172: 687b ldr r3, [r7, #4]
8002174: 681b ldr r3, [r3, #0]
8002176: 2208 movs r2, #8
8002178: 615a str r2, [r3, #20]
}
/* Handle Host channel Interrupt */
if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
800217a: 687b ldr r3, [r7, #4]
800217c: 681b ldr r3, [r3, #0]
800217e: 4618 mov r0, r3
8002180: f004 f9e8 bl 8006554 <USB_ReadInterrupts>
8002184: 4603 mov r3, r0
8002186: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800218a: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
800218e: d139 bne.n 8002204 <HAL_HCD_IRQHandler+0x1d2>
{
interrupt = USB_HC_ReadInterrupt(hhcd->Instance);
8002190: 687b ldr r3, [r7, #4]
8002192: 681b ldr r3, [r3, #0]
8002194: 4618 mov r0, r3
8002196: f004 fa5c bl 8006652 <USB_HC_ReadInterrupt>
800219a: 60b8 str r0, [r7, #8]
for (i = 0U; i < hhcd->Init.Host_channels; i++)
800219c: 2300 movs r3, #0
800219e: 617b str r3, [r7, #20]
80021a0: e025 b.n 80021ee <HAL_HCD_IRQHandler+0x1bc>
{
if ((interrupt & (1UL << (i & 0xFU))) != 0U)
80021a2: 697b ldr r3, [r7, #20]
80021a4: f003 030f and.w r3, r3, #15
80021a8: 68ba ldr r2, [r7, #8]
80021aa: fa22 f303 lsr.w r3, r2, r3
80021ae: f003 0301 and.w r3, r3, #1
80021b2: 2b00 cmp r3, #0
80021b4: d018 beq.n 80021e8 <HAL_HCD_IRQHandler+0x1b6>
{
if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR)
80021b6: 697b ldr r3, [r7, #20]
80021b8: 015a lsls r2, r3, #5
80021ba: 68fb ldr r3, [r7, #12]
80021bc: 4413 add r3, r2
80021be: f503 63a0 add.w r3, r3, #1280 @ 0x500
80021c2: 681b ldr r3, [r3, #0]
80021c4: f403 4300 and.w r3, r3, #32768 @ 0x8000
80021c8: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80021cc: d106 bne.n 80021dc <HAL_HCD_IRQHandler+0x1aa>
{
HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i);
80021ce: 697b ldr r3, [r7, #20]
80021d0: b2db uxtb r3, r3
80021d2: 4619 mov r1, r3
80021d4: 6878 ldr r0, [r7, #4]
80021d6: f000 f859 bl 800228c <HCD_HC_IN_IRQHandler>
80021da: e005 b.n 80021e8 <HAL_HCD_IRQHandler+0x1b6>
}
else
{
HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i);
80021dc: 697b ldr r3, [r7, #20]
80021de: b2db uxtb r3, r3
80021e0: 4619 mov r1, r3
80021e2: 6878 ldr r0, [r7, #4]
80021e4: f000 febb bl 8002f5e <HCD_HC_OUT_IRQHandler>
for (i = 0U; i < hhcd->Init.Host_channels; i++)
80021e8: 697b ldr r3, [r7, #20]
80021ea: 3301 adds r3, #1
80021ec: 617b str r3, [r7, #20]
80021ee: 687b ldr r3, [r7, #4]
80021f0: 795b ldrb r3, [r3, #5]
80021f2: 461a mov r2, r3
80021f4: 697b ldr r3, [r7, #20]
80021f6: 4293 cmp r3, r2
80021f8: d3d3 bcc.n 80021a2 <HAL_HCD_IRQHandler+0x170>
}
}
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
80021fa: 687b ldr r3, [r7, #4]
80021fc: 681b ldr r3, [r3, #0]
80021fe: f04f 7200 mov.w r2, #33554432 @ 0x2000000
8002202: 615a str r2, [r3, #20]
}
/* Handle Rx Queue Level Interrupts */
if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
8002204: 687b ldr r3, [r7, #4]
8002206: 681b ldr r3, [r3, #0]
8002208: 4618 mov r0, r3
800220a: f004 f9a3 bl 8006554 <USB_ReadInterrupts>
800220e: 4603 mov r3, r0
8002210: f003 0310 and.w r3, r3, #16
8002214: 2b10 cmp r3, #16
8002216: d101 bne.n 800221c <HAL_HCD_IRQHandler+0x1ea>
8002218: 2301 movs r3, #1
800221a: e000 b.n 800221e <HAL_HCD_IRQHandler+0x1ec>
800221c: 2300 movs r3, #0
800221e: 2b00 cmp r3, #0
8002220: d014 beq.n 800224c <HAL_HCD_IRQHandler+0x21a>
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8002222: 687b ldr r3, [r7, #4]
8002224: 681b ldr r3, [r3, #0]
8002226: 699a ldr r2, [r3, #24]
8002228: 687b ldr r3, [r7, #4]
800222a: 681b ldr r3, [r3, #0]
800222c: f022 0210 bic.w r2, r2, #16
8002230: 619a str r2, [r3, #24]
HCD_RXQLVL_IRQHandler(hhcd);
8002232: 6878 ldr r0, [r7, #4]
8002234: f001 fb52 bl 80038dc <HCD_RXQLVL_IRQHandler>
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
8002238: 687b ldr r3, [r7, #4]
800223a: 681b ldr r3, [r3, #0]
800223c: 699a ldr r2, [r3, #24]
800223e: 687b ldr r3, [r7, #4]
8002240: 681b ldr r3, [r3, #0]
8002242: f042 0210 orr.w r2, r2, #16
8002246: 619a str r2, [r3, #24]
8002248: e000 b.n 800224c <HAL_HCD_IRQHandler+0x21a>
return;
800224a: bf00 nop
}
}
}
800224c: 3718 adds r7, #24
800224e: 46bd mov sp, r7
8002250: bd80 pop {r7, pc}
08002252 <HAL_HCD_Stop>:
* @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
{
8002252: b580 push {r7, lr}
8002254: b082 sub sp, #8
8002256: af00 add r7, sp, #0
8002258: 6078 str r0, [r7, #4]
__HAL_LOCK(hhcd);
800225a: 687b ldr r3, [r7, #4]
800225c: f893 33d4 ldrb.w r3, [r3, #980] @ 0x3d4
8002260: 2b01 cmp r3, #1
8002262: d101 bne.n 8002268 <HAL_HCD_Stop+0x16>
8002264: 2302 movs r3, #2
8002266: e00d b.n 8002284 <HAL_HCD_Stop+0x32>
8002268: 687b ldr r3, [r7, #4]
800226a: 2201 movs r2, #1
800226c: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
(void)USB_StopHost(hhcd->Instance);
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 4618 mov r0, r3
8002276: f004 fb1d bl 80068b4 <USB_StopHost>
__HAL_UNLOCK(hhcd);
800227a: 687b ldr r3, [r7, #4]
800227c: 2200 movs r2, #0
800227e: f883 23d4 strb.w r2, [r3, #980] @ 0x3d4
return HAL_OK;
8002282: 2300 movs r3, #0
}
8002284: 4618 mov r0, r3
8002286: 3708 adds r7, #8
8002288: 46bd mov sp, r7
800228a: bd80 pop {r7, pc}
0800228c <HCD_HC_IN_IRQHandler>:
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
800228c: b580 push {r7, lr}
800228e: b086 sub sp, #24
8002290: af00 add r7, sp, #0
8002292: 6078 str r0, [r7, #4]
8002294: 460b mov r3, r1
8002296: 70fb strb r3, [r7, #3]
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
8002298: 687b ldr r3, [r7, #4]
800229a: 681b ldr r3, [r3, #0]
800229c: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
800229e: 697b ldr r3, [r7, #20]
80022a0: 613b str r3, [r7, #16]
uint32_t tmpreg;
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
80022a2: 687b ldr r3, [r7, #4]
80022a4: 681b ldr r3, [r3, #0]
80022a6: 78fa ldrb r2, [r7, #3]
80022a8: 4611 mov r1, r2
80022aa: 4618 mov r0, r3
80022ac: f004 f965 bl 800657a <USB_ReadChInterrupts>
80022b0: 4603 mov r3, r0
80022b2: f003 0304 and.w r3, r3, #4
80022b6: 2b04 cmp r3, #4
80022b8: d11a bne.n 80022f0 <HCD_HC_IN_IRQHandler+0x64>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
80022ba: 78fb ldrb r3, [r7, #3]
80022bc: 015a lsls r2, r3, #5
80022be: 693b ldr r3, [r7, #16]
80022c0: 4413 add r3, r2
80022c2: f503 63a0 add.w r3, r3, #1280 @ 0x500
80022c6: 461a mov r2, r3
80022c8: 2304 movs r3, #4
80022ca: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_XACTERR;
80022cc: 78fa ldrb r2, [r7, #3]
80022ce: 6879 ldr r1, [r7, #4]
80022d0: 4613 mov r3, r2
80022d2: 011b lsls r3, r3, #4
80022d4: 1a9b subs r3, r3, r2
80022d6: 009b lsls r3, r3, #2
80022d8: 440b add r3, r1
80022da: 334d adds r3, #77 @ 0x4d
80022dc: 2207 movs r2, #7
80022de: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80022e0: 687b ldr r3, [r7, #4]
80022e2: 681b ldr r3, [r3, #0]
80022e4: 78fa ldrb r2, [r7, #3]
80022e6: 4611 mov r1, r2
80022e8: 4618 mov r0, r3
80022ea: f004 f9c3 bl 8006674 <USB_HC_Halt>
80022ee: e09e b.n 800242e <HCD_HC_IN_IRQHandler+0x1a2>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
80022f0: 687b ldr r3, [r7, #4]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 78fa ldrb r2, [r7, #3]
80022f6: 4611 mov r1, r2
80022f8: 4618 mov r0, r3
80022fa: f004 f93e bl 800657a <USB_ReadChInterrupts>
80022fe: 4603 mov r3, r0
8002300: f403 7380 and.w r3, r3, #256 @ 0x100
8002304: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002308: d11b bne.n 8002342 <HCD_HC_IN_IRQHandler+0xb6>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
800230a: 78fb ldrb r3, [r7, #3]
800230c: 015a lsls r2, r3, #5
800230e: 693b ldr r3, [r7, #16]
8002310: 4413 add r3, r2
8002312: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002316: 461a mov r2, r3
8002318: f44f 7380 mov.w r3, #256 @ 0x100
800231c: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_BBLERR;
800231e: 78fa ldrb r2, [r7, #3]
8002320: 6879 ldr r1, [r7, #4]
8002322: 4613 mov r3, r2
8002324: 011b lsls r3, r3, #4
8002326: 1a9b subs r3, r3, r2
8002328: 009b lsls r3, r3, #2
800232a: 440b add r3, r1
800232c: 334d adds r3, #77 @ 0x4d
800232e: 2208 movs r2, #8
8002330: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002332: 687b ldr r3, [r7, #4]
8002334: 681b ldr r3, [r3, #0]
8002336: 78fa ldrb r2, [r7, #3]
8002338: 4611 mov r1, r2
800233a: 4618 mov r0, r3
800233c: f004 f99a bl 8006674 <USB_HC_Halt>
8002340: e075 b.n 800242e <HCD_HC_IN_IRQHandler+0x1a2>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
8002342: 687b ldr r3, [r7, #4]
8002344: 681b ldr r3, [r3, #0]
8002346: 78fa ldrb r2, [r7, #3]
8002348: 4611 mov r1, r2
800234a: 4618 mov r0, r3
800234c: f004 f915 bl 800657a <USB_ReadChInterrupts>
8002350: 4603 mov r3, r0
8002352: f003 0308 and.w r3, r3, #8
8002356: 2b08 cmp r3, #8
8002358: d11a bne.n 8002390 <HCD_HC_IN_IRQHandler+0x104>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
800235a: 78fb ldrb r3, [r7, #3]
800235c: 015a lsls r2, r3, #5
800235e: 693b ldr r3, [r7, #16]
8002360: 4413 add r3, r2
8002362: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002366: 461a mov r2, r3
8002368: 2308 movs r3, #8
800236a: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_STALL;
800236c: 78fa ldrb r2, [r7, #3]
800236e: 6879 ldr r1, [r7, #4]
8002370: 4613 mov r3, r2
8002372: 011b lsls r3, r3, #4
8002374: 1a9b subs r3, r3, r2
8002376: 009b lsls r3, r3, #2
8002378: 440b add r3, r1
800237a: 334d adds r3, #77 @ 0x4d
800237c: 2206 movs r2, #6
800237e: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002380: 687b ldr r3, [r7, #4]
8002382: 681b ldr r3, [r3, #0]
8002384: 78fa ldrb r2, [r7, #3]
8002386: 4611 mov r1, r2
8002388: 4618 mov r0, r3
800238a: f004 f973 bl 8006674 <USB_HC_Halt>
800238e: e04e b.n 800242e <HCD_HC_IN_IRQHandler+0x1a2>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
8002390: 687b ldr r3, [r7, #4]
8002392: 681b ldr r3, [r3, #0]
8002394: 78fa ldrb r2, [r7, #3]
8002396: 4611 mov r1, r2
8002398: 4618 mov r0, r3
800239a: f004 f8ee bl 800657a <USB_ReadChInterrupts>
800239e: 4603 mov r3, r0
80023a0: f403 6380 and.w r3, r3, #1024 @ 0x400
80023a4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80023a8: d11b bne.n 80023e2 <HCD_HC_IN_IRQHandler+0x156>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
80023aa: 78fb ldrb r3, [r7, #3]
80023ac: 015a lsls r2, r3, #5
80023ae: 693b ldr r3, [r7, #16]
80023b0: 4413 add r3, r2
80023b2: f503 63a0 add.w r3, r3, #1280 @ 0x500
80023b6: 461a mov r2, r3
80023b8: f44f 6380 mov.w r3, #1024 @ 0x400
80023bc: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_DATATGLERR;
80023be: 78fa ldrb r2, [r7, #3]
80023c0: 6879 ldr r1, [r7, #4]
80023c2: 4613 mov r3, r2
80023c4: 011b lsls r3, r3, #4
80023c6: 1a9b subs r3, r3, r2
80023c8: 009b lsls r3, r3, #2
80023ca: 440b add r3, r1
80023cc: 334d adds r3, #77 @ 0x4d
80023ce: 2209 movs r2, #9
80023d0: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80023d2: 687b ldr r3, [r7, #4]
80023d4: 681b ldr r3, [r3, #0]
80023d6: 78fa ldrb r2, [r7, #3]
80023d8: 4611 mov r1, r2
80023da: 4618 mov r0, r3
80023dc: f004 f94a bl 8006674 <USB_HC_Halt>
80023e0: e025 b.n 800242e <HCD_HC_IN_IRQHandler+0x1a2>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
80023e2: 687b ldr r3, [r7, #4]
80023e4: 681b ldr r3, [r3, #0]
80023e6: 78fa ldrb r2, [r7, #3]
80023e8: 4611 mov r1, r2
80023ea: 4618 mov r0, r3
80023ec: f004 f8c5 bl 800657a <USB_ReadChInterrupts>
80023f0: 4603 mov r3, r0
80023f2: f003 0380 and.w r3, r3, #128 @ 0x80
80023f6: 2b80 cmp r3, #128 @ 0x80
80023f8: d119 bne.n 800242e <HCD_HC_IN_IRQHandler+0x1a2>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
80023fa: 78fb ldrb r3, [r7, #3]
80023fc: 015a lsls r2, r3, #5
80023fe: 693b ldr r3, [r7, #16]
8002400: 4413 add r3, r2
8002402: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002406: 461a mov r2, r3
8002408: 2380 movs r3, #128 @ 0x80
800240a: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_XACTERR;
800240c: 78fa ldrb r2, [r7, #3]
800240e: 6879 ldr r1, [r7, #4]
8002410: 4613 mov r3, r2
8002412: 011b lsls r3, r3, #4
8002414: 1a9b subs r3, r3, r2
8002416: 009b lsls r3, r3, #2
8002418: 440b add r3, r1
800241a: 334d adds r3, #77 @ 0x4d
800241c: 2207 movs r2, #7
800241e: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002420: 687b ldr r3, [r7, #4]
8002422: 681b ldr r3, [r3, #0]
8002424: 78fa ldrb r2, [r7, #3]
8002426: 4611 mov r1, r2
8002428: 4618 mov r0, r3
800242a: f004 f923 bl 8006674 <USB_HC_Halt>
else
{
/* ... */
}
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
800242e: 687b ldr r3, [r7, #4]
8002430: 681b ldr r3, [r3, #0]
8002432: 78fa ldrb r2, [r7, #3]
8002434: 4611 mov r1, r2
8002436: 4618 mov r0, r3
8002438: f004 f89f bl 800657a <USB_ReadChInterrupts>
800243c: 4603 mov r3, r0
800243e: f403 7300 and.w r3, r3, #512 @ 0x200
8002442: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002446: d112 bne.n 800246e <HCD_HC_IN_IRQHandler+0x1e2>
{
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002448: 687b ldr r3, [r7, #4]
800244a: 681b ldr r3, [r3, #0]
800244c: 78fa ldrb r2, [r7, #3]
800244e: 4611 mov r1, r2
8002450: 4618 mov r0, r3
8002452: f004 f90f bl 8006674 <USB_HC_Halt>
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
8002456: 78fb ldrb r3, [r7, #3]
8002458: 015a lsls r2, r3, #5
800245a: 693b ldr r3, [r7, #16]
800245c: 4413 add r3, r2
800245e: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002462: 461a mov r2, r3
8002464: f44f 7300 mov.w r3, #512 @ 0x200
8002468: 6093 str r3, [r2, #8]
800246a: f000 bd75 b.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
800246e: 687b ldr r3, [r7, #4]
8002470: 681b ldr r3, [r3, #0]
8002472: 78fa ldrb r2, [r7, #3]
8002474: 4611 mov r1, r2
8002476: 4618 mov r0, r3
8002478: f004 f87f bl 800657a <USB_ReadChInterrupts>
800247c: 4603 mov r3, r0
800247e: f003 0301 and.w r3, r3, #1
8002482: 2b01 cmp r3, #1
8002484: f040 8128 bne.w 80026d8 <HCD_HC_IN_IRQHandler+0x44c>
{
/* Clear any pending ACK IT */
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
8002488: 78fb ldrb r3, [r7, #3]
800248a: 015a lsls r2, r3, #5
800248c: 693b ldr r3, [r7, #16]
800248e: 4413 add r3, r2
8002490: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002494: 461a mov r2, r3
8002496: 2320 movs r3, #32
8002498: 6093 str r3, [r2, #8]
if (hhcd->hc[chnum].do_csplit == 1U)
800249a: 78fa ldrb r2, [r7, #3]
800249c: 6879 ldr r1, [r7, #4]
800249e: 4613 mov r3, r2
80024a0: 011b lsls r3, r3, #4
80024a2: 1a9b subs r3, r3, r2
80024a4: 009b lsls r3, r3, #2
80024a6: 440b add r3, r1
80024a8: 331b adds r3, #27
80024aa: 781b ldrb r3, [r3, #0]
80024ac: 2b01 cmp r3, #1
80024ae: d119 bne.n 80024e4 <HCD_HC_IN_IRQHandler+0x258>
{
hhcd->hc[chnum].do_csplit = 0U;
80024b0: 78fa ldrb r2, [r7, #3]
80024b2: 6879 ldr r1, [r7, #4]
80024b4: 4613 mov r3, r2
80024b6: 011b lsls r3, r3, #4
80024b8: 1a9b subs r3, r3, r2
80024ba: 009b lsls r3, r3, #2
80024bc: 440b add r3, r1
80024be: 331b adds r3, #27
80024c0: 2200 movs r2, #0
80024c2: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
80024c4: 78fb ldrb r3, [r7, #3]
80024c6: 015a lsls r2, r3, #5
80024c8: 693b ldr r3, [r7, #16]
80024ca: 4413 add r3, r2
80024cc: f503 63a0 add.w r3, r3, #1280 @ 0x500
80024d0: 685b ldr r3, [r3, #4]
80024d2: 78fa ldrb r2, [r7, #3]
80024d4: 0151 lsls r1, r2, #5
80024d6: 693a ldr r2, [r7, #16]
80024d8: 440a add r2, r1
80024da: f502 62a0 add.w r2, r2, #1280 @ 0x500
80024de: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80024e2: 6053 str r3, [r2, #4]
}
if (hhcd->Init.dma_enable != 0U)
80024e4: 687b ldr r3, [r7, #4]
80024e6: 799b ldrb r3, [r3, #6]
80024e8: 2b00 cmp r3, #0
80024ea: d01b beq.n 8002524 <HCD_HC_IN_IRQHandler+0x298>
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
80024ec: 78fa ldrb r2, [r7, #3]
80024ee: 6879 ldr r1, [r7, #4]
80024f0: 4613 mov r3, r2
80024f2: 011b lsls r3, r3, #4
80024f4: 1a9b subs r3, r3, r2
80024f6: 009b lsls r3, r3, #2
80024f8: 440b add r3, r1
80024fa: 3330 adds r3, #48 @ 0x30
80024fc: 6819 ldr r1, [r3, #0]
80024fe: 78fb ldrb r3, [r7, #3]
8002500: 015a lsls r2, r3, #5
8002502: 693b ldr r3, [r7, #16]
8002504: 4413 add r3, r2
8002506: f503 63a0 add.w r3, r3, #1280 @ 0x500
800250a: 691b ldr r3, [r3, #16]
800250c: f3c3 0312 ubfx r3, r3, #0, #19
8002510: 78fa ldrb r2, [r7, #3]
8002512: 1ac9 subs r1, r1, r3
8002514: 6878 ldr r0, [r7, #4]
8002516: 4613 mov r3, r2
8002518: 011b lsls r3, r3, #4
800251a: 1a9b subs r3, r3, r2
800251c: 009b lsls r3, r3, #2
800251e: 4403 add r3, r0
8002520: 3338 adds r3, #56 @ 0x38
8002522: 6019 str r1, [r3, #0]
}
hhcd->hc[chnum].state = HC_XFRC;
8002524: 78fa ldrb r2, [r7, #3]
8002526: 6879 ldr r1, [r7, #4]
8002528: 4613 mov r3, r2
800252a: 011b lsls r3, r3, #4
800252c: 1a9b subs r3, r3, r2
800252e: 009b lsls r3, r3, #2
8002530: 440b add r3, r1
8002532: 334d adds r3, #77 @ 0x4d
8002534: 2201 movs r2, #1
8002536: 701a strb r2, [r3, #0]
hhcd->hc[chnum].ErrCnt = 0U;
8002538: 78fa ldrb r2, [r7, #3]
800253a: 6879 ldr r1, [r7, #4]
800253c: 4613 mov r3, r2
800253e: 011b lsls r3, r3, #4
8002540: 1a9b subs r3, r3, r2
8002542: 009b lsls r3, r3, #2
8002544: 440b add r3, r1
8002546: 3344 adds r3, #68 @ 0x44
8002548: 2200 movs r2, #0
800254a: 601a str r2, [r3, #0]
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
800254c: 78fb ldrb r3, [r7, #3]
800254e: 015a lsls r2, r3, #5
8002550: 693b ldr r3, [r7, #16]
8002552: 4413 add r3, r2
8002554: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002558: 461a mov r2, r3
800255a: 2301 movs r3, #1
800255c: 6093 str r3, [r2, #8]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
800255e: 78fa ldrb r2, [r7, #3]
8002560: 6879 ldr r1, [r7, #4]
8002562: 4613 mov r3, r2
8002564: 011b lsls r3, r3, #4
8002566: 1a9b subs r3, r3, r2
8002568: 009b lsls r3, r3, #2
800256a: 440b add r3, r1
800256c: 3326 adds r3, #38 @ 0x26
800256e: 781b ldrb r3, [r3, #0]
8002570: 2b00 cmp r3, #0
8002572: d00a beq.n 800258a <HCD_HC_IN_IRQHandler+0x2fe>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
8002574: 78fa ldrb r2, [r7, #3]
8002576: 6879 ldr r1, [r7, #4]
8002578: 4613 mov r3, r2
800257a: 011b lsls r3, r3, #4
800257c: 1a9b subs r3, r3, r2
800257e: 009b lsls r3, r3, #2
8002580: 440b add r3, r1
8002582: 3326 adds r3, #38 @ 0x26
8002584: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002586: 2b02 cmp r3, #2
8002588: d110 bne.n 80025ac <HCD_HC_IN_IRQHandler+0x320>
{
(void)USB_HC_Halt(hhcd->Instance, chnum);
800258a: 687b ldr r3, [r7, #4]
800258c: 681b ldr r3, [r3, #0]
800258e: 78fa ldrb r2, [r7, #3]
8002590: 4611 mov r1, r2
8002592: 4618 mov r0, r3
8002594: f004 f86e bl 8006674 <USB_HC_Halt>
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
8002598: 78fb ldrb r3, [r7, #3]
800259a: 015a lsls r2, r3, #5
800259c: 693b ldr r3, [r7, #16]
800259e: 4413 add r3, r2
80025a0: f503 63a0 add.w r3, r3, #1280 @ 0x500
80025a4: 461a mov r2, r3
80025a6: 2310 movs r3, #16
80025a8: 6093 str r3, [r2, #8]
80025aa: e03d b.n 8002628 <HCD_HC_IN_IRQHandler+0x39c>
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
80025ac: 78fa ldrb r2, [r7, #3]
80025ae: 6879 ldr r1, [r7, #4]
80025b0: 4613 mov r3, r2
80025b2: 011b lsls r3, r3, #4
80025b4: 1a9b subs r3, r3, r2
80025b6: 009b lsls r3, r3, #2
80025b8: 440b add r3, r1
80025ba: 3326 adds r3, #38 @ 0x26
80025bc: 781b ldrb r3, [r3, #0]
80025be: 2b03 cmp r3, #3
80025c0: d00a beq.n 80025d8 <HCD_HC_IN_IRQHandler+0x34c>
(hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
80025c2: 78fa ldrb r2, [r7, #3]
80025c4: 6879 ldr r1, [r7, #4]
80025c6: 4613 mov r3, r2
80025c8: 011b lsls r3, r3, #4
80025ca: 1a9b subs r3, r3, r2
80025cc: 009b lsls r3, r3, #2
80025ce: 440b add r3, r1
80025d0: 3326 adds r3, #38 @ 0x26
80025d2: 781b ldrb r3, [r3, #0]
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
80025d4: 2b01 cmp r3, #1
80025d6: d127 bne.n 8002628 <HCD_HC_IN_IRQHandler+0x39c>
{
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
80025d8: 78fb ldrb r3, [r7, #3]
80025da: 015a lsls r2, r3, #5
80025dc: 693b ldr r3, [r7, #16]
80025de: 4413 add r3, r2
80025e0: f503 63a0 add.w r3, r3, #1280 @ 0x500
80025e4: 681b ldr r3, [r3, #0]
80025e6: 78fa ldrb r2, [r7, #3]
80025e8: 0151 lsls r1, r2, #5
80025ea: 693a ldr r2, [r7, #16]
80025ec: 440a add r2, r1
80025ee: f502 62a0 add.w r2, r2, #1280 @ 0x500
80025f2: f043 5300 orr.w r3, r3, #536870912 @ 0x20000000
80025f6: 6013 str r3, [r2, #0]
hhcd->hc[chnum].urb_state = URB_DONE;
80025f8: 78fa ldrb r2, [r7, #3]
80025fa: 6879 ldr r1, [r7, #4]
80025fc: 4613 mov r3, r2
80025fe: 011b lsls r3, r3, #4
8002600: 1a9b subs r3, r3, r2
8002602: 009b lsls r3, r3, #2
8002604: 440b add r3, r1
8002606: 334c adds r3, #76 @ 0x4c
8002608: 2201 movs r2, #1
800260a: 701a strb r2, [r3, #0]
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
800260c: 78fa ldrb r2, [r7, #3]
800260e: 6879 ldr r1, [r7, #4]
8002610: 4613 mov r3, r2
8002612: 011b lsls r3, r3, #4
8002614: 1a9b subs r3, r3, r2
8002616: 009b lsls r3, r3, #2
8002618: 440b add r3, r1
800261a: 334c adds r3, #76 @ 0x4c
800261c: 781a ldrb r2, [r3, #0]
800261e: 78fb ldrb r3, [r7, #3]
8002620: 4619 mov r1, r3
8002622: 6878 ldr r0, [r7, #4]
8002624: f005 fbbe bl 8007da4 <HAL_HCD_HC_NotifyURBChange_Callback>
else
{
/* ... */
}
if (hhcd->Init.dma_enable == 1U)
8002628: 687b ldr r3, [r7, #4]
800262a: 799b ldrb r3, [r3, #6]
800262c: 2b01 cmp r3, #1
800262e: d13b bne.n 80026a8 <HCD_HC_IN_IRQHandler+0x41c>
{
if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
8002630: 78fa ldrb r2, [r7, #3]
8002632: 6879 ldr r1, [r7, #4]
8002634: 4613 mov r3, r2
8002636: 011b lsls r3, r3, #4
8002638: 1a9b subs r3, r3, r2
800263a: 009b lsls r3, r3, #2
800263c: 440b add r3, r1
800263e: 3338 adds r3, #56 @ 0x38
8002640: 6819 ldr r1, [r3, #0]
8002642: 78fa ldrb r2, [r7, #3]
8002644: 6878 ldr r0, [r7, #4]
8002646: 4613 mov r3, r2
8002648: 011b lsls r3, r3, #4
800264a: 1a9b subs r3, r3, r2
800264c: 009b lsls r3, r3, #2
800264e: 4403 add r3, r0
8002650: 3328 adds r3, #40 @ 0x28
8002652: 881b ldrh r3, [r3, #0]
8002654: 440b add r3, r1
8002656: 1e59 subs r1, r3, #1
8002658: 78fa ldrb r2, [r7, #3]
800265a: 6878 ldr r0, [r7, #4]
800265c: 4613 mov r3, r2
800265e: 011b lsls r3, r3, #4
8002660: 1a9b subs r3, r3, r2
8002662: 009b lsls r3, r3, #2
8002664: 4403 add r3, r0
8002666: 3328 adds r3, #40 @ 0x28
8002668: 881b ldrh r3, [r3, #0]
800266a: fbb1 f3f3 udiv r3, r1, r3
800266e: f003 0301 and.w r3, r3, #1
8002672: 2b00 cmp r3, #0
8002674: f000 8470 beq.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
{
hhcd->hc[chnum].toggle_in ^= 1U;
8002678: 78fa ldrb r2, [r7, #3]
800267a: 6879 ldr r1, [r7, #4]
800267c: 4613 mov r3, r2
800267e: 011b lsls r3, r3, #4
8002680: 1a9b subs r3, r3, r2
8002682: 009b lsls r3, r3, #2
8002684: 440b add r3, r1
8002686: 333c adds r3, #60 @ 0x3c
8002688: 781b ldrb r3, [r3, #0]
800268a: 78fa ldrb r2, [r7, #3]
800268c: f083 0301 eor.w r3, r3, #1
8002690: b2d8 uxtb r0, r3
8002692: 6879 ldr r1, [r7, #4]
8002694: 4613 mov r3, r2
8002696: 011b lsls r3, r3, #4
8002698: 1a9b subs r3, r3, r2
800269a: 009b lsls r3, r3, #2
800269c: 440b add r3, r1
800269e: 333c adds r3, #60 @ 0x3c
80026a0: 4602 mov r2, r0
80026a2: 701a strb r2, [r3, #0]
80026a4: f000 bc58 b.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
}
}
else
{
hhcd->hc[chnum].toggle_in ^= 1U;
80026a8: 78fa ldrb r2, [r7, #3]
80026aa: 6879 ldr r1, [r7, #4]
80026ac: 4613 mov r3, r2
80026ae: 011b lsls r3, r3, #4
80026b0: 1a9b subs r3, r3, r2
80026b2: 009b lsls r3, r3, #2
80026b4: 440b add r3, r1
80026b6: 333c adds r3, #60 @ 0x3c
80026b8: 781b ldrb r3, [r3, #0]
80026ba: 78fa ldrb r2, [r7, #3]
80026bc: f083 0301 eor.w r3, r3, #1
80026c0: b2d8 uxtb r0, r3
80026c2: 6879 ldr r1, [r7, #4]
80026c4: 4613 mov r3, r2
80026c6: 011b lsls r3, r3, #4
80026c8: 1a9b subs r3, r3, r2
80026ca: 009b lsls r3, r3, #2
80026cc: 440b add r3, r1
80026ce: 333c adds r3, #60 @ 0x3c
80026d0: 4602 mov r2, r0
80026d2: 701a strb r2, [r3, #0]
80026d4: f000 bc40 b.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
}
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
80026d8: 687b ldr r3, [r7, #4]
80026da: 681b ldr r3, [r3, #0]
80026dc: 78fa ldrb r2, [r7, #3]
80026de: 4611 mov r1, r2
80026e0: 4618 mov r0, r3
80026e2: f003 ff4a bl 800657a <USB_ReadChInterrupts>
80026e6: 4603 mov r3, r0
80026e8: f003 0320 and.w r3, r3, #32
80026ec: 2b20 cmp r3, #32
80026ee: d131 bne.n 8002754 <HCD_HC_IN_IRQHandler+0x4c8>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
80026f0: 78fb ldrb r3, [r7, #3]
80026f2: 015a lsls r2, r3, #5
80026f4: 693b ldr r3, [r7, #16]
80026f6: 4413 add r3, r2
80026f8: f503 63a0 add.w r3, r3, #1280 @ 0x500
80026fc: 461a mov r2, r3
80026fe: 2320 movs r3, #32
8002700: 6093 str r3, [r2, #8]
if (hhcd->hc[chnum].do_ssplit == 1U)
8002702: 78fa ldrb r2, [r7, #3]
8002704: 6879 ldr r1, [r7, #4]
8002706: 4613 mov r3, r2
8002708: 011b lsls r3, r3, #4
800270a: 1a9b subs r3, r3, r2
800270c: 009b lsls r3, r3, #2
800270e: 440b add r3, r1
8002710: 331a adds r3, #26
8002712: 781b ldrb r3, [r3, #0]
8002714: 2b01 cmp r3, #1
8002716: f040 841f bne.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
{
hhcd->hc[chnum].do_csplit = 1U;
800271a: 78fa ldrb r2, [r7, #3]
800271c: 6879 ldr r1, [r7, #4]
800271e: 4613 mov r3, r2
8002720: 011b lsls r3, r3, #4
8002722: 1a9b subs r3, r3, r2
8002724: 009b lsls r3, r3, #2
8002726: 440b add r3, r1
8002728: 331b adds r3, #27
800272a: 2201 movs r2, #1
800272c: 701a strb r2, [r3, #0]
hhcd->hc[chnum].state = HC_ACK;
800272e: 78fa ldrb r2, [r7, #3]
8002730: 6879 ldr r1, [r7, #4]
8002732: 4613 mov r3, r2
8002734: 011b lsls r3, r3, #4
8002736: 1a9b subs r3, r3, r2
8002738: 009b lsls r3, r3, #2
800273a: 440b add r3, r1
800273c: 334d adds r3, #77 @ 0x4d
800273e: 2203 movs r2, #3
8002740: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: 78fa ldrb r2, [r7, #3]
8002748: 4611 mov r1, r2
800274a: 4618 mov r0, r3
800274c: f003 ff92 bl 8006674 <USB_HC_Halt>
8002750: f000 bc02 b.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
}
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
8002754: 687b ldr r3, [r7, #4]
8002756: 681b ldr r3, [r3, #0]
8002758: 78fa ldrb r2, [r7, #3]
800275a: 4611 mov r1, r2
800275c: 4618 mov r0, r3
800275e: f003 ff0c bl 800657a <USB_ReadChInterrupts>
8002762: 4603 mov r3, r0
8002764: f003 0302 and.w r3, r3, #2
8002768: 2b02 cmp r3, #2
800276a: f040 8305 bne.w 8002d78 <HCD_HC_IN_IRQHandler+0xaec>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
800276e: 78fb ldrb r3, [r7, #3]
8002770: 015a lsls r2, r3, #5
8002772: 693b ldr r3, [r7, #16]
8002774: 4413 add r3, r2
8002776: f503 63a0 add.w r3, r3, #1280 @ 0x500
800277a: 461a mov r2, r3
800277c: 2302 movs r3, #2
800277e: 6093 str r3, [r2, #8]
if (hhcd->hc[chnum].state == HC_XFRC)
8002780: 78fa ldrb r2, [r7, #3]
8002782: 6879 ldr r1, [r7, #4]
8002784: 4613 mov r3, r2
8002786: 011b lsls r3, r3, #4
8002788: 1a9b subs r3, r3, r2
800278a: 009b lsls r3, r3, #2
800278c: 440b add r3, r1
800278e: 334d adds r3, #77 @ 0x4d
8002790: 781b ldrb r3, [r3, #0]
8002792: 2b01 cmp r3, #1
8002794: d114 bne.n 80027c0 <HCD_HC_IN_IRQHandler+0x534>
{
hhcd->hc[chnum].state = HC_HALTED;
8002796: 78fa ldrb r2, [r7, #3]
8002798: 6879 ldr r1, [r7, #4]
800279a: 4613 mov r3, r2
800279c: 011b lsls r3, r3, #4
800279e: 1a9b subs r3, r3, r2
80027a0: 009b lsls r3, r3, #2
80027a2: 440b add r3, r1
80027a4: 334d adds r3, #77 @ 0x4d
80027a6: 2202 movs r2, #2
80027a8: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_DONE;
80027aa: 78fa ldrb r2, [r7, #3]
80027ac: 6879 ldr r1, [r7, #4]
80027ae: 4613 mov r3, r2
80027b0: 011b lsls r3, r3, #4
80027b2: 1a9b subs r3, r3, r2
80027b4: 009b lsls r3, r3, #2
80027b6: 440b add r3, r1
80027b8: 334c adds r3, #76 @ 0x4c
80027ba: 2201 movs r2, #1
80027bc: 701a strb r2, [r3, #0]
80027be: e2cc b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
else if (hhcd->hc[chnum].state == HC_STALL)
80027c0: 78fa ldrb r2, [r7, #3]
80027c2: 6879 ldr r1, [r7, #4]
80027c4: 4613 mov r3, r2
80027c6: 011b lsls r3, r3, #4
80027c8: 1a9b subs r3, r3, r2
80027ca: 009b lsls r3, r3, #2
80027cc: 440b add r3, r1
80027ce: 334d adds r3, #77 @ 0x4d
80027d0: 781b ldrb r3, [r3, #0]
80027d2: 2b06 cmp r3, #6
80027d4: d114 bne.n 8002800 <HCD_HC_IN_IRQHandler+0x574>
{
hhcd->hc[chnum].state = HC_HALTED;
80027d6: 78fa ldrb r2, [r7, #3]
80027d8: 6879 ldr r1, [r7, #4]
80027da: 4613 mov r3, r2
80027dc: 011b lsls r3, r3, #4
80027de: 1a9b subs r3, r3, r2
80027e0: 009b lsls r3, r3, #2
80027e2: 440b add r3, r1
80027e4: 334d adds r3, #77 @ 0x4d
80027e6: 2202 movs r2, #2
80027e8: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_STALL;
80027ea: 78fa ldrb r2, [r7, #3]
80027ec: 6879 ldr r1, [r7, #4]
80027ee: 4613 mov r3, r2
80027f0: 011b lsls r3, r3, #4
80027f2: 1a9b subs r3, r3, r2
80027f4: 009b lsls r3, r3, #2
80027f6: 440b add r3, r1
80027f8: 334c adds r3, #76 @ 0x4c
80027fa: 2205 movs r2, #5
80027fc: 701a strb r2, [r3, #0]
80027fe: e2ac b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
8002800: 78fa ldrb r2, [r7, #3]
8002802: 6879 ldr r1, [r7, #4]
8002804: 4613 mov r3, r2
8002806: 011b lsls r3, r3, #4
8002808: 1a9b subs r3, r3, r2
800280a: 009b lsls r3, r3, #2
800280c: 440b add r3, r1
800280e: 334d adds r3, #77 @ 0x4d
8002810: 781b ldrb r3, [r3, #0]
8002812: 2b07 cmp r3, #7
8002814: d00b beq.n 800282e <HCD_HC_IN_IRQHandler+0x5a2>
(hhcd->hc[chnum].state == HC_DATATGLERR))
8002816: 78fa ldrb r2, [r7, #3]
8002818: 6879 ldr r1, [r7, #4]
800281a: 4613 mov r3, r2
800281c: 011b lsls r3, r3, #4
800281e: 1a9b subs r3, r3, r2
8002820: 009b lsls r3, r3, #2
8002822: 440b add r3, r1
8002824: 334d adds r3, #77 @ 0x4d
8002826: 781b ldrb r3, [r3, #0]
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
8002828: 2b09 cmp r3, #9
800282a: f040 80a6 bne.w 800297a <HCD_HC_IN_IRQHandler+0x6ee>
{
hhcd->hc[chnum].state = HC_HALTED;
800282e: 78fa ldrb r2, [r7, #3]
8002830: 6879 ldr r1, [r7, #4]
8002832: 4613 mov r3, r2
8002834: 011b lsls r3, r3, #4
8002836: 1a9b subs r3, r3, r2
8002838: 009b lsls r3, r3, #2
800283a: 440b add r3, r1
800283c: 334d adds r3, #77 @ 0x4d
800283e: 2202 movs r2, #2
8002840: 701a strb r2, [r3, #0]
hhcd->hc[chnum].ErrCnt++;
8002842: 78fa ldrb r2, [r7, #3]
8002844: 6879 ldr r1, [r7, #4]
8002846: 4613 mov r3, r2
8002848: 011b lsls r3, r3, #4
800284a: 1a9b subs r3, r3, r2
800284c: 009b lsls r3, r3, #2
800284e: 440b add r3, r1
8002850: 3344 adds r3, #68 @ 0x44
8002852: 681b ldr r3, [r3, #0]
8002854: 1c59 adds r1, r3, #1
8002856: 6878 ldr r0, [r7, #4]
8002858: 4613 mov r3, r2
800285a: 011b lsls r3, r3, #4
800285c: 1a9b subs r3, r3, r2
800285e: 009b lsls r3, r3, #2
8002860: 4403 add r3, r0
8002862: 3344 adds r3, #68 @ 0x44
8002864: 6019 str r1, [r3, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
8002866: 78fa ldrb r2, [r7, #3]
8002868: 6879 ldr r1, [r7, #4]
800286a: 4613 mov r3, r2
800286c: 011b lsls r3, r3, #4
800286e: 1a9b subs r3, r3, r2
8002870: 009b lsls r3, r3, #2
8002872: 440b add r3, r1
8002874: 3344 adds r3, #68 @ 0x44
8002876: 681b ldr r3, [r3, #0]
8002878: 2b02 cmp r3, #2
800287a: d943 bls.n 8002904 <HCD_HC_IN_IRQHandler+0x678>
{
hhcd->hc[chnum].ErrCnt = 0U;
800287c: 78fa ldrb r2, [r7, #3]
800287e: 6879 ldr r1, [r7, #4]
8002880: 4613 mov r3, r2
8002882: 011b lsls r3, r3, #4
8002884: 1a9b subs r3, r3, r2
8002886: 009b lsls r3, r3, #2
8002888: 440b add r3, r1
800288a: 3344 adds r3, #68 @ 0x44
800288c: 2200 movs r2, #0
800288e: 601a str r2, [r3, #0]
if (hhcd->hc[chnum].do_ssplit == 1U)
8002890: 78fa ldrb r2, [r7, #3]
8002892: 6879 ldr r1, [r7, #4]
8002894: 4613 mov r3, r2
8002896: 011b lsls r3, r3, #4
8002898: 1a9b subs r3, r3, r2
800289a: 009b lsls r3, r3, #2
800289c: 440b add r3, r1
800289e: 331a adds r3, #26
80028a0: 781b ldrb r3, [r3, #0]
80028a2: 2b01 cmp r3, #1
80028a4: d123 bne.n 80028ee <HCD_HC_IN_IRQHandler+0x662>
{
hhcd->hc[chnum].do_csplit = 0U;
80028a6: 78fa ldrb r2, [r7, #3]
80028a8: 6879 ldr r1, [r7, #4]
80028aa: 4613 mov r3, r2
80028ac: 011b lsls r3, r3, #4
80028ae: 1a9b subs r3, r3, r2
80028b0: 009b lsls r3, r3, #2
80028b2: 440b add r3, r1
80028b4: 331b adds r3, #27
80028b6: 2200 movs r2, #0
80028b8: 701a strb r2, [r3, #0]
hhcd->hc[chnum].ep_ss_schedule = 0U;
80028ba: 78fa ldrb r2, [r7, #3]
80028bc: 6879 ldr r1, [r7, #4]
80028be: 4613 mov r3, r2
80028c0: 011b lsls r3, r3, #4
80028c2: 1a9b subs r3, r3, r2
80028c4: 009b lsls r3, r3, #2
80028c6: 440b add r3, r1
80028c8: 331c adds r3, #28
80028ca: 2200 movs r2, #0
80028cc: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
80028ce: 78fb ldrb r3, [r7, #3]
80028d0: 015a lsls r2, r3, #5
80028d2: 693b ldr r3, [r7, #16]
80028d4: 4413 add r3, r2
80028d6: f503 63a0 add.w r3, r3, #1280 @ 0x500
80028da: 685b ldr r3, [r3, #4]
80028dc: 78fa ldrb r2, [r7, #3]
80028de: 0151 lsls r1, r2, #5
80028e0: 693a ldr r2, [r7, #16]
80028e2: 440a add r2, r1
80028e4: f502 62a0 add.w r2, r2, #1280 @ 0x500
80028e8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80028ec: 6053 str r3, [r2, #4]
}
hhcd->hc[chnum].urb_state = URB_ERROR;
80028ee: 78fa ldrb r2, [r7, #3]
80028f0: 6879 ldr r1, [r7, #4]
80028f2: 4613 mov r3, r2
80028f4: 011b lsls r3, r3, #4
80028f6: 1a9b subs r3, r3, r2
80028f8: 009b lsls r3, r3, #2
80028fa: 440b add r3, r1
80028fc: 334c adds r3, #76 @ 0x4c
80028fe: 2204 movs r2, #4
8002900: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
8002902: e229 b.n 8002d58 <HCD_HC_IN_IRQHandler+0xacc>
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8002904: 78fa ldrb r2, [r7, #3]
8002906: 6879 ldr r1, [r7, #4]
8002908: 4613 mov r3, r2
800290a: 011b lsls r3, r3, #4
800290c: 1a9b subs r3, r3, r2
800290e: 009b lsls r3, r3, #2
8002910: 440b add r3, r1
8002912: 334c adds r3, #76 @ 0x4c
8002914: 2202 movs r2, #2
8002916: 701a strb r2, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002918: 78fa ldrb r2, [r7, #3]
800291a: 6879 ldr r1, [r7, #4]
800291c: 4613 mov r3, r2
800291e: 011b lsls r3, r3, #4
8002920: 1a9b subs r3, r3, r2
8002922: 009b lsls r3, r3, #2
8002924: 440b add r3, r1
8002926: 3326 adds r3, #38 @ 0x26
8002928: 781b ldrb r3, [r3, #0]
800292a: 2b00 cmp r3, #0
800292c: d00b beq.n 8002946 <HCD_HC_IN_IRQHandler+0x6ba>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
800292e: 78fa ldrb r2, [r7, #3]
8002930: 6879 ldr r1, [r7, #4]
8002932: 4613 mov r3, r2
8002934: 011b lsls r3, r3, #4
8002936: 1a9b subs r3, r3, r2
8002938: 009b lsls r3, r3, #2
800293a: 440b add r3, r1
800293c: 3326 adds r3, #38 @ 0x26
800293e: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002940: 2b02 cmp r3, #2
8002942: f040 8209 bne.w 8002d58 <HCD_HC_IN_IRQHandler+0xacc>
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
8002946: 78fb ldrb r3, [r7, #3]
8002948: 015a lsls r2, r3, #5
800294a: 693b ldr r3, [r7, #16]
800294c: 4413 add r3, r2
800294e: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002952: 681b ldr r3, [r3, #0]
8002954: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8002956: 68fb ldr r3, [r7, #12]
8002958: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
800295c: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
800295e: 68fb ldr r3, [r7, #12]
8002960: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8002964: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
8002966: 78fb ldrb r3, [r7, #3]
8002968: 015a lsls r2, r3, #5
800296a: 693b ldr r3, [r7, #16]
800296c: 4413 add r3, r2
800296e: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002972: 461a mov r2, r3
8002974: 68fb ldr r3, [r7, #12]
8002976: 6013 str r3, [r2, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
8002978: e1ee b.n 8002d58 <HCD_HC_IN_IRQHandler+0xacc>
}
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
800297a: 78fa ldrb r2, [r7, #3]
800297c: 6879 ldr r1, [r7, #4]
800297e: 4613 mov r3, r2
8002980: 011b lsls r3, r3, #4
8002982: 1a9b subs r3, r3, r2
8002984: 009b lsls r3, r3, #2
8002986: 440b add r3, r1
8002988: 334d adds r3, #77 @ 0x4d
800298a: 781b ldrb r3, [r3, #0]
800298c: 2b05 cmp r3, #5
800298e: f040 80c8 bne.w 8002b22 <HCD_HC_IN_IRQHandler+0x896>
{
hhcd->hc[chnum].state = HC_HALTED;
8002992: 78fa ldrb r2, [r7, #3]
8002994: 6879 ldr r1, [r7, #4]
8002996: 4613 mov r3, r2
8002998: 011b lsls r3, r3, #4
800299a: 1a9b subs r3, r3, r2
800299c: 009b lsls r3, r3, #2
800299e: 440b add r3, r1
80029a0: 334d adds r3, #77 @ 0x4d
80029a2: 2202 movs r2, #2
80029a4: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_csplit == 1U)
80029a6: 78fa ldrb r2, [r7, #3]
80029a8: 6879 ldr r1, [r7, #4]
80029aa: 4613 mov r3, r2
80029ac: 011b lsls r3, r3, #4
80029ae: 1a9b subs r3, r3, r2
80029b0: 009b lsls r3, r3, #2
80029b2: 440b add r3, r1
80029b4: 331b adds r3, #27
80029b6: 781b ldrb r3, [r3, #0]
80029b8: 2b01 cmp r3, #1
80029ba: f040 81ce bne.w 8002d5a <HCD_HC_IN_IRQHandler+0xace>
{
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
80029be: 78fa ldrb r2, [r7, #3]
80029c0: 6879 ldr r1, [r7, #4]
80029c2: 4613 mov r3, r2
80029c4: 011b lsls r3, r3, #4
80029c6: 1a9b subs r3, r3, r2
80029c8: 009b lsls r3, r3, #2
80029ca: 440b add r3, r1
80029cc: 3326 adds r3, #38 @ 0x26
80029ce: 781b ldrb r3, [r3, #0]
80029d0: 2b03 cmp r3, #3
80029d2: d16b bne.n 8002aac <HCD_HC_IN_IRQHandler+0x820>
{
hhcd->hc[chnum].NyetErrCnt++;
80029d4: 78fa ldrb r2, [r7, #3]
80029d6: 6879 ldr r1, [r7, #4]
80029d8: 4613 mov r3, r2
80029da: 011b lsls r3, r3, #4
80029dc: 1a9b subs r3, r3, r2
80029de: 009b lsls r3, r3, #2
80029e0: 440b add r3, r1
80029e2: 3348 adds r3, #72 @ 0x48
80029e4: 681b ldr r3, [r3, #0]
80029e6: 1c59 adds r1, r3, #1
80029e8: 6878 ldr r0, [r7, #4]
80029ea: 4613 mov r3, r2
80029ec: 011b lsls r3, r3, #4
80029ee: 1a9b subs r3, r3, r2
80029f0: 009b lsls r3, r3, #2
80029f2: 4403 add r3, r0
80029f4: 3348 adds r3, #72 @ 0x48
80029f6: 6019 str r1, [r3, #0]
if (hhcd->hc[chnum].NyetErrCnt > 2U)
80029f8: 78fa ldrb r2, [r7, #3]
80029fa: 6879 ldr r1, [r7, #4]
80029fc: 4613 mov r3, r2
80029fe: 011b lsls r3, r3, #4
8002a00: 1a9b subs r3, r3, r2
8002a02: 009b lsls r3, r3, #2
8002a04: 440b add r3, r1
8002a06: 3348 adds r3, #72 @ 0x48
8002a08: 681b ldr r3, [r3, #0]
8002a0a: 2b02 cmp r3, #2
8002a0c: d943 bls.n 8002a96 <HCD_HC_IN_IRQHandler+0x80a>
{
hhcd->hc[chnum].NyetErrCnt = 0U;
8002a0e: 78fa ldrb r2, [r7, #3]
8002a10: 6879 ldr r1, [r7, #4]
8002a12: 4613 mov r3, r2
8002a14: 011b lsls r3, r3, #4
8002a16: 1a9b subs r3, r3, r2
8002a18: 009b lsls r3, r3, #2
8002a1a: 440b add r3, r1
8002a1c: 3348 adds r3, #72 @ 0x48
8002a1e: 2200 movs r2, #0
8002a20: 601a str r2, [r3, #0]
hhcd->hc[chnum].do_csplit = 0U;
8002a22: 78fa ldrb r2, [r7, #3]
8002a24: 6879 ldr r1, [r7, #4]
8002a26: 4613 mov r3, r2
8002a28: 011b lsls r3, r3, #4
8002a2a: 1a9b subs r3, r3, r2
8002a2c: 009b lsls r3, r3, #2
8002a2e: 440b add r3, r1
8002a30: 331b adds r3, #27
8002a32: 2200 movs r2, #0
8002a34: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].ErrCnt < 3U)
8002a36: 78fa ldrb r2, [r7, #3]
8002a38: 6879 ldr r1, [r7, #4]
8002a3a: 4613 mov r3, r2
8002a3c: 011b lsls r3, r3, #4
8002a3e: 1a9b subs r3, r3, r2
8002a40: 009b lsls r3, r3, #2
8002a42: 440b add r3, r1
8002a44: 3344 adds r3, #68 @ 0x44
8002a46: 681b ldr r3, [r3, #0]
8002a48: 2b02 cmp r3, #2
8002a4a: d809 bhi.n 8002a60 <HCD_HC_IN_IRQHandler+0x7d4>
{
hhcd->hc[chnum].ep_ss_schedule = 1U;
8002a4c: 78fa ldrb r2, [r7, #3]
8002a4e: 6879 ldr r1, [r7, #4]
8002a50: 4613 mov r3, r2
8002a52: 011b lsls r3, r3, #4
8002a54: 1a9b subs r3, r3, r2
8002a56: 009b lsls r3, r3, #2
8002a58: 440b add r3, r1
8002a5a: 331c adds r3, #28
8002a5c: 2201 movs r2, #1
8002a5e: 701a strb r2, [r3, #0]
}
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
8002a60: 78fb ldrb r3, [r7, #3]
8002a62: 015a lsls r2, r3, #5
8002a64: 693b ldr r3, [r7, #16]
8002a66: 4413 add r3, r2
8002a68: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002a6c: 685b ldr r3, [r3, #4]
8002a6e: 78fa ldrb r2, [r7, #3]
8002a70: 0151 lsls r1, r2, #5
8002a72: 693a ldr r2, [r7, #16]
8002a74: 440a add r2, r1
8002a76: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002a7a: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002a7e: 6053 str r3, [r2, #4]
hhcd->hc[chnum].urb_state = URB_ERROR;
8002a80: 78fa ldrb r2, [r7, #3]
8002a82: 6879 ldr r1, [r7, #4]
8002a84: 4613 mov r3, r2
8002a86: 011b lsls r3, r3, #4
8002a88: 1a9b subs r3, r3, r2
8002a8a: 009b lsls r3, r3, #2
8002a8c: 440b add r3, r1
8002a8e: 334c adds r3, #76 @ 0x4c
8002a90: 2204 movs r2, #4
8002a92: 701a strb r2, [r3, #0]
8002a94: e014 b.n 8002ac0 <HCD_HC_IN_IRQHandler+0x834>
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8002a96: 78fa ldrb r2, [r7, #3]
8002a98: 6879 ldr r1, [r7, #4]
8002a9a: 4613 mov r3, r2
8002a9c: 011b lsls r3, r3, #4
8002a9e: 1a9b subs r3, r3, r2
8002aa0: 009b lsls r3, r3, #2
8002aa2: 440b add r3, r1
8002aa4: 334c adds r3, #76 @ 0x4c
8002aa6: 2202 movs r2, #2
8002aa8: 701a strb r2, [r3, #0]
8002aaa: e009 b.n 8002ac0 <HCD_HC_IN_IRQHandler+0x834>
}
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8002aac: 78fa ldrb r2, [r7, #3]
8002aae: 6879 ldr r1, [r7, #4]
8002ab0: 4613 mov r3, r2
8002ab2: 011b lsls r3, r3, #4
8002ab4: 1a9b subs r3, r3, r2
8002ab6: 009b lsls r3, r3, #2
8002ab8: 440b add r3, r1
8002aba: 334c adds r3, #76 @ 0x4c
8002abc: 2202 movs r2, #2
8002abe: 701a strb r2, [r3, #0]
}
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002ac0: 78fa ldrb r2, [r7, #3]
8002ac2: 6879 ldr r1, [r7, #4]
8002ac4: 4613 mov r3, r2
8002ac6: 011b lsls r3, r3, #4
8002ac8: 1a9b subs r3, r3, r2
8002aca: 009b lsls r3, r3, #2
8002acc: 440b add r3, r1
8002ace: 3326 adds r3, #38 @ 0x26
8002ad0: 781b ldrb r3, [r3, #0]
8002ad2: 2b00 cmp r3, #0
8002ad4: d00b beq.n 8002aee <HCD_HC_IN_IRQHandler+0x862>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
8002ad6: 78fa ldrb r2, [r7, #3]
8002ad8: 6879 ldr r1, [r7, #4]
8002ada: 4613 mov r3, r2
8002adc: 011b lsls r3, r3, #4
8002ade: 1a9b subs r3, r3, r2
8002ae0: 009b lsls r3, r3, #2
8002ae2: 440b add r3, r1
8002ae4: 3326 adds r3, #38 @ 0x26
8002ae6: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002ae8: 2b02 cmp r3, #2
8002aea: f040 8136 bne.w 8002d5a <HCD_HC_IN_IRQHandler+0xace>
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
8002aee: 78fb ldrb r3, [r7, #3]
8002af0: 015a lsls r2, r3, #5
8002af2: 693b ldr r3, [r7, #16]
8002af4: 4413 add r3, r2
8002af6: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002afa: 681b ldr r3, [r3, #0]
8002afc: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8002afe: 68fb ldr r3, [r7, #12]
8002b00: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8002b04: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8002b06: 68fb ldr r3, [r7, #12]
8002b08: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8002b0c: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
8002b0e: 78fb ldrb r3, [r7, #3]
8002b10: 015a lsls r2, r3, #5
8002b12: 693b ldr r3, [r7, #16]
8002b14: 4413 add r3, r2
8002b16: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002b1a: 461a mov r2, r3
8002b1c: 68fb ldr r3, [r7, #12]
8002b1e: 6013 str r3, [r2, #0]
8002b20: e11b b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
}
}
else if (hhcd->hc[chnum].state == HC_ACK)
8002b22: 78fa ldrb r2, [r7, #3]
8002b24: 6879 ldr r1, [r7, #4]
8002b26: 4613 mov r3, r2
8002b28: 011b lsls r3, r3, #4
8002b2a: 1a9b subs r3, r3, r2
8002b2c: 009b lsls r3, r3, #2
8002b2e: 440b add r3, r1
8002b30: 334d adds r3, #77 @ 0x4d
8002b32: 781b ldrb r3, [r3, #0]
8002b34: 2b03 cmp r3, #3
8002b36: f040 8081 bne.w 8002c3c <HCD_HC_IN_IRQHandler+0x9b0>
{
hhcd->hc[chnum].state = HC_HALTED;
8002b3a: 78fa ldrb r2, [r7, #3]
8002b3c: 6879 ldr r1, [r7, #4]
8002b3e: 4613 mov r3, r2
8002b40: 011b lsls r3, r3, #4
8002b42: 1a9b subs r3, r3, r2
8002b44: 009b lsls r3, r3, #2
8002b46: 440b add r3, r1
8002b48: 334d adds r3, #77 @ 0x4d
8002b4a: 2202 movs r2, #2
8002b4c: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_csplit == 1U)
8002b4e: 78fa ldrb r2, [r7, #3]
8002b50: 6879 ldr r1, [r7, #4]
8002b52: 4613 mov r3, r2
8002b54: 011b lsls r3, r3, #4
8002b56: 1a9b subs r3, r3, r2
8002b58: 009b lsls r3, r3, #2
8002b5a: 440b add r3, r1
8002b5c: 331b adds r3, #27
8002b5e: 781b ldrb r3, [r3, #0]
8002b60: 2b01 cmp r3, #1
8002b62: f040 80fa bne.w 8002d5a <HCD_HC_IN_IRQHandler+0xace>
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8002b66: 78fa ldrb r2, [r7, #3]
8002b68: 6879 ldr r1, [r7, #4]
8002b6a: 4613 mov r3, r2
8002b6c: 011b lsls r3, r3, #4
8002b6e: 1a9b subs r3, r3, r2
8002b70: 009b lsls r3, r3, #2
8002b72: 440b add r3, r1
8002b74: 334c adds r3, #76 @ 0x4c
8002b76: 2202 movs r2, #2
8002b78: 701a strb r2, [r3, #0]
/* Set Complete split and re-activate the channel */
USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
8002b7a: 78fb ldrb r3, [r7, #3]
8002b7c: 015a lsls r2, r3, #5
8002b7e: 693b ldr r3, [r7, #16]
8002b80: 4413 add r3, r2
8002b82: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002b86: 685b ldr r3, [r3, #4]
8002b88: 78fa ldrb r2, [r7, #3]
8002b8a: 0151 lsls r1, r2, #5
8002b8c: 693a ldr r2, [r7, #16]
8002b8e: 440a add r2, r1
8002b90: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002b94: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8002b98: 6053 str r3, [r2, #4]
USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
8002b9a: 78fb ldrb r3, [r7, #3]
8002b9c: 015a lsls r2, r3, #5
8002b9e: 693b ldr r3, [r7, #16]
8002ba0: 4413 add r3, r2
8002ba2: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002ba6: 68db ldr r3, [r3, #12]
8002ba8: 78fa ldrb r2, [r7, #3]
8002baa: 0151 lsls r1, r2, #5
8002bac: 693a ldr r2, [r7, #16]
8002bae: 440a add r2, r1
8002bb0: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002bb4: f043 0340 orr.w r3, r3, #64 @ 0x40
8002bb8: 60d3 str r3, [r2, #12]
USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
8002bba: 78fb ldrb r3, [r7, #3]
8002bbc: 015a lsls r2, r3, #5
8002bbe: 693b ldr r3, [r7, #16]
8002bc0: 4413 add r3, r2
8002bc2: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002bc6: 68db ldr r3, [r3, #12]
8002bc8: 78fa ldrb r2, [r7, #3]
8002bca: 0151 lsls r1, r2, #5
8002bcc: 693a ldr r2, [r7, #16]
8002bce: 440a add r2, r1
8002bd0: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002bd4: f023 0320 bic.w r3, r3, #32
8002bd8: 60d3 str r3, [r2, #12]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002bda: 78fa ldrb r2, [r7, #3]
8002bdc: 6879 ldr r1, [r7, #4]
8002bde: 4613 mov r3, r2
8002be0: 011b lsls r3, r3, #4
8002be2: 1a9b subs r3, r3, r2
8002be4: 009b lsls r3, r3, #2
8002be6: 440b add r3, r1
8002be8: 3326 adds r3, #38 @ 0x26
8002bea: 781b ldrb r3, [r3, #0]
8002bec: 2b00 cmp r3, #0
8002bee: d00b beq.n 8002c08 <HCD_HC_IN_IRQHandler+0x97c>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
8002bf0: 78fa ldrb r2, [r7, #3]
8002bf2: 6879 ldr r1, [r7, #4]
8002bf4: 4613 mov r3, r2
8002bf6: 011b lsls r3, r3, #4
8002bf8: 1a9b subs r3, r3, r2
8002bfa: 009b lsls r3, r3, #2
8002bfc: 440b add r3, r1
8002bfe: 3326 adds r3, #38 @ 0x26
8002c00: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002c02: 2b02 cmp r3, #2
8002c04: f040 80a9 bne.w 8002d5a <HCD_HC_IN_IRQHandler+0xace>
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
8002c08: 78fb ldrb r3, [r7, #3]
8002c0a: 015a lsls r2, r3, #5
8002c0c: 693b ldr r3, [r7, #16]
8002c0e: 4413 add r3, r2
8002c10: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002c14: 681b ldr r3, [r3, #0]
8002c16: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8002c18: 68fb ldr r3, [r7, #12]
8002c1a: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8002c1e: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8002c20: 68fb ldr r3, [r7, #12]
8002c22: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8002c26: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
8002c28: 78fb ldrb r3, [r7, #3]
8002c2a: 015a lsls r2, r3, #5
8002c2c: 693b ldr r3, [r7, #16]
8002c2e: 4413 add r3, r2
8002c30: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002c34: 461a mov r2, r3
8002c36: 68fb ldr r3, [r7, #12]
8002c38: 6013 str r3, [r2, #0]
8002c3a: e08e b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
8002c3c: 78fa ldrb r2, [r7, #3]
8002c3e: 6879 ldr r1, [r7, #4]
8002c40: 4613 mov r3, r2
8002c42: 011b lsls r3, r3, #4
8002c44: 1a9b subs r3, r3, r2
8002c46: 009b lsls r3, r3, #2
8002c48: 440b add r3, r1
8002c4a: 334d adds r3, #77 @ 0x4d
8002c4c: 781b ldrb r3, [r3, #0]
8002c4e: 2b04 cmp r3, #4
8002c50: d143 bne.n 8002cda <HCD_HC_IN_IRQHandler+0xa4e>
{
hhcd->hc[chnum].state = HC_HALTED;
8002c52: 78fa ldrb r2, [r7, #3]
8002c54: 6879 ldr r1, [r7, #4]
8002c56: 4613 mov r3, r2
8002c58: 011b lsls r3, r3, #4
8002c5a: 1a9b subs r3, r3, r2
8002c5c: 009b lsls r3, r3, #2
8002c5e: 440b add r3, r1
8002c60: 334d adds r3, #77 @ 0x4d
8002c62: 2202 movs r2, #2
8002c64: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8002c66: 78fa ldrb r2, [r7, #3]
8002c68: 6879 ldr r1, [r7, #4]
8002c6a: 4613 mov r3, r2
8002c6c: 011b lsls r3, r3, #4
8002c6e: 1a9b subs r3, r3, r2
8002c70: 009b lsls r3, r3, #2
8002c72: 440b add r3, r1
8002c74: 334c adds r3, #76 @ 0x4c
8002c76: 2202 movs r2, #2
8002c78: 701a strb r2, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002c7a: 78fa ldrb r2, [r7, #3]
8002c7c: 6879 ldr r1, [r7, #4]
8002c7e: 4613 mov r3, r2
8002c80: 011b lsls r3, r3, #4
8002c82: 1a9b subs r3, r3, r2
8002c84: 009b lsls r3, r3, #2
8002c86: 440b add r3, r1
8002c88: 3326 adds r3, #38 @ 0x26
8002c8a: 781b ldrb r3, [r3, #0]
8002c8c: 2b00 cmp r3, #0
8002c8e: d00a beq.n 8002ca6 <HCD_HC_IN_IRQHandler+0xa1a>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
8002c90: 78fa ldrb r2, [r7, #3]
8002c92: 6879 ldr r1, [r7, #4]
8002c94: 4613 mov r3, r2
8002c96: 011b lsls r3, r3, #4
8002c98: 1a9b subs r3, r3, r2
8002c9a: 009b lsls r3, r3, #2
8002c9c: 440b add r3, r1
8002c9e: 3326 adds r3, #38 @ 0x26
8002ca0: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002ca2: 2b02 cmp r3, #2
8002ca4: d159 bne.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
{
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
8002ca6: 78fb ldrb r3, [r7, #3]
8002ca8: 015a lsls r2, r3, #5
8002caa: 693b ldr r3, [r7, #16]
8002cac: 4413 add r3, r2
8002cae: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002cb2: 681b ldr r3, [r3, #0]
8002cb4: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8002cb6: 68fb ldr r3, [r7, #12]
8002cb8: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8002cbc: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8002cbe: 68fb ldr r3, [r7, #12]
8002cc0: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8002cc4: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
8002cc6: 78fb ldrb r3, [r7, #3]
8002cc8: 015a lsls r2, r3, #5
8002cca: 693b ldr r3, [r7, #16]
8002ccc: 4413 add r3, r2
8002cce: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002cd2: 461a mov r2, r3
8002cd4: 68fb ldr r3, [r7, #12]
8002cd6: 6013 str r3, [r2, #0]
8002cd8: e03f b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
}
else if (hhcd->hc[chnum].state == HC_BBLERR)
8002cda: 78fa ldrb r2, [r7, #3]
8002cdc: 6879 ldr r1, [r7, #4]
8002cde: 4613 mov r3, r2
8002ce0: 011b lsls r3, r3, #4
8002ce2: 1a9b subs r3, r3, r2
8002ce4: 009b lsls r3, r3, #2
8002ce6: 440b add r3, r1
8002ce8: 334d adds r3, #77 @ 0x4d
8002cea: 781b ldrb r3, [r3, #0]
8002cec: 2b08 cmp r3, #8
8002cee: d126 bne.n 8002d3e <HCD_HC_IN_IRQHandler+0xab2>
{
hhcd->hc[chnum].state = HC_HALTED;
8002cf0: 78fa ldrb r2, [r7, #3]
8002cf2: 6879 ldr r1, [r7, #4]
8002cf4: 4613 mov r3, r2
8002cf6: 011b lsls r3, r3, #4
8002cf8: 1a9b subs r3, r3, r2
8002cfa: 009b lsls r3, r3, #2
8002cfc: 440b add r3, r1
8002cfe: 334d adds r3, #77 @ 0x4d
8002d00: 2202 movs r2, #2
8002d02: 701a strb r2, [r3, #0]
hhcd->hc[chnum].ErrCnt++;
8002d04: 78fa ldrb r2, [r7, #3]
8002d06: 6879 ldr r1, [r7, #4]
8002d08: 4613 mov r3, r2
8002d0a: 011b lsls r3, r3, #4
8002d0c: 1a9b subs r3, r3, r2
8002d0e: 009b lsls r3, r3, #2
8002d10: 440b add r3, r1
8002d12: 3344 adds r3, #68 @ 0x44
8002d14: 681b ldr r3, [r3, #0]
8002d16: 1c59 adds r1, r3, #1
8002d18: 6878 ldr r0, [r7, #4]
8002d1a: 4613 mov r3, r2
8002d1c: 011b lsls r3, r3, #4
8002d1e: 1a9b subs r3, r3, r2
8002d20: 009b lsls r3, r3, #2
8002d22: 4403 add r3, r0
8002d24: 3344 adds r3, #68 @ 0x44
8002d26: 6019 str r1, [r3, #0]
hhcd->hc[chnum].urb_state = URB_ERROR;
8002d28: 78fa ldrb r2, [r7, #3]
8002d2a: 6879 ldr r1, [r7, #4]
8002d2c: 4613 mov r3, r2
8002d2e: 011b lsls r3, r3, #4
8002d30: 1a9b subs r3, r3, r2
8002d32: 009b lsls r3, r3, #2
8002d34: 440b add r3, r1
8002d36: 334c adds r3, #76 @ 0x4c
8002d38: 2204 movs r2, #4
8002d3a: 701a strb r2, [r3, #0]
8002d3c: e00d b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
}
else
{
if (hhcd->hc[chnum].state == HC_HALTED)
8002d3e: 78fa ldrb r2, [r7, #3]
8002d40: 6879 ldr r1, [r7, #4]
8002d42: 4613 mov r3, r2
8002d44: 011b lsls r3, r3, #4
8002d46: 1a9b subs r3, r3, r2
8002d48: 009b lsls r3, r3, #2
8002d4a: 440b add r3, r1
8002d4c: 334d adds r3, #77 @ 0x4d
8002d4e: 781b ldrb r3, [r3, #0]
8002d50: 2b02 cmp r3, #2
8002d52: f000 8100 beq.w 8002f56 <HCD_HC_IN_IRQHandler+0xcca>
8002d56: e000 b.n 8002d5a <HCD_HC_IN_IRQHandler+0xace>
if (hhcd->hc[chnum].ErrCnt > 2U)
8002d58: bf00 nop
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
8002d5a: 78fa ldrb r2, [r7, #3]
8002d5c: 6879 ldr r1, [r7, #4]
8002d5e: 4613 mov r3, r2
8002d60: 011b lsls r3, r3, #4
8002d62: 1a9b subs r3, r3, r2
8002d64: 009b lsls r3, r3, #2
8002d66: 440b add r3, r1
8002d68: 334c adds r3, #76 @ 0x4c
8002d6a: 781a ldrb r2, [r3, #0]
8002d6c: 78fb ldrb r3, [r7, #3]
8002d6e: 4619 mov r1, r3
8002d70: 6878 ldr r0, [r7, #4]
8002d72: f005 f817 bl 8007da4 <HAL_HCD_HC_NotifyURBChange_Callback>
8002d76: e0ef b.n 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
8002d78: 687b ldr r3, [r7, #4]
8002d7a: 681b ldr r3, [r3, #0]
8002d7c: 78fa ldrb r2, [r7, #3]
8002d7e: 4611 mov r1, r2
8002d80: 4618 mov r0, r3
8002d82: f003 fbfa bl 800657a <USB_ReadChInterrupts>
8002d86: 4603 mov r3, r0
8002d88: f003 0340 and.w r3, r3, #64 @ 0x40
8002d8c: 2b40 cmp r3, #64 @ 0x40
8002d8e: d12f bne.n 8002df0 <HCD_HC_IN_IRQHandler+0xb64>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
8002d90: 78fb ldrb r3, [r7, #3]
8002d92: 015a lsls r2, r3, #5
8002d94: 693b ldr r3, [r7, #16]
8002d96: 4413 add r3, r2
8002d98: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002d9c: 461a mov r2, r3
8002d9e: 2340 movs r3, #64 @ 0x40
8002da0: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_NYET;
8002da2: 78fa ldrb r2, [r7, #3]
8002da4: 6879 ldr r1, [r7, #4]
8002da6: 4613 mov r3, r2
8002da8: 011b lsls r3, r3, #4
8002daa: 1a9b subs r3, r3, r2
8002dac: 009b lsls r3, r3, #2
8002dae: 440b add r3, r1
8002db0: 334d adds r3, #77 @ 0x4d
8002db2: 2205 movs r2, #5
8002db4: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_ssplit == 0U)
8002db6: 78fa ldrb r2, [r7, #3]
8002db8: 6879 ldr r1, [r7, #4]
8002dba: 4613 mov r3, r2
8002dbc: 011b lsls r3, r3, #4
8002dbe: 1a9b subs r3, r3, r2
8002dc0: 009b lsls r3, r3, #2
8002dc2: 440b add r3, r1
8002dc4: 331a adds r3, #26
8002dc6: 781b ldrb r3, [r3, #0]
8002dc8: 2b00 cmp r3, #0
8002dca: d109 bne.n 8002de0 <HCD_HC_IN_IRQHandler+0xb54>
{
hhcd->hc[chnum].ErrCnt = 0U;
8002dcc: 78fa ldrb r2, [r7, #3]
8002dce: 6879 ldr r1, [r7, #4]
8002dd0: 4613 mov r3, r2
8002dd2: 011b lsls r3, r3, #4
8002dd4: 1a9b subs r3, r3, r2
8002dd6: 009b lsls r3, r3, #2
8002dd8: 440b add r3, r1
8002dda: 3344 adds r3, #68 @ 0x44
8002ddc: 2200 movs r2, #0
8002dde: 601a str r2, [r3, #0]
}
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002de0: 687b ldr r3, [r7, #4]
8002de2: 681b ldr r3, [r3, #0]
8002de4: 78fa ldrb r2, [r7, #3]
8002de6: 4611 mov r1, r2
8002de8: 4618 mov r0, r3
8002dea: f003 fc43 bl 8006674 <USB_HC_Halt>
8002dee: e0b3 b.n 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
8002df0: 687b ldr r3, [r7, #4]
8002df2: 681b ldr r3, [r3, #0]
8002df4: 78fa ldrb r2, [r7, #3]
8002df6: 4611 mov r1, r2
8002df8: 4618 mov r0, r3
8002dfa: f003 fbbe bl 800657a <USB_ReadChInterrupts>
8002dfe: 4603 mov r3, r0
8002e00: f003 0310 and.w r3, r3, #16
8002e04: 2b10 cmp r3, #16
8002e06: f040 80a7 bne.w 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
{
if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
8002e0a: 78fa ldrb r2, [r7, #3]
8002e0c: 6879 ldr r1, [r7, #4]
8002e0e: 4613 mov r3, r2
8002e10: 011b lsls r3, r3, #4
8002e12: 1a9b subs r3, r3, r2
8002e14: 009b lsls r3, r3, #2
8002e16: 440b add r3, r1
8002e18: 3326 adds r3, #38 @ 0x26
8002e1a: 781b ldrb r3, [r3, #0]
8002e1c: 2b03 cmp r3, #3
8002e1e: d11b bne.n 8002e58 <HCD_HC_IN_IRQHandler+0xbcc>
{
hhcd->hc[chnum].ErrCnt = 0U;
8002e20: 78fa ldrb r2, [r7, #3]
8002e22: 6879 ldr r1, [r7, #4]
8002e24: 4613 mov r3, r2
8002e26: 011b lsls r3, r3, #4
8002e28: 1a9b subs r3, r3, r2
8002e2a: 009b lsls r3, r3, #2
8002e2c: 440b add r3, r1
8002e2e: 3344 adds r3, #68 @ 0x44
8002e30: 2200 movs r2, #0
8002e32: 601a str r2, [r3, #0]
hhcd->hc[chnum].state = HC_NAK;
8002e34: 78fa ldrb r2, [r7, #3]
8002e36: 6879 ldr r1, [r7, #4]
8002e38: 4613 mov r3, r2
8002e3a: 011b lsls r3, r3, #4
8002e3c: 1a9b subs r3, r3, r2
8002e3e: 009b lsls r3, r3, #2
8002e40: 440b add r3, r1
8002e42: 334d adds r3, #77 @ 0x4d
8002e44: 2204 movs r2, #4
8002e46: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002e48: 687b ldr r3, [r7, #4]
8002e4a: 681b ldr r3, [r3, #0]
8002e4c: 78fa ldrb r2, [r7, #3]
8002e4e: 4611 mov r1, r2
8002e50: 4618 mov r0, r3
8002e52: f003 fc0f bl 8006674 <USB_HC_Halt>
8002e56: e03f b.n 8002ed8 <HCD_HC_IN_IRQHandler+0xc4c>
}
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002e58: 78fa ldrb r2, [r7, #3]
8002e5a: 6879 ldr r1, [r7, #4]
8002e5c: 4613 mov r3, r2
8002e5e: 011b lsls r3, r3, #4
8002e60: 1a9b subs r3, r3, r2
8002e62: 009b lsls r3, r3, #2
8002e64: 440b add r3, r1
8002e66: 3326 adds r3, #38 @ 0x26
8002e68: 781b ldrb r3, [r3, #0]
8002e6a: 2b00 cmp r3, #0
8002e6c: d00a beq.n 8002e84 <HCD_HC_IN_IRQHandler+0xbf8>
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
8002e6e: 78fa ldrb r2, [r7, #3]
8002e70: 6879 ldr r1, [r7, #4]
8002e72: 4613 mov r3, r2
8002e74: 011b lsls r3, r3, #4
8002e76: 1a9b subs r3, r3, r2
8002e78: 009b lsls r3, r3, #2
8002e7a: 440b add r3, r1
8002e7c: 3326 adds r3, #38 @ 0x26
8002e7e: 781b ldrb r3, [r3, #0]
else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
8002e80: 2b02 cmp r3, #2
8002e82: d129 bne.n 8002ed8 <HCD_HC_IN_IRQHandler+0xc4c>
{
hhcd->hc[chnum].ErrCnt = 0U;
8002e84: 78fa ldrb r2, [r7, #3]
8002e86: 6879 ldr r1, [r7, #4]
8002e88: 4613 mov r3, r2
8002e8a: 011b lsls r3, r3, #4
8002e8c: 1a9b subs r3, r3, r2
8002e8e: 009b lsls r3, r3, #2
8002e90: 440b add r3, r1
8002e92: 3344 adds r3, #68 @ 0x44
8002e94: 2200 movs r2, #0
8002e96: 601a str r2, [r3, #0]
if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
8002e98: 687b ldr r3, [r7, #4]
8002e9a: 799b ldrb r3, [r3, #6]
8002e9c: 2b00 cmp r3, #0
8002e9e: d00a beq.n 8002eb6 <HCD_HC_IN_IRQHandler+0xc2a>
8002ea0: 78fa ldrb r2, [r7, #3]
8002ea2: 6879 ldr r1, [r7, #4]
8002ea4: 4613 mov r3, r2
8002ea6: 011b lsls r3, r3, #4
8002ea8: 1a9b subs r3, r3, r2
8002eaa: 009b lsls r3, r3, #2
8002eac: 440b add r3, r1
8002eae: 331b adds r3, #27
8002eb0: 781b ldrb r3, [r3, #0]
8002eb2: 2b01 cmp r3, #1
8002eb4: d110 bne.n 8002ed8 <HCD_HC_IN_IRQHandler+0xc4c>
{
hhcd->hc[chnum].state = HC_NAK;
8002eb6: 78fa ldrb r2, [r7, #3]
8002eb8: 6879 ldr r1, [r7, #4]
8002eba: 4613 mov r3, r2
8002ebc: 011b lsls r3, r3, #4
8002ebe: 1a9b subs r3, r3, r2
8002ec0: 009b lsls r3, r3, #2
8002ec2: 440b add r3, r1
8002ec4: 334d adds r3, #77 @ 0x4d
8002ec6: 2204 movs r2, #4
8002ec8: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002eca: 687b ldr r3, [r7, #4]
8002ecc: 681b ldr r3, [r3, #0]
8002ece: 78fa ldrb r2, [r7, #3]
8002ed0: 4611 mov r1, r2
8002ed2: 4618 mov r0, r3
8002ed4: f003 fbce bl 8006674 <USB_HC_Halt>
else
{
/* ... */
}
if (hhcd->hc[chnum].do_csplit == 1U)
8002ed8: 78fa ldrb r2, [r7, #3]
8002eda: 6879 ldr r1, [r7, #4]
8002edc: 4613 mov r3, r2
8002ede: 011b lsls r3, r3, #4
8002ee0: 1a9b subs r3, r3, r2
8002ee2: 009b lsls r3, r3, #2
8002ee4: 440b add r3, r1
8002ee6: 331b adds r3, #27
8002ee8: 781b ldrb r3, [r3, #0]
8002eea: 2b01 cmp r3, #1
8002eec: d129 bne.n 8002f42 <HCD_HC_IN_IRQHandler+0xcb6>
{
hhcd->hc[chnum].do_csplit = 0U;
8002eee: 78fa ldrb r2, [r7, #3]
8002ef0: 6879 ldr r1, [r7, #4]
8002ef2: 4613 mov r3, r2
8002ef4: 011b lsls r3, r3, #4
8002ef6: 1a9b subs r3, r3, r2
8002ef8: 009b lsls r3, r3, #2
8002efa: 440b add r3, r1
8002efc: 331b adds r3, #27
8002efe: 2200 movs r2, #0
8002f00: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
8002f02: 78fb ldrb r3, [r7, #3]
8002f04: 015a lsls r2, r3, #5
8002f06: 693b ldr r3, [r7, #16]
8002f08: 4413 add r3, r2
8002f0a: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002f0e: 685b ldr r3, [r3, #4]
8002f10: 78fa ldrb r2, [r7, #3]
8002f12: 0151 lsls r1, r2, #5
8002f14: 693a ldr r2, [r7, #16]
8002f16: 440a add r2, r1
8002f18: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002f1c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8002f20: 6053 str r3, [r2, #4]
__HAL_HCD_UNMASK_ACK_HC_INT(chnum);
8002f22: 78fb ldrb r3, [r7, #3]
8002f24: 015a lsls r2, r3, #5
8002f26: 693b ldr r3, [r7, #16]
8002f28: 4413 add r3, r2
8002f2a: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002f2e: 68db ldr r3, [r3, #12]
8002f30: 78fa ldrb r2, [r7, #3]
8002f32: 0151 lsls r1, r2, #5
8002f34: 693a ldr r2, [r7, #16]
8002f36: 440a add r2, r1
8002f38: f502 62a0 add.w r2, r2, #1280 @ 0x500
8002f3c: f043 0320 orr.w r3, r3, #32
8002f40: 60d3 str r3, [r2, #12]
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
8002f42: 78fb ldrb r3, [r7, #3]
8002f44: 015a lsls r2, r3, #5
8002f46: 693b ldr r3, [r7, #16]
8002f48: 4413 add r3, r2
8002f4a: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002f4e: 461a mov r2, r3
8002f50: 2310 movs r3, #16
8002f52: 6093 str r3, [r2, #8]
8002f54: e000 b.n 8002f58 <HCD_HC_IN_IRQHandler+0xccc>
return;
8002f56: bf00 nop
}
else
{
/* ... */
}
}
8002f58: 3718 adds r7, #24
8002f5a: 46bd mov sp, r7
8002f5c: bd80 pop {r7, pc}
08002f5e <HCD_HC_OUT_IRQHandler>:
* @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
8002f5e: b580 push {r7, lr}
8002f60: b086 sub sp, #24
8002f62: af00 add r7, sp, #0
8002f64: 6078 str r0, [r7, #4]
8002f66: 460b mov r3, r1
8002f68: 70fb strb r3, [r7, #3]
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
8002f6a: 687b ldr r3, [r7, #4]
8002f6c: 681b ldr r3, [r3, #0]
8002f6e: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8002f70: 697b ldr r3, [r7, #20]
8002f72: 613b str r3, [r7, #16]
uint32_t tmpreg;
uint32_t num_packets;
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
8002f74: 687b ldr r3, [r7, #4]
8002f76: 681b ldr r3, [r3, #0]
8002f78: 78fa ldrb r2, [r7, #3]
8002f7a: 4611 mov r1, r2
8002f7c: 4618 mov r0, r3
8002f7e: f003 fafc bl 800657a <USB_ReadChInterrupts>
8002f82: 4603 mov r3, r0
8002f84: f003 0304 and.w r3, r3, #4
8002f88: 2b04 cmp r3, #4
8002f8a: d11b bne.n 8002fc4 <HCD_HC_OUT_IRQHandler+0x66>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
8002f8c: 78fb ldrb r3, [r7, #3]
8002f8e: 015a lsls r2, r3, #5
8002f90: 693b ldr r3, [r7, #16]
8002f92: 4413 add r3, r2
8002f94: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002f98: 461a mov r2, r3
8002f9a: 2304 movs r3, #4
8002f9c: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_XACTERR;
8002f9e: 78fa ldrb r2, [r7, #3]
8002fa0: 6879 ldr r1, [r7, #4]
8002fa2: 4613 mov r3, r2
8002fa4: 011b lsls r3, r3, #4
8002fa6: 1a9b subs r3, r3, r2
8002fa8: 009b lsls r3, r3, #2
8002faa: 440b add r3, r1
8002fac: 334d adds r3, #77 @ 0x4d
8002fae: 2207 movs r2, #7
8002fb0: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8002fb2: 687b ldr r3, [r7, #4]
8002fb4: 681b ldr r3, [r3, #0]
8002fb6: 78fa ldrb r2, [r7, #3]
8002fb8: 4611 mov r1, r2
8002fba: 4618 mov r0, r3
8002fbc: f003 fb5a bl 8006674 <USB_HC_Halt>
8002fc0: f000 bc89 b.w 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
8002fc4: 687b ldr r3, [r7, #4]
8002fc6: 681b ldr r3, [r3, #0]
8002fc8: 78fa ldrb r2, [r7, #3]
8002fca: 4611 mov r1, r2
8002fcc: 4618 mov r0, r3
8002fce: f003 fad4 bl 800657a <USB_ReadChInterrupts>
8002fd2: 4603 mov r3, r0
8002fd4: f003 0320 and.w r3, r3, #32
8002fd8: 2b20 cmp r3, #32
8002fda: f040 8082 bne.w 80030e2 <HCD_HC_OUT_IRQHandler+0x184>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
8002fde: 78fb ldrb r3, [r7, #3]
8002fe0: 015a lsls r2, r3, #5
8002fe2: 693b ldr r3, [r7, #16]
8002fe4: 4413 add r3, r2
8002fe6: f503 63a0 add.w r3, r3, #1280 @ 0x500
8002fea: 461a mov r2, r3
8002fec: 2320 movs r3, #32
8002fee: 6093 str r3, [r2, #8]
if (hhcd->hc[chnum].do_ping == 1U)
8002ff0: 78fa ldrb r2, [r7, #3]
8002ff2: 6879 ldr r1, [r7, #4]
8002ff4: 4613 mov r3, r2
8002ff6: 011b lsls r3, r3, #4
8002ff8: 1a9b subs r3, r3, r2
8002ffa: 009b lsls r3, r3, #2
8002ffc: 440b add r3, r1
8002ffe: 3319 adds r3, #25
8003000: 781b ldrb r3, [r3, #0]
8003002: 2b01 cmp r3, #1
8003004: d124 bne.n 8003050 <HCD_HC_OUT_IRQHandler+0xf2>
{
hhcd->hc[chnum].do_ping = 0U;
8003006: 78fa ldrb r2, [r7, #3]
8003008: 6879 ldr r1, [r7, #4]
800300a: 4613 mov r3, r2
800300c: 011b lsls r3, r3, #4
800300e: 1a9b subs r3, r3, r2
8003010: 009b lsls r3, r3, #2
8003012: 440b add r3, r1
8003014: 3319 adds r3, #25
8003016: 2200 movs r2, #0
8003018: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_NOTREADY;
800301a: 78fa ldrb r2, [r7, #3]
800301c: 6879 ldr r1, [r7, #4]
800301e: 4613 mov r3, r2
8003020: 011b lsls r3, r3, #4
8003022: 1a9b subs r3, r3, r2
8003024: 009b lsls r3, r3, #2
8003026: 440b add r3, r1
8003028: 334c adds r3, #76 @ 0x4c
800302a: 2202 movs r2, #2
800302c: 701a strb r2, [r3, #0]
hhcd->hc[chnum].state = HC_ACK;
800302e: 78fa ldrb r2, [r7, #3]
8003030: 6879 ldr r1, [r7, #4]
8003032: 4613 mov r3, r2
8003034: 011b lsls r3, r3, #4
8003036: 1a9b subs r3, r3, r2
8003038: 009b lsls r3, r3, #2
800303a: 440b add r3, r1
800303c: 334d adds r3, #77 @ 0x4d
800303e: 2203 movs r2, #3
8003040: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8003042: 687b ldr r3, [r7, #4]
8003044: 681b ldr r3, [r3, #0]
8003046: 78fa ldrb r2, [r7, #3]
8003048: 4611 mov r1, r2
800304a: 4618 mov r0, r3
800304c: f003 fb12 bl 8006674 <USB_HC_Halt>
}
if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
8003050: 78fa ldrb r2, [r7, #3]
8003052: 6879 ldr r1, [r7, #4]
8003054: 4613 mov r3, r2
8003056: 011b lsls r3, r3, #4
8003058: 1a9b subs r3, r3, r2
800305a: 009b lsls r3, r3, #2
800305c: 440b add r3, r1
800305e: 331a adds r3, #26
8003060: 781b ldrb r3, [r3, #0]
8003062: 2b01 cmp r3, #1
8003064: f040 8437 bne.w 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
8003068: 78fa ldrb r2, [r7, #3]
800306a: 6879 ldr r1, [r7, #4]
800306c: 4613 mov r3, r2
800306e: 011b lsls r3, r3, #4
8003070: 1a9b subs r3, r3, r2
8003072: 009b lsls r3, r3, #2
8003074: 440b add r3, r1
8003076: 331b adds r3, #27
8003078: 781b ldrb r3, [r3, #0]
800307a: 2b00 cmp r3, #0
800307c: f040 842b bne.w 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
{
if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
8003080: 78fa ldrb r2, [r7, #3]
8003082: 6879 ldr r1, [r7, #4]
8003084: 4613 mov r3, r2
8003086: 011b lsls r3, r3, #4
8003088: 1a9b subs r3, r3, r2
800308a: 009b lsls r3, r3, #2
800308c: 440b add r3, r1
800308e: 3326 adds r3, #38 @ 0x26
8003090: 781b ldrb r3, [r3, #0]
8003092: 2b01 cmp r3, #1
8003094: d009 beq.n 80030aa <HCD_HC_OUT_IRQHandler+0x14c>
{
hhcd->hc[chnum].do_csplit = 1U;
8003096: 78fa ldrb r2, [r7, #3]
8003098: 6879 ldr r1, [r7, #4]
800309a: 4613 mov r3, r2
800309c: 011b lsls r3, r3, #4
800309e: 1a9b subs r3, r3, r2
80030a0: 009b lsls r3, r3, #2
80030a2: 440b add r3, r1
80030a4: 331b adds r3, #27
80030a6: 2201 movs r2, #1
80030a8: 701a strb r2, [r3, #0]
}
hhcd->hc[chnum].state = HC_ACK;
80030aa: 78fa ldrb r2, [r7, #3]
80030ac: 6879 ldr r1, [r7, #4]
80030ae: 4613 mov r3, r2
80030b0: 011b lsls r3, r3, #4
80030b2: 1a9b subs r3, r3, r2
80030b4: 009b lsls r3, r3, #2
80030b6: 440b add r3, r1
80030b8: 334d adds r3, #77 @ 0x4d
80030ba: 2203 movs r2, #3
80030bc: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80030be: 687b ldr r3, [r7, #4]
80030c0: 681b ldr r3, [r3, #0]
80030c2: 78fa ldrb r2, [r7, #3]
80030c4: 4611 mov r1, r2
80030c6: 4618 mov r0, r3
80030c8: f003 fad4 bl 8006674 <USB_HC_Halt>
/* reset error_count */
hhcd->hc[chnum].ErrCnt = 0U;
80030cc: 78fa ldrb r2, [r7, #3]
80030ce: 6879 ldr r1, [r7, #4]
80030d0: 4613 mov r3, r2
80030d2: 011b lsls r3, r3, #4
80030d4: 1a9b subs r3, r3, r2
80030d6: 009b lsls r3, r3, #2
80030d8: 440b add r3, r1
80030da: 3344 adds r3, #68 @ 0x44
80030dc: 2200 movs r2, #0
80030de: 601a str r2, [r3, #0]
80030e0: e3f9 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
80030e2: 687b ldr r3, [r7, #4]
80030e4: 681b ldr r3, [r3, #0]
80030e6: 78fa ldrb r2, [r7, #3]
80030e8: 4611 mov r1, r2
80030ea: 4618 mov r0, r3
80030ec: f003 fa45 bl 800657a <USB_ReadChInterrupts>
80030f0: 4603 mov r3, r0
80030f2: f403 7300 and.w r3, r3, #512 @ 0x200
80030f6: f5b3 7f00 cmp.w r3, #512 @ 0x200
80030fa: d111 bne.n 8003120 <HCD_HC_OUT_IRQHandler+0x1c2>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
80030fc: 78fb ldrb r3, [r7, #3]
80030fe: 015a lsls r2, r3, #5
8003100: 693b ldr r3, [r7, #16]
8003102: 4413 add r3, r2
8003104: f503 63a0 add.w r3, r3, #1280 @ 0x500
8003108: 461a mov r2, r3
800310a: f44f 7300 mov.w r3, #512 @ 0x200
800310e: 6093 str r3, [r2, #8]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8003110: 687b ldr r3, [r7, #4]
8003112: 681b ldr r3, [r3, #0]
8003114: 78fa ldrb r2, [r7, #3]
8003116: 4611 mov r1, r2
8003118: 4618 mov r0, r3
800311a: f003 faab bl 8006674 <USB_HC_Halt>
800311e: e3da b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
8003120: 687b ldr r3, [r7, #4]
8003122: 681b ldr r3, [r3, #0]
8003124: 78fa ldrb r2, [r7, #3]
8003126: 4611 mov r1, r2
8003128: 4618 mov r0, r3
800312a: f003 fa26 bl 800657a <USB_ReadChInterrupts>
800312e: 4603 mov r3, r0
8003130: f003 0301 and.w r3, r3, #1
8003134: 2b01 cmp r3, #1
8003136: d168 bne.n 800320a <HCD_HC_OUT_IRQHandler+0x2ac>
{
hhcd->hc[chnum].ErrCnt = 0U;
8003138: 78fa ldrb r2, [r7, #3]
800313a: 6879 ldr r1, [r7, #4]
800313c: 4613 mov r3, r2
800313e: 011b lsls r3, r3, #4
8003140: 1a9b subs r3, r3, r2
8003142: 009b lsls r3, r3, #2
8003144: 440b add r3, r1
8003146: 3344 adds r3, #68 @ 0x44
8003148: 2200 movs r2, #0
800314a: 601a str r2, [r3, #0]
/* transaction completed with NYET state, update do ping state */
if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
800314c: 687b ldr r3, [r7, #4]
800314e: 681b ldr r3, [r3, #0]
8003150: 78fa ldrb r2, [r7, #3]
8003152: 4611 mov r1, r2
8003154: 4618 mov r0, r3
8003156: f003 fa10 bl 800657a <USB_ReadChInterrupts>
800315a: 4603 mov r3, r0
800315c: f003 0340 and.w r3, r3, #64 @ 0x40
8003160: 2b40 cmp r3, #64 @ 0x40
8003162: d112 bne.n 800318a <HCD_HC_OUT_IRQHandler+0x22c>
{
hhcd->hc[chnum].do_ping = 1U;
8003164: 78fa ldrb r2, [r7, #3]
8003166: 6879 ldr r1, [r7, #4]
8003168: 4613 mov r3, r2
800316a: 011b lsls r3, r3, #4
800316c: 1a9b subs r3, r3, r2
800316e: 009b lsls r3, r3, #2
8003170: 440b add r3, r1
8003172: 3319 adds r3, #25
8003174: 2201 movs r2, #1
8003176: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
8003178: 78fb ldrb r3, [r7, #3]
800317a: 015a lsls r2, r3, #5
800317c: 693b ldr r3, [r7, #16]
800317e: 4413 add r3, r2
8003180: f503 63a0 add.w r3, r3, #1280 @ 0x500
8003184: 461a mov r2, r3
8003186: 2340 movs r3, #64 @ 0x40
8003188: 6093 str r3, [r2, #8]
}
if (hhcd->hc[chnum].do_csplit != 0U)
800318a: 78fa ldrb r2, [r7, #3]
800318c: 6879 ldr r1, [r7, #4]
800318e: 4613 mov r3, r2
8003190: 011b lsls r3, r3, #4
8003192: 1a9b subs r3, r3, r2
8003194: 009b lsls r3, r3, #2
8003196: 440b add r3, r1
8003198: 331b adds r3, #27
800319a: 781b ldrb r3, [r3, #0]
800319c: 2b00 cmp r3, #0
800319e: d019 beq.n 80031d4 <HCD_HC_OUT_IRQHandler+0x276>
{
hhcd->hc[chnum].do_csplit = 0U;
80031a0: 78fa ldrb r2, [r7, #3]
80031a2: 6879 ldr r1, [r7, #4]
80031a4: 4613 mov r3, r2
80031a6: 011b lsls r3, r3, #4
80031a8: 1a9b subs r3, r3, r2
80031aa: 009b lsls r3, r3, #2
80031ac: 440b add r3, r1
80031ae: 331b adds r3, #27
80031b0: 2200 movs r2, #0
80031b2: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
80031b4: 78fb ldrb r3, [r7, #3]
80031b6: 015a lsls r2, r3, #5
80031b8: 693b ldr r3, [r7, #16]
80031ba: 4413 add r3, r2
80031bc: f503 63a0 add.w r3, r3, #1280 @ 0x500
80031c0: 685b ldr r3, [r3, #4]
80031c2: 78fa ldrb r2, [r7, #3]
80031c4: 0151 lsls r1, r2, #5
80031c6: 693a ldr r2, [r7, #16]
80031c8: 440a add r2, r1
80031ca: f502 62a0 add.w r2, r2, #1280 @ 0x500
80031ce: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80031d2: 6053 str r3, [r2, #4]
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
80031d4: 78fb ldrb r3, [r7, #3]
80031d6: 015a lsls r2, r3, #5
80031d8: 693b ldr r3, [r7, #16]
80031da: 4413 add r3, r2
80031dc: f503 63a0 add.w r3, r3, #1280 @ 0x500
80031e0: 461a mov r2, r3
80031e2: 2301 movs r3, #1
80031e4: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_XFRC;
80031e6: 78fa ldrb r2, [r7, #3]
80031e8: 6879 ldr r1, [r7, #4]
80031ea: 4613 mov r3, r2
80031ec: 011b lsls r3, r3, #4
80031ee: 1a9b subs r3, r3, r2
80031f0: 009b lsls r3, r3, #2
80031f2: 440b add r3, r1
80031f4: 334d adds r3, #77 @ 0x4d
80031f6: 2201 movs r2, #1
80031f8: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80031fa: 687b ldr r3, [r7, #4]
80031fc: 681b ldr r3, [r3, #0]
80031fe: 78fa ldrb r2, [r7, #3]
8003200: 4611 mov r1, r2
8003202: 4618 mov r0, r3
8003204: f003 fa36 bl 8006674 <USB_HC_Halt>
8003208: e365 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
800320a: 687b ldr r3, [r7, #4]
800320c: 681b ldr r3, [r3, #0]
800320e: 78fa ldrb r2, [r7, #3]
8003210: 4611 mov r1, r2
8003212: 4618 mov r0, r3
8003214: f003 f9b1 bl 800657a <USB_ReadChInterrupts>
8003218: 4603 mov r3, r0
800321a: f003 0340 and.w r3, r3, #64 @ 0x40
800321e: 2b40 cmp r3, #64 @ 0x40
8003220: d139 bne.n 8003296 <HCD_HC_OUT_IRQHandler+0x338>
{
hhcd->hc[chnum].state = HC_NYET;
8003222: 78fa ldrb r2, [r7, #3]
8003224: 6879 ldr r1, [r7, #4]
8003226: 4613 mov r3, r2
8003228: 011b lsls r3, r3, #4
800322a: 1a9b subs r3, r3, r2
800322c: 009b lsls r3, r3, #2
800322e: 440b add r3, r1
8003230: 334d adds r3, #77 @ 0x4d
8003232: 2205 movs r2, #5
8003234: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_ssplit == 0U)
8003236: 78fa ldrb r2, [r7, #3]
8003238: 6879 ldr r1, [r7, #4]
800323a: 4613 mov r3, r2
800323c: 011b lsls r3, r3, #4
800323e: 1a9b subs r3, r3, r2
8003240: 009b lsls r3, r3, #2
8003242: 440b add r3, r1
8003244: 331a adds r3, #26
8003246: 781b ldrb r3, [r3, #0]
8003248: 2b00 cmp r3, #0
800324a: d109 bne.n 8003260 <HCD_HC_OUT_IRQHandler+0x302>
{
hhcd->hc[chnum].do_ping = 1U;
800324c: 78fa ldrb r2, [r7, #3]
800324e: 6879 ldr r1, [r7, #4]
8003250: 4613 mov r3, r2
8003252: 011b lsls r3, r3, #4
8003254: 1a9b subs r3, r3, r2
8003256: 009b lsls r3, r3, #2
8003258: 440b add r3, r1
800325a: 3319 adds r3, #25
800325c: 2201 movs r2, #1
800325e: 701a strb r2, [r3, #0]
}
hhcd->hc[chnum].ErrCnt = 0U;
8003260: 78fa ldrb r2, [r7, #3]
8003262: 6879 ldr r1, [r7, #4]
8003264: 4613 mov r3, r2
8003266: 011b lsls r3, r3, #4
8003268: 1a9b subs r3, r3, r2
800326a: 009b lsls r3, r3, #2
800326c: 440b add r3, r1
800326e: 3344 adds r3, #68 @ 0x44
8003270: 2200 movs r2, #0
8003272: 601a str r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
8003274: 687b ldr r3, [r7, #4]
8003276: 681b ldr r3, [r3, #0]
8003278: 78fa ldrb r2, [r7, #3]
800327a: 4611 mov r1, r2
800327c: 4618 mov r0, r3
800327e: f003 f9f9 bl 8006674 <USB_HC_Halt>
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
8003282: 78fb ldrb r3, [r7, #3]
8003284: 015a lsls r2, r3, #5
8003286: 693b ldr r3, [r7, #16]
8003288: 4413 add r3, r2
800328a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800328e: 461a mov r2, r3
8003290: 2340 movs r3, #64 @ 0x40
8003292: 6093 str r3, [r2, #8]
8003294: e31f b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
8003296: 687b ldr r3, [r7, #4]
8003298: 681b ldr r3, [r3, #0]
800329a: 78fa ldrb r2, [r7, #3]
800329c: 4611 mov r1, r2
800329e: 4618 mov r0, r3
80032a0: f003 f96b bl 800657a <USB_ReadChInterrupts>
80032a4: 4603 mov r3, r0
80032a6: f003 0308 and.w r3, r3, #8
80032aa: 2b08 cmp r3, #8
80032ac: d11a bne.n 80032e4 <HCD_HC_OUT_IRQHandler+0x386>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
80032ae: 78fb ldrb r3, [r7, #3]
80032b0: 015a lsls r2, r3, #5
80032b2: 693b ldr r3, [r7, #16]
80032b4: 4413 add r3, r2
80032b6: f503 63a0 add.w r3, r3, #1280 @ 0x500
80032ba: 461a mov r2, r3
80032bc: 2308 movs r3, #8
80032be: 6093 str r3, [r2, #8]
hhcd->hc[chnum].state = HC_STALL;
80032c0: 78fa ldrb r2, [r7, #3]
80032c2: 6879 ldr r1, [r7, #4]
80032c4: 4613 mov r3, r2
80032c6: 011b lsls r3, r3, #4
80032c8: 1a9b subs r3, r3, r2
80032ca: 009b lsls r3, r3, #2
80032cc: 440b add r3, r1
80032ce: 334d adds r3, #77 @ 0x4d
80032d0: 2206 movs r2, #6
80032d2: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80032d4: 687b ldr r3, [r7, #4]
80032d6: 681b ldr r3, [r3, #0]
80032d8: 78fa ldrb r2, [r7, #3]
80032da: 4611 mov r1, r2
80032dc: 4618 mov r0, r3
80032de: f003 f9c9 bl 8006674 <USB_HC_Halt>
80032e2: e2f8 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
80032e4: 687b ldr r3, [r7, #4]
80032e6: 681b ldr r3, [r3, #0]
80032e8: 78fa ldrb r2, [r7, #3]
80032ea: 4611 mov r1, r2
80032ec: 4618 mov r0, r3
80032ee: f003 f944 bl 800657a <USB_ReadChInterrupts>
80032f2: 4603 mov r3, r0
80032f4: f003 0310 and.w r3, r3, #16
80032f8: 2b10 cmp r3, #16
80032fa: d144 bne.n 8003386 <HCD_HC_OUT_IRQHandler+0x428>
{
hhcd->hc[chnum].ErrCnt = 0U;
80032fc: 78fa ldrb r2, [r7, #3]
80032fe: 6879 ldr r1, [r7, #4]
8003300: 4613 mov r3, r2
8003302: 011b lsls r3, r3, #4
8003304: 1a9b subs r3, r3, r2
8003306: 009b lsls r3, r3, #2
8003308: 440b add r3, r1
800330a: 3344 adds r3, #68 @ 0x44
800330c: 2200 movs r2, #0
800330e: 601a str r2, [r3, #0]
hhcd->hc[chnum].state = HC_NAK;
8003310: 78fa ldrb r2, [r7, #3]
8003312: 6879 ldr r1, [r7, #4]
8003314: 4613 mov r3, r2
8003316: 011b lsls r3, r3, #4
8003318: 1a9b subs r3, r3, r2
800331a: 009b lsls r3, r3, #2
800331c: 440b add r3, r1
800331e: 334d adds r3, #77 @ 0x4d
8003320: 2204 movs r2, #4
8003322: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_ping == 0U)
8003324: 78fa ldrb r2, [r7, #3]
8003326: 6879 ldr r1, [r7, #4]
8003328: 4613 mov r3, r2
800332a: 011b lsls r3, r3, #4
800332c: 1a9b subs r3, r3, r2
800332e: 009b lsls r3, r3, #2
8003330: 440b add r3, r1
8003332: 3319 adds r3, #25
8003334: 781b ldrb r3, [r3, #0]
8003336: 2b00 cmp r3, #0
8003338: d114 bne.n 8003364 <HCD_HC_OUT_IRQHandler+0x406>
{
if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
800333a: 78fa ldrb r2, [r7, #3]
800333c: 6879 ldr r1, [r7, #4]
800333e: 4613 mov r3, r2
8003340: 011b lsls r3, r3, #4
8003342: 1a9b subs r3, r3, r2
8003344: 009b lsls r3, r3, #2
8003346: 440b add r3, r1
8003348: 3318 adds r3, #24
800334a: 781b ldrb r3, [r3, #0]
800334c: 2b00 cmp r3, #0
800334e: d109 bne.n 8003364 <HCD_HC_OUT_IRQHandler+0x406>
{
hhcd->hc[chnum].do_ping = 1U;
8003350: 78fa ldrb r2, [r7, #3]
8003352: 6879 ldr r1, [r7, #4]
8003354: 4613 mov r3, r2
8003356: 011b lsls r3, r3, #4
8003358: 1a9b subs r3, r3, r2
800335a: 009b lsls r3, r3, #2
800335c: 440b add r3, r1
800335e: 3319 adds r3, #25
8003360: 2201 movs r2, #1
8003362: 701a strb r2, [r3, #0]
}
}
(void)USB_HC_Halt(hhcd->Instance, chnum);
8003364: 687b ldr r3, [r7, #4]
8003366: 681b ldr r3, [r3, #0]
8003368: 78fa ldrb r2, [r7, #3]
800336a: 4611 mov r1, r2
800336c: 4618 mov r0, r3
800336e: f003 f981 bl 8006674 <USB_HC_Halt>
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
8003372: 78fb ldrb r3, [r7, #3]
8003374: 015a lsls r2, r3, #5
8003376: 693b ldr r3, [r7, #16]
8003378: 4413 add r3, r2
800337a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800337e: 461a mov r2, r3
8003380: 2310 movs r3, #16
8003382: 6093 str r3, [r2, #8]
8003384: e2a7 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
8003386: 687b ldr r3, [r7, #4]
8003388: 681b ldr r3, [r3, #0]
800338a: 78fa ldrb r2, [r7, #3]
800338c: 4611 mov r1, r2
800338e: 4618 mov r0, r3
8003390: f003 f8f3 bl 800657a <USB_ReadChInterrupts>
8003394: 4603 mov r3, r0
8003396: f003 0380 and.w r3, r3, #128 @ 0x80
800339a: 2b80 cmp r3, #128 @ 0x80
800339c: f040 8083 bne.w 80034a6 <HCD_HC_OUT_IRQHandler+0x548>
{
if (hhcd->Init.dma_enable == 0U)
80033a0: 687b ldr r3, [r7, #4]
80033a2: 799b ldrb r3, [r3, #6]
80033a4: 2b00 cmp r3, #0
80033a6: d111 bne.n 80033cc <HCD_HC_OUT_IRQHandler+0x46e>
{
hhcd->hc[chnum].state = HC_XACTERR;
80033a8: 78fa ldrb r2, [r7, #3]
80033aa: 6879 ldr r1, [r7, #4]
80033ac: 4613 mov r3, r2
80033ae: 011b lsls r3, r3, #4
80033b0: 1a9b subs r3, r3, r2
80033b2: 009b lsls r3, r3, #2
80033b4: 440b add r3, r1
80033b6: 334d adds r3, #77 @ 0x4d
80033b8: 2207 movs r2, #7
80033ba: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80033bc: 687b ldr r3, [r7, #4]
80033be: 681b ldr r3, [r3, #0]
80033c0: 78fa ldrb r2, [r7, #3]
80033c2: 4611 mov r1, r2
80033c4: 4618 mov r0, r3
80033c6: f003 f955 bl 8006674 <USB_HC_Halt>
80033ca: e062 b.n 8003492 <HCD_HC_OUT_IRQHandler+0x534>
}
else
{
hhcd->hc[chnum].ErrCnt++;
80033cc: 78fa ldrb r2, [r7, #3]
80033ce: 6879 ldr r1, [r7, #4]
80033d0: 4613 mov r3, r2
80033d2: 011b lsls r3, r3, #4
80033d4: 1a9b subs r3, r3, r2
80033d6: 009b lsls r3, r3, #2
80033d8: 440b add r3, r1
80033da: 3344 adds r3, #68 @ 0x44
80033dc: 681b ldr r3, [r3, #0]
80033de: 1c59 adds r1, r3, #1
80033e0: 6878 ldr r0, [r7, #4]
80033e2: 4613 mov r3, r2
80033e4: 011b lsls r3, r3, #4
80033e6: 1a9b subs r3, r3, r2
80033e8: 009b lsls r3, r3, #2
80033ea: 4403 add r3, r0
80033ec: 3344 adds r3, #68 @ 0x44
80033ee: 6019 str r1, [r3, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
80033f0: 78fa ldrb r2, [r7, #3]
80033f2: 6879 ldr r1, [r7, #4]
80033f4: 4613 mov r3, r2
80033f6: 011b lsls r3, r3, #4
80033f8: 1a9b subs r3, r3, r2
80033fa: 009b lsls r3, r3, #2
80033fc: 440b add r3, r1
80033fe: 3344 adds r3, #68 @ 0x44
8003400: 681b ldr r3, [r3, #0]
8003402: 2b02 cmp r3, #2
8003404: d922 bls.n 800344c <HCD_HC_OUT_IRQHandler+0x4ee>
{
hhcd->hc[chnum].ErrCnt = 0U;
8003406: 78fa ldrb r2, [r7, #3]
8003408: 6879 ldr r1, [r7, #4]
800340a: 4613 mov r3, r2
800340c: 011b lsls r3, r3, #4
800340e: 1a9b subs r3, r3, r2
8003410: 009b lsls r3, r3, #2
8003412: 440b add r3, r1
8003414: 3344 adds r3, #68 @ 0x44
8003416: 2200 movs r2, #0
8003418: 601a str r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_ERROR;
800341a: 78fa ldrb r2, [r7, #3]
800341c: 6879 ldr r1, [r7, #4]
800341e: 4613 mov r3, r2
8003420: 011b lsls r3, r3, #4
8003422: 1a9b subs r3, r3, r2
8003424: 009b lsls r3, r3, #2
8003426: 440b add r3, r1
8003428: 334c adds r3, #76 @ 0x4c
800342a: 2204 movs r2, #4
800342c: 701a strb r2, [r3, #0]
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
800342e: 78fa ldrb r2, [r7, #3]
8003430: 6879 ldr r1, [r7, #4]
8003432: 4613 mov r3, r2
8003434: 011b lsls r3, r3, #4
8003436: 1a9b subs r3, r3, r2
8003438: 009b lsls r3, r3, #2
800343a: 440b add r3, r1
800343c: 334c adds r3, #76 @ 0x4c
800343e: 781a ldrb r2, [r3, #0]
8003440: 78fb ldrb r3, [r7, #3]
8003442: 4619 mov r1, r3
8003444: 6878 ldr r0, [r7, #4]
8003446: f004 fcad bl 8007da4 <HAL_HCD_HC_NotifyURBChange_Callback>
800344a: e022 b.n 8003492 <HCD_HC_OUT_IRQHandler+0x534>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
800344c: 78fa ldrb r2, [r7, #3]
800344e: 6879 ldr r1, [r7, #4]
8003450: 4613 mov r3, r2
8003452: 011b lsls r3, r3, #4
8003454: 1a9b subs r3, r3, r2
8003456: 009b lsls r3, r3, #2
8003458: 440b add r3, r1
800345a: 334c adds r3, #76 @ 0x4c
800345c: 2202 movs r2, #2
800345e: 701a strb r2, [r3, #0]
/* Re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
8003460: 78fb ldrb r3, [r7, #3]
8003462: 015a lsls r2, r3, #5
8003464: 693b ldr r3, [r7, #16]
8003466: 4413 add r3, r2
8003468: f503 63a0 add.w r3, r3, #1280 @ 0x500
800346c: 681b ldr r3, [r3, #0]
800346e: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8003470: 68fb ldr r3, [r7, #12]
8003472: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8003476: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8003478: 68fb ldr r3, [r7, #12]
800347a: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800347e: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
8003480: 78fb ldrb r3, [r7, #3]
8003482: 015a lsls r2, r3, #5
8003484: 693b ldr r3, [r7, #16]
8003486: 4413 add r3, r2
8003488: f503 63a0 add.w r3, r3, #1280 @ 0x500
800348c: 461a mov r2, r3
800348e: 68fb ldr r3, [r7, #12]
8003490: 6013 str r3, [r2, #0]
}
}
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
8003492: 78fb ldrb r3, [r7, #3]
8003494: 015a lsls r2, r3, #5
8003496: 693b ldr r3, [r7, #16]
8003498: 4413 add r3, r2
800349a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800349e: 461a mov r2, r3
80034a0: 2380 movs r3, #128 @ 0x80
80034a2: 6093 str r3, [r2, #8]
80034a4: e217 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
80034a6: 687b ldr r3, [r7, #4]
80034a8: 681b ldr r3, [r3, #0]
80034aa: 78fa ldrb r2, [r7, #3]
80034ac: 4611 mov r1, r2
80034ae: 4618 mov r0, r3
80034b0: f003 f863 bl 800657a <USB_ReadChInterrupts>
80034b4: 4603 mov r3, r0
80034b6: f403 6380 and.w r3, r3, #1024 @ 0x400
80034ba: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80034be: d11b bne.n 80034f8 <HCD_HC_OUT_IRQHandler+0x59a>
{
hhcd->hc[chnum].state = HC_DATATGLERR;
80034c0: 78fa ldrb r2, [r7, #3]
80034c2: 6879 ldr r1, [r7, #4]
80034c4: 4613 mov r3, r2
80034c6: 011b lsls r3, r3, #4
80034c8: 1a9b subs r3, r3, r2
80034ca: 009b lsls r3, r3, #2
80034cc: 440b add r3, r1
80034ce: 334d adds r3, #77 @ 0x4d
80034d0: 2209 movs r2, #9
80034d2: 701a strb r2, [r3, #0]
(void)USB_HC_Halt(hhcd->Instance, chnum);
80034d4: 687b ldr r3, [r7, #4]
80034d6: 681b ldr r3, [r3, #0]
80034d8: 78fa ldrb r2, [r7, #3]
80034da: 4611 mov r1, r2
80034dc: 4618 mov r0, r3
80034de: f003 f8c9 bl 8006674 <USB_HC_Halt>
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
80034e2: 78fb ldrb r3, [r7, #3]
80034e4: 015a lsls r2, r3, #5
80034e6: 693b ldr r3, [r7, #16]
80034e8: 4413 add r3, r2
80034ea: f503 63a0 add.w r3, r3, #1280 @ 0x500
80034ee: 461a mov r2, r3
80034f0: f44f 6380 mov.w r3, #1024 @ 0x400
80034f4: 6093 str r3, [r2, #8]
80034f6: e1ee b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
}
else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
80034f8: 687b ldr r3, [r7, #4]
80034fa: 681b ldr r3, [r3, #0]
80034fc: 78fa ldrb r2, [r7, #3]
80034fe: 4611 mov r1, r2
8003500: 4618 mov r0, r3
8003502: f003 f83a bl 800657a <USB_ReadChInterrupts>
8003506: 4603 mov r3, r0
8003508: f003 0302 and.w r3, r3, #2
800350c: 2b02 cmp r3, #2
800350e: f040 81df bne.w 80038d0 <HCD_HC_OUT_IRQHandler+0x972>
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
8003512: 78fb ldrb r3, [r7, #3]
8003514: 015a lsls r2, r3, #5
8003516: 693b ldr r3, [r7, #16]
8003518: 4413 add r3, r2
800351a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800351e: 461a mov r2, r3
8003520: 2302 movs r3, #2
8003522: 6093 str r3, [r2, #8]
if (hhcd->hc[chnum].state == HC_XFRC)
8003524: 78fa ldrb r2, [r7, #3]
8003526: 6879 ldr r1, [r7, #4]
8003528: 4613 mov r3, r2
800352a: 011b lsls r3, r3, #4
800352c: 1a9b subs r3, r3, r2
800352e: 009b lsls r3, r3, #2
8003530: 440b add r3, r1
8003532: 334d adds r3, #77 @ 0x4d
8003534: 781b ldrb r3, [r3, #0]
8003536: 2b01 cmp r3, #1
8003538: f040 8093 bne.w 8003662 <HCD_HC_OUT_IRQHandler+0x704>
{
hhcd->hc[chnum].state = HC_HALTED;
800353c: 78fa ldrb r2, [r7, #3]
800353e: 6879 ldr r1, [r7, #4]
8003540: 4613 mov r3, r2
8003542: 011b lsls r3, r3, #4
8003544: 1a9b subs r3, r3, r2
8003546: 009b lsls r3, r3, #2
8003548: 440b add r3, r1
800354a: 334d adds r3, #77 @ 0x4d
800354c: 2202 movs r2, #2
800354e: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_DONE;
8003550: 78fa ldrb r2, [r7, #3]
8003552: 6879 ldr r1, [r7, #4]
8003554: 4613 mov r3, r2
8003556: 011b lsls r3, r3, #4
8003558: 1a9b subs r3, r3, r2
800355a: 009b lsls r3, r3, #2
800355c: 440b add r3, r1
800355e: 334c adds r3, #76 @ 0x4c
8003560: 2201 movs r2, #1
8003562: 701a strb r2, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
8003564: 78fa ldrb r2, [r7, #3]
8003566: 6879 ldr r1, [r7, #4]
8003568: 4613 mov r3, r2
800356a: 011b lsls r3, r3, #4
800356c: 1a9b subs r3, r3, r2
800356e: 009b lsls r3, r3, #2
8003570: 440b add r3, r1
8003572: 3326 adds r3, #38 @ 0x26
8003574: 781b ldrb r3, [r3, #0]
8003576: 2b02 cmp r3, #2
8003578: d00b beq.n 8003592 <HCD_HC_OUT_IRQHandler+0x634>
(hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
800357a: 78fa ldrb r2, [r7, #3]
800357c: 6879 ldr r1, [r7, #4]
800357e: 4613 mov r3, r2
8003580: 011b lsls r3, r3, #4
8003582: 1a9b subs r3, r3, r2
8003584: 009b lsls r3, r3, #2
8003586: 440b add r3, r1
8003588: 3326 adds r3, #38 @ 0x26
800358a: 781b ldrb r3, [r3, #0]
if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
800358c: 2b03 cmp r3, #3
800358e: f040 8190 bne.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
{
if (hhcd->Init.dma_enable == 0U)
8003592: 687b ldr r3, [r7, #4]
8003594: 799b ldrb r3, [r3, #6]
8003596: 2b00 cmp r3, #0
8003598: d115 bne.n 80035c6 <HCD_HC_OUT_IRQHandler+0x668>
{
hhcd->hc[chnum].toggle_out ^= 1U;
800359a: 78fa ldrb r2, [r7, #3]
800359c: 6879 ldr r1, [r7, #4]
800359e: 4613 mov r3, r2
80035a0: 011b lsls r3, r3, #4
80035a2: 1a9b subs r3, r3, r2
80035a4: 009b lsls r3, r3, #2
80035a6: 440b add r3, r1
80035a8: 333d adds r3, #61 @ 0x3d
80035aa: 781b ldrb r3, [r3, #0]
80035ac: 78fa ldrb r2, [r7, #3]
80035ae: f083 0301 eor.w r3, r3, #1
80035b2: b2d8 uxtb r0, r3
80035b4: 6879 ldr r1, [r7, #4]
80035b6: 4613 mov r3, r2
80035b8: 011b lsls r3, r3, #4
80035ba: 1a9b subs r3, r3, r2
80035bc: 009b lsls r3, r3, #2
80035be: 440b add r3, r1
80035c0: 333d adds r3, #61 @ 0x3d
80035c2: 4602 mov r2, r0
80035c4: 701a strb r2, [r3, #0]
}
if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
80035c6: 687b ldr r3, [r7, #4]
80035c8: 799b ldrb r3, [r3, #6]
80035ca: 2b01 cmp r3, #1
80035cc: f040 8171 bne.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
80035d0: 78fa ldrb r2, [r7, #3]
80035d2: 6879 ldr r1, [r7, #4]
80035d4: 4613 mov r3, r2
80035d6: 011b lsls r3, r3, #4
80035d8: 1a9b subs r3, r3, r2
80035da: 009b lsls r3, r3, #2
80035dc: 440b add r3, r1
80035de: 3334 adds r3, #52 @ 0x34
80035e0: 681b ldr r3, [r3, #0]
80035e2: 2b00 cmp r3, #0
80035e4: f000 8165 beq.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
{
num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
80035e8: 78fa ldrb r2, [r7, #3]
80035ea: 6879 ldr r1, [r7, #4]
80035ec: 4613 mov r3, r2
80035ee: 011b lsls r3, r3, #4
80035f0: 1a9b subs r3, r3, r2
80035f2: 009b lsls r3, r3, #2
80035f4: 440b add r3, r1
80035f6: 3334 adds r3, #52 @ 0x34
80035f8: 6819 ldr r1, [r3, #0]
80035fa: 78fa ldrb r2, [r7, #3]
80035fc: 6878 ldr r0, [r7, #4]
80035fe: 4613 mov r3, r2
8003600: 011b lsls r3, r3, #4
8003602: 1a9b subs r3, r3, r2
8003604: 009b lsls r3, r3, #2
8003606: 4403 add r3, r0
8003608: 3328 adds r3, #40 @ 0x28
800360a: 881b ldrh r3, [r3, #0]
800360c: 440b add r3, r1
800360e: 1e59 subs r1, r3, #1
8003610: 78fa ldrb r2, [r7, #3]
8003612: 6878 ldr r0, [r7, #4]
8003614: 4613 mov r3, r2
8003616: 011b lsls r3, r3, #4
8003618: 1a9b subs r3, r3, r2
800361a: 009b lsls r3, r3, #2
800361c: 4403 add r3, r0
800361e: 3328 adds r3, #40 @ 0x28
8003620: 881b ldrh r3, [r3, #0]
8003622: fbb1 f3f3 udiv r3, r1, r3
8003626: 60bb str r3, [r7, #8]
if ((num_packets & 1U) != 0U)
8003628: 68bb ldr r3, [r7, #8]
800362a: f003 0301 and.w r3, r3, #1
800362e: 2b00 cmp r3, #0
8003630: f000 813f beq.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
{
hhcd->hc[chnum].toggle_out ^= 1U;
8003634: 78fa ldrb r2, [r7, #3]
8003636: 6879 ldr r1, [r7, #4]
8003638: 4613 mov r3, r2
800363a: 011b lsls r3, r3, #4
800363c: 1a9b subs r3, r3, r2
800363e: 009b lsls r3, r3, #2
8003640: 440b add r3, r1
8003642: 333d adds r3, #61 @ 0x3d
8003644: 781b ldrb r3, [r3, #0]
8003646: 78fa ldrb r2, [r7, #3]
8003648: f083 0301 eor.w r3, r3, #1
800364c: b2d8 uxtb r0, r3
800364e: 6879 ldr r1, [r7, #4]
8003650: 4613 mov r3, r2
8003652: 011b lsls r3, r3, #4
8003654: 1a9b subs r3, r3, r2
8003656: 009b lsls r3, r3, #2
8003658: 440b add r3, r1
800365a: 333d adds r3, #61 @ 0x3d
800365c: 4602 mov r2, r0
800365e: 701a strb r2, [r3, #0]
8003660: e127 b.n 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
}
}
}
}
else if (hhcd->hc[chnum].state == HC_ACK)
8003662: 78fa ldrb r2, [r7, #3]
8003664: 6879 ldr r1, [r7, #4]
8003666: 4613 mov r3, r2
8003668: 011b lsls r3, r3, #4
800366a: 1a9b subs r3, r3, r2
800366c: 009b lsls r3, r3, #2
800366e: 440b add r3, r1
8003670: 334d adds r3, #77 @ 0x4d
8003672: 781b ldrb r3, [r3, #0]
8003674: 2b03 cmp r3, #3
8003676: d120 bne.n 80036ba <HCD_HC_OUT_IRQHandler+0x75c>
{
hhcd->hc[chnum].state = HC_HALTED;
8003678: 78fa ldrb r2, [r7, #3]
800367a: 6879 ldr r1, [r7, #4]
800367c: 4613 mov r3, r2
800367e: 011b lsls r3, r3, #4
8003680: 1a9b subs r3, r3, r2
8003682: 009b lsls r3, r3, #2
8003684: 440b add r3, r1
8003686: 334d adds r3, #77 @ 0x4d
8003688: 2202 movs r2, #2
800368a: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_csplit == 1U)
800368c: 78fa ldrb r2, [r7, #3]
800368e: 6879 ldr r1, [r7, #4]
8003690: 4613 mov r3, r2
8003692: 011b lsls r3, r3, #4
8003694: 1a9b subs r3, r3, r2
8003696: 009b lsls r3, r3, #2
8003698: 440b add r3, r1
800369a: 331b adds r3, #27
800369c: 781b ldrb r3, [r3, #0]
800369e: 2b01 cmp r3, #1
80036a0: f040 8107 bne.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
80036a4: 78fa ldrb r2, [r7, #3]
80036a6: 6879 ldr r1, [r7, #4]
80036a8: 4613 mov r3, r2
80036aa: 011b lsls r3, r3, #4
80036ac: 1a9b subs r3, r3, r2
80036ae: 009b lsls r3, r3, #2
80036b0: 440b add r3, r1
80036b2: 334c adds r3, #76 @ 0x4c
80036b4: 2202 movs r2, #2
80036b6: 701a strb r2, [r3, #0]
80036b8: e0fb b.n 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
}
}
else if (hhcd->hc[chnum].state == HC_NAK)
80036ba: 78fa ldrb r2, [r7, #3]
80036bc: 6879 ldr r1, [r7, #4]
80036be: 4613 mov r3, r2
80036c0: 011b lsls r3, r3, #4
80036c2: 1a9b subs r3, r3, r2
80036c4: 009b lsls r3, r3, #2
80036c6: 440b add r3, r1
80036c8: 334d adds r3, #77 @ 0x4d
80036ca: 781b ldrb r3, [r3, #0]
80036cc: 2b04 cmp r3, #4
80036ce: d13a bne.n 8003746 <HCD_HC_OUT_IRQHandler+0x7e8>
{
hhcd->hc[chnum].state = HC_HALTED;
80036d0: 78fa ldrb r2, [r7, #3]
80036d2: 6879 ldr r1, [r7, #4]
80036d4: 4613 mov r3, r2
80036d6: 011b lsls r3, r3, #4
80036d8: 1a9b subs r3, r3, r2
80036da: 009b lsls r3, r3, #2
80036dc: 440b add r3, r1
80036de: 334d adds r3, #77 @ 0x4d
80036e0: 2202 movs r2, #2
80036e2: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_NOTREADY;
80036e4: 78fa ldrb r2, [r7, #3]
80036e6: 6879 ldr r1, [r7, #4]
80036e8: 4613 mov r3, r2
80036ea: 011b lsls r3, r3, #4
80036ec: 1a9b subs r3, r3, r2
80036ee: 009b lsls r3, r3, #2
80036f0: 440b add r3, r1
80036f2: 334c adds r3, #76 @ 0x4c
80036f4: 2202 movs r2, #2
80036f6: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].do_csplit == 1U)
80036f8: 78fa ldrb r2, [r7, #3]
80036fa: 6879 ldr r1, [r7, #4]
80036fc: 4613 mov r3, r2
80036fe: 011b lsls r3, r3, #4
8003700: 1a9b subs r3, r3, r2
8003702: 009b lsls r3, r3, #2
8003704: 440b add r3, r1
8003706: 331b adds r3, #27
8003708: 781b ldrb r3, [r3, #0]
800370a: 2b01 cmp r3, #1
800370c: f040 80d1 bne.w 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
{
hhcd->hc[chnum].do_csplit = 0U;
8003710: 78fa ldrb r2, [r7, #3]
8003712: 6879 ldr r1, [r7, #4]
8003714: 4613 mov r3, r2
8003716: 011b lsls r3, r3, #4
8003718: 1a9b subs r3, r3, r2
800371a: 009b lsls r3, r3, #2
800371c: 440b add r3, r1
800371e: 331b adds r3, #27
8003720: 2200 movs r2, #0
8003722: 701a strb r2, [r3, #0]
__HAL_HCD_CLEAR_HC_CSPLT(chnum);
8003724: 78fb ldrb r3, [r7, #3]
8003726: 015a lsls r2, r3, #5
8003728: 693b ldr r3, [r7, #16]
800372a: 4413 add r3, r2
800372c: f503 63a0 add.w r3, r3, #1280 @ 0x500
8003730: 685b ldr r3, [r3, #4]
8003732: 78fa ldrb r2, [r7, #3]
8003734: 0151 lsls r1, r2, #5
8003736: 693a ldr r2, [r7, #16]
8003738: 440a add r2, r1
800373a: f502 62a0 add.w r2, r2, #1280 @ 0x500
800373e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003742: 6053 str r3, [r2, #4]
8003744: e0b5 b.n 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
}
}
else if (hhcd->hc[chnum].state == HC_NYET)
8003746: 78fa ldrb r2, [r7, #3]
8003748: 6879 ldr r1, [r7, #4]
800374a: 4613 mov r3, r2
800374c: 011b lsls r3, r3, #4
800374e: 1a9b subs r3, r3, r2
8003750: 009b lsls r3, r3, #2
8003752: 440b add r3, r1
8003754: 334d adds r3, #77 @ 0x4d
8003756: 781b ldrb r3, [r3, #0]
8003758: 2b05 cmp r3, #5
800375a: d114 bne.n 8003786 <HCD_HC_OUT_IRQHandler+0x828>
{
hhcd->hc[chnum].state = HC_HALTED;
800375c: 78fa ldrb r2, [r7, #3]
800375e: 6879 ldr r1, [r7, #4]
8003760: 4613 mov r3, r2
8003762: 011b lsls r3, r3, #4
8003764: 1a9b subs r3, r3, r2
8003766: 009b lsls r3, r3, #2
8003768: 440b add r3, r1
800376a: 334d adds r3, #77 @ 0x4d
800376c: 2202 movs r2, #2
800376e: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_NOTREADY;
8003770: 78fa ldrb r2, [r7, #3]
8003772: 6879 ldr r1, [r7, #4]
8003774: 4613 mov r3, r2
8003776: 011b lsls r3, r3, #4
8003778: 1a9b subs r3, r3, r2
800377a: 009b lsls r3, r3, #2
800377c: 440b add r3, r1
800377e: 334c adds r3, #76 @ 0x4c
8003780: 2202 movs r2, #2
8003782: 701a strb r2, [r3, #0]
8003784: e095 b.n 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
}
else if (hhcd->hc[chnum].state == HC_STALL)
8003786: 78fa ldrb r2, [r7, #3]
8003788: 6879 ldr r1, [r7, #4]
800378a: 4613 mov r3, r2
800378c: 011b lsls r3, r3, #4
800378e: 1a9b subs r3, r3, r2
8003790: 009b lsls r3, r3, #2
8003792: 440b add r3, r1
8003794: 334d adds r3, #77 @ 0x4d
8003796: 781b ldrb r3, [r3, #0]
8003798: 2b06 cmp r3, #6
800379a: d114 bne.n 80037c6 <HCD_HC_OUT_IRQHandler+0x868>
{
hhcd->hc[chnum].state = HC_HALTED;
800379c: 78fa ldrb r2, [r7, #3]
800379e: 6879 ldr r1, [r7, #4]
80037a0: 4613 mov r3, r2
80037a2: 011b lsls r3, r3, #4
80037a4: 1a9b subs r3, r3, r2
80037a6: 009b lsls r3, r3, #2
80037a8: 440b add r3, r1
80037aa: 334d adds r3, #77 @ 0x4d
80037ac: 2202 movs r2, #2
80037ae: 701a strb r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_STALL;
80037b0: 78fa ldrb r2, [r7, #3]
80037b2: 6879 ldr r1, [r7, #4]
80037b4: 4613 mov r3, r2
80037b6: 011b lsls r3, r3, #4
80037b8: 1a9b subs r3, r3, r2
80037ba: 009b lsls r3, r3, #2
80037bc: 440b add r3, r1
80037be: 334c adds r3, #76 @ 0x4c
80037c0: 2205 movs r2, #5
80037c2: 701a strb r2, [r3, #0]
80037c4: e075 b.n 80038b2 <HCD_HC_OUT_IRQHandler+0x954>
}
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
80037c6: 78fa ldrb r2, [r7, #3]
80037c8: 6879 ldr r1, [r7, #4]
80037ca: 4613 mov r3, r2
80037cc: 011b lsls r3, r3, #4
80037ce: 1a9b subs r3, r3, r2
80037d0: 009b lsls r3, r3, #2
80037d2: 440b add r3, r1
80037d4: 334d adds r3, #77 @ 0x4d
80037d6: 781b ldrb r3, [r3, #0]
80037d8: 2b07 cmp r3, #7
80037da: d00a beq.n 80037f2 <HCD_HC_OUT_IRQHandler+0x894>
(hhcd->hc[chnum].state == HC_DATATGLERR))
80037dc: 78fa ldrb r2, [r7, #3]
80037de: 6879 ldr r1, [r7, #4]
80037e0: 4613 mov r3, r2
80037e2: 011b lsls r3, r3, #4
80037e4: 1a9b subs r3, r3, r2
80037e6: 009b lsls r3, r3, #2
80037e8: 440b add r3, r1
80037ea: 334d adds r3, #77 @ 0x4d
80037ec: 781b ldrb r3, [r3, #0]
else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
80037ee: 2b09 cmp r3, #9
80037f0: d170 bne.n 80038d4 <HCD_HC_OUT_IRQHandler+0x976>
{
hhcd->hc[chnum].state = HC_HALTED;
80037f2: 78fa ldrb r2, [r7, #3]
80037f4: 6879 ldr r1, [r7, #4]
80037f6: 4613 mov r3, r2
80037f8: 011b lsls r3, r3, #4
80037fa: 1a9b subs r3, r3, r2
80037fc: 009b lsls r3, r3, #2
80037fe: 440b add r3, r1
8003800: 334d adds r3, #77 @ 0x4d
8003802: 2202 movs r2, #2
8003804: 701a strb r2, [r3, #0]
hhcd->hc[chnum].ErrCnt++;
8003806: 78fa ldrb r2, [r7, #3]
8003808: 6879 ldr r1, [r7, #4]
800380a: 4613 mov r3, r2
800380c: 011b lsls r3, r3, #4
800380e: 1a9b subs r3, r3, r2
8003810: 009b lsls r3, r3, #2
8003812: 440b add r3, r1
8003814: 3344 adds r3, #68 @ 0x44
8003816: 681b ldr r3, [r3, #0]
8003818: 1c59 adds r1, r3, #1
800381a: 6878 ldr r0, [r7, #4]
800381c: 4613 mov r3, r2
800381e: 011b lsls r3, r3, #4
8003820: 1a9b subs r3, r3, r2
8003822: 009b lsls r3, r3, #2
8003824: 4403 add r3, r0
8003826: 3344 adds r3, #68 @ 0x44
8003828: 6019 str r1, [r3, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
800382a: 78fa ldrb r2, [r7, #3]
800382c: 6879 ldr r1, [r7, #4]
800382e: 4613 mov r3, r2
8003830: 011b lsls r3, r3, #4
8003832: 1a9b subs r3, r3, r2
8003834: 009b lsls r3, r3, #2
8003836: 440b add r3, r1
8003838: 3344 adds r3, #68 @ 0x44
800383a: 681b ldr r3, [r3, #0]
800383c: 2b02 cmp r3, #2
800383e: d914 bls.n 800386a <HCD_HC_OUT_IRQHandler+0x90c>
{
hhcd->hc[chnum].ErrCnt = 0U;
8003840: 78fa ldrb r2, [r7, #3]
8003842: 6879 ldr r1, [r7, #4]
8003844: 4613 mov r3, r2
8003846: 011b lsls r3, r3, #4
8003848: 1a9b subs r3, r3, r2
800384a: 009b lsls r3, r3, #2
800384c: 440b add r3, r1
800384e: 3344 adds r3, #68 @ 0x44
8003850: 2200 movs r2, #0
8003852: 601a str r2, [r3, #0]
hhcd->hc[chnum].urb_state = URB_ERROR;
8003854: 78fa ldrb r2, [r7, #3]
8003856: 6879 ldr r1, [r7, #4]
8003858: 4613 mov r3, r2
800385a: 011b lsls r3, r3, #4
800385c: 1a9b subs r3, r3, r2
800385e: 009b lsls r3, r3, #2
8003860: 440b add r3, r1
8003862: 334c adds r3, #76 @ 0x4c
8003864: 2204 movs r2, #4
8003866: 701a strb r2, [r3, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
8003868: e022 b.n 80038b0 <HCD_HC_OUT_IRQHandler+0x952>
}
else
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
800386a: 78fa ldrb r2, [r7, #3]
800386c: 6879 ldr r1, [r7, #4]
800386e: 4613 mov r3, r2
8003870: 011b lsls r3, r3, #4
8003872: 1a9b subs r3, r3, r2
8003874: 009b lsls r3, r3, #2
8003876: 440b add r3, r1
8003878: 334c adds r3, #76 @ 0x4c
800387a: 2202 movs r2, #2
800387c: 701a strb r2, [r3, #0]
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
800387e: 78fb ldrb r3, [r7, #3]
8003880: 015a lsls r2, r3, #5
8003882: 693b ldr r3, [r7, #16]
8003884: 4413 add r3, r2
8003886: f503 63a0 add.w r3, r3, #1280 @ 0x500
800388a: 681b ldr r3, [r3, #0]
800388c: 60fb str r3, [r7, #12]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
800388e: 68fb ldr r3, [r7, #12]
8003890: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8003894: 60fb str r3, [r7, #12]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8003896: 68fb ldr r3, [r7, #12]
8003898: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
800389c: 60fb str r3, [r7, #12]
USBx_HC(chnum)->HCCHAR = tmpreg;
800389e: 78fb ldrb r3, [r7, #3]
80038a0: 015a lsls r2, r3, #5
80038a2: 693b ldr r3, [r7, #16]
80038a4: 4413 add r3, r2
80038a6: f503 63a0 add.w r3, r3, #1280 @ 0x500
80038aa: 461a mov r2, r3
80038ac: 68fb ldr r3, [r7, #12]
80038ae: 6013 str r3, [r2, #0]
if (hhcd->hc[chnum].ErrCnt > 2U)
80038b0: bf00 nop
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
#else
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
80038b2: 78fa ldrb r2, [r7, #3]
80038b4: 6879 ldr r1, [r7, #4]
80038b6: 4613 mov r3, r2
80038b8: 011b lsls r3, r3, #4
80038ba: 1a9b subs r3, r3, r2
80038bc: 009b lsls r3, r3, #2
80038be: 440b add r3, r1
80038c0: 334c adds r3, #76 @ 0x4c
80038c2: 781a ldrb r2, [r3, #0]
80038c4: 78fb ldrb r3, [r7, #3]
80038c6: 4619 mov r1, r3
80038c8: 6878 ldr r0, [r7, #4]
80038ca: f004 fa6b bl 8007da4 <HAL_HCD_HC_NotifyURBChange_Callback>
80038ce: e002 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
else
{
return;
80038d0: bf00 nop
80038d2: e000 b.n 80038d6 <HCD_HC_OUT_IRQHandler+0x978>
return;
80038d4: bf00 nop
}
}
80038d6: 3718 adds r7, #24
80038d8: 46bd mov sp, r7
80038da: bd80 pop {r7, pc}
080038dc <HCD_RXQLVL_IRQHandler>:
* @brief Handle Rx Queue Level interrupt requests.
* @param hhcd HCD handle
* @retval none
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
{
80038dc: b580 push {r7, lr}
80038de: b08a sub sp, #40 @ 0x28
80038e0: af00 add r7, sp, #0
80038e2: 6078 str r0, [r7, #4]
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
80038e4: 687b ldr r3, [r7, #4]
80038e6: 681b ldr r3, [r3, #0]
80038e8: 627b str r3, [r7, #36] @ 0x24
uint32_t USBx_BASE = (uint32_t)USBx;
80038ea: 6a7b ldr r3, [r7, #36] @ 0x24
80038ec: 623b str r3, [r7, #32]
uint32_t GrxstspReg;
uint32_t xferSizePktCnt;
uint32_t tmpreg;
uint32_t chnum;
GrxstspReg = hhcd->Instance->GRXSTSP;
80038ee: 687b ldr r3, [r7, #4]
80038f0: 681b ldr r3, [r3, #0]
80038f2: 6a1b ldr r3, [r3, #32]
80038f4: 61fb str r3, [r7, #28]
chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
80038f6: 69fb ldr r3, [r7, #28]
80038f8: f003 030f and.w r3, r3, #15
80038fc: 61bb str r3, [r7, #24]
pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
80038fe: 69fb ldr r3, [r7, #28]
8003900: 0c5b lsrs r3, r3, #17
8003902: f003 030f and.w r3, r3, #15
8003906: 617b str r3, [r7, #20]
pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
8003908: 69fb ldr r3, [r7, #28]
800390a: 091b lsrs r3, r3, #4
800390c: f3c3 030a ubfx r3, r3, #0, #11
8003910: 613b str r3, [r7, #16]
switch (pktsts)
8003912: 697b ldr r3, [r7, #20]
8003914: 2b02 cmp r3, #2
8003916: d004 beq.n 8003922 <HCD_RXQLVL_IRQHandler+0x46>
8003918: 697b ldr r3, [r7, #20]
800391a: 2b05 cmp r3, #5
800391c: f000 80b6 beq.w 8003a8c <HCD_RXQLVL_IRQHandler+0x1b0>
break;
case GRXSTS_PKTSTS_IN_XFER_COMP:
case GRXSTS_PKTSTS_CH_HALTED:
default:
break;
8003920: e0b7 b.n 8003a92 <HCD_RXQLVL_IRQHandler+0x1b6>
if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
8003922: 693b ldr r3, [r7, #16]
8003924: 2b00 cmp r3, #0
8003926: f000 80b3 beq.w 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
800392a: 6879 ldr r1, [r7, #4]
800392c: 69ba ldr r2, [r7, #24]
800392e: 4613 mov r3, r2
8003930: 011b lsls r3, r3, #4
8003932: 1a9b subs r3, r3, r2
8003934: 009b lsls r3, r3, #2
8003936: 440b add r3, r1
8003938: 332c adds r3, #44 @ 0x2c
800393a: 681b ldr r3, [r3, #0]
800393c: 2b00 cmp r3, #0
800393e: f000 80a7 beq.w 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
8003942: 6879 ldr r1, [r7, #4]
8003944: 69ba ldr r2, [r7, #24]
8003946: 4613 mov r3, r2
8003948: 011b lsls r3, r3, #4
800394a: 1a9b subs r3, r3, r2
800394c: 009b lsls r3, r3, #2
800394e: 440b add r3, r1
8003950: 3338 adds r3, #56 @ 0x38
8003952: 681a ldr r2, [r3, #0]
8003954: 693b ldr r3, [r7, #16]
8003956: 18d1 adds r1, r2, r3
8003958: 6878 ldr r0, [r7, #4]
800395a: 69ba ldr r2, [r7, #24]
800395c: 4613 mov r3, r2
800395e: 011b lsls r3, r3, #4
8003960: 1a9b subs r3, r3, r2
8003962: 009b lsls r3, r3, #2
8003964: 4403 add r3, r0
8003966: 3334 adds r3, #52 @ 0x34
8003968: 681b ldr r3, [r3, #0]
800396a: 4299 cmp r1, r3
800396c: f200 8083 bhi.w 8003a76 <HCD_RXQLVL_IRQHandler+0x19a>
(void)USB_ReadPacket(hhcd->Instance,
8003970: 687b ldr r3, [r7, #4]
8003972: 6818 ldr r0, [r3, #0]
8003974: 6879 ldr r1, [r7, #4]
8003976: 69ba ldr r2, [r7, #24]
8003978: 4613 mov r3, r2
800397a: 011b lsls r3, r3, #4
800397c: 1a9b subs r3, r3, r2
800397e: 009b lsls r3, r3, #2
8003980: 440b add r3, r1
8003982: 332c adds r3, #44 @ 0x2c
8003984: 681b ldr r3, [r3, #0]
8003986: 693a ldr r2, [r7, #16]
8003988: b292 uxth r2, r2
800398a: 4619 mov r1, r3
800398c: f002 fd8a bl 80064a4 <USB_ReadPacket>
hhcd->hc[chnum].xfer_buff += pktcnt;
8003990: 6879 ldr r1, [r7, #4]
8003992: 69ba ldr r2, [r7, #24]
8003994: 4613 mov r3, r2
8003996: 011b lsls r3, r3, #4
8003998: 1a9b subs r3, r3, r2
800399a: 009b lsls r3, r3, #2
800399c: 440b add r3, r1
800399e: 332c adds r3, #44 @ 0x2c
80039a0: 681a ldr r2, [r3, #0]
80039a2: 693b ldr r3, [r7, #16]
80039a4: 18d1 adds r1, r2, r3
80039a6: 6878 ldr r0, [r7, #4]
80039a8: 69ba ldr r2, [r7, #24]
80039aa: 4613 mov r3, r2
80039ac: 011b lsls r3, r3, #4
80039ae: 1a9b subs r3, r3, r2
80039b0: 009b lsls r3, r3, #2
80039b2: 4403 add r3, r0
80039b4: 332c adds r3, #44 @ 0x2c
80039b6: 6019 str r1, [r3, #0]
hhcd->hc[chnum].xfer_count += pktcnt;
80039b8: 6879 ldr r1, [r7, #4]
80039ba: 69ba ldr r2, [r7, #24]
80039bc: 4613 mov r3, r2
80039be: 011b lsls r3, r3, #4
80039c0: 1a9b subs r3, r3, r2
80039c2: 009b lsls r3, r3, #2
80039c4: 440b add r3, r1
80039c6: 3338 adds r3, #56 @ 0x38
80039c8: 681a ldr r2, [r3, #0]
80039ca: 693b ldr r3, [r7, #16]
80039cc: 18d1 adds r1, r2, r3
80039ce: 6878 ldr r0, [r7, #4]
80039d0: 69ba ldr r2, [r7, #24]
80039d2: 4613 mov r3, r2
80039d4: 011b lsls r3, r3, #4
80039d6: 1a9b subs r3, r3, r2
80039d8: 009b lsls r3, r3, #2
80039da: 4403 add r3, r0
80039dc: 3338 adds r3, #56 @ 0x38
80039de: 6019 str r1, [r3, #0]
xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
80039e0: 69bb ldr r3, [r7, #24]
80039e2: 015a lsls r2, r3, #5
80039e4: 6a3b ldr r3, [r7, #32]
80039e6: 4413 add r3, r2
80039e8: f503 63a0 add.w r3, r3, #1280 @ 0x500
80039ec: 691b ldr r3, [r3, #16]
80039ee: 0cdb lsrs r3, r3, #19
80039f0: f3c3 0309 ubfx r3, r3, #0, #10
80039f4: 60fb str r3, [r7, #12]
if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
80039f6: 6879 ldr r1, [r7, #4]
80039f8: 69ba ldr r2, [r7, #24]
80039fa: 4613 mov r3, r2
80039fc: 011b lsls r3, r3, #4
80039fe: 1a9b subs r3, r3, r2
8003a00: 009b lsls r3, r3, #2
8003a02: 440b add r3, r1
8003a04: 3328 adds r3, #40 @ 0x28
8003a06: 881b ldrh r3, [r3, #0]
8003a08: 461a mov r2, r3
8003a0a: 693b ldr r3, [r7, #16]
8003a0c: 4293 cmp r3, r2
8003a0e: d13f bne.n 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
8003a10: 68fb ldr r3, [r7, #12]
8003a12: 2b00 cmp r3, #0
8003a14: d03c beq.n 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
tmpreg = USBx_HC(chnum)->HCCHAR;
8003a16: 69bb ldr r3, [r7, #24]
8003a18: 015a lsls r2, r3, #5
8003a1a: 6a3b ldr r3, [r7, #32]
8003a1c: 4413 add r3, r2
8003a1e: f503 63a0 add.w r3, r3, #1280 @ 0x500
8003a22: 681b ldr r3, [r3, #0]
8003a24: 60bb str r3, [r7, #8]
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
8003a26: 68bb ldr r3, [r7, #8]
8003a28: f023 4380 bic.w r3, r3, #1073741824 @ 0x40000000
8003a2c: 60bb str r3, [r7, #8]
tmpreg |= USB_OTG_HCCHAR_CHENA;
8003a2e: 68bb ldr r3, [r7, #8]
8003a30: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8003a34: 60bb str r3, [r7, #8]
USBx_HC(chnum)->HCCHAR = tmpreg;
8003a36: 69bb ldr r3, [r7, #24]
8003a38: 015a lsls r2, r3, #5
8003a3a: 6a3b ldr r3, [r7, #32]
8003a3c: 4413 add r3, r2
8003a3e: f503 63a0 add.w r3, r3, #1280 @ 0x500
8003a42: 461a mov r2, r3
8003a44: 68bb ldr r3, [r7, #8]
8003a46: 6013 str r3, [r2, #0]
hhcd->hc[chnum].toggle_in ^= 1U;
8003a48: 6879 ldr r1, [r7, #4]
8003a4a: 69ba ldr r2, [r7, #24]
8003a4c: 4613 mov r3, r2
8003a4e: 011b lsls r3, r3, #4
8003a50: 1a9b subs r3, r3, r2
8003a52: 009b lsls r3, r3, #2
8003a54: 440b add r3, r1
8003a56: 333c adds r3, #60 @ 0x3c
8003a58: 781b ldrb r3, [r3, #0]
8003a5a: f083 0301 eor.w r3, r3, #1
8003a5e: b2d8 uxtb r0, r3
8003a60: 6879 ldr r1, [r7, #4]
8003a62: 69ba ldr r2, [r7, #24]
8003a64: 4613 mov r3, r2
8003a66: 011b lsls r3, r3, #4
8003a68: 1a9b subs r3, r3, r2
8003a6a: 009b lsls r3, r3, #2
8003a6c: 440b add r3, r1
8003a6e: 333c adds r3, #60 @ 0x3c
8003a70: 4602 mov r2, r0
8003a72: 701a strb r2, [r3, #0]
break;
8003a74: e00c b.n 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
hhcd->hc[chnum].urb_state = URB_ERROR;
8003a76: 6879 ldr r1, [r7, #4]
8003a78: 69ba ldr r2, [r7, #24]
8003a7a: 4613 mov r3, r2
8003a7c: 011b lsls r3, r3, #4
8003a7e: 1a9b subs r3, r3, r2
8003a80: 009b lsls r3, r3, #2
8003a82: 440b add r3, r1
8003a84: 334c adds r3, #76 @ 0x4c
8003a86: 2204 movs r2, #4
8003a88: 701a strb r2, [r3, #0]
break;
8003a8a: e001 b.n 8003a90 <HCD_RXQLVL_IRQHandler+0x1b4>
break;
8003a8c: bf00 nop
8003a8e: e000 b.n 8003a92 <HCD_RXQLVL_IRQHandler+0x1b6>
break;
8003a90: bf00 nop
}
}
8003a92: bf00 nop
8003a94: 3728 adds r7, #40 @ 0x28
8003a96: 46bd mov sp, r7
8003a98: bd80 pop {r7, pc}
08003a9a <HCD_Port_IRQHandler>:
* @brief Handle Host Port interrupt requests.
* @param hhcd HCD handle
* @retval None
*/
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
{
8003a9a: b580 push {r7, lr}
8003a9c: b086 sub sp, #24
8003a9e: af00 add r7, sp, #0
8003aa0: 6078 str r0, [r7, #4]
const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
8003aa2: 687b ldr r3, [r7, #4]
8003aa4: 681b ldr r3, [r3, #0]
8003aa6: 617b str r3, [r7, #20]
uint32_t USBx_BASE = (uint32_t)USBx;
8003aa8: 697b ldr r3, [r7, #20]
8003aaa: 613b str r3, [r7, #16]
__IO uint32_t hprt0;
__IO uint32_t hprt0_dup;
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
8003aac: 693b ldr r3, [r7, #16]
8003aae: f503 6388 add.w r3, r3, #1088 @ 0x440
8003ab2: 681b ldr r3, [r3, #0]
8003ab4: 60fb str r3, [r7, #12]
hprt0_dup = USBx_HPRT0;
8003ab6: 693b ldr r3, [r7, #16]
8003ab8: f503 6388 add.w r3, r3, #1088 @ 0x440
8003abc: 681b ldr r3, [r3, #0]
8003abe: 60bb str r3, [r7, #8]
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \
8003ac0: 68bb ldr r3, [r7, #8]
8003ac2: f023 032e bic.w r3, r3, #46 @ 0x2e
8003ac6: 60bb str r3, [r7, #8]
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
/* Check whether Port Connect detected */
if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
8003ac8: 68fb ldr r3, [r7, #12]
8003aca: f003 0302 and.w r3, r3, #2
8003ace: 2b02 cmp r3, #2
8003ad0: d10b bne.n 8003aea <HCD_Port_IRQHandler+0x50>
{
if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
8003ad2: 68fb ldr r3, [r7, #12]
8003ad4: f003 0301 and.w r3, r3, #1
8003ad8: 2b01 cmp r3, #1
8003ada: d102 bne.n 8003ae2 <HCD_Port_IRQHandler+0x48>
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->ConnectCallback(hhcd);
#else
HAL_HCD_Connect_Callback(hhcd);
8003adc: 6878 ldr r0, [r7, #4]
8003ade: f004 f945 bl 8007d6c <HAL_HCD_Connect_Callback>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
8003ae2: 68bb ldr r3, [r7, #8]
8003ae4: f043 0302 orr.w r3, r3, #2
8003ae8: 60bb str r3, [r7, #8]
}
/* Check whether Port Enable Changed */
if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
8003aea: 68fb ldr r3, [r7, #12]
8003aec: f003 0308 and.w r3, r3, #8
8003af0: 2b08 cmp r3, #8
8003af2: d132 bne.n 8003b5a <HCD_Port_IRQHandler+0xc0>
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
8003af4: 68bb ldr r3, [r7, #8]
8003af6: f043 0308 orr.w r3, r3, #8
8003afa: 60bb str r3, [r7, #8]
if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
8003afc: 68fb ldr r3, [r7, #12]
8003afe: f003 0304 and.w r3, r3, #4
8003b02: 2b04 cmp r3, #4
8003b04: d126 bne.n 8003b54 <HCD_Port_IRQHandler+0xba>
{
if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
8003b06: 687b ldr r3, [r7, #4]
8003b08: 7a5b ldrb r3, [r3, #9]
8003b0a: 2b02 cmp r3, #2
8003b0c: d113 bne.n 8003b36 <HCD_Port_IRQHandler+0x9c>
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
8003b0e: 68fb ldr r3, [r7, #12]
8003b10: f403 23c0 and.w r3, r3, #393216 @ 0x60000
8003b14: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8003b18: d106 bne.n 8003b28 <HCD_Port_IRQHandler+0x8e>
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ);
8003b1a: 687b ldr r3, [r7, #4]
8003b1c: 681b ldr r3, [r3, #0]
8003b1e: 2102 movs r1, #2
8003b20: 4618 mov r0, r3
8003b22: f002 fd59 bl 80065d8 <USB_InitFSLSPClkSel>
8003b26: e011 b.n 8003b4c <HCD_Port_IRQHandler+0xb2>
}
else
{
(void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
8003b28: 687b ldr r3, [r7, #4]
8003b2a: 681b ldr r3, [r3, #0]
8003b2c: 2101 movs r1, #1
8003b2e: 4618 mov r0, r3
8003b30: f002 fd52 bl 80065d8 <USB_InitFSLSPClkSel>
8003b34: e00a b.n 8003b4c <HCD_Port_IRQHandler+0xb2>
}
}
else
{
if (hhcd->Init.speed == HCD_SPEED_FULL)
8003b36: 687b ldr r3, [r7, #4]
8003b38: 79db ldrb r3, [r3, #7]
8003b3a: 2b01 cmp r3, #1
8003b3c: d106 bne.n 8003b4c <HCD_Port_IRQHandler+0xb2>
{
USBx_HOST->HFIR = HFIR_60_MHZ;
8003b3e: 693b ldr r3, [r7, #16]
8003b40: f503 6380 add.w r3, r3, #1024 @ 0x400
8003b44: 461a mov r2, r3
8003b46: f64e 2360 movw r3, #60000 @ 0xea60
8003b4a: 6053 str r3, [r2, #4]
}
}
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortEnabledCallback(hhcd);
#else
HAL_HCD_PortEnabled_Callback(hhcd);
8003b4c: 6878 ldr r0, [r7, #4]
8003b4e: f004 f93b bl 8007dc8 <HAL_HCD_PortEnabled_Callback>
8003b52: e002 b.n 8003b5a <HCD_Port_IRQHandler+0xc0>
else
{
#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
hhcd->PortDisabledCallback(hhcd);
#else
HAL_HCD_PortDisabled_Callback(hhcd);
8003b54: 6878 ldr r0, [r7, #4]
8003b56: f004 f945 bl 8007de4 <HAL_HCD_PortDisabled_Callback>
#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
}
}
/* Check for an overcurrent */
if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
8003b5a: 68fb ldr r3, [r7, #12]
8003b5c: f003 0320 and.w r3, r3, #32
8003b60: 2b20 cmp r3, #32
8003b62: d103 bne.n 8003b6c <HCD_Port_IRQHandler+0xd2>
{
hprt0_dup |= USB_OTG_HPRT_POCCHNG;
8003b64: 68bb ldr r3, [r7, #8]
8003b66: f043 0320 orr.w r3, r3, #32
8003b6a: 60bb str r3, [r7, #8]
}
/* Clear Port Interrupts */
USBx_HPRT0 = hprt0_dup;
8003b6c: 693b ldr r3, [r7, #16]
8003b6e: f503 6388 add.w r3, r3, #1088 @ 0x440
8003b72: 461a mov r2, r3
8003b74: 68bb ldr r3, [r7, #8]
8003b76: 6013 str r3, [r2, #0]
}
8003b78: bf00 nop
8003b7a: 3718 adds r7, #24
8003b7c: 46bd mov sp, r7
8003b7e: bd80 pop {r7, pc}
08003b80 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003b80: b580 push {r7, lr}
8003b82: b084 sub sp, #16
8003b84: af00 add r7, sp, #0
8003b86: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003b88: 687b ldr r3, [r7, #4]
8003b8a: 2b00 cmp r3, #0
8003b8c: d101 bne.n 8003b92 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
8003b8e: 2301 movs r3, #1
8003b90: e12b b.n 8003dea <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003b92: 687b ldr r3, [r7, #4]
8003b94: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003b98: b2db uxtb r3, r3
8003b9a: 2b00 cmp r3, #0
8003b9c: d106 bne.n 8003bac <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
8003b9e: 687b ldr r3, [r7, #4]
8003ba0: 2200 movs r2, #0
8003ba2: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003ba6: 6878 ldr r0, [r7, #4]
8003ba8: f7fd f930 bl 8000e0c <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
8003bac: 687b ldr r3, [r7, #4]
8003bae: 2224 movs r2, #36 @ 0x24
8003bb0: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003bb4: 687b ldr r3, [r7, #4]
8003bb6: 681b ldr r3, [r3, #0]
8003bb8: 681a ldr r2, [r3, #0]
8003bba: 687b ldr r3, [r7, #4]
8003bbc: 681b ldr r3, [r3, #0]
8003bbe: f022 0201 bic.w r2, r2, #1
8003bc2: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003bc4: 687b ldr r3, [r7, #4]
8003bc6: 681b ldr r3, [r3, #0]
8003bc8: 681a ldr r2, [r3, #0]
8003bca: 687b ldr r3, [r7, #4]
8003bcc: 681b ldr r3, [r3, #0]
8003bce: f442 4200 orr.w r2, r2, #32768 @ 0x8000
8003bd2: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003bd4: 687b ldr r3, [r7, #4]
8003bd6: 681b ldr r3, [r3, #0]
8003bd8: 681a ldr r2, [r3, #0]
8003bda: 687b ldr r3, [r7, #4]
8003bdc: 681b ldr r3, [r3, #0]
8003bde: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003be2: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003be4: f001 f90c bl 8004e00 <HAL_RCC_GetPCLK1Freq>
8003be8: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
8003bea: 687b ldr r3, [r7, #4]
8003bec: 685b ldr r3, [r3, #4]
8003bee: 4a81 ldr r2, [pc, #516] @ (8003df4 <HAL_I2C_Init+0x274>)
8003bf0: 4293 cmp r3, r2
8003bf2: d807 bhi.n 8003c04 <HAL_I2C_Init+0x84>
8003bf4: 68fb ldr r3, [r7, #12]
8003bf6: 4a80 ldr r2, [pc, #512] @ (8003df8 <HAL_I2C_Init+0x278>)
8003bf8: 4293 cmp r3, r2
8003bfa: bf94 ite ls
8003bfc: 2301 movls r3, #1
8003bfe: 2300 movhi r3, #0
8003c00: b2db uxtb r3, r3
8003c02: e006 b.n 8003c12 <HAL_I2C_Init+0x92>
8003c04: 68fb ldr r3, [r7, #12]
8003c06: 4a7d ldr r2, [pc, #500] @ (8003dfc <HAL_I2C_Init+0x27c>)
8003c08: 4293 cmp r3, r2
8003c0a: bf94 ite ls
8003c0c: 2301 movls r3, #1
8003c0e: 2300 movhi r3, #0
8003c10: b2db uxtb r3, r3
8003c12: 2b00 cmp r3, #0
8003c14: d001 beq.n 8003c1a <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003c16: 2301 movs r3, #1
8003c18: e0e7 b.n 8003dea <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
8003c1a: 68fb ldr r3, [r7, #12]
8003c1c: 4a78 ldr r2, [pc, #480] @ (8003e00 <HAL_I2C_Init+0x280>)
8003c1e: fba2 2303 umull r2, r3, r2, r3
8003c22: 0c9b lsrs r3, r3, #18
8003c24: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
8003c26: 687b ldr r3, [r7, #4]
8003c28: 681b ldr r3, [r3, #0]
8003c2a: 685b ldr r3, [r3, #4]
8003c2c: f023 013f bic.w r1, r3, #63 @ 0x3f
8003c30: 687b ldr r3, [r7, #4]
8003c32: 681b ldr r3, [r3, #0]
8003c34: 68ba ldr r2, [r7, #8]
8003c36: 430a orrs r2, r1
8003c38: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
8003c3a: 687b ldr r3, [r7, #4]
8003c3c: 681b ldr r3, [r3, #0]
8003c3e: 6a1b ldr r3, [r3, #32]
8003c40: f023 013f bic.w r1, r3, #63 @ 0x3f
8003c44: 687b ldr r3, [r7, #4]
8003c46: 685b ldr r3, [r3, #4]
8003c48: 4a6a ldr r2, [pc, #424] @ (8003df4 <HAL_I2C_Init+0x274>)
8003c4a: 4293 cmp r3, r2
8003c4c: d802 bhi.n 8003c54 <HAL_I2C_Init+0xd4>
8003c4e: 68bb ldr r3, [r7, #8]
8003c50: 3301 adds r3, #1
8003c52: e009 b.n 8003c68 <HAL_I2C_Init+0xe8>
8003c54: 68bb ldr r3, [r7, #8]
8003c56: f44f 7296 mov.w r2, #300 @ 0x12c
8003c5a: fb02 f303 mul.w r3, r2, r3
8003c5e: 4a69 ldr r2, [pc, #420] @ (8003e04 <HAL_I2C_Init+0x284>)
8003c60: fba2 2303 umull r2, r3, r2, r3
8003c64: 099b lsrs r3, r3, #6
8003c66: 3301 adds r3, #1
8003c68: 687a ldr r2, [r7, #4]
8003c6a: 6812 ldr r2, [r2, #0]
8003c6c: 430b orrs r3, r1
8003c6e: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
8003c70: 687b ldr r3, [r7, #4]
8003c72: 681b ldr r3, [r3, #0]
8003c74: 69db ldr r3, [r3, #28]
8003c76: f423 424f bic.w r2, r3, #52992 @ 0xcf00
8003c7a: f022 02ff bic.w r2, r2, #255 @ 0xff
8003c7e: 687b ldr r3, [r7, #4]
8003c80: 685b ldr r3, [r3, #4]
8003c82: 495c ldr r1, [pc, #368] @ (8003df4 <HAL_I2C_Init+0x274>)
8003c84: 428b cmp r3, r1
8003c86: d819 bhi.n 8003cbc <HAL_I2C_Init+0x13c>
8003c88: 68fb ldr r3, [r7, #12]
8003c8a: 1e59 subs r1, r3, #1
8003c8c: 687b ldr r3, [r7, #4]
8003c8e: 685b ldr r3, [r3, #4]
8003c90: 005b lsls r3, r3, #1
8003c92: fbb1 f3f3 udiv r3, r1, r3
8003c96: 1c59 adds r1, r3, #1
8003c98: f640 73fc movw r3, #4092 @ 0xffc
8003c9c: 400b ands r3, r1
8003c9e: 2b00 cmp r3, #0
8003ca0: d00a beq.n 8003cb8 <HAL_I2C_Init+0x138>
8003ca2: 68fb ldr r3, [r7, #12]
8003ca4: 1e59 subs r1, r3, #1
8003ca6: 687b ldr r3, [r7, #4]
8003ca8: 685b ldr r3, [r3, #4]
8003caa: 005b lsls r3, r3, #1
8003cac: fbb1 f3f3 udiv r3, r1, r3
8003cb0: 3301 adds r3, #1
8003cb2: f3c3 030b ubfx r3, r3, #0, #12
8003cb6: e051 b.n 8003d5c <HAL_I2C_Init+0x1dc>
8003cb8: 2304 movs r3, #4
8003cba: e04f b.n 8003d5c <HAL_I2C_Init+0x1dc>
8003cbc: 687b ldr r3, [r7, #4]
8003cbe: 689b ldr r3, [r3, #8]
8003cc0: 2b00 cmp r3, #0
8003cc2: d111 bne.n 8003ce8 <HAL_I2C_Init+0x168>
8003cc4: 68fb ldr r3, [r7, #12]
8003cc6: 1e58 subs r0, r3, #1
8003cc8: 687b ldr r3, [r7, #4]
8003cca: 6859 ldr r1, [r3, #4]
8003ccc: 460b mov r3, r1
8003cce: 005b lsls r3, r3, #1
8003cd0: 440b add r3, r1
8003cd2: fbb0 f3f3 udiv r3, r0, r3
8003cd6: 3301 adds r3, #1
8003cd8: f3c3 030b ubfx r3, r3, #0, #12
8003cdc: 2b00 cmp r3, #0
8003cde: bf0c ite eq
8003ce0: 2301 moveq r3, #1
8003ce2: 2300 movne r3, #0
8003ce4: b2db uxtb r3, r3
8003ce6: e012 b.n 8003d0e <HAL_I2C_Init+0x18e>
8003ce8: 68fb ldr r3, [r7, #12]
8003cea: 1e58 subs r0, r3, #1
8003cec: 687b ldr r3, [r7, #4]
8003cee: 6859 ldr r1, [r3, #4]
8003cf0: 460b mov r3, r1
8003cf2: 009b lsls r3, r3, #2
8003cf4: 440b add r3, r1
8003cf6: 0099 lsls r1, r3, #2
8003cf8: 440b add r3, r1
8003cfa: fbb0 f3f3 udiv r3, r0, r3
8003cfe: 3301 adds r3, #1
8003d00: f3c3 030b ubfx r3, r3, #0, #12
8003d04: 2b00 cmp r3, #0
8003d06: bf0c ite eq
8003d08: 2301 moveq r3, #1
8003d0a: 2300 movne r3, #0
8003d0c: b2db uxtb r3, r3
8003d0e: 2b00 cmp r3, #0
8003d10: d001 beq.n 8003d16 <HAL_I2C_Init+0x196>
8003d12: 2301 movs r3, #1
8003d14: e022 b.n 8003d5c <HAL_I2C_Init+0x1dc>
8003d16: 687b ldr r3, [r7, #4]
8003d18: 689b ldr r3, [r3, #8]
8003d1a: 2b00 cmp r3, #0
8003d1c: d10e bne.n 8003d3c <HAL_I2C_Init+0x1bc>
8003d1e: 68fb ldr r3, [r7, #12]
8003d20: 1e58 subs r0, r3, #1
8003d22: 687b ldr r3, [r7, #4]
8003d24: 6859 ldr r1, [r3, #4]
8003d26: 460b mov r3, r1
8003d28: 005b lsls r3, r3, #1
8003d2a: 440b add r3, r1
8003d2c: fbb0 f3f3 udiv r3, r0, r3
8003d30: 3301 adds r3, #1
8003d32: f3c3 030b ubfx r3, r3, #0, #12
8003d36: f443 4300 orr.w r3, r3, #32768 @ 0x8000
8003d3a: e00f b.n 8003d5c <HAL_I2C_Init+0x1dc>
8003d3c: 68fb ldr r3, [r7, #12]
8003d3e: 1e58 subs r0, r3, #1
8003d40: 687b ldr r3, [r7, #4]
8003d42: 6859 ldr r1, [r3, #4]
8003d44: 460b mov r3, r1
8003d46: 009b lsls r3, r3, #2
8003d48: 440b add r3, r1
8003d4a: 0099 lsls r1, r3, #2
8003d4c: 440b add r3, r1
8003d4e: fbb0 f3f3 udiv r3, r0, r3
8003d52: 3301 adds r3, #1
8003d54: f3c3 030b ubfx r3, r3, #0, #12
8003d58: f443 4340 orr.w r3, r3, #49152 @ 0xc000
8003d5c: 6879 ldr r1, [r7, #4]
8003d5e: 6809 ldr r1, [r1, #0]
8003d60: 4313 orrs r3, r2
8003d62: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
8003d64: 687b ldr r3, [r7, #4]
8003d66: 681b ldr r3, [r3, #0]
8003d68: 681b ldr r3, [r3, #0]
8003d6a: f023 01c0 bic.w r1, r3, #192 @ 0xc0
8003d6e: 687b ldr r3, [r7, #4]
8003d70: 69da ldr r2, [r3, #28]
8003d72: 687b ldr r3, [r7, #4]
8003d74: 6a1b ldr r3, [r3, #32]
8003d76: 431a orrs r2, r3
8003d78: 687b ldr r3, [r7, #4]
8003d7a: 681b ldr r3, [r3, #0]
8003d7c: 430a orrs r2, r1
8003d7e: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8003d80: 687b ldr r3, [r7, #4]
8003d82: 681b ldr r3, [r3, #0]
8003d84: 689b ldr r3, [r3, #8]
8003d86: f423 4303 bic.w r3, r3, #33536 @ 0x8300
8003d8a: f023 03ff bic.w r3, r3, #255 @ 0xff
8003d8e: 687a ldr r2, [r7, #4]
8003d90: 6911 ldr r1, [r2, #16]
8003d92: 687a ldr r2, [r7, #4]
8003d94: 68d2 ldr r2, [r2, #12]
8003d96: 4311 orrs r1, r2
8003d98: 687a ldr r2, [r7, #4]
8003d9a: 6812 ldr r2, [r2, #0]
8003d9c: 430b orrs r3, r1
8003d9e: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
8003da0: 687b ldr r3, [r7, #4]
8003da2: 681b ldr r3, [r3, #0]
8003da4: 68db ldr r3, [r3, #12]
8003da6: f023 01ff bic.w r1, r3, #255 @ 0xff
8003daa: 687b ldr r3, [r7, #4]
8003dac: 695a ldr r2, [r3, #20]
8003dae: 687b ldr r3, [r7, #4]
8003db0: 699b ldr r3, [r3, #24]
8003db2: 431a orrs r2, r3
8003db4: 687b ldr r3, [r7, #4]
8003db6: 681b ldr r3, [r3, #0]
8003db8: 430a orrs r2, r1
8003dba: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
8003dbc: 687b ldr r3, [r7, #4]
8003dbe: 681b ldr r3, [r3, #0]
8003dc0: 681a ldr r2, [r3, #0]
8003dc2: 687b ldr r3, [r7, #4]
8003dc4: 681b ldr r3, [r3, #0]
8003dc6: f042 0201 orr.w r2, r2, #1
8003dca: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8003dcc: 687b ldr r3, [r7, #4]
8003dce: 2200 movs r2, #0
8003dd0: 641a str r2, [r3, #64] @ 0x40
hi2c->State = HAL_I2C_STATE_READY;
8003dd2: 687b ldr r3, [r7, #4]
8003dd4: 2220 movs r2, #32
8003dd6: f883 203d strb.w r2, [r3, #61] @ 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
8003dda: 687b ldr r3, [r7, #4]
8003ddc: 2200 movs r2, #0
8003dde: 631a str r2, [r3, #48] @ 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8003de0: 687b ldr r3, [r7, #4]
8003de2: 2200 movs r2, #0
8003de4: f883 203e strb.w r2, [r3, #62] @ 0x3e
return HAL_OK;
8003de8: 2300 movs r3, #0
}
8003dea: 4618 mov r0, r3
8003dec: 3710 adds r7, #16
8003dee: 46bd mov sp, r7
8003df0: bd80 pop {r7, pc}
8003df2: bf00 nop
8003df4: 000186a0 .word 0x000186a0
8003df8: 001e847f .word 0x001e847f
8003dfc: 003d08ff .word 0x003d08ff
8003e00: 431bde83 .word 0x431bde83
8003e04: 10624dd3 .word 0x10624dd3
08003e08 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter new state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
8003e08: b480 push {r7}
8003e0a: b083 sub sp, #12
8003e0c: af00 add r7, sp, #0
8003e0e: 6078 str r0, [r7, #4]
8003e10: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8003e12: 687b ldr r3, [r7, #4]
8003e14: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003e18: b2db uxtb r3, r3
8003e1a: 2b20 cmp r3, #32
8003e1c: d129 bne.n 8003e72 <HAL_I2CEx_ConfigAnalogFilter+0x6a>
{
hi2c->State = HAL_I2C_STATE_BUSY;
8003e1e: 687b ldr r3, [r7, #4]
8003e20: 2224 movs r2, #36 @ 0x24
8003e22: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003e26: 687b ldr r3, [r7, #4]
8003e28: 681b ldr r3, [r3, #0]
8003e2a: 681a ldr r2, [r3, #0]
8003e2c: 687b ldr r3, [r7, #4]
8003e2e: 681b ldr r3, [r3, #0]
8003e30: f022 0201 bic.w r2, r2, #1
8003e34: 601a str r2, [r3, #0]
/* Reset I2Cx ANOFF bit */
hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);
8003e36: 687b ldr r3, [r7, #4]
8003e38: 681b ldr r3, [r3, #0]
8003e3a: 6a5a ldr r2, [r3, #36] @ 0x24
8003e3c: 687b ldr r3, [r7, #4]
8003e3e: 681b ldr r3, [r3, #0]
8003e40: f022 0210 bic.w r2, r2, #16
8003e44: 625a str r2, [r3, #36] @ 0x24
/* Disable the analog filter */
hi2c->Instance->FLTR |= AnalogFilter;
8003e46: 687b ldr r3, [r7, #4]
8003e48: 681b ldr r3, [r3, #0]
8003e4a: 6a59 ldr r1, [r3, #36] @ 0x24
8003e4c: 687b ldr r3, [r7, #4]
8003e4e: 681b ldr r3, [r3, #0]
8003e50: 683a ldr r2, [r7, #0]
8003e52: 430a orrs r2, r1
8003e54: 625a str r2, [r3, #36] @ 0x24
__HAL_I2C_ENABLE(hi2c);
8003e56: 687b ldr r3, [r7, #4]
8003e58: 681b ldr r3, [r3, #0]
8003e5a: 681a ldr r2, [r3, #0]
8003e5c: 687b ldr r3, [r7, #4]
8003e5e: 681b ldr r3, [r3, #0]
8003e60: f042 0201 orr.w r2, r2, #1
8003e64: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003e66: 687b ldr r3, [r7, #4]
8003e68: 2220 movs r2, #32
8003e6a: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003e6e: 2300 movs r3, #0
8003e70: e000 b.n 8003e74 <HAL_I2CEx_ConfigAnalogFilter+0x6c>
}
else
{
return HAL_BUSY;
8003e72: 2302 movs r3, #2
}
}
8003e74: 4618 mov r0, r3
8003e76: 370c adds r7, #12
8003e78: 46bd mov sp, r7
8003e7a: f85d 7b04 ldr.w r7, [sp], #4
8003e7e: 4770 bx lr
08003e80 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
8003e80: b480 push {r7}
8003e82: b085 sub sp, #20
8003e84: af00 add r7, sp, #0
8003e86: 6078 str r0, [r7, #4]
8003e88: 6039 str r1, [r7, #0]
uint16_t tmpreg = 0;
8003e8a: 2300 movs r3, #0
8003e8c: 81fb strh r3, [r7, #14]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
8003e8e: 687b ldr r3, [r7, #4]
8003e90: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8003e94: b2db uxtb r3, r3
8003e96: 2b20 cmp r3, #32
8003e98: d12a bne.n 8003ef0 <HAL_I2CEx_ConfigDigitalFilter+0x70>
{
hi2c->State = HAL_I2C_STATE_BUSY;
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 2224 movs r2, #36 @ 0x24
8003e9e: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003ea2: 687b ldr r3, [r7, #4]
8003ea4: 681b ldr r3, [r3, #0]
8003ea6: 681a ldr r2, [r3, #0]
8003ea8: 687b ldr r3, [r7, #4]
8003eaa: 681b ldr r3, [r3, #0]
8003eac: f022 0201 bic.w r2, r2, #1
8003eb0: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->FLTR;
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: 681b ldr r3, [r3, #0]
8003eb6: 6a5b ldr r3, [r3, #36] @ 0x24
8003eb8: 81fb strh r3, [r7, #14]
/* Reset I2Cx DNF bit [3:0] */
tmpreg &= ~(I2C_FLTR_DNF);
8003eba: 89fb ldrh r3, [r7, #14]
8003ebc: f023 030f bic.w r3, r3, #15
8003ec0: 81fb strh r3, [r7, #14]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter;
8003ec2: 683b ldr r3, [r7, #0]
8003ec4: b29a uxth r2, r3
8003ec6: 89fb ldrh r3, [r7, #14]
8003ec8: 4313 orrs r3, r2
8003eca: 81fb strh r3, [r7, #14]
/* Store the new register value */
hi2c->Instance->FLTR = tmpreg;
8003ecc: 687b ldr r3, [r7, #4]
8003ece: 681b ldr r3, [r3, #0]
8003ed0: 89fa ldrh r2, [r7, #14]
8003ed2: 625a str r2, [r3, #36] @ 0x24
__HAL_I2C_ENABLE(hi2c);
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 681b ldr r3, [r3, #0]
8003ed8: 681a ldr r2, [r3, #0]
8003eda: 687b ldr r3, [r7, #4]
8003edc: 681b ldr r3, [r3, #0]
8003ede: f042 0201 orr.w r2, r2, #1
8003ee2: 601a str r2, [r3, #0]
hi2c->State = HAL_I2C_STATE_READY;
8003ee4: 687b ldr r3, [r7, #4]
8003ee6: 2220 movs r2, #32
8003ee8: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8003eec: 2300 movs r3, #0
8003eee: e000 b.n 8003ef2 <HAL_I2CEx_ConfigDigitalFilter+0x72>
}
else
{
return HAL_BUSY;
8003ef0: 2302 movs r3, #2
}
}
8003ef2: 4618 mov r0, r3
8003ef4: 3714 adds r7, #20
8003ef6: 46bd mov sp, r7
8003ef8: f85d 7b04 ldr.w r7, [sp], #4
8003efc: 4770 bx lr
08003efe <HAL_LTDC_Init>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
{
8003efe: b580 push {r7, lr}
8003f00: b084 sub sp, #16
8003f02: af00 add r7, sp, #0
8003f04: 6078 str r0, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
/* Check the LTDC peripheral state */
if (hltdc == NULL)
8003f06: 687b ldr r3, [r7, #4]
8003f08: 2b00 cmp r3, #0
8003f0a: d101 bne.n 8003f10 <HAL_LTDC_Init+0x12>
{
return HAL_ERROR;
8003f0c: 2301 movs r3, #1
8003f0e: e08f b.n 8004030 <HAL_LTDC_Init+0x132>
}
/* Init the low level hardware */
hltdc->MspInitCallback(hltdc);
}
#else
if (hltdc->State == HAL_LTDC_STATE_RESET)
8003f10: 687b ldr r3, [r7, #4]
8003f12: f893 30a1 ldrb.w r3, [r3, #161] @ 0xa1
8003f16: b2db uxtb r3, r3
8003f18: 2b00 cmp r3, #0
8003f1a: d106 bne.n 8003f2a <HAL_LTDC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hltdc->Lock = HAL_UNLOCKED;
8003f1c: 687b ldr r3, [r7, #4]
8003f1e: 2200 movs r2, #0
8003f20: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
/* Init the low level hardware */
HAL_LTDC_MspInit(hltdc);
8003f24: 6878 ldr r0, [r7, #4]
8003f26: f7fc ffdb bl 8000ee0 <HAL_LTDC_MspInit>
}
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
8003f2a: 687b ldr r3, [r7, #4]
8003f2c: 2202 movs r2, #2
8003f2e: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Configure the HS, VS, DE and PC polarity */
hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL);
8003f32: 687b ldr r3, [r7, #4]
8003f34: 681b ldr r3, [r3, #0]
8003f36: 699a ldr r2, [r3, #24]
8003f38: 687b ldr r3, [r7, #4]
8003f3a: 681b ldr r3, [r3, #0]
8003f3c: f022 4270 bic.w r2, r2, #4026531840 @ 0xf0000000
8003f40: 619a str r2, [r3, #24]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8003f42: 687b ldr r3, [r7, #4]
8003f44: 681b ldr r3, [r3, #0]
8003f46: 6999 ldr r1, [r3, #24]
8003f48: 687b ldr r3, [r7, #4]
8003f4a: 685a ldr r2, [r3, #4]
8003f4c: 687b ldr r3, [r7, #4]
8003f4e: 689b ldr r3, [r3, #8]
8003f50: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8003f52: 687b ldr r3, [r7, #4]
8003f54: 68db ldr r3, [r3, #12]
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8003f56: 431a orrs r2, r3
hltdc->Init.DEPolarity | hltdc->Init.PCPolarity);
8003f58: 687b ldr r3, [r7, #4]
8003f5a: 691b ldr r3, [r3, #16]
8003f5c: 431a orrs r2, r3
hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \
8003f5e: 687b ldr r3, [r7, #4]
8003f60: 681b ldr r3, [r3, #0]
8003f62: 430a orrs r2, r1
8003f64: 619a str r2, [r3, #24]
/* Set Synchronization size */
tmp = (hltdc->Init.HorizontalSync << 16U);
8003f66: 687b ldr r3, [r7, #4]
8003f68: 695b ldr r3, [r3, #20]
8003f6a: 041b lsls r3, r3, #16
8003f6c: 60fb str r3, [r7, #12]
WRITE_REG(hltdc->Instance->SSCR, (tmp | hltdc->Init.VerticalSync));
8003f6e: 687b ldr r3, [r7, #4]
8003f70: 6999 ldr r1, [r3, #24]
8003f72: 687b ldr r3, [r7, #4]
8003f74: 681b ldr r3, [r3, #0]
8003f76: 68fa ldr r2, [r7, #12]
8003f78: 430a orrs r2, r1
8003f7a: 609a str r2, [r3, #8]
/* Set Accumulated Back porch */
tmp = (hltdc->Init.AccumulatedHBP << 16U);
8003f7c: 687b ldr r3, [r7, #4]
8003f7e: 69db ldr r3, [r3, #28]
8003f80: 041b lsls r3, r3, #16
8003f82: 60fb str r3, [r7, #12]
WRITE_REG(hltdc->Instance->BPCR, (tmp | hltdc->Init.AccumulatedVBP));
8003f84: 687b ldr r3, [r7, #4]
8003f86: 6a19 ldr r1, [r3, #32]
8003f88: 687b ldr r3, [r7, #4]
8003f8a: 681b ldr r3, [r3, #0]
8003f8c: 68fa ldr r2, [r7, #12]
8003f8e: 430a orrs r2, r1
8003f90: 60da str r2, [r3, #12]
/* Set Accumulated Active Width */
tmp = (hltdc->Init.AccumulatedActiveW << 16U);
8003f92: 687b ldr r3, [r7, #4]
8003f94: 6a5b ldr r3, [r3, #36] @ 0x24
8003f96: 041b lsls r3, r3, #16
8003f98: 60fb str r3, [r7, #12]
WRITE_REG(hltdc->Instance->AWCR, (tmp | hltdc->Init.AccumulatedActiveH));
8003f9a: 687b ldr r3, [r7, #4]
8003f9c: 6a99 ldr r1, [r3, #40] @ 0x28
8003f9e: 687b ldr r3, [r7, #4]
8003fa0: 681b ldr r3, [r3, #0]
8003fa2: 68fa ldr r2, [r7, #12]
8003fa4: 430a orrs r2, r1
8003fa6: 611a str r2, [r3, #16]
/* Set Total Width */
tmp = (hltdc->Init.TotalWidth << 16U);
8003fa8: 687b ldr r3, [r7, #4]
8003faa: 6adb ldr r3, [r3, #44] @ 0x2c
8003fac: 041b lsls r3, r3, #16
8003fae: 60fb str r3, [r7, #12]
WRITE_REG(hltdc->Instance->TWCR, (tmp | hltdc->Init.TotalHeigh));
8003fb0: 687b ldr r3, [r7, #4]
8003fb2: 6b19 ldr r1, [r3, #48] @ 0x30
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 681b ldr r3, [r3, #0]
8003fb8: 68fa ldr r2, [r7, #12]
8003fba: 430a orrs r2, r1
8003fbc: 615a str r2, [r3, #20]
/* Set the background color value */
tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U);
8003fbe: 687b ldr r3, [r7, #4]
8003fc0: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
8003fc4: 021b lsls r3, r3, #8
8003fc6: 60fb str r3, [r7, #12]
tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U);
8003fc8: 687b ldr r3, [r7, #4]
8003fca: f893 3036 ldrb.w r3, [r3, #54] @ 0x36
8003fce: 041b lsls r3, r3, #16
8003fd0: 60bb str r3, [r7, #8]
hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED);
8003fd2: 687b ldr r3, [r7, #4]
8003fd4: 681b ldr r3, [r3, #0]
8003fd6: 6ada ldr r2, [r3, #44] @ 0x2c
8003fd8: 687b ldr r3, [r7, #4]
8003fda: 681b ldr r3, [r3, #0]
8003fdc: f002 427f and.w r2, r2, #4278190080 @ 0xff000000
8003fe0: 62da str r2, [r3, #44] @ 0x2c
hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue);
8003fe2: 687b ldr r3, [r7, #4]
8003fe4: 681b ldr r3, [r3, #0]
8003fe6: 6ad9 ldr r1, [r3, #44] @ 0x2c
8003fe8: 68ba ldr r2, [r7, #8]
8003fea: 68fb ldr r3, [r7, #12]
8003fec: 4313 orrs r3, r2
8003fee: 687a ldr r2, [r7, #4]
8003ff0: f892 2034 ldrb.w r2, [r2, #52] @ 0x34
8003ff4: 431a orrs r2, r3
8003ff6: 687b ldr r3, [r7, #4]
8003ff8: 681b ldr r3, [r3, #0]
8003ffa: 430a orrs r2, r1
8003ffc: 62da str r2, [r3, #44] @ 0x2c
/* Enable the Transfer Error and FIFO underrun interrupts */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU);
8003ffe: 687b ldr r3, [r7, #4]
8004000: 681b ldr r3, [r3, #0]
8004002: 6b5a ldr r2, [r3, #52] @ 0x34
8004004: 687b ldr r3, [r7, #4]
8004006: 681b ldr r3, [r3, #0]
8004008: f042 0206 orr.w r2, r2, #6
800400c: 635a str r2, [r3, #52] @ 0x34
/* Enable LTDC by setting LTDCEN bit */
__HAL_LTDC_ENABLE(hltdc);
800400e: 687b ldr r3, [r7, #4]
8004010: 681b ldr r3, [r3, #0]
8004012: 699a ldr r2, [r3, #24]
8004014: 687b ldr r3, [r7, #4]
8004016: 681b ldr r3, [r3, #0]
8004018: f042 0201 orr.w r2, r2, #1
800401c: 619a str r2, [r3, #24]
/* Initialize the error code */
hltdc->ErrorCode = HAL_LTDC_ERROR_NONE;
800401e: 687b ldr r3, [r7, #4]
8004020: 2200 movs r2, #0
8004022: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
8004026: 687b ldr r3, [r7, #4]
8004028: 2201 movs r2, #1
800402a: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
return HAL_OK;
800402e: 2300 movs r3, #0
}
8004030: 4618 mov r0, r3
8004032: 3710 adds r7, #16
8004034: 46bd mov sp, r7
8004036: bd80 pop {r7, pc}
08004038 <HAL_LTDC_IRQHandler>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
{
8004038: b580 push {r7, lr}
800403a: b084 sub sp, #16
800403c: af00 add r7, sp, #0
800403e: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(hltdc->Instance->ISR);
8004040: 687b ldr r3, [r7, #4]
8004042: 681b ldr r3, [r3, #0]
8004044: 6b9b ldr r3, [r3, #56] @ 0x38
8004046: 60fb str r3, [r7, #12]
uint32_t itsources = READ_REG(hltdc->Instance->IER);
8004048: 687b ldr r3, [r7, #4]
800404a: 681b ldr r3, [r3, #0]
800404c: 6b5b ldr r3, [r3, #52] @ 0x34
800404e: 60bb str r3, [r7, #8]
/* Transfer Error Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U))
8004050: 68fb ldr r3, [r7, #12]
8004052: f003 0304 and.w r3, r3, #4
8004056: 2b00 cmp r3, #0
8004058: d023 beq.n 80040a2 <HAL_LTDC_IRQHandler+0x6a>
800405a: 68bb ldr r3, [r7, #8]
800405c: f003 0304 and.w r3, r3, #4
8004060: 2b00 cmp r3, #0
8004062: d01e beq.n 80040a2 <HAL_LTDC_IRQHandler+0x6a>
{
/* Disable the transfer Error interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE);
8004064: 687b ldr r3, [r7, #4]
8004066: 681b ldr r3, [r3, #0]
8004068: 6b5a ldr r2, [r3, #52] @ 0x34
800406a: 687b ldr r3, [r7, #4]
800406c: 681b ldr r3, [r3, #0]
800406e: f022 0204 bic.w r2, r2, #4
8004072: 635a str r2, [r3, #52] @ 0x34
/* Clear the transfer error flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE);
8004074: 687b ldr r3, [r7, #4]
8004076: 681b ldr r3, [r3, #0]
8004078: 2204 movs r2, #4
800407a: 63da str r2, [r3, #60] @ 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_TE;
800407c: 687b ldr r3, [r7, #4]
800407e: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
8004082: f043 0201 orr.w r2, r3, #1
8004086: 687b ldr r3, [r7, #4]
8004088: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
800408c: 687b ldr r3, [r7, #4]
800408e: 2204 movs r2, #4
8004090: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8004094: 687b ldr r3, [r7, #4]
8004096: 2200 movs r2, #0
8004098: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
800409c: 6878 ldr r0, [r7, #4]
800409e: f000 f86f bl 8004180 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* FIFO underrun Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U))
80040a2: 68fb ldr r3, [r7, #12]
80040a4: f003 0302 and.w r3, r3, #2
80040a8: 2b00 cmp r3, #0
80040aa: d023 beq.n 80040f4 <HAL_LTDC_IRQHandler+0xbc>
80040ac: 68bb ldr r3, [r7, #8]
80040ae: f003 0302 and.w r3, r3, #2
80040b2: 2b00 cmp r3, #0
80040b4: d01e beq.n 80040f4 <HAL_LTDC_IRQHandler+0xbc>
{
/* Disable the FIFO underrun interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU);
80040b6: 687b ldr r3, [r7, #4]
80040b8: 681b ldr r3, [r3, #0]
80040ba: 6b5a ldr r2, [r3, #52] @ 0x34
80040bc: 687b ldr r3, [r7, #4]
80040be: 681b ldr r3, [r3, #0]
80040c0: f022 0202 bic.w r2, r2, #2
80040c4: 635a str r2, [r3, #52] @ 0x34
/* Clear the FIFO underrun flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU);
80040c6: 687b ldr r3, [r7, #4]
80040c8: 681b ldr r3, [r3, #0]
80040ca: 2202 movs r2, #2
80040cc: 63da str r2, [r3, #60] @ 0x3c
/* Update error code */
hltdc->ErrorCode |= HAL_LTDC_ERROR_FU;
80040ce: 687b ldr r3, [r7, #4]
80040d0: f8d3 30a4 ldr.w r3, [r3, #164] @ 0xa4
80040d4: f043 0202 orr.w r2, r3, #2
80040d8: 687b ldr r3, [r7, #4]
80040da: f8c3 20a4 str.w r2, [r3, #164] @ 0xa4
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_ERROR;
80040de: 687b ldr r3, [r7, #4]
80040e0: 2204 movs r2, #4
80040e2: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
80040e6: 687b ldr r3, [r7, #4]
80040e8: 2200 movs r2, #0
80040ea: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hltdc->ErrorCallback(hltdc);
#else
/* Call legacy error callback*/
HAL_LTDC_ErrorCallback(hltdc);
80040ee: 6878 ldr r0, [r7, #4]
80040f0: f000 f846 bl 8004180 <HAL_LTDC_ErrorCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Line Interrupt management ************************************************/
if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U))
80040f4: 68fb ldr r3, [r7, #12]
80040f6: f003 0301 and.w r3, r3, #1
80040fa: 2b00 cmp r3, #0
80040fc: d01b beq.n 8004136 <HAL_LTDC_IRQHandler+0xfe>
80040fe: 68bb ldr r3, [r7, #8]
8004100: f003 0301 and.w r3, r3, #1
8004104: 2b00 cmp r3, #0
8004106: d016 beq.n 8004136 <HAL_LTDC_IRQHandler+0xfe>
{
/* Disable the Line interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI);
8004108: 687b ldr r3, [r7, #4]
800410a: 681b ldr r3, [r3, #0]
800410c: 6b5a ldr r2, [r3, #52] @ 0x34
800410e: 687b ldr r3, [r7, #4]
8004110: 681b ldr r3, [r3, #0]
8004112: f022 0201 bic.w r2, r2, #1
8004116: 635a str r2, [r3, #52] @ 0x34
/* Clear the Line interrupt flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI);
8004118: 687b ldr r3, [r7, #4]
800411a: 681b ldr r3, [r3, #0]
800411c: 2201 movs r2, #1
800411e: 63da str r2, [r3, #60] @ 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8004120: 687b ldr r3, [r7, #4]
8004122: 2201 movs r2, #1
8004124: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8004128: 687b ldr r3, [r7, #4]
800412a: 2200 movs r2, #0
800412c: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered Line Event callback */
hltdc->LineEventCallback(hltdc);
#else
/*Call Legacy Line Event callback */
HAL_LTDC_LineEventCallback(hltdc);
8004130: 6878 ldr r0, [r7, #4]
8004132: f000 f82f bl 8004194 <HAL_LTDC_LineEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
/* Register reload Interrupt management ***************************************/
if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U))
8004136: 68fb ldr r3, [r7, #12]
8004138: f003 0308 and.w r3, r3, #8
800413c: 2b00 cmp r3, #0
800413e: d01b beq.n 8004178 <HAL_LTDC_IRQHandler+0x140>
8004140: 68bb ldr r3, [r7, #8]
8004142: f003 0308 and.w r3, r3, #8
8004146: 2b00 cmp r3, #0
8004148: d016 beq.n 8004178 <HAL_LTDC_IRQHandler+0x140>
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
800414a: 687b ldr r3, [r7, #4]
800414c: 681b ldr r3, [r3, #0]
800414e: 6b5a ldr r2, [r3, #52] @ 0x34
8004150: 687b ldr r3, [r7, #4]
8004152: 681b ldr r3, [r3, #0]
8004154: f022 0208 bic.w r2, r2, #8
8004158: 635a str r2, [r3, #52] @ 0x34
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
800415a: 687b ldr r3, [r7, #4]
800415c: 681b ldr r3, [r3, #0]
800415e: 2208 movs r2, #8
8004160: 63da str r2, [r3, #60] @ 0x3c
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
8004162: 687b ldr r3, [r7, #4]
8004164: 2201 movs r2, #1
8004166: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
800416a: 687b ldr r3, [r7, #4]
800416c: 2200 movs r2, #0
800416e: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/*Call registered reload Event callback */
hltdc->ReloadEventCallback(hltdc);
#else
/*Call Legacy Reload Event callback */
HAL_LTDC_ReloadEventCallback(hltdc);
8004172: 6878 ldr r0, [r7, #4]
8004174: f000 f818 bl 80041a8 <HAL_LTDC_ReloadEventCallback>
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
}
}
8004178: bf00 nop
800417a: 3710 adds r7, #16
800417c: 46bd mov sp, r7
800417e: bd80 pop {r7, pc}
08004180 <HAL_LTDC_ErrorCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc)
{
8004180: b480 push {r7}
8004182: b083 sub sp, #12
8004184: af00 add r7, sp, #0
8004186: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ErrorCallback could be implemented in the user file
*/
}
8004188: bf00 nop
800418a: 370c adds r7, #12
800418c: 46bd mov sp, r7
800418e: f85d 7b04 ldr.w r7, [sp], #4
8004192: 4770 bx lr
08004194 <HAL_LTDC_LineEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
8004194: b480 push {r7}
8004196: b083 sub sp, #12
8004198: af00 add r7, sp, #0
800419a: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
800419c: bf00 nop
800419e: 370c adds r7, #12
80041a0: 46bd mov sp, r7
80041a2: f85d 7b04 ldr.w r7, [sp], #4
80041a6: 4770 bx lr
080041a8 <HAL_LTDC_ReloadEventCallback>:
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
80041a8: b480 push {r7}
80041aa: b083 sub sp, #12
80041ac: af00 add r7, sp, #0
80041ae: 6078 str r0, [r7, #4]
UNUSED(hltdc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
80041b0: bf00 nop
80041b2: 370c adds r7, #12
80041b4: 46bd mov sp, r7
80041b6: f85d 7b04 ldr.w r7, [sp], #4
80041ba: 4770 bx lr
080041bc <HAL_LTDC_ConfigLayer>:
* This parameter can be one of the following values:
* LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
80041bc: b5b0 push {r4, r5, r7, lr}
80041be: b084 sub sp, #16
80041c0: af00 add r7, sp, #0
80041c2: 60f8 str r0, [r7, #12]
80041c4: 60b9 str r1, [r7, #8]
80041c6: 607a str r2, [r7, #4]
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Process locked */
__HAL_LOCK(hltdc);
80041c8: 68fb ldr r3, [r7, #12]
80041ca: f893 30a0 ldrb.w r3, [r3, #160] @ 0xa0
80041ce: 2b01 cmp r3, #1
80041d0: d101 bne.n 80041d6 <HAL_LTDC_ConfigLayer+0x1a>
80041d2: 2302 movs r3, #2
80041d4: e02c b.n 8004230 <HAL_LTDC_ConfigLayer+0x74>
80041d6: 68fb ldr r3, [r7, #12]
80041d8: 2201 movs r2, #1
80041da: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
80041de: 68fb ldr r3, [r7, #12]
80041e0: 2202 movs r2, #2
80041e2: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
80041e6: 68fa ldr r2, [r7, #12]
80041e8: 687b ldr r3, [r7, #4]
80041ea: 2134 movs r1, #52 @ 0x34
80041ec: fb01 f303 mul.w r3, r1, r3
80041f0: 4413 add r3, r2
80041f2: f103 0238 add.w r2, r3, #56 @ 0x38
80041f6: 68bb ldr r3, [r7, #8]
80041f8: 4614 mov r4, r2
80041fa: 461d mov r5, r3
80041fc: cd0f ldmia r5!, {r0, r1, r2, r3}
80041fe: c40f stmia r4!, {r0, r1, r2, r3}
8004200: cd0f ldmia r5!, {r0, r1, r2, r3}
8004202: c40f stmia r4!, {r0, r1, r2, r3}
8004204: cd0f ldmia r5!, {r0, r1, r2, r3}
8004206: c40f stmia r4!, {r0, r1, r2, r3}
8004208: 682b ldr r3, [r5, #0]
800420a: 6023 str r3, [r4, #0]
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
800420c: 687a ldr r2, [r7, #4]
800420e: 68b9 ldr r1, [r7, #8]
8004210: 68f8 ldr r0, [r7, #12]
8004212: f000 f811 bl 8004238 <LTDC_SetConfig>
/* Set the Immediate Reload type */
hltdc->Instance->SRCR = LTDC_SRCR_IMR;
8004216: 68fb ldr r3, [r7, #12]
8004218: 681b ldr r3, [r3, #0]
800421a: 2201 movs r2, #1
800421c: 625a str r2, [r3, #36] @ 0x24
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
800421e: 68fb ldr r3, [r7, #12]
8004220: 2201 movs r2, #1
8004222: f883 20a1 strb.w r2, [r3, #161] @ 0xa1
/* Process unlocked */
__HAL_UNLOCK(hltdc);
8004226: 68fb ldr r3, [r7, #12]
8004228: 2200 movs r2, #0
800422a: f883 20a0 strb.w r2, [r3, #160] @ 0xa0
return HAL_OK;
800422e: 2300 movs r3, #0
}
8004230: 4618 mov r0, r3
8004232: 3710 adds r7, #16
8004234: 46bd mov sp, r7
8004236: bdb0 pop {r4, r5, r7, pc}
08004238 <LTDC_SetConfig>:
* @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
* @retval None
*/
static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
8004238: b480 push {r7}
800423a: b089 sub sp, #36 @ 0x24
800423c: af00 add r7, sp, #0
800423e: 60f8 str r0, [r7, #12]
8004240: 60b9 str r1, [r7, #8]
8004242: 607a str r2, [r7, #4]
uint32_t tmp;
uint32_t tmp1;
uint32_t tmp2;
/* Configure the horizontal start and stop position */
tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
8004244: 68bb ldr r3, [r7, #8]
8004246: 685a ldr r2, [r3, #4]
8004248: 68fb ldr r3, [r7, #12]
800424a: 681b ldr r3, [r3, #0]
800424c: 68db ldr r3, [r3, #12]
800424e: 0c1b lsrs r3, r3, #16
8004250: f3c3 030b ubfx r3, r3, #0, #12
8004254: 4413 add r3, r2
8004256: 041b lsls r3, r3, #16
8004258: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
800425a: 68fb ldr r3, [r7, #12]
800425c: 681b ldr r3, [r3, #0]
800425e: 461a mov r2, r3
8004260: 687b ldr r3, [r7, #4]
8004262: 01db lsls r3, r3, #7
8004264: 4413 add r3, r2
8004266: 3384 adds r3, #132 @ 0x84
8004268: 685b ldr r3, [r3, #4]
800426a: 68fa ldr r2, [r7, #12]
800426c: 6812 ldr r2, [r2, #0]
800426e: 4611 mov r1, r2
8004270: 687a ldr r2, [r7, #4]
8004272: 01d2 lsls r2, r2, #7
8004274: 440a add r2, r1
8004276: 3284 adds r2, #132 @ 0x84
8004278: f403 4370 and.w r3, r3, #61440 @ 0xf000
800427c: 6053 str r3, [r2, #4]
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
800427e: 68bb ldr r3, [r7, #8]
8004280: 681a ldr r2, [r3, #0]
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
8004282: 68fb ldr r3, [r7, #12]
8004284: 681b ldr r3, [r3, #0]
8004286: 68db ldr r3, [r3, #12]
8004288: 0c1b lsrs r3, r3, #16
800428a: f3c3 030b ubfx r3, r3, #0, #12
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
800428e: 4413 add r3, r2
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
8004290: 1c5a adds r2, r3, #1
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
8004292: 68fb ldr r3, [r7, #12]
8004294: 681b ldr r3, [r3, #0]
8004296: 4619 mov r1, r3
8004298: 687b ldr r3, [r7, #4]
800429a: 01db lsls r3, r3, #7
800429c: 440b add r3, r1
800429e: 3384 adds r3, #132 @ 0x84
80042a0: 4619 mov r1, r3
((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
80042a2: 69fb ldr r3, [r7, #28]
80042a4: 4313 orrs r3, r2
LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
80042a6: 604b str r3, [r1, #4]
/* Configure the vertical start and stop position */
tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
80042a8: 68bb ldr r3, [r7, #8]
80042aa: 68da ldr r2, [r3, #12]
80042ac: 68fb ldr r3, [r7, #12]
80042ae: 681b ldr r3, [r3, #0]
80042b0: 68db ldr r3, [r3, #12]
80042b2: f3c3 030a ubfx r3, r3, #0, #11
80042b6: 4413 add r3, r2
80042b8: 041b lsls r3, r3, #16
80042ba: 61fb str r3, [r7, #28]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS);
80042bc: 68fb ldr r3, [r7, #12]
80042be: 681b ldr r3, [r3, #0]
80042c0: 461a mov r2, r3
80042c2: 687b ldr r3, [r7, #4]
80042c4: 01db lsls r3, r3, #7
80042c6: 4413 add r3, r2
80042c8: 3384 adds r3, #132 @ 0x84
80042ca: 689b ldr r3, [r3, #8]
80042cc: 68fa ldr r2, [r7, #12]
80042ce: 6812 ldr r2, [r2, #0]
80042d0: 4611 mov r1, r2
80042d2: 687a ldr r2, [r7, #4]
80042d4: 01d2 lsls r2, r2, #7
80042d6: 440a add r2, r1
80042d8: 3284 adds r2, #132 @ 0x84
80042da: f403 4370 and.w r3, r3, #61440 @ 0xf000
80042de: 6093 str r3, [r2, #8]
LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp);
80042e0: 68bb ldr r3, [r7, #8]
80042e2: 689a ldr r2, [r3, #8]
80042e4: 68fb ldr r3, [r7, #12]
80042e6: 681b ldr r3, [r3, #0]
80042e8: 68db ldr r3, [r3, #12]
80042ea: f3c3 030a ubfx r3, r3, #0, #11
80042ee: 4413 add r3, r2
80042f0: 1c5a adds r2, r3, #1
80042f2: 68fb ldr r3, [r7, #12]
80042f4: 681b ldr r3, [r3, #0]
80042f6: 4619 mov r1, r3
80042f8: 687b ldr r3, [r7, #4]
80042fa: 01db lsls r3, r3, #7
80042fc: 440b add r3, r1
80042fe: 3384 adds r3, #132 @ 0x84
8004300: 4619 mov r1, r3
8004302: 69fb ldr r3, [r7, #28]
8004304: 4313 orrs r3, r2
8004306: 608b str r3, [r1, #8]
/* Specifies the pixel format */
LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF);
8004308: 68fb ldr r3, [r7, #12]
800430a: 681b ldr r3, [r3, #0]
800430c: 461a mov r2, r3
800430e: 687b ldr r3, [r7, #4]
8004310: 01db lsls r3, r3, #7
8004312: 4413 add r3, r2
8004314: 3384 adds r3, #132 @ 0x84
8004316: 691b ldr r3, [r3, #16]
8004318: 68fa ldr r2, [r7, #12]
800431a: 6812 ldr r2, [r2, #0]
800431c: 4611 mov r1, r2
800431e: 687a ldr r2, [r7, #4]
8004320: 01d2 lsls r2, r2, #7
8004322: 440a add r2, r1
8004324: 3284 adds r2, #132 @ 0x84
8004326: f023 0307 bic.w r3, r3, #7
800432a: 6113 str r3, [r2, #16]
LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat);
800432c: 68fb ldr r3, [r7, #12]
800432e: 681b ldr r3, [r3, #0]
8004330: 461a mov r2, r3
8004332: 687b ldr r3, [r7, #4]
8004334: 01db lsls r3, r3, #7
8004336: 4413 add r3, r2
8004338: 3384 adds r3, #132 @ 0x84
800433a: 461a mov r2, r3
800433c: 68bb ldr r3, [r7, #8]
800433e: 691b ldr r3, [r3, #16]
8004340: 6113 str r3, [r2, #16]
/* Configure the default color values */
tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
8004342: 68bb ldr r3, [r7, #8]
8004344: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
8004348: 021b lsls r3, r3, #8
800434a: 61fb str r3, [r7, #28]
tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
800434c: 68bb ldr r3, [r7, #8]
800434e: f893 3032 ldrb.w r3, [r3, #50] @ 0x32
8004352: 041b lsls r3, r3, #16
8004354: 61bb str r3, [r7, #24]
tmp2 = (pLayerCfg->Alpha0 << 24U);
8004356: 68bb ldr r3, [r7, #8]
8004358: 699b ldr r3, [r3, #24]
800435a: 061b lsls r3, r3, #24
800435c: 617b str r3, [r7, #20]
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->DCCR, (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2));
800435e: 68bb ldr r3, [r7, #8]
8004360: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
8004364: 461a mov r2, r3
8004366: 69fb ldr r3, [r7, #28]
8004368: 431a orrs r2, r3
800436a: 69bb ldr r3, [r7, #24]
800436c: 431a orrs r2, r3
800436e: 68fb ldr r3, [r7, #12]
8004370: 681b ldr r3, [r3, #0]
8004372: 4619 mov r1, r3
8004374: 687b ldr r3, [r7, #4]
8004376: 01db lsls r3, r3, #7
8004378: 440b add r3, r1
800437a: 3384 adds r3, #132 @ 0x84
800437c: 4619 mov r1, r3
800437e: 697b ldr r3, [r7, #20]
8004380: 4313 orrs r3, r2
8004382: 618b str r3, [r1, #24]
/* Specifies the constant alpha value */
LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA);
8004384: 68fb ldr r3, [r7, #12]
8004386: 681b ldr r3, [r3, #0]
8004388: 461a mov r2, r3
800438a: 687b ldr r3, [r7, #4]
800438c: 01db lsls r3, r3, #7
800438e: 4413 add r3, r2
8004390: 3384 adds r3, #132 @ 0x84
8004392: 695b ldr r3, [r3, #20]
8004394: 68fa ldr r2, [r7, #12]
8004396: 6812 ldr r2, [r2, #0]
8004398: 4611 mov r1, r2
800439a: 687a ldr r2, [r7, #4]
800439c: 01d2 lsls r2, r2, #7
800439e: 440a add r2, r1
80043a0: 3284 adds r2, #132 @ 0x84
80043a2: f023 03ff bic.w r3, r3, #255 @ 0xff
80043a6: 6153 str r3, [r2, #20]
LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha);
80043a8: 68fb ldr r3, [r7, #12]
80043aa: 681b ldr r3, [r3, #0]
80043ac: 461a mov r2, r3
80043ae: 687b ldr r3, [r7, #4]
80043b0: 01db lsls r3, r3, #7
80043b2: 4413 add r3, r2
80043b4: 3384 adds r3, #132 @ 0x84
80043b6: 461a mov r2, r3
80043b8: 68bb ldr r3, [r7, #8]
80043ba: 695b ldr r3, [r3, #20]
80043bc: 6153 str r3, [r2, #20]
/* Specifies the blending factors */
LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1);
80043be: 68fb ldr r3, [r7, #12]
80043c0: 681b ldr r3, [r3, #0]
80043c2: 461a mov r2, r3
80043c4: 687b ldr r3, [r7, #4]
80043c6: 01db lsls r3, r3, #7
80043c8: 4413 add r3, r2
80043ca: 3384 adds r3, #132 @ 0x84
80043cc: 69db ldr r3, [r3, #28]
80043ce: 68fa ldr r2, [r7, #12]
80043d0: 6812 ldr r2, [r2, #0]
80043d2: 4611 mov r1, r2
80043d4: 687a ldr r2, [r7, #4]
80043d6: 01d2 lsls r2, r2, #7
80043d8: 440a add r2, r1
80043da: 3284 adds r2, #132 @ 0x84
80043dc: f423 63e0 bic.w r3, r3, #1792 @ 0x700
80043e0: f023 0307 bic.w r3, r3, #7
80043e4: 61d3 str r3, [r2, #28]
LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2);
80043e6: 68bb ldr r3, [r7, #8]
80043e8: 69da ldr r2, [r3, #28]
80043ea: 68bb ldr r3, [r7, #8]
80043ec: 6a1b ldr r3, [r3, #32]
80043ee: 68f9 ldr r1, [r7, #12]
80043f0: 6809 ldr r1, [r1, #0]
80043f2: 4608 mov r0, r1
80043f4: 6879 ldr r1, [r7, #4]
80043f6: 01c9 lsls r1, r1, #7
80043f8: 4401 add r1, r0
80043fa: 3184 adds r1, #132 @ 0x84
80043fc: 4313 orrs r3, r2
80043fe: 61cb str r3, [r1, #28]
/* Configure the color frame buffer start address */
WRITE_REG(LTDC_LAYER(hltdc, LayerIdx)->CFBAR, pLayerCfg->FBStartAdress);
8004400: 68fb ldr r3, [r7, #12]
8004402: 681b ldr r3, [r3, #0]
8004404: 461a mov r2, r3
8004406: 687b ldr r3, [r7, #4]
8004408: 01db lsls r3, r3, #7
800440a: 4413 add r3, r2
800440c: 3384 adds r3, #132 @ 0x84
800440e: 461a mov r2, r3
8004410: 68bb ldr r3, [r7, #8]
8004412: 6a5b ldr r3, [r3, #36] @ 0x24
8004414: 6293 str r3, [r2, #40] @ 0x28
if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
8004416: 68bb ldr r3, [r7, #8]
8004418: 691b ldr r3, [r3, #16]
800441a: 2b00 cmp r3, #0
800441c: d102 bne.n 8004424 <LTDC_SetConfig+0x1ec>
{
tmp = 4U;
800441e: 2304 movs r3, #4
8004420: 61fb str r3, [r7, #28]
8004422: e01b b.n 800445c <LTDC_SetConfig+0x224>
}
else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888)
8004424: 68bb ldr r3, [r7, #8]
8004426: 691b ldr r3, [r3, #16]
8004428: 2b01 cmp r3, #1
800442a: d102 bne.n 8004432 <LTDC_SetConfig+0x1fa>
{
tmp = 3U;
800442c: 2303 movs r3, #3
800442e: 61fb str r3, [r7, #28]
8004430: e014 b.n 800445c <LTDC_SetConfig+0x224>
}
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
8004432: 68bb ldr r3, [r7, #8]
8004434: 691b ldr r3, [r3, #16]
8004436: 2b04 cmp r3, #4
8004438: d00b beq.n 8004452 <LTDC_SetConfig+0x21a>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
800443a: 68bb ldr r3, [r7, #8]
800443c: 691b ldr r3, [r3, #16]
else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
800443e: 2b02 cmp r3, #2
8004440: d007 beq.n 8004452 <LTDC_SetConfig+0x21a>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
8004442: 68bb ldr r3, [r7, #8]
8004444: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
8004446: 2b03 cmp r3, #3
8004448: d003 beq.n 8004452 <LTDC_SetConfig+0x21a>
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88))
800444a: 68bb ldr r3, [r7, #8]
800444c: 691b ldr r3, [r3, #16]
(pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
800444e: 2b07 cmp r3, #7
8004450: d102 bne.n 8004458 <LTDC_SetConfig+0x220>
{
tmp = 2U;
8004452: 2302 movs r3, #2
8004454: 61fb str r3, [r7, #28]
8004456: e001 b.n 800445c <LTDC_SetConfig+0x224>
}
else
{
tmp = 1U;
8004458: 2301 movs r3, #1
800445a: 61fb str r3, [r7, #28]
}
/* Configure the color frame buffer pitch in byte */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
800445c: 68fb ldr r3, [r7, #12]
800445e: 681b ldr r3, [r3, #0]
8004460: 461a mov r2, r3
8004462: 687b ldr r3, [r7, #4]
8004464: 01db lsls r3, r3, #7
8004466: 4413 add r3, r2
8004468: 3384 adds r3, #132 @ 0x84
800446a: 6adb ldr r3, [r3, #44] @ 0x2c
800446c: 68fa ldr r2, [r7, #12]
800446e: 6812 ldr r2, [r2, #0]
8004470: 4611 mov r1, r2
8004472: 687a ldr r2, [r7, #4]
8004474: 01d2 lsls r2, r2, #7
8004476: 440a add r2, r1
8004478: 3284 adds r2, #132 @ 0x84
800447a: f003 23e0 and.w r3, r3, #3758153728 @ 0xe000e000
800447e: 62d3 str r3, [r2, #44] @ 0x2c
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
8004480: 68bb ldr r3, [r7, #8]
8004482: 6a9b ldr r3, [r3, #40] @ 0x28
8004484: 69fa ldr r2, [r7, #28]
8004486: fb02 f303 mul.w r3, r2, r3
800448a: 041a lsls r2, r3, #16
(((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U));
800448c: 68bb ldr r3, [r7, #8]
800448e: 6859 ldr r1, [r3, #4]
8004490: 68bb ldr r3, [r7, #8]
8004492: 681b ldr r3, [r3, #0]
8004494: 1acb subs r3, r1, r3
8004496: 69f9 ldr r1, [r7, #28]
8004498: fb01 f303 mul.w r3, r1, r3
800449c: 3303 adds r3, #3
LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \
800449e: 68f9 ldr r1, [r7, #12]
80044a0: 6809 ldr r1, [r1, #0]
80044a2: 4608 mov r0, r1
80044a4: 6879 ldr r1, [r7, #4]
80044a6: 01c9 lsls r1, r1, #7
80044a8: 4401 add r1, r0
80044aa: 3184 adds r1, #132 @ 0x84
80044ac: 4313 orrs r3, r2
80044ae: 62cb str r3, [r1, #44] @ 0x2c
/* Configure the frame buffer line number */
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR);
80044b0: 68fb ldr r3, [r7, #12]
80044b2: 681b ldr r3, [r3, #0]
80044b4: 461a mov r2, r3
80044b6: 687b ldr r3, [r7, #4]
80044b8: 01db lsls r3, r3, #7
80044ba: 4413 add r3, r2
80044bc: 3384 adds r3, #132 @ 0x84
80044be: 6b1b ldr r3, [r3, #48] @ 0x30
80044c0: 68fa ldr r2, [r7, #12]
80044c2: 6812 ldr r2, [r2, #0]
80044c4: 4611 mov r1, r2
80044c6: 687a ldr r2, [r7, #4]
80044c8: 01d2 lsls r2, r2, #7
80044ca: 440a add r2, r1
80044cc: 3284 adds r2, #132 @ 0x84
80044ce: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
80044d2: f023 0307 bic.w r3, r3, #7
80044d6: 6313 str r3, [r2, #48] @ 0x30
LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight);
80044d8: 68fb ldr r3, [r7, #12]
80044da: 681b ldr r3, [r3, #0]
80044dc: 461a mov r2, r3
80044de: 687b ldr r3, [r7, #4]
80044e0: 01db lsls r3, r3, #7
80044e2: 4413 add r3, r2
80044e4: 3384 adds r3, #132 @ 0x84
80044e6: 461a mov r2, r3
80044e8: 68bb ldr r3, [r7, #8]
80044ea: 6adb ldr r3, [r3, #44] @ 0x2c
80044ec: 6313 str r3, [r2, #48] @ 0x30
/* Enable LTDC_Layer by setting LEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN;
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 681b ldr r3, [r3, #0]
80044f2: 461a mov r2, r3
80044f4: 687b ldr r3, [r7, #4]
80044f6: 01db lsls r3, r3, #7
80044f8: 4413 add r3, r2
80044fa: 3384 adds r3, #132 @ 0x84
80044fc: 681b ldr r3, [r3, #0]
80044fe: 68fa ldr r2, [r7, #12]
8004500: 6812 ldr r2, [r2, #0]
8004502: 4611 mov r1, r2
8004504: 687a ldr r2, [r7, #4]
8004506: 01d2 lsls r2, r2, #7
8004508: 440a add r2, r1
800450a: 3284 adds r2, #132 @ 0x84
800450c: f043 0301 orr.w r3, r3, #1
8004510: 6013 str r3, [r2, #0]
}
8004512: bf00 nop
8004514: 3724 adds r7, #36 @ 0x24
8004516: 46bd mov sp, r7
8004518: f85d 7b04 ldr.w r7, [sp], #4
800451c: 4770 bx lr
...
08004520 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8004520: b580 push {r7, lr}
8004522: b086 sub sp, #24
8004524: af00 add r7, sp, #0
8004526: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t pll_config;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8004528: 687b ldr r3, [r7, #4]
800452a: 2b00 cmp r3, #0
800452c: d101 bne.n 8004532 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800452e: 2301 movs r3, #1
8004530: e267 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8004532: 687b ldr r3, [r7, #4]
8004534: 681b ldr r3, [r3, #0]
8004536: f003 0301 and.w r3, r3, #1
800453a: 2b00 cmp r3, #0
800453c: d075 beq.n 800462a <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
800453e: 4b88 ldr r3, [pc, #544] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004540: 689b ldr r3, [r3, #8]
8004542: f003 030c and.w r3, r3, #12
8004546: 2b04 cmp r3, #4
8004548: d00c beq.n 8004564 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
800454a: 4b85 ldr r3, [pc, #532] @ (8004760 <HAL_RCC_OscConfig+0x240>)
800454c: 689b ldr r3, [r3, #8]
800454e: f003 030c and.w r3, r3, #12
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || \
8004552: 2b08 cmp r3, #8
8004554: d112 bne.n 800457c <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8004556: 4b82 ldr r3, [pc, #520] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004558: 685b ldr r3, [r3, #4]
800455a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
800455e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8004562: d10b bne.n 800457c <HAL_RCC_OscConfig+0x5c>
{
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004564: 4b7e ldr r3, [pc, #504] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004566: 681b ldr r3, [r3, #0]
8004568: f403 3300 and.w r3, r3, #131072 @ 0x20000
800456c: 2b00 cmp r3, #0
800456e: d05b beq.n 8004628 <HAL_RCC_OscConfig+0x108>
8004570: 687b ldr r3, [r7, #4]
8004572: 685b ldr r3, [r3, #4]
8004574: 2b00 cmp r3, #0
8004576: d157 bne.n 8004628 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8004578: 2301 movs r3, #1
800457a: e242 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800457c: 687b ldr r3, [r7, #4]
800457e: 685b ldr r3, [r3, #4]
8004580: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004584: d106 bne.n 8004594 <HAL_RCC_OscConfig+0x74>
8004586: 4b76 ldr r3, [pc, #472] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004588: 681b ldr r3, [r3, #0]
800458a: 4a75 ldr r2, [pc, #468] @ (8004760 <HAL_RCC_OscConfig+0x240>)
800458c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8004590: 6013 str r3, [r2, #0]
8004592: e01d b.n 80045d0 <HAL_RCC_OscConfig+0xb0>
8004594: 687b ldr r3, [r7, #4]
8004596: 685b ldr r3, [r3, #4]
8004598: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800459c: d10c bne.n 80045b8 <HAL_RCC_OscConfig+0x98>
800459e: 4b70 ldr r3, [pc, #448] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045a0: 681b ldr r3, [r3, #0]
80045a2: 4a6f ldr r2, [pc, #444] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045a4: f443 2380 orr.w r3, r3, #262144 @ 0x40000
80045a8: 6013 str r3, [r2, #0]
80045aa: 4b6d ldr r3, [pc, #436] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045ac: 681b ldr r3, [r3, #0]
80045ae: 4a6c ldr r2, [pc, #432] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045b0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80045b4: 6013 str r3, [r2, #0]
80045b6: e00b b.n 80045d0 <HAL_RCC_OscConfig+0xb0>
80045b8: 4b69 ldr r3, [pc, #420] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045ba: 681b ldr r3, [r3, #0]
80045bc: 4a68 ldr r2, [pc, #416] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045be: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80045c2: 6013 str r3, [r2, #0]
80045c4: 4b66 ldr r3, [pc, #408] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045c6: 681b ldr r3, [r3, #0]
80045c8: 4a65 ldr r2, [pc, #404] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045ca: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80045ce: 6013 str r3, [r2, #0]
/* Check the HSE State */
if ((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
80045d0: 687b ldr r3, [r7, #4]
80045d2: 685b ldr r3, [r3, #4]
80045d4: 2b00 cmp r3, #0
80045d6: d013 beq.n 8004600 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80045d8: f7fd f832 bl 8001640 <HAL_GetTick>
80045dc: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80045de: e008 b.n 80045f2 <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80045e0: f7fd f82e bl 8001640 <HAL_GetTick>
80045e4: 4602 mov r2, r0
80045e6: 693b ldr r3, [r7, #16]
80045e8: 1ad3 subs r3, r2, r3
80045ea: 2b64 cmp r3, #100 @ 0x64
80045ec: d901 bls.n 80045f2 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
80045ee: 2303 movs r3, #3
80045f0: e207 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
80045f2: 4b5b ldr r3, [pc, #364] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80045f4: 681b ldr r3, [r3, #0]
80045f6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80045fa: 2b00 cmp r3, #0
80045fc: d0f0 beq.n 80045e0 <HAL_RCC_OscConfig+0xc0>
80045fe: e014 b.n 800462a <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004600: f7fd f81e bl 8001640 <HAL_GetTick>
8004604: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8004606: e008 b.n 800461a <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8004608: f7fd f81a bl 8001640 <HAL_GetTick>
800460c: 4602 mov r2, r0
800460e: 693b ldr r3, [r7, #16]
8004610: 1ad3 subs r3, r2, r3
8004612: 2b64 cmp r3, #100 @ 0x64
8004614: d901 bls.n 800461a <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8004616: 2303 movs r3, #3
8004618: e1f3 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800461a: 4b51 ldr r3, [pc, #324] @ (8004760 <HAL_RCC_OscConfig+0x240>)
800461c: 681b ldr r3, [r3, #0]
800461e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004622: 2b00 cmp r3, #0
8004624: d1f0 bne.n 8004608 <HAL_RCC_OscConfig+0xe8>
8004626: e000 b.n 800462a <HAL_RCC_OscConfig+0x10a>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8004628: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800462a: 687b ldr r3, [r7, #4]
800462c: 681b ldr r3, [r3, #0]
800462e: f003 0302 and.w r3, r3, #2
8004632: 2b00 cmp r3, #0
8004634: d063 beq.n 80046fe <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
8004636: 4b4a ldr r3, [pc, #296] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004638: 689b ldr r3, [r3, #8]
800463a: f003 030c and.w r3, r3, #12
800463e: 2b00 cmp r3, #0
8004640: d00b beq.n 800465a <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8004642: 4b47 ldr r3, [pc, #284] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004644: 689b ldr r3, [r3, #8]
8004646: f003 030c and.w r3, r3, #12
if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || \
800464a: 2b08 cmp r3, #8
800464c: d11c bne.n 8004688 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800464e: 4b44 ldr r3, [pc, #272] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004650: 685b ldr r3, [r3, #4]
8004652: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8004656: 2b00 cmp r3, #0
8004658: d116 bne.n 8004688 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800465a: 4b41 ldr r3, [pc, #260] @ (8004760 <HAL_RCC_OscConfig+0x240>)
800465c: 681b ldr r3, [r3, #0]
800465e: f003 0302 and.w r3, r3, #2
8004662: 2b00 cmp r3, #0
8004664: d005 beq.n 8004672 <HAL_RCC_OscConfig+0x152>
8004666: 687b ldr r3, [r7, #4]
8004668: 68db ldr r3, [r3, #12]
800466a: 2b01 cmp r3, #1
800466c: d001 beq.n 8004672 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
800466e: 2301 movs r3, #1
8004670: e1c7 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8004672: 4b3b ldr r3, [pc, #236] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004674: 681b ldr r3, [r3, #0]
8004676: f023 02f8 bic.w r2, r3, #248 @ 0xf8
800467a: 687b ldr r3, [r7, #4]
800467c: 691b ldr r3, [r3, #16]
800467e: 00db lsls r3, r3, #3
8004680: 4937 ldr r1, [pc, #220] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004682: 4313 orrs r3, r2
8004684: 600b str r3, [r1, #0]
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8004686: e03a b.n 80046fe <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
8004688: 687b ldr r3, [r7, #4]
800468a: 68db ldr r3, [r3, #12]
800468c: 2b00 cmp r3, #0
800468e: d020 beq.n 80046d2 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8004690: 4b34 ldr r3, [pc, #208] @ (8004764 <HAL_RCC_OscConfig+0x244>)
8004692: 2201 movs r2, #1
8004694: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004696: f7fc ffd3 bl 8001640 <HAL_GetTick>
800469a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800469c: e008 b.n 80046b0 <HAL_RCC_OscConfig+0x190>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
800469e: f7fc ffcf bl 8001640 <HAL_GetTick>
80046a2: 4602 mov r2, r0
80046a4: 693b ldr r3, [r7, #16]
80046a6: 1ad3 subs r3, r2, r3
80046a8: 2b02 cmp r3, #2
80046aa: d901 bls.n 80046b0 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
80046ac: 2303 movs r3, #3
80046ae: e1a8 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80046b0: 4b2b ldr r3, [pc, #172] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80046b2: 681b ldr r3, [r3, #0]
80046b4: f003 0302 and.w r3, r3, #2
80046b8: 2b00 cmp r3, #0
80046ba: d0f0 beq.n 800469e <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80046bc: 4b28 ldr r3, [pc, #160] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80046be: 681b ldr r3, [r3, #0]
80046c0: f023 02f8 bic.w r2, r3, #248 @ 0xf8
80046c4: 687b ldr r3, [r7, #4]
80046c6: 691b ldr r3, [r3, #16]
80046c8: 00db lsls r3, r3, #3
80046ca: 4925 ldr r1, [pc, #148] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80046cc: 4313 orrs r3, r2
80046ce: 600b str r3, [r1, #0]
80046d0: e015 b.n 80046fe <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80046d2: 4b24 ldr r3, [pc, #144] @ (8004764 <HAL_RCC_OscConfig+0x244>)
80046d4: 2200 movs r2, #0
80046d6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80046d8: f7fc ffb2 bl 8001640 <HAL_GetTick>
80046dc: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80046de: e008 b.n 80046f2 <HAL_RCC_OscConfig+0x1d2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80046e0: f7fc ffae bl 8001640 <HAL_GetTick>
80046e4: 4602 mov r2, r0
80046e6: 693b ldr r3, [r7, #16]
80046e8: 1ad3 subs r3, r2, r3
80046ea: 2b02 cmp r3, #2
80046ec: d901 bls.n 80046f2 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
80046ee: 2303 movs r3, #3
80046f0: e187 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80046f2: 4b1b ldr r3, [pc, #108] @ (8004760 <HAL_RCC_OscConfig+0x240>)
80046f4: 681b ldr r3, [r3, #0]
80046f6: f003 0302 and.w r3, r3, #2
80046fa: 2b00 cmp r3, #0
80046fc: d1f0 bne.n 80046e0 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80046fe: 687b ldr r3, [r7, #4]
8004700: 681b ldr r3, [r3, #0]
8004702: f003 0308 and.w r3, r3, #8
8004706: 2b00 cmp r3, #0
8004708: d036 beq.n 8004778 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
800470a: 687b ldr r3, [r7, #4]
800470c: 695b ldr r3, [r3, #20]
800470e: 2b00 cmp r3, #0
8004710: d016 beq.n 8004740 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8004712: 4b15 ldr r3, [pc, #84] @ (8004768 <HAL_RCC_OscConfig+0x248>)
8004714: 2201 movs r2, #1
8004716: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004718: f7fc ff92 bl 8001640 <HAL_GetTick>
800471c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800471e: e008 b.n 8004732 <HAL_RCC_OscConfig+0x212>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8004720: f7fc ff8e bl 8001640 <HAL_GetTick>
8004724: 4602 mov r2, r0
8004726: 693b ldr r3, [r7, #16]
8004728: 1ad3 subs r3, r2, r3
800472a: 2b02 cmp r3, #2
800472c: d901 bls.n 8004732 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
800472e: 2303 movs r3, #3
8004730: e167 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8004732: 4b0b ldr r3, [pc, #44] @ (8004760 <HAL_RCC_OscConfig+0x240>)
8004734: 6f5b ldr r3, [r3, #116] @ 0x74
8004736: f003 0302 and.w r3, r3, #2
800473a: 2b00 cmp r3, #0
800473c: d0f0 beq.n 8004720 <HAL_RCC_OscConfig+0x200>
800473e: e01b b.n 8004778 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8004740: 4b09 ldr r3, [pc, #36] @ (8004768 <HAL_RCC_OscConfig+0x248>)
8004742: 2200 movs r2, #0
8004744: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004746: f7fc ff7b bl 8001640 <HAL_GetTick>
800474a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800474c: e00e b.n 800476c <HAL_RCC_OscConfig+0x24c>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800474e: f7fc ff77 bl 8001640 <HAL_GetTick>
8004752: 4602 mov r2, r0
8004754: 693b ldr r3, [r7, #16]
8004756: 1ad3 subs r3, r2, r3
8004758: 2b02 cmp r3, #2
800475a: d907 bls.n 800476c <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
800475c: 2303 movs r3, #3
800475e: e150 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
8004760: 40023800 .word 0x40023800
8004764: 42470000 .word 0x42470000
8004768: 42470e80 .word 0x42470e80
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800476c: 4b88 ldr r3, [pc, #544] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800476e: 6f5b ldr r3, [r3, #116] @ 0x74
8004770: f003 0302 and.w r3, r3, #2
8004774: 2b00 cmp r3, #0
8004776: d1ea bne.n 800474e <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8004778: 687b ldr r3, [r7, #4]
800477a: 681b ldr r3, [r3, #0]
800477c: f003 0304 and.w r3, r3, #4
8004780: 2b00 cmp r3, #0
8004782: f000 8097 beq.w 80048b4 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8004786: 2300 movs r3, #0
8004788: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
800478a: 4b81 ldr r3, [pc, #516] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800478c: 6c1b ldr r3, [r3, #64] @ 0x40
800478e: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8004792: 2b00 cmp r3, #0
8004794: d10f bne.n 80047b6 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8004796: 2300 movs r3, #0
8004798: 60bb str r3, [r7, #8]
800479a: 4b7d ldr r3, [pc, #500] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800479c: 6c1b ldr r3, [r3, #64] @ 0x40
800479e: 4a7c ldr r2, [pc, #496] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80047a0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80047a4: 6413 str r3, [r2, #64] @ 0x40
80047a6: 4b7a ldr r3, [pc, #488] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80047a8: 6c1b ldr r3, [r3, #64] @ 0x40
80047aa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80047ae: 60bb str r3, [r7, #8]
80047b0: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80047b2: 2301 movs r3, #1
80047b4: 75fb strb r3, [r7, #23]
}
if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80047b6: 4b77 ldr r3, [pc, #476] @ (8004994 <HAL_RCC_OscConfig+0x474>)
80047b8: 681b ldr r3, [r3, #0]
80047ba: f403 7380 and.w r3, r3, #256 @ 0x100
80047be: 2b00 cmp r3, #0
80047c0: d118 bne.n 80047f4 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80047c2: 4b74 ldr r3, [pc, #464] @ (8004994 <HAL_RCC_OscConfig+0x474>)
80047c4: 681b ldr r3, [r3, #0]
80047c6: 4a73 ldr r2, [pc, #460] @ (8004994 <HAL_RCC_OscConfig+0x474>)
80047c8: f443 7380 orr.w r3, r3, #256 @ 0x100
80047cc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80047ce: f7fc ff37 bl 8001640 <HAL_GetTick>
80047d2: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80047d4: e008 b.n 80047e8 <HAL_RCC_OscConfig+0x2c8>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80047d6: f7fc ff33 bl 8001640 <HAL_GetTick>
80047da: 4602 mov r2, r0
80047dc: 693b ldr r3, [r7, #16]
80047de: 1ad3 subs r3, r2, r3
80047e0: 2b02 cmp r3, #2
80047e2: d901 bls.n 80047e8 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
80047e4: 2303 movs r3, #3
80047e6: e10c b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80047e8: 4b6a ldr r3, [pc, #424] @ (8004994 <HAL_RCC_OscConfig+0x474>)
80047ea: 681b ldr r3, [r3, #0]
80047ec: f403 7380 and.w r3, r3, #256 @ 0x100
80047f0: 2b00 cmp r3, #0
80047f2: d0f0 beq.n 80047d6 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80047f4: 687b ldr r3, [r7, #4]
80047f6: 689b ldr r3, [r3, #8]
80047f8: 2b01 cmp r3, #1
80047fa: d106 bne.n 800480a <HAL_RCC_OscConfig+0x2ea>
80047fc: 4b64 ldr r3, [pc, #400] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80047fe: 6f1b ldr r3, [r3, #112] @ 0x70
8004800: 4a63 ldr r2, [pc, #396] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004802: f043 0301 orr.w r3, r3, #1
8004806: 6713 str r3, [r2, #112] @ 0x70
8004808: e01c b.n 8004844 <HAL_RCC_OscConfig+0x324>
800480a: 687b ldr r3, [r7, #4]
800480c: 689b ldr r3, [r3, #8]
800480e: 2b05 cmp r3, #5
8004810: d10c bne.n 800482c <HAL_RCC_OscConfig+0x30c>
8004812: 4b5f ldr r3, [pc, #380] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004814: 6f1b ldr r3, [r3, #112] @ 0x70
8004816: 4a5e ldr r2, [pc, #376] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004818: f043 0304 orr.w r3, r3, #4
800481c: 6713 str r3, [r2, #112] @ 0x70
800481e: 4b5c ldr r3, [pc, #368] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004820: 6f1b ldr r3, [r3, #112] @ 0x70
8004822: 4a5b ldr r2, [pc, #364] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004824: f043 0301 orr.w r3, r3, #1
8004828: 6713 str r3, [r2, #112] @ 0x70
800482a: e00b b.n 8004844 <HAL_RCC_OscConfig+0x324>
800482c: 4b58 ldr r3, [pc, #352] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800482e: 6f1b ldr r3, [r3, #112] @ 0x70
8004830: 4a57 ldr r2, [pc, #348] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004832: f023 0301 bic.w r3, r3, #1
8004836: 6713 str r3, [r2, #112] @ 0x70
8004838: 4b55 ldr r3, [pc, #340] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800483a: 6f1b ldr r3, [r3, #112] @ 0x70
800483c: 4a54 ldr r2, [pc, #336] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800483e: f023 0304 bic.w r3, r3, #4
8004842: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8004844: 687b ldr r3, [r7, #4]
8004846: 689b ldr r3, [r3, #8]
8004848: 2b00 cmp r3, #0
800484a: d015 beq.n 8004878 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800484c: f7fc fef8 bl 8001640 <HAL_GetTick>
8004850: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004852: e00a b.n 800486a <HAL_RCC_OscConfig+0x34a>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004854: f7fc fef4 bl 8001640 <HAL_GetTick>
8004858: 4602 mov r2, r0
800485a: 693b ldr r3, [r7, #16]
800485c: 1ad3 subs r3, r2, r3
800485e: f241 3288 movw r2, #5000 @ 0x1388
8004862: 4293 cmp r3, r2
8004864: d901 bls.n 800486a <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
8004866: 2303 movs r3, #3
8004868: e0cb b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800486a: 4b49 ldr r3, [pc, #292] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800486c: 6f1b ldr r3, [r3, #112] @ 0x70
800486e: f003 0302 and.w r3, r3, #2
8004872: 2b00 cmp r3, #0
8004874: d0ee beq.n 8004854 <HAL_RCC_OscConfig+0x334>
8004876: e014 b.n 80048a2 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8004878: f7fc fee2 bl 8001640 <HAL_GetTick>
800487c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800487e: e00a b.n 8004896 <HAL_RCC_OscConfig+0x376>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8004880: f7fc fede bl 8001640 <HAL_GetTick>
8004884: 4602 mov r2, r0
8004886: 693b ldr r3, [r7, #16]
8004888: 1ad3 subs r3, r2, r3
800488a: f241 3288 movw r2, #5000 @ 0x1388
800488e: 4293 cmp r3, r2
8004890: d901 bls.n 8004896 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
8004892: 2303 movs r3, #3
8004894: e0b5 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004896: 4b3e ldr r3, [pc, #248] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004898: 6f1b ldr r3, [r3, #112] @ 0x70
800489a: f003 0302 and.w r3, r3, #2
800489e: 2b00 cmp r3, #0
80048a0: d1ee bne.n 8004880 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80048a2: 7dfb ldrb r3, [r7, #23]
80048a4: 2b01 cmp r3, #1
80048a6: d105 bne.n 80048b4 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
80048a8: 4b39 ldr r3, [pc, #228] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80048aa: 6c1b ldr r3, [r3, #64] @ 0x40
80048ac: 4a38 ldr r2, [pc, #224] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80048ae: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80048b2: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80048b4: 687b ldr r3, [r7, #4]
80048b6: 699b ldr r3, [r3, #24]
80048b8: 2b00 cmp r3, #0
80048ba: f000 80a1 beq.w 8004a00 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80048be: 4b34 ldr r3, [pc, #208] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80048c0: 689b ldr r3, [r3, #8]
80048c2: f003 030c and.w r3, r3, #12
80048c6: 2b08 cmp r3, #8
80048c8: d05c beq.n 8004984 <HAL_RCC_OscConfig+0x464>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80048ca: 687b ldr r3, [r7, #4]
80048cc: 699b ldr r3, [r3, #24]
80048ce: 2b02 cmp r3, #2
80048d0: d141 bne.n 8004956 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80048d2: 4b31 ldr r3, [pc, #196] @ (8004998 <HAL_RCC_OscConfig+0x478>)
80048d4: 2200 movs r2, #0
80048d6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80048d8: f7fc feb2 bl 8001640 <HAL_GetTick>
80048dc: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80048de: e008 b.n 80048f2 <HAL_RCC_OscConfig+0x3d2>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80048e0: f7fc feae bl 8001640 <HAL_GetTick>
80048e4: 4602 mov r2, r0
80048e6: 693b ldr r3, [r7, #16]
80048e8: 1ad3 subs r3, r2, r3
80048ea: 2b02 cmp r3, #2
80048ec: d901 bls.n 80048f2 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
80048ee: 2303 movs r3, #3
80048f0: e087 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80048f2: 4b27 ldr r3, [pc, #156] @ (8004990 <HAL_RCC_OscConfig+0x470>)
80048f4: 681b ldr r3, [r3, #0]
80048f6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80048fa: 2b00 cmp r3, #0
80048fc: d1f0 bne.n 80048e0 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
80048fe: 687b ldr r3, [r7, #4]
8004900: 69da ldr r2, [r3, #28]
8004902: 687b ldr r3, [r7, #4]
8004904: 6a1b ldr r3, [r3, #32]
8004906: 431a orrs r2, r3
8004908: 687b ldr r3, [r7, #4]
800490a: 6a5b ldr r3, [r3, #36] @ 0x24
800490c: 019b lsls r3, r3, #6
800490e: 431a orrs r2, r3
8004910: 687b ldr r3, [r7, #4]
8004912: 6a9b ldr r3, [r3, #40] @ 0x28
8004914: 085b lsrs r3, r3, #1
8004916: 3b01 subs r3, #1
8004918: 041b lsls r3, r3, #16
800491a: 431a orrs r2, r3
800491c: 687b ldr r3, [r7, #4]
800491e: 6adb ldr r3, [r3, #44] @ 0x2c
8004920: 061b lsls r3, r3, #24
8004922: 491b ldr r1, [pc, #108] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004924: 4313 orrs r3, r2
8004926: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8004928: 4b1b ldr r3, [pc, #108] @ (8004998 <HAL_RCC_OscConfig+0x478>)
800492a: 2201 movs r2, #1
800492c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800492e: f7fc fe87 bl 8001640 <HAL_GetTick>
8004932: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004934: e008 b.n 8004948 <HAL_RCC_OscConfig+0x428>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004936: f7fc fe83 bl 8001640 <HAL_GetTick>
800493a: 4602 mov r2, r0
800493c: 693b ldr r3, [r7, #16]
800493e: 1ad3 subs r3, r2, r3
8004940: 2b02 cmp r3, #2
8004942: d901 bls.n 8004948 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
8004944: 2303 movs r3, #3
8004946: e05c b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004948: 4b11 ldr r3, [pc, #68] @ (8004990 <HAL_RCC_OscConfig+0x470>)
800494a: 681b ldr r3, [r3, #0]
800494c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004950: 2b00 cmp r3, #0
8004952: d0f0 beq.n 8004936 <HAL_RCC_OscConfig+0x416>
8004954: e054 b.n 8004a00 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8004956: 4b10 ldr r3, [pc, #64] @ (8004998 <HAL_RCC_OscConfig+0x478>)
8004958: 2200 movs r2, #0
800495a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800495c: f7fc fe70 bl 8001640 <HAL_GetTick>
8004960: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004962: e008 b.n 8004976 <HAL_RCC_OscConfig+0x456>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8004964: f7fc fe6c bl 8001640 <HAL_GetTick>
8004968: 4602 mov r2, r0
800496a: 693b ldr r3, [r7, #16]
800496c: 1ad3 subs r3, r2, r3
800496e: 2b02 cmp r3, #2
8004970: d901 bls.n 8004976 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
8004972: 2303 movs r3, #3
8004974: e045 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004976: 4b06 ldr r3, [pc, #24] @ (8004990 <HAL_RCC_OscConfig+0x470>)
8004978: 681b ldr r3, [r3, #0]
800497a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800497e: 2b00 cmp r3, #0
8004980: d1f0 bne.n 8004964 <HAL_RCC_OscConfig+0x444>
8004982: e03d b.n 8004a00 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8004984: 687b ldr r3, [r7, #4]
8004986: 699b ldr r3, [r3, #24]
8004988: 2b01 cmp r3, #1
800498a: d107 bne.n 800499c <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
800498c: 2301 movs r3, #1
800498e: e038 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
8004990: 40023800 .word 0x40023800
8004994: 40007000 .word 0x40007000
8004998: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800499c: 4b1b ldr r3, [pc, #108] @ (8004a0c <HAL_RCC_OscConfig+0x4ec>)
800499e: 685b ldr r3, [r3, #4]
80049a0: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80049a2: 687b ldr r3, [r7, #4]
80049a4: 699b ldr r3, [r3, #24]
80049a6: 2b01 cmp r3, #1
80049a8: d028 beq.n 80049fc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80049aa: 68fb ldr r3, [r7, #12]
80049ac: f403 0280 and.w r2, r3, #4194304 @ 0x400000
80049b0: 687b ldr r3, [r7, #4]
80049b2: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80049b4: 429a cmp r2, r3
80049b6: d121 bne.n 80049fc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80049b8: 68fb ldr r3, [r7, #12]
80049ba: f003 023f and.w r2, r3, #63 @ 0x3f
80049be: 687b ldr r3, [r7, #4]
80049c0: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80049c2: 429a cmp r2, r3
80049c4: d11a bne.n 80049fc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80049c6: 68fa ldr r2, [r7, #12]
80049c8: f647 73c0 movw r3, #32704 @ 0x7fc0
80049cc: 4013 ands r3, r2
80049ce: 687a ldr r2, [r7, #4]
80049d0: 6a52 ldr r2, [r2, #36] @ 0x24
80049d2: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80049d4: 4293 cmp r3, r2
80049d6: d111 bne.n 80049fc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80049d8: 68fb ldr r3, [r7, #12]
80049da: f403 3240 and.w r2, r3, #196608 @ 0x30000
80049de: 687b ldr r3, [r7, #4]
80049e0: 6a9b ldr r3, [r3, #40] @ 0x28
80049e2: 085b lsrs r3, r3, #1
80049e4: 3b01 subs r3, #1
80049e6: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80049e8: 429a cmp r2, r3
80049ea: d107 bne.n 80049fc <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80049ec: 68fb ldr r3, [r7, #12]
80049ee: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
80049f2: 687b ldr r3, [r7, #4]
80049f4: 6adb ldr r3, [r3, #44] @ 0x2c
80049f6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80049f8: 429a cmp r2, r3
80049fa: d001 beq.n 8004a00 <HAL_RCC_OscConfig+0x4e0>
#endif /* RCC_PLLCFGR_PLLR */
{
return HAL_ERROR;
80049fc: 2301 movs r3, #1
80049fe: e000 b.n 8004a02 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8004a00: 2300 movs r3, #0
}
8004a02: 4618 mov r0, r3
8004a04: 3718 adds r7, #24
8004a06: 46bd mov sp, r7
8004a08: bd80 pop {r7, pc}
8004a0a: bf00 nop
8004a0c: 40023800 .word 0x40023800
08004a10 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8004a10: b580 push {r7, lr}
8004a12: b084 sub sp, #16
8004a14: af00 add r7, sp, #0
8004a16: 6078 str r0, [r7, #4]
8004a18: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8004a1a: 687b ldr r3, [r7, #4]
8004a1c: 2b00 cmp r3, #0
8004a1e: d101 bne.n 8004a24 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8004a20: 2301 movs r3, #1
8004a22: e0cc b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8004a24: 4b68 ldr r3, [pc, #416] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004a26: 681b ldr r3, [r3, #0]
8004a28: f003 030f and.w r3, r3, #15
8004a2c: 683a ldr r2, [r7, #0]
8004a2e: 429a cmp r2, r3
8004a30: d90c bls.n 8004a4c <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004a32: 4b65 ldr r3, [pc, #404] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004a34: 683a ldr r2, [r7, #0]
8004a36: b2d2 uxtb r2, r2
8004a38: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8004a3a: 4b63 ldr r3, [pc, #396] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004a3c: 681b ldr r3, [r3, #0]
8004a3e: f003 030f and.w r3, r3, #15
8004a42: 683a ldr r2, [r7, #0]
8004a44: 429a cmp r2, r3
8004a46: d001 beq.n 8004a4c <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8004a48: 2301 movs r3, #1
8004a4a: e0b8 b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8004a4c: 687b ldr r3, [r7, #4]
8004a4e: 681b ldr r3, [r3, #0]
8004a50: f003 0302 and.w r3, r3, #2
8004a54: 2b00 cmp r3, #0
8004a56: d020 beq.n 8004a9a <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004a58: 687b ldr r3, [r7, #4]
8004a5a: 681b ldr r3, [r3, #0]
8004a5c: f003 0304 and.w r3, r3, #4
8004a60: 2b00 cmp r3, #0
8004a62: d005 beq.n 8004a70 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8004a64: 4b59 ldr r3, [pc, #356] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a66: 689b ldr r3, [r3, #8]
8004a68: 4a58 ldr r2, [pc, #352] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a6a: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
8004a6e: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004a70: 687b ldr r3, [r7, #4]
8004a72: 681b ldr r3, [r3, #0]
8004a74: f003 0308 and.w r3, r3, #8
8004a78: 2b00 cmp r3, #0
8004a7a: d005 beq.n 8004a88 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8004a7c: 4b53 ldr r3, [pc, #332] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a7e: 689b ldr r3, [r3, #8]
8004a80: 4a52 ldr r2, [pc, #328] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a82: f443 4360 orr.w r3, r3, #57344 @ 0xe000
8004a86: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8004a88: 4b50 ldr r3, [pc, #320] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a8a: 689b ldr r3, [r3, #8]
8004a8c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8004a90: 687b ldr r3, [r7, #4]
8004a92: 689b ldr r3, [r3, #8]
8004a94: 494d ldr r1, [pc, #308] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004a96: 4313 orrs r3, r2
8004a98: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8004a9a: 687b ldr r3, [r7, #4]
8004a9c: 681b ldr r3, [r3, #0]
8004a9e: f003 0301 and.w r3, r3, #1
8004aa2: 2b00 cmp r3, #0
8004aa4: d044 beq.n 8004b30 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8004aa6: 687b ldr r3, [r7, #4]
8004aa8: 685b ldr r3, [r3, #4]
8004aaa: 2b01 cmp r3, #1
8004aac: d107 bne.n 8004abe <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8004aae: 4b47 ldr r3, [pc, #284] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004ab0: 681b ldr r3, [r3, #0]
8004ab2: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004ab6: 2b00 cmp r3, #0
8004ab8: d119 bne.n 8004aee <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004aba: 2301 movs r3, #1
8004abc: e07f b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8004abe: 687b ldr r3, [r7, #4]
8004ac0: 685b ldr r3, [r3, #4]
8004ac2: 2b02 cmp r3, #2
8004ac4: d003 beq.n 8004ace <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8004ac6: 687b ldr r3, [r7, #4]
8004ac8: 685b ldr r3, [r3, #4]
else if ((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8004aca: 2b03 cmp r3, #3
8004acc: d107 bne.n 8004ade <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8004ace: 4b3f ldr r3, [pc, #252] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004ad0: 681b ldr r3, [r3, #0]
8004ad2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004ad6: 2b00 cmp r3, #0
8004ad8: d109 bne.n 8004aee <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004ada: 2301 movs r3, #1
8004adc: e06f b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8004ade: 4b3b ldr r3, [pc, #236] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004ae0: 681b ldr r3, [r3, #0]
8004ae2: f003 0302 and.w r3, r3, #2
8004ae6: 2b00 cmp r3, #0
8004ae8: d101 bne.n 8004aee <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8004aea: 2301 movs r3, #1
8004aec: e067 b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8004aee: 4b37 ldr r3, [pc, #220] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004af0: 689b ldr r3, [r3, #8]
8004af2: f023 0203 bic.w r2, r3, #3
8004af6: 687b ldr r3, [r7, #4]
8004af8: 685b ldr r3, [r3, #4]
8004afa: 4934 ldr r1, [pc, #208] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004afc: 4313 orrs r3, r2
8004afe: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8004b00: f7fc fd9e bl 8001640 <HAL_GetTick>
8004b04: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004b06: e00a b.n 8004b1e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8004b08: f7fc fd9a bl 8001640 <HAL_GetTick>
8004b0c: 4602 mov r2, r0
8004b0e: 68fb ldr r3, [r7, #12]
8004b10: 1ad3 subs r3, r2, r3
8004b12: f241 3288 movw r2, #5000 @ 0x1388
8004b16: 4293 cmp r3, r2
8004b18: d901 bls.n 8004b1e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8004b1a: 2303 movs r3, #3
8004b1c: e04f b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8004b1e: 4b2b ldr r3, [pc, #172] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b20: 689b ldr r3, [r3, #8]
8004b22: f003 020c and.w r2, r3, #12
8004b26: 687b ldr r3, [r7, #4]
8004b28: 685b ldr r3, [r3, #4]
8004b2a: 009b lsls r3, r3, #2
8004b2c: 429a cmp r2, r3
8004b2e: d1eb bne.n 8004b08 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8004b30: 4b25 ldr r3, [pc, #148] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004b32: 681b ldr r3, [r3, #0]
8004b34: f003 030f and.w r3, r3, #15
8004b38: 683a ldr r2, [r7, #0]
8004b3a: 429a cmp r2, r3
8004b3c: d20c bcs.n 8004b58 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8004b3e: 4b22 ldr r3, [pc, #136] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004b40: 683a ldr r2, [r7, #0]
8004b42: b2d2 uxtb r2, r2
8004b44: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8004b46: 4b20 ldr r3, [pc, #128] @ (8004bc8 <HAL_RCC_ClockConfig+0x1b8>)
8004b48: 681b ldr r3, [r3, #0]
8004b4a: f003 030f and.w r3, r3, #15
8004b4e: 683a ldr r2, [r7, #0]
8004b50: 429a cmp r2, r3
8004b52: d001 beq.n 8004b58 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8004b54: 2301 movs r3, #1
8004b56: e032 b.n 8004bbe <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8004b58: 687b ldr r3, [r7, #4]
8004b5a: 681b ldr r3, [r3, #0]
8004b5c: f003 0304 and.w r3, r3, #4
8004b60: 2b00 cmp r3, #0
8004b62: d008 beq.n 8004b76 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8004b64: 4b19 ldr r3, [pc, #100] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b66: 689b ldr r3, [r3, #8]
8004b68: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
8004b6c: 687b ldr r3, [r7, #4]
8004b6e: 68db ldr r3, [r3, #12]
8004b70: 4916 ldr r1, [pc, #88] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b72: 4313 orrs r3, r2
8004b74: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8004b76: 687b ldr r3, [r7, #4]
8004b78: 681b ldr r3, [r3, #0]
8004b7a: f003 0308 and.w r3, r3, #8
8004b7e: 2b00 cmp r3, #0
8004b80: d009 beq.n 8004b96 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8004b82: 4b12 ldr r3, [pc, #72] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b84: 689b ldr r3, [r3, #8]
8004b86: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8004b8a: 687b ldr r3, [r7, #4]
8004b8c: 691b ldr r3, [r3, #16]
8004b8e: 00db lsls r3, r3, #3
8004b90: 490e ldr r1, [pc, #56] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b92: 4313 orrs r3, r2
8004b94: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
8004b96: f000 f821 bl 8004bdc <HAL_RCC_GetSysClockFreq>
8004b9a: 4602 mov r2, r0
8004b9c: 4b0b ldr r3, [pc, #44] @ (8004bcc <HAL_RCC_ClockConfig+0x1bc>)
8004b9e: 689b ldr r3, [r3, #8]
8004ba0: 091b lsrs r3, r3, #4
8004ba2: f003 030f and.w r3, r3, #15
8004ba6: 490a ldr r1, [pc, #40] @ (8004bd0 <HAL_RCC_ClockConfig+0x1c0>)
8004ba8: 5ccb ldrb r3, [r1, r3]
8004baa: fa22 f303 lsr.w r3, r2, r3
8004bae: 4a09 ldr r2, [pc, #36] @ (8004bd4 <HAL_RCC_ClockConfig+0x1c4>)
8004bb0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick(uwTickPrio);
8004bb2: 4b09 ldr r3, [pc, #36] @ (8004bd8 <HAL_RCC_ClockConfig+0x1c8>)
8004bb4: 681b ldr r3, [r3, #0]
8004bb6: 4618 mov r0, r3
8004bb8: f7fc fc10 bl 80013dc <HAL_InitTick>
return HAL_OK;
8004bbc: 2300 movs r3, #0
}
8004bbe: 4618 mov r0, r3
8004bc0: 3710 adds r7, #16
8004bc2: 46bd mov sp, r7
8004bc4: bd80 pop {r7, pc}
8004bc6: bf00 nop
8004bc8: 40023c00 .word 0x40023c00
8004bcc: 40023800 .word 0x40023800
8004bd0: 08007f1c .word 0x08007f1c
8004bd4: 20000000 .word 0x20000000
8004bd8: 20000004 .word 0x20000004
08004bdc <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8004bdc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8004be0: b094 sub sp, #80 @ 0x50
8004be2: af00 add r7, sp, #0
uint32_t pllm = 0U;
8004be4: 2300 movs r3, #0
8004be6: 647b str r3, [r7, #68] @ 0x44
uint32_t pllvco = 0U;
8004be8: 2300 movs r3, #0
8004bea: 64fb str r3, [r7, #76] @ 0x4c
uint32_t pllp = 0U;
8004bec: 2300 movs r3, #0
8004bee: 643b str r3, [r7, #64] @ 0x40
uint32_t sysclockfreq = 0U;
8004bf0: 2300 movs r3, #0
8004bf2: 64bb str r3, [r7, #72] @ 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8004bf4: 4b79 ldr r3, [pc, #484] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004bf6: 689b ldr r3, [r3, #8]
8004bf8: f003 030c and.w r3, r3, #12
8004bfc: 2b08 cmp r3, #8
8004bfe: d00d beq.n 8004c1c <HAL_RCC_GetSysClockFreq+0x40>
8004c00: 2b08 cmp r3, #8
8004c02: f200 80e1 bhi.w 8004dc8 <HAL_RCC_GetSysClockFreq+0x1ec>
8004c06: 2b00 cmp r3, #0
8004c08: d002 beq.n 8004c10 <HAL_RCC_GetSysClockFreq+0x34>
8004c0a: 2b04 cmp r3, #4
8004c0c: d003 beq.n 8004c16 <HAL_RCC_GetSysClockFreq+0x3a>
8004c0e: e0db b.n 8004dc8 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8004c10: 4b73 ldr r3, [pc, #460] @ (8004de0 <HAL_RCC_GetSysClockFreq+0x204>)
8004c12: 64bb str r3, [r7, #72] @ 0x48
break;
8004c14: e0db b.n 8004dce <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8004c16: 4b73 ldr r3, [pc, #460] @ (8004de4 <HAL_RCC_GetSysClockFreq+0x208>)
8004c18: 64bb str r3, [r7, #72] @ 0x48
break;
8004c1a: e0d8 b.n 8004dce <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8004c1c: 4b6f ldr r3, [pc, #444] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004c1e: 685b ldr r3, [r3, #4]
8004c20: f003 033f and.w r3, r3, #63 @ 0x3f
8004c24: 647b str r3, [r7, #68] @ 0x44
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8004c26: 4b6d ldr r3, [pc, #436] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004c28: 685b ldr r3, [r3, #4]
8004c2a: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8004c2e: 2b00 cmp r3, #0
8004c30: d063 beq.n 8004cfa <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8004c32: 4b6a ldr r3, [pc, #424] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004c34: 685b ldr r3, [r3, #4]
8004c36: 099b lsrs r3, r3, #6
8004c38: 2200 movs r2, #0
8004c3a: 63bb str r3, [r7, #56] @ 0x38
8004c3c: 63fa str r2, [r7, #60] @ 0x3c
8004c3e: 6bbb ldr r3, [r7, #56] @ 0x38
8004c40: f3c3 0308 ubfx r3, r3, #0, #9
8004c44: 633b str r3, [r7, #48] @ 0x30
8004c46: 2300 movs r3, #0
8004c48: 637b str r3, [r7, #52] @ 0x34
8004c4a: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
8004c4e: 4622 mov r2, r4
8004c50: 462b mov r3, r5
8004c52: f04f 0000 mov.w r0, #0
8004c56: f04f 0100 mov.w r1, #0
8004c5a: 0159 lsls r1, r3, #5
8004c5c: ea41 61d2 orr.w r1, r1, r2, lsr #27
8004c60: 0150 lsls r0, r2, #5
8004c62: 4602 mov r2, r0
8004c64: 460b mov r3, r1
8004c66: 4621 mov r1, r4
8004c68: 1a51 subs r1, r2, r1
8004c6a: 6139 str r1, [r7, #16]
8004c6c: 4629 mov r1, r5
8004c6e: eb63 0301 sbc.w r3, r3, r1
8004c72: 617b str r3, [r7, #20]
8004c74: f04f 0200 mov.w r2, #0
8004c78: f04f 0300 mov.w r3, #0
8004c7c: e9d7 ab04 ldrd sl, fp, [r7, #16]
8004c80: 4659 mov r1, fp
8004c82: 018b lsls r3, r1, #6
8004c84: 4651 mov r1, sl
8004c86: ea43 6391 orr.w r3, r3, r1, lsr #26
8004c8a: 4651 mov r1, sl
8004c8c: 018a lsls r2, r1, #6
8004c8e: 4651 mov r1, sl
8004c90: ebb2 0801 subs.w r8, r2, r1
8004c94: 4659 mov r1, fp
8004c96: eb63 0901 sbc.w r9, r3, r1
8004c9a: f04f 0200 mov.w r2, #0
8004c9e: f04f 0300 mov.w r3, #0
8004ca2: ea4f 03c9 mov.w r3, r9, lsl #3
8004ca6: ea43 7358 orr.w r3, r3, r8, lsr #29
8004caa: ea4f 02c8 mov.w r2, r8, lsl #3
8004cae: 4690 mov r8, r2
8004cb0: 4699 mov r9, r3
8004cb2: 4623 mov r3, r4
8004cb4: eb18 0303 adds.w r3, r8, r3
8004cb8: 60bb str r3, [r7, #8]
8004cba: 462b mov r3, r5
8004cbc: eb49 0303 adc.w r3, r9, r3
8004cc0: 60fb str r3, [r7, #12]
8004cc2: f04f 0200 mov.w r2, #0
8004cc6: f04f 0300 mov.w r3, #0
8004cca: e9d7 4502 ldrd r4, r5, [r7, #8]
8004cce: 4629 mov r1, r5
8004cd0: 024b lsls r3, r1, #9
8004cd2: 4621 mov r1, r4
8004cd4: ea43 53d1 orr.w r3, r3, r1, lsr #23
8004cd8: 4621 mov r1, r4
8004cda: 024a lsls r2, r1, #9
8004cdc: 4610 mov r0, r2
8004cde: 4619 mov r1, r3
8004ce0: 6c7b ldr r3, [r7, #68] @ 0x44
8004ce2: 2200 movs r2, #0
8004ce4: 62bb str r3, [r7, #40] @ 0x28
8004ce6: 62fa str r2, [r7, #44] @ 0x2c
8004ce8: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
8004cec: f7fb fa80 bl 80001f0 <__aeabi_uldivmod>
8004cf0: 4602 mov r2, r0
8004cf2: 460b mov r3, r1
8004cf4: 4613 mov r3, r2
8004cf6: 64fb str r3, [r7, #76] @ 0x4c
8004cf8: e058 b.n 8004dac <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8004cfa: 4b38 ldr r3, [pc, #224] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004cfc: 685b ldr r3, [r3, #4]
8004cfe: 099b lsrs r3, r3, #6
8004d00: 2200 movs r2, #0
8004d02: 4618 mov r0, r3
8004d04: 4611 mov r1, r2
8004d06: f3c0 0308 ubfx r3, r0, #0, #9
8004d0a: 623b str r3, [r7, #32]
8004d0c: 2300 movs r3, #0
8004d0e: 627b str r3, [r7, #36] @ 0x24
8004d10: e9d7 8908 ldrd r8, r9, [r7, #32]
8004d14: 4642 mov r2, r8
8004d16: 464b mov r3, r9
8004d18: f04f 0000 mov.w r0, #0
8004d1c: f04f 0100 mov.w r1, #0
8004d20: 0159 lsls r1, r3, #5
8004d22: ea41 61d2 orr.w r1, r1, r2, lsr #27
8004d26: 0150 lsls r0, r2, #5
8004d28: 4602 mov r2, r0
8004d2a: 460b mov r3, r1
8004d2c: 4641 mov r1, r8
8004d2e: ebb2 0a01 subs.w sl, r2, r1
8004d32: 4649 mov r1, r9
8004d34: eb63 0b01 sbc.w fp, r3, r1
8004d38: f04f 0200 mov.w r2, #0
8004d3c: f04f 0300 mov.w r3, #0
8004d40: ea4f 138b mov.w r3, fp, lsl #6
8004d44: ea43 639a orr.w r3, r3, sl, lsr #26
8004d48: ea4f 128a mov.w r2, sl, lsl #6
8004d4c: ebb2 040a subs.w r4, r2, sl
8004d50: eb63 050b sbc.w r5, r3, fp
8004d54: f04f 0200 mov.w r2, #0
8004d58: f04f 0300 mov.w r3, #0
8004d5c: 00eb lsls r3, r5, #3
8004d5e: ea43 7354 orr.w r3, r3, r4, lsr #29
8004d62: 00e2 lsls r2, r4, #3
8004d64: 4614 mov r4, r2
8004d66: 461d mov r5, r3
8004d68: 4643 mov r3, r8
8004d6a: 18e3 adds r3, r4, r3
8004d6c: 603b str r3, [r7, #0]
8004d6e: 464b mov r3, r9
8004d70: eb45 0303 adc.w r3, r5, r3
8004d74: 607b str r3, [r7, #4]
8004d76: f04f 0200 mov.w r2, #0
8004d7a: f04f 0300 mov.w r3, #0
8004d7e: e9d7 4500 ldrd r4, r5, [r7]
8004d82: 4629 mov r1, r5
8004d84: 028b lsls r3, r1, #10
8004d86: 4621 mov r1, r4
8004d88: ea43 5391 orr.w r3, r3, r1, lsr #22
8004d8c: 4621 mov r1, r4
8004d8e: 028a lsls r2, r1, #10
8004d90: 4610 mov r0, r2
8004d92: 4619 mov r1, r3
8004d94: 6c7b ldr r3, [r7, #68] @ 0x44
8004d96: 2200 movs r2, #0
8004d98: 61bb str r3, [r7, #24]
8004d9a: 61fa str r2, [r7, #28]
8004d9c: e9d7 2306 ldrd r2, r3, [r7, #24]
8004da0: f7fb fa26 bl 80001f0 <__aeabi_uldivmod>
8004da4: 4602 mov r2, r0
8004da6: 460b mov r3, r1
8004da8: 4613 mov r3, r2
8004daa: 64fb str r3, [r7, #76] @ 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) * 2U);
8004dac: 4b0b ldr r3, [pc, #44] @ (8004ddc <HAL_RCC_GetSysClockFreq+0x200>)
8004dae: 685b ldr r3, [r3, #4]
8004db0: 0c1b lsrs r3, r3, #16
8004db2: f003 0303 and.w r3, r3, #3
8004db6: 3301 adds r3, #1
8004db8: 005b lsls r3, r3, #1
8004dba: 643b str r3, [r7, #64] @ 0x40
sysclockfreq = pllvco / pllp;
8004dbc: 6cfa ldr r2, [r7, #76] @ 0x4c
8004dbe: 6c3b ldr r3, [r7, #64] @ 0x40
8004dc0: fbb2 f3f3 udiv r3, r2, r3
8004dc4: 64bb str r3, [r7, #72] @ 0x48
break;
8004dc6: e002 b.n 8004dce <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
8004dc8: 4b05 ldr r3, [pc, #20] @ (8004de0 <HAL_RCC_GetSysClockFreq+0x204>)
8004dca: 64bb str r3, [r7, #72] @ 0x48
break;
8004dcc: bf00 nop
}
}
return sysclockfreq;
8004dce: 6cbb ldr r3, [r7, #72] @ 0x48
}
8004dd0: 4618 mov r0, r3
8004dd2: 3750 adds r7, #80 @ 0x50
8004dd4: 46bd mov sp, r7
8004dd6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8004dda: bf00 nop
8004ddc: 40023800 .word 0x40023800
8004de0: 00f42400 .word 0x00f42400
8004de4: 007a1200 .word 0x007a1200
08004de8 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8004de8: b480 push {r7}
8004dea: af00 add r7, sp, #0
return SystemCoreClock;
8004dec: 4b03 ldr r3, [pc, #12] @ (8004dfc <HAL_RCC_GetHCLKFreq+0x14>)
8004dee: 681b ldr r3, [r3, #0]
}
8004df0: 4618 mov r0, r3
8004df2: 46bd mov sp, r7
8004df4: f85d 7b04 ldr.w r7, [sp], #4
8004df8: 4770 bx lr
8004dfa: bf00 nop
8004dfc: 20000000 .word 0x20000000
08004e00 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8004e00: b580 push {r7, lr}
8004e02: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
8004e04: f7ff fff0 bl 8004de8 <HAL_RCC_GetHCLKFreq>
8004e08: 4602 mov r2, r0
8004e0a: 4b05 ldr r3, [pc, #20] @ (8004e20 <HAL_RCC_GetPCLK1Freq+0x20>)
8004e0c: 689b ldr r3, [r3, #8]
8004e0e: 0a9b lsrs r3, r3, #10
8004e10: f003 0307 and.w r3, r3, #7
8004e14: 4903 ldr r1, [pc, #12] @ (8004e24 <HAL_RCC_GetPCLK1Freq+0x24>)
8004e16: 5ccb ldrb r3, [r1, r3]
8004e18: fa22 f303 lsr.w r3, r2, r3
}
8004e1c: 4618 mov r0, r3
8004e1e: bd80 pop {r7, pc}
8004e20: 40023800 .word 0x40023800
8004e24: 08007f2c .word 0x08007f2c
08004e28 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8004e28: b580 push {r7, lr}
8004e2a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
8004e2c: f7ff ffdc bl 8004de8 <HAL_RCC_GetHCLKFreq>
8004e30: 4602 mov r2, r0
8004e32: 4b05 ldr r3, [pc, #20] @ (8004e48 <HAL_RCC_GetPCLK2Freq+0x20>)
8004e34: 689b ldr r3, [r3, #8]
8004e36: 0b5b lsrs r3, r3, #13
8004e38: f003 0307 and.w r3, r3, #7
8004e3c: 4903 ldr r1, [pc, #12] @ (8004e4c <HAL_RCC_GetPCLK2Freq+0x24>)
8004e3e: 5ccb ldrb r3, [r1, r3]
8004e40: fa22 f303 lsr.w r3, r2, r3
}
8004e44: 4618 mov r0, r3
8004e46: bd80 pop {r7, pc}
8004e48: 40023800 .word 0x40023800
8004e4c: 08007f2c .word 0x08007f2c
08004e50 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8004e50: b480 push {r7}
8004e52: b083 sub sp, #12
8004e54: af00 add r7, sp, #0
8004e56: 6078 str r0, [r7, #4]
8004e58: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8004e5a: 687b ldr r3, [r7, #4]
8004e5c: 220f movs r2, #15
8004e5e: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8004e60: 4b12 ldr r3, [pc, #72] @ (8004eac <HAL_RCC_GetClockConfig+0x5c>)
8004e62: 689b ldr r3, [r3, #8]
8004e64: f003 0203 and.w r2, r3, #3
8004e68: 687b ldr r3, [r7, #4]
8004e6a: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8004e6c: 4b0f ldr r3, [pc, #60] @ (8004eac <HAL_RCC_GetClockConfig+0x5c>)
8004e6e: 689b ldr r3, [r3, #8]
8004e70: f003 02f0 and.w r2, r3, #240 @ 0xf0
8004e74: 687b ldr r3, [r7, #4]
8004e76: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8004e78: 4b0c ldr r3, [pc, #48] @ (8004eac <HAL_RCC_GetClockConfig+0x5c>)
8004e7a: 689b ldr r3, [r3, #8]
8004e7c: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8004e80: 687b ldr r3, [r7, #4]
8004e82: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
8004e84: 4b09 ldr r3, [pc, #36] @ (8004eac <HAL_RCC_GetClockConfig+0x5c>)
8004e86: 689b ldr r3, [r3, #8]
8004e88: 08db lsrs r3, r3, #3
8004e8a: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8004e8e: 687b ldr r3, [r7, #4]
8004e90: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8004e92: 4b07 ldr r3, [pc, #28] @ (8004eb0 <HAL_RCC_GetClockConfig+0x60>)
8004e94: 681b ldr r3, [r3, #0]
8004e96: f003 020f and.w r2, r3, #15
8004e9a: 683b ldr r3, [r7, #0]
8004e9c: 601a str r2, [r3, #0]
}
8004e9e: bf00 nop
8004ea0: 370c adds r7, #12
8004ea2: 46bd mov sp, r7
8004ea4: f85d 7b04 ldr.w r7, [sp], #4
8004ea8: 4770 bx lr
8004eaa: bf00 nop
8004eac: 40023800 .word 0x40023800
8004eb0: 40023c00 .word 0x40023c00
08004eb4 <HAL_RCCEx_PeriphCLKConfig>:
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8004eb4: b580 push {r7, lr}
8004eb6: b086 sub sp, #24
8004eb8: af00 add r7, sp, #0
8004eba: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8004ebc: 2300 movs r3, #0
8004ebe: 617b str r3, [r7, #20]
uint32_t tmpreg1 = 0U;
8004ec0: 2300 movs r3, #0
8004ec2: 613b str r3, [r7, #16]
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
/*----------------------- Common configuration SAI/I2S ---------------------*/
/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
factor is common parameters for both peripherals */
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8004ec4: 687b ldr r3, [r7, #4]
8004ec6: 681b ldr r3, [r3, #0]
8004ec8: f003 0301 and.w r3, r3, #1
8004ecc: 2b00 cmp r3, #0
8004ece: d10b bne.n 8004ee8 <HAL_RCCEx_PeriphCLKConfig+0x34>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 681b ldr r3, [r3, #0]
8004ed4: f003 0302 and.w r3, r3, #2
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
8004ed8: 2b00 cmp r3, #0
8004eda: d105 bne.n 8004ee8 <HAL_RCCEx_PeriphCLKConfig+0x34>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
8004edc: 687b ldr r3, [r7, #4]
8004ede: 681b ldr r3, [r3, #0]
8004ee0: f003 0340 and.w r3, r3, #64 @ 0x40
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
8004ee4: 2b00 cmp r3, #0
8004ee6: d075 beq.n 8004fd4 <HAL_RCCEx_PeriphCLKConfig+0x120>
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/* Disable the PLLI2S */
__HAL_RCC_PLLI2S_DISABLE();
8004ee8: 4b91 ldr r3, [pc, #580] @ (8005130 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
8004eea: 2200 movs r2, #0
8004eec: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8004eee: f7fc fba7 bl 8001640 <HAL_GetTick>
8004ef2: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8004ef4: e008 b.n 8004f08 <HAL_RCCEx_PeriphCLKConfig+0x54>
{
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8004ef6: f7fc fba3 bl 8001640 <HAL_GetTick>
8004efa: 4602 mov r2, r0
8004efc: 697b ldr r3, [r7, #20]
8004efe: 1ad3 subs r3, r2, r3
8004f00: 2b02 cmp r3, #2
8004f02: d901 bls.n 8004f08 <HAL_RCCEx_PeriphCLKConfig+0x54>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8004f04: 2303 movs r3, #3
8004f06: e189 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
8004f08: 4b8a ldr r3, [pc, #552] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f0a: 681b ldr r3, [r3, #0]
8004f0c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8004f10: 2b00 cmp r3, #0
8004f12: d1f0 bne.n 8004ef6 <HAL_RCCEx_PeriphCLKConfig+0x42>
}
/*---------------------------- I2S configuration -------------------------*/
/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
only for I2S configuration */
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
8004f14: 687b ldr r3, [r7, #4]
8004f16: 681b ldr r3, [r3, #0]
8004f18: f003 0301 and.w r3, r3, #1
8004f1c: 2b00 cmp r3, #0
8004f1e: d009 beq.n 8004f34 <HAL_RCCEx_PeriphCLKConfig+0x80>
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
8004f20: 687b ldr r3, [r7, #4]
8004f22: 685b ldr r3, [r3, #4]
8004f24: 019a lsls r2, r3, #6
8004f26: 687b ldr r3, [r7, #4]
8004f28: 689b ldr r3, [r3, #8]
8004f2a: 071b lsls r3, r3, #28
8004f2c: 4981 ldr r1, [pc, #516] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f2e: 4313 orrs r3, r2
8004f30: f8c1 3084 str.w r3, [r1, #132] @ 0x84
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
be added only for SAI configuration */
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
8004f34: 687b ldr r3, [r7, #4]
8004f36: 681b ldr r3, [r3, #0]
8004f38: f003 0302 and.w r3, r3, #2
8004f3c: 2b00 cmp r3, #0
8004f3e: d01f beq.n 8004f80 <HAL_RCCEx_PeriphCLKConfig+0xcc>
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
8004f40: 4b7c ldr r3, [pc, #496] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f42: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
8004f46: 0f1b lsrs r3, r3, #28
8004f48: f003 0307 and.w r3, r3, #7
8004f4c: 613b str r3, [r7, #16]
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1);
8004f4e: 687b ldr r3, [r7, #4]
8004f50: 685b ldr r3, [r3, #4]
8004f52: 019a lsls r2, r3, #6
8004f54: 687b ldr r3, [r7, #4]
8004f56: 68db ldr r3, [r3, #12]
8004f58: 061b lsls r3, r3, #24
8004f5a: 431a orrs r2, r3
8004f5c: 693b ldr r3, [r7, #16]
8004f5e: 071b lsls r3, r3, #28
8004f60: 4974 ldr r1, [pc, #464] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f62: 4313 orrs r3, r2
8004f64: f8c1 3084 str.w r3, [r1, #132] @ 0x84
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
8004f68: 4b72 ldr r3, [pc, #456] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f6a: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8004f6e: f023 021f bic.w r2, r3, #31
8004f72: 687b ldr r3, [r7, #4]
8004f74: 69db ldr r3, [r3, #28]
8004f76: 3b01 subs r3, #1
8004f78: 496e ldr r1, [pc, #440] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004f7a: 4313 orrs r3, r2
8004f7c: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*----------------- In Case of PLLI2S is just selected -----------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
8004f80: 687b ldr r3, [r7, #4]
8004f82: 681b ldr r3, [r3, #0]
8004f84: f003 0340 and.w r3, r3, #64 @ 0x40
8004f88: 2b00 cmp r3, #0
8004f8a: d00d beq.n 8004fa8 <HAL_RCCEx_PeriphCLKConfig+0xf4>
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ,
8004f8c: 687b ldr r3, [r7, #4]
8004f8e: 685b ldr r3, [r3, #4]
8004f90: 019a lsls r2, r3, #6
8004f92: 687b ldr r3, [r7, #4]
8004f94: 68db ldr r3, [r3, #12]
8004f96: 061b lsls r3, r3, #24
8004f98: 431a orrs r2, r3
8004f9a: 687b ldr r3, [r7, #4]
8004f9c: 689b ldr r3, [r3, #8]
8004f9e: 071b lsls r3, r3, #28
8004fa0: 4964 ldr r1, [pc, #400] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004fa2: 4313 orrs r3, r2
8004fa4: f8c1 3084 str.w r3, [r1, #132] @ 0x84
PeriphClkInit->PLLI2S.PLLI2SR);
}
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
8004fa8: 4b61 ldr r3, [pc, #388] @ (8005130 <HAL_RCCEx_PeriphCLKConfig+0x27c>)
8004faa: 2201 movs r2, #1
8004fac: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8004fae: f7fc fb47 bl 8001640 <HAL_GetTick>
8004fb2: 6178 str r0, [r7, #20]
/* Wait till PLLI2S is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8004fb4: e008 b.n 8004fc8 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
8004fb6: f7fc fb43 bl 8001640 <HAL_GetTick>
8004fba: 4602 mov r2, r0
8004fbc: 697b ldr r3, [r7, #20]
8004fbe: 1ad3 subs r3, r2, r3
8004fc0: 2b02 cmp r3, #2
8004fc2: d901 bls.n 8004fc8 <HAL_RCCEx_PeriphCLKConfig+0x114>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8004fc4: 2303 movs r3, #3
8004fc6: e129 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
8004fc8: 4b5a ldr r3, [pc, #360] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8004fca: 681b ldr r3, [r3, #0]
8004fcc: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
8004fd0: 2b00 cmp r3, #0
8004fd2: d0f0 beq.n 8004fb6 <HAL_RCCEx_PeriphCLKConfig+0x102>
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
factor is common parameters for both peripherals */
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
8004fd4: 687b ldr r3, [r7, #4]
8004fd6: 681b ldr r3, [r3, #0]
8004fd8: f003 0304 and.w r3, r3, #4
8004fdc: 2b00 cmp r3, #0
8004fde: d105 bne.n 8004fec <HAL_RCCEx_PeriphCLKConfig+0x138>
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
8004fe0: 687b ldr r3, [r7, #4]
8004fe2: 681b ldr r3, [r3, #0]
8004fe4: f003 0308 and.w r3, r3, #8
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
8004fe8: 2b00 cmp r3, #0
8004fea: d079 beq.n 80050e0 <HAL_RCCEx_PeriphCLKConfig+0x22c>
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
/* Disable PLLSAI Clock */
__HAL_RCC_PLLSAI_DISABLE();
8004fec: 4b52 ldr r3, [pc, #328] @ (8005138 <HAL_RCCEx_PeriphCLKConfig+0x284>)
8004fee: 2200 movs r2, #0
8004ff0: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8004ff2: f7fc fb25 bl 8001640 <HAL_GetTick>
8004ff6: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is disabled */
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
8004ff8: e008 b.n 800500c <HAL_RCCEx_PeriphCLKConfig+0x158>
{
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
8004ffa: f7fc fb21 bl 8001640 <HAL_GetTick>
8004ffe: 4602 mov r2, r0
8005000: 697b ldr r3, [r7, #20]
8005002: 1ad3 subs r3, r2, r3
8005004: 2b02 cmp r3, #2
8005006: d901 bls.n 800500c <HAL_RCCEx_PeriphCLKConfig+0x158>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
8005008: 2303 movs r3, #3
800500a: e107 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
while (__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
800500c: 4b49 ldr r3, [pc, #292] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
800500e: 681b ldr r3, [r3, #0]
8005010: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8005014: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8005018: d0ef beq.n 8004ffa <HAL_RCCEx_PeriphCLKConfig+0x146>
}
/*---------------------------- SAI configuration -------------------------*/
/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
be added only for SAI configuration */
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
800501a: 687b ldr r3, [r7, #4]
800501c: 681b ldr r3, [r3, #0]
800501e: f003 0304 and.w r3, r3, #4
8005022: 2b00 cmp r3, #0
8005024: d020 beq.n 8005068 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
8005026: 4b43 ldr r3, [pc, #268] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005028: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800502c: 0f1b lsrs r3, r3, #28
800502e: f003 0307 and.w r3, r3, #7
8005032: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
8005034: 687b ldr r3, [r7, #4]
8005036: 691b ldr r3, [r3, #16]
8005038: 019a lsls r2, r3, #6
800503a: 687b ldr r3, [r7, #4]
800503c: 695b ldr r3, [r3, #20]
800503e: 061b lsls r3, r3, #24
8005040: 431a orrs r2, r3
8005042: 693b ldr r3, [r7, #16]
8005044: 071b lsls r3, r3, #28
8005046: 493b ldr r1, [pc, #236] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005048: 4313 orrs r3, r2
800504a: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
800504e: 4b39 ldr r3, [pc, #228] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005050: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
8005054: f423 52f8 bic.w r2, r3, #7936 @ 0x1f00
8005058: 687b ldr r3, [r7, #4]
800505a: 6a1b ldr r3, [r3, #32]
800505c: 3b01 subs r3, #1
800505e: 021b lsls r3, r3, #8
8005060: 4934 ldr r1, [pc, #208] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005062: 4313 orrs r3, r2
8005064: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/*---------------------------- LTDC configuration ------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
8005068: 687b ldr r3, [r7, #4]
800506a: 681b ldr r3, [r3, #0]
800506c: f003 0308 and.w r3, r3, #8
8005070: 2b00 cmp r3, #0
8005072: d01e beq.n 80050b2 <HAL_RCCEx_PeriphCLKConfig+0x1fe>
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
8005074: 4b2f ldr r3, [pc, #188] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005076: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800507a: 0e1b lsrs r3, r3, #24
800507c: f003 030f and.w r3, r3, #15
8005080: 613b str r3, [r7, #16]
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
8005082: 687b ldr r3, [r7, #4]
8005084: 691b ldr r3, [r3, #16]
8005086: 019a lsls r2, r3, #6
8005088: 693b ldr r3, [r7, #16]
800508a: 061b lsls r3, r3, #24
800508c: 431a orrs r2, r3
800508e: 687b ldr r3, [r7, #4]
8005090: 699b ldr r3, [r3, #24]
8005092: 071b lsls r3, r3, #28
8005094: 4927 ldr r1, [pc, #156] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005096: 4313 orrs r3, r2
8005098: f8c1 3088 str.w r3, [r1, #136] @ 0x88
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
800509c: 4b25 ldr r3, [pc, #148] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
800509e: f8d3 308c ldr.w r3, [r3, #140] @ 0x8c
80050a2: f423 3240 bic.w r2, r3, #196608 @ 0x30000
80050a6: 687b ldr r3, [r7, #4]
80050a8: 6a5b ldr r3, [r3, #36] @ 0x24
80050aa: 4922 ldr r1, [pc, #136] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
80050ac: 4313 orrs r3, r2
80050ae: f8c1 308c str.w r3, [r1, #140] @ 0x8c
}
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
80050b2: 4b21 ldr r3, [pc, #132] @ (8005138 <HAL_RCCEx_PeriphCLKConfig+0x284>)
80050b4: 2201 movs r2, #1
80050b6: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
80050b8: f7fc fac2 bl 8001640 <HAL_GetTick>
80050bc: 6178 str r0, [r7, #20]
/* Wait till PLLSAI is ready */
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
80050be: e008 b.n 80050d2 <HAL_RCCEx_PeriphCLKConfig+0x21e>
{
if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
80050c0: f7fc fabe bl 8001640 <HAL_GetTick>
80050c4: 4602 mov r2, r0
80050c6: 697b ldr r3, [r7, #20]
80050c8: 1ad3 subs r3, r2, r3
80050ca: 2b02 cmp r3, #2
80050cc: d901 bls.n 80050d2 <HAL_RCCEx_PeriphCLKConfig+0x21e>
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
80050ce: 2303 movs r3, #3
80050d0: e0a4 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
while (__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
80050d2: 4b18 ldr r3, [pc, #96] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
80050d4: 681b ldr r3, [r3, #0]
80050d6: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
80050da: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80050de: d1ef bne.n 80050c0 <HAL_RCCEx_PeriphCLKConfig+0x20c>
}
}
/*--------------------------------------------------------------------------*/
/*---------------------------- RTC configuration ---------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
80050e0: 687b ldr r3, [r7, #4]
80050e2: 681b ldr r3, [r3, #0]
80050e4: f003 0320 and.w r3, r3, #32
80050e8: 2b00 cmp r3, #0
80050ea: f000 808b beq.w 8005204 <HAL_RCCEx_PeriphCLKConfig+0x350>
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
80050ee: 2300 movs r3, #0
80050f0: 60fb str r3, [r7, #12]
80050f2: 4b10 ldr r3, [pc, #64] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
80050f4: 6c1b ldr r3, [r3, #64] @ 0x40
80050f6: 4a0f ldr r2, [pc, #60] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
80050f8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80050fc: 6413 str r3, [r2, #64] @ 0x40
80050fe: 4b0d ldr r3, [pc, #52] @ (8005134 <HAL_RCCEx_PeriphCLKConfig+0x280>)
8005100: 6c1b ldr r3, [r3, #64] @ 0x40
8005102: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8005106: 60fb str r3, [r7, #12]
8005108: 68fb ldr r3, [r7, #12]
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
800510a: 4b0c ldr r3, [pc, #48] @ (800513c <HAL_RCCEx_PeriphCLKConfig+0x288>)
800510c: 681b ldr r3, [r3, #0]
800510e: 4a0b ldr r2, [pc, #44] @ (800513c <HAL_RCCEx_PeriphCLKConfig+0x288>)
8005110: f443 7380 orr.w r3, r3, #256 @ 0x100
8005114: 6013 str r3, [r2, #0]
/* Get tick */
tickstart = HAL_GetTick();
8005116: f7fc fa93 bl 8001640 <HAL_GetTick>
800511a: 6178 str r0, [r7, #20]
while ((PWR->CR & PWR_CR_DBP) == RESET)
800511c: e010 b.n 8005140 <HAL_RCCEx_PeriphCLKConfig+0x28c>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800511e: f7fc fa8f bl 8001640 <HAL_GetTick>
8005122: 4602 mov r2, r0
8005124: 697b ldr r3, [r7, #20]
8005126: 1ad3 subs r3, r2, r3
8005128: 2b02 cmp r3, #2
800512a: d909 bls.n 8005140 <HAL_RCCEx_PeriphCLKConfig+0x28c>
{
return HAL_TIMEOUT;
800512c: 2303 movs r3, #3
800512e: e075 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
8005130: 42470068 .word 0x42470068
8005134: 40023800 .word 0x40023800
8005138: 42470070 .word 0x42470070
800513c: 40007000 .word 0x40007000
while ((PWR->CR & PWR_CR_DBP) == RESET)
8005140: 4b38 ldr r3, [pc, #224] @ (8005224 <HAL_RCCEx_PeriphCLKConfig+0x370>)
8005142: 681b ldr r3, [r3, #0]
8005144: f403 7380 and.w r3, r3, #256 @ 0x100
8005148: 2b00 cmp r3, #0
800514a: d0e8 beq.n 800511e <HAL_RCCEx_PeriphCLKConfig+0x26a>
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
800514c: 4b36 ldr r3, [pc, #216] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
800514e: 6f1b ldr r3, [r3, #112] @ 0x70
8005150: f403 7340 and.w r3, r3, #768 @ 0x300
8005154: 613b str r3, [r7, #16]
if ((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8005156: 693b ldr r3, [r7, #16]
8005158: 2b00 cmp r3, #0
800515a: d02f beq.n 80051bc <HAL_RCCEx_PeriphCLKConfig+0x308>
800515c: 687b ldr r3, [r7, #4]
800515e: 6a9b ldr r3, [r3, #40] @ 0x28
8005160: f403 7340 and.w r3, r3, #768 @ 0x300
8005164: 693a ldr r2, [r7, #16]
8005166: 429a cmp r2, r3
8005168: d028 beq.n 80051bc <HAL_RCCEx_PeriphCLKConfig+0x308>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
800516a: 4b2f ldr r3, [pc, #188] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
800516c: 6f1b ldr r3, [r3, #112] @ 0x70
800516e: f423 7340 bic.w r3, r3, #768 @ 0x300
8005172: 613b str r3, [r7, #16]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8005174: 4b2d ldr r3, [pc, #180] @ (800522c <HAL_RCCEx_PeriphCLKConfig+0x378>)
8005176: 2201 movs r2, #1
8005178: 601a str r2, [r3, #0]
__HAL_RCC_BACKUPRESET_RELEASE();
800517a: 4b2c ldr r3, [pc, #176] @ (800522c <HAL_RCCEx_PeriphCLKConfig+0x378>)
800517c: 2200 movs r2, #0
800517e: 601a str r2, [r3, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg1;
8005180: 4a29 ldr r2, [pc, #164] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8005182: 693b ldr r3, [r7, #16]
8005184: 6713 str r3, [r2, #112] @ 0x70
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
8005186: 4b28 ldr r3, [pc, #160] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8005188: 6f1b ldr r3, [r3, #112] @ 0x70
800518a: f003 0301 and.w r3, r3, #1
800518e: 2b01 cmp r3, #1
8005190: d114 bne.n 80051bc <HAL_RCCEx_PeriphCLKConfig+0x308>
{
/* Get tick */
tickstart = HAL_GetTick();
8005192: f7fc fa55 bl 8001640 <HAL_GetTick>
8005196: 6178 str r0, [r7, #20]
/* Wait till LSE is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8005198: e00a b.n 80051b0 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800519a: f7fc fa51 bl 8001640 <HAL_GetTick>
800519e: 4602 mov r2, r0
80051a0: 697b ldr r3, [r7, #20]
80051a2: 1ad3 subs r3, r2, r3
80051a4: f241 3288 movw r2, #5000 @ 0x1388
80051a8: 4293 cmp r3, r2
80051aa: d901 bls.n 80051b0 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
return HAL_TIMEOUT;
80051ac: 2303 movs r3, #3
80051ae: e035 b.n 800521c <HAL_RCCEx_PeriphCLKConfig+0x368>
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80051b0: 4b1d ldr r3, [pc, #116] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051b2: 6f1b ldr r3, [r3, #112] @ 0x70
80051b4: f003 0302 and.w r3, r3, #2
80051b8: 2b00 cmp r3, #0
80051ba: d0ee beq.n 800519a <HAL_RCCEx_PeriphCLKConfig+0x2e6>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
80051bc: 687b ldr r3, [r7, #4]
80051be: 6a9b ldr r3, [r3, #40] @ 0x28
80051c0: f403 7340 and.w r3, r3, #768 @ 0x300
80051c4: f5b3 7f40 cmp.w r3, #768 @ 0x300
80051c8: d10d bne.n 80051e6 <HAL_RCCEx_PeriphCLKConfig+0x332>
80051ca: 4b17 ldr r3, [pc, #92] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051cc: 689b ldr r3, [r3, #8]
80051ce: f423 12f8 bic.w r2, r3, #2031616 @ 0x1f0000
80051d2: 687b ldr r3, [r7, #4]
80051d4: 6a9b ldr r3, [r3, #40] @ 0x28
80051d6: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
80051da: f423 7340 bic.w r3, r3, #768 @ 0x300
80051de: 4912 ldr r1, [pc, #72] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051e0: 4313 orrs r3, r2
80051e2: 608b str r3, [r1, #8]
80051e4: e005 b.n 80051f2 <HAL_RCCEx_PeriphCLKConfig+0x33e>
80051e6: 4b10 ldr r3, [pc, #64] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051e8: 689b ldr r3, [r3, #8]
80051ea: 4a0f ldr r2, [pc, #60] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051ec: f423 13f8 bic.w r3, r3, #2031616 @ 0x1f0000
80051f0: 6093 str r3, [r2, #8]
80051f2: 4b0d ldr r3, [pc, #52] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
80051f4: 6f1a ldr r2, [r3, #112] @ 0x70
80051f6: 687b ldr r3, [r7, #4]
80051f8: 6a9b ldr r3, [r3, #40] @ 0x28
80051fa: f3c3 030b ubfx r3, r3, #0, #12
80051fe: 490a ldr r1, [pc, #40] @ (8005228 <HAL_RCCEx_PeriphCLKConfig+0x374>)
8005200: 4313 orrs r3, r2
8005202: 670b str r3, [r1, #112] @ 0x70
}
/*--------------------------------------------------------------------------*/
/*---------------------------- TIM configuration ---------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
8005204: 687b ldr r3, [r7, #4]
8005206: 681b ldr r3, [r3, #0]
8005208: f003 0310 and.w r3, r3, #16
800520c: 2b00 cmp r3, #0
800520e: d004 beq.n 800521a <HAL_RCCEx_PeriphCLKConfig+0x366>
{
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8005210: 687b ldr r3, [r7, #4]
8005212: f893 202c ldrb.w r2, [r3, #44] @ 0x2c
8005216: 4b06 ldr r3, [pc, #24] @ (8005230 <HAL_RCCEx_PeriphCLKConfig+0x37c>)
8005218: 601a str r2, [r3, #0]
}
return HAL_OK;
800521a: 2300 movs r3, #0
}
800521c: 4618 mov r0, r3
800521e: 3718 adds r7, #24
8005220: 46bd mov sp, r7
8005222: bd80 pop {r7, pc}
8005224: 40007000 .word 0x40007000
8005228: 40023800 .word 0x40023800
800522c: 42470e40 .word 0x42470e40
8005230: 424711e0 .word 0x424711e0
08005234 <HAL_SDRAM_Init>:
* the configuration information for SDRAM module.
* @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
8005234: b580 push {r7, lr}
8005236: b082 sub sp, #8
8005238: af00 add r7, sp, #0
800523a: 6078 str r0, [r7, #4]
800523c: 6039 str r1, [r7, #0]
/* Check the SDRAM handle parameter */
if (hsdram == NULL)
800523e: 687b ldr r3, [r7, #4]
8005240: 2b00 cmp r3, #0
8005242: d101 bne.n 8005248 <HAL_SDRAM_Init+0x14>
{
return HAL_ERROR;
8005244: 2301 movs r3, #1
8005246: e025 b.n 8005294 <HAL_SDRAM_Init+0x60>
}
if (hsdram->State == HAL_SDRAM_STATE_RESET)
8005248: 687b ldr r3, [r7, #4]
800524a: f893 302c ldrb.w r3, [r3, #44] @ 0x2c
800524e: b2db uxtb r3, r3
8005250: 2b00 cmp r3, #0
8005252: d106 bne.n 8005262 <HAL_SDRAM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
8005254: 687b ldr r3, [r7, #4]
8005256: 2200 movs r2, #0
8005258: f883 202d strb.w r2, [r3, #45] @ 0x2d
/* Init the low level hardware */
hsdram->MspInitCallback(hsdram);
#else
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
800525c: 6878 ldr r0, [r7, #4]
800525e: f7fc f8b3 bl 80013c8 <HAL_SDRAM_MspInit>
#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
8005262: 687b ldr r3, [r7, #4]
8005264: 2202 movs r2, #2
8005266: f883 202c strb.w r2, [r3, #44] @ 0x2c
/* Initialize SDRAM control Interface */
(void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
800526a: 687b ldr r3, [r7, #4]
800526c: 681a ldr r2, [r3, #0]
800526e: 687b ldr r3, [r7, #4]
8005270: 3304 adds r3, #4
8005272: 4619 mov r1, r3
8005274: 4610 mov r0, r2
8005276: f000 ffcd bl 8006214 <FMC_SDRAM_Init>
/* Initialize SDRAM timing Interface */
(void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
800527a: 687b ldr r3, [r7, #4]
800527c: 6818 ldr r0, [r3, #0]
800527e: 687b ldr r3, [r7, #4]
8005280: 685b ldr r3, [r3, #4]
8005282: 461a mov r2, r3
8005284: 6839 ldr r1, [r7, #0]
8005286: f001 f822 bl 80062ce <FMC_SDRAM_Timing_Init>
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
800528a: 687b ldr r3, [r7, #4]
800528c: 2201 movs r2, #1
800528e: f883 202c strb.w r2, [r3, #44] @ 0x2c
return HAL_OK;
8005292: 2300 movs r3, #0
}
8005294: 4618 mov r0, r3
8005296: 3708 adds r7, #8
8005298: 46bd mov sp, r7
800529a: bd80 pop {r7, pc}
0800529c <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
800529c: b580 push {r7, lr}
800529e: b082 sub sp, #8
80052a0: af00 add r7, sp, #0
80052a2: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
80052a4: 687b ldr r3, [r7, #4]
80052a6: 2b00 cmp r3, #0
80052a8: d101 bne.n 80052ae <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
80052aa: 2301 movs r3, #1
80052ac: e07b b.n 80053a6 <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
80052ae: 687b ldr r3, [r7, #4]
80052b0: 6a5b ldr r3, [r3, #36] @ 0x24
80052b2: 2b00 cmp r3, #0
80052b4: d108 bne.n 80052c8 <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
80052b6: 687b ldr r3, [r7, #4]
80052b8: 685b ldr r3, [r3, #4]
80052ba: f5b3 7f82 cmp.w r3, #260 @ 0x104
80052be: d009 beq.n 80052d4 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80052c0: 687b ldr r3, [r7, #4]
80052c2: 2200 movs r2, #0
80052c4: 61da str r2, [r3, #28]
80052c6: e005 b.n 80052d4 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
80052c8: 687b ldr r3, [r7, #4]
80052ca: 2200 movs r2, #0
80052cc: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
80052ce: 687b ldr r3, [r7, #4]
80052d0: 2200 movs r2, #0
80052d2: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80052d4: 687b ldr r3, [r7, #4]
80052d6: 2200 movs r2, #0
80052d8: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
80052da: 687b ldr r3, [r7, #4]
80052dc: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
80052e0: b2db uxtb r3, r3
80052e2: 2b00 cmp r3, #0
80052e4: d106 bne.n 80052f4 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
80052e6: 687b ldr r3, [r7, #4]
80052e8: 2200 movs r2, #0
80052ea: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
80052ee: 6878 ldr r0, [r7, #4]
80052f0: f7fb ff26 bl 8001140 <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
80052f4: 687b ldr r3, [r7, #4]
80052f6: 2202 movs r2, #2
80052f8: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
80052fc: 687b ldr r3, [r7, #4]
80052fe: 681b ldr r3, [r3, #0]
8005300: 681a ldr r2, [r3, #0]
8005302: 687b ldr r3, [r7, #4]
8005304: 681b ldr r3, [r3, #0]
8005306: f022 0240 bic.w r2, r2, #64 @ 0x40
800530a: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
800530c: 687b ldr r3, [r7, #4]
800530e: 685b ldr r3, [r3, #4]
8005310: f403 7282 and.w r2, r3, #260 @ 0x104
8005314: 687b ldr r3, [r7, #4]
8005316: 689b ldr r3, [r3, #8]
8005318: f403 4304 and.w r3, r3, #33792 @ 0x8400
800531c: 431a orrs r2, r3
800531e: 687b ldr r3, [r7, #4]
8005320: 68db ldr r3, [r3, #12]
8005322: f403 6300 and.w r3, r3, #2048 @ 0x800
8005326: 431a orrs r2, r3
8005328: 687b ldr r3, [r7, #4]
800532a: 691b ldr r3, [r3, #16]
800532c: f003 0302 and.w r3, r3, #2
8005330: 431a orrs r2, r3
8005332: 687b ldr r3, [r7, #4]
8005334: 695b ldr r3, [r3, #20]
8005336: f003 0301 and.w r3, r3, #1
800533a: 431a orrs r2, r3
800533c: 687b ldr r3, [r7, #4]
800533e: 699b ldr r3, [r3, #24]
8005340: f403 7300 and.w r3, r3, #512 @ 0x200
8005344: 431a orrs r2, r3
8005346: 687b ldr r3, [r7, #4]
8005348: 69db ldr r3, [r3, #28]
800534a: f003 0338 and.w r3, r3, #56 @ 0x38
800534e: 431a orrs r2, r3
8005350: 687b ldr r3, [r7, #4]
8005352: 6a1b ldr r3, [r3, #32]
8005354: f003 0380 and.w r3, r3, #128 @ 0x80
8005358: ea42 0103 orr.w r1, r2, r3
800535c: 687b ldr r3, [r7, #4]
800535e: 6a9b ldr r3, [r3, #40] @ 0x28
8005360: f403 5200 and.w r2, r3, #8192 @ 0x2000
8005364: 687b ldr r3, [r7, #4]
8005366: 681b ldr r3, [r3, #0]
8005368: 430a orrs r2, r1
800536a: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
800536c: 687b ldr r3, [r7, #4]
800536e: 699b ldr r3, [r3, #24]
8005370: 0c1b lsrs r3, r3, #16
8005372: f003 0104 and.w r1, r3, #4
8005376: 687b ldr r3, [r7, #4]
8005378: 6a5b ldr r3, [r3, #36] @ 0x24
800537a: f003 0210 and.w r2, r3, #16
800537e: 687b ldr r3, [r7, #4]
8005380: 681b ldr r3, [r3, #0]
8005382: 430a orrs r2, r1
8005384: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
8005386: 687b ldr r3, [r7, #4]
8005388: 681b ldr r3, [r3, #0]
800538a: 69da ldr r2, [r3, #28]
800538c: 687b ldr r3, [r7, #4]
800538e: 681b ldr r3, [r3, #0]
8005390: f422 6200 bic.w r2, r2, #2048 @ 0x800
8005394: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
8005396: 687b ldr r3, [r7, #4]
8005398: 2200 movs r2, #0
800539a: 655a str r2, [r3, #84] @ 0x54
hspi->State = HAL_SPI_STATE_READY;
800539c: 687b ldr r3, [r7, #4]
800539e: 2201 movs r2, #1
80053a0: f883 2051 strb.w r2, [r3, #81] @ 0x51
return HAL_OK;
80053a4: 2300 movs r3, #0
}
80053a6: 4618 mov r0, r3
80053a8: 3708 adds r7, #8
80053aa: 46bd mov sp, r7
80053ac: bd80 pop {r7, pc}
080053ae <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80053ae: b580 push {r7, lr}
80053b0: b082 sub sp, #8
80053b2: af00 add r7, sp, #0
80053b4: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80053b6: 687b ldr r3, [r7, #4]
80053b8: 2b00 cmp r3, #0
80053ba: d101 bne.n 80053c0 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80053bc: 2301 movs r3, #1
80053be: e041 b.n 8005444 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80053c0: 687b ldr r3, [r7, #4]
80053c2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80053c6: b2db uxtb r3, r3
80053c8: 2b00 cmp r3, #0
80053ca: d106 bne.n 80053da <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80053cc: 687b ldr r3, [r7, #4]
80053ce: 2200 movs r2, #0
80053d0: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80053d4: 6878 ldr r0, [r7, #4]
80053d6: f7fb fefb bl 80011d0 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80053da: 687b ldr r3, [r7, #4]
80053dc: 2202 movs r2, #2
80053de: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80053e2: 687b ldr r3, [r7, #4]
80053e4: 681a ldr r2, [r3, #0]
80053e6: 687b ldr r3, [r7, #4]
80053e8: 3304 adds r3, #4
80053ea: 4619 mov r1, r3
80053ec: 4610 mov r0, r2
80053ee: f000 fa7d bl 80058ec <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80053f2: 687b ldr r3, [r7, #4]
80053f4: 2201 movs r2, #1
80053f6: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80053fa: 687b ldr r3, [r7, #4]
80053fc: 2201 movs r2, #1
80053fe: f883 203e strb.w r2, [r3, #62] @ 0x3e
8005402: 687b ldr r3, [r7, #4]
8005404: 2201 movs r2, #1
8005406: f883 203f strb.w r2, [r3, #63] @ 0x3f
800540a: 687b ldr r3, [r7, #4]
800540c: 2201 movs r2, #1
800540e: f883 2040 strb.w r2, [r3, #64] @ 0x40
8005412: 687b ldr r3, [r7, #4]
8005414: 2201 movs r2, #1
8005416: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
800541a: 687b ldr r3, [r7, #4]
800541c: 2201 movs r2, #1
800541e: f883 2042 strb.w r2, [r3, #66] @ 0x42
8005422: 687b ldr r3, [r7, #4]
8005424: 2201 movs r2, #1
8005426: f883 2043 strb.w r2, [r3, #67] @ 0x43
800542a: 687b ldr r3, [r7, #4]
800542c: 2201 movs r2, #1
800542e: f883 2044 strb.w r2, [r3, #68] @ 0x44
8005432: 687b ldr r3, [r7, #4]
8005434: 2201 movs r2, #1
8005436: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
800543a: 687b ldr r3, [r7, #4]
800543c: 2201 movs r2, #1
800543e: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8005442: 2300 movs r3, #0
}
8005444: 4618 mov r0, r3
8005446: 3708 adds r7, #8
8005448: 46bd mov sp, r7
800544a: bd80 pop {r7, pc}
0800544c <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
800544c: b480 push {r7}
800544e: b085 sub sp, #20
8005450: af00 add r7, sp, #0
8005452: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8005454: 687b ldr r3, [r7, #4]
8005456: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
800545a: b2db uxtb r3, r3
800545c: 2b01 cmp r3, #1
800545e: d001 beq.n 8005464 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8005460: 2301 movs r3, #1
8005462: e04e b.n 8005502 <HAL_TIM_Base_Start_IT+0xb6>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8005464: 687b ldr r3, [r7, #4]
8005466: 2202 movs r2, #2
8005468: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
800546c: 687b ldr r3, [r7, #4]
800546e: 681b ldr r3, [r3, #0]
8005470: 68da ldr r2, [r3, #12]
8005472: 687b ldr r3, [r7, #4]
8005474: 681b ldr r3, [r3, #0]
8005476: f042 0201 orr.w r2, r2, #1
800547a: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800547c: 687b ldr r3, [r7, #4]
800547e: 681b ldr r3, [r3, #0]
8005480: 4a23 ldr r2, [pc, #140] @ (8005510 <HAL_TIM_Base_Start_IT+0xc4>)
8005482: 4293 cmp r3, r2
8005484: d022 beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
8005486: 687b ldr r3, [r7, #4]
8005488: 681b ldr r3, [r3, #0]
800548a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800548e: d01d beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
8005490: 687b ldr r3, [r7, #4]
8005492: 681b ldr r3, [r3, #0]
8005494: 4a1f ldr r2, [pc, #124] @ (8005514 <HAL_TIM_Base_Start_IT+0xc8>)
8005496: 4293 cmp r3, r2
8005498: d018 beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
800549a: 687b ldr r3, [r7, #4]
800549c: 681b ldr r3, [r3, #0]
800549e: 4a1e ldr r2, [pc, #120] @ (8005518 <HAL_TIM_Base_Start_IT+0xcc>)
80054a0: 4293 cmp r3, r2
80054a2: d013 beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
80054a4: 687b ldr r3, [r7, #4]
80054a6: 681b ldr r3, [r3, #0]
80054a8: 4a1c ldr r2, [pc, #112] @ (800551c <HAL_TIM_Base_Start_IT+0xd0>)
80054aa: 4293 cmp r3, r2
80054ac: d00e beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
80054ae: 687b ldr r3, [r7, #4]
80054b0: 681b ldr r3, [r3, #0]
80054b2: 4a1b ldr r2, [pc, #108] @ (8005520 <HAL_TIM_Base_Start_IT+0xd4>)
80054b4: 4293 cmp r3, r2
80054b6: d009 beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
80054b8: 687b ldr r3, [r7, #4]
80054ba: 681b ldr r3, [r3, #0]
80054bc: 4a19 ldr r2, [pc, #100] @ (8005524 <HAL_TIM_Base_Start_IT+0xd8>)
80054be: 4293 cmp r3, r2
80054c0: d004 beq.n 80054cc <HAL_TIM_Base_Start_IT+0x80>
80054c2: 687b ldr r3, [r7, #4]
80054c4: 681b ldr r3, [r3, #0]
80054c6: 4a18 ldr r2, [pc, #96] @ (8005528 <HAL_TIM_Base_Start_IT+0xdc>)
80054c8: 4293 cmp r3, r2
80054ca: d111 bne.n 80054f0 <HAL_TIM_Base_Start_IT+0xa4>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80054cc: 687b ldr r3, [r7, #4]
80054ce: 681b ldr r3, [r3, #0]
80054d0: 689b ldr r3, [r3, #8]
80054d2: f003 0307 and.w r3, r3, #7
80054d6: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80054d8: 68fb ldr r3, [r7, #12]
80054da: 2b06 cmp r3, #6
80054dc: d010 beq.n 8005500 <HAL_TIM_Base_Start_IT+0xb4>
{
__HAL_TIM_ENABLE(htim);
80054de: 687b ldr r3, [r7, #4]
80054e0: 681b ldr r3, [r3, #0]
80054e2: 681a ldr r2, [r3, #0]
80054e4: 687b ldr r3, [r7, #4]
80054e6: 681b ldr r3, [r3, #0]
80054e8: f042 0201 orr.w r2, r2, #1
80054ec: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
80054ee: e007 b.n 8005500 <HAL_TIM_Base_Start_IT+0xb4>
}
}
else
{
__HAL_TIM_ENABLE(htim);
80054f0: 687b ldr r3, [r7, #4]
80054f2: 681b ldr r3, [r3, #0]
80054f4: 681a ldr r2, [r3, #0]
80054f6: 687b ldr r3, [r7, #4]
80054f8: 681b ldr r3, [r3, #0]
80054fa: f042 0201 orr.w r2, r2, #1
80054fe: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8005500: 2300 movs r3, #0
}
8005502: 4618 mov r0, r3
8005504: 3714 adds r7, #20
8005506: 46bd mov sp, r7
8005508: f85d 7b04 ldr.w r7, [sp], #4
800550c: 4770 bx lr
800550e: bf00 nop
8005510: 40010000 .word 0x40010000
8005514: 40000400 .word 0x40000400
8005518: 40000800 .word 0x40000800
800551c: 40000c00 .word 0x40000c00
8005520: 40010400 .word 0x40010400
8005524: 40014000 .word 0x40014000
8005528: 40001800 .word 0x40001800
0800552c <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
800552c: b580 push {r7, lr}
800552e: b084 sub sp, #16
8005530: af00 add r7, sp, #0
8005532: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8005534: 687b ldr r3, [r7, #4]
8005536: 681b ldr r3, [r3, #0]
8005538: 68db ldr r3, [r3, #12]
800553a: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800553c: 687b ldr r3, [r7, #4]
800553e: 681b ldr r3, [r3, #0]
8005540: 691b ldr r3, [r3, #16]
8005542: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8005544: 68bb ldr r3, [r7, #8]
8005546: f003 0302 and.w r3, r3, #2
800554a: 2b00 cmp r3, #0
800554c: d020 beq.n 8005590 <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800554e: 68fb ldr r3, [r7, #12]
8005550: f003 0302 and.w r3, r3, #2
8005554: 2b00 cmp r3, #0
8005556: d01b beq.n 8005590 <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8005558: 687b ldr r3, [r7, #4]
800555a: 681b ldr r3, [r3, #0]
800555c: f06f 0202 mvn.w r2, #2
8005560: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8005562: 687b ldr r3, [r7, #4]
8005564: 2201 movs r2, #1
8005566: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8005568: 687b ldr r3, [r7, #4]
800556a: 681b ldr r3, [r3, #0]
800556c: 699b ldr r3, [r3, #24]
800556e: f003 0303 and.w r3, r3, #3
8005572: 2b00 cmp r3, #0
8005574: d003 beq.n 800557e <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8005576: 6878 ldr r0, [r7, #4]
8005578: f000 f999 bl 80058ae <HAL_TIM_IC_CaptureCallback>
800557c: e005 b.n 800558a <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800557e: 6878 ldr r0, [r7, #4]
8005580: f000 f98b bl 800589a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005584: 6878 ldr r0, [r7, #4]
8005586: f000 f99c bl 80058c2 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800558a: 687b ldr r3, [r7, #4]
800558c: 2200 movs r2, #0
800558e: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8005590: 68bb ldr r3, [r7, #8]
8005592: f003 0304 and.w r3, r3, #4
8005596: 2b00 cmp r3, #0
8005598: d020 beq.n 80055dc <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
800559a: 68fb ldr r3, [r7, #12]
800559c: f003 0304 and.w r3, r3, #4
80055a0: 2b00 cmp r3, #0
80055a2: d01b beq.n 80055dc <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80055a4: 687b ldr r3, [r7, #4]
80055a6: 681b ldr r3, [r3, #0]
80055a8: f06f 0204 mvn.w r2, #4
80055ac: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80055ae: 687b ldr r3, [r7, #4]
80055b0: 2202 movs r2, #2
80055b2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80055b4: 687b ldr r3, [r7, #4]
80055b6: 681b ldr r3, [r3, #0]
80055b8: 699b ldr r3, [r3, #24]
80055ba: f403 7340 and.w r3, r3, #768 @ 0x300
80055be: 2b00 cmp r3, #0
80055c0: d003 beq.n 80055ca <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80055c2: 6878 ldr r0, [r7, #4]
80055c4: f000 f973 bl 80058ae <HAL_TIM_IC_CaptureCallback>
80055c8: e005 b.n 80055d6 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80055ca: 6878 ldr r0, [r7, #4]
80055cc: f000 f965 bl 800589a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80055d0: 6878 ldr r0, [r7, #4]
80055d2: f000 f976 bl 80058c2 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80055d6: 687b ldr r3, [r7, #4]
80055d8: 2200 movs r2, #0
80055da: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80055dc: 68bb ldr r3, [r7, #8]
80055de: f003 0308 and.w r3, r3, #8
80055e2: 2b00 cmp r3, #0
80055e4: d020 beq.n 8005628 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80055e6: 68fb ldr r3, [r7, #12]
80055e8: f003 0308 and.w r3, r3, #8
80055ec: 2b00 cmp r3, #0
80055ee: d01b beq.n 8005628 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80055f0: 687b ldr r3, [r7, #4]
80055f2: 681b ldr r3, [r3, #0]
80055f4: f06f 0208 mvn.w r2, #8
80055f8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
80055fa: 687b ldr r3, [r7, #4]
80055fc: 2204 movs r2, #4
80055fe: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8005600: 687b ldr r3, [r7, #4]
8005602: 681b ldr r3, [r3, #0]
8005604: 69db ldr r3, [r3, #28]
8005606: f003 0303 and.w r3, r3, #3
800560a: 2b00 cmp r3, #0
800560c: d003 beq.n 8005616 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800560e: 6878 ldr r0, [r7, #4]
8005610: f000 f94d bl 80058ae <HAL_TIM_IC_CaptureCallback>
8005614: e005 b.n 8005622 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005616: 6878 ldr r0, [r7, #4]
8005618: f000 f93f bl 800589a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800561c: 6878 ldr r0, [r7, #4]
800561e: f000 f950 bl 80058c2 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8005622: 687b ldr r3, [r7, #4]
8005624: 2200 movs r2, #0
8005626: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8005628: 68bb ldr r3, [r7, #8]
800562a: f003 0310 and.w r3, r3, #16
800562e: 2b00 cmp r3, #0
8005630: d020 beq.n 8005674 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8005632: 68fb ldr r3, [r7, #12]
8005634: f003 0310 and.w r3, r3, #16
8005638: 2b00 cmp r3, #0
800563a: d01b beq.n 8005674 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800563c: 687b ldr r3, [r7, #4]
800563e: 681b ldr r3, [r3, #0]
8005640: f06f 0210 mvn.w r2, #16
8005644: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8005646: 687b ldr r3, [r7, #4]
8005648: 2208 movs r2, #8
800564a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800564c: 687b ldr r3, [r7, #4]
800564e: 681b ldr r3, [r3, #0]
8005650: 69db ldr r3, [r3, #28]
8005652: f403 7340 and.w r3, r3, #768 @ 0x300
8005656: 2b00 cmp r3, #0
8005658: d003 beq.n 8005662 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800565a: 6878 ldr r0, [r7, #4]
800565c: f000 f927 bl 80058ae <HAL_TIM_IC_CaptureCallback>
8005660: e005 b.n 800566e <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8005662: 6878 ldr r0, [r7, #4]
8005664: f000 f919 bl 800589a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8005668: 6878 ldr r0, [r7, #4]
800566a: f000 f92a bl 80058c2 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800566e: 687b ldr r3, [r7, #4]
8005670: 2200 movs r2, #0
8005672: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8005674: 68bb ldr r3, [r7, #8]
8005676: f003 0301 and.w r3, r3, #1
800567a: 2b00 cmp r3, #0
800567c: d00c beq.n 8005698 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800567e: 68fb ldr r3, [r7, #12]
8005680: f003 0301 and.w r3, r3, #1
8005684: 2b00 cmp r3, #0
8005686: d007 beq.n 8005698 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8005688: 687b ldr r3, [r7, #4]
800568a: 681b ldr r3, [r3, #0]
800568c: f06f 0201 mvn.w r2, #1
8005690: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8005692: 6878 ldr r0, [r7, #4]
8005694: f7fb fb2c bl 8000cf0 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
8005698: 68bb ldr r3, [r7, #8]
800569a: f003 0380 and.w r3, r3, #128 @ 0x80
800569e: 2b00 cmp r3, #0
80056a0: d00c beq.n 80056bc <HAL_TIM_IRQHandler+0x190>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80056a2: 68fb ldr r3, [r7, #12]
80056a4: f003 0380 and.w r3, r3, #128 @ 0x80
80056a8: 2b00 cmp r3, #0
80056aa: d007 beq.n 80056bc <HAL_TIM_IRQHandler+0x190>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
80056ac: 687b ldr r3, [r7, #4]
80056ae: 681b ldr r3, [r3, #0]
80056b0: f06f 0280 mvn.w r2, #128 @ 0x80
80056b4: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80056b6: 6878 ldr r0, [r7, #4]
80056b8: f000 fade bl 8005c78 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80056bc: 68bb ldr r3, [r7, #8]
80056be: f003 0340 and.w r3, r3, #64 @ 0x40
80056c2: 2b00 cmp r3, #0
80056c4: d00c beq.n 80056e0 <HAL_TIM_IRQHandler+0x1b4>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80056c6: 68fb ldr r3, [r7, #12]
80056c8: f003 0340 and.w r3, r3, #64 @ 0x40
80056cc: 2b00 cmp r3, #0
80056ce: d007 beq.n 80056e0 <HAL_TIM_IRQHandler+0x1b4>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80056d0: 687b ldr r3, [r7, #4]
80056d2: 681b ldr r3, [r3, #0]
80056d4: f06f 0240 mvn.w r2, #64 @ 0x40
80056d8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80056da: 6878 ldr r0, [r7, #4]
80056dc: f000 f8fb bl 80058d6 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80056e0: 68bb ldr r3, [r7, #8]
80056e2: f003 0320 and.w r3, r3, #32
80056e6: 2b00 cmp r3, #0
80056e8: d00c beq.n 8005704 <HAL_TIM_IRQHandler+0x1d8>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80056ea: 68fb ldr r3, [r7, #12]
80056ec: f003 0320 and.w r3, r3, #32
80056f0: 2b00 cmp r3, #0
80056f2: d007 beq.n 8005704 <HAL_TIM_IRQHandler+0x1d8>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
80056f4: 687b ldr r3, [r7, #4]
80056f6: 681b ldr r3, [r3, #0]
80056f8: f06f 0220 mvn.w r2, #32
80056fc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
80056fe: 6878 ldr r0, [r7, #4]
8005700: f000 fab0 bl 8005c64 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8005704: bf00 nop
8005706: 3710 adds r7, #16
8005708: 46bd mov sp, r7
800570a: bd80 pop {r7, pc}
0800570c <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
800570c: b580 push {r7, lr}
800570e: b084 sub sp, #16
8005710: af00 add r7, sp, #0
8005712: 6078 str r0, [r7, #4]
8005714: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8005716: 2300 movs r3, #0
8005718: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
800571a: 687b ldr r3, [r7, #4]
800571c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005720: 2b01 cmp r3, #1
8005722: d101 bne.n 8005728 <HAL_TIM_ConfigClockSource+0x1c>
8005724: 2302 movs r3, #2
8005726: e0b4 b.n 8005892 <HAL_TIM_ConfigClockSource+0x186>
8005728: 687b ldr r3, [r7, #4]
800572a: 2201 movs r2, #1
800572c: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8005730: 687b ldr r3, [r7, #4]
8005732: 2202 movs r2, #2
8005734: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8005738: 687b ldr r3, [r7, #4]
800573a: 681b ldr r3, [r3, #0]
800573c: 689b ldr r3, [r3, #8]
800573e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8005740: 68bb ldr r3, [r7, #8]
8005742: f023 0377 bic.w r3, r3, #119 @ 0x77
8005746: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005748: 68bb ldr r3, [r7, #8]
800574a: f423 437f bic.w r3, r3, #65280 @ 0xff00
800574e: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8005750: 687b ldr r3, [r7, #4]
8005752: 681b ldr r3, [r3, #0]
8005754: 68ba ldr r2, [r7, #8]
8005756: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8005758: 683b ldr r3, [r7, #0]
800575a: 681b ldr r3, [r3, #0]
800575c: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005760: d03e beq.n 80057e0 <HAL_TIM_ConfigClockSource+0xd4>
8005762: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8005766: f200 8087 bhi.w 8005878 <HAL_TIM_ConfigClockSource+0x16c>
800576a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800576e: f000 8086 beq.w 800587e <HAL_TIM_ConfigClockSource+0x172>
8005772: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8005776: d87f bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
8005778: 2b70 cmp r3, #112 @ 0x70
800577a: d01a beq.n 80057b2 <HAL_TIM_ConfigClockSource+0xa6>
800577c: 2b70 cmp r3, #112 @ 0x70
800577e: d87b bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
8005780: 2b60 cmp r3, #96 @ 0x60
8005782: d050 beq.n 8005826 <HAL_TIM_ConfigClockSource+0x11a>
8005784: 2b60 cmp r3, #96 @ 0x60
8005786: d877 bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
8005788: 2b50 cmp r3, #80 @ 0x50
800578a: d03c beq.n 8005806 <HAL_TIM_ConfigClockSource+0xfa>
800578c: 2b50 cmp r3, #80 @ 0x50
800578e: d873 bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
8005790: 2b40 cmp r3, #64 @ 0x40
8005792: d058 beq.n 8005846 <HAL_TIM_ConfigClockSource+0x13a>
8005794: 2b40 cmp r3, #64 @ 0x40
8005796: d86f bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
8005798: 2b30 cmp r3, #48 @ 0x30
800579a: d064 beq.n 8005866 <HAL_TIM_ConfigClockSource+0x15a>
800579c: 2b30 cmp r3, #48 @ 0x30
800579e: d86b bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
80057a0: 2b20 cmp r3, #32
80057a2: d060 beq.n 8005866 <HAL_TIM_ConfigClockSource+0x15a>
80057a4: 2b20 cmp r3, #32
80057a6: d867 bhi.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
80057a8: 2b00 cmp r3, #0
80057aa: d05c beq.n 8005866 <HAL_TIM_ConfigClockSource+0x15a>
80057ac: 2b10 cmp r3, #16
80057ae: d05a beq.n 8005866 <HAL_TIM_ConfigClockSource+0x15a>
80057b0: e062 b.n 8005878 <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80057b2: 687b ldr r3, [r7, #4]
80057b4: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80057b6: 683b ldr r3, [r7, #0]
80057b8: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80057ba: 683b ldr r3, [r7, #0]
80057bc: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80057be: 683b ldr r3, [r7, #0]
80057c0: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80057c2: f000 f9b3 bl 8005b2c <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
80057c6: 687b ldr r3, [r7, #4]
80057c8: 681b ldr r3, [r3, #0]
80057ca: 689b ldr r3, [r3, #8]
80057cc: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80057ce: 68bb ldr r3, [r7, #8]
80057d0: f043 0377 orr.w r3, r3, #119 @ 0x77
80057d4: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80057d6: 687b ldr r3, [r7, #4]
80057d8: 681b ldr r3, [r3, #0]
80057da: 68ba ldr r2, [r7, #8]
80057dc: 609a str r2, [r3, #8]
break;
80057de: e04f b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
80057e0: 687b ldr r3, [r7, #4]
80057e2: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
80057e4: 683b ldr r3, [r7, #0]
80057e6: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
80057e8: 683b ldr r3, [r7, #0]
80057ea: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
80057ec: 683b ldr r3, [r7, #0]
80057ee: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
80057f0: f000 f99c bl 8005b2c <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
80057f4: 687b ldr r3, [r7, #4]
80057f6: 681b ldr r3, [r3, #0]
80057f8: 689a ldr r2, [r3, #8]
80057fa: 687b ldr r3, [r7, #4]
80057fc: 681b ldr r3, [r3, #0]
80057fe: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8005802: 609a str r2, [r3, #8]
break;
8005804: e03c b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005806: 687b ldr r3, [r7, #4]
8005808: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800580a: 683b ldr r3, [r7, #0]
800580c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800580e: 683b ldr r3, [r7, #0]
8005810: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005812: 461a mov r2, r3
8005814: f000 f910 bl 8005a38 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8005818: 687b ldr r3, [r7, #4]
800581a: 681b ldr r3, [r3, #0]
800581c: 2150 movs r1, #80 @ 0x50
800581e: 4618 mov r0, r3
8005820: f000 f969 bl 8005af6 <TIM_ITRx_SetConfig>
break;
8005824: e02c b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8005826: 687b ldr r3, [r7, #4]
8005828: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800582a: 683b ldr r3, [r7, #0]
800582c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800582e: 683b ldr r3, [r7, #0]
8005830: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8005832: 461a mov r2, r3
8005834: f000 f92f bl 8005a96 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8005838: 687b ldr r3, [r7, #4]
800583a: 681b ldr r3, [r3, #0]
800583c: 2160 movs r1, #96 @ 0x60
800583e: 4618 mov r0, r3
8005840: f000 f959 bl 8005af6 <TIM_ITRx_SetConfig>
break;
8005844: e01c b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8005846: 687b ldr r3, [r7, #4]
8005848: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
800584a: 683b ldr r3, [r7, #0]
800584c: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
800584e: 683b ldr r3, [r7, #0]
8005850: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8005852: 461a mov r2, r3
8005854: f000 f8f0 bl 8005a38 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8005858: 687b ldr r3, [r7, #4]
800585a: 681b ldr r3, [r3, #0]
800585c: 2140 movs r1, #64 @ 0x40
800585e: 4618 mov r0, r3
8005860: f000 f949 bl 8005af6 <TIM_ITRx_SetConfig>
break;
8005864: e00c b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8005866: 687b ldr r3, [r7, #4]
8005868: 681a ldr r2, [r3, #0]
800586a: 683b ldr r3, [r7, #0]
800586c: 681b ldr r3, [r3, #0]
800586e: 4619 mov r1, r3
8005870: 4610 mov r0, r2
8005872: f000 f940 bl 8005af6 <TIM_ITRx_SetConfig>
break;
8005876: e003 b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8005878: 2301 movs r3, #1
800587a: 73fb strb r3, [r7, #15]
break;
800587c: e000 b.n 8005880 <HAL_TIM_ConfigClockSource+0x174>
break;
800587e: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8005880: 687b ldr r3, [r7, #4]
8005882: 2201 movs r2, #1
8005884: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005888: 687b ldr r3, [r7, #4]
800588a: 2200 movs r2, #0
800588c: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8005890: 7bfb ldrb r3, [r7, #15]
}
8005892: 4618 mov r0, r3
8005894: 3710 adds r7, #16
8005896: 46bd mov sp, r7
8005898: bd80 pop {r7, pc}
0800589a <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
800589a: b480 push {r7}
800589c: b083 sub sp, #12
800589e: af00 add r7, sp, #0
80058a0: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
80058a2: bf00 nop
80058a4: 370c adds r7, #12
80058a6: 46bd mov sp, r7
80058a8: f85d 7b04 ldr.w r7, [sp], #4
80058ac: 4770 bx lr
080058ae <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
80058ae: b480 push {r7}
80058b0: b083 sub sp, #12
80058b2: af00 add r7, sp, #0
80058b4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
80058b6: bf00 nop
80058b8: 370c adds r7, #12
80058ba: 46bd mov sp, r7
80058bc: f85d 7b04 ldr.w r7, [sp], #4
80058c0: 4770 bx lr
080058c2 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
80058c2: b480 push {r7}
80058c4: b083 sub sp, #12
80058c6: af00 add r7, sp, #0
80058c8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
80058ca: bf00 nop
80058cc: 370c adds r7, #12
80058ce: 46bd mov sp, r7
80058d0: f85d 7b04 ldr.w r7, [sp], #4
80058d4: 4770 bx lr
080058d6 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
80058d6: b480 push {r7}
80058d8: b083 sub sp, #12
80058da: af00 add r7, sp, #0
80058dc: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
80058de: bf00 nop
80058e0: 370c adds r7, #12
80058e2: 46bd mov sp, r7
80058e4: f85d 7b04 ldr.w r7, [sp], #4
80058e8: 4770 bx lr
...
080058ec <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
80058ec: b480 push {r7}
80058ee: b085 sub sp, #20
80058f0: af00 add r7, sp, #0
80058f2: 6078 str r0, [r7, #4]
80058f4: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
80058f6: 687b ldr r3, [r7, #4]
80058f8: 681b ldr r3, [r3, #0]
80058fa: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80058fc: 687b ldr r3, [r7, #4]
80058fe: 4a43 ldr r2, [pc, #268] @ (8005a0c <TIM_Base_SetConfig+0x120>)
8005900: 4293 cmp r3, r2
8005902: d013 beq.n 800592c <TIM_Base_SetConfig+0x40>
8005904: 687b ldr r3, [r7, #4]
8005906: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800590a: d00f beq.n 800592c <TIM_Base_SetConfig+0x40>
800590c: 687b ldr r3, [r7, #4]
800590e: 4a40 ldr r2, [pc, #256] @ (8005a10 <TIM_Base_SetConfig+0x124>)
8005910: 4293 cmp r3, r2
8005912: d00b beq.n 800592c <TIM_Base_SetConfig+0x40>
8005914: 687b ldr r3, [r7, #4]
8005916: 4a3f ldr r2, [pc, #252] @ (8005a14 <TIM_Base_SetConfig+0x128>)
8005918: 4293 cmp r3, r2
800591a: d007 beq.n 800592c <TIM_Base_SetConfig+0x40>
800591c: 687b ldr r3, [r7, #4]
800591e: 4a3e ldr r2, [pc, #248] @ (8005a18 <TIM_Base_SetConfig+0x12c>)
8005920: 4293 cmp r3, r2
8005922: d003 beq.n 800592c <TIM_Base_SetConfig+0x40>
8005924: 687b ldr r3, [r7, #4]
8005926: 4a3d ldr r2, [pc, #244] @ (8005a1c <TIM_Base_SetConfig+0x130>)
8005928: 4293 cmp r3, r2
800592a: d108 bne.n 800593e <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
800592c: 68fb ldr r3, [r7, #12]
800592e: f023 0370 bic.w r3, r3, #112 @ 0x70
8005932: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8005934: 683b ldr r3, [r7, #0]
8005936: 685b ldr r3, [r3, #4]
8005938: 68fa ldr r2, [r7, #12]
800593a: 4313 orrs r3, r2
800593c: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800593e: 687b ldr r3, [r7, #4]
8005940: 4a32 ldr r2, [pc, #200] @ (8005a0c <TIM_Base_SetConfig+0x120>)
8005942: 4293 cmp r3, r2
8005944: d02b beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005946: 687b ldr r3, [r7, #4]
8005948: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800594c: d027 beq.n 800599e <TIM_Base_SetConfig+0xb2>
800594e: 687b ldr r3, [r7, #4]
8005950: 4a2f ldr r2, [pc, #188] @ (8005a10 <TIM_Base_SetConfig+0x124>)
8005952: 4293 cmp r3, r2
8005954: d023 beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005956: 687b ldr r3, [r7, #4]
8005958: 4a2e ldr r2, [pc, #184] @ (8005a14 <TIM_Base_SetConfig+0x128>)
800595a: 4293 cmp r3, r2
800595c: d01f beq.n 800599e <TIM_Base_SetConfig+0xb2>
800595e: 687b ldr r3, [r7, #4]
8005960: 4a2d ldr r2, [pc, #180] @ (8005a18 <TIM_Base_SetConfig+0x12c>)
8005962: 4293 cmp r3, r2
8005964: d01b beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005966: 687b ldr r3, [r7, #4]
8005968: 4a2c ldr r2, [pc, #176] @ (8005a1c <TIM_Base_SetConfig+0x130>)
800596a: 4293 cmp r3, r2
800596c: d017 beq.n 800599e <TIM_Base_SetConfig+0xb2>
800596e: 687b ldr r3, [r7, #4]
8005970: 4a2b ldr r2, [pc, #172] @ (8005a20 <TIM_Base_SetConfig+0x134>)
8005972: 4293 cmp r3, r2
8005974: d013 beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005976: 687b ldr r3, [r7, #4]
8005978: 4a2a ldr r2, [pc, #168] @ (8005a24 <TIM_Base_SetConfig+0x138>)
800597a: 4293 cmp r3, r2
800597c: d00f beq.n 800599e <TIM_Base_SetConfig+0xb2>
800597e: 687b ldr r3, [r7, #4]
8005980: 4a29 ldr r2, [pc, #164] @ (8005a28 <TIM_Base_SetConfig+0x13c>)
8005982: 4293 cmp r3, r2
8005984: d00b beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005986: 687b ldr r3, [r7, #4]
8005988: 4a28 ldr r2, [pc, #160] @ (8005a2c <TIM_Base_SetConfig+0x140>)
800598a: 4293 cmp r3, r2
800598c: d007 beq.n 800599e <TIM_Base_SetConfig+0xb2>
800598e: 687b ldr r3, [r7, #4]
8005990: 4a27 ldr r2, [pc, #156] @ (8005a30 <TIM_Base_SetConfig+0x144>)
8005992: 4293 cmp r3, r2
8005994: d003 beq.n 800599e <TIM_Base_SetConfig+0xb2>
8005996: 687b ldr r3, [r7, #4]
8005998: 4a26 ldr r2, [pc, #152] @ (8005a34 <TIM_Base_SetConfig+0x148>)
800599a: 4293 cmp r3, r2
800599c: d108 bne.n 80059b0 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
800599e: 68fb ldr r3, [r7, #12]
80059a0: f423 7340 bic.w r3, r3, #768 @ 0x300
80059a4: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
80059a6: 683b ldr r3, [r7, #0]
80059a8: 68db ldr r3, [r3, #12]
80059aa: 68fa ldr r2, [r7, #12]
80059ac: 4313 orrs r3, r2
80059ae: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
80059b0: 68fb ldr r3, [r7, #12]
80059b2: f023 0280 bic.w r2, r3, #128 @ 0x80
80059b6: 683b ldr r3, [r7, #0]
80059b8: 695b ldr r3, [r3, #20]
80059ba: 4313 orrs r3, r2
80059bc: 60fb str r3, [r7, #12]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
80059be: 683b ldr r3, [r7, #0]
80059c0: 689a ldr r2, [r3, #8]
80059c2: 687b ldr r3, [r7, #4]
80059c4: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
80059c6: 683b ldr r3, [r7, #0]
80059c8: 681a ldr r2, [r3, #0]
80059ca: 687b ldr r3, [r7, #4]
80059cc: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
80059ce: 687b ldr r3, [r7, #4]
80059d0: 4a0e ldr r2, [pc, #56] @ (8005a0c <TIM_Base_SetConfig+0x120>)
80059d2: 4293 cmp r3, r2
80059d4: d003 beq.n 80059de <TIM_Base_SetConfig+0xf2>
80059d6: 687b ldr r3, [r7, #4]
80059d8: 4a10 ldr r2, [pc, #64] @ (8005a1c <TIM_Base_SetConfig+0x130>)
80059da: 4293 cmp r3, r2
80059dc: d103 bne.n 80059e6 <TIM_Base_SetConfig+0xfa>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
80059de: 683b ldr r3, [r7, #0]
80059e0: 691a ldr r2, [r3, #16]
80059e2: 687b ldr r3, [r7, #4]
80059e4: 631a str r2, [r3, #48] @ 0x30
}
/* Disable Update Event (UEV) with Update Generation (UG)
by changing Update Request Source (URS) to avoid Update flag (UIF) */
SET_BIT(TIMx->CR1, TIM_CR1_URS);
80059e6: 687b ldr r3, [r7, #4]
80059e8: 681b ldr r3, [r3, #0]
80059ea: f043 0204 orr.w r2, r3, #4
80059ee: 687b ldr r3, [r7, #4]
80059f0: 601a str r2, [r3, #0]
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
80059f2: 687b ldr r3, [r7, #4]
80059f4: 2201 movs r2, #1
80059f6: 615a str r2, [r3, #20]
TIMx->CR1 = tmpcr1;
80059f8: 687b ldr r3, [r7, #4]
80059fa: 68fa ldr r2, [r7, #12]
80059fc: 601a str r2, [r3, #0]
}
80059fe: bf00 nop
8005a00: 3714 adds r7, #20
8005a02: 46bd mov sp, r7
8005a04: f85d 7b04 ldr.w r7, [sp], #4
8005a08: 4770 bx lr
8005a0a: bf00 nop
8005a0c: 40010000 .word 0x40010000
8005a10: 40000400 .word 0x40000400
8005a14: 40000800 .word 0x40000800
8005a18: 40000c00 .word 0x40000c00
8005a1c: 40010400 .word 0x40010400
8005a20: 40014000 .word 0x40014000
8005a24: 40014400 .word 0x40014400
8005a28: 40014800 .word 0x40014800
8005a2c: 40001800 .word 0x40001800
8005a30: 40001c00 .word 0x40001c00
8005a34: 40002000 .word 0x40002000
08005a38 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005a38: b480 push {r7}
8005a3a: b087 sub sp, #28
8005a3c: af00 add r7, sp, #0
8005a3e: 60f8 str r0, [r7, #12]
8005a40: 60b9 str r1, [r7, #8]
8005a42: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8005a44: 68fb ldr r3, [r7, #12]
8005a46: 6a1b ldr r3, [r3, #32]
8005a48: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8005a4a: 68fb ldr r3, [r7, #12]
8005a4c: 6a1b ldr r3, [r3, #32]
8005a4e: f023 0201 bic.w r2, r3, #1
8005a52: 68fb ldr r3, [r7, #12]
8005a54: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005a56: 68fb ldr r3, [r7, #12]
8005a58: 699b ldr r3, [r3, #24]
8005a5a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8005a5c: 693b ldr r3, [r7, #16]
8005a5e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8005a62: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8005a64: 687b ldr r3, [r7, #4]
8005a66: 011b lsls r3, r3, #4
8005a68: 693a ldr r2, [r7, #16]
8005a6a: 4313 orrs r3, r2
8005a6c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8005a6e: 697b ldr r3, [r7, #20]
8005a70: f023 030a bic.w r3, r3, #10
8005a74: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8005a76: 697a ldr r2, [r7, #20]
8005a78: 68bb ldr r3, [r7, #8]
8005a7a: 4313 orrs r3, r2
8005a7c: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8005a7e: 68fb ldr r3, [r7, #12]
8005a80: 693a ldr r2, [r7, #16]
8005a82: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005a84: 68fb ldr r3, [r7, #12]
8005a86: 697a ldr r2, [r7, #20]
8005a88: 621a str r2, [r3, #32]
}
8005a8a: bf00 nop
8005a8c: 371c adds r7, #28
8005a8e: 46bd mov sp, r7
8005a90: f85d 7b04 ldr.w r7, [sp], #4
8005a94: 4770 bx lr
08005a96 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005a96: b480 push {r7}
8005a98: b087 sub sp, #28
8005a9a: af00 add r7, sp, #0
8005a9c: 60f8 str r0, [r7, #12]
8005a9e: 60b9 str r1, [r7, #8]
8005aa0: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8005aa2: 68fb ldr r3, [r7, #12]
8005aa4: 6a1b ldr r3, [r3, #32]
8005aa6: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8005aa8: 68fb ldr r3, [r7, #12]
8005aaa: 6a1b ldr r3, [r3, #32]
8005aac: f023 0210 bic.w r2, r3, #16
8005ab0: 68fb ldr r3, [r7, #12]
8005ab2: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005ab4: 68fb ldr r3, [r7, #12]
8005ab6: 699b ldr r3, [r3, #24]
8005ab8: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8005aba: 693b ldr r3, [r7, #16]
8005abc: f423 4370 bic.w r3, r3, #61440 @ 0xf000
8005ac0: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
8005ac2: 687b ldr r3, [r7, #4]
8005ac4: 031b lsls r3, r3, #12
8005ac6: 693a ldr r2, [r7, #16]
8005ac8: 4313 orrs r3, r2
8005aca: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8005acc: 697b ldr r3, [r7, #20]
8005ace: f023 03a0 bic.w r3, r3, #160 @ 0xa0
8005ad2: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
8005ad4: 68bb ldr r3, [r7, #8]
8005ad6: 011b lsls r3, r3, #4
8005ad8: 697a ldr r2, [r7, #20]
8005ada: 4313 orrs r3, r2
8005adc: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8005ade: 68fb ldr r3, [r7, #12]
8005ae0: 693a ldr r2, [r7, #16]
8005ae2: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005ae4: 68fb ldr r3, [r7, #12]
8005ae6: 697a ldr r2, [r7, #20]
8005ae8: 621a str r2, [r3, #32]
}
8005aea: bf00 nop
8005aec: 371c adds r7, #28
8005aee: 46bd mov sp, r7
8005af0: f85d 7b04 ldr.w r7, [sp], #4
8005af4: 4770 bx lr
08005af6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
8005af6: b480 push {r7}
8005af8: b085 sub sp, #20
8005afa: af00 add r7, sp, #0
8005afc: 6078 str r0, [r7, #4]
8005afe: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8005b00: 687b ldr r3, [r7, #4]
8005b02: 689b ldr r3, [r3, #8]
8005b04: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8005b06: 68fb ldr r3, [r7, #12]
8005b08: f023 0370 bic.w r3, r3, #112 @ 0x70
8005b0c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8005b0e: 683a ldr r2, [r7, #0]
8005b10: 68fb ldr r3, [r7, #12]
8005b12: 4313 orrs r3, r2
8005b14: f043 0307 orr.w r3, r3, #7
8005b18: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005b1a: 687b ldr r3, [r7, #4]
8005b1c: 68fa ldr r2, [r7, #12]
8005b1e: 609a str r2, [r3, #8]
}
8005b20: bf00 nop
8005b22: 3714 adds r7, #20
8005b24: 46bd mov sp, r7
8005b26: f85d 7b04 ldr.w r7, [sp], #4
8005b2a: 4770 bx lr
08005b2c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8005b2c: b480 push {r7}
8005b2e: b087 sub sp, #28
8005b30: af00 add r7, sp, #0
8005b32: 60f8 str r0, [r7, #12]
8005b34: 60b9 str r1, [r7, #8]
8005b36: 607a str r2, [r7, #4]
8005b38: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8005b3a: 68fb ldr r3, [r7, #12]
8005b3c: 689b ldr r3, [r3, #8]
8005b3e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005b40: 697b ldr r3, [r7, #20]
8005b42: f423 437f bic.w r3, r3, #65280 @ 0xff00
8005b46: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8005b48: 683b ldr r3, [r7, #0]
8005b4a: 021a lsls r2, r3, #8
8005b4c: 687b ldr r3, [r7, #4]
8005b4e: 431a orrs r2, r3
8005b50: 68bb ldr r3, [r7, #8]
8005b52: 4313 orrs r3, r2
8005b54: 697a ldr r2, [r7, #20]
8005b56: 4313 orrs r3, r2
8005b58: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8005b5a: 68fb ldr r3, [r7, #12]
8005b5c: 697a ldr r2, [r7, #20]
8005b5e: 609a str r2, [r3, #8]
}
8005b60: bf00 nop
8005b62: 371c adds r7, #28
8005b64: 46bd mov sp, r7
8005b66: f85d 7b04 ldr.w r7, [sp], #4
8005b6a: 4770 bx lr
08005b6c <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8005b6c: b480 push {r7}
8005b6e: b085 sub sp, #20
8005b70: af00 add r7, sp, #0
8005b72: 6078 str r0, [r7, #4]
8005b74: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005b76: 687b ldr r3, [r7, #4]
8005b78: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005b7c: 2b01 cmp r3, #1
8005b7e: d101 bne.n 8005b84 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8005b80: 2302 movs r3, #2
8005b82: e05a b.n 8005c3a <HAL_TIMEx_MasterConfigSynchronization+0xce>
8005b84: 687b ldr r3, [r7, #4]
8005b86: 2201 movs r2, #1
8005b88: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8005b8c: 687b ldr r3, [r7, #4]
8005b8e: 2202 movs r2, #2
8005b90: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005b94: 687b ldr r3, [r7, #4]
8005b96: 681b ldr r3, [r3, #0]
8005b98: 685b ldr r3, [r3, #4]
8005b9a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8005b9c: 687b ldr r3, [r7, #4]
8005b9e: 681b ldr r3, [r3, #0]
8005ba0: 689b ldr r3, [r3, #8]
8005ba2: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8005ba4: 68fb ldr r3, [r7, #12]
8005ba6: f023 0370 bic.w r3, r3, #112 @ 0x70
8005baa: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8005bac: 683b ldr r3, [r7, #0]
8005bae: 681b ldr r3, [r3, #0]
8005bb0: 68fa ldr r2, [r7, #12]
8005bb2: 4313 orrs r3, r2
8005bb4: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8005bb6: 687b ldr r3, [r7, #4]
8005bb8: 681b ldr r3, [r3, #0]
8005bba: 68fa ldr r2, [r7, #12]
8005bbc: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8005bbe: 687b ldr r3, [r7, #4]
8005bc0: 681b ldr r3, [r3, #0]
8005bc2: 4a21 ldr r2, [pc, #132] @ (8005c48 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
8005bc4: 4293 cmp r3, r2
8005bc6: d022 beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005bc8: 687b ldr r3, [r7, #4]
8005bca: 681b ldr r3, [r3, #0]
8005bcc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8005bd0: d01d beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005bd2: 687b ldr r3, [r7, #4]
8005bd4: 681b ldr r3, [r3, #0]
8005bd6: 4a1d ldr r2, [pc, #116] @ (8005c4c <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
8005bd8: 4293 cmp r3, r2
8005bda: d018 beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005bdc: 687b ldr r3, [r7, #4]
8005bde: 681b ldr r3, [r3, #0]
8005be0: 4a1b ldr r2, [pc, #108] @ (8005c50 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
8005be2: 4293 cmp r3, r2
8005be4: d013 beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005be6: 687b ldr r3, [r7, #4]
8005be8: 681b ldr r3, [r3, #0]
8005bea: 4a1a ldr r2, [pc, #104] @ (8005c54 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
8005bec: 4293 cmp r3, r2
8005bee: d00e beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005bf0: 687b ldr r3, [r7, #4]
8005bf2: 681b ldr r3, [r3, #0]
8005bf4: 4a18 ldr r2, [pc, #96] @ (8005c58 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
8005bf6: 4293 cmp r3, r2
8005bf8: d009 beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005bfa: 687b ldr r3, [r7, #4]
8005bfc: 681b ldr r3, [r3, #0]
8005bfe: 4a17 ldr r2, [pc, #92] @ (8005c5c <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8005c00: 4293 cmp r3, r2
8005c02: d004 beq.n 8005c0e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005c04: 687b ldr r3, [r7, #4]
8005c06: 681b ldr r3, [r3, #0]
8005c08: 4a15 ldr r2, [pc, #84] @ (8005c60 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
8005c0a: 4293 cmp r3, r2
8005c0c: d10c bne.n 8005c28 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8005c0e: 68bb ldr r3, [r7, #8]
8005c10: f023 0380 bic.w r3, r3, #128 @ 0x80
8005c14: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005c16: 683b ldr r3, [r7, #0]
8005c18: 685b ldr r3, [r3, #4]
8005c1a: 68ba ldr r2, [r7, #8]
8005c1c: 4313 orrs r3, r2
8005c1e: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005c20: 687b ldr r3, [r7, #4]
8005c22: 681b ldr r3, [r3, #0]
8005c24: 68ba ldr r2, [r7, #8]
8005c26: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005c28: 687b ldr r3, [r7, #4]
8005c2a: 2201 movs r2, #1
8005c2c: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005c30: 687b ldr r3, [r7, #4]
8005c32: 2200 movs r2, #0
8005c34: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005c38: 2300 movs r3, #0
}
8005c3a: 4618 mov r0, r3
8005c3c: 3714 adds r7, #20
8005c3e: 46bd mov sp, r7
8005c40: f85d 7b04 ldr.w r7, [sp], #4
8005c44: 4770 bx lr
8005c46: bf00 nop
8005c48: 40010000 .word 0x40010000
8005c4c: 40000400 .word 0x40000400
8005c50: 40000800 .word 0x40000800
8005c54: 40000c00 .word 0x40000c00
8005c58: 40010400 .word 0x40010400
8005c5c: 40014000 .word 0x40014000
8005c60: 40001800 .word 0x40001800
08005c64 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8005c64: b480 push {r7}
8005c66: b083 sub sp, #12
8005c68: af00 add r7, sp, #0
8005c6a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8005c6c: bf00 nop
8005c6e: 370c adds r7, #12
8005c70: 46bd mov sp, r7
8005c72: f85d 7b04 ldr.w r7, [sp], #4
8005c76: 4770 bx lr
08005c78 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8005c78: b480 push {r7}
8005c7a: b083 sub sp, #12
8005c7c: af00 add r7, sp, #0
8005c7e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8005c80: bf00 nop
8005c82: 370c adds r7, #12
8005c84: 46bd mov sp, r7
8005c86: f85d 7b04 ldr.w r7, [sp], #4
8005c8a: 4770 bx lr
08005c8c <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005c8c: b580 push {r7, lr}
8005c8e: b082 sub sp, #8
8005c90: af00 add r7, sp, #0
8005c92: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005c94: 687b ldr r3, [r7, #4]
8005c96: 2b00 cmp r3, #0
8005c98: d101 bne.n 8005c9e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8005c9a: 2301 movs r3, #1
8005c9c: e042 b.n 8005d24 <HAL_UART_Init+0x98>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8005c9e: 687b ldr r3, [r7, #4]
8005ca0: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005ca4: b2db uxtb r3, r3
8005ca6: 2b00 cmp r3, #0
8005ca8: d106 bne.n 8005cb8 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8005caa: 687b ldr r3, [r7, #4]
8005cac: 2200 movs r2, #0
8005cae: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005cb2: 6878 ldr r0, [r7, #4]
8005cb4: f7fb faae bl 8001214 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8005cb8: 687b ldr r3, [r7, #4]
8005cba: 2224 movs r2, #36 @ 0x24
8005cbc: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8005cc0: 687b ldr r3, [r7, #4]
8005cc2: 681b ldr r3, [r3, #0]
8005cc4: 68da ldr r2, [r3, #12]
8005cc6: 687b ldr r3, [r7, #4]
8005cc8: 681b ldr r3, [r3, #0]
8005cca: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8005cce: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8005cd0: 6878 ldr r0, [r7, #4]
8005cd2: f000 f82b bl 8005d2c <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8005cd6: 687b ldr r3, [r7, #4]
8005cd8: 681b ldr r3, [r3, #0]
8005cda: 691a ldr r2, [r3, #16]
8005cdc: 687b ldr r3, [r7, #4]
8005cde: 681b ldr r3, [r3, #0]
8005ce0: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005ce4: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8005ce6: 687b ldr r3, [r7, #4]
8005ce8: 681b ldr r3, [r3, #0]
8005cea: 695a ldr r2, [r3, #20]
8005cec: 687b ldr r3, [r7, #4]
8005cee: 681b ldr r3, [r3, #0]
8005cf0: f022 022a bic.w r2, r2, #42 @ 0x2a
8005cf4: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8005cf6: 687b ldr r3, [r7, #4]
8005cf8: 681b ldr r3, [r3, #0]
8005cfa: 68da ldr r2, [r3, #12]
8005cfc: 687b ldr r3, [r7, #4]
8005cfe: 681b ldr r3, [r3, #0]
8005d00: f442 5200 orr.w r2, r2, #8192 @ 0x2000
8005d04: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8005d06: 687b ldr r3, [r7, #4]
8005d08: 2200 movs r2, #0
8005d0a: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
8005d0c: 687b ldr r3, [r7, #4]
8005d0e: 2220 movs r2, #32
8005d10: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
8005d14: 687b ldr r3, [r7, #4]
8005d16: 2220 movs r2, #32
8005d18: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005d1c: 687b ldr r3, [r7, #4]
8005d1e: 2200 movs r2, #0
8005d20: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8005d22: 2300 movs r3, #0
}
8005d24: 4618 mov r0, r3
8005d26: 3708 adds r7, #8
8005d28: 46bd mov sp, r7
8005d2a: bd80 pop {r7, pc}
08005d2c <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8005d2c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8005d30: b0c0 sub sp, #256 @ 0x100
8005d32: af00 add r7, sp, #0
8005d34: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8005d38: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d3c: 681b ldr r3, [r3, #0]
8005d3e: 691b ldr r3, [r3, #16]
8005d40: f423 5040 bic.w r0, r3, #12288 @ 0x3000
8005d44: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d48: 68d9 ldr r1, [r3, #12]
8005d4a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d4e: 681a ldr r2, [r3, #0]
8005d50: ea40 0301 orr.w r3, r0, r1
8005d54: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8005d56: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d5a: 689a ldr r2, [r3, #8]
8005d5c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d60: 691b ldr r3, [r3, #16]
8005d62: 431a orrs r2, r3
8005d64: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d68: 695b ldr r3, [r3, #20]
8005d6a: 431a orrs r2, r3
8005d6c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d70: 69db ldr r3, [r3, #28]
8005d72: 4313 orrs r3, r2
8005d74: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
MODIFY_REG(huart->Instance->CR1,
8005d78: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d7c: 681b ldr r3, [r3, #0]
8005d7e: 68db ldr r3, [r3, #12]
8005d80: f423 4116 bic.w r1, r3, #38400 @ 0x9600
8005d84: f021 010c bic.w r1, r1, #12
8005d88: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d8c: 681a ldr r2, [r3, #0]
8005d8e: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005d92: 430b orrs r3, r1
8005d94: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8005d96: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005d9a: 681b ldr r3, [r3, #0]
8005d9c: 695b ldr r3, [r3, #20]
8005d9e: f423 7040 bic.w r0, r3, #768 @ 0x300
8005da2: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005da6: 6999 ldr r1, [r3, #24]
8005da8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005dac: 681a ldr r2, [r3, #0]
8005dae: ea40 0301 orr.w r3, r0, r1
8005db2: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8005db4: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005db8: 681a ldr r2, [r3, #0]
8005dba: 4b8f ldr r3, [pc, #572] @ (8005ff8 <UART_SetConfig+0x2cc>)
8005dbc: 429a cmp r2, r3
8005dbe: d005 beq.n 8005dcc <UART_SetConfig+0xa0>
8005dc0: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005dc4: 681a ldr r2, [r3, #0]
8005dc6: 4b8d ldr r3, [pc, #564] @ (8005ffc <UART_SetConfig+0x2d0>)
8005dc8: 429a cmp r2, r3
8005dca: d104 bne.n 8005dd6 <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
8005dcc: f7ff f82c bl 8004e28 <HAL_RCC_GetPCLK2Freq>
8005dd0: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
8005dd4: e003 b.n 8005dde <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8005dd6: f7ff f813 bl 8004e00 <HAL_RCC_GetPCLK1Freq>
8005dda: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8005dde: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005de2: 69db ldr r3, [r3, #28]
8005de4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8005de8: f040 810c bne.w 8006004 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8005dec: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8005df0: 2200 movs r2, #0
8005df2: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
8005df6: f8c7 20ec str.w r2, [r7, #236] @ 0xec
8005dfa: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
8005dfe: 4622 mov r2, r4
8005e00: 462b mov r3, r5
8005e02: 1891 adds r1, r2, r2
8005e04: 65b9 str r1, [r7, #88] @ 0x58
8005e06: 415b adcs r3, r3
8005e08: 65fb str r3, [r7, #92] @ 0x5c
8005e0a: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
8005e0e: 4621 mov r1, r4
8005e10: eb12 0801 adds.w r8, r2, r1
8005e14: 4629 mov r1, r5
8005e16: eb43 0901 adc.w r9, r3, r1
8005e1a: f04f 0200 mov.w r2, #0
8005e1e: f04f 0300 mov.w r3, #0
8005e22: ea4f 03c9 mov.w r3, r9, lsl #3
8005e26: ea43 7358 orr.w r3, r3, r8, lsr #29
8005e2a: ea4f 02c8 mov.w r2, r8, lsl #3
8005e2e: 4690 mov r8, r2
8005e30: 4699 mov r9, r3
8005e32: 4623 mov r3, r4
8005e34: eb18 0303 adds.w r3, r8, r3
8005e38: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
8005e3c: 462b mov r3, r5
8005e3e: eb49 0303 adc.w r3, r9, r3
8005e42: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
8005e46: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005e4a: 685b ldr r3, [r3, #4]
8005e4c: 2200 movs r2, #0
8005e4e: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
8005e52: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
8005e56: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
8005e5a: 460b mov r3, r1
8005e5c: 18db adds r3, r3, r3
8005e5e: 653b str r3, [r7, #80] @ 0x50
8005e60: 4613 mov r3, r2
8005e62: eb42 0303 adc.w r3, r2, r3
8005e66: 657b str r3, [r7, #84] @ 0x54
8005e68: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
8005e6c: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
8005e70: f7fa f9be bl 80001f0 <__aeabi_uldivmod>
8005e74: 4602 mov r2, r0
8005e76: 460b mov r3, r1
8005e78: 4b61 ldr r3, [pc, #388] @ (8006000 <UART_SetConfig+0x2d4>)
8005e7a: fba3 2302 umull r2, r3, r3, r2
8005e7e: 095b lsrs r3, r3, #5
8005e80: 011c lsls r4, r3, #4
8005e82: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8005e86: 2200 movs r2, #0
8005e88: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8005e8c: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
8005e90: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
8005e94: 4642 mov r2, r8
8005e96: 464b mov r3, r9
8005e98: 1891 adds r1, r2, r2
8005e9a: 64b9 str r1, [r7, #72] @ 0x48
8005e9c: 415b adcs r3, r3
8005e9e: 64fb str r3, [r7, #76] @ 0x4c
8005ea0: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
8005ea4: 4641 mov r1, r8
8005ea6: eb12 0a01 adds.w sl, r2, r1
8005eaa: 4649 mov r1, r9
8005eac: eb43 0b01 adc.w fp, r3, r1
8005eb0: f04f 0200 mov.w r2, #0
8005eb4: f04f 0300 mov.w r3, #0
8005eb8: ea4f 03cb mov.w r3, fp, lsl #3
8005ebc: ea43 735a orr.w r3, r3, sl, lsr #29
8005ec0: ea4f 02ca mov.w r2, sl, lsl #3
8005ec4: 4692 mov sl, r2
8005ec6: 469b mov fp, r3
8005ec8: 4643 mov r3, r8
8005eca: eb1a 0303 adds.w r3, sl, r3
8005ece: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8005ed2: 464b mov r3, r9
8005ed4: eb4b 0303 adc.w r3, fp, r3
8005ed8: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8005edc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005ee0: 685b ldr r3, [r3, #4]
8005ee2: 2200 movs r2, #0
8005ee4: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
8005ee8: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
8005eec: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
8005ef0: 460b mov r3, r1
8005ef2: 18db adds r3, r3, r3
8005ef4: 643b str r3, [r7, #64] @ 0x40
8005ef6: 4613 mov r3, r2
8005ef8: eb42 0303 adc.w r3, r2, r3
8005efc: 647b str r3, [r7, #68] @ 0x44
8005efe: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
8005f02: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
8005f06: f7fa f973 bl 80001f0 <__aeabi_uldivmod>
8005f0a: 4602 mov r2, r0
8005f0c: 460b mov r3, r1
8005f0e: 4611 mov r1, r2
8005f10: 4b3b ldr r3, [pc, #236] @ (8006000 <UART_SetConfig+0x2d4>)
8005f12: fba3 2301 umull r2, r3, r3, r1
8005f16: 095b lsrs r3, r3, #5
8005f18: 2264 movs r2, #100 @ 0x64
8005f1a: fb02 f303 mul.w r3, r2, r3
8005f1e: 1acb subs r3, r1, r3
8005f20: 00db lsls r3, r3, #3
8005f22: f103 0232 add.w r2, r3, #50 @ 0x32
8005f26: 4b36 ldr r3, [pc, #216] @ (8006000 <UART_SetConfig+0x2d4>)
8005f28: fba3 2302 umull r2, r3, r3, r2
8005f2c: 095b lsrs r3, r3, #5
8005f2e: 005b lsls r3, r3, #1
8005f30: f403 73f8 and.w r3, r3, #496 @ 0x1f0
8005f34: 441c add r4, r3
8005f36: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8005f3a: 2200 movs r2, #0
8005f3c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
8005f40: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
8005f44: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
8005f48: 4642 mov r2, r8
8005f4a: 464b mov r3, r9
8005f4c: 1891 adds r1, r2, r2
8005f4e: 63b9 str r1, [r7, #56] @ 0x38
8005f50: 415b adcs r3, r3
8005f52: 63fb str r3, [r7, #60] @ 0x3c
8005f54: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
8005f58: 4641 mov r1, r8
8005f5a: 1851 adds r1, r2, r1
8005f5c: 6339 str r1, [r7, #48] @ 0x30
8005f5e: 4649 mov r1, r9
8005f60: 414b adcs r3, r1
8005f62: 637b str r3, [r7, #52] @ 0x34
8005f64: f04f 0200 mov.w r2, #0
8005f68: f04f 0300 mov.w r3, #0
8005f6c: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
8005f70: 4659 mov r1, fp
8005f72: 00cb lsls r3, r1, #3
8005f74: 4651 mov r1, sl
8005f76: ea43 7351 orr.w r3, r3, r1, lsr #29
8005f7a: 4651 mov r1, sl
8005f7c: 00ca lsls r2, r1, #3
8005f7e: 4610 mov r0, r2
8005f80: 4619 mov r1, r3
8005f82: 4603 mov r3, r0
8005f84: 4642 mov r2, r8
8005f86: 189b adds r3, r3, r2
8005f88: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8005f8c: 464b mov r3, r9
8005f8e: 460a mov r2, r1
8005f90: eb42 0303 adc.w r3, r2, r3
8005f94: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8005f98: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005f9c: 685b ldr r3, [r3, #4]
8005f9e: 2200 movs r2, #0
8005fa0: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
8005fa4: f8c7 20ac str.w r2, [r7, #172] @ 0xac
8005fa8: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
8005fac: 460b mov r3, r1
8005fae: 18db adds r3, r3, r3
8005fb0: 62bb str r3, [r7, #40] @ 0x28
8005fb2: 4613 mov r3, r2
8005fb4: eb42 0303 adc.w r3, r2, r3
8005fb8: 62fb str r3, [r7, #44] @ 0x2c
8005fba: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
8005fbe: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
8005fc2: f7fa f915 bl 80001f0 <__aeabi_uldivmod>
8005fc6: 4602 mov r2, r0
8005fc8: 460b mov r3, r1
8005fca: 4b0d ldr r3, [pc, #52] @ (8006000 <UART_SetConfig+0x2d4>)
8005fcc: fba3 1302 umull r1, r3, r3, r2
8005fd0: 095b lsrs r3, r3, #5
8005fd2: 2164 movs r1, #100 @ 0x64
8005fd4: fb01 f303 mul.w r3, r1, r3
8005fd8: 1ad3 subs r3, r2, r3
8005fda: 00db lsls r3, r3, #3
8005fdc: 3332 adds r3, #50 @ 0x32
8005fde: 4a08 ldr r2, [pc, #32] @ (8006000 <UART_SetConfig+0x2d4>)
8005fe0: fba2 2303 umull r2, r3, r2, r3
8005fe4: 095b lsrs r3, r3, #5
8005fe6: f003 0207 and.w r2, r3, #7
8005fea: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005fee: 681b ldr r3, [r3, #0]
8005ff0: 4422 add r2, r4
8005ff2: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8005ff4: e106 b.n 8006204 <UART_SetConfig+0x4d8>
8005ff6: bf00 nop
8005ff8: 40011000 .word 0x40011000
8005ffc: 40011400 .word 0x40011400
8006000: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8006004: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8006008: 2200 movs r2, #0
800600a: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
800600e: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
8006012: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
8006016: 4642 mov r2, r8
8006018: 464b mov r3, r9
800601a: 1891 adds r1, r2, r2
800601c: 6239 str r1, [r7, #32]
800601e: 415b adcs r3, r3
8006020: 627b str r3, [r7, #36] @ 0x24
8006022: e9d7 2308 ldrd r2, r3, [r7, #32]
8006026: 4641 mov r1, r8
8006028: 1854 adds r4, r2, r1
800602a: 4649 mov r1, r9
800602c: eb43 0501 adc.w r5, r3, r1
8006030: f04f 0200 mov.w r2, #0
8006034: f04f 0300 mov.w r3, #0
8006038: 00eb lsls r3, r5, #3
800603a: ea43 7354 orr.w r3, r3, r4, lsr #29
800603e: 00e2 lsls r2, r4, #3
8006040: 4614 mov r4, r2
8006042: 461d mov r5, r3
8006044: 4643 mov r3, r8
8006046: 18e3 adds r3, r4, r3
8006048: f8c7 3098 str.w r3, [r7, #152] @ 0x98
800604c: 464b mov r3, r9
800604e: eb45 0303 adc.w r3, r5, r3
8006052: f8c7 309c str.w r3, [r7, #156] @ 0x9c
8006056: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
800605a: 685b ldr r3, [r3, #4]
800605c: 2200 movs r2, #0
800605e: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8006062: f8c7 2094 str.w r2, [r7, #148] @ 0x94
8006066: f04f 0200 mov.w r2, #0
800606a: f04f 0300 mov.w r3, #0
800606e: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
8006072: 4629 mov r1, r5
8006074: 008b lsls r3, r1, #2
8006076: 4621 mov r1, r4
8006078: ea43 7391 orr.w r3, r3, r1, lsr #30
800607c: 4621 mov r1, r4
800607e: 008a lsls r2, r1, #2
8006080: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
8006084: f7fa f8b4 bl 80001f0 <__aeabi_uldivmod>
8006088: 4602 mov r2, r0
800608a: 460b mov r3, r1
800608c: 4b60 ldr r3, [pc, #384] @ (8006210 <UART_SetConfig+0x4e4>)
800608e: fba3 2302 umull r2, r3, r3, r2
8006092: 095b lsrs r3, r3, #5
8006094: 011c lsls r4, r3, #4
8006096: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
800609a: 2200 movs r2, #0
800609c: f8c7 3088 str.w r3, [r7, #136] @ 0x88
80060a0: f8c7 208c str.w r2, [r7, #140] @ 0x8c
80060a4: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
80060a8: 4642 mov r2, r8
80060aa: 464b mov r3, r9
80060ac: 1891 adds r1, r2, r2
80060ae: 61b9 str r1, [r7, #24]
80060b0: 415b adcs r3, r3
80060b2: 61fb str r3, [r7, #28]
80060b4: e9d7 2306 ldrd r2, r3, [r7, #24]
80060b8: 4641 mov r1, r8
80060ba: 1851 adds r1, r2, r1
80060bc: 6139 str r1, [r7, #16]
80060be: 4649 mov r1, r9
80060c0: 414b adcs r3, r1
80060c2: 617b str r3, [r7, #20]
80060c4: f04f 0200 mov.w r2, #0
80060c8: f04f 0300 mov.w r3, #0
80060cc: e9d7 ab04 ldrd sl, fp, [r7, #16]
80060d0: 4659 mov r1, fp
80060d2: 00cb lsls r3, r1, #3
80060d4: 4651 mov r1, sl
80060d6: ea43 7351 orr.w r3, r3, r1, lsr #29
80060da: 4651 mov r1, sl
80060dc: 00ca lsls r2, r1, #3
80060de: 4610 mov r0, r2
80060e0: 4619 mov r1, r3
80060e2: 4603 mov r3, r0
80060e4: 4642 mov r2, r8
80060e6: 189b adds r3, r3, r2
80060e8: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80060ec: 464b mov r3, r9
80060ee: 460a mov r2, r1
80060f0: eb42 0303 adc.w r3, r2, r3
80060f4: f8c7 3084 str.w r3, [r7, #132] @ 0x84
80060f8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80060fc: 685b ldr r3, [r3, #4]
80060fe: 2200 movs r2, #0
8006100: 67bb str r3, [r7, #120] @ 0x78
8006102: 67fa str r2, [r7, #124] @ 0x7c
8006104: f04f 0200 mov.w r2, #0
8006108: f04f 0300 mov.w r3, #0
800610c: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
8006110: 4649 mov r1, r9
8006112: 008b lsls r3, r1, #2
8006114: 4641 mov r1, r8
8006116: ea43 7391 orr.w r3, r3, r1, lsr #30
800611a: 4641 mov r1, r8
800611c: 008a lsls r2, r1, #2
800611e: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
8006122: f7fa f865 bl 80001f0 <__aeabi_uldivmod>
8006126: 4602 mov r2, r0
8006128: 460b mov r3, r1
800612a: 4611 mov r1, r2
800612c: 4b38 ldr r3, [pc, #224] @ (8006210 <UART_SetConfig+0x4e4>)
800612e: fba3 2301 umull r2, r3, r3, r1
8006132: 095b lsrs r3, r3, #5
8006134: 2264 movs r2, #100 @ 0x64
8006136: fb02 f303 mul.w r3, r2, r3
800613a: 1acb subs r3, r1, r3
800613c: 011b lsls r3, r3, #4
800613e: 3332 adds r3, #50 @ 0x32
8006140: 4a33 ldr r2, [pc, #204] @ (8006210 <UART_SetConfig+0x4e4>)
8006142: fba2 2303 umull r2, r3, r2, r3
8006146: 095b lsrs r3, r3, #5
8006148: f003 03f0 and.w r3, r3, #240 @ 0xf0
800614c: 441c add r4, r3
800614e: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8006152: 2200 movs r2, #0
8006154: 673b str r3, [r7, #112] @ 0x70
8006156: 677a str r2, [r7, #116] @ 0x74
8006158: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
800615c: 4642 mov r2, r8
800615e: 464b mov r3, r9
8006160: 1891 adds r1, r2, r2
8006162: 60b9 str r1, [r7, #8]
8006164: 415b adcs r3, r3
8006166: 60fb str r3, [r7, #12]
8006168: e9d7 2302 ldrd r2, r3, [r7, #8]
800616c: 4641 mov r1, r8
800616e: 1851 adds r1, r2, r1
8006170: 6039 str r1, [r7, #0]
8006172: 4649 mov r1, r9
8006174: 414b adcs r3, r1
8006176: 607b str r3, [r7, #4]
8006178: f04f 0200 mov.w r2, #0
800617c: f04f 0300 mov.w r3, #0
8006180: e9d7 ab00 ldrd sl, fp, [r7]
8006184: 4659 mov r1, fp
8006186: 00cb lsls r3, r1, #3
8006188: 4651 mov r1, sl
800618a: ea43 7351 orr.w r3, r3, r1, lsr #29
800618e: 4651 mov r1, sl
8006190: 00ca lsls r2, r1, #3
8006192: 4610 mov r0, r2
8006194: 4619 mov r1, r3
8006196: 4603 mov r3, r0
8006198: 4642 mov r2, r8
800619a: 189b adds r3, r3, r2
800619c: 66bb str r3, [r7, #104] @ 0x68
800619e: 464b mov r3, r9
80061a0: 460a mov r2, r1
80061a2: eb42 0303 adc.w r3, r2, r3
80061a6: 66fb str r3, [r7, #108] @ 0x6c
80061a8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80061ac: 685b ldr r3, [r3, #4]
80061ae: 2200 movs r2, #0
80061b0: 663b str r3, [r7, #96] @ 0x60
80061b2: 667a str r2, [r7, #100] @ 0x64
80061b4: f04f 0200 mov.w r2, #0
80061b8: f04f 0300 mov.w r3, #0
80061bc: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
80061c0: 4649 mov r1, r9
80061c2: 008b lsls r3, r1, #2
80061c4: 4641 mov r1, r8
80061c6: ea43 7391 orr.w r3, r3, r1, lsr #30
80061ca: 4641 mov r1, r8
80061cc: 008a lsls r2, r1, #2
80061ce: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
80061d2: f7fa f80d bl 80001f0 <__aeabi_uldivmod>
80061d6: 4602 mov r2, r0
80061d8: 460b mov r3, r1
80061da: 4b0d ldr r3, [pc, #52] @ (8006210 <UART_SetConfig+0x4e4>)
80061dc: fba3 1302 umull r1, r3, r3, r2
80061e0: 095b lsrs r3, r3, #5
80061e2: 2164 movs r1, #100 @ 0x64
80061e4: fb01 f303 mul.w r3, r1, r3
80061e8: 1ad3 subs r3, r2, r3
80061ea: 011b lsls r3, r3, #4
80061ec: 3332 adds r3, #50 @ 0x32
80061ee: 4a08 ldr r2, [pc, #32] @ (8006210 <UART_SetConfig+0x4e4>)
80061f0: fba2 2303 umull r2, r3, r2, r3
80061f4: 095b lsrs r3, r3, #5
80061f6: f003 020f and.w r2, r3, #15
80061fa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80061fe: 681b ldr r3, [r3, #0]
8006200: 4422 add r2, r4
8006202: 609a str r2, [r3, #8]
}
8006204: bf00 nop
8006206: f507 7780 add.w r7, r7, #256 @ 0x100
800620a: 46bd mov sp, r7
800620c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8006210: 51eb851f .word 0x51eb851f
08006214 <FMC_SDRAM_Init>:
* @param Device Pointer to SDRAM device instance
* @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
{
8006214: b480 push {r7}
8006216: b083 sub sp, #12
8006218: af00 add r7, sp, #0
800621a: 6078 str r0, [r7, #4]
800621c: 6039 str r1, [r7, #0]
assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
/* Set SDRAM bank configuration parameters */
if (Init->SDBank == FMC_SDRAM_BANK1)
800621e: 683b ldr r3, [r7, #0]
8006220: 681b ldr r3, [r3, #0]
8006222: 2b00 cmp r3, #0
8006224: d123 bne.n 800626e <FMC_SDRAM_Init+0x5a>
{
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
8006226: 687b ldr r3, [r7, #4]
8006228: 681b ldr r3, [r3, #0]
800622a: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
800622e: f023 037f bic.w r3, r3, #127 @ 0x7f
8006232: 683a ldr r2, [r7, #0]
8006234: 6851 ldr r1, [r2, #4]
8006236: 683a ldr r2, [r7, #0]
8006238: 6892 ldr r2, [r2, #8]
800623a: 4311 orrs r1, r2
800623c: 683a ldr r2, [r7, #0]
800623e: 68d2 ldr r2, [r2, #12]
8006240: 4311 orrs r1, r2
8006242: 683a ldr r2, [r7, #0]
8006244: 6912 ldr r2, [r2, #16]
8006246: 4311 orrs r1, r2
8006248: 683a ldr r2, [r7, #0]
800624a: 6952 ldr r2, [r2, #20]
800624c: 4311 orrs r1, r2
800624e: 683a ldr r2, [r7, #0]
8006250: 6992 ldr r2, [r2, #24]
8006252: 4311 orrs r1, r2
8006254: 683a ldr r2, [r7, #0]
8006256: 69d2 ldr r2, [r2, #28]
8006258: 4311 orrs r1, r2
800625a: 683a ldr r2, [r7, #0]
800625c: 6a12 ldr r2, [r2, #32]
800625e: 4311 orrs r1, r2
8006260: 683a ldr r2, [r7, #0]
8006262: 6a52 ldr r2, [r2, #36] @ 0x24
8006264: 430a orrs r2, r1
8006266: 431a orrs r2, r3
8006268: 687b ldr r3, [r7, #4]
800626a: 601a str r2, [r3, #0]
800626c: e028 b.n 80062c0 <FMC_SDRAM_Init+0xac>
Init->ReadBurst |
Init->ReadPipeDelay));
}
else /* FMC_Bank2_SDRAM */
{
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
800626e: 687b ldr r3, [r7, #4]
8006270: 681b ldr r3, [r3, #0]
8006272: f423 42f8 bic.w r2, r3, #31744 @ 0x7c00
8006276: 683b ldr r3, [r7, #0]
8006278: 69d9 ldr r1, [r3, #28]
800627a: 683b ldr r3, [r7, #0]
800627c: 6a1b ldr r3, [r3, #32]
800627e: 4319 orrs r1, r3
8006280: 683b ldr r3, [r7, #0]
8006282: 6a5b ldr r3, [r3, #36] @ 0x24
8006284: 430b orrs r3, r1
8006286: 431a orrs r2, r3
8006288: 687b ldr r3, [r7, #4]
800628a: 601a str r2, [r3, #0]
FMC_SDCR1_RPIPE,
(Init->SDClockPeriod |
Init->ReadBurst |
Init->ReadPipeDelay));
MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
800628c: 687b ldr r3, [r7, #4]
800628e: 685b ldr r3, [r3, #4]
8006290: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
8006294: f023 037f bic.w r3, r3, #127 @ 0x7f
8006298: 683a ldr r2, [r7, #0]
800629a: 6851 ldr r1, [r2, #4]
800629c: 683a ldr r2, [r7, #0]
800629e: 6892 ldr r2, [r2, #8]
80062a0: 4311 orrs r1, r2
80062a2: 683a ldr r2, [r7, #0]
80062a4: 68d2 ldr r2, [r2, #12]
80062a6: 4311 orrs r1, r2
80062a8: 683a ldr r2, [r7, #0]
80062aa: 6912 ldr r2, [r2, #16]
80062ac: 4311 orrs r1, r2
80062ae: 683a ldr r2, [r7, #0]
80062b0: 6952 ldr r2, [r2, #20]
80062b2: 4311 orrs r1, r2
80062b4: 683a ldr r2, [r7, #0]
80062b6: 6992 ldr r2, [r2, #24]
80062b8: 430a orrs r2, r1
80062ba: 431a orrs r2, r3
80062bc: 687b ldr r3, [r7, #4]
80062be: 605a str r2, [r3, #4]
Init->InternalBankNumber |
Init->CASLatency |
Init->WriteProtection));
}
return HAL_OK;
80062c0: 2300 movs r3, #0
}
80062c2: 4618 mov r0, r3
80062c4: 370c adds r7, #12
80062c6: 46bd mov sp, r7
80062c8: f85d 7b04 ldr.w r7, [sp], #4
80062cc: 4770 bx lr
080062ce <FMC_SDRAM_Timing_Init>:
* @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
{
80062ce: b480 push {r7}
80062d0: b085 sub sp, #20
80062d2: af00 add r7, sp, #0
80062d4: 60f8 str r0, [r7, #12]
80062d6: 60b9 str r1, [r7, #8]
80062d8: 607a str r2, [r7, #4]
assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
assert_param(IS_FMC_SDRAM_BANK(Bank));
/* Set SDRAM device timing parameters */
if (Bank == FMC_SDRAM_BANK1)
80062da: 687b ldr r3, [r7, #4]
80062dc: 2b00 cmp r3, #0
80062de: d128 bne.n 8006332 <FMC_SDRAM_Timing_Init+0x64>
{
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
80062e0: 68fb ldr r3, [r7, #12]
80062e2: 689b ldr r3, [r3, #8]
80062e4: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
80062e8: 68bb ldr r3, [r7, #8]
80062ea: 681b ldr r3, [r3, #0]
80062ec: 1e59 subs r1, r3, #1
80062ee: 68bb ldr r3, [r7, #8]
80062f0: 685b ldr r3, [r3, #4]
80062f2: 3b01 subs r3, #1
80062f4: 011b lsls r3, r3, #4
80062f6: 4319 orrs r1, r3
80062f8: 68bb ldr r3, [r7, #8]
80062fa: 689b ldr r3, [r3, #8]
80062fc: 3b01 subs r3, #1
80062fe: 021b lsls r3, r3, #8
8006300: 4319 orrs r1, r3
8006302: 68bb ldr r3, [r7, #8]
8006304: 68db ldr r3, [r3, #12]
8006306: 3b01 subs r3, #1
8006308: 031b lsls r3, r3, #12
800630a: 4319 orrs r1, r3
800630c: 68bb ldr r3, [r7, #8]
800630e: 691b ldr r3, [r3, #16]
8006310: 3b01 subs r3, #1
8006312: 041b lsls r3, r3, #16
8006314: 4319 orrs r1, r3
8006316: 68bb ldr r3, [r7, #8]
8006318: 695b ldr r3, [r3, #20]
800631a: 3b01 subs r3, #1
800631c: 051b lsls r3, r3, #20
800631e: 4319 orrs r1, r3
8006320: 68bb ldr r3, [r7, #8]
8006322: 699b ldr r3, [r3, #24]
8006324: 3b01 subs r3, #1
8006326: 061b lsls r3, r3, #24
8006328: 430b orrs r3, r1
800632a: 431a orrs r2, r3
800632c: 68fb ldr r3, [r7, #12]
800632e: 609a str r2, [r3, #8]
8006330: e02f b.n 8006392 <FMC_SDRAM_Timing_Init+0xc4>
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
}
else /* FMC_Bank2_SDRAM */
{
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
8006332: 68fb ldr r3, [r7, #12]
8006334: 689b ldr r3, [r3, #8]
8006336: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
800633a: f423 4370 bic.w r3, r3, #61440 @ 0xf000
800633e: 68ba ldr r2, [r7, #8]
8006340: 68d2 ldr r2, [r2, #12]
8006342: 3a01 subs r2, #1
8006344: 0311 lsls r1, r2, #12
8006346: 68ba ldr r2, [r7, #8]
8006348: 6952 ldr r2, [r2, #20]
800634a: 3a01 subs r2, #1
800634c: 0512 lsls r2, r2, #20
800634e: 430a orrs r2, r1
8006350: 431a orrs r2, r3
8006352: 68fb ldr r3, [r7, #12]
8006354: 609a str r2, [r3, #8]
FMC_SDTR1_TRC |
FMC_SDTR1_TRP,
(((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
(((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
8006356: 68fb ldr r3, [r7, #12]
8006358: 68db ldr r3, [r3, #12]
800635a: f003 4270 and.w r2, r3, #4026531840 @ 0xf0000000
800635e: 68bb ldr r3, [r7, #8]
8006360: 681b ldr r3, [r3, #0]
8006362: 1e59 subs r1, r3, #1
8006364: 68bb ldr r3, [r7, #8]
8006366: 685b ldr r3, [r3, #4]
8006368: 3b01 subs r3, #1
800636a: 011b lsls r3, r3, #4
800636c: 4319 orrs r1, r3
800636e: 68bb ldr r3, [r7, #8]
8006370: 689b ldr r3, [r3, #8]
8006372: 3b01 subs r3, #1
8006374: 021b lsls r3, r3, #8
8006376: 4319 orrs r1, r3
8006378: 68bb ldr r3, [r7, #8]
800637a: 691b ldr r3, [r3, #16]
800637c: 3b01 subs r3, #1
800637e: 041b lsls r3, r3, #16
8006380: 4319 orrs r1, r3
8006382: 68bb ldr r3, [r7, #8]
8006384: 699b ldr r3, [r3, #24]
8006386: 3b01 subs r3, #1
8006388: 061b lsls r3, r3, #24
800638a: 430b orrs r3, r1
800638c: 431a orrs r2, r3
800638e: 68fb ldr r3, [r7, #12]
8006390: 60da str r2, [r3, #12]
(((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
(((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
(((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
}
return HAL_OK;
8006392: 2300 movs r3, #0
}
8006394: 4618 mov r0, r3
8006396: 3714 adds r7, #20
8006398: 46bd mov sp, r7
800639a: f85d 7b04 ldr.w r7, [sp], #4
800639e: 4770 bx lr
080063a0 <USB_EnableGlobalInt>:
* Enables the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80063a0: b480 push {r7}
80063a2: b083 sub sp, #12
80063a4: af00 add r7, sp, #0
80063a6: 6078 str r0, [r7, #4]
USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
80063a8: 687b ldr r3, [r7, #4]
80063aa: 689b ldr r3, [r3, #8]
80063ac: f043 0201 orr.w r2, r3, #1
80063b0: 687b ldr r3, [r7, #4]
80063b2: 609a str r2, [r3, #8]
return HAL_OK;
80063b4: 2300 movs r3, #0
}
80063b6: 4618 mov r0, r3
80063b8: 370c adds r7, #12
80063ba: 46bd mov sp, r7
80063bc: f85d 7b04 ldr.w r7, [sp], #4
80063c0: 4770 bx lr
080063c2 <USB_DisableGlobalInt>:
* Disable the controller's Global Int in the AHB Config reg
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
{
80063c2: b480 push {r7}
80063c4: b083 sub sp, #12
80063c6: af00 add r7, sp, #0
80063c8: 6078 str r0, [r7, #4]
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
80063ca: 687b ldr r3, [r7, #4]
80063cc: 689b ldr r3, [r3, #8]
80063ce: f023 0201 bic.w r2, r3, #1
80063d2: 687b ldr r3, [r7, #4]
80063d4: 609a str r2, [r3, #8]
return HAL_OK;
80063d6: 2300 movs r3, #0
}
80063d8: 4618 mov r0, r3
80063da: 370c adds r7, #12
80063dc: 46bd mov sp, r7
80063de: f85d 7b04 ldr.w r7, [sp], #4
80063e2: 4770 bx lr
080063e4 <USB_FlushTxFifo>:
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{
80063e4: b480 push {r7}
80063e6: b085 sub sp, #20
80063e8: af00 add r7, sp, #0
80063ea: 6078 str r0, [r7, #4]
80063ec: 6039 str r1, [r7, #0]
__IO uint32_t count = 0U;
80063ee: 2300 movs r3, #0
80063f0: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
80063f2: 68fb ldr r3, [r7, #12]
80063f4: 3301 adds r3, #1
80063f6: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
80063f8: 68fb ldr r3, [r7, #12]
80063fa: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
80063fe: d901 bls.n 8006404 <USB_FlushTxFifo+0x20>
{
return HAL_TIMEOUT;
8006400: 2303 movs r3, #3
8006402: e01b b.n 800643c <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8006404: 687b ldr r3, [r7, #4]
8006406: 691b ldr r3, [r3, #16]
8006408: 2b00 cmp r3, #0
800640a: daf2 bge.n 80063f2 <USB_FlushTxFifo+0xe>
/* Flush TX Fifo */
count = 0U;
800640c: 2300 movs r3, #0
800640e: 60fb str r3, [r7, #12]
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
8006410: 683b ldr r3, [r7, #0]
8006412: 019b lsls r3, r3, #6
8006414: f043 0220 orr.w r2, r3, #32
8006418: 687b ldr r3, [r7, #4]
800641a: 611a str r2, [r3, #16]
do
{
count++;
800641c: 68fb ldr r3, [r7, #12]
800641e: 3301 adds r3, #1
8006420: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
8006422: 68fb ldr r3, [r7, #12]
8006424: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8006428: d901 bls.n 800642e <USB_FlushTxFifo+0x4a>
{
return HAL_TIMEOUT;
800642a: 2303 movs r3, #3
800642c: e006 b.n 800643c <USB_FlushTxFifo+0x58>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
800642e: 687b ldr r3, [r7, #4]
8006430: 691b ldr r3, [r3, #16]
8006432: f003 0320 and.w r3, r3, #32
8006436: 2b20 cmp r3, #32
8006438: d0f0 beq.n 800641c <USB_FlushTxFifo+0x38>
return HAL_OK;
800643a: 2300 movs r3, #0
}
800643c: 4618 mov r0, r3
800643e: 3714 adds r7, #20
8006440: 46bd mov sp, r7
8006442: f85d 7b04 ldr.w r7, [sp], #4
8006446: 4770 bx lr
08006448 <USB_FlushRxFifo>:
* @brief USB_FlushRxFifo Flush Rx FIFO
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
8006448: b480 push {r7}
800644a: b085 sub sp, #20
800644c: af00 add r7, sp, #0
800644e: 6078 str r0, [r7, #4]
__IO uint32_t count = 0U;
8006450: 2300 movs r3, #0
8006452: 60fb str r3, [r7, #12]
/* Wait for AHB master IDLE state. */
do
{
count++;
8006454: 68fb ldr r3, [r7, #12]
8006456: 3301 adds r3, #1
8006458: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
800645a: 68fb ldr r3, [r7, #12]
800645c: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8006460: d901 bls.n 8006466 <USB_FlushRxFifo+0x1e>
{
return HAL_TIMEOUT;
8006462: 2303 movs r3, #3
8006464: e018 b.n 8006498 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
8006466: 687b ldr r3, [r7, #4]
8006468: 691b ldr r3, [r3, #16]
800646a: 2b00 cmp r3, #0
800646c: daf2 bge.n 8006454 <USB_FlushRxFifo+0xc>
/* Flush RX Fifo */
count = 0U;
800646e: 2300 movs r3, #0
8006470: 60fb str r3, [r7, #12]
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
8006472: 687b ldr r3, [r7, #4]
8006474: 2210 movs r2, #16
8006476: 611a str r2, [r3, #16]
do
{
count++;
8006478: 68fb ldr r3, [r7, #12]
800647a: 3301 adds r3, #1
800647c: 60fb str r3, [r7, #12]
if (count > HAL_USB_TIMEOUT)
800647e: 68fb ldr r3, [r7, #12]
8006480: f1b3 6f70 cmp.w r3, #251658240 @ 0xf000000
8006484: d901 bls.n 800648a <USB_FlushRxFifo+0x42>
{
return HAL_TIMEOUT;
8006486: 2303 movs r3, #3
8006488: e006 b.n 8006498 <USB_FlushRxFifo+0x50>
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
800648a: 687b ldr r3, [r7, #4]
800648c: 691b ldr r3, [r3, #16]
800648e: f003 0310 and.w r3, r3, #16
8006492: 2b10 cmp r3, #16
8006494: d0f0 beq.n 8006478 <USB_FlushRxFifo+0x30>
return HAL_OK;
8006496: 2300 movs r3, #0
}
8006498: 4618 mov r0, r3
800649a: 3714 adds r7, #20
800649c: 46bd mov sp, r7
800649e: f85d 7b04 ldr.w r7, [sp], #4
80064a2: 4770 bx lr
080064a4 <USB_ReadPacket>:
* @param dest source pointer
* @param len Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
80064a4: b480 push {r7}
80064a6: b08b sub sp, #44 @ 0x2c
80064a8: af00 add r7, sp, #0
80064aa: 60f8 str r0, [r7, #12]
80064ac: 60b9 str r1, [r7, #8]
80064ae: 4613 mov r3, r2
80064b0: 80fb strh r3, [r7, #6]
uint32_t USBx_BASE = (uint32_t)USBx;
80064b2: 68fb ldr r3, [r7, #12]
80064b4: 61bb str r3, [r7, #24]
uint8_t *pDest = dest;
80064b6: 68bb ldr r3, [r7, #8]
80064b8: 627b str r3, [r7, #36] @ 0x24
uint32_t pData;
uint32_t i;
uint32_t count32b = (uint32_t)len >> 2U;
80064ba: 88fb ldrh r3, [r7, #6]
80064bc: 089b lsrs r3, r3, #2
80064be: b29b uxth r3, r3
80064c0: 617b str r3, [r7, #20]
uint16_t remaining_bytes = len % 4U;
80064c2: 88fb ldrh r3, [r7, #6]
80064c4: f003 0303 and.w r3, r3, #3
80064c8: 83fb strh r3, [r7, #30]
for (i = 0U; i < count32b; i++)
80064ca: 2300 movs r3, #0
80064cc: 623b str r3, [r7, #32]
80064ce: e014 b.n 80064fa <USB_ReadPacket+0x56>
{
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
80064d0: 69bb ldr r3, [r7, #24]
80064d2: f503 5380 add.w r3, r3, #4096 @ 0x1000
80064d6: 681a ldr r2, [r3, #0]
80064d8: 6a7b ldr r3, [r7, #36] @ 0x24
80064da: 601a str r2, [r3, #0]
pDest++;
80064dc: 6a7b ldr r3, [r7, #36] @ 0x24
80064de: 3301 adds r3, #1
80064e0: 627b str r3, [r7, #36] @ 0x24
pDest++;
80064e2: 6a7b ldr r3, [r7, #36] @ 0x24
80064e4: 3301 adds r3, #1
80064e6: 627b str r3, [r7, #36] @ 0x24
pDest++;
80064e8: 6a7b ldr r3, [r7, #36] @ 0x24
80064ea: 3301 adds r3, #1
80064ec: 627b str r3, [r7, #36] @ 0x24
pDest++;
80064ee: 6a7b ldr r3, [r7, #36] @ 0x24
80064f0: 3301 adds r3, #1
80064f2: 627b str r3, [r7, #36] @ 0x24
for (i = 0U; i < count32b; i++)
80064f4: 6a3b ldr r3, [r7, #32]
80064f6: 3301 adds r3, #1
80064f8: 623b str r3, [r7, #32]
80064fa: 6a3a ldr r2, [r7, #32]
80064fc: 697b ldr r3, [r7, #20]
80064fe: 429a cmp r2, r3
8006500: d3e6 bcc.n 80064d0 <USB_ReadPacket+0x2c>
}
/* When Number of data is not word aligned, read the remaining byte */
if (remaining_bytes != 0U)
8006502: 8bfb ldrh r3, [r7, #30]
8006504: 2b00 cmp r3, #0
8006506: d01e beq.n 8006546 <USB_ReadPacket+0xa2>
{
i = 0U;
8006508: 2300 movs r3, #0
800650a: 623b str r3, [r7, #32]
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
800650c: 69bb ldr r3, [r7, #24]
800650e: f503 5380 add.w r3, r3, #4096 @ 0x1000
8006512: 461a mov r2, r3
8006514: f107 0310 add.w r3, r7, #16
8006518: 6812 ldr r2, [r2, #0]
800651a: 601a str r2, [r3, #0]
do
{
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
800651c: 693a ldr r2, [r7, #16]
800651e: 6a3b ldr r3, [r7, #32]
8006520: b2db uxtb r3, r3
8006522: 00db lsls r3, r3, #3
8006524: fa22 f303 lsr.w r3, r2, r3
8006528: b2da uxtb r2, r3
800652a: 6a7b ldr r3, [r7, #36] @ 0x24
800652c: 701a strb r2, [r3, #0]
i++;
800652e: 6a3b ldr r3, [r7, #32]
8006530: 3301 adds r3, #1
8006532: 623b str r3, [r7, #32]
pDest++;
8006534: 6a7b ldr r3, [r7, #36] @ 0x24
8006536: 3301 adds r3, #1
8006538: 627b str r3, [r7, #36] @ 0x24
remaining_bytes--;
800653a: 8bfb ldrh r3, [r7, #30]
800653c: 3b01 subs r3, #1
800653e: 83fb strh r3, [r7, #30]
} while (remaining_bytes != 0U);
8006540: 8bfb ldrh r3, [r7, #30]
8006542: 2b00 cmp r3, #0
8006544: d1ea bne.n 800651c <USB_ReadPacket+0x78>
}
return ((void *)pDest);
8006546: 6a7b ldr r3, [r7, #36] @ 0x24
}
8006548: 4618 mov r0, r3
800654a: 372c adds r7, #44 @ 0x2c
800654c: 46bd mov sp, r7
800654e: f85d 7b04 ldr.w r7, [sp], #4
8006552: 4770 bx lr
08006554 <USB_ReadInterrupts>:
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx Selected device
* @retval USB Global Interrupt status
*/
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
{
8006554: b480 push {r7}
8006556: b085 sub sp, #20
8006558: af00 add r7, sp, #0
800655a: 6078 str r0, [r7, #4]
uint32_t tmpreg;
tmpreg = USBx->GINTSTS;
800655c: 687b ldr r3, [r7, #4]
800655e: 695b ldr r3, [r3, #20]
8006560: 60fb str r3, [r7, #12]
tmpreg &= USBx->GINTMSK;
8006562: 687b ldr r3, [r7, #4]
8006564: 699b ldr r3, [r3, #24]
8006566: 68fa ldr r2, [r7, #12]
8006568: 4013 ands r3, r2
800656a: 60fb str r3, [r7, #12]
return tmpreg;
800656c: 68fb ldr r3, [r7, #12]
}
800656e: 4618 mov r0, r3
8006570: 3714 adds r7, #20
8006572: 46bd mov sp, r7
8006574: f85d 7b04 ldr.w r7, [sp], #4
8006578: 4770 bx lr
0800657a <USB_ReadChInterrupts>:
* @param USBx Selected device
* @param chnum Channel number
* @retval USB Channel Interrupt status
*/
uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
{
800657a: b480 push {r7}
800657c: b085 sub sp, #20
800657e: af00 add r7, sp, #0
8006580: 6078 str r0, [r7, #4]
8006582: 460b mov r3, r1
8006584: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8006586: 687b ldr r3, [r7, #4]
8006588: 60fb str r3, [r7, #12]
uint32_t tmpreg;
tmpreg = USBx_HC(chnum)->HCINT;
800658a: 78fb ldrb r3, [r7, #3]
800658c: 015a lsls r2, r3, #5
800658e: 68fb ldr r3, [r7, #12]
8006590: 4413 add r3, r2
8006592: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006596: 689b ldr r3, [r3, #8]
8006598: 60bb str r3, [r7, #8]
tmpreg &= USBx_HC(chnum)->HCINTMSK;
800659a: 78fb ldrb r3, [r7, #3]
800659c: 015a lsls r2, r3, #5
800659e: 68fb ldr r3, [r7, #12]
80065a0: 4413 add r3, r2
80065a2: f503 63a0 add.w r3, r3, #1280 @ 0x500
80065a6: 68db ldr r3, [r3, #12]
80065a8: 68ba ldr r2, [r7, #8]
80065aa: 4013 ands r3, r2
80065ac: 60bb str r3, [r7, #8]
return tmpreg;
80065ae: 68bb ldr r3, [r7, #8]
}
80065b0: 4618 mov r0, r3
80065b2: 3714 adds r7, #20
80065b4: 46bd mov sp, r7
80065b6: f85d 7b04 ldr.w r7, [sp], #4
80065ba: 4770 bx lr
080065bc <USB_GetMode>:
* This parameter can be one of these values:
* 1 : Host
* 0 : Device
*/
uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
{
80065bc: b480 push {r7}
80065be: b083 sub sp, #12
80065c0: af00 add r7, sp, #0
80065c2: 6078 str r0, [r7, #4]
return ((USBx->GINTSTS) & 0x1U);
80065c4: 687b ldr r3, [r7, #4]
80065c6: 695b ldr r3, [r3, #20]
80065c8: f003 0301 and.w r3, r3, #1
}
80065cc: 4618 mov r0, r3
80065ce: 370c adds r7, #12
80065d0: 46bd mov sp, r7
80065d2: f85d 7b04 ldr.w r7, [sp], #4
80065d6: 4770 bx lr
080065d8 <USB_InitFSLSPClkSel>:
* HCFG_48_MHZ : Full Speed 48 MHz Clock
* HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
{
80065d8: b480 push {r7}
80065da: b085 sub sp, #20
80065dc: af00 add r7, sp, #0
80065de: 6078 str r0, [r7, #4]
80065e0: 460b mov r3, r1
80065e2: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
80065e4: 687b ldr r3, [r7, #4]
80065e6: 60fb str r3, [r7, #12]
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
80065e8: 68fb ldr r3, [r7, #12]
80065ea: f503 6380 add.w r3, r3, #1024 @ 0x400
80065ee: 681b ldr r3, [r3, #0]
80065f0: 68fa ldr r2, [r7, #12]
80065f2: f502 6280 add.w r2, r2, #1024 @ 0x400
80065f6: f023 0303 bic.w r3, r3, #3
80065fa: 6013 str r3, [r2, #0]
USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;
80065fc: 68fb ldr r3, [r7, #12]
80065fe: f503 6380 add.w r3, r3, #1024 @ 0x400
8006602: 681a ldr r2, [r3, #0]
8006604: 78fb ldrb r3, [r7, #3]
8006606: f003 0303 and.w r3, r3, #3
800660a: 68f9 ldr r1, [r7, #12]
800660c: f501 6180 add.w r1, r1, #1024 @ 0x400
8006610: 4313 orrs r3, r2
8006612: 600b str r3, [r1, #0]
if (freq == HCFG_48_MHZ)
8006614: 78fb ldrb r3, [r7, #3]
8006616: 2b01 cmp r3, #1
8006618: d107 bne.n 800662a <USB_InitFSLSPClkSel+0x52>
{
USBx_HOST->HFIR = HFIR_48_MHZ;
800661a: 68fb ldr r3, [r7, #12]
800661c: f503 6380 add.w r3, r3, #1024 @ 0x400
8006620: 461a mov r2, r3
8006622: f64b 3380 movw r3, #48000 @ 0xbb80
8006626: 6053 str r3, [r2, #4]
8006628: e00c b.n 8006644 <USB_InitFSLSPClkSel+0x6c>
}
else if (freq == HCFG_6_MHZ)
800662a: 78fb ldrb r3, [r7, #3]
800662c: 2b02 cmp r3, #2
800662e: d107 bne.n 8006640 <USB_InitFSLSPClkSel+0x68>
{
USBx_HOST->HFIR = HFIR_6_MHZ;
8006630: 68fb ldr r3, [r7, #12]
8006632: f503 6380 add.w r3, r3, #1024 @ 0x400
8006636: 461a mov r2, r3
8006638: f241 7370 movw r3, #6000 @ 0x1770
800663c: 6053 str r3, [r2, #4]
800663e: e001 b.n 8006644 <USB_InitFSLSPClkSel+0x6c>
}
else
{
return HAL_ERROR;
8006640: 2301 movs r3, #1
8006642: e000 b.n 8006646 <USB_InitFSLSPClkSel+0x6e>
}
return HAL_OK;
8006644: 2300 movs r3, #0
}
8006646: 4618 mov r0, r3
8006648: 3714 adds r7, #20
800664a: 46bd mov sp, r7
800664c: f85d 7b04 ldr.w r7, [sp], #4
8006650: 4770 bx lr
08006652 <USB_HC_ReadInterrupt>:
* @brief Read all host channel interrupts status
* @param USBx Selected device
* @retval HAL state
*/
uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
{
8006652: b480 push {r7}
8006654: b085 sub sp, #20
8006656: af00 add r7, sp, #0
8006658: 6078 str r0, [r7, #4]
uint32_t USBx_BASE = (uint32_t)USBx;
800665a: 687b ldr r3, [r7, #4]
800665c: 60fb str r3, [r7, #12]
return ((USBx_HOST->HAINT) & 0xFFFFU);
800665e: 68fb ldr r3, [r7, #12]
8006660: f503 6380 add.w r3, r3, #1024 @ 0x400
8006664: 695b ldr r3, [r3, #20]
8006666: b29b uxth r3, r3
}
8006668: 4618 mov r0, r3
800666a: 3714 adds r7, #20
800666c: 46bd mov sp, r7
800666e: f85d 7b04 ldr.w r7, [sp], #4
8006672: 4770 bx lr
08006674 <USB_HC_Halt>:
* @param hc_num Host Channel number
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
{
8006674: b480 push {r7}
8006676: b089 sub sp, #36 @ 0x24
8006678: af00 add r7, sp, #0
800667a: 6078 str r0, [r7, #4]
800667c: 460b mov r3, r1
800667e: 70fb strb r3, [r7, #3]
uint32_t USBx_BASE = (uint32_t)USBx;
8006680: 687b ldr r3, [r7, #4]
8006682: 61fb str r3, [r7, #28]
uint32_t hcnum = (uint32_t)hc_num;
8006684: 78fb ldrb r3, [r7, #3]
8006686: 61bb str r3, [r7, #24]
__IO uint32_t count = 0U;
8006688: 2300 movs r3, #0
800668a: 60bb str r3, [r7, #8]
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
800668c: 69bb ldr r3, [r7, #24]
800668e: 015a lsls r2, r3, #5
8006690: 69fb ldr r3, [r7, #28]
8006692: 4413 add r3, r2
8006694: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006698: 681b ldr r3, [r3, #0]
800669a: 0c9b lsrs r3, r3, #18
800669c: f003 0303 and.w r3, r3, #3
80066a0: 617b str r3, [r7, #20]
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
80066a2: 69bb ldr r3, [r7, #24]
80066a4: 015a lsls r2, r3, #5
80066a6: 69fb ldr r3, [r7, #28]
80066a8: 4413 add r3, r2
80066aa: f503 63a0 add.w r3, r3, #1280 @ 0x500
80066ae: 681b ldr r3, [r3, #0]
80066b0: 0fdb lsrs r3, r3, #31
80066b2: f003 0301 and.w r3, r3, #1
80066b6: 613b str r3, [r7, #16]
uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
80066b8: 69bb ldr r3, [r7, #24]
80066ba: 015a lsls r2, r3, #5
80066bc: 69fb ldr r3, [r7, #28]
80066be: 4413 add r3, r2
80066c0: f503 63a0 add.w r3, r3, #1280 @ 0x500
80066c4: 685b ldr r3, [r3, #4]
80066c6: 0fdb lsrs r3, r3, #31
80066c8: f003 0301 and.w r3, r3, #1
80066cc: 60fb str r3, [r7, #12]
/* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
At the end of the next uframe/frame (in the worst case), the core generates a channel halted
and disables the channel automatically. */
if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
80066ce: 687b ldr r3, [r7, #4]
80066d0: 689b ldr r3, [r3, #8]
80066d2: f003 0320 and.w r3, r3, #32
80066d6: 2b20 cmp r3, #32
80066d8: d10d bne.n 80066f6 <USB_HC_Halt+0x82>
80066da: 68fb ldr r3, [r7, #12]
80066dc: 2b00 cmp r3, #0
80066de: d10a bne.n 80066f6 <USB_HC_Halt+0x82>
80066e0: 693b ldr r3, [r7, #16]
80066e2: 2b00 cmp r3, #0
80066e4: d005 beq.n 80066f2 <USB_HC_Halt+0x7e>
((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
80066e6: 697b ldr r3, [r7, #20]
80066e8: 2b01 cmp r3, #1
80066ea: d002 beq.n 80066f2 <USB_HC_Halt+0x7e>
80066ec: 697b ldr r3, [r7, #20]
80066ee: 2b03 cmp r3, #3
80066f0: d101 bne.n 80066f6 <USB_HC_Halt+0x82>
{
return HAL_OK;
80066f2: 2300 movs r3, #0
80066f4: e0d8 b.n 80068a8 <USB_HC_Halt+0x234>
}
/* Check for space in the request queue to issue the halt. */
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
80066f6: 697b ldr r3, [r7, #20]
80066f8: 2b00 cmp r3, #0
80066fa: d002 beq.n 8006702 <USB_HC_Halt+0x8e>
80066fc: 697b ldr r3, [r7, #20]
80066fe: 2b02 cmp r3, #2
8006700: d173 bne.n 80067ea <USB_HC_Halt+0x176>
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
8006702: 69bb ldr r3, [r7, #24]
8006704: 015a lsls r2, r3, #5
8006706: 69fb ldr r3, [r7, #28]
8006708: 4413 add r3, r2
800670a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800670e: 681b ldr r3, [r3, #0]
8006710: 69ba ldr r2, [r7, #24]
8006712: 0151 lsls r1, r2, #5
8006714: 69fa ldr r2, [r7, #28]
8006716: 440a add r2, r1
8006718: f502 62a0 add.w r2, r2, #1280 @ 0x500
800671c: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8006720: 6013 str r3, [r2, #0]
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
8006722: 687b ldr r3, [r7, #4]
8006724: 689b ldr r3, [r3, #8]
8006726: f003 0320 and.w r3, r3, #32
800672a: 2b00 cmp r3, #0
800672c: d14a bne.n 80067c4 <USB_HC_Halt+0x150>
{
if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
800672e: 687b ldr r3, [r7, #4]
8006730: 6adb ldr r3, [r3, #44] @ 0x2c
8006732: f403 037f and.w r3, r3, #16711680 @ 0xff0000
8006736: 2b00 cmp r3, #0
8006738: d133 bne.n 80067a2 <USB_HC_Halt+0x12e>
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
800673a: 69bb ldr r3, [r7, #24]
800673c: 015a lsls r2, r3, #5
800673e: 69fb ldr r3, [r7, #28]
8006740: 4413 add r3, r2
8006742: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006746: 681b ldr r3, [r3, #0]
8006748: 69ba ldr r2, [r7, #24]
800674a: 0151 lsls r1, r2, #5
800674c: 69fa ldr r2, [r7, #28]
800674e: 440a add r2, r1
8006750: f502 62a0 add.w r2, r2, #1280 @ 0x500
8006754: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8006758: 6013 str r3, [r2, #0]
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
800675a: 69bb ldr r3, [r7, #24]
800675c: 015a lsls r2, r3, #5
800675e: 69fb ldr r3, [r7, #28]
8006760: 4413 add r3, r2
8006762: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006766: 681b ldr r3, [r3, #0]
8006768: 69ba ldr r2, [r7, #24]
800676a: 0151 lsls r1, r2, #5
800676c: 69fa ldr r2, [r7, #28]
800676e: 440a add r2, r1
8006770: f502 62a0 add.w r2, r2, #1280 @ 0x500
8006774: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8006778: 6013 str r3, [r2, #0]
do
{
count++;
800677a: 68bb ldr r3, [r7, #8]
800677c: 3301 adds r3, #1
800677e: 60bb str r3, [r7, #8]
if (count > 1000U)
8006780: 68bb ldr r3, [r7, #8]
8006782: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8006786: d82e bhi.n 80067e6 <USB_HC_Halt+0x172>
{
break;
}
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
8006788: 69bb ldr r3, [r7, #24]
800678a: 015a lsls r2, r3, #5
800678c: 69fb ldr r3, [r7, #28]
800678e: 4413 add r3, r2
8006790: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006794: 681b ldr r3, [r3, #0]
8006796: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800679a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800679e: d0ec beq.n 800677a <USB_HC_Halt+0x106>
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
80067a0: e081 b.n 80068a6 <USB_HC_Halt+0x232>
}
else
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
80067a2: 69bb ldr r3, [r7, #24]
80067a4: 015a lsls r2, r3, #5
80067a6: 69fb ldr r3, [r7, #28]
80067a8: 4413 add r3, r2
80067aa: f503 63a0 add.w r3, r3, #1280 @ 0x500
80067ae: 681b ldr r3, [r3, #0]
80067b0: 69ba ldr r2, [r7, #24]
80067b2: 0151 lsls r1, r2, #5
80067b4: 69fa ldr r2, [r7, #28]
80067b6: 440a add r2, r1
80067b8: f502 62a0 add.w r2, r2, #1280 @ 0x500
80067bc: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
80067c0: 6013 str r3, [r2, #0]
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
80067c2: e070 b.n 80068a6 <USB_HC_Halt+0x232>
}
}
else
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
80067c4: 69bb ldr r3, [r7, #24]
80067c6: 015a lsls r2, r3, #5
80067c8: 69fb ldr r3, [r7, #28]
80067ca: 4413 add r3, r2
80067cc: f503 63a0 add.w r3, r3, #1280 @ 0x500
80067d0: 681b ldr r3, [r3, #0]
80067d2: 69ba ldr r2, [r7, #24]
80067d4: 0151 lsls r1, r2, #5
80067d6: 69fa ldr r2, [r7, #28]
80067d8: 440a add r2, r1
80067da: f502 62a0 add.w r2, r2, #1280 @ 0x500
80067de: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
80067e2: 6013 str r3, [r2, #0]
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
80067e4: e05f b.n 80068a6 <USB_HC_Halt+0x232>
break;
80067e6: bf00 nop
if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
80067e8: e05d b.n 80068a6 <USB_HC_Halt+0x232>
}
}
else
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
80067ea: 69bb ldr r3, [r7, #24]
80067ec: 015a lsls r2, r3, #5
80067ee: 69fb ldr r3, [r7, #28]
80067f0: 4413 add r3, r2
80067f2: f503 63a0 add.w r3, r3, #1280 @ 0x500
80067f6: 681b ldr r3, [r3, #0]
80067f8: 69ba ldr r2, [r7, #24]
80067fa: 0151 lsls r1, r2, #5
80067fc: 69fa ldr r2, [r7, #28]
80067fe: 440a add r2, r1
8006800: f502 62a0 add.w r2, r2, #1280 @ 0x500
8006804: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8006808: 6013 str r3, [r2, #0]
if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)
800680a: 69fb ldr r3, [r7, #28]
800680c: f503 6380 add.w r3, r3, #1024 @ 0x400
8006810: 691b ldr r3, [r3, #16]
8006812: f403 037f and.w r3, r3, #16711680 @ 0xff0000
8006816: 2b00 cmp r3, #0
8006818: d133 bne.n 8006882 <USB_HC_Halt+0x20e>
{
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
800681a: 69bb ldr r3, [r7, #24]
800681c: 015a lsls r2, r3, #5
800681e: 69fb ldr r3, [r7, #28]
8006820: 4413 add r3, r2
8006822: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006826: 681b ldr r3, [r3, #0]
8006828: 69ba ldr r2, [r7, #24]
800682a: 0151 lsls r1, r2, #5
800682c: 69fa ldr r2, [r7, #28]
800682e: 440a add r2, r1
8006830: f502 62a0 add.w r2, r2, #1280 @ 0x500
8006834: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8006838: 6013 str r3, [r2, #0]
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
800683a: 69bb ldr r3, [r7, #24]
800683c: 015a lsls r2, r3, #5
800683e: 69fb ldr r3, [r7, #28]
8006840: 4413 add r3, r2
8006842: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006846: 681b ldr r3, [r3, #0]
8006848: 69ba ldr r2, [r7, #24]
800684a: 0151 lsls r1, r2, #5
800684c: 69fa ldr r2, [r7, #28]
800684e: 440a add r2, r1
8006850: f502 62a0 add.w r2, r2, #1280 @ 0x500
8006854: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8006858: 6013 str r3, [r2, #0]
do
{
count++;
800685a: 68bb ldr r3, [r7, #8]
800685c: 3301 adds r3, #1
800685e: 60bb str r3, [r7, #8]
if (count > 1000U)
8006860: 68bb ldr r3, [r7, #8]
8006862: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8006866: d81d bhi.n 80068a4 <USB_HC_Halt+0x230>
{
break;
}
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
8006868: 69bb ldr r3, [r7, #24]
800686a: 015a lsls r2, r3, #5
800686c: 69fb ldr r3, [r7, #28]
800686e: 4413 add r3, r2
8006870: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006874: 681b ldr r3, [r3, #0]
8006876: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800687a: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800687e: d0ec beq.n 800685a <USB_HC_Halt+0x1e6>
8006880: e011 b.n 80068a6 <USB_HC_Halt+0x232>
}
else
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
8006882: 69bb ldr r3, [r7, #24]
8006884: 015a lsls r2, r3, #5
8006886: 69fb ldr r3, [r7, #28]
8006888: 4413 add r3, r2
800688a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800688e: 681b ldr r3, [r3, #0]
8006890: 69ba ldr r2, [r7, #24]
8006892: 0151 lsls r1, r2, #5
8006894: 69fa ldr r2, [r7, #28]
8006896: 440a add r2, r1
8006898: f502 62a0 add.w r2, r2, #1280 @ 0x500
800689c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
80068a0: 6013 str r3, [r2, #0]
80068a2: e000 b.n 80068a6 <USB_HC_Halt+0x232>
break;
80068a4: bf00 nop
}
}
return HAL_OK;
80068a6: 2300 movs r3, #0
}
80068a8: 4618 mov r0, r3
80068aa: 3724 adds r7, #36 @ 0x24
80068ac: 46bd mov sp, r7
80068ae: f85d 7b04 ldr.w r7, [sp], #4
80068b2: 4770 bx lr
080068b4 <USB_StopHost>:
* @brief Stop Host Core
* @param USBx Selected device
* @retval HAL state
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
{
80068b4: b580 push {r7, lr}
80068b6: b088 sub sp, #32
80068b8: af00 add r7, sp, #0
80068ba: 6078 str r0, [r7, #4]
HAL_StatusTypeDef ret = HAL_OK;
80068bc: 2300 movs r3, #0
80068be: 77fb strb r3, [r7, #31]
uint32_t USBx_BASE = (uint32_t)USBx;
80068c0: 687b ldr r3, [r7, #4]
80068c2: 617b str r3, [r7, #20]
__IO uint32_t count = 0U;
80068c4: 2300 movs r3, #0
80068c6: 60fb str r3, [r7, #12]
uint32_t value;
uint32_t i;
(void)USB_DisableGlobalInt(USBx);
80068c8: 6878 ldr r0, [r7, #4]
80068ca: f7ff fd7a bl 80063c2 <USB_DisableGlobalInt>
/* Flush USB FIFO */
if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
80068ce: 2110 movs r1, #16
80068d0: 6878 ldr r0, [r7, #4]
80068d2: f7ff fd87 bl 80063e4 <USB_FlushTxFifo>
80068d6: 4603 mov r3, r0
80068d8: 2b00 cmp r3, #0
80068da: d001 beq.n 80068e0 <USB_StopHost+0x2c>
{
ret = HAL_ERROR;
80068dc: 2301 movs r3, #1
80068de: 77fb strb r3, [r7, #31]
}
if (USB_FlushRxFifo(USBx) != HAL_OK)
80068e0: 6878 ldr r0, [r7, #4]
80068e2: f7ff fdb1 bl 8006448 <USB_FlushRxFifo>
80068e6: 4603 mov r3, r0
80068e8: 2b00 cmp r3, #0
80068ea: d001 beq.n 80068f0 <USB_StopHost+0x3c>
{
ret = HAL_ERROR;
80068ec: 2301 movs r3, #1
80068ee: 77fb strb r3, [r7, #31]
}
/* Flush out any leftover queued requests. */
for (i = 0U; i <= 15U; i++)
80068f0: 2300 movs r3, #0
80068f2: 61bb str r3, [r7, #24]
80068f4: e01f b.n 8006936 <USB_StopHost+0x82>
{
value = USBx_HC(i)->HCCHAR;
80068f6: 69bb ldr r3, [r7, #24]
80068f8: 015a lsls r2, r3, #5
80068fa: 697b ldr r3, [r7, #20]
80068fc: 4413 add r3, r2
80068fe: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006902: 681b ldr r3, [r3, #0]
8006904: 613b str r3, [r7, #16]
value |= USB_OTG_HCCHAR_CHDIS;
8006906: 693b ldr r3, [r7, #16]
8006908: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
800690c: 613b str r3, [r7, #16]
value &= ~USB_OTG_HCCHAR_CHENA;
800690e: 693b ldr r3, [r7, #16]
8006910: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8006914: 613b str r3, [r7, #16]
value &= ~USB_OTG_HCCHAR_EPDIR;
8006916: 693b ldr r3, [r7, #16]
8006918: f423 4300 bic.w r3, r3, #32768 @ 0x8000
800691c: 613b str r3, [r7, #16]
USBx_HC(i)->HCCHAR = value;
800691e: 69bb ldr r3, [r7, #24]
8006920: 015a lsls r2, r3, #5
8006922: 697b ldr r3, [r7, #20]
8006924: 4413 add r3, r2
8006926: f503 63a0 add.w r3, r3, #1280 @ 0x500
800692a: 461a mov r2, r3
800692c: 693b ldr r3, [r7, #16]
800692e: 6013 str r3, [r2, #0]
for (i = 0U; i <= 15U; i++)
8006930: 69bb ldr r3, [r7, #24]
8006932: 3301 adds r3, #1
8006934: 61bb str r3, [r7, #24]
8006936: 69bb ldr r3, [r7, #24]
8006938: 2b0f cmp r3, #15
800693a: d9dc bls.n 80068f6 <USB_StopHost+0x42>
}
/* Halt all channels to put them into a known state. */
for (i = 0U; i <= 15U; i++)
800693c: 2300 movs r3, #0
800693e: 61bb str r3, [r7, #24]
8006940: e034 b.n 80069ac <USB_StopHost+0xf8>
{
value = USBx_HC(i)->HCCHAR;
8006942: 69bb ldr r3, [r7, #24]
8006944: 015a lsls r2, r3, #5
8006946: 697b ldr r3, [r7, #20]
8006948: 4413 add r3, r2
800694a: f503 63a0 add.w r3, r3, #1280 @ 0x500
800694e: 681b ldr r3, [r3, #0]
8006950: 613b str r3, [r7, #16]
value |= USB_OTG_HCCHAR_CHDIS;
8006952: 693b ldr r3, [r7, #16]
8006954: f043 4380 orr.w r3, r3, #1073741824 @ 0x40000000
8006958: 613b str r3, [r7, #16]
value |= USB_OTG_HCCHAR_CHENA;
800695a: 693b ldr r3, [r7, #16]
800695c: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
8006960: 613b str r3, [r7, #16]
value &= ~USB_OTG_HCCHAR_EPDIR;
8006962: 693b ldr r3, [r7, #16]
8006964: f423 4300 bic.w r3, r3, #32768 @ 0x8000
8006968: 613b str r3, [r7, #16]
USBx_HC(i)->HCCHAR = value;
800696a: 69bb ldr r3, [r7, #24]
800696c: 015a lsls r2, r3, #5
800696e: 697b ldr r3, [r7, #20]
8006970: 4413 add r3, r2
8006972: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006976: 461a mov r2, r3
8006978: 693b ldr r3, [r7, #16]
800697a: 6013 str r3, [r2, #0]
do
{
count++;
800697c: 68fb ldr r3, [r7, #12]
800697e: 3301 adds r3, #1
8006980: 60fb str r3, [r7, #12]
if (count > 1000U)
8006982: 68fb ldr r3, [r7, #12]
8006984: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
8006988: d80c bhi.n 80069a4 <USB_StopHost+0xf0>
{
break;
}
} while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
800698a: 69bb ldr r3, [r7, #24]
800698c: 015a lsls r2, r3, #5
800698e: 697b ldr r3, [r7, #20]
8006990: 4413 add r3, r2
8006992: f503 63a0 add.w r3, r3, #1280 @ 0x500
8006996: 681b ldr r3, [r3, #0]
8006998: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
800699c: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80069a0: d0ec beq.n 800697c <USB_StopHost+0xc8>
80069a2: e000 b.n 80069a6 <USB_StopHost+0xf2>
break;
80069a4: bf00 nop
for (i = 0U; i <= 15U; i++)
80069a6: 69bb ldr r3, [r7, #24]
80069a8: 3301 adds r3, #1
80069aa: 61bb str r3, [r7, #24]
80069ac: 69bb ldr r3, [r7, #24]
80069ae: 2b0f cmp r3, #15
80069b0: d9c7 bls.n 8006942 <USB_StopHost+0x8e>
}
/* Clear any pending Host interrupts */
USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK;
80069b2: 697b ldr r3, [r7, #20]
80069b4: f503 6380 add.w r3, r3, #1024 @ 0x400
80069b8: 461a mov r2, r3
80069ba: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
80069be: 6153 str r3, [r2, #20]
USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
80069c0: 687b ldr r3, [r7, #4]
80069c2: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80069c6: 615a str r2, [r3, #20]
(void)USB_EnableGlobalInt(USBx);
80069c8: 6878 ldr r0, [r7, #4]
80069ca: f7ff fce9 bl 80063a0 <USB_EnableGlobalInt>
return ret;
80069ce: 7ffb ldrb r3, [r7, #31]
}
80069d0: 4618 mov r0, r3
80069d2: 3720 adds r7, #32
80069d4: 46bd mov sp, r7
80069d6: bd80 pop {r7, pc}
080069d8 <USBH_LL_IncTimer>:
* Increment Host Timer tick
* @param phost: Host Handle
* @retval None
*/
void USBH_LL_IncTimer(USBH_HandleTypeDef *phost)
{
80069d8: b580 push {r7, lr}
80069da: b082 sub sp, #8
80069dc: af00 add r7, sp, #0
80069de: 6078 str r0, [r7, #4]
phost->Timer++;
80069e0: 687b ldr r3, [r7, #4]
80069e2: f8d3 33c4 ldr.w r3, [r3, #964] @ 0x3c4
80069e6: 1c5a adds r2, r3, #1
80069e8: 687b ldr r3, [r7, #4]
80069ea: f8c3 23c4 str.w r2, [r3, #964] @ 0x3c4
USBH_HandleSof(phost);
80069ee: 6878 ldr r0, [r7, #4]
80069f0: f000 f804 bl 80069fc <USBH_HandleSof>
}
80069f4: bf00 nop
80069f6: 3708 adds r7, #8
80069f8: 46bd mov sp, r7
80069fa: bd80 pop {r7, pc}
080069fc <USBH_HandleSof>:
* Call SOF process
* @param phost: Host Handle
* @retval None
*/
static void USBH_HandleSof(USBH_HandleTypeDef *phost)
{
80069fc: b580 push {r7, lr}
80069fe: b082 sub sp, #8
8006a00: af00 add r7, sp, #0
8006a02: 6078 str r0, [r7, #4]
if ((phost->gState == HOST_CLASS) && (phost->pActiveClass != NULL))
8006a04: 687b ldr r3, [r7, #4]
8006a06: 781b ldrb r3, [r3, #0]
8006a08: b2db uxtb r3, r3
8006a0a: 2b0b cmp r3, #11
8006a0c: d10a bne.n 8006a24 <USBH_HandleSof+0x28>
8006a0e: 687b ldr r3, [r7, #4]
8006a10: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
8006a14: 2b00 cmp r3, #0
8006a16: d005 beq.n 8006a24 <USBH_HandleSof+0x28>
{
phost->pActiveClass->SOFProcess(phost);
8006a18: 687b ldr r3, [r7, #4]
8006a1a: f8d3 337c ldr.w r3, [r3, #892] @ 0x37c
8006a1e: 699b ldr r3, [r3, #24]
8006a20: 6878 ldr r0, [r7, #4]
8006a22: 4798 blx r3
}
}
8006a24: bf00 nop
8006a26: 3708 adds r7, #8
8006a28: 46bd mov sp, r7
8006a2a: bd80 pop {r7, pc}
08006a2c <USBH_LL_PortEnabled>:
* Port Enabled
* @param phost: Host Handle
* @retval None
*/
void USBH_LL_PortEnabled(USBH_HandleTypeDef *phost)
{
8006a2c: b580 push {r7, lr}
8006a2e: b082 sub sp, #8
8006a30: af00 add r7, sp, #0
8006a32: 6078 str r0, [r7, #4]
phost->device.PortEnabled = 1U;
8006a34: 687b ldr r3, [r7, #4]
8006a36: 2201 movs r2, #1
8006a38: f883 2323 strb.w r2, [r3, #803] @ 0x323
#if (USBH_USE_OS == 1U)
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
8006a3c: 2300 movs r3, #0
8006a3e: 2200 movs r2, #0
8006a40: 2101 movs r1, #1
8006a42: 6878 ldr r0, [r7, #4]
8006a44: f000 f85b bl 8006afe <USBH_OS_PutMessage>
#endif /* (USBH_USE_OS == 1U) */
return;
8006a48: bf00 nop
}
8006a4a: 3708 adds r7, #8
8006a4c: 46bd mov sp, r7
8006a4e: bd80 pop {r7, pc}
08006a50 <USBH_LL_PortDisabled>:
* Port Disabled
* @param phost: Host Handle
* @retval None
*/
void USBH_LL_PortDisabled(USBH_HandleTypeDef *phost)
{
8006a50: b480 push {r7}
8006a52: b083 sub sp, #12
8006a54: af00 add r7, sp, #0
8006a56: 6078 str r0, [r7, #4]
phost->device.PortEnabled = 0U;
8006a58: 687b ldr r3, [r7, #4]
8006a5a: 2200 movs r2, #0
8006a5c: f883 2323 strb.w r2, [r3, #803] @ 0x323
phost->device.is_disconnected = 1U;
8006a60: 687b ldr r3, [r7, #4]
8006a62: 2201 movs r2, #1
8006a64: f883 2321 strb.w r2, [r3, #801] @ 0x321
return;
8006a68: bf00 nop
}
8006a6a: 370c adds r7, #12
8006a6c: 46bd mov sp, r7
8006a6e: f85d 7b04 ldr.w r7, [sp], #4
8006a72: 4770 bx lr
08006a74 <USBH_LL_Connect>:
* Handle USB Host connection event
* @param phost: Host Handle
* @retval USBH_Status
*/
USBH_StatusTypeDef USBH_LL_Connect(USBH_HandleTypeDef *phost)
{
8006a74: b580 push {r7, lr}
8006a76: b082 sub sp, #8
8006a78: af00 add r7, sp, #0
8006a7a: 6078 str r0, [r7, #4]
phost->device.is_connected = 1U;
8006a7c: 687b ldr r3, [r7, #4]
8006a7e: 2201 movs r2, #1
8006a80: f883 2320 strb.w r2, [r3, #800] @ 0x320
phost->device.is_disconnected = 0U;
8006a84: 687b ldr r3, [r7, #4]
8006a86: 2200 movs r2, #0
8006a88: f883 2321 strb.w r2, [r3, #801] @ 0x321
phost->device.is_ReEnumerated = 0U;
8006a8c: 687b ldr r3, [r7, #4]
8006a8e: 2200 movs r2, #0
8006a90: f883 2322 strb.w r2, [r3, #802] @ 0x322
#if (USBH_USE_OS == 1U)
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
8006a94: 2300 movs r3, #0
8006a96: 2200 movs r2, #0
8006a98: 2101 movs r1, #1
8006a9a: 6878 ldr r0, [r7, #4]
8006a9c: f000 f82f bl 8006afe <USBH_OS_PutMessage>
#endif /* (USBH_USE_OS == 1U) */
return USBH_OK;
8006aa0: 2300 movs r3, #0
}
8006aa2: 4618 mov r0, r3
8006aa4: 3708 adds r7, #8
8006aa6: 46bd mov sp, r7
8006aa8: bd80 pop {r7, pc}
08006aaa <USBH_LL_Disconnect>:
* Handle USB Host disconnection event
* @param phost: Host Handle
* @retval USBH_Status
*/
USBH_StatusTypeDef USBH_LL_Disconnect(USBH_HandleTypeDef *phost)
{
8006aaa: b580 push {r7, lr}
8006aac: b082 sub sp, #8
8006aae: af00 add r7, sp, #0
8006ab0: 6078 str r0, [r7, #4]
/* update device connection states */
phost->device.is_disconnected = 1U;
8006ab2: 687b ldr r3, [r7, #4]
8006ab4: 2201 movs r2, #1
8006ab6: f883 2321 strb.w r2, [r3, #801] @ 0x321
phost->device.is_connected = 0U;
8006aba: 687b ldr r3, [r7, #4]
8006abc: 2200 movs r2, #0
8006abe: f883 2320 strb.w r2, [r3, #800] @ 0x320
phost->device.PortEnabled = 0U;
8006ac2: 687b ldr r3, [r7, #4]
8006ac4: 2200 movs r2, #0
8006ac6: f883 2323 strb.w r2, [r3, #803] @ 0x323
/* Stop Host */
(void)USBH_LL_Stop(phost);
8006aca: 6878 ldr r0, [r7, #4]
8006acc: f001 f998 bl 8007e00 <USBH_LL_Stop>
/* FRee Control Pipes */
(void)USBH_FreePipe(phost, phost->Control.pipe_in);
8006ad0: 687b ldr r3, [r7, #4]
8006ad2: 791b ldrb r3, [r3, #4]
8006ad4: 4619 mov r1, r3
8006ad6: 6878 ldr r0, [r7, #4]
8006ad8: f000 f847 bl 8006b6a <USBH_FreePipe>
(void)USBH_FreePipe(phost, phost->Control.pipe_out);
8006adc: 687b ldr r3, [r7, #4]
8006ade: 795b ldrb r3, [r3, #5]
8006ae0: 4619 mov r1, r3
8006ae2: 6878 ldr r0, [r7, #4]
8006ae4: f000 f841 bl 8006b6a <USBH_FreePipe>
#if (USBH_USE_OS == 1U)
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
8006ae8: 2300 movs r3, #0
8006aea: 2200 movs r2, #0
8006aec: 2101 movs r1, #1
8006aee: 6878 ldr r0, [r7, #4]
8006af0: f000 f805 bl 8006afe <USBH_OS_PutMessage>
#endif /* (USBH_USE_OS == 1U) */
return USBH_OK;
8006af4: 2300 movs r3, #0
}
8006af6: 4618 mov r0, r3
8006af8: 3708 adds r7, #8
8006afa: 46bd mov sp, r7
8006afc: bd80 pop {r7, pc}
08006afe <USBH_OS_PutMessage>:
* @param timeout message event timeout
* @param priority message event priority
* @retval None
*/
void USBH_OS_PutMessage(USBH_HandleTypeDef *phost, USBH_OSEventTypeDef message, uint32_t timeout, uint32_t priority)
{
8006afe: b580 push {r7, lr}
8006b00: b086 sub sp, #24
8006b02: af00 add r7, sp, #0
8006b04: 60f8 str r0, [r7, #12]
8006b06: 607a str r2, [r7, #4]
8006b08: 603b str r3, [r7, #0]
8006b0a: 460b mov r3, r1
8006b0c: 72fb strb r3, [r7, #11]
phost->os_msg = (uint32_t)message;
8006b0e: 7afa ldrb r2, [r7, #11]
8006b10: 68fb ldr r3, [r7, #12]
8006b12: f8c3 23e0 str.w r2, [r3, #992] @ 0x3e0
#if (osCMSIS < 0x20000U)
UNUSED(priority);
/* Calculate the number of available spaces */
uint32_t available_spaces = MSGQUEUE_OBJECTS - osMessageWaiting(phost->os_event);
8006b16: 68fb ldr r3, [r7, #12]
8006b18: f8d3 33d8 ldr.w r3, [r3, #984] @ 0x3d8
8006b1c: 4618 mov r0, r3
8006b1e: f000 f895 bl 8006c4c <osMessageWaiting>
8006b22: 4603 mov r3, r0
8006b24: f1c3 0310 rsb r3, r3, #16
8006b28: 617b str r3, [r7, #20]
if (available_spaces != 0U)
8006b2a: 697b ldr r3, [r7, #20]
8006b2c: 2b00 cmp r3, #0
8006b2e: d009 beq.n 8006b44 <USBH_OS_PutMessage+0x46>
{
(void)osMessagePut(phost->os_event, phost->os_msg, timeout);
8006b30: 68fb ldr r3, [r7, #12]
8006b32: f8d3 03d8 ldr.w r0, [r3, #984] @ 0x3d8
8006b36: 68fb ldr r3, [r7, #12]
8006b38: f8d3 33e0 ldr.w r3, [r3, #992] @ 0x3e0
8006b3c: 687a ldr r2, [r7, #4]
8006b3e: 4619 mov r1, r3
8006b40: f000 f844 bl 8006bcc <osMessagePut>
if (osMessageQueueGetSpace(phost->os_event) != 0U)
{
(void)osMessageQueuePut(phost->os_event, &phost->os_msg, priority, timeout);
}
#endif /* (osCMSIS < 0x20000U) */
}
8006b44: bf00 nop
8006b46: 3718 adds r7, #24
8006b48: 46bd mov sp, r7
8006b4a: bd80 pop {r7, pc}
08006b4c <USBH_LL_NotifyURBChange>:
* Notify URB state Change
* @param phost: Host handle
* @retval USBH Status
*/
USBH_StatusTypeDef USBH_LL_NotifyURBChange(USBH_HandleTypeDef *phost)
{
8006b4c: b580 push {r7, lr}
8006b4e: b082 sub sp, #8
8006b50: af00 add r7, sp, #0
8006b52: 6078 str r0, [r7, #4]
#if (USBH_USE_OS == 1U)
USBH_OS_PutMessage(phost, USBH_PORT_EVENT, 0U, 0U);
8006b54: 2300 movs r3, #0
8006b56: 2200 movs r2, #0
8006b58: 2101 movs r1, #1
8006b5a: 6878 ldr r0, [r7, #4]
8006b5c: f7ff ffcf bl 8006afe <USBH_OS_PutMessage>
#endif /* (USBH_USE_OS == 1U) */
return USBH_OK;
8006b60: 2300 movs r3, #0
}
8006b62: 4618 mov r0, r3
8006b64: 3708 adds r7, #8
8006b66: 46bd mov sp, r7
8006b68: bd80 pop {r7, pc}
08006b6a <USBH_FreePipe>:
* @param phost: Host Handle
* @param idx: Pipe number to be freed
* @retval USBH Status
*/
USBH_StatusTypeDef USBH_FreePipe(USBH_HandleTypeDef *phost, uint8_t idx)
{
8006b6a: b480 push {r7}
8006b6c: b083 sub sp, #12
8006b6e: af00 add r7, sp, #0
8006b70: 6078 str r0, [r7, #4]
8006b72: 460b mov r3, r1
8006b74: 70fb strb r3, [r7, #3]
if (idx < USBH_MAX_PIPES_NBR)
8006b76: 78fb ldrb r3, [r7, #3]
8006b78: 2b0f cmp r3, #15
8006b7a: d80d bhi.n 8006b98 <USBH_FreePipe+0x2e>
{
phost->Pipes[idx] &= 0x7FFFU;
8006b7c: 78fb ldrb r3, [r7, #3]
8006b7e: 687a ldr r2, [r7, #4]
8006b80: 33e0 adds r3, #224 @ 0xe0
8006b82: 009b lsls r3, r3, #2
8006b84: 4413 add r3, r2
8006b86: 685a ldr r2, [r3, #4]
8006b88: 78fb ldrb r3, [r7, #3]
8006b8a: f3c2 020e ubfx r2, r2, #0, #15
8006b8e: 6879 ldr r1, [r7, #4]
8006b90: 33e0 adds r3, #224 @ 0xe0
8006b92: 009b lsls r3, r3, #2
8006b94: 440b add r3, r1
8006b96: 605a str r2, [r3, #4]
}
return USBH_OK;
8006b98: 2300 movs r3, #0
}
8006b9a: 4618 mov r0, r3
8006b9c: 370c adds r7, #12
8006b9e: 46bd mov sp, r7
8006ba0: f85d 7b04 ldr.w r7, [sp], #4
8006ba4: 4770 bx lr
08006ba6 <inHandlerMode>:
#endif
/* Determine whether we are in thread mode or handler mode. */
static int inHandlerMode (void)
{
8006ba6: b480 push {r7}
8006ba8: b083 sub sp, #12
8006baa: af00 add r7, sp, #0
*/
__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8006bac: f3ef 8305 mrs r3, IPSR
8006bb0: 607b str r3, [r7, #4]
return(result);
8006bb2: 687b ldr r3, [r7, #4]
return __get_IPSR() != 0;
8006bb4: 2b00 cmp r3, #0
8006bb6: bf14 ite ne
8006bb8: 2301 movne r3, #1
8006bba: 2300 moveq r3, #0
8006bbc: b2db uxtb r3, r3
}
8006bbe: 4618 mov r0, r3
8006bc0: 370c adds r7, #12
8006bc2: 46bd mov sp, r7
8006bc4: f85d 7b04 ldr.w r7, [sp], #4
8006bc8: 4770 bx lr
...
08006bcc <osMessagePut>:
* @param millisec timeout value or 0 in case of no time-out.
* @retval status code that indicates the execution status of the function.
* @note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
*/
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec)
{
8006bcc: b580 push {r7, lr}
8006bce: b086 sub sp, #24
8006bd0: af00 add r7, sp, #0
8006bd2: 60f8 str r0, [r7, #12]
8006bd4: 60b9 str r1, [r7, #8]
8006bd6: 607a str r2, [r7, #4]
portBASE_TYPE taskWoken = pdFALSE;
8006bd8: 2300 movs r3, #0
8006bda: 613b str r3, [r7, #16]
TickType_t ticks;
ticks = millisec / portTICK_PERIOD_MS;
8006bdc: 687b ldr r3, [r7, #4]
8006bde: 617b str r3, [r7, #20]
if (ticks == 0) {
8006be0: 697b ldr r3, [r7, #20]
8006be2: 2b00 cmp r3, #0
8006be4: d101 bne.n 8006bea <osMessagePut+0x1e>
ticks = 1;
8006be6: 2301 movs r3, #1
8006be8: 617b str r3, [r7, #20]
}
if (inHandlerMode()) {
8006bea: f7ff ffdc bl 8006ba6 <inHandlerMode>
8006bee: 4603 mov r3, r0
8006bf0: 2b00 cmp r3, #0
8006bf2: d018 beq.n 8006c26 <osMessagePut+0x5a>
if (xQueueSendFromISR(queue_id, &info, &taskWoken) != pdTRUE) {
8006bf4: f107 0210 add.w r2, r7, #16
8006bf8: f107 0108 add.w r1, r7, #8
8006bfc: 2300 movs r3, #0
8006bfe: 68f8 ldr r0, [r7, #12]
8006c00: f000 f9c4 bl 8006f8c <xQueueGenericSendFromISR>
8006c04: 4603 mov r3, r0
8006c06: 2b01 cmp r3, #1
8006c08: d001 beq.n 8006c0e <osMessagePut+0x42>
return osErrorOS;
8006c0a: 23ff movs r3, #255 @ 0xff
8006c0c: e018 b.n 8006c40 <osMessagePut+0x74>
}
portEND_SWITCHING_ISR(taskWoken);
8006c0e: 693b ldr r3, [r7, #16]
8006c10: 2b00 cmp r3, #0
8006c12: d014 beq.n 8006c3e <osMessagePut+0x72>
8006c14: 4b0c ldr r3, [pc, #48] @ (8006c48 <osMessagePut+0x7c>)
8006c16: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006c1a: 601a str r2, [r3, #0]
8006c1c: f3bf 8f4f dsb sy
8006c20: f3bf 8f6f isb sy
8006c24: e00b b.n 8006c3e <osMessagePut+0x72>
}
else {
if (xQueueSend(queue_id, &info, ticks) != pdTRUE) {
8006c26: f107 0108 add.w r1, r7, #8
8006c2a: 2300 movs r3, #0
8006c2c: 697a ldr r2, [r7, #20]
8006c2e: 68f8 ldr r0, [r7, #12]
8006c30: f000 f8aa bl 8006d88 <xQueueGenericSend>
8006c34: 4603 mov r3, r0
8006c36: 2b01 cmp r3, #1
8006c38: d001 beq.n 8006c3e <osMessagePut+0x72>
return osErrorOS;
8006c3a: 23ff movs r3, #255 @ 0xff
8006c3c: e000 b.n 8006c40 <osMessagePut+0x74>
}
}
return osOK;
8006c3e: 2300 movs r3, #0
}
8006c40: 4618 mov r0, r3
8006c42: 3718 adds r7, #24
8006c44: 46bd mov sp, r7
8006c46: bd80 pop {r7, pc}
8006c48: e000ed04 .word 0xe000ed04
08006c4c <osMessageWaiting>:
* @brief Get the number of messaged stored in a queue.
* @param queue_id message queue ID obtained with \ref osMessageCreate.
* @retval number of messages stored in a queue.
*/
uint32_t osMessageWaiting(osMessageQId queue_id)
{
8006c4c: b580 push {r7, lr}
8006c4e: b082 sub sp, #8
8006c50: af00 add r7, sp, #0
8006c52: 6078 str r0, [r7, #4]
if (inHandlerMode()) {
8006c54: f7ff ffa7 bl 8006ba6 <inHandlerMode>
8006c58: 4603 mov r3, r0
8006c5a: 2b00 cmp r3, #0
8006c5c: d004 beq.n 8006c68 <osMessageWaiting+0x1c>
return uxQueueMessagesWaitingFromISR(queue_id);
8006c5e: 6878 ldr r0, [r7, #4]
8006c60: f000 fa51 bl 8007106 <uxQueueMessagesWaitingFromISR>
8006c64: 4603 mov r3, r0
8006c66: e003 b.n 8006c70 <osMessageWaiting+0x24>
}
else
{
return uxQueueMessagesWaiting(queue_id);
8006c68: 6878 ldr r0, [r7, #4]
8006c6a: f000 fa2d bl 80070c8 <uxQueueMessagesWaiting>
8006c6e: 4603 mov r3, r0
}
}
8006c70: 4618 mov r0, r3
8006c72: 3708 adds r7, #8
8006c74: 46bd mov sp, r7
8006c76: bd80 pop {r7, pc}
08006c78 <vListInsertEnd>:
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8006c78: b480 push {r7}
8006c7a: b085 sub sp, #20
8006c7c: af00 add r7, sp, #0
8006c7e: 6078 str r0, [r7, #4]
8006c80: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
8006c82: 687b ldr r3, [r7, #4]
8006c84: 685b ldr r3, [r3, #4]
8006c86: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
8006c88: 683b ldr r3, [r7, #0]
8006c8a: 68fa ldr r2, [r7, #12]
8006c8c: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
8006c8e: 68fb ldr r3, [r7, #12]
8006c90: 689a ldr r2, [r3, #8]
8006c92: 683b ldr r3, [r7, #0]
8006c94: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
8006c96: 68fb ldr r3, [r7, #12]
8006c98: 689b ldr r3, [r3, #8]
8006c9a: 683a ldr r2, [r7, #0]
8006c9c: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
8006c9e: 68fb ldr r3, [r7, #12]
8006ca0: 683a ldr r2, [r7, #0]
8006ca2: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
8006ca4: 683b ldr r3, [r7, #0]
8006ca6: 687a ldr r2, [r7, #4]
8006ca8: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8006caa: 687b ldr r3, [r7, #4]
8006cac: 681b ldr r3, [r3, #0]
8006cae: 1c5a adds r2, r3, #1
8006cb0: 687b ldr r3, [r7, #4]
8006cb2: 601a str r2, [r3, #0]
}
8006cb4: bf00 nop
8006cb6: 3714 adds r7, #20
8006cb8: 46bd mov sp, r7
8006cba: f85d 7b04 ldr.w r7, [sp], #4
8006cbe: 4770 bx lr
08006cc0 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8006cc0: b480 push {r7}
8006cc2: b085 sub sp, #20
8006cc4: af00 add r7, sp, #0
8006cc6: 6078 str r0, [r7, #4]
8006cc8: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
8006cca: 683b ldr r3, [r7, #0]
8006ccc: 681b ldr r3, [r3, #0]
8006cce: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
8006cd0: 68bb ldr r3, [r7, #8]
8006cd2: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8006cd6: d103 bne.n 8006ce0 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
8006cd8: 687b ldr r3, [r7, #4]
8006cda: 691b ldr r3, [r3, #16]
8006cdc: 60fb str r3, [r7, #12]
8006cde: e00c b.n 8006cfa <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
8006ce0: 687b ldr r3, [r7, #4]
8006ce2: 3308 adds r3, #8
8006ce4: 60fb str r3, [r7, #12]
8006ce6: e002 b.n 8006cee <vListInsert+0x2e>
8006ce8: 68fb ldr r3, [r7, #12]
8006cea: 685b ldr r3, [r3, #4]
8006cec: 60fb str r3, [r7, #12]
8006cee: 68fb ldr r3, [r7, #12]
8006cf0: 685b ldr r3, [r3, #4]
8006cf2: 681b ldr r3, [r3, #0]
8006cf4: 68ba ldr r2, [r7, #8]
8006cf6: 429a cmp r2, r3
8006cf8: d2f6 bcs.n 8006ce8 <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
8006cfa: 68fb ldr r3, [r7, #12]
8006cfc: 685a ldr r2, [r3, #4]
8006cfe: 683b ldr r3, [r7, #0]
8006d00: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8006d02: 683b ldr r3, [r7, #0]
8006d04: 685b ldr r3, [r3, #4]
8006d06: 683a ldr r2, [r7, #0]
8006d08: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
8006d0a: 683b ldr r3, [r7, #0]
8006d0c: 68fa ldr r2, [r7, #12]
8006d0e: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8006d10: 68fb ldr r3, [r7, #12]
8006d12: 683a ldr r2, [r7, #0]
8006d14: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
8006d16: 683b ldr r3, [r7, #0]
8006d18: 687a ldr r2, [r7, #4]
8006d1a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8006d1c: 687b ldr r3, [r7, #4]
8006d1e: 681b ldr r3, [r3, #0]
8006d20: 1c5a adds r2, r3, #1
8006d22: 687b ldr r3, [r7, #4]
8006d24: 601a str r2, [r3, #0]
}
8006d26: bf00 nop
8006d28: 3714 adds r7, #20
8006d2a: 46bd mov sp, r7
8006d2c: f85d 7b04 ldr.w r7, [sp], #4
8006d30: 4770 bx lr
08006d32 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8006d32: b480 push {r7}
8006d34: b085 sub sp, #20
8006d36: af00 add r7, sp, #0
8006d38: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
8006d3a: 687b ldr r3, [r7, #4]
8006d3c: 691b ldr r3, [r3, #16]
8006d3e: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8006d40: 687b ldr r3, [r7, #4]
8006d42: 685b ldr r3, [r3, #4]
8006d44: 687a ldr r2, [r7, #4]
8006d46: 6892 ldr r2, [r2, #8]
8006d48: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
8006d4a: 687b ldr r3, [r7, #4]
8006d4c: 689b ldr r3, [r3, #8]
8006d4e: 687a ldr r2, [r7, #4]
8006d50: 6852 ldr r2, [r2, #4]
8006d52: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8006d54: 68fb ldr r3, [r7, #12]
8006d56: 685b ldr r3, [r3, #4]
8006d58: 687a ldr r2, [r7, #4]
8006d5a: 429a cmp r2, r3
8006d5c: d103 bne.n 8006d66 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8006d5e: 687b ldr r3, [r7, #4]
8006d60: 689a ldr r2, [r3, #8]
8006d62: 68fb ldr r3, [r7, #12]
8006d64: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8006d66: 687b ldr r3, [r7, #4]
8006d68: 2200 movs r2, #0
8006d6a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
8006d6c: 68fb ldr r3, [r7, #12]
8006d6e: 681b ldr r3, [r3, #0]
8006d70: 1e5a subs r2, r3, #1
8006d72: 68fb ldr r3, [r7, #12]
8006d74: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8006d76: 68fb ldr r3, [r7, #12]
8006d78: 681b ldr r3, [r3, #0]
}
8006d7a: 4618 mov r0, r3
8006d7c: 3714 adds r7, #20
8006d7e: 46bd mov sp, r7
8006d80: f85d 7b04 ldr.w r7, [sp], #4
8006d84: 4770 bx lr
...
08006d88 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
8006d88: b580 push {r7, lr}
8006d8a: b08e sub sp, #56 @ 0x38
8006d8c: af00 add r7, sp, #0
8006d8e: 60f8 str r0, [r7, #12]
8006d90: 60b9 str r1, [r7, #8]
8006d92: 607a str r2, [r7, #4]
8006d94: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
8006d96: 2300 movs r3, #0
8006d98: 637b str r3, [r7, #52] @ 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8006d9a: 68fb ldr r3, [r7, #12]
8006d9c: 633b str r3, [r7, #48] @ 0x30
configASSERT( pxQueue );
8006d9e: 6b3b ldr r3, [r7, #48] @ 0x30
8006da0: 2b00 cmp r3, #0
8006da2: d10b bne.n 8006dbc <xQueueGenericSend+0x34>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
8006da4: f04f 0350 mov.w r3, #80 @ 0x50
8006da8: f383 8811 msr BASEPRI, r3
8006dac: f3bf 8f6f isb sy
8006db0: f3bf 8f4f dsb sy
8006db4: 62bb str r3, [r7, #40] @ 0x28
" msr basepri, %0 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
8006db6: bf00 nop
8006db8: bf00 nop
8006dba: e7fd b.n 8006db8 <xQueueGenericSend+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8006dbc: 68bb ldr r3, [r7, #8]
8006dbe: 2b00 cmp r3, #0
8006dc0: d103 bne.n 8006dca <xQueueGenericSend+0x42>
8006dc2: 6b3b ldr r3, [r7, #48] @ 0x30
8006dc4: 6c1b ldr r3, [r3, #64] @ 0x40
8006dc6: 2b00 cmp r3, #0
8006dc8: d101 bne.n 8006dce <xQueueGenericSend+0x46>
8006dca: 2301 movs r3, #1
8006dcc: e000 b.n 8006dd0 <xQueueGenericSend+0x48>
8006dce: 2300 movs r3, #0
8006dd0: 2b00 cmp r3, #0
8006dd2: d10b bne.n 8006dec <xQueueGenericSend+0x64>
__asm volatile
8006dd4: f04f 0350 mov.w r3, #80 @ 0x50
8006dd8: f383 8811 msr BASEPRI, r3
8006ddc: f3bf 8f6f isb sy
8006de0: f3bf 8f4f dsb sy
8006de4: 627b str r3, [r7, #36] @ 0x24
}
8006de6: bf00 nop
8006de8: bf00 nop
8006dea: e7fd b.n 8006de8 <xQueueGenericSend+0x60>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8006dec: 683b ldr r3, [r7, #0]
8006dee: 2b02 cmp r3, #2
8006df0: d103 bne.n 8006dfa <xQueueGenericSend+0x72>
8006df2: 6b3b ldr r3, [r7, #48] @ 0x30
8006df4: 6bdb ldr r3, [r3, #60] @ 0x3c
8006df6: 2b01 cmp r3, #1
8006df8: d101 bne.n 8006dfe <xQueueGenericSend+0x76>
8006dfa: 2301 movs r3, #1
8006dfc: e000 b.n 8006e00 <xQueueGenericSend+0x78>
8006dfe: 2300 movs r3, #0
8006e00: 2b00 cmp r3, #0
8006e02: d10b bne.n 8006e1c <xQueueGenericSend+0x94>
__asm volatile
8006e04: f04f 0350 mov.w r3, #80 @ 0x50
8006e08: f383 8811 msr BASEPRI, r3
8006e0c: f3bf 8f6f isb sy
8006e10: f3bf 8f4f dsb sy
8006e14: 623b str r3, [r7, #32]
}
8006e16: bf00 nop
8006e18: bf00 nop
8006e1a: e7fd b.n 8006e18 <xQueueGenericSend+0x90>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8006e1c: f000 fd7e bl 800791c <xTaskGetSchedulerState>
8006e20: 4603 mov r3, r0
8006e22: 2b00 cmp r3, #0
8006e24: d102 bne.n 8006e2c <xQueueGenericSend+0xa4>
8006e26: 687b ldr r3, [r7, #4]
8006e28: 2b00 cmp r3, #0
8006e2a: d101 bne.n 8006e30 <xQueueGenericSend+0xa8>
8006e2c: 2301 movs r3, #1
8006e2e: e000 b.n 8006e32 <xQueueGenericSend+0xaa>
8006e30: 2300 movs r3, #0
8006e32: 2b00 cmp r3, #0
8006e34: d10b bne.n 8006e4e <xQueueGenericSend+0xc6>
__asm volatile
8006e36: f04f 0350 mov.w r3, #80 @ 0x50
8006e3a: f383 8811 msr BASEPRI, r3
8006e3e: f3bf 8f6f isb sy
8006e42: f3bf 8f4f dsb sy
8006e46: 61fb str r3, [r7, #28]
}
8006e48: bf00 nop
8006e4a: bf00 nop
8006e4c: e7fd b.n 8006e4a <xQueueGenericSend+0xc2>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8006e4e: f000 fe8b bl 8007b68 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8006e52: 6b3b ldr r3, [r7, #48] @ 0x30
8006e54: 6b9a ldr r2, [r3, #56] @ 0x38
8006e56: 6b3b ldr r3, [r7, #48] @ 0x30
8006e58: 6bdb ldr r3, [r3, #60] @ 0x3c
8006e5a: 429a cmp r2, r3
8006e5c: d302 bcc.n 8006e64 <xQueueGenericSend+0xdc>
8006e5e: 683b ldr r3, [r7, #0]
8006e60: 2b02 cmp r3, #2
8006e62: d129 bne.n 8006eb8 <xQueueGenericSend+0x130>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8006e64: 683a ldr r2, [r7, #0]
8006e66: 68b9 ldr r1, [r7, #8]
8006e68: 6b38 ldr r0, [r7, #48] @ 0x30
8006e6a: f000 f96b bl 8007144 <prvCopyDataToQueue>
8006e6e: 62f8 str r0, [r7, #44] @ 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8006e70: 6b3b ldr r3, [r7, #48] @ 0x30
8006e72: 6a5b ldr r3, [r3, #36] @ 0x24
8006e74: 2b00 cmp r3, #0
8006e76: d010 beq.n 8006e9a <xQueueGenericSend+0x112>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8006e78: 6b3b ldr r3, [r7, #48] @ 0x30
8006e7a: 3324 adds r3, #36 @ 0x24
8006e7c: 4618 mov r0, r3
8006e7e: f000 fc43 bl 8007708 <xTaskRemoveFromEventList>
8006e82: 4603 mov r3, r0
8006e84: 2b00 cmp r3, #0
8006e86: d013 beq.n 8006eb0 <xQueueGenericSend+0x128>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
8006e88: 4b3f ldr r3, [pc, #252] @ (8006f88 <xQueueGenericSend+0x200>)
8006e8a: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006e8e: 601a str r2, [r3, #0]
8006e90: f3bf 8f4f dsb sy
8006e94: f3bf 8f6f isb sy
8006e98: e00a b.n 8006eb0 <xQueueGenericSend+0x128>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
8006e9a: 6afb ldr r3, [r7, #44] @ 0x2c
8006e9c: 2b00 cmp r3, #0
8006e9e: d007 beq.n 8006eb0 <xQueueGenericSend+0x128>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
8006ea0: 4b39 ldr r3, [pc, #228] @ (8006f88 <xQueueGenericSend+0x200>)
8006ea2: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006ea6: 601a str r2, [r3, #0]
8006ea8: f3bf 8f4f dsb sy
8006eac: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
8006eb0: f000 fe8c bl 8007bcc <vPortExitCritical>
return pdPASS;
8006eb4: 2301 movs r3, #1
8006eb6: e063 b.n 8006f80 <xQueueGenericSend+0x1f8>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8006eb8: 687b ldr r3, [r7, #4]
8006eba: 2b00 cmp r3, #0
8006ebc: d103 bne.n 8006ec6 <xQueueGenericSend+0x13e>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
8006ebe: f000 fe85 bl 8007bcc <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8006ec2: 2300 movs r3, #0
8006ec4: e05c b.n 8006f80 <xQueueGenericSend+0x1f8>
}
else if( xEntryTimeSet == pdFALSE )
8006ec6: 6b7b ldr r3, [r7, #52] @ 0x34
8006ec8: 2b00 cmp r3, #0
8006eca: d106 bne.n 8006eda <xQueueGenericSend+0x152>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8006ecc: f107 0314 add.w r3, r7, #20
8006ed0: 4618 mov r0, r3
8006ed2: f000 fc7d bl 80077d0 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8006ed6: 2301 movs r3, #1
8006ed8: 637b str r3, [r7, #52] @ 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8006eda: f000 fe77 bl 8007bcc <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
8006ede: f000 fa05 bl 80072ec <vTaskSuspendAll>
prvLockQueue( pxQueue );
8006ee2: f000 fe41 bl 8007b68 <vPortEnterCritical>
8006ee6: 6b3b ldr r3, [r7, #48] @ 0x30
8006ee8: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8006eec: b25b sxtb r3, r3
8006eee: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8006ef2: d103 bne.n 8006efc <xQueueGenericSend+0x174>
8006ef4: 6b3b ldr r3, [r7, #48] @ 0x30
8006ef6: 2200 movs r2, #0
8006ef8: f883 2044 strb.w r2, [r3, #68] @ 0x44
8006efc: 6b3b ldr r3, [r7, #48] @ 0x30
8006efe: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
8006f02: b25b sxtb r3, r3
8006f04: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8006f08: d103 bne.n 8006f12 <xQueueGenericSend+0x18a>
8006f0a: 6b3b ldr r3, [r7, #48] @ 0x30
8006f0c: 2200 movs r2, #0
8006f0e: f883 2045 strb.w r2, [r3, #69] @ 0x45
8006f12: f000 fe5b bl 8007bcc <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8006f16: 1d3a adds r2, r7, #4
8006f18: f107 0314 add.w r3, r7, #20
8006f1c: 4611 mov r1, r2
8006f1e: 4618 mov r0, r3
8006f20: f000 fc6c bl 80077fc <xTaskCheckForTimeOut>
8006f24: 4603 mov r3, r0
8006f26: 2b00 cmp r3, #0
8006f28: d124 bne.n 8006f74 <xQueueGenericSend+0x1ec>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
8006f2a: 6b38 ldr r0, [r7, #48] @ 0x30
8006f2c: f000 f9c6 bl 80072bc <prvIsQueueFull>
8006f30: 4603 mov r3, r0
8006f32: 2b00 cmp r3, #0
8006f34: d018 beq.n 8006f68 <xQueueGenericSend+0x1e0>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
8006f36: 6b3b ldr r3, [r7, #48] @ 0x30
8006f38: 3310 adds r3, #16
8006f3a: 687a ldr r2, [r7, #4]
8006f3c: 4611 mov r1, r2
8006f3e: 4618 mov r0, r3
8006f40: f000 fbbc bl 80076bc <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
8006f44: 6b38 ldr r0, [r7, #48] @ 0x30
8006f46: f000 f967 bl 8007218 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
8006f4a: f000 f9dd bl 8007308 <xTaskResumeAll>
8006f4e: 4603 mov r3, r0
8006f50: 2b00 cmp r3, #0
8006f52: f47f af7c bne.w 8006e4e <xQueueGenericSend+0xc6>
{
portYIELD_WITHIN_API();
8006f56: 4b0c ldr r3, [pc, #48] @ (8006f88 <xQueueGenericSend+0x200>)
8006f58: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8006f5c: 601a str r2, [r3, #0]
8006f5e: f3bf 8f4f dsb sy
8006f62: f3bf 8f6f isb sy
8006f66: e772 b.n 8006e4e <xQueueGenericSend+0xc6>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
8006f68: 6b38 ldr r0, [r7, #48] @ 0x30
8006f6a: f000 f955 bl 8007218 <prvUnlockQueue>
( void ) xTaskResumeAll();
8006f6e: f000 f9cb bl 8007308 <xTaskResumeAll>
8006f72: e76c b.n 8006e4e <xQueueGenericSend+0xc6>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
8006f74: 6b38 ldr r0, [r7, #48] @ 0x30
8006f76: f000 f94f bl 8007218 <prvUnlockQueue>
( void ) xTaskResumeAll();
8006f7a: f000 f9c5 bl 8007308 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8006f7e: 2300 movs r3, #0
}
} /*lint -restore */
}
8006f80: 4618 mov r0, r3
8006f82: 3738 adds r7, #56 @ 0x38
8006f84: 46bd mov sp, r7
8006f86: bd80 pop {r7, pc}
8006f88: e000ed04 .word 0xe000ed04
08006f8c <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
8006f8c: b580 push {r7, lr}
8006f8e: b090 sub sp, #64 @ 0x40
8006f90: af00 add r7, sp, #0
8006f92: 60f8 str r0, [r7, #12]
8006f94: 60b9 str r1, [r7, #8]
8006f96: 607a str r2, [r7, #4]
8006f98: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
8006f9a: 68fb ldr r3, [r7, #12]
8006f9c: 63bb str r3, [r7, #56] @ 0x38
configASSERT( pxQueue );
8006f9e: 6bbb ldr r3, [r7, #56] @ 0x38
8006fa0: 2b00 cmp r3, #0
8006fa2: d10b bne.n 8006fbc <xQueueGenericSendFromISR+0x30>
__asm volatile
8006fa4: f04f 0350 mov.w r3, #80 @ 0x50
8006fa8: f383 8811 msr BASEPRI, r3
8006fac: f3bf 8f6f isb sy
8006fb0: f3bf 8f4f dsb sy
8006fb4: 62bb str r3, [r7, #40] @ 0x28
}
8006fb6: bf00 nop
8006fb8: bf00 nop
8006fba: e7fd b.n 8006fb8 <xQueueGenericSendFromISR+0x2c>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8006fbc: 68bb ldr r3, [r7, #8]
8006fbe: 2b00 cmp r3, #0
8006fc0: d103 bne.n 8006fca <xQueueGenericSendFromISR+0x3e>
8006fc2: 6bbb ldr r3, [r7, #56] @ 0x38
8006fc4: 6c1b ldr r3, [r3, #64] @ 0x40
8006fc6: 2b00 cmp r3, #0
8006fc8: d101 bne.n 8006fce <xQueueGenericSendFromISR+0x42>
8006fca: 2301 movs r3, #1
8006fcc: e000 b.n 8006fd0 <xQueueGenericSendFromISR+0x44>
8006fce: 2300 movs r3, #0
8006fd0: 2b00 cmp r3, #0
8006fd2: d10b bne.n 8006fec <xQueueGenericSendFromISR+0x60>
__asm volatile
8006fd4: f04f 0350 mov.w r3, #80 @ 0x50
8006fd8: f383 8811 msr BASEPRI, r3
8006fdc: f3bf 8f6f isb sy
8006fe0: f3bf 8f4f dsb sy
8006fe4: 627b str r3, [r7, #36] @ 0x24
}
8006fe6: bf00 nop
8006fe8: bf00 nop
8006fea: e7fd b.n 8006fe8 <xQueueGenericSendFromISR+0x5c>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8006fec: 683b ldr r3, [r7, #0]
8006fee: 2b02 cmp r3, #2
8006ff0: d103 bne.n 8006ffa <xQueueGenericSendFromISR+0x6e>
8006ff2: 6bbb ldr r3, [r7, #56] @ 0x38
8006ff4: 6bdb ldr r3, [r3, #60] @ 0x3c
8006ff6: 2b01 cmp r3, #1
8006ff8: d101 bne.n 8006ffe <xQueueGenericSendFromISR+0x72>
8006ffa: 2301 movs r3, #1
8006ffc: e000 b.n 8007000 <xQueueGenericSendFromISR+0x74>
8006ffe: 2300 movs r3, #0
8007000: 2b00 cmp r3, #0
8007002: d10b bne.n 800701c <xQueueGenericSendFromISR+0x90>
__asm volatile
8007004: f04f 0350 mov.w r3, #80 @ 0x50
8007008: f383 8811 msr BASEPRI, r3
800700c: f3bf 8f6f isb sy
8007010: f3bf 8f4f dsb sy
8007014: 623b str r3, [r7, #32]
}
8007016: bf00 nop
8007018: bf00 nop
800701a: e7fd b.n 8007018 <xQueueGenericSendFromISR+0x8c>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800701c: f000 fe56 bl 8007ccc <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
8007020: f3ef 8211 mrs r2, BASEPRI
8007024: f04f 0350 mov.w r3, #80 @ 0x50
8007028: f383 8811 msr BASEPRI, r3
800702c: f3bf 8f6f isb sy
8007030: f3bf 8f4f dsb sy
8007034: 61fa str r2, [r7, #28]
8007036: 61bb str r3, [r7, #24]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
8007038: 69fb ldr r3, [r7, #28]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
800703a: 637b str r3, [r7, #52] @ 0x34
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
800703c: 6bbb ldr r3, [r7, #56] @ 0x38
800703e: 6b9a ldr r2, [r3, #56] @ 0x38
8007040: 6bbb ldr r3, [r7, #56] @ 0x38
8007042: 6bdb ldr r3, [r3, #60] @ 0x3c
8007044: 429a cmp r2, r3
8007046: d302 bcc.n 800704e <xQueueGenericSendFromISR+0xc2>
8007048: 683b ldr r3, [r7, #0]
800704a: 2b02 cmp r3, #2
800704c: d12f bne.n 80070ae <xQueueGenericSendFromISR+0x122>
{
const int8_t cTxLock = pxQueue->cTxLock;
800704e: 6bbb ldr r3, [r7, #56] @ 0x38
8007050: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
8007054: f887 3033 strb.w r3, [r7, #51] @ 0x33
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
8007058: 6bbb ldr r3, [r7, #56] @ 0x38
800705a: 6b9b ldr r3, [r3, #56] @ 0x38
800705c: 62fb str r3, [r7, #44] @ 0x2c
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
800705e: 683a ldr r2, [r7, #0]
8007060: 68b9 ldr r1, [r7, #8]
8007062: 6bb8 ldr r0, [r7, #56] @ 0x38
8007064: f000 f86e bl 8007144 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
8007068: f997 3033 ldrsb.w r3, [r7, #51] @ 0x33
800706c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8007070: d112 bne.n 8007098 <xQueueGenericSendFromISR+0x10c>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8007072: 6bbb ldr r3, [r7, #56] @ 0x38
8007074: 6a5b ldr r3, [r3, #36] @ 0x24
8007076: 2b00 cmp r3, #0
8007078: d016 beq.n 80070a8 <xQueueGenericSendFromISR+0x11c>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
800707a: 6bbb ldr r3, [r7, #56] @ 0x38
800707c: 3324 adds r3, #36 @ 0x24
800707e: 4618 mov r0, r3
8007080: f000 fb42 bl 8007708 <xTaskRemoveFromEventList>
8007084: 4603 mov r3, r0
8007086: 2b00 cmp r3, #0
8007088: d00e beq.n 80070a8 <xQueueGenericSendFromISR+0x11c>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
800708a: 687b ldr r3, [r7, #4]
800708c: 2b00 cmp r3, #0
800708e: d00b beq.n 80070a8 <xQueueGenericSendFromISR+0x11c>
{
*pxHigherPriorityTaskWoken = pdTRUE;
8007090: 687b ldr r3, [r7, #4]
8007092: 2201 movs r2, #1
8007094: 601a str r2, [r3, #0]
8007096: e007 b.n 80070a8 <xQueueGenericSendFromISR+0x11c>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
8007098: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
800709c: 3301 adds r3, #1
800709e: b2db uxtb r3, r3
80070a0: b25a sxtb r2, r3
80070a2: 6bbb ldr r3, [r7, #56] @ 0x38
80070a4: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
xReturn = pdPASS;
80070a8: 2301 movs r3, #1
80070aa: 63fb str r3, [r7, #60] @ 0x3c
{
80070ac: e001 b.n 80070b2 <xQueueGenericSendFromISR+0x126>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
80070ae: 2300 movs r3, #0
80070b0: 63fb str r3, [r7, #60] @ 0x3c
80070b2: 6b7b ldr r3, [r7, #52] @ 0x34
80070b4: 617b str r3, [r7, #20]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
80070b6: 697b ldr r3, [r7, #20]
80070b8: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
80070bc: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
80070be: 6bfb ldr r3, [r7, #60] @ 0x3c
}
80070c0: 4618 mov r0, r3
80070c2: 3740 adds r7, #64 @ 0x40
80070c4: 46bd mov sp, r7
80070c6: bd80 pop {r7, pc}
080070c8 <uxQueueMessagesWaiting>:
return xReturn;
}
/*-----------------------------------------------------------*/
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
{
80070c8: b580 push {r7, lr}
80070ca: b084 sub sp, #16
80070cc: af00 add r7, sp, #0
80070ce: 6078 str r0, [r7, #4]
UBaseType_t uxReturn;
configASSERT( xQueue );
80070d0: 687b ldr r3, [r7, #4]
80070d2: 2b00 cmp r3, #0
80070d4: d10b bne.n 80070ee <uxQueueMessagesWaiting+0x26>
__asm volatile
80070d6: f04f 0350 mov.w r3, #80 @ 0x50
80070da: f383 8811 msr BASEPRI, r3
80070de: f3bf 8f6f isb sy
80070e2: f3bf 8f4f dsb sy
80070e6: 60bb str r3, [r7, #8]
}
80070e8: bf00 nop
80070ea: bf00 nop
80070ec: e7fd b.n 80070ea <uxQueueMessagesWaiting+0x22>
taskENTER_CRITICAL();
80070ee: f000 fd3b bl 8007b68 <vPortEnterCritical>
{
uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
80070f2: 687b ldr r3, [r7, #4]
80070f4: 6b9b ldr r3, [r3, #56] @ 0x38
80070f6: 60fb str r3, [r7, #12]
}
taskEXIT_CRITICAL();
80070f8: f000 fd68 bl 8007bcc <vPortExitCritical>
return uxReturn;
80070fc: 68fb ldr r3, [r7, #12]
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
80070fe: 4618 mov r0, r3
8007100: 3710 adds r7, #16
8007102: 46bd mov sp, r7
8007104: bd80 pop {r7, pc}
08007106 <uxQueueMessagesWaitingFromISR>:
return uxReturn;
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
/*-----------------------------------------------------------*/
UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
{
8007106: b480 push {r7}
8007108: b087 sub sp, #28
800710a: af00 add r7, sp, #0
800710c: 6078 str r0, [r7, #4]
UBaseType_t uxReturn;
Queue_t * const pxQueue = xQueue;
800710e: 687b ldr r3, [r7, #4]
8007110: 617b str r3, [r7, #20]
configASSERT( pxQueue );
8007112: 697b ldr r3, [r7, #20]
8007114: 2b00 cmp r3, #0
8007116: d10b bne.n 8007130 <uxQueueMessagesWaitingFromISR+0x2a>
__asm volatile
8007118: f04f 0350 mov.w r3, #80 @ 0x50
800711c: f383 8811 msr BASEPRI, r3
8007120: f3bf 8f6f isb sy
8007124: f3bf 8f4f dsb sy
8007128: 60fb str r3, [r7, #12]
}
800712a: bf00 nop
800712c: bf00 nop
800712e: e7fd b.n 800712c <uxQueueMessagesWaitingFromISR+0x26>
uxReturn = pxQueue->uxMessagesWaiting;
8007130: 697b ldr r3, [r7, #20]
8007132: 6b9b ldr r3, [r3, #56] @ 0x38
8007134: 613b str r3, [r7, #16]
return uxReturn;
8007136: 693b ldr r3, [r7, #16]
} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
8007138: 4618 mov r0, r3
800713a: 371c adds r7, #28
800713c: 46bd mov sp, r7
800713e: f85d 7b04 ldr.w r7, [sp], #4
8007142: 4770 bx lr
08007144 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
8007144: b580 push {r7, lr}
8007146: b086 sub sp, #24
8007148: af00 add r7, sp, #0
800714a: 60f8 str r0, [r7, #12]
800714c: 60b9 str r1, [r7, #8]
800714e: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
8007150: 2300 movs r3, #0
8007152: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8007154: 68fb ldr r3, [r7, #12]
8007156: 6b9b ldr r3, [r3, #56] @ 0x38
8007158: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800715a: 68fb ldr r3, [r7, #12]
800715c: 6c1b ldr r3, [r3, #64] @ 0x40
800715e: 2b00 cmp r3, #0
8007160: d10d bne.n 800717e <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
8007162: 68fb ldr r3, [r7, #12]
8007164: 681b ldr r3, [r3, #0]
8007166: 2b00 cmp r3, #0
8007168: d14d bne.n 8007206 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800716a: 68fb ldr r3, [r7, #12]
800716c: 689b ldr r3, [r3, #8]
800716e: 4618 mov r0, r3
8007170: f000 fbf2 bl 8007958 <xTaskPriorityDisinherit>
8007174: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
8007176: 68fb ldr r3, [r7, #12]
8007178: 2200 movs r2, #0
800717a: 609a str r2, [r3, #8]
800717c: e043 b.n 8007206 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
800717e: 687b ldr r3, [r7, #4]
8007180: 2b00 cmp r3, #0
8007182: d119 bne.n 80071b8 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8007184: 68fb ldr r3, [r7, #12]
8007186: 6858 ldr r0, [r3, #4]
8007188: 68fb ldr r3, [r7, #12]
800718a: 6c1b ldr r3, [r3, #64] @ 0x40
800718c: 461a mov r2, r3
800718e: 68b9 ldr r1, [r7, #8]
8007190: f000 feaa bl 8007ee8 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
8007194: 68fb ldr r3, [r7, #12]
8007196: 685a ldr r2, [r3, #4]
8007198: 68fb ldr r3, [r7, #12]
800719a: 6c1b ldr r3, [r3, #64] @ 0x40
800719c: 441a add r2, r3
800719e: 68fb ldr r3, [r7, #12]
80071a0: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
80071a2: 68fb ldr r3, [r7, #12]
80071a4: 685a ldr r2, [r3, #4]
80071a6: 68fb ldr r3, [r7, #12]
80071a8: 689b ldr r3, [r3, #8]
80071aa: 429a cmp r2, r3
80071ac: d32b bcc.n 8007206 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
80071ae: 68fb ldr r3, [r7, #12]
80071b0: 681a ldr r2, [r3, #0]
80071b2: 68fb ldr r3, [r7, #12]
80071b4: 605a str r2, [r3, #4]
80071b6: e026 b.n 8007206 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
80071b8: 68fb ldr r3, [r7, #12]
80071ba: 68d8 ldr r0, [r3, #12]
80071bc: 68fb ldr r3, [r7, #12]
80071be: 6c1b ldr r3, [r3, #64] @ 0x40
80071c0: 461a mov r2, r3
80071c2: 68b9 ldr r1, [r7, #8]
80071c4: f000 fe90 bl 8007ee8 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
80071c8: 68fb ldr r3, [r7, #12]
80071ca: 68da ldr r2, [r3, #12]
80071cc: 68fb ldr r3, [r7, #12]
80071ce: 6c1b ldr r3, [r3, #64] @ 0x40
80071d0: 425b negs r3, r3
80071d2: 441a add r2, r3
80071d4: 68fb ldr r3, [r7, #12]
80071d6: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
80071d8: 68fb ldr r3, [r7, #12]
80071da: 68da ldr r2, [r3, #12]
80071dc: 68fb ldr r3, [r7, #12]
80071de: 681b ldr r3, [r3, #0]
80071e0: 429a cmp r2, r3
80071e2: d207 bcs.n 80071f4 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
80071e4: 68fb ldr r3, [r7, #12]
80071e6: 689a ldr r2, [r3, #8]
80071e8: 68fb ldr r3, [r7, #12]
80071ea: 6c1b ldr r3, [r3, #64] @ 0x40
80071ec: 425b negs r3, r3
80071ee: 441a add r2, r3
80071f0: 68fb ldr r3, [r7, #12]
80071f2: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
80071f4: 687b ldr r3, [r7, #4]
80071f6: 2b02 cmp r3, #2
80071f8: d105 bne.n 8007206 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80071fa: 693b ldr r3, [r7, #16]
80071fc: 2b00 cmp r3, #0
80071fe: d002 beq.n 8007206 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
8007200: 693b ldr r3, [r7, #16]
8007202: 3b01 subs r3, #1
8007204: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
8007206: 693b ldr r3, [r7, #16]
8007208: 1c5a adds r2, r3, #1
800720a: 68fb ldr r3, [r7, #12]
800720c: 639a str r2, [r3, #56] @ 0x38
return xReturn;
800720e: 697b ldr r3, [r7, #20]
}
8007210: 4618 mov r0, r3
8007212: 3718 adds r7, #24
8007214: 46bd mov sp, r7
8007216: bd80 pop {r7, pc}
08007218 <prvUnlockQueue>:
}
}
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
8007218: b580 push {r7, lr}
800721a: b084 sub sp, #16
800721c: af00 add r7, sp, #0
800721e: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
8007220: f000 fca2 bl 8007b68 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
8007224: 687b ldr r3, [r7, #4]
8007226: f893 3045 ldrb.w r3, [r3, #69] @ 0x45
800722a: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
800722c: e011 b.n 8007252 <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800722e: 687b ldr r3, [r7, #4]
8007230: 6a5b ldr r3, [r3, #36] @ 0x24
8007232: 2b00 cmp r3, #0
8007234: d012 beq.n 800725c <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8007236: 687b ldr r3, [r7, #4]
8007238: 3324 adds r3, #36 @ 0x24
800723a: 4618 mov r0, r3
800723c: f000 fa64 bl 8007708 <xTaskRemoveFromEventList>
8007240: 4603 mov r3, r0
8007242: 2b00 cmp r3, #0
8007244: d001 beq.n 800724a <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
8007246: f000 fb3d bl 80078c4 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
800724a: 7bfb ldrb r3, [r7, #15]
800724c: 3b01 subs r3, #1
800724e: b2db uxtb r3, r3
8007250: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
8007252: f997 300f ldrsb.w r3, [r7, #15]
8007256: 2b00 cmp r3, #0
8007258: dce9 bgt.n 800722e <prvUnlockQueue+0x16>
800725a: e000 b.n 800725e <prvUnlockQueue+0x46>
break;
800725c: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800725e: 687b ldr r3, [r7, #4]
8007260: 22ff movs r2, #255 @ 0xff
8007262: f883 2045 strb.w r2, [r3, #69] @ 0x45
}
taskEXIT_CRITICAL();
8007266: f000 fcb1 bl 8007bcc <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
800726a: f000 fc7d bl 8007b68 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800726e: 687b ldr r3, [r7, #4]
8007270: f893 3044 ldrb.w r3, [r3, #68] @ 0x44
8007274: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8007276: e011 b.n 800729c <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8007278: 687b ldr r3, [r7, #4]
800727a: 691b ldr r3, [r3, #16]
800727c: 2b00 cmp r3, #0
800727e: d012 beq.n 80072a6 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8007280: 687b ldr r3, [r7, #4]
8007282: 3310 adds r3, #16
8007284: 4618 mov r0, r3
8007286: f000 fa3f bl 8007708 <xTaskRemoveFromEventList>
800728a: 4603 mov r3, r0
800728c: 2b00 cmp r3, #0
800728e: d001 beq.n 8007294 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
8007290: f000 fb18 bl 80078c4 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
8007294: 7bbb ldrb r3, [r7, #14]
8007296: 3b01 subs r3, #1
8007298: b2db uxtb r3, r3
800729a: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
800729c: f997 300e ldrsb.w r3, [r7, #14]
80072a0: 2b00 cmp r3, #0
80072a2: dce9 bgt.n 8007278 <prvUnlockQueue+0x60>
80072a4: e000 b.n 80072a8 <prvUnlockQueue+0x90>
}
else
{
break;
80072a6: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
80072a8: 687b ldr r3, [r7, #4]
80072aa: 22ff movs r2, #255 @ 0xff
80072ac: f883 2044 strb.w r2, [r3, #68] @ 0x44
}
taskEXIT_CRITICAL();
80072b0: f000 fc8c bl 8007bcc <vPortExitCritical>
}
80072b4: bf00 nop
80072b6: 3710 adds r7, #16
80072b8: 46bd mov sp, r7
80072ba: bd80 pop {r7, pc}
080072bc <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
80072bc: b580 push {r7, lr}
80072be: b084 sub sp, #16
80072c0: af00 add r7, sp, #0
80072c2: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
80072c4: f000 fc50 bl 8007b68 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
80072c8: 687b ldr r3, [r7, #4]
80072ca: 6b9a ldr r2, [r3, #56] @ 0x38
80072cc: 687b ldr r3, [r7, #4]
80072ce: 6bdb ldr r3, [r3, #60] @ 0x3c
80072d0: 429a cmp r2, r3
80072d2: d102 bne.n 80072da <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
80072d4: 2301 movs r3, #1
80072d6: 60fb str r3, [r7, #12]
80072d8: e001 b.n 80072de <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
80072da: 2300 movs r3, #0
80072dc: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
80072de: f000 fc75 bl 8007bcc <vPortExitCritical>
return xReturn;
80072e2: 68fb ldr r3, [r7, #12]
}
80072e4: 4618 mov r0, r3
80072e6: 3710 adds r7, #16
80072e8: 46bd mov sp, r7
80072ea: bd80 pop {r7, pc}
080072ec <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
80072ec: b480 push {r7}
80072ee: af00 add r7, sp, #0
do not otherwise exhibit real time behaviour. */
portSOFTWARE_BARRIER();
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
is used to allow calls to vTaskSuspendAll() to nest. */
++uxSchedulerSuspended;
80072f0: 4b04 ldr r3, [pc, #16] @ (8007304 <vTaskSuspendAll+0x18>)
80072f2: 681b ldr r3, [r3, #0]
80072f4: 3301 adds r3, #1
80072f6: 4a03 ldr r2, [pc, #12] @ (8007304 <vTaskSuspendAll+0x18>)
80072f8: 6013 str r3, [r2, #0]
/* Enforces ordering for ports and optimised compilers that may otherwise place
the above increment elsewhere. */
portMEMORY_BARRIER();
}
80072fa: bf00 nop
80072fc: 46bd mov sp, r7
80072fe: f85d 7b04 ldr.w r7, [sp], #4
8007302: 4770 bx lr
8007304: 200003bc .word 0x200003bc
08007308 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
8007308: b580 push {r7, lr}
800730a: b084 sub sp, #16
800730c: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
800730e: 2300 movs r3, #0
8007310: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
8007312: 2300 movs r3, #0
8007314: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
8007316: 4b42 ldr r3, [pc, #264] @ (8007420 <xTaskResumeAll+0x118>)
8007318: 681b ldr r3, [r3, #0]
800731a: 2b00 cmp r3, #0
800731c: d10b bne.n 8007336 <xTaskResumeAll+0x2e>
__asm volatile
800731e: f04f 0350 mov.w r3, #80 @ 0x50
8007322: f383 8811 msr BASEPRI, r3
8007326: f3bf 8f6f isb sy
800732a: f3bf 8f4f dsb sy
800732e: 603b str r3, [r7, #0]
}
8007330: bf00 nop
8007332: bf00 nop
8007334: e7fd b.n 8007332 <xTaskResumeAll+0x2a>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
8007336: f000 fc17 bl 8007b68 <vPortEnterCritical>
{
--uxSchedulerSuspended;
800733a: 4b39 ldr r3, [pc, #228] @ (8007420 <xTaskResumeAll+0x118>)
800733c: 681b ldr r3, [r3, #0]
800733e: 3b01 subs r3, #1
8007340: 4a37 ldr r2, [pc, #220] @ (8007420 <xTaskResumeAll+0x118>)
8007342: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8007344: 4b36 ldr r3, [pc, #216] @ (8007420 <xTaskResumeAll+0x118>)
8007346: 681b ldr r3, [r3, #0]
8007348: 2b00 cmp r3, #0
800734a: d161 bne.n 8007410 <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
800734c: 4b35 ldr r3, [pc, #212] @ (8007424 <xTaskResumeAll+0x11c>)
800734e: 681b ldr r3, [r3, #0]
8007350: 2b00 cmp r3, #0
8007352: d05d beq.n 8007410 <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8007354: e02e b.n 80073b4 <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8007356: 4b34 ldr r3, [pc, #208] @ (8007428 <xTaskResumeAll+0x120>)
8007358: 68db ldr r3, [r3, #12]
800735a: 68db ldr r3, [r3, #12]
800735c: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
800735e: 68fb ldr r3, [r7, #12]
8007360: 3318 adds r3, #24
8007362: 4618 mov r0, r3
8007364: f7ff fce5 bl 8006d32 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8007368: 68fb ldr r3, [r7, #12]
800736a: 3304 adds r3, #4
800736c: 4618 mov r0, r3
800736e: f7ff fce0 bl 8006d32 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
8007372: 68fb ldr r3, [r7, #12]
8007374: 6adb ldr r3, [r3, #44] @ 0x2c
8007376: 2201 movs r2, #1
8007378: 409a lsls r2, r3
800737a: 4b2c ldr r3, [pc, #176] @ (800742c <xTaskResumeAll+0x124>)
800737c: 681b ldr r3, [r3, #0]
800737e: 4313 orrs r3, r2
8007380: 4a2a ldr r2, [pc, #168] @ (800742c <xTaskResumeAll+0x124>)
8007382: 6013 str r3, [r2, #0]
8007384: 68fb ldr r3, [r7, #12]
8007386: 6ada ldr r2, [r3, #44] @ 0x2c
8007388: 4613 mov r3, r2
800738a: 009b lsls r3, r3, #2
800738c: 4413 add r3, r2
800738e: 009b lsls r3, r3, #2
8007390: 4a27 ldr r2, [pc, #156] @ (8007430 <xTaskResumeAll+0x128>)
8007392: 441a add r2, r3
8007394: 68fb ldr r3, [r7, #12]
8007396: 3304 adds r3, #4
8007398: 4619 mov r1, r3
800739a: 4610 mov r0, r2
800739c: f7ff fc6c bl 8006c78 <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
80073a0: 68fb ldr r3, [r7, #12]
80073a2: 6ada ldr r2, [r3, #44] @ 0x2c
80073a4: 4b23 ldr r3, [pc, #140] @ (8007434 <xTaskResumeAll+0x12c>)
80073a6: 681b ldr r3, [r3, #0]
80073a8: 6adb ldr r3, [r3, #44] @ 0x2c
80073aa: 429a cmp r2, r3
80073ac: d302 bcc.n 80073b4 <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
80073ae: 4b22 ldr r3, [pc, #136] @ (8007438 <xTaskResumeAll+0x130>)
80073b0: 2201 movs r2, #1
80073b2: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
80073b4: 4b1c ldr r3, [pc, #112] @ (8007428 <xTaskResumeAll+0x120>)
80073b6: 681b ldr r3, [r3, #0]
80073b8: 2b00 cmp r3, #0
80073ba: d1cc bne.n 8007356 <xTaskResumeAll+0x4e>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
80073bc: 68fb ldr r3, [r7, #12]
80073be: 2b00 cmp r3, #0
80073c0: d001 beq.n 80073c6 <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
80073c2: f000 fa8b bl 80078dc <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
80073c6: 4b1d ldr r3, [pc, #116] @ (800743c <xTaskResumeAll+0x134>)
80073c8: 681b ldr r3, [r3, #0]
80073ca: 607b str r3, [r7, #4]
if( xPendedCounts > ( TickType_t ) 0U )
80073cc: 687b ldr r3, [r7, #4]
80073ce: 2b00 cmp r3, #0
80073d0: d010 beq.n 80073f4 <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
80073d2: f000 f837 bl 8007444 <xTaskIncrementTick>
80073d6: 4603 mov r3, r0
80073d8: 2b00 cmp r3, #0
80073da: d002 beq.n 80073e2 <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
80073dc: 4b16 ldr r3, [pc, #88] @ (8007438 <xTaskResumeAll+0x130>)
80073de: 2201 movs r2, #1
80073e0: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--xPendedCounts;
80073e2: 687b ldr r3, [r7, #4]
80073e4: 3b01 subs r3, #1
80073e6: 607b str r3, [r7, #4]
} while( xPendedCounts > ( TickType_t ) 0U );
80073e8: 687b ldr r3, [r7, #4]
80073ea: 2b00 cmp r3, #0
80073ec: d1f1 bne.n 80073d2 <xTaskResumeAll+0xca>
xPendedTicks = 0;
80073ee: 4b13 ldr r3, [pc, #76] @ (800743c <xTaskResumeAll+0x134>)
80073f0: 2200 movs r2, #0
80073f2: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
80073f4: 4b10 ldr r3, [pc, #64] @ (8007438 <xTaskResumeAll+0x130>)
80073f6: 681b ldr r3, [r3, #0]
80073f8: 2b00 cmp r3, #0
80073fa: d009 beq.n 8007410 <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
80073fc: 2301 movs r3, #1
80073fe: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8007400: 4b0f ldr r3, [pc, #60] @ (8007440 <xTaskResumeAll+0x138>)
8007402: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8007406: 601a str r2, [r3, #0]
8007408: f3bf 8f4f dsb sy
800740c: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8007410: f000 fbdc bl 8007bcc <vPortExitCritical>
return xAlreadyYielded;
8007414: 68bb ldr r3, [r7, #8]
}
8007416: 4618 mov r0, r3
8007418: 3710 adds r7, #16
800741a: 46bd mov sp, r7
800741c: bd80 pop {r7, pc}
800741e: bf00 nop
8007420: 200003bc .word 0x200003bc
8007424: 2000039c .word 0x2000039c
8007428: 20000374 .word 0x20000374
800742c: 200003a4 .word 0x200003a4
8007430: 200002e0 .word 0x200002e0
8007434: 200002dc .word 0x200002dc
8007438: 200003b0 .word 0x200003b0
800743c: 200003ac .word 0x200003ac
8007440: e000ed04 .word 0xe000ed04
08007444 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
8007444: b580 push {r7, lr}
8007446: b086 sub sp, #24
8007448: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
800744a: 2300 movs r3, #0
800744c: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
800744e: 4b4f ldr r3, [pc, #316] @ (800758c <xTaskIncrementTick+0x148>)
8007450: 681b ldr r3, [r3, #0]
8007452: 2b00 cmp r3, #0
8007454: f040 808f bne.w 8007576 <xTaskIncrementTick+0x132>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
8007458: 4b4d ldr r3, [pc, #308] @ (8007590 <xTaskIncrementTick+0x14c>)
800745a: 681b ldr r3, [r3, #0]
800745c: 3301 adds r3, #1
800745e: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
8007460: 4a4b ldr r2, [pc, #300] @ (8007590 <xTaskIncrementTick+0x14c>)
8007462: 693b ldr r3, [r7, #16]
8007464: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
8007466: 693b ldr r3, [r7, #16]
8007468: 2b00 cmp r3, #0
800746a: d121 bne.n 80074b0 <xTaskIncrementTick+0x6c>
{
taskSWITCH_DELAYED_LISTS();
800746c: 4b49 ldr r3, [pc, #292] @ (8007594 <xTaskIncrementTick+0x150>)
800746e: 681b ldr r3, [r3, #0]
8007470: 681b ldr r3, [r3, #0]
8007472: 2b00 cmp r3, #0
8007474: d00b beq.n 800748e <xTaskIncrementTick+0x4a>
__asm volatile
8007476: f04f 0350 mov.w r3, #80 @ 0x50
800747a: f383 8811 msr BASEPRI, r3
800747e: f3bf 8f6f isb sy
8007482: f3bf 8f4f dsb sy
8007486: 603b str r3, [r7, #0]
}
8007488: bf00 nop
800748a: bf00 nop
800748c: e7fd b.n 800748a <xTaskIncrementTick+0x46>
800748e: 4b41 ldr r3, [pc, #260] @ (8007594 <xTaskIncrementTick+0x150>)
8007490: 681b ldr r3, [r3, #0]
8007492: 60fb str r3, [r7, #12]
8007494: 4b40 ldr r3, [pc, #256] @ (8007598 <xTaskIncrementTick+0x154>)
8007496: 681b ldr r3, [r3, #0]
8007498: 4a3e ldr r2, [pc, #248] @ (8007594 <xTaskIncrementTick+0x150>)
800749a: 6013 str r3, [r2, #0]
800749c: 4a3e ldr r2, [pc, #248] @ (8007598 <xTaskIncrementTick+0x154>)
800749e: 68fb ldr r3, [r7, #12]
80074a0: 6013 str r3, [r2, #0]
80074a2: 4b3e ldr r3, [pc, #248] @ (800759c <xTaskIncrementTick+0x158>)
80074a4: 681b ldr r3, [r3, #0]
80074a6: 3301 adds r3, #1
80074a8: 4a3c ldr r2, [pc, #240] @ (800759c <xTaskIncrementTick+0x158>)
80074aa: 6013 str r3, [r2, #0]
80074ac: f000 fa16 bl 80078dc <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
80074b0: 4b3b ldr r3, [pc, #236] @ (80075a0 <xTaskIncrementTick+0x15c>)
80074b2: 681b ldr r3, [r3, #0]
80074b4: 693a ldr r2, [r7, #16]
80074b6: 429a cmp r2, r3
80074b8: d348 bcc.n 800754c <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
80074ba: 4b36 ldr r3, [pc, #216] @ (8007594 <xTaskIncrementTick+0x150>)
80074bc: 681b ldr r3, [r3, #0]
80074be: 681b ldr r3, [r3, #0]
80074c0: 2b00 cmp r3, #0
80074c2: d104 bne.n 80074ce <xTaskIncrementTick+0x8a>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
80074c4: 4b36 ldr r3, [pc, #216] @ (80075a0 <xTaskIncrementTick+0x15c>)
80074c6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80074ca: 601a str r2, [r3, #0]
break;
80074cc: e03e b.n 800754c <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80074ce: 4b31 ldr r3, [pc, #196] @ (8007594 <xTaskIncrementTick+0x150>)
80074d0: 681b ldr r3, [r3, #0]
80074d2: 68db ldr r3, [r3, #12]
80074d4: 68db ldr r3, [r3, #12]
80074d6: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
80074d8: 68bb ldr r3, [r7, #8]
80074da: 685b ldr r3, [r3, #4]
80074dc: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
80074de: 693a ldr r2, [r7, #16]
80074e0: 687b ldr r3, [r7, #4]
80074e2: 429a cmp r2, r3
80074e4: d203 bcs.n 80074ee <xTaskIncrementTick+0xaa>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
80074e6: 4a2e ldr r2, [pc, #184] @ (80075a0 <xTaskIncrementTick+0x15c>)
80074e8: 687b ldr r3, [r7, #4]
80074ea: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
80074ec: e02e b.n 800754c <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
80074ee: 68bb ldr r3, [r7, #8]
80074f0: 3304 adds r3, #4
80074f2: 4618 mov r0, r3
80074f4: f7ff fc1d bl 8006d32 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
80074f8: 68bb ldr r3, [r7, #8]
80074fa: 6a9b ldr r3, [r3, #40] @ 0x28
80074fc: 2b00 cmp r3, #0
80074fe: d004 beq.n 800750a <xTaskIncrementTick+0xc6>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8007500: 68bb ldr r3, [r7, #8]
8007502: 3318 adds r3, #24
8007504: 4618 mov r0, r3
8007506: f7ff fc14 bl 8006d32 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
800750a: 68bb ldr r3, [r7, #8]
800750c: 6adb ldr r3, [r3, #44] @ 0x2c
800750e: 2201 movs r2, #1
8007510: 409a lsls r2, r3
8007512: 4b24 ldr r3, [pc, #144] @ (80075a4 <xTaskIncrementTick+0x160>)
8007514: 681b ldr r3, [r3, #0]
8007516: 4313 orrs r3, r2
8007518: 4a22 ldr r2, [pc, #136] @ (80075a4 <xTaskIncrementTick+0x160>)
800751a: 6013 str r3, [r2, #0]
800751c: 68bb ldr r3, [r7, #8]
800751e: 6ada ldr r2, [r3, #44] @ 0x2c
8007520: 4613 mov r3, r2
8007522: 009b lsls r3, r3, #2
8007524: 4413 add r3, r2
8007526: 009b lsls r3, r3, #2
8007528: 4a1f ldr r2, [pc, #124] @ (80075a8 <xTaskIncrementTick+0x164>)
800752a: 441a add r2, r3
800752c: 68bb ldr r3, [r7, #8]
800752e: 3304 adds r3, #4
8007530: 4619 mov r1, r3
8007532: 4610 mov r0, r2
8007534: f7ff fba0 bl 8006c78 <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8007538: 68bb ldr r3, [r7, #8]
800753a: 6ada ldr r2, [r3, #44] @ 0x2c
800753c: 4b1b ldr r3, [pc, #108] @ (80075ac <xTaskIncrementTick+0x168>)
800753e: 681b ldr r3, [r3, #0]
8007540: 6adb ldr r3, [r3, #44] @ 0x2c
8007542: 429a cmp r2, r3
8007544: d3b9 bcc.n 80074ba <xTaskIncrementTick+0x76>
{
xSwitchRequired = pdTRUE;
8007546: 2301 movs r3, #1
8007548: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800754a: e7b6 b.n 80074ba <xTaskIncrementTick+0x76>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
800754c: 4b17 ldr r3, [pc, #92] @ (80075ac <xTaskIncrementTick+0x168>)
800754e: 681b ldr r3, [r3, #0]
8007550: 6ada ldr r2, [r3, #44] @ 0x2c
8007552: 4915 ldr r1, [pc, #84] @ (80075a8 <xTaskIncrementTick+0x164>)
8007554: 4613 mov r3, r2
8007556: 009b lsls r3, r3, #2
8007558: 4413 add r3, r2
800755a: 009b lsls r3, r3, #2
800755c: 440b add r3, r1
800755e: 681b ldr r3, [r3, #0]
8007560: 2b01 cmp r3, #1
8007562: d901 bls.n 8007568 <xTaskIncrementTick+0x124>
{
xSwitchRequired = pdTRUE;
8007564: 2301 movs r3, #1
8007566: 617b str r3, [r7, #20]
}
#endif /* configUSE_TICK_HOOK */
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
8007568: 4b11 ldr r3, [pc, #68] @ (80075b0 <xTaskIncrementTick+0x16c>)
800756a: 681b ldr r3, [r3, #0]
800756c: 2b00 cmp r3, #0
800756e: d007 beq.n 8007580 <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
8007570: 2301 movs r3, #1
8007572: 617b str r3, [r7, #20]
8007574: e004 b.n 8007580 <xTaskIncrementTick+0x13c>
}
#endif /* configUSE_PREEMPTION */
}
else
{
++xPendedTicks;
8007576: 4b0f ldr r3, [pc, #60] @ (80075b4 <xTaskIncrementTick+0x170>)
8007578: 681b ldr r3, [r3, #0]
800757a: 3301 adds r3, #1
800757c: 4a0d ldr r2, [pc, #52] @ (80075b4 <xTaskIncrementTick+0x170>)
800757e: 6013 str r3, [r2, #0]
vApplicationTickHook();
}
#endif
}
return xSwitchRequired;
8007580: 697b ldr r3, [r7, #20]
}
8007582: 4618 mov r0, r3
8007584: 3718 adds r7, #24
8007586: 46bd mov sp, r7
8007588: bd80 pop {r7, pc}
800758a: bf00 nop
800758c: 200003bc .word 0x200003bc
8007590: 200003a0 .word 0x200003a0
8007594: 2000036c .word 0x2000036c
8007598: 20000370 .word 0x20000370
800759c: 200003b4 .word 0x200003b4
80075a0: 200003b8 .word 0x200003b8
80075a4: 200003a4 .word 0x200003a4
80075a8: 200002e0 .word 0x200002e0
80075ac: 200002dc .word 0x200002dc
80075b0: 200003b0 .word 0x200003b0
80075b4: 200003ac .word 0x200003ac
080075b8 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
80075b8: b580 push {r7, lr}
80075ba: b088 sub sp, #32
80075bc: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
80075be: 4b3a ldr r3, [pc, #232] @ (80076a8 <vTaskSwitchContext+0xf0>)
80075c0: 681b ldr r3, [r3, #0]
80075c2: 2b00 cmp r3, #0
80075c4: d003 beq.n 80075ce <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
80075c6: 4b39 ldr r3, [pc, #228] @ (80076ac <vTaskSwitchContext+0xf4>)
80075c8: 2201 movs r2, #1
80075ca: 601a str r2, [r3, #0]
for additional information. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
80075cc: e067 b.n 800769e <vTaskSwitchContext+0xe6>
xYieldPending = pdFALSE;
80075ce: 4b37 ldr r3, [pc, #220] @ (80076ac <vTaskSwitchContext+0xf4>)
80075d0: 2200 movs r2, #0
80075d2: 601a str r2, [r3, #0]
taskCHECK_FOR_STACK_OVERFLOW();
80075d4: 4b36 ldr r3, [pc, #216] @ (80076b0 <vTaskSwitchContext+0xf8>)
80075d6: 681b ldr r3, [r3, #0]
80075d8: 6b1b ldr r3, [r3, #48] @ 0x30
80075da: 61fb str r3, [r7, #28]
80075dc: f04f 33a5 mov.w r3, #2779096485 @ 0xa5a5a5a5
80075e0: 61bb str r3, [r7, #24]
80075e2: 69fb ldr r3, [r7, #28]
80075e4: 681b ldr r3, [r3, #0]
80075e6: 69ba ldr r2, [r7, #24]
80075e8: 429a cmp r2, r3
80075ea: d111 bne.n 8007610 <vTaskSwitchContext+0x58>
80075ec: 69fb ldr r3, [r7, #28]
80075ee: 3304 adds r3, #4
80075f0: 681b ldr r3, [r3, #0]
80075f2: 69ba ldr r2, [r7, #24]
80075f4: 429a cmp r2, r3
80075f6: d10b bne.n 8007610 <vTaskSwitchContext+0x58>
80075f8: 69fb ldr r3, [r7, #28]
80075fa: 3308 adds r3, #8
80075fc: 681b ldr r3, [r3, #0]
80075fe: 69ba ldr r2, [r7, #24]
8007600: 429a cmp r2, r3
8007602: d105 bne.n 8007610 <vTaskSwitchContext+0x58>
8007604: 69fb ldr r3, [r7, #28]
8007606: 330c adds r3, #12
8007608: 681b ldr r3, [r3, #0]
800760a: 69ba ldr r2, [r7, #24]
800760c: 429a cmp r2, r3
800760e: d008 beq.n 8007622 <vTaskSwitchContext+0x6a>
8007610: 4b27 ldr r3, [pc, #156] @ (80076b0 <vTaskSwitchContext+0xf8>)
8007612: 681a ldr r2, [r3, #0]
8007614: 4b26 ldr r3, [pc, #152] @ (80076b0 <vTaskSwitchContext+0xf8>)
8007616: 681b ldr r3, [r3, #0]
8007618: 3334 adds r3, #52 @ 0x34
800761a: 4619 mov r1, r3
800761c: 4610 mov r0, r2
800761e: f7f8 ffab bl 8000578 <vApplicationStackOverflowHook>
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8007622: 4b24 ldr r3, [pc, #144] @ (80076b4 <vTaskSwitchContext+0xfc>)
8007624: 681b ldr r3, [r3, #0]
8007626: 60fb str r3, [r7, #12]
__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
8007628: 68fb ldr r3, [r7, #12]
800762a: fab3 f383 clz r3, r3
800762e: 72fb strb r3, [r7, #11]
return ucReturn;
8007630: 7afb ldrb r3, [r7, #11]
8007632: f1c3 031f rsb r3, r3, #31
8007636: 617b str r3, [r7, #20]
8007638: 491f ldr r1, [pc, #124] @ (80076b8 <vTaskSwitchContext+0x100>)
800763a: 697a ldr r2, [r7, #20]
800763c: 4613 mov r3, r2
800763e: 009b lsls r3, r3, #2
8007640: 4413 add r3, r2
8007642: 009b lsls r3, r3, #2
8007644: 440b add r3, r1
8007646: 681b ldr r3, [r3, #0]
8007648: 2b00 cmp r3, #0
800764a: d10b bne.n 8007664 <vTaskSwitchContext+0xac>
__asm volatile
800764c: f04f 0350 mov.w r3, #80 @ 0x50
8007650: f383 8811 msr BASEPRI, r3
8007654: f3bf 8f6f isb sy
8007658: f3bf 8f4f dsb sy
800765c: 607b str r3, [r7, #4]
}
800765e: bf00 nop
8007660: bf00 nop
8007662: e7fd b.n 8007660 <vTaskSwitchContext+0xa8>
8007664: 697a ldr r2, [r7, #20]
8007666: 4613 mov r3, r2
8007668: 009b lsls r3, r3, #2
800766a: 4413 add r3, r2
800766c: 009b lsls r3, r3, #2
800766e: 4a12 ldr r2, [pc, #72] @ (80076b8 <vTaskSwitchContext+0x100>)
8007670: 4413 add r3, r2
8007672: 613b str r3, [r7, #16]
8007674: 693b ldr r3, [r7, #16]
8007676: 685b ldr r3, [r3, #4]
8007678: 685a ldr r2, [r3, #4]
800767a: 693b ldr r3, [r7, #16]
800767c: 605a str r2, [r3, #4]
800767e: 693b ldr r3, [r7, #16]
8007680: 685a ldr r2, [r3, #4]
8007682: 693b ldr r3, [r7, #16]
8007684: 3308 adds r3, #8
8007686: 429a cmp r2, r3
8007688: d104 bne.n 8007694 <vTaskSwitchContext+0xdc>
800768a: 693b ldr r3, [r7, #16]
800768c: 685b ldr r3, [r3, #4]
800768e: 685a ldr r2, [r3, #4]
8007690: 693b ldr r3, [r7, #16]
8007692: 605a str r2, [r3, #4]
8007694: 693b ldr r3, [r7, #16]
8007696: 685b ldr r3, [r3, #4]
8007698: 68db ldr r3, [r3, #12]
800769a: 4a05 ldr r2, [pc, #20] @ (80076b0 <vTaskSwitchContext+0xf8>)
800769c: 6013 str r3, [r2, #0]
}
800769e: bf00 nop
80076a0: 3720 adds r7, #32
80076a2: 46bd mov sp, r7
80076a4: bd80 pop {r7, pc}
80076a6: bf00 nop
80076a8: 200003bc .word 0x200003bc
80076ac: 200003b0 .word 0x200003b0
80076b0: 200002dc .word 0x200002dc
80076b4: 200003a4 .word 0x200003a4
80076b8: 200002e0 .word 0x200002e0
080076bc <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
80076bc: b580 push {r7, lr}
80076be: b084 sub sp, #16
80076c0: af00 add r7, sp, #0
80076c2: 6078 str r0, [r7, #4]
80076c4: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
80076c6: 687b ldr r3, [r7, #4]
80076c8: 2b00 cmp r3, #0
80076ca: d10b bne.n 80076e4 <vTaskPlaceOnEventList+0x28>
__asm volatile
80076cc: f04f 0350 mov.w r3, #80 @ 0x50
80076d0: f383 8811 msr BASEPRI, r3
80076d4: f3bf 8f6f isb sy
80076d8: f3bf 8f4f dsb sy
80076dc: 60fb str r3, [r7, #12]
}
80076de: bf00 nop
80076e0: bf00 nop
80076e2: e7fd b.n 80076e0 <vTaskPlaceOnEventList+0x24>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
80076e4: 4b07 ldr r3, [pc, #28] @ (8007704 <vTaskPlaceOnEventList+0x48>)
80076e6: 681b ldr r3, [r3, #0]
80076e8: 3318 adds r3, #24
80076ea: 4619 mov r1, r3
80076ec: 6878 ldr r0, [r7, #4]
80076ee: f7ff fae7 bl 8006cc0 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
80076f2: 2101 movs r1, #1
80076f4: 6838 ldr r0, [r7, #0]
80076f6: f000 f9b7 bl 8007a68 <prvAddCurrentTaskToDelayedList>
}
80076fa: bf00 nop
80076fc: 3710 adds r7, #16
80076fe: 46bd mov sp, r7
8007700: bd80 pop {r7, pc}
8007702: bf00 nop
8007704: 200002dc .word 0x200002dc
08007708 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
8007708: b580 push {r7, lr}
800770a: b086 sub sp, #24
800770c: af00 add r7, sp, #0
800770e: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8007710: 687b ldr r3, [r7, #4]
8007712: 68db ldr r3, [r3, #12]
8007714: 68db ldr r3, [r3, #12]
8007716: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
8007718: 693b ldr r3, [r7, #16]
800771a: 2b00 cmp r3, #0
800771c: d10b bne.n 8007736 <xTaskRemoveFromEventList+0x2e>
__asm volatile
800771e: f04f 0350 mov.w r3, #80 @ 0x50
8007722: f383 8811 msr BASEPRI, r3
8007726: f3bf 8f6f isb sy
800772a: f3bf 8f4f dsb sy
800772e: 60fb str r3, [r7, #12]
}
8007730: bf00 nop
8007732: bf00 nop
8007734: e7fd b.n 8007732 <xTaskRemoveFromEventList+0x2a>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
8007736: 693b ldr r3, [r7, #16]
8007738: 3318 adds r3, #24
800773a: 4618 mov r0, r3
800773c: f7ff faf9 bl 8006d32 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8007740: 4b1d ldr r3, [pc, #116] @ (80077b8 <xTaskRemoveFromEventList+0xb0>)
8007742: 681b ldr r3, [r3, #0]
8007744: 2b00 cmp r3, #0
8007746: d11c bne.n 8007782 <xTaskRemoveFromEventList+0x7a>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
8007748: 693b ldr r3, [r7, #16]
800774a: 3304 adds r3, #4
800774c: 4618 mov r0, r3
800774e: f7ff faf0 bl 8006d32 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
8007752: 693b ldr r3, [r7, #16]
8007754: 6adb ldr r3, [r3, #44] @ 0x2c
8007756: 2201 movs r2, #1
8007758: 409a lsls r2, r3
800775a: 4b18 ldr r3, [pc, #96] @ (80077bc <xTaskRemoveFromEventList+0xb4>)
800775c: 681b ldr r3, [r3, #0]
800775e: 4313 orrs r3, r2
8007760: 4a16 ldr r2, [pc, #88] @ (80077bc <xTaskRemoveFromEventList+0xb4>)
8007762: 6013 str r3, [r2, #0]
8007764: 693b ldr r3, [r7, #16]
8007766: 6ada ldr r2, [r3, #44] @ 0x2c
8007768: 4613 mov r3, r2
800776a: 009b lsls r3, r3, #2
800776c: 4413 add r3, r2
800776e: 009b lsls r3, r3, #2
8007770: 4a13 ldr r2, [pc, #76] @ (80077c0 <xTaskRemoveFromEventList+0xb8>)
8007772: 441a add r2, r3
8007774: 693b ldr r3, [r7, #16]
8007776: 3304 adds r3, #4
8007778: 4619 mov r1, r3
800777a: 4610 mov r0, r2
800777c: f7ff fa7c bl 8006c78 <vListInsertEnd>
8007780: e005 b.n 800778e <xTaskRemoveFromEventList+0x86>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
8007782: 693b ldr r3, [r7, #16]
8007784: 3318 adds r3, #24
8007786: 4619 mov r1, r3
8007788: 480e ldr r0, [pc, #56] @ (80077c4 <xTaskRemoveFromEventList+0xbc>)
800778a: f7ff fa75 bl 8006c78 <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
800778e: 693b ldr r3, [r7, #16]
8007790: 6ada ldr r2, [r3, #44] @ 0x2c
8007792: 4b0d ldr r3, [pc, #52] @ (80077c8 <xTaskRemoveFromEventList+0xc0>)
8007794: 681b ldr r3, [r3, #0]
8007796: 6adb ldr r3, [r3, #44] @ 0x2c
8007798: 429a cmp r2, r3
800779a: d905 bls.n 80077a8 <xTaskRemoveFromEventList+0xa0>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
800779c: 2301 movs r3, #1
800779e: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
80077a0: 4b0a ldr r3, [pc, #40] @ (80077cc <xTaskRemoveFromEventList+0xc4>)
80077a2: 2201 movs r2, #1
80077a4: 601a str r2, [r3, #0]
80077a6: e001 b.n 80077ac <xTaskRemoveFromEventList+0xa4>
}
else
{
xReturn = pdFALSE;
80077a8: 2300 movs r3, #0
80077aa: 617b str r3, [r7, #20]
}
return xReturn;
80077ac: 697b ldr r3, [r7, #20]
}
80077ae: 4618 mov r0, r3
80077b0: 3718 adds r7, #24
80077b2: 46bd mov sp, r7
80077b4: bd80 pop {r7, pc}
80077b6: bf00 nop
80077b8: 200003bc .word 0x200003bc
80077bc: 200003a4 .word 0x200003a4
80077c0: 200002e0 .word 0x200002e0
80077c4: 20000374 .word 0x20000374
80077c8: 200002dc .word 0x200002dc
80077cc: 200003b0 .word 0x200003b0
080077d0 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
80077d0: b480 push {r7}
80077d2: b083 sub sp, #12
80077d4: af00 add r7, sp, #0
80077d6: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
80077d8: 4b06 ldr r3, [pc, #24] @ (80077f4 <vTaskInternalSetTimeOutState+0x24>)
80077da: 681a ldr r2, [r3, #0]
80077dc: 687b ldr r3, [r7, #4]
80077de: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
80077e0: 4b05 ldr r3, [pc, #20] @ (80077f8 <vTaskInternalSetTimeOutState+0x28>)
80077e2: 681a ldr r2, [r3, #0]
80077e4: 687b ldr r3, [r7, #4]
80077e6: 605a str r2, [r3, #4]
}
80077e8: bf00 nop
80077ea: 370c adds r7, #12
80077ec: 46bd mov sp, r7
80077ee: f85d 7b04 ldr.w r7, [sp], #4
80077f2: 4770 bx lr
80077f4: 200003b4 .word 0x200003b4
80077f8: 200003a0 .word 0x200003a0
080077fc <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
80077fc: b580 push {r7, lr}
80077fe: b088 sub sp, #32
8007800: af00 add r7, sp, #0
8007802: 6078 str r0, [r7, #4]
8007804: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
8007806: 687b ldr r3, [r7, #4]
8007808: 2b00 cmp r3, #0
800780a: d10b bne.n 8007824 <xTaskCheckForTimeOut+0x28>
__asm volatile
800780c: f04f 0350 mov.w r3, #80 @ 0x50
8007810: f383 8811 msr BASEPRI, r3
8007814: f3bf 8f6f isb sy
8007818: f3bf 8f4f dsb sy
800781c: 613b str r3, [r7, #16]
}
800781e: bf00 nop
8007820: bf00 nop
8007822: e7fd b.n 8007820 <xTaskCheckForTimeOut+0x24>
configASSERT( pxTicksToWait );
8007824: 683b ldr r3, [r7, #0]
8007826: 2b00 cmp r3, #0
8007828: d10b bne.n 8007842 <xTaskCheckForTimeOut+0x46>
__asm volatile
800782a: f04f 0350 mov.w r3, #80 @ 0x50
800782e: f383 8811 msr BASEPRI, r3
8007832: f3bf 8f6f isb sy
8007836: f3bf 8f4f dsb sy
800783a: 60fb str r3, [r7, #12]
}
800783c: bf00 nop
800783e: bf00 nop
8007840: e7fd b.n 800783e <xTaskCheckForTimeOut+0x42>
taskENTER_CRITICAL();
8007842: f000 f991 bl 8007b68 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
8007846: 4b1d ldr r3, [pc, #116] @ (80078bc <xTaskCheckForTimeOut+0xc0>)
8007848: 681b ldr r3, [r3, #0]
800784a: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800784c: 687b ldr r3, [r7, #4]
800784e: 685b ldr r3, [r3, #4]
8007850: 69ba ldr r2, [r7, #24]
8007852: 1ad3 subs r3, r2, r3
8007854: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
8007856: 683b ldr r3, [r7, #0]
8007858: 681b ldr r3, [r3, #0]
800785a: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
800785e: d102 bne.n 8007866 <xTaskCheckForTimeOut+0x6a>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
8007860: 2300 movs r3, #0
8007862: 61fb str r3, [r7, #28]
8007864: e023 b.n 80078ae <xTaskCheckForTimeOut+0xb2>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
8007866: 687b ldr r3, [r7, #4]
8007868: 681a ldr r2, [r3, #0]
800786a: 4b15 ldr r3, [pc, #84] @ (80078c0 <xTaskCheckForTimeOut+0xc4>)
800786c: 681b ldr r3, [r3, #0]
800786e: 429a cmp r2, r3
8007870: d007 beq.n 8007882 <xTaskCheckForTimeOut+0x86>
8007872: 687b ldr r3, [r7, #4]
8007874: 685b ldr r3, [r3, #4]
8007876: 69ba ldr r2, [r7, #24]
8007878: 429a cmp r2, r3
800787a: d302 bcc.n 8007882 <xTaskCheckForTimeOut+0x86>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
800787c: 2301 movs r3, #1
800787e: 61fb str r3, [r7, #28]
8007880: e015 b.n 80078ae <xTaskCheckForTimeOut+0xb2>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
8007882: 683b ldr r3, [r7, #0]
8007884: 681b ldr r3, [r3, #0]
8007886: 697a ldr r2, [r7, #20]
8007888: 429a cmp r2, r3
800788a: d20b bcs.n 80078a4 <xTaskCheckForTimeOut+0xa8>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
800788c: 683b ldr r3, [r7, #0]
800788e: 681a ldr r2, [r3, #0]
8007890: 697b ldr r3, [r7, #20]
8007892: 1ad2 subs r2, r2, r3
8007894: 683b ldr r3, [r7, #0]
8007896: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
8007898: 6878 ldr r0, [r7, #4]
800789a: f7ff ff99 bl 80077d0 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
800789e: 2300 movs r3, #0
80078a0: 61fb str r3, [r7, #28]
80078a2: e004 b.n 80078ae <xTaskCheckForTimeOut+0xb2>
}
else
{
*pxTicksToWait = 0;
80078a4: 683b ldr r3, [r7, #0]
80078a6: 2200 movs r2, #0
80078a8: 601a str r2, [r3, #0]
xReturn = pdTRUE;
80078aa: 2301 movs r3, #1
80078ac: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
80078ae: f000 f98d bl 8007bcc <vPortExitCritical>
return xReturn;
80078b2: 69fb ldr r3, [r7, #28]
}
80078b4: 4618 mov r0, r3
80078b6: 3720 adds r7, #32
80078b8: 46bd mov sp, r7
80078ba: bd80 pop {r7, pc}
80078bc: 200003a0 .word 0x200003a0
80078c0: 200003b4 .word 0x200003b4
080078c4 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
80078c4: b480 push {r7}
80078c6: af00 add r7, sp, #0
xYieldPending = pdTRUE;
80078c8: 4b03 ldr r3, [pc, #12] @ (80078d8 <vTaskMissedYield+0x14>)
80078ca: 2201 movs r2, #1
80078cc: 601a str r2, [r3, #0]
}
80078ce: bf00 nop
80078d0: 46bd mov sp, r7
80078d2: f85d 7b04 ldr.w r7, [sp], #4
80078d6: 4770 bx lr
80078d8: 200003b0 .word 0x200003b0
080078dc <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
80078dc: b480 push {r7}
80078de: b083 sub sp, #12
80078e0: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
80078e2: 4b0c ldr r3, [pc, #48] @ (8007914 <prvResetNextTaskUnblockTime+0x38>)
80078e4: 681b ldr r3, [r3, #0]
80078e6: 681b ldr r3, [r3, #0]
80078e8: 2b00 cmp r3, #0
80078ea: d104 bne.n 80078f6 <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
80078ec: 4b0a ldr r3, [pc, #40] @ (8007918 <prvResetNextTaskUnblockTime+0x3c>)
80078ee: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
80078f2: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
80078f4: e008 b.n 8007908 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
80078f6: 4b07 ldr r3, [pc, #28] @ (8007914 <prvResetNextTaskUnblockTime+0x38>)
80078f8: 681b ldr r3, [r3, #0]
80078fa: 68db ldr r3, [r3, #12]
80078fc: 68db ldr r3, [r3, #12]
80078fe: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
8007900: 687b ldr r3, [r7, #4]
8007902: 685b ldr r3, [r3, #4]
8007904: 4a04 ldr r2, [pc, #16] @ (8007918 <prvResetNextTaskUnblockTime+0x3c>)
8007906: 6013 str r3, [r2, #0]
}
8007908: bf00 nop
800790a: 370c adds r7, #12
800790c: 46bd mov sp, r7
800790e: f85d 7b04 ldr.w r7, [sp], #4
8007912: 4770 bx lr
8007914: 2000036c .word 0x2000036c
8007918: 200003b8 .word 0x200003b8
0800791c <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
800791c: b480 push {r7}
800791e: b083 sub sp, #12
8007920: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
8007922: 4b0b ldr r3, [pc, #44] @ (8007950 <xTaskGetSchedulerState+0x34>)
8007924: 681b ldr r3, [r3, #0]
8007926: 2b00 cmp r3, #0
8007928: d102 bne.n 8007930 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800792a: 2301 movs r3, #1
800792c: 607b str r3, [r7, #4]
800792e: e008 b.n 8007942 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8007930: 4b08 ldr r3, [pc, #32] @ (8007954 <xTaskGetSchedulerState+0x38>)
8007932: 681b ldr r3, [r3, #0]
8007934: 2b00 cmp r3, #0
8007936: d102 bne.n 800793e <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
8007938: 2302 movs r3, #2
800793a: 607b str r3, [r7, #4]
800793c: e001 b.n 8007942 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
800793e: 2300 movs r3, #0
8007940: 607b str r3, [r7, #4]
}
}
return xReturn;
8007942: 687b ldr r3, [r7, #4]
}
8007944: 4618 mov r0, r3
8007946: 370c adds r7, #12
8007948: 46bd mov sp, r7
800794a: f85d 7b04 ldr.w r7, [sp], #4
800794e: 4770 bx lr
8007950: 200003a8 .word 0x200003a8
8007954: 200003bc .word 0x200003bc
08007958 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
8007958: b580 push {r7, lr}
800795a: b086 sub sp, #24
800795c: af00 add r7, sp, #0
800795e: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
8007960: 687b ldr r3, [r7, #4]
8007962: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
8007964: 2300 movs r3, #0
8007966: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
8007968: 687b ldr r3, [r7, #4]
800796a: 2b00 cmp r3, #0
800796c: d070 beq.n 8007a50 <xTaskPriorityDisinherit+0xf8>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
800796e: 4b3b ldr r3, [pc, #236] @ (8007a5c <xTaskPriorityDisinherit+0x104>)
8007970: 681b ldr r3, [r3, #0]
8007972: 693a ldr r2, [r7, #16]
8007974: 429a cmp r2, r3
8007976: d00b beq.n 8007990 <xTaskPriorityDisinherit+0x38>
__asm volatile
8007978: f04f 0350 mov.w r3, #80 @ 0x50
800797c: f383 8811 msr BASEPRI, r3
8007980: f3bf 8f6f isb sy
8007984: f3bf 8f4f dsb sy
8007988: 60fb str r3, [r7, #12]
}
800798a: bf00 nop
800798c: bf00 nop
800798e: e7fd b.n 800798c <xTaskPriorityDisinherit+0x34>
configASSERT( pxTCB->uxMutexesHeld );
8007990: 693b ldr r3, [r7, #16]
8007992: 6c9b ldr r3, [r3, #72] @ 0x48
8007994: 2b00 cmp r3, #0
8007996: d10b bne.n 80079b0 <xTaskPriorityDisinherit+0x58>
__asm volatile
8007998: f04f 0350 mov.w r3, #80 @ 0x50
800799c: f383 8811 msr BASEPRI, r3
80079a0: f3bf 8f6f isb sy
80079a4: f3bf 8f4f dsb sy
80079a8: 60bb str r3, [r7, #8]
}
80079aa: bf00 nop
80079ac: bf00 nop
80079ae: e7fd b.n 80079ac <xTaskPriorityDisinherit+0x54>
( pxTCB->uxMutexesHeld )--;
80079b0: 693b ldr r3, [r7, #16]
80079b2: 6c9b ldr r3, [r3, #72] @ 0x48
80079b4: 1e5a subs r2, r3, #1
80079b6: 693b ldr r3, [r7, #16]
80079b8: 649a str r2, [r3, #72] @ 0x48
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
80079ba: 693b ldr r3, [r7, #16]
80079bc: 6ada ldr r2, [r3, #44] @ 0x2c
80079be: 693b ldr r3, [r7, #16]
80079c0: 6c5b ldr r3, [r3, #68] @ 0x44
80079c2: 429a cmp r2, r3
80079c4: d044 beq.n 8007a50 <xTaskPriorityDisinherit+0xf8>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
80079c6: 693b ldr r3, [r7, #16]
80079c8: 6c9b ldr r3, [r3, #72] @ 0x48
80079ca: 2b00 cmp r3, #0
80079cc: d140 bne.n 8007a50 <xTaskPriorityDisinherit+0xf8>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready/delayed list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
80079ce: 693b ldr r3, [r7, #16]
80079d0: 3304 adds r3, #4
80079d2: 4618 mov r0, r3
80079d4: f7ff f9ad bl 8006d32 <uxListRemove>
80079d8: 4603 mov r3, r0
80079da: 2b00 cmp r3, #0
80079dc: d115 bne.n 8007a0a <xTaskPriorityDisinherit+0xb2>
{
taskRESET_READY_PRIORITY( pxTCB->uxPriority );
80079de: 693b ldr r3, [r7, #16]
80079e0: 6ada ldr r2, [r3, #44] @ 0x2c
80079e2: 491f ldr r1, [pc, #124] @ (8007a60 <xTaskPriorityDisinherit+0x108>)
80079e4: 4613 mov r3, r2
80079e6: 009b lsls r3, r3, #2
80079e8: 4413 add r3, r2
80079ea: 009b lsls r3, r3, #2
80079ec: 440b add r3, r1
80079ee: 681b ldr r3, [r3, #0]
80079f0: 2b00 cmp r3, #0
80079f2: d10a bne.n 8007a0a <xTaskPriorityDisinherit+0xb2>
80079f4: 693b ldr r3, [r7, #16]
80079f6: 6adb ldr r3, [r3, #44] @ 0x2c
80079f8: 2201 movs r2, #1
80079fa: fa02 f303 lsl.w r3, r2, r3
80079fe: 43da mvns r2, r3
8007a00: 4b18 ldr r3, [pc, #96] @ (8007a64 <xTaskPriorityDisinherit+0x10c>)
8007a02: 681b ldr r3, [r3, #0]
8007a04: 4013 ands r3, r2
8007a06: 4a17 ldr r2, [pc, #92] @ (8007a64 <xTaskPriorityDisinherit+0x10c>)
8007a08: 6013 str r3, [r2, #0]
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
8007a0a: 693b ldr r3, [r7, #16]
8007a0c: 6c5a ldr r2, [r3, #68] @ 0x44
8007a0e: 693b ldr r3, [r7, #16]
8007a10: 62da str r2, [r3, #44] @ 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8007a12: 693b ldr r3, [r7, #16]
8007a14: 6adb ldr r3, [r3, #44] @ 0x2c
8007a16: f1c3 0207 rsb r2, r3, #7
8007a1a: 693b ldr r3, [r7, #16]
8007a1c: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
8007a1e: 693b ldr r3, [r7, #16]
8007a20: 6adb ldr r3, [r3, #44] @ 0x2c
8007a22: 2201 movs r2, #1
8007a24: 409a lsls r2, r3
8007a26: 4b0f ldr r3, [pc, #60] @ (8007a64 <xTaskPriorityDisinherit+0x10c>)
8007a28: 681b ldr r3, [r3, #0]
8007a2a: 4313 orrs r3, r2
8007a2c: 4a0d ldr r2, [pc, #52] @ (8007a64 <xTaskPriorityDisinherit+0x10c>)
8007a2e: 6013 str r3, [r2, #0]
8007a30: 693b ldr r3, [r7, #16]
8007a32: 6ada ldr r2, [r3, #44] @ 0x2c
8007a34: 4613 mov r3, r2
8007a36: 009b lsls r3, r3, #2
8007a38: 4413 add r3, r2
8007a3a: 009b lsls r3, r3, #2
8007a3c: 4a08 ldr r2, [pc, #32] @ (8007a60 <xTaskPriorityDisinherit+0x108>)
8007a3e: 441a add r2, r3
8007a40: 693b ldr r3, [r7, #16]
8007a42: 3304 adds r3, #4
8007a44: 4619 mov r1, r3
8007a46: 4610 mov r0, r2
8007a48: f7ff f916 bl 8006c78 <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
8007a4c: 2301 movs r3, #1
8007a4e: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8007a50: 697b ldr r3, [r7, #20]
}
8007a52: 4618 mov r0, r3
8007a54: 3718 adds r7, #24
8007a56: 46bd mov sp, r7
8007a58: bd80 pop {r7, pc}
8007a5a: bf00 nop
8007a5c: 200002dc .word 0x200002dc
8007a60: 200002e0 .word 0x200002e0
8007a64: 200003a4 .word 0x200003a4
08007a68 <prvAddCurrentTaskToDelayedList>:
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
8007a68: b580 push {r7, lr}
8007a6a: b084 sub sp, #16
8007a6c: af00 add r7, sp, #0
8007a6e: 6078 str r0, [r7, #4]
8007a70: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
8007a72: 4b29 ldr r3, [pc, #164] @ (8007b18 <prvAddCurrentTaskToDelayedList+0xb0>)
8007a74: 681b ldr r3, [r3, #0]
8007a76: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8007a78: 4b28 ldr r3, [pc, #160] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007a7a: 681b ldr r3, [r3, #0]
8007a7c: 3304 adds r3, #4
8007a7e: 4618 mov r0, r3
8007a80: f7ff f957 bl 8006d32 <uxListRemove>
8007a84: 4603 mov r3, r0
8007a86: 2b00 cmp r3, #0
8007a88: d10b bne.n 8007aa2 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* The current task must be in a ready list, so there is no need to
check, and the port reset macro can be called directly. */
portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
8007a8a: 4b24 ldr r3, [pc, #144] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007a8c: 681b ldr r3, [r3, #0]
8007a8e: 6adb ldr r3, [r3, #44] @ 0x2c
8007a90: 2201 movs r2, #1
8007a92: fa02 f303 lsl.w r3, r2, r3
8007a96: 43da mvns r2, r3
8007a98: 4b21 ldr r3, [pc, #132] @ (8007b20 <prvAddCurrentTaskToDelayedList+0xb8>)
8007a9a: 681b ldr r3, [r3, #0]
8007a9c: 4013 ands r3, r2
8007a9e: 4a20 ldr r2, [pc, #128] @ (8007b20 <prvAddCurrentTaskToDelayedList+0xb8>)
8007aa0: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
8007aa2: 687b ldr r3, [r7, #4]
8007aa4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
8007aa8: d10a bne.n 8007ac0 <prvAddCurrentTaskToDelayedList+0x58>
8007aaa: 683b ldr r3, [r7, #0]
8007aac: 2b00 cmp r3, #0
8007aae: d007 beq.n 8007ac0 <prvAddCurrentTaskToDelayedList+0x58>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
8007ab0: 4b1a ldr r3, [pc, #104] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007ab2: 681b ldr r3, [r3, #0]
8007ab4: 3304 adds r3, #4
8007ab6: 4619 mov r1, r3
8007ab8: 481a ldr r0, [pc, #104] @ (8007b24 <prvAddCurrentTaskToDelayedList+0xbc>)
8007aba: f7ff f8dd bl 8006c78 <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
8007abe: e026 b.n 8007b0e <prvAddCurrentTaskToDelayedList+0xa6>
xTimeToWake = xConstTickCount + xTicksToWait;
8007ac0: 68fa ldr r2, [r7, #12]
8007ac2: 687b ldr r3, [r7, #4]
8007ac4: 4413 add r3, r2
8007ac6: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
8007ac8: 4b14 ldr r3, [pc, #80] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007aca: 681b ldr r3, [r3, #0]
8007acc: 68ba ldr r2, [r7, #8]
8007ace: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
8007ad0: 68ba ldr r2, [r7, #8]
8007ad2: 68fb ldr r3, [r7, #12]
8007ad4: 429a cmp r2, r3
8007ad6: d209 bcs.n 8007aec <prvAddCurrentTaskToDelayedList+0x84>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
8007ad8: 4b13 ldr r3, [pc, #76] @ (8007b28 <prvAddCurrentTaskToDelayedList+0xc0>)
8007ada: 681a ldr r2, [r3, #0]
8007adc: 4b0f ldr r3, [pc, #60] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007ade: 681b ldr r3, [r3, #0]
8007ae0: 3304 adds r3, #4
8007ae2: 4619 mov r1, r3
8007ae4: 4610 mov r0, r2
8007ae6: f7ff f8eb bl 8006cc0 <vListInsert>
}
8007aea: e010 b.n 8007b0e <prvAddCurrentTaskToDelayedList+0xa6>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
8007aec: 4b0f ldr r3, [pc, #60] @ (8007b2c <prvAddCurrentTaskToDelayedList+0xc4>)
8007aee: 681a ldr r2, [r3, #0]
8007af0: 4b0a ldr r3, [pc, #40] @ (8007b1c <prvAddCurrentTaskToDelayedList+0xb4>)
8007af2: 681b ldr r3, [r3, #0]
8007af4: 3304 adds r3, #4
8007af6: 4619 mov r1, r3
8007af8: 4610 mov r0, r2
8007afa: f7ff f8e1 bl 8006cc0 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
8007afe: 4b0c ldr r3, [pc, #48] @ (8007b30 <prvAddCurrentTaskToDelayedList+0xc8>)
8007b00: 681b ldr r3, [r3, #0]
8007b02: 68ba ldr r2, [r7, #8]
8007b04: 429a cmp r2, r3
8007b06: d202 bcs.n 8007b0e <prvAddCurrentTaskToDelayedList+0xa6>
xNextTaskUnblockTime = xTimeToWake;
8007b08: 4a09 ldr r2, [pc, #36] @ (8007b30 <prvAddCurrentTaskToDelayedList+0xc8>)
8007b0a: 68bb ldr r3, [r7, #8]
8007b0c: 6013 str r3, [r2, #0]
}
8007b0e: bf00 nop
8007b10: 3710 adds r7, #16
8007b12: 46bd mov sp, r7
8007b14: bd80 pop {r7, pc}
8007b16: bf00 nop
8007b18: 200003a0 .word 0x200003a0
8007b1c: 200002dc .word 0x200002dc
8007b20: 200003a4 .word 0x200003a4
8007b24: 20000388 .word 0x20000388
8007b28: 20000370 .word 0x20000370
8007b2c: 2000036c .word 0x2000036c
8007b30: 200003b8 .word 0x200003b8
...
08007b40 <SVC_Handler>:
}
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8007b40: 4b07 ldr r3, [pc, #28] @ (8007b60 <pxCurrentTCBConst2>)
8007b42: 6819 ldr r1, [r3, #0]
8007b44: 6808 ldr r0, [r1, #0]
8007b46: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8007b4a: f380 8809 msr PSP, r0
8007b4e: f3bf 8f6f isb sy
8007b52: f04f 0000 mov.w r0, #0
8007b56: f380 8811 msr BASEPRI, r0
8007b5a: 4770 bx lr
8007b5c: f3af 8000 nop.w
08007b60 <pxCurrentTCBConst2>:
8007b60: 200002dc .word 0x200002dc
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8007b64: bf00 nop
8007b66: bf00 nop
08007b68 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
8007b68: b480 push {r7}
8007b6a: b083 sub sp, #12
8007b6c: af00 add r7, sp, #0
__asm volatile
8007b6e: f04f 0350 mov.w r3, #80 @ 0x50
8007b72: f383 8811 msr BASEPRI, r3
8007b76: f3bf 8f6f isb sy
8007b7a: f3bf 8f4f dsb sy
8007b7e: 607b str r3, [r7, #4]
}
8007b80: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
8007b82: 4b10 ldr r3, [pc, #64] @ (8007bc4 <vPortEnterCritical+0x5c>)
8007b84: 681b ldr r3, [r3, #0]
8007b86: 3301 adds r3, #1
8007b88: 4a0e ldr r2, [pc, #56] @ (8007bc4 <vPortEnterCritical+0x5c>)
8007b8a: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
8007b8c: 4b0d ldr r3, [pc, #52] @ (8007bc4 <vPortEnterCritical+0x5c>)
8007b8e: 681b ldr r3, [r3, #0]
8007b90: 2b01 cmp r3, #1
8007b92: d110 bne.n 8007bb6 <vPortEnterCritical+0x4e>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
8007b94: 4b0c ldr r3, [pc, #48] @ (8007bc8 <vPortEnterCritical+0x60>)
8007b96: 681b ldr r3, [r3, #0]
8007b98: b2db uxtb r3, r3
8007b9a: 2b00 cmp r3, #0
8007b9c: d00b beq.n 8007bb6 <vPortEnterCritical+0x4e>
__asm volatile
8007b9e: f04f 0350 mov.w r3, #80 @ 0x50
8007ba2: f383 8811 msr BASEPRI, r3
8007ba6: f3bf 8f6f isb sy
8007baa: f3bf 8f4f dsb sy
8007bae: 603b str r3, [r7, #0]
}
8007bb0: bf00 nop
8007bb2: bf00 nop
8007bb4: e7fd b.n 8007bb2 <vPortEnterCritical+0x4a>
}
}
8007bb6: bf00 nop
8007bb8: 370c adds r7, #12
8007bba: 46bd mov sp, r7
8007bbc: f85d 7b04 ldr.w r7, [sp], #4
8007bc0: 4770 bx lr
8007bc2: bf00 nop
8007bc4: 2000000c .word 0x2000000c
8007bc8: e000ed04 .word 0xe000ed04
08007bcc <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8007bcc: b480 push {r7}
8007bce: b083 sub sp, #12
8007bd0: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
8007bd2: 4b12 ldr r3, [pc, #72] @ (8007c1c <vPortExitCritical+0x50>)
8007bd4: 681b ldr r3, [r3, #0]
8007bd6: 2b00 cmp r3, #0
8007bd8: d10b bne.n 8007bf2 <vPortExitCritical+0x26>
__asm volatile
8007bda: f04f 0350 mov.w r3, #80 @ 0x50
8007bde: f383 8811 msr BASEPRI, r3
8007be2: f3bf 8f6f isb sy
8007be6: f3bf 8f4f dsb sy
8007bea: 607b str r3, [r7, #4]
}
8007bec: bf00 nop
8007bee: bf00 nop
8007bf0: e7fd b.n 8007bee <vPortExitCritical+0x22>
uxCriticalNesting--;
8007bf2: 4b0a ldr r3, [pc, #40] @ (8007c1c <vPortExitCritical+0x50>)
8007bf4: 681b ldr r3, [r3, #0]
8007bf6: 3b01 subs r3, #1
8007bf8: 4a08 ldr r2, [pc, #32] @ (8007c1c <vPortExitCritical+0x50>)
8007bfa: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
8007bfc: 4b07 ldr r3, [pc, #28] @ (8007c1c <vPortExitCritical+0x50>)
8007bfe: 681b ldr r3, [r3, #0]
8007c00: 2b00 cmp r3, #0
8007c02: d105 bne.n 8007c10 <vPortExitCritical+0x44>
8007c04: 2300 movs r3, #0
8007c06: 603b str r3, [r7, #0]
__asm volatile
8007c08: 683b ldr r3, [r7, #0]
8007c0a: f383 8811 msr BASEPRI, r3
}
8007c0e: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
8007c10: bf00 nop
8007c12: 370c adds r7, #12
8007c14: 46bd mov sp, r7
8007c16: f85d 7b04 ldr.w r7, [sp], #4
8007c1a: 4770 bx lr
8007c1c: 2000000c .word 0x2000000c
08007c20 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
8007c20: f3ef 8009 mrs r0, PSP
8007c24: f3bf 8f6f isb sy
8007c28: 4b15 ldr r3, [pc, #84] @ (8007c80 <pxCurrentTCBConst>)
8007c2a: 681a ldr r2, [r3, #0]
8007c2c: f01e 0f10 tst.w lr, #16
8007c30: bf08 it eq
8007c32: ed20 8a10 vstmdbeq r0!, {s16-s31}
8007c36: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8007c3a: 6010 str r0, [r2, #0]
8007c3c: e92d 0009 stmdb sp!, {r0, r3}
8007c40: f04f 0050 mov.w r0, #80 @ 0x50
8007c44: f380 8811 msr BASEPRI, r0
8007c48: f3bf 8f4f dsb sy
8007c4c: f3bf 8f6f isb sy
8007c50: f7ff fcb2 bl 80075b8 <vTaskSwitchContext>
8007c54: f04f 0000 mov.w r0, #0
8007c58: f380 8811 msr BASEPRI, r0
8007c5c: bc09 pop {r0, r3}
8007c5e: 6819 ldr r1, [r3, #0]
8007c60: 6808 ldr r0, [r1, #0]
8007c62: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8007c66: f01e 0f10 tst.w lr, #16
8007c6a: bf08 it eq
8007c6c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
8007c70: f380 8809 msr PSP, r0
8007c74: f3bf 8f6f isb sy
8007c78: 4770 bx lr
8007c7a: bf00 nop
8007c7c: f3af 8000 nop.w
08007c80 <pxCurrentTCBConst>:
8007c80: 200002dc .word 0x200002dc
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
8007c84: bf00 nop
8007c86: bf00 nop
08007c88 <SysTick_Handler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
8007c88: b580 push {r7, lr}
8007c8a: b082 sub sp, #8
8007c8c: af00 add r7, sp, #0
__asm volatile
8007c8e: f04f 0350 mov.w r3, #80 @ 0x50
8007c92: f383 8811 msr BASEPRI, r3
8007c96: f3bf 8f6f isb sy
8007c9a: f3bf 8f4f dsb sy
8007c9e: 607b str r3, [r7, #4]
}
8007ca0: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8007ca2: f7ff fbcf bl 8007444 <xTaskIncrementTick>
8007ca6: 4603 mov r3, r0
8007ca8: 2b00 cmp r3, #0
8007caa: d003 beq.n 8007cb4 <SysTick_Handler+0x2c>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
8007cac: 4b06 ldr r3, [pc, #24] @ (8007cc8 <SysTick_Handler+0x40>)
8007cae: f04f 5280 mov.w r2, #268435456 @ 0x10000000
8007cb2: 601a str r2, [r3, #0]
8007cb4: 2300 movs r3, #0
8007cb6: 603b str r3, [r7, #0]
__asm volatile
8007cb8: 683b ldr r3, [r7, #0]
8007cba: f383 8811 msr BASEPRI, r3
}
8007cbe: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8007cc0: bf00 nop
8007cc2: 3708 adds r7, #8
8007cc4: 46bd mov sp, r7
8007cc6: bd80 pop {r7, pc}
8007cc8: e000ed04 .word 0xe000ed04
08007ccc <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
8007ccc: b480 push {r7}
8007cce: b085 sub sp, #20
8007cd0: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
8007cd2: f3ef 8305 mrs r3, IPSR
8007cd6: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
8007cd8: 68fb ldr r3, [r7, #12]
8007cda: 2b0f cmp r3, #15
8007cdc: d915 bls.n 8007d0a <vPortValidateInterruptPriority+0x3e>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
8007cde: 4a18 ldr r2, [pc, #96] @ (8007d40 <vPortValidateInterruptPriority+0x74>)
8007ce0: 68fb ldr r3, [r7, #12]
8007ce2: 4413 add r3, r2
8007ce4: 781b ldrb r3, [r3, #0]
8007ce6: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
8007ce8: 4b16 ldr r3, [pc, #88] @ (8007d44 <vPortValidateInterruptPriority+0x78>)
8007cea: 781b ldrb r3, [r3, #0]
8007cec: 7afa ldrb r2, [r7, #11]
8007cee: 429a cmp r2, r3
8007cf0: d20b bcs.n 8007d0a <vPortValidateInterruptPriority+0x3e>
__asm volatile
8007cf2: f04f 0350 mov.w r3, #80 @ 0x50
8007cf6: f383 8811 msr BASEPRI, r3
8007cfa: f3bf 8f6f isb sy
8007cfe: f3bf 8f4f dsb sy
8007d02: 607b str r3, [r7, #4]
}
8007d04: bf00 nop
8007d06: bf00 nop
8007d08: e7fd b.n 8007d06 <vPortValidateInterruptPriority+0x3a>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
8007d0a: 4b0f ldr r3, [pc, #60] @ (8007d48 <vPortValidateInterruptPriority+0x7c>)
8007d0c: 681b ldr r3, [r3, #0]
8007d0e: f403 62e0 and.w r2, r3, #1792 @ 0x700
8007d12: 4b0e ldr r3, [pc, #56] @ (8007d4c <vPortValidateInterruptPriority+0x80>)
8007d14: 681b ldr r3, [r3, #0]
8007d16: 429a cmp r2, r3
8007d18: d90b bls.n 8007d32 <vPortValidateInterruptPriority+0x66>
__asm volatile
8007d1a: f04f 0350 mov.w r3, #80 @ 0x50
8007d1e: f383 8811 msr BASEPRI, r3
8007d22: f3bf 8f6f isb sy
8007d26: f3bf 8f4f dsb sy
8007d2a: 603b str r3, [r7, #0]
}
8007d2c: bf00 nop
8007d2e: bf00 nop
8007d30: e7fd b.n 8007d2e <vPortValidateInterruptPriority+0x62>
}
8007d32: bf00 nop
8007d34: 3714 adds r7, #20
8007d36: 46bd mov sp, r7
8007d38: f85d 7b04 ldr.w r7, [sp], #4
8007d3c: 4770 bx lr
8007d3e: bf00 nop
8007d40: e000e3f0 .word 0xe000e3f0
8007d44: 200003c0 .word 0x200003c0
8007d48: e000ed0c .word 0xe000ed0c
8007d4c: 200003c4 .word 0x200003c4
08007d50 <HAL_HCD_SOF_Callback>:
* @brief SOF callback.
* @param hhcd: HCD handle
* @retval None
*/
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
8007d50: b580 push {r7, lr}
8007d52: b082 sub sp, #8
8007d54: af00 add r7, sp, #0
8007d56: 6078 str r0, [r7, #4]
USBH_LL_IncTimer(hhcd->pData);
8007d58: 687b ldr r3, [r7, #4]
8007d5a: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007d5e: 4618 mov r0, r3
8007d60: f7fe fe3a bl 80069d8 <USBH_LL_IncTimer>
}
8007d64: bf00 nop
8007d66: 3708 adds r7, #8
8007d68: 46bd mov sp, r7
8007d6a: bd80 pop {r7, pc}
08007d6c <HAL_HCD_Connect_Callback>:
* @brief SOF callback.
* @param hhcd: HCD handle
* @retval None
*/
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
8007d6c: b580 push {r7, lr}
8007d6e: b082 sub sp, #8
8007d70: af00 add r7, sp, #0
8007d72: 6078 str r0, [r7, #4]
USBH_LL_Connect(hhcd->pData);
8007d74: 687b ldr r3, [r7, #4]
8007d76: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007d7a: 4618 mov r0, r3
8007d7c: f7fe fe7a bl 8006a74 <USBH_LL_Connect>
}
8007d80: bf00 nop
8007d82: 3708 adds r7, #8
8007d84: 46bd mov sp, r7
8007d86: bd80 pop {r7, pc}
08007d88 <HAL_HCD_Disconnect_Callback>:
* @brief SOF callback.
* @param hhcd: HCD handle
* @retval None
*/
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
8007d88: b580 push {r7, lr}
8007d8a: b082 sub sp, #8
8007d8c: af00 add r7, sp, #0
8007d8e: 6078 str r0, [r7, #4]
USBH_LL_Disconnect(hhcd->pData);
8007d90: 687b ldr r3, [r7, #4]
8007d92: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007d96: 4618 mov r0, r3
8007d98: f7fe fe87 bl 8006aaa <USBH_LL_Disconnect>
}
8007d9c: bf00 nop
8007d9e: 3708 adds r7, #8
8007da0: 46bd mov sp, r7
8007da2: bd80 pop {r7, pc}
08007da4 <HAL_HCD_HC_NotifyURBChange_Callback>:
* @param chnum: channel number
* @param urb_state: state
* @retval None
*/
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
8007da4: b580 push {r7, lr}
8007da6: b082 sub sp, #8
8007da8: af00 add r7, sp, #0
8007daa: 6078 str r0, [r7, #4]
8007dac: 460b mov r3, r1
8007dae: 70fb strb r3, [r7, #3]
8007db0: 4613 mov r3, r2
8007db2: 70bb strb r3, [r7, #2]
/* To be used with OS to sync URB state with the global state machine */
#if (USBH_USE_OS == 1)
USBH_LL_NotifyURBChange(hhcd->pData);
8007db4: 687b ldr r3, [r7, #4]
8007db6: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007dba: 4618 mov r0, r3
8007dbc: f7fe fec6 bl 8006b4c <USBH_LL_NotifyURBChange>
#endif
}
8007dc0: bf00 nop
8007dc2: 3708 adds r7, #8
8007dc4: 46bd mov sp, r7
8007dc6: bd80 pop {r7, pc}
08007dc8 <HAL_HCD_PortEnabled_Callback>:
* @brief Port Port Enabled callback.
* @param hhcd: HCD handle
* @retval None
*/
void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
{
8007dc8: b580 push {r7, lr}
8007dca: b082 sub sp, #8
8007dcc: af00 add r7, sp, #0
8007dce: 6078 str r0, [r7, #4]
USBH_LL_PortEnabled(hhcd->pData);
8007dd0: 687b ldr r3, [r7, #4]
8007dd2: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007dd6: 4618 mov r0, r3
8007dd8: f7fe fe28 bl 8006a2c <USBH_LL_PortEnabled>
}
8007ddc: bf00 nop
8007dde: 3708 adds r7, #8
8007de0: 46bd mov sp, r7
8007de2: bd80 pop {r7, pc}
08007de4 <HAL_HCD_PortDisabled_Callback>:
* @brief Port Port Disabled callback.
* @param hhcd: HCD handle
* @retval None
*/
void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
{
8007de4: b580 push {r7, lr}
8007de6: b082 sub sp, #8
8007de8: af00 add r7, sp, #0
8007dea: 6078 str r0, [r7, #4]
USBH_LL_PortDisabled(hhcd->pData);
8007dec: 687b ldr r3, [r7, #4]
8007dee: f8d3 33dc ldr.w r3, [r3, #988] @ 0x3dc
8007df2: 4618 mov r0, r3
8007df4: f7fe fe2c bl 8006a50 <USBH_LL_PortDisabled>
}
8007df8: bf00 nop
8007dfa: 3708 adds r7, #8
8007dfc: 46bd mov sp, r7
8007dfe: bd80 pop {r7, pc}
08007e00 <USBH_LL_Stop>:
* @brief Stop the low level portion of the host driver.
* @param phost: Host handle
* @retval USBH status
*/
USBH_StatusTypeDef USBH_LL_Stop(USBH_HandleTypeDef *phost)
{
8007e00: b580 push {r7, lr}
8007e02: b084 sub sp, #16
8007e04: af00 add r7, sp, #0
8007e06: 6078 str r0, [r7, #4]
HAL_StatusTypeDef hal_status = HAL_OK;
8007e08: 2300 movs r3, #0
8007e0a: 73fb strb r3, [r7, #15]
USBH_StatusTypeDef usb_status = USBH_OK;
8007e0c: 2300 movs r3, #0
8007e0e: 73bb strb r3, [r7, #14]
hal_status = HAL_HCD_Stop(phost->pData);
8007e10: 687b ldr r3, [r7, #4]
8007e12: f8d3 33d0 ldr.w r3, [r3, #976] @ 0x3d0
8007e16: 4618 mov r0, r3
8007e18: f7fa fa1b bl 8002252 <HAL_HCD_Stop>
8007e1c: 4603 mov r3, r0
8007e1e: 73fb strb r3, [r7, #15]
usb_status = USBH_Get_USB_Status(hal_status);
8007e20: 7bfb ldrb r3, [r7, #15]
8007e22: 4618 mov r0, r3
8007e24: f000 f808 bl 8007e38 <USBH_Get_USB_Status>
8007e28: 4603 mov r3, r0
8007e2a: 73bb strb r3, [r7, #14]
return usb_status;
8007e2c: 7bbb ldrb r3, [r7, #14]
}
8007e2e: 4618 mov r0, r3
8007e30: 3710 adds r7, #16
8007e32: 46bd mov sp, r7
8007e34: bd80 pop {r7, pc}
...
08007e38 <USBH_Get_USB_Status>:
* @brief Returns the USB status depending on the HAL status:
* @param hal_status: HAL status
* @retval USB status
*/
USBH_StatusTypeDef USBH_Get_USB_Status(HAL_StatusTypeDef hal_status)
{
8007e38: b480 push {r7}
8007e3a: b085 sub sp, #20
8007e3c: af00 add r7, sp, #0
8007e3e: 4603 mov r3, r0
8007e40: 71fb strb r3, [r7, #7]
USBH_StatusTypeDef usb_status = USBH_OK;
8007e42: 2300 movs r3, #0
8007e44: 73fb strb r3, [r7, #15]
switch (hal_status)
8007e46: 79fb ldrb r3, [r7, #7]
8007e48: 2b03 cmp r3, #3
8007e4a: d817 bhi.n 8007e7c <USBH_Get_USB_Status+0x44>
8007e4c: a201 add r2, pc, #4 @ (adr r2, 8007e54 <USBH_Get_USB_Status+0x1c>)
8007e4e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007e52: bf00 nop
8007e54: 08007e65 .word 0x08007e65
8007e58: 08007e6b .word 0x08007e6b
8007e5c: 08007e71 .word 0x08007e71
8007e60: 08007e77 .word 0x08007e77
{
case HAL_OK :
usb_status = USBH_OK;
8007e64: 2300 movs r3, #0
8007e66: 73fb strb r3, [r7, #15]
break;
8007e68: e00b b.n 8007e82 <USBH_Get_USB_Status+0x4a>
case HAL_ERROR :
usb_status = USBH_FAIL;
8007e6a: 2302 movs r3, #2
8007e6c: 73fb strb r3, [r7, #15]
break;
8007e6e: e008 b.n 8007e82 <USBH_Get_USB_Status+0x4a>
case HAL_BUSY :
usb_status = USBH_BUSY;
8007e70: 2301 movs r3, #1
8007e72: 73fb strb r3, [r7, #15]
break;
8007e74: e005 b.n 8007e82 <USBH_Get_USB_Status+0x4a>
case HAL_TIMEOUT :
usb_status = USBH_FAIL;
8007e76: 2302 movs r3, #2
8007e78: 73fb strb r3, [r7, #15]
break;
8007e7a: e002 b.n 8007e82 <USBH_Get_USB_Status+0x4a>
default :
usb_status = USBH_FAIL;
8007e7c: 2302 movs r3, #2
8007e7e: 73fb strb r3, [r7, #15]
break;
8007e80: bf00 nop
}
return usb_status;
8007e82: 7bfb ldrb r3, [r7, #15]
}
8007e84: 4618 mov r0, r3
8007e86: 3714 adds r7, #20
8007e88: 46bd mov sp, r7
8007e8a: f85d 7b04 ldr.w r7, [sp], #4
8007e8e: 4770 bx lr
08007e90 <memset>:
8007e90: 4402 add r2, r0
8007e92: 4603 mov r3, r0
8007e94: 4293 cmp r3, r2
8007e96: d100 bne.n 8007e9a <memset+0xa>
8007e98: 4770 bx lr
8007e9a: f803 1b01 strb.w r1, [r3], #1
8007e9e: e7f9 b.n 8007e94 <memset+0x4>
08007ea0 <__libc_init_array>:
8007ea0: b570 push {r4, r5, r6, lr}
8007ea2: 4d0d ldr r5, [pc, #52] @ (8007ed8 <__libc_init_array+0x38>)
8007ea4: 4c0d ldr r4, [pc, #52] @ (8007edc <__libc_init_array+0x3c>)
8007ea6: 1b64 subs r4, r4, r5
8007ea8: 10a4 asrs r4, r4, #2
8007eaa: 2600 movs r6, #0
8007eac: 42a6 cmp r6, r4
8007eae: d109 bne.n 8007ec4 <__libc_init_array+0x24>
8007eb0: 4d0b ldr r5, [pc, #44] @ (8007ee0 <__libc_init_array+0x40>)
8007eb2: 4c0c ldr r4, [pc, #48] @ (8007ee4 <__libc_init_array+0x44>)
8007eb4: f000 f826 bl 8007f04 <_init>
8007eb8: 1b64 subs r4, r4, r5
8007eba: 10a4 asrs r4, r4, #2
8007ebc: 2600 movs r6, #0
8007ebe: 42a6 cmp r6, r4
8007ec0: d105 bne.n 8007ece <__libc_init_array+0x2e>
8007ec2: bd70 pop {r4, r5, r6, pc}
8007ec4: f855 3b04 ldr.w r3, [r5], #4
8007ec8: 4798 blx r3
8007eca: 3601 adds r6, #1
8007ecc: e7ee b.n 8007eac <__libc_init_array+0xc>
8007ece: f855 3b04 ldr.w r3, [r5], #4
8007ed2: 4798 blx r3
8007ed4: 3601 adds r6, #1
8007ed6: e7f2 b.n 8007ebe <__libc_init_array+0x1e>
8007ed8: 08007f3c .word 0x08007f3c
8007edc: 08007f3c .word 0x08007f3c
8007ee0: 08007f3c .word 0x08007f3c
8007ee4: 08007f40 .word 0x08007f40
08007ee8 <memcpy>:
8007ee8: 440a add r2, r1
8007eea: 4291 cmp r1, r2
8007eec: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
8007ef0: d100 bne.n 8007ef4 <memcpy+0xc>
8007ef2: 4770 bx lr
8007ef4: b510 push {r4, lr}
8007ef6: f811 4b01 ldrb.w r4, [r1], #1
8007efa: f803 4f01 strb.w r4, [r3, #1]!
8007efe: 4291 cmp r1, r2
8007f00: d1f9 bne.n 8007ef6 <memcpy+0xe>
8007f02: bd10 pop {r4, pc}
08007f04 <_init>:
8007f04: b5f8 push {r3, r4, r5, r6, r7, lr}
8007f06: bf00 nop
8007f08: bcf8 pop {r3, r4, r5, r6, r7}
8007f0a: bc08 pop {r3}
8007f0c: 469e mov lr, r3
8007f0e: 4770 bx lr
08007f10 <_fini>:
8007f10: b5f8 push {r3, r4, r5, r6, r7, lr}
8007f12: bf00 nop
8007f14: bcf8 pop {r3, r4, r5, r6, r7}
8007f16: bc08 pop {r3}
8007f18: 469e mov lr, r3
8007f1a: 4770 bx lr
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